Yamaha YMF724F User's Manual
Contents
1. YMF724F V Se N H un El E Se de Ao E de de Se Hao fey fu Ox rons MX OSM Fu QHH NaaavHnods e BHB AOH ZHE NNHO XNN NODAAHRANNNHNAHNHNOALAHHN a CUtAatOmMmHoPOOSOMADHHNH AHAHAHAS HNMHNNHKAHDOOVUOYN VDVVVUMHHAZHAAHAGHS XX SSAHHHOOULUOUOUUHZEZEZ A GP4 J XRST GP5 2 ACSH GP 6 3 ACDO GP7 4 ACDI RXD 5 ASCLK TXD 6 ASDO ROMDO VOLDW 7 ABCLK ROMSK VOLUP 8 ALRCK VDD5 9 VSS VDD3 0 VSS VSS 1 VDD3 VSS 2 VDD5 IRQ5 3 PVDD IRQ7 4 NC IRQ9 5 PCREQ IRO10 6 PCGNT IRO11 7 SERIROdw INTA 8 ADO VSS 9 AD1 RST PVSS VDD5 AD2 PVSS AD3 PCICLK AD4 PVDD PVSS GNT AD5 REO AD6 AD31 AD7 AD30 PVSS AD29 PVDD PVSS CBEO AD28 AD8 AD27 AD9 AD26 PVSS PVSS AD10 AD25 AD11 AD24 AD12 GUB AAA REL S Qoa E Uo ana EEEPREEEREEPREEEEEFPEEEEEEETTEFEEEEEE A Qi 0 3 eG KG e Ds n n n KG eG r D a SEE E m nu R n n nu o H o HH gt U Oo i Ed a 144 Pin LQFP Top View September 21 1998 YME724F VAMARA PIN DESCRIPTION 1 PCI Bus Interface 53 pin racak Jif e poc o SR daif ere ree 05 appro fio Pr Address Data Emus De om sms o ean to Pr Paty FRAMES IO Pur Pam RDY fio Pur __ titiator Ready reve ro Pe _ Target Ready stoe fio Pur Iso msee 1 P Psia pbvsEL to Pur Deiceseer 33 reos o PO JjmlRqes 5 5 0 0 ONT Jije room S Pereo2. O Pr POPCIRegus 33 PCPA Grant pecon 1 Pr erect Grant perreo IO par Parity Error serre O Pod SytemBmor o untar o Pod _ imterrupt signal output for pct bus serro ro Pr seriaizeano 2 YMF730 AC 2 Interface 6 pin E O LT oma Romsimaliman CMCLK Master Clock of AC link 24 576MHz and AC3F2 ax 1 T ACHmkBitClckforAC2audiodaa cspo ol T sma ACI AC seriat audio output data eso at T ACHmkAC2Senaawioipudaa esye o r sma ACHmkSynhronzedsgna September 21 1998 YMF724F MANIA 3 YMF727 AC3F2 Interface 9 pin xmsT o C ama Resetforlocaldevice ac lol T sma chipsetectforacsr2 ASCLK o T 6mA _ Clock for Serial control data transfer of AC3F2_ acoo o T sma seriat controtdata ouputof ACIF2 acor Ja mp Serial control data inputot ac3F2 ALRCK o T sma LR clock for Serial audio data of ACIFZ LABCLK O r sma Bitclock for Serial audio data ot AC3F2 po o T sma Seriataudio data outputto AC3E2_ kin a E 4 SPDIF Interface 1 pin name T O type Size function DIT O T 3mA Digital audio interface output 48kHz 5 Legacy Device Interface 16 pin Ttr 12mA Interrupt5 of Legacy Audio It is directly connected to the interrupt signal of System I O chip mor Jo Tr I2mA tnterrupe7 of Legacy Audio IRQ9 o Tr 12
3. September 21 1998 35 YMF724F VALA A Eth nin D Read Write Default 00h b7 b6 b5 b4 b3 b2 bi b 7 0 SCAN DATA This is the data port for reading and writing the internal state F8h Interrupt Flag Register Read Only Default 00h b7 b6 b5 b4 b3 b2 bt bo GEARS E ge ERE b0 SBI SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt This bit is read only Thus read the SB DSP read port to clearing the interrupt and this bit Then the value of the read port is invalid September 21 1998 36 YME724F VEIA 2 3 MPU401 This block is for transmitting and receiving MIDI data It is compatible with UART mode of MPU401 Full duplex operation is possible using the 16 byte FIFO for each direction transmitting and receiving The following shows the MPUBase I O map for MPU401 MPUBase R W MIDI Data port MPUBase lh R Status Register port MPUBase lh W Command Register port Command ba Oi E ES se rose 2 4 Joystick JSBase R W pot m be os om ps pm p o JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX JACX Joystick A Coordinate X JACY Joystick A Coordinate Y JBCX Joystick B Coordinate X JBCY Joystick B Coordinate Y JABI Joystick A Button 1 JAB2 Joystick A Button 2 JBB1 Joystick B Button 1 JBB2 Joystick B Button 2 September 21 1998 37 YMF724F
4. are hardwired to OOb n EA Extended Address DS 1 does not support extended address mode This bit is hardwired to Ob b 15 4 Base Address D DMA Slave Base Address These bits indicate the D DMA slave base address 50h Capability ID Read Only Default 01h Access Bus Width 8 16 32 bit b7 bs bs bs ba ba b bo Capability ID b 7 0 ei vans Capability ID Capability Identifier This register indicates that the new capability register is for Power Management control This register is hardwired to 01h September 21 1998 24 YMF724F YAMAHA ai td 51h Next Item Pointer Read Only Default 00h Access Bus Width 8 16 32 bit b7 be b5 b4 b3 ba bi bo Next Item Pointer E Next Item Pointer DS 1 does not provide other new capability besides Power Management This register is hardwired to 00h 2 53h Power Man m Read Only Default 0401h Access Bus Width 8 16 32 bit CC E O E A n iliti D2S DIS Version b 2 0 Version These bits contain the revision number of the Power Management Interface Specification They are hardwired to 001b Dm D1S D1 Support This bit indicates whether DS 1 support D1 of the power state Only when EEPROM connects When EEPROM does not connect externally use ACPI mode 58 59h ACPI Mode Register ACPI bit to support D1 state The default value is 0 externally this bit can be set
5. eu us September 21 1998 29 YMF724F VISITER 2 1 2 OPL3 Data Register OPL3 Data Register Array 0 R W Das os 9 x T T T9 T 00 01h LSI TEST TIMER 1 TIMER 2 LSI TEST SE mane 0 Lm E SO CINC COI we et Le RR em ww 3332 wm mo To RO sa a J m os uno coc om La EEE E SS RS ER The registers marked with exist but do not function September 21 1998 30 YMF724F VEDA 2 2 Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro Only playback functions are supported record functions are not supported However to maintain compatibility for games it is designed so that every DSP command receives a correct response The DMA transfer of this block uses PC PCI or D DMA protocol The following shows the SBBase I O map of SB Pro SBBase R OPL3 Status port SBBase W OPL3 Address port for Register Array O SBBase 1h R W OPL3 Data register SBBase 2h W OPL3 Address port for Register Array 1 SBBase 3h R W OPL3 Data port SBBase 4h W SB Mixer Address port SBBase 5h R W SB Mixer Data port SBBase 6h W SB DSP Reset port SBBase 8h R OPL3 Status port SBBase 8h W OPL3 Address port for Register Array O SBBase 9h R W OPL3 Data port SBBase Ah R DSP Read Data port SBBase Ch R DSP Write buffer status port SBBase Ch W DSP Write Command Data port SBBase Eh R DSP Read buffer status port Sep
6. 16 32 bit 57 be b5 b ba ba bi bo TEN Revision ID This register contains the revision number of DS 1 This register is hardwired to 03h 09h Programming Interface Read Only Default 00h Access Bus Width 8 16 32 bit b7 b6 bs b4 ba b2 bi bo Programming Interface n Programming Interface This register indicates the programming interface of DS 1 This register is hardwired to 00h OAh Sub class Code Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 bs ba ba ba b bo Sub class Code b 7 0 Sub class Code This register indicates the sub class of DS 1 This register is hardwired to 01h DS 1 belongs to the Audio Sub class OBh Base Class Code Read Only Default 04h Access Bus Width 8 16 32 bit b7 b6 bs bs ba ba b bo Base Class Code b 7 0 Base Class Code This register indicates the base class of DS 1 This register is hardwired to 04h Multimedia Base Class DS 1 belongs to the September 21 1998 13 YMF724F MANIA ODh Latency Timer Read Write Default 00h Access Bus Width 8 16 32 bit b7 b b5 b4 ba ba bi bo b 7 0 Latency Timer When DS 1 becomes a Bus Master device this register indicates the initial value of the Master Latency Timer OEh Header Type Read Only Default 00h Access Bus Width 8 16 32 bit b7 b6 bs b4 b
7. 3 V C 250 pF Applicable to all PCI Iuput Output pins and Iunput pins except PCICLK and RST pin 2 Applicable to RST pin Applicable to CBCLK CSDI ACDI ASDI GP 7 4 RXD VOLUP VOLDW ROMDI and TEST 7 0 pins Applicable to XI24 pin Applicable to AD 31 0 C BE 3 0 PAR REQ PCREQ SERIRQ TXD ALRCK ASDO ACDO ACS ROMSK ROMDO ROMCS and DIT pins Applicable to FRAME IRDY TRDY STOP DEVSEL PERR SERR ABCLK ASCLK CRST CSYNC and CSDO pins Applicable to IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 and INTA pins Applicable to CMCLK XRST and XO24 pins 0 DS 1 Power Control Register DUC DPLLO DPLL1 PSN PSLO PSL1 1 PCICLK 33MHz is stopped September 21 1998 43 sram YMF724F TURA 4 AC Characteristics 4 1 Master Clock Fig 1 XD4CydeTime Inc 4060 m 16 124 m XD4lowTime tow 16 24 m Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0 3 V XD4 tXIHIGH tXILOW tyicye Fig 1 XI24 Master Clock timing 4 2 Reset Fig 2 Reset Active Time after Power Stable t 1 m Power Stable to Reset Rising Edge tysro 10 ms ReeSlwRae so vin Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0 3 V C 250 pF LC aasy PVDD VDD5 VDD3 t RSTOFF RST Fig 2 PCI Reset tim
8. Corporation hold jointly O Se nsaura Sensaura logo is a trademark of Central Research Laboratories Limited 1 GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements and MIDI functions 2 XG XG is a format about MIDI synthesizer that is proposed by YAMAHA and keeps the upper compatibility of GM system level 1 The good points are the voice arrangements kept extensively a large number of the voices modification of the voices 3 kinds of effects and so on 3 SONDIUS XG Products bearing the SONDIUS XG logo are licensed under patents of Stanford University and YAMAHA Corporation as listed on lt http www sondius xg com gt The SONDIUS XG produces acoustic sound outputs by running a virtual simulation of the actual acoustic instrument operation Therefore it provides much more real world acoustic sound outputs fundamentally different from the Wavetable sound generator that simply processes the recorded acoustic sound sources only The SONDIUS XG adds the technology of virtual acoustic sound to the XG format 4 Sensaura Sensaura is a technology which provides 3D positional audio and moving effect by HRTF Head Related Transfer Function with 2 speakers or headphone This feature makes it possible to enjoy invariable and unchangeable sound feelings in all positional area covering as wide as 360 degrees September 21 1998 2 YMF724F AMARA PIN CONFIGURATION
9. channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ Only one protocol can be used at once SIEN IMOD Interrupt protocol 0 0 Legacy interrupt IRQs default 0 1 PCI interrupt INTA 1 Serialized IRQ y AAA LAD Legacy Audio Disable This bit disables the Legacy Audio block 0 Enables the Legacy Audio block 1 Disables the Legacy Audio block default When this bit is set to 1 DS 1 does not respond to the I O Target transaction for legacy I O address on the PCI bus September 21 1998 18 ES YMF724F VAMARA 42 43h Exten L Audi ntrol Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bis b12 bi bio bo b8 b7 b bs b4 ba b2 bi bO mop sever SMOD MAM JSIO MPUIO SBIO FMIO b 1 0 FMIO FM I O Address allocation These bits determine the base I O address for the of the OPL3 block FMBase OPL3 block uses 4 bytes in the I O address space 0 388h default pri 398h us 3A0h RI 3A8h b 3 2 SBIO SB I O Address allocation These bits determine the base I O address for the Sound Blaster Pro block SBBase This block uses 16 bytes in the I O address space o 220h default up 240h b 260h 37 280h b 5 4 MPUIO MPU I O Address allocation These bits determine the base I O address for the MPU401 block MPUBase This block uses 2 bytes in t
10. is 1 this register indicates 00h September 21 1998 15 YMF724F MAMA h Interr Lin Read Write Default 00h Access Bus Width 8 16 32 bit b7 b b5 b4 b3 b2 bi bo b 7 0 Interrupt Line This register indicates the interrupt channel that INTA is assigned to 3Dh Interrupt Pin Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 b5 ba ba ba bi bo b 7 0 Interrupt Pin DS 1 supports INTA only This register is hardwired to 01h Eh Minimum Gran Read Only Default 05h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 b0 Minimum Grant b 7 0 Minimum Grant This register indicates the length of the burst period required by DS 1 This register is hardwired to 05h 3Fh Maximum Latency Read Only Default 19h Access Bus Width 8 16 32 bit b7 b b5 b4 b8 ba bi bo b 7 0 Maximum Latency This register indicates how often DS 1 generates the Bus Master Request This register is hardwired to 19h September 21 1998 16 YME724F VARA ai td 40 41h L A Read Write Default 907Fh Access Bus Width 8 16 32 bit b15 bia bis b12 bi bio bo b8 b7 b bs b4 ba b2 bi bo i ntrol bO SBEN Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I O space spec
11. single cycle DMA mode digitized sound output with ref byte 8bit to 4bit ADPCM auto init DMA mode digitized sound output with ref byte 8bit to 3bit ADPCM auto init DMA mode digitized sound output with ref byte Pause DAC for a duration 8bit high speed auto init DMA mode digitized sound output 8bit high speed single cycle DMA mode digitized sound output 8bit high speed auto init DMA mode digitized sound input 8bit high speed single cycle DMA mode digitized sound input Set input mode to mono Set input mode to stereo Pause 8bit DMA mode digitized sound I O Turn on speaker Turn off speaker Continue 8bit DMA mode digitized sound I O Get speaker status Exit 8bit auto init DMA mode digitized sound I O Get DSP version number 1 The SB Block responds correctly to the commands for recording and also executes the DMA transfer 80h is always transferred 2 Only output is supported for this command 3 This command only changes Speaker Status D8h Undocumented commands other than the ones listed above are also supported 32 September 21 1998 YMF724F VATA 2 2 2 Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro ores wr oo e o o o oo rm EA A A ee oan IO c E MC voume o f titer or p tnt Sources Jr EA El io iaE Ee SB Pro Mixer Master Volume L Master Volume R MIDI Volume L MIDI Volume R Lem owes or TT E Line Volume
12. this bit to 1 stops providing the clock with the Legacy Audio function block 1 This block includes MPU401 and Joystick 0 Normal default 1 Power Save A PSN Power Save PCI Audio block Setting this bit to 1 stops providing the clock with the PCI Audio function block This block includes PCI Audio SRC AC3F2 I F AC 2 I F H W Vol and SPDIF 0 Normal default 1 Power Save DE ea Si PRO AC 2 Power down Control O This bit controls the power state of the ADC and Input Mux in AC 2 0 Normal default 1 Power down tel agents ad PR1 AC 2 Power down Control 1 This bit controls the power state of the DAC in AC 2 0 Normal default 1 Power down nulo adsgasea PR2 AC 2 Power down Control 2 This bit controls the power state of the Analog Mixer Vref still on in AC 2 This power state retains the Reference Voltage of AC 2 0 Normal default 1 Power down T PR3 AC 2 Power down Control 3 This bit controls the power state of the Analog Mixer Vref off in AC 2 This power state removes Reference Voltage of AC 2 0 Normal default 1 Power down September 21 1998 22 YMF724F VADIA IA Imi y AA PR4 AC 2 Power down Control 4 This bit controls the power state of the AC link in AC 2 0 Normal default 1 Power down D113 A PR5 AC 2 Power down Control 5 Setting this bit to 1 disa
13. to 1 and D1 state can support b10 D2S D2 Support This bit indicates that DS 1 support D2 of the power state It is hardwired to 1 September 21 1998 25 YME724F VEIA 4 55h Power Man men ntrol Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bis b12 bi bio bo b8 b7 b bs b4 ba b2 bi bo AA ee AAA s b 1 0 PS Power State These bits determine the power state of DS 1 DS 1 supports the following power states 0 DO amp 1 DI not supported pn D2 35 D3 hot When the power state is changed from D3 to DO DS 1 resets the PCI Configuration register 00 3Fh DS 1 transits to DO Uninitialized state Though the power state of this register is changed the power consumption of DS 1 is not changed To support low power Windows driver controls DS 1 Power Control Register DS 1 can support the power state of DO D1 D2 and D3 with ACPI In this case set ACPI bit 58 59h ACPI Mode Register to 1 to disable Capabilities of PCI Bus Power Management 58 59h ACPI Mode Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 bis b12 b11 bio bo b8 b7 b bs b4 ba b2 bi bo aaa aaa ACP DO auus ACPI ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS 1 0 PCI Bus Power Management is
14. Analog Ptr Tri State PCI Ttr Tri State TTL C CMOS Pstr Sustained Tri Sate PCI Tup Pull up Max 300kohm TTL P PCI Pod Open Drain PCI September 21 1998 YMF724F BLOCK DIAGRAM PC PCI D DMA Legacy Audio S IRQ SBPro Rate Converter OPL3 MPU401 pune Joystick PCI Bus Interface BUS Master PCI Audio DMA Controller XG Synthesizer Direct Sound Acc Wave In Out W m In un Uu h t U trl lu iru E ni AC 2 Interface AC3F2 Interface September 21 1998 punogioeuiq YMF724F SYSTEM DIAGRAM oipny 19d oipny Od 40 AXA 19943 sl WH punospaig 1d 9xX IdVZEUIM oipny Dd 40 Aug eoieg 1nOIPIA 1 I I Lost IdVOLUIM uoneoddy OV torNdia ESSE oeBe7 10 AXA youshor pxa pholA sde O I sde11 O I uoneoiddy ulejs I ao 1SASININ sog September 21 1998 YME724F VIMIMIAIRIA FUNCTION OVERVIEW 1 PCI INTERFACE DS 1 supports the PCI bus interface and complies to PCI revision 2 1 1 1 PCI Bus Command DS 1 supports the following PCI Bus commands 1 1 1 Target Device Mode CBE 0 0 0 Interrupt Acknowledge not support 0 Memory Read 0 Memory Write reserved 1 1 Memory Write and Invalidate not support reserved nizi i 2 _ oco o o j o j o j Tj o Io oc Rriz a O O oO O a Rr O OoO R OoOo o a o 1 1 DS 1 does not assert DEV
15. D3 LVDD 3 60 V Operating Ambient Temperature Tow o as 70 cc Note PVSS LVSS VSS 0 V September 21 1998 42 YMF724F VANIA RIA nar i I 3 DC Characteristics High Level Input Voltage 1 We 22 Vpn 40 5 v V Low Level Input Voltage Vu os os v High Level Input Voltage 2 H2 E Ditos V 2 2 2 Low Level Input Voltage 2 2 Pos ll ml High Level Input Voltage3 vm 3 22 Low Level Input Voltage 3 3 3 Low Level Input Voltage 4 EN 4 Input Leakage Current EN O lt Vin Vpps 10 High Level Output Voltage 1 5 Ioui 1mA 2 4 Low Level Output Voltage 1 5 Joy 3mA High Level Output Voltage 2 6 Iom 2mA Low Level Output Voltage 2 6 lor OMA High Level Output Voltage 3 7 Ions 4mA V V ok v High Level Input Voltage 4 v x V ok High Level Output Voltage 4 8 Tong 80uA Vpps 1 0 Low Level Output Voltage 4 Vou Input Pin Capacitance EC Co Clock Pin Capacitance a IL4 In OLA C IN IDSEL Pin Capacitance Output Leakage Current Io 10 Power Supply Current 1 Normal Operation Power Supply Current 2 Power Save ma W 4 UA os vs oo I p E E IE apo Low Level Output Voltage 3 ooo iy END NE ES pa E ES PVDD VDD5 VDD3 9 PVDD VDD5 9 VDD3 Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0
16. L Line Volume R rom sm ss sw se seeon SCAN DATA EE a 3 ron A ros Suspend Resume The registers marked with exist but do not function DS 1 does not have the circuit that corresponds to the SB Mixer Therefore the volume settings on the SB Mixer are converted to the DSP coefficients of DS 1 or to AC 2 register values The conversion for each case is described below 1 SB Mixer gt DSP The volume of master MIDI and Voice are applied to this case When the SB register is set a 14 bit coefficient value is determined from the following conversion table and used as the DSP coefficient The attenuation value of Master Volume MIDI and voice are summed together to obtain the coefficient These volumes cannot be controlled from PCI Audio block September 21 1998 33 YMF724F MIA 1 Volume for MIDI MIDI Vol 26h lvan Cid EESTI RESETAR Moo mue 26d 1608 1008 eoB ado 208 008 The default is Master 4 MIDI 4 12dB Master Vol 22h 2 Volume for Voice Voice Vol 04h Pic Vol 04m Cd EE NEM URGE GEN NE NUES SSB The default is Master 4 Voice 4 16dB I N N o gt is D 2 o 2 SB Mixer gt AC 2 The volume of CD Line and MIC are applied to this case AC 2 volume are not updated automatically when these values are changed Thus the SB Mixer values need to be written to the AC 2 regist
17. S YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR USE AND TITLE Note The specifications of this product are subject to improvement change without prior notice YAMAHA CORPORATION Address inquires to Semi conductor Sales Department AGENCY Head Office 203 MatsunokiJima Toyooka mura Iwata gun Shizuoka ken 438 0192 Tel 81 539 62 4918 Fax 81 539 62 5054 Tokyo Office 2 17 11 Takanawa Minato ku Tokyo 108 8568 Tel 81 3 5488 5431 Fax 81 3 5488 5088 Osaka Office 1 13 17 Namba Naka Naniwa ku Osaka City Osaka 556 0011 Tel 81 6 633 3690 Fax 81 6 633 3691 U S A Office YAMAHA System Technology 100 Century Center Court San Jose CA 95112 Tel 1 408 467 2300 Fax 1 408 437 8791 September 21 1998 50
18. SEL when accessed with commands that are indicated as not supported or reserved 1 1 2 Master Device Mode C BE 3 0 Command 1 1 0 1 1 1 When DS 1 becomes a Master Device it generates only memory write and read cycle commands September 21 1998 YMF724F MAMARIA 1 2 PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2 1 DS 1 provides proprietary PCI Configuration Registers in order to control legacy audio function such as OPL3 Sound Blaster Pro MPU401 and Joystick These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation The following shows the overview of the PCI Configuration Register POAeMemayBaeAMies 10 13h PCI Audio Memory Base Address Reserved 2C 2Fh Subsystem ID Subsystem Vendor ID 38 3Bh Reserved O o 40 43h Legacy Audio Control registers are hardwired to 0 All data written to these registers are discarded The values read from these registers are all zero DS 1 can be accessed by using any bus width 8 bit 16 bit or 32 bit September 21 1998 10 YMF724F 01h Ven m i i i r ID N lg i mi TTE Jal i U AM H Read Only Default 1073h ra I ru ml o Access Bus Width 8 16 32 bit bis bia bis b12 bi bio bo b8 b7 b bs b4 ba b2 b bo b 15 0 Vendor ID Vendor ID This register contains the YAMAHA
19. Time forCBCLK toon 12 o Input Setup Time to CBCLK tosu 13 Input Hold Time for CBCLK 13 Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0 3 V C 250 pF 12 This characteristic is applicable to CSYNC and CSDO signal 13 This characteristic is applicable to CSDI signal September 21 1998 46 YMF724F t CBICYC CBCLK P dn MN aa t CBILOW t CSYNC po shee iy e qu a ao a CSYHIGH Q mmnmnmnnm MIT MIN HA U brand Lim CSDO CSDI Fig 6 AC link timing 4 6 AC3F2 Interface Fig 7 8 tesycyc LASCLK Cyele Time twccve 395 n ASCLK High Time LASCHIGH ASCLK Low Time ASCLK to Signal Valid Delay i ao iso m Do o H0 i m e o 50 qom ET Output Hold Time forASCLK tacon 14 10 m as 14 Input Setup Time to ASCLK 15 i 15 Input Hold Time for ASCLK taom 415 ABCLK Cycle Time ere ABCLK High Time taBIHIGH ABCLK Low Time tABILOW Output Hold Time for ABCLK tyson 16 ao 17 Input Setup Time to ABCLK ns ate poa o pom e x m 10 20 os BH s Input Hold Time for ABCLK um 7 ao m Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0 3 V Cj 250 pF 14 This characteristic is applicable to ACS and ACDO signal 15 Th
20. VAARA 3 DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller 8237 ISA DMAC on the system to transfer the sound data from to the host For DS 1 however ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block Because signals to connect to the ISA DMAC are generally not available on the PCI bus there are two ways proposed from the industry to emulate the ISA DMAC on the PCI bus One is PC PCI and the other is D DMA DS 1 supports both protocols for transferring SB Pro sound data on the PCI bus 3 1 PC PCI DS 1 provides two signals PCREQ and PCGNT to realize the PC PCI The format of the signals is shown below DS 1 asserts PCREQ and sets PCREQ to HIGH using the PCICLK corresponding to the DMA channel it is going to use In addition DS 1 determines whether the next PCI I O cycle is its own from the channel information that is encoded in PCGNT Ons 100ns 200ns 300ns 400ns PCICLK REQ star CHO XcH1 XcH2 KCHS XcH4 XcHs X CH6 X CH7 GNT PCGNT is encoded as follows bit2 bitl bito GNT Bits lo o o DMAChamelo 0 o 1 DMAChanel lo 1 0 DMAChannel2 ofa LL pa Ches 9 Reserved o pos cas 1 o DMAChamel Eat DS 1 supports only 8 bit DMA channels DMA Channel 0 3 It also only suppo
21. Vendor ID registered in Revision 2 1 1073h This register is hardwired to 02 03h Device ID Read Only Default 000Dh Access Bus Width 8 16 32 bit bid b14 b13 b12 b11 bio bo bs b7 be b5 b4 ba b2 b EO Device ID b 15 0 Device ID This register contains the Device ID of DS 1 This register is hardwired to 000Dh 04 05h Command Read Write Default 0000h Access Bus Width 8 16 32 bit MS Memory Space b15 bia bia bi2 bt bio bo b8 b7 bo bs b4 ba b2 bt bo Lo li E EH NENNEN PME vs This bit enables DS 1 to response to Memory Space Access 0 DS 1 ignores Memory Space Access 1 DS 1 responds to Memory Space Access b2 default BME Bus Master Enable This bit enables DS 1 to act as a master device on the PCI bus 0 Do not set DS 1 to be the master device 1 Set DS 1 to be the master device b6 default ii PER Parity Error Response This bit enables DS 1 responses to Parity Error 0 DS 1 ignores all parity errors 1 DS 1 performs error operation when DS 1 detects a parity error 11 September 21 1998 YMF724F m nm ra m LU inl lu Ln hainnise SER SERR Enable This bit enables DS 1 to drive SERR 0 Do not drive SERR default 1 Drives SERR when DS 1 detects an Address Parity Error on normal target cycle or a Data Parity Error on special
22. a b2 b bo Header Type b 7 0 Header Type This register indicates the device type of DS 1 This is hardwired to 00h 10 13h PCI Audio Memory Base Address Read Write Default 00000000h Access Bus Width 8 16 32 bit b15 bia bia biz bt bio bo be b7 bo bo b4 ba b2 bt bo MBA EE EA ESSE ES RS EE ERI A A A RS b 31 14 MBA Memory Base Address This register indicates the physical Memory Base address of the PCI Audio registers in DS 1 The base address can be located anywhere in the 32 bit address space Data in the DS 1 register is not prefetchable DS 1 needs 32768 bytes of memory address space September 21 1998 14 YME724F VARA TRA 2C 2Dh m Vendor ID Read Only Default 1073h Access Bus Width 8 16 32 bit bis bia bis b12 bi bio bo b8 b7 b bs b4 ba b2 bi bo Subsystem Vendor ID b 15 0 Subsystem Vendor ID This register contains the Subsystem Vendor ID In general this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor This register is read only To write the IHV s Vendor ID use 44 45h Subsystem Vendor ID Write Register IHVs must change this ID to their Vendor ID in the BIOS POST routine In case of the system such as Sound Card which BIOS can not control this ID can be changed by connecting EEPROM externally Then Subsystem Vend
23. alue of the shadow register is decremented by 1 5dB on the rising edge of the signal input to the VOLDW pin If it is already set to the minimum value it does not change The value set in the shadow register automatically updates the AC 2 master volume register through the AC Link Also when both VOLUP VOLDW3 pins are at LOW level the MUTE bit of the shadow address is enabled and the Master Volume Mute bit of the AC 2 register is automatically set through the AC Link When a rising edge is detected on either VOLUP or VOLDWY the MUTE bit is reset through the AC Link The Master Volume is set to the value before the Mute If the AC Link is BUSY when controlling the register from the AC 2 Control Register the value in the shadow register is set to AC 2 on the next frame The AC 2 Control Register is set to BUSY in this case When the master volume changes or is muted due to VOLUP VOLDW3 an interrupt is generated at the host The interrupt is used to notify the driver that the Master Volume has been changed from the outside September 21 1998 41 YMF724F WENA ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Symbol Power Supply Voltage 1 PVDD VDDS Power Supply Voltage 2 VDD3 LVDD Input Voltage 1 PVDD VDDS Input Voltage 2 VDD3 LVDD io Operating Ambient Temperature Storage Temperature ES as pens Note PVSS LVSS VSS 0 V 2 Recommended Operating Conditions Power Supply Voltage 2 VD
24. bles the internal clock of AC 2 In case AC 2 is used with DS 1 the master clock is supplied from DS 1 Therefore when the clock of AC 2 is stopped completely set both PR5 and PSN bits to 1 0 Normal default 1 Disable b 15 14 AC 2 Power down Control 6 and 7 The function of this bit is not supported by YAMAHA AC 2 chip But the software can access this register without causing an error PSLO Legacy func O Master PLLO 24 576MHz 33 87MHz bain Legacy func 1 MPU401 Joystick PSN PCI func 0 PLL1 49 152MHz AC3F2 I F AC 2 I F H W Vol PCI Audio SRC SPDIF PCI func 1 PCI I F PC PCI PCICLK 33MHz D DMA S IRQ Set DPLLO DPLL1 PSLO PSL1 and PSN bits to 1 when DMC bit is set to 1 Set PSLO and PSL1 bits to 1 when DPLLO bit is set to 1 Set PSN bit to 1 when DPLLI bit is set to 1 September 21 1998 23 YMF724F VALA A 4C 4Dh D DMA Slav Read Write Default 0000h Access Bus Width 8 16 32 bit bis bia bis b12 bi bio b9 b8 b7 b bs b4 ba b2 bt bo Base Address Ge cue CE Channel Enable This bit enables the Distributed DMA function O Disable Distributed DMA default 1 Enable Distributed DMA Em TS Transfer Size These bits indicate the size of the DMA transfer Since DS 1 supports only 8 bit DMA transfer the bits
25. cycle 06 07h Status Read Write Clear Default 0210h Access Bus Width 8 16 32 bit b15 bia bia biz bt bio bo be b7 bo bo b4 ba b2 bi bo Read Only Pore sse Rma Rta STA Devt pPp car J CAP Capability This bit indicates that DS 1 supports the capability register ister This bit is read only When 58 59h ACPI Mode register ACPI bit is 0 the bit is 1 When ACPI bit is 1 the bit is 0 DPD Data Parity Error Detected This bit indicates that DS 1 detects a Data Parity Error during a PCI master cycle b 10 9 DEVT DEVSEL Timing This bit indicates that the decoding speed of DS 1 is Medium b11 STA Signaled Target Abort This bit indicates that DS 1 terminates a transaction with Target Abort during a target cycle RTA Received Target Abort cycle This bit indicates that a transaction is terminated with Target Abort while DS 1 is in the master memory RMA Received Master Abort cycle This bit indicates that a transaction is terminated with Master Abort while DS 1 is in the master memory SSE Signaled System Error This bit indicates that DS 1 asserts SERR b15 DPE Detected Parity Error This bit indicates that DS 1 detects Address Parity Error or Data Parity Error during a transaction September 21 1998 12 YMF724F VAMARA Li 08h Revision ID Read Only Default O3h Access Bus Width 8
26. d D3 state PCI Bus Master for PCI Audio True Full Duplex Playback and Capture with different Sampling Rate Maximum 64 voice XG capital Wavetable Synthesizer including GM compatibility Supports PC PCI and Distributed DMA for legacy DMAC 8237 emulation Supports Serialized IRQ Supports YAMAHA AC 3 device YMF727 AC3F2 interface to enable AC 3 decode Supports Consumer IEC958 Output SPDIF port Supports AC 2 Interface AC Link Hardware Volume Control EEPROM Interface DirectSound Hardware Acceleration DirectMusic Hardware Acceleration Downloadable Sound DLS level 1 Legacy Audio compatibility Genuine OPL3 Hardware Sound Blaster Pro compatibility MPU401 UART mode MIDI interface Joystick e Single Crystal operation 24 576MHz 5V Power supply for I O 3 3V Power supply for Internal core logic 144 pin LQFP YMF724F V Midi lt SONDIUS YE Xs A Sensaura The contents of this catalog are target specifications and are subject to change i without prior notice When using this device please recheck the specifications YAMAHA CORPORATION September 21 1998 YMF724F VAMARA LOGOS midi GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry AMED gt and indicates GM system level 1 Compliant Xd XG logo is a trademark of YAMAHA Corporation 9 i i j e y b SONDIUS XG logo is a trademark that Stanford University in the United States and YAMAHA
27. e information contained in this document has been carefully checked and is believed to be reliable However Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document 2 These Yamaha Products are designed only for commercial and normal industrial applications and are not suitable for other uses such as medical life support equipment nuclear facilities critical care equipment or any other application the failure of which could lead to death personal injury or environmental or property damage Use of the Products in any such application is at the customer s sole risk and expense 3 YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS 4 YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON NFRINGEMENT WITH RESPECT TO THE PRODUCTS YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS INFRINGEMENT OF ANY THIRD PARTY S INTELLECTUAL PROPERTY RIGHTS INCLUDING THE PATENT COPYRIGHT TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY 5 EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCT
28. enerates an interrupt signal when it receives any kind of MIDI data from the RXD pin 0 The MPU401 block can not use the interrupt service 1 The MPU401 block can use interrupt signals determined by the MPUIRQ bits default e I O I O Address Aliasing Control This bit selects the number of bits to decode for the I O address of each block 0 16 bit address decode 1 10 bit address decode default September 21 1998 17 1 YMF724F VISITE b 7 6 SDMA Sound Blaster DMA 8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block 0 DMA ch0 TIS DMA chl default p reserved SAN DMA ch3 b 10 8 SBIRQ Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block 0 IRQ5 default pr IRQ7 ole IRQ9 eon IRQIO A IRQII 5 7 reserved b 13 11 MPUIRQ MPU401 IRQ Channel Select When MIEN is set to 1 these bits select the interrupt channel for the MPU401 block o IRQ5 eT IRQ7 p IRQ9 default ao IRQIO A IRQII 5 7 reserved Same interrupt channels can be assigned to SBIRQ and MPUIRQ b14 SIEN Serialized IRQ enable DS 1 supports 3 types of interrupt protocols PCI interrupt INTA Legacy interrupt IRQs and Serialized IRQ The interrupt protocol is selected with IMOD and SIEN as follows The interrupt
29. er with the software September 21 1998 34 YMF724F VATA IA 2 2 3 SB Suspend Resume The SB block can read the internal state as to support Suspend and Resume functions The internal state 1s made up of 218 flip flops To read the state these states are shifted in order and read 8 bits at a time from the SCAN DATA register These registers are mapped to the SB Mixer space see SB Mixer Register map The registers have the following functions FOh nin ntrol Read Write Default 00h b7 b6 b5 b4 ba b2 bi sePDA ss sm SE SBPDR DO uuu SBPDR Sound Blaster Power Down Request This bit stops the internal state of the Sound Blaster block 0 Normal default 1 Stop b1 SE Scan Enable This bit Shifts the internal state by 1 bit Setting a 1 followed by a O shifts the internal state D2 uuu SM Scan Mode This bit sets whether to read or write the state 0 Write default 1 Read e AA SS Scan Select This bit gives permission to read or write the internal data to the SCAN DATA register 0 Normal operation Do not allow read or write default 1 Allow read and write AAA SBPDA Sound Blaster Power Down Acknowledgement This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR This bit is read only 0 Read Write not possible 1 Read Write possible
30. he I O address space 0 330h default Ts 300h De 332h 37 334h b 7 6 JSIO Joystick I O Address allocation These bits determine the base I O address for the Joystick block JSBase This block uses byte in the I O address space 0 201h default sy 202h 2S 204h M3 205h D8 AAA MAIM MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is asserted when the acknowledge which is occurred by changing MPU401 mode form default to UART is returned 0 Interrupt is asserted when the acknowledge is returned default 1 Interrupt is masked when the acknowledge is returned September 21 1998 19 YMF724F VADIA IA Ir b 12 11 SMOD SB DMA mode These bits determine the protocol to achieve the DMAC 8237 function on the PCI bus 0 PC PCI default ab reserved SOUS Distributed DMA s3 reserved b 14 13 SBVER SB Version Select These bits set the version of the SB Pro DSP The value set in these bits is returned by sending the Elh DSP command 0 ver 3 01 default Ie ver 2 01 Dee ver 1 05 E reserved b15 IMOD Legacy IRQ mode DS 1 supports 3 types of interrupt protocols PCI interrupt INTA Legacy interrupt IRQs and Serialized IRQ The interrupt protocol is selected with IMOD and SIEN as follows SIEN IMOD Interrupt protocol 0 0 Legacy interrupt IRQs default 0 1 PCI interrupt INTA 1 Se
31. ified by the SBIO bits when LAD is set to 0 The OPL3 registers can be accessed via SB I O space while the SB block is enabled even if FMEN is set to 0 0 Disable the mapping of the SB block to the I O space 1 Enable the mapping of the SB block to the I O space default FMEN FM Synthesizer Enable This bit enables the mapping of the OPL3 block in the I O space specified by the FMIO bits when LAD is set to 0 OPL3 registers can be accessed via SB I O space while the SB block is enabled even if FMEN is set to 0 0 Disable the mapping of the OPL3 block to the FMIO space 1 Enable the mapping of the OPL3 block to the FMIO space default After setting FMEN to 1 about 100 msec is necessary before accessing these I O space GPEN Gameport Enable This bit enables the mapping of the Joystick block in the I O space specified by the JSIO bits when LAD is set to 0 0 Disable the mapping of the Joystick block 1 Enable the mapping of the Joystick block default coslada MEN MPU401 Enable This bit enables the mapping of the MPU401 block in the I O space specified by the MPUIO bits when LAD is set to 0 0 Disable the mapping of the MPU401 block 1 Enable the mapping of the MPU401 block default ET MIEN MPU401 IRQ Enable This bit enables the interrupt service of MPU401 when LAD is set to 0 and MEN is set to 1 MPUA01 g
32. ing September 21 1998 44 YMF724F VANIA 4 3 PCI Interface Fig 3 4 E a FEIC ieh THE tm GM o Fem dt PCICLK Slew Rate RE eS DE ERU ERE ELATI paces vaa po ia eta SE Rs iue ada E patio tm Farma aaa Input Setup Time to PCICLK mE corm it into n La esto ob Jm Note Top 0 70 C PVDD 5 0 0 25 V VDD5 5 0 0 25 V VDD3 3 3 0 3 V LVDD 3 3 0 3 V C 50 pF 10 This characteristic is applicable to REQ and PCREQ signal 11 This characteristic is applicable to GNT and PCGNT signal PCICLK eese eem See a fis tpeyc Fig 3 PCI Clock timing PCICLK OUTPUT Tri State OUTPUT tporr gt lt gt INPUT Fig 4 PCI Bus Signals timing September 21 1998 45 YMF724F VAMARA 4 4 AC 2 AC3F2 Master Clock Fig 5 CMCLK Cycle Time twere 4060 m CMCLK High Time tomou 8 om CMCLKLowTime teow 8 CMCLK Rising Time 4 gt 4 gt t CMHIGH t CMLOW tcmcyc Fig 5 Master Clock timing for AC 2 and AC3F2 4 5 AC link Fig 6 CBCLK Cyce Time tmwe i 814 ns CBCLK High Time tenon 35 407 45 ms CBCLK LowTime temow 35 407 45 m CSYNC Cycle Time tesrere 208 m CSYNCHighTime emu 13 ms CSYNCLowTime temow 095 ms CBCLK to Signal Valid Delay tva fio 20 m Output Hold
33. is characteristic is applicable to ACDI signal 16 This characteristic is applicable to ASDO and ALRCK signal 17 This characteristic is applicable to ASDI signal 47 September 21 1998 YMF724F We h M Hi H i Very oy MISI i LOU bed Lim tasceyc ASCLK ASCLOW ACS ACDO ACDI Fig 7 AC3F2 Control Interface timing ABICYC ABRE Ep ABILOW ASDO ALRCK ASDI Fig 8 AC3F2 Audio Interface timing 48 September 21 1998 I YMF724F VADIA EXTERNAL DIMENSIONS YMF724F V 22 00 0 40 ________ 20 00 0 30 109 72 o o o o o o o e e o A N N 144 37 m L 1 36 LL a BIN a LS 0 20 0 10 P 0 50TYP E amp a o ce 2 EN 1 00 o HH HN 1 LEAD THICKNESS 0 15 0 10 i 0 50 0 20 0 06 The shape of the molded corner may slightly different from the shape in this diagram The figure in the parenthesis should be used as a reference Plastic body dimensions do not include burr of resin UNIT mm Note The LSIs for surface mount need especial consideration on storage and soldering conditions For detailed information please contact your nearest agent of Yamaha September 21 1998 49 m m IMPORTANT NOTICE 1 Yamaha reserves the right to make changes to its Products and to this document without notice Th
34. ling just AdLib only masks the access The driver by Yamaha supports only logical device ID YMH0100 For YMHO0101 use the driver provided by Microsoft September 21 1998 27 i u YMF724F VAARA DS 1 supports PC PCI and D DMA protocols to emulate the DMA of SB Pro on the PCI In addition DS 1 supports the old type of interrupts used by ISA and the Serialized IRQ protocol Yamaha recommends the combination of PC PCI and Serialized IRQ The system block diagram when using Intel 430TX chip set is shown below Address Data Control Bridge PIIX4 iRQ9 4 IRQ10 IRQI l SERIRQ Select either protocols The PCI to ISA bridge needs to support PC PCI IRQ is directly connected to the IRQ input pins on the PCI to ISA bridge September 21 1998 28 YME724F WISIS ir 2 1 OPL3 Block OPL3 Block is register compatible with YMF289B However Power Management register has been deleted because it is now controlled by the PCI Configuration Register The following shows the FMBase I O map of OPL3 FMBase R Status Register port FMBase W Address port for Register Array O FMBase 1 R W Data port FMBase 2 W Address port for Register Array 1 FMBase 3 R W Data port The default FMBase value is 0x0388 The following shows the OPL3 Block registers 2 1 1 Status Register OPL3 Status Register RO eso 9 o T9 o mo rr mu j
35. ma Interrupt9 of Legacy Audio moo o Te toma Imermuptid of Legacy Audio EE cel Interruptl1 of Legacy Audio or Lj A ama o 3 Y amra 1 Tp amem 0 0 0 arer 1 A ReferenceforGamePort RXb Ja Tp MD Daareceive 3333 TXD LO T sma mmi paw transfer September 21 1998 YMF724F WENA 6 Miscellaneous 15 pin ROMCS Ge hi ae Sia Chip select for external EEPROM Serial clock for external EEPROM ROMSK VOLUP IO Tup 3mA or Hardware Volume Up Serial data output for external EEPROM ROMDO VOLDW IO Tup 3mA or Hardware Volume Down Serial data input for external EEPROM or Test pin ROMDI TEST2 Tup air not connect EE ny when EEPROM is not xg las 576 MHz 24 576 MHz Crystal sid X024 HH 24 576 MHz Crystal TEST 7 4 1 0 EEEF Test pins Do not connect externally TEST3 Test pin Connect to ground LOOPF 1 0 IN AE Capacitor of PLL Note Hardware volume and EEPROM interface can not be used at the same time When both hardware volume and EEPROM are not used do not connect these pins externally 7 Power Supply 39 pin Pvpp so Powersupply for PCI Bus Imerface 45 0 jevssiiao Ground for Pct Bus interface voo Powersupply for PLL Fiter 3 3 REUS TOES Ground for PLL Filter vogo Powersupply assy voos _ Powersupply esov vss Ground TYPE T TTL A
36. ntrol This bit controls the CRST signal 0 Inactive CRST High 1 Active CRST Low default bd un XRST Local Device Software Reset Signal Control This bit controls the XRST signal 0 Inactive XRST High default 1 Active XRST Low 4A 4Bh DS 1 Power Control Register Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 bis b12 b11 bio bo b8 b7 b bs b4 ba b2 bi bo PR7 pre PR5 PR4 Pes PR2 eri Pro PSN PSL1 PSLO DPLL DPLLO DMC b DMC Disable Master Clock Oscillation Setting this bit to 1 disables the oscillation of the Master Clock 24 576 MHz 0 Normal default 1 Disable o pe DPLLO Disable PLLO Clock Oscillation Setting this bit to 1 disables the oscillation of PLL for the Legacy Audio function 0 Normal default 1 Disable September 21 1998 21 m UA U jay i LIVNI IA YMF724F WANNA EE DPLL1 Disable PLL1 Clock Oscillation Setting this bit to 1 disables the oscillation of PLL for the PCI Audio function 0 Normal default 1 Disable PSLO Power Save Legacy Audio Block 0 Setting this bit to 1 stops providing the clock with the Legacy Audio function block 0 This block includes OPL3 and SB Pro engines 0 Normal default 1 Power Save PSL1 Power Save Legacy Audio Block 1 Setting
37. or ID Write Register is invalid In case EEPROM is not externally the default value is the YAMAHA s Vendor ID 1073h 2E 2Fh Subsystem ID Read Only Default 000Dh Access Bus Width 8 16 32 bit b14 b13 bi2 b11 bio b9 be b7 bo b5 b4 b8 ba bi Subsystem ID b 15 0 Subsystem ID This register contains the Subsystem ID In general this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor This register is read only To write the IHV s Device ID use 46 47h Subsystem ID Write Register IHVs must change this ID to their ID in the BIOS POST routine In case of the system such as Sound Card which BIOS can not control this ID can be changed by connecting EEPROM externally Then Subsystem ID Write Register is invalid In case EEPROM is not externally the default value is the YAMAHA s Device ID 000Dh 4h ility Register Poin Read Only Default 50h Access Bus Width 8 16 32 bit b7 b b5 b4 b3 b2 bi bo b 7 0 Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58 59h ACPI Mode register ACPI bit is 0 DS 1 provides PCI Bus Power Management registers as the capabilities The Power Management registers are mapped to 50h 57h in the PCI Configuration register and this register indicates 50h When ACPI bit
38. pu 4 YAMAHA YMF72 DS 1 OVERVIEW YMF724F DS 1 is a high performance audio controller for the PCI Bus DS 1 consists of two separated functional blocks One is the PCI Audio block and the other is the Legacy Audio block PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency By using the Software Driver from YAMAHA PCI Audio provides 64 voice XG wavetable synthesizer with Reverb and variation It also supports DirectSound hardware accelerator Downloadable Sound DLS and DirectMusic accelerator Legacy Audio block supports OPL3 Sound Blaster Pro MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver To achieve legacy DMAC compatibility on the PCI DS 1 supports both PC PCI and Distributed DMA protocols DS 1 also supports Serialized IRQ for legacy IRQ compatibility DS 1 supports the connection to YAMAHA YMF730 AC 2 which provides high quality DAC ADC and analog mixing In addition it supports consumer IEC958 Audio Digital Interface SPDIF output for high quality external audio amplification FEATURES e PCI 2 1 Compliant e PC 97 PC 98 specification Compliant PCI Bus Power Management rev 1 0 Compliant Support DO D2 an
39. ration Register 4 1 Serialized IRQ Serialized IRQ is a method to encode IRQs of 15 channels into one signal DS 1 provides the SERIRQ pin to support Serialized IRQ Only one channel out of the 5 channels IRQ5 IRQ7 IRQ9 IRQIO and IRQII can be encoded into the IRQ Data frame of Serialized IRQ The IRQ channel is selected using 40h 43h Legacy Audio Control Register of the PCI Configuration Register 5 Digital Audio Interface DS 1 only supports SPDIF output conforming to IEC958 The only supported Fs is 48 kHz It can be selectable from the Dolby Digital AC 3 encoded data or the result of Digital Mixing September 21 1998 40 YMF724F VEDA 6 Hardware Volume Control The hardware volume control determines the AC 2 master volume without using any software control using the external circuit listed below Two pins VOLUP for increasing the volume and VOLDW for decreasing the volume are used Push SW aa 1k VOLUP Push SW 1k uwe VOLDW amp 1000p T T 1000p DS 1 provides a shadow register for the AC 2 master volume When the software accesses the AC 2 Master Volume it is always reflected in the shadow register The value of the shadow register is incremented by 1 5dB on the rising edge of the signal input to the VOLUP pin If it is already set to the maximum value it does not change The value set in the shadow register automatically updates the AC 2 master volume register through the AC Link The v
40. rialized IRQ 44 45h m Vendor ID Write Register Read Write Default 1073h Access Bus Width 16 bit b15 bia bi3 b12 b11 bio bo b8 b7 b bS b4 ba be bi bO Subsystem Vendor ID Write b 15 0 Subsystem Vendor ID Write Register This register sets the Subsystem Vendor ID that is read from 2C 2Dh Subsystem Vendor ID register The default value is the YAMAHA Vendor ID 1073h IHVs must change this ID to their Vendor ID in the BIOS POST routine In case EEPROM connects externally this register is invalid and do not reflect to Subsystem Vendor ID September 21 1998 20 YMF724F VISA 46 47h m ID Write Register Read Write Default 000Dh Access Bus Width 16 bit b15 bia bia b12 bit bio bo b8 b7 bo bo b4 bs b2 bt bo Subsystem ID Write b 15 0 Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E 2Fh Subsystem ID register The default value is the DS 1 Device ID 000Dh IHVs must change this ID to their ID in the BIOS POST routine In case EEPROM connects externally this register is invalid and do not reflect to Subsystem ID 48 49h DS 1 Control Register Read Write Default 0001h Access Bus Width 8 16 32 bit b15 bia bis b12 b11 bio bo b8 b7 b b5 b4 ba b2 bi bo oper pepe pe SEE spe SERES S Eli DO una CRST AC 2 Software Reset Signal Co
41. rts Single DMA transfer September 21 1998 38 YMF724F 3 2 D DMA A AAA 1 MN il IM i R Ih U trab Em imo DS 1 provides the following registers to support D DMA D DMA Slave Configuration Register 4C 4Dh of the PCI Configuration register is used to set the Base address of the Slave Address Slave Address Base 2h Base 5h NA Bar R w ase Address 0 7 urrent Address 0 7 ase Address 8 15 urrent Address 8 15 urrent Address 16 23 ase Address 24 31 urrent Address 24 31 ase Word Count 0 7 urrent Word Count 0 7 ase Word Count 8 15 Current Word Count 8 15 Base Word Count 16 23 urrent Word Count 16 23 eserved ommand tatus equest eserved ode eserved aster Clear eserved ulti Channel Mask These registers can be accessed by 8 bit or 16 bit bus width DS 1 supports 8 bit DMA transfer only September 21 1998 39 YMF724F AMIGA 4 Interrupt Routing DS 1 supports three types of interrupts interrupt signal on the PCI bus INTA interrupt signal on the ISA bus IRQ 5 7 9 10 11 and Serialized IRQ The IRQs on DS 1 are routed as shown below PCI Audio INTA ISA IRQ IEN IMOD SERIRQ SIED ING La Select Signal Vi PCI Audio can only use INTA but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols The protocol can be switched using 40 43h Legacy Audio Control Register of the PCI Configu
42. tember 21 1998 31 YMF724F 1 DSP Command mam m FATA Hl MEA fnd The following shows the list of DSP Commands that are supported by the SB Pro engine Both SB and SB Pro commands are supported CMD Support Function 10h 14h 16h 17h 1Ch 1Fh 20h 1 24h 1 2Ch 1 30h 31h 34h 35h 36h 2 37h 2 38h 40h 48h 74h 75h 76h 77h 7Dh Note o o o oooooooooooo oo oooooooooooo oo 8bit direct mode single byte digitized sound output 8bit single cycle DMA mode digitized sound output 8bit to 2bit ADPCM single cycle DMA mode digitized sound output 8bit to 2bit ADPCM single cycle DMA mode digitized sound output with ref byte 8bit auto init DMA mode digitized sound output 8bit to 2bit ADPCM auto init DMA mode digitized sound output with ref byte 8bit direct mode single byte digitized sound input 8bit single cycle DMA mode digitized sound input 8bit auto init DMA mode digitized sound input Polling mode MIDI input Interrupt mode MIDI input UART polling mode MIDI I O UART interrupt mode MIDI I O UART polling mode MIDI I O with time stamping UART interrupt mode MIDI I O with time stamping MIDI output Set digitized sound transfer Time Constant Set DSP block transfer size 8bit to 4bit ADPCM single cycle DMA mode digitized sound output 8bit to 4bit ADPCM single cycle DMA mode digitized sound output with ref byte 8bit to 3bit ADPCM single cycle DAM mode digitized sound output 8bit to 3bit ADPCM
43. used CAP bit 06 07h Status Register and Capabilities Pointer 34h are enabled default 1 ACPI Mode is used CAP bit and Capabilities Pointer are hardwired O and disabled September 21 1998 26 YMF724F VEDA 2 ISA Compatible Device DS 1 contains the following functions to maintain the compatibility with the past ISA Sound Devices These devices are considered Legacy devices and the functions are referred to as Legacy Audio Legacy Audio is independent from PCI Audio and can be used simultaneously The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space Basically these registers are configured by the BIOS Also logical device IDs are assigned to the devices to support Plug and Play Yamaha defines the following logical IDs To control the device with the BIOS the logical device IDs must be defined in the PnP BIOS extended ROM space The logical IDs are determined by how it is configured IDs and configuration are as follows Functions used Block Logical Device ID A E OPL3 mPuaoi YMH0100 YMHOI0 p rp ooo 477 e Seer The blocks pertain to the following OPL3 Points to the FM synthesizer mapped to AdLibBase 0x0388 SB Pro Points to the Voice Playback section only These devices are independent from each other and can be Enabled Disabled individually However both AdLib and Sound Blaster must be disabled to disable the internal OPL3 Disab
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