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Xilinx Virtex-5 User's Manual

1. DB3 DB2 DB1 DB0 Data Line Address DB0 10H DB1 11H DB2 12H DB3 13H 0 0 1 0 Page 2 DB4 14H DB5 15H DB6 16H DB7 17H DB0 18H DB1 19H DB2 1AH DB3 1BH 0 0 1 1 Page 3 DB4 1CH DB5 1DH DB6 1 DB7 1FH DB0 20H DB1 21H DB2 22H DB3 23H 0 1 0 0 Page 4 DB4 24H DB5 25H DB6 26H DB7 27H DBO 28H DB1 29H DB2 2AH DB3 0 1 0 1 Page 5 DB4 2CH DB5 2DH DB6 2EH DB7 2FH 124 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Table 2 LCD Panel Continued Hardware Schematic Diagram Line DB3 DB2 DB1 DBO Data Address DB0 BD 30H DB1 E 31H DB2 32H DB3 a 33H 0 1 1 0 Page 6 DB4 B 34H DB5 E 35H DB6 B 36H DB7 37H DBO 38H DB1 39H DB2 B DB3 B 3BH 0 1 1 1 Page 7 DB4 E 3CH DB5 B 3DH DB6 3EH DB7 3FH 1101010 DBO Page 8 ADC 0 0 1 2 3 4 5 6 7 8 9 A 7E 7 80 81 82 83 Column Address ADC 1 83 82 81 80 7 7 7 7 7 7 79 78 5 4 3 2 1 0 i E D C B DI ND NI do
2. Signal Name Pin Signal Name Pin FPGA 3 Test and Debug Signals cont FPGA3_TEST_HDR_BY1_B4 AC24 FPGA3 TEST HDR BY1 B6 AE26 FPGA3 TEST B5 AC25 FPGA3 TEST B7 AE27 FPGA 3 Test Display Signals FPGA3 7SEG 0 N 17 FPGA3_7SEG_6_N AF19 75 1 18 7SEG DP 21 FPGA3_7SEG_2_N 18 LEDO AD19 FPGA3 7SEG 3 N AF18 FPGA3_LED1 AE19 FPGA3 7SEG 4 16 FPGA3_LED2 17 FPGA3 7SEG 5 17 FPGA3_LED3 AF16 FPGA 3 External Interfaces FPGA3 RS232 CTS G15 FPGA3 USB H13 FPGA3 RS232 RIS L18 FPGA3 USB L19 FPGA3 RS232 RX H18 FPGA3 USB RIS N H15 FPGA3 RS232 TX K17 FPGA3 USB RX J20 FPGA3 USB CTS N 14 FPGA3_USB_SUSPEND K19 FPGA3_USB_DSR_N 14 FPGA3_USB_TX 21 FPGA 3 System ACE Control Signals SYSACE CTRLO H12 MPA5 K22 SYSACE CTRL1 523 6 J12 SYSACE_CTRL2 H23 SYSACE_MPDO L21 SYSACE_CTRL3 K13 SYSACE_MPD1 1 20 SYSACE CTRL4 K12 SYSACE MPD2 L15 SYSACE 0 G22 SYSACE MPD3 L16 SYSACE MPA1 H22 SYSACE MPD4 J22 SYSACE MPA2 L14 SYSACE MPD5 K21 K14 MPD6 K16 SYSACE MPA4 K23 SYSACE MPD7 J15 114 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Appendix Bill of Materials This appendix lists the bill of materials BOM for many of the components used for the assembly of the Virtex 5 FPGA ML561 De
3. 2 1 4 9 C 9 Chapter 1 Introduction About the Virtex 5 FPGA ML561 Memory Interfaces Tool Kit 11 Virtex 5 FPGA ML561 Memory Interfaces Development Board 12 Chapter 2 Getting Started Documentation and Reference Design 15 Initial Board Check Before Applying 15 Applying Power to the 16 Chapter 3 Hardware Description Hardware 17 qQ T 18 Tr 19 DDR400 SDRANICOPDOFPONBISs 19 9 1 mE 19 SDRAM Compan ME 20 QDRII 5 2 24 20 OEE PL ees ee 20 Memory PUR PR 21 DDR400 and DDR2 Component 21 PORZ SDRAM DIMM RR nee aqe basa paui 23 ODRII RLDRAM II Memories 25 External Inteffac s Loo cocos do opea swinia Seedy sents ered rua oa teas 27 36 3 5 9 V
4. ADU A opm Voltage mV EE gt Probe 3 C8 1 at pin 25 000 35 000 45 000 55 000 65 000 75 000 Time ns 90199 c7 34 071007 Figure 7 34 DDR2 DIMM Read Correlation Waveform Scope Shot at Probe Point Slow Corner 78 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results Figure 7 35 DDR2 DIMM Read Extrapolation Eye Scope Shot at Receiver IOB Slow Corner Voltage mV Figure 7 36 DDR2 DIMM Read Extrapolation Waveform Scope Shot at Receiver IOB Slow Corner Voltage mV 1800 0 p ns lees 1200 0 5 1000 0 800 0 600 0 400 0 2000 0 2400 0 2800 0 3200 0 3600 0 4000 0 Timedps UG199 c7 35 071007 333 MHz Slow PRBS6 82 UI Cursor 1 1 1007V 2 3997 ns Cursor 2 1 0232V 3 6257 ns Delta Voltage 77 5 mV Delta Time 1 2260 ns 82 UI 1800 0 1600 0 HIME Eo ns LAB IL MEET EH EE EH EE AE I s A ear QUE 11151 eee 30 000 40 000 50 000 60 000 70 000 5 00199 7 36 071007 Virtex 5 FPGA 561 User Guide www xilinx com UG199 v1 2 April 19 2008 79 Chapter 7 ML561 Hardware Simulation Correlation Voltage mV 9 9 sa gt N Z NZ LF Jr AN
5. ST5 ST4 ST3 S 12 ST1 STO 0 0 0 0 0 0 Line address 0 0 0 0 0 0 1 Line address 1 1 1 1 1 1 0 Line address 62 1 1 1 1 1 1 Line address 63 Set reference voltage mode 0 0 1 0 0 0 0 0 0 1 Set reference voltage register 0 0 x x SV5 SV4 SV3 SV2 SV1 SV0 This is a two byte instruction The first instruction sets the reference voltage mode The second instruction sets the reference voltage parameter SV5 SV4 SV3 SV2 SV1 SVO 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 130 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Hardware Schematic Diagram Table C 6 Display Instructions Continued Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Set page address 0 0 1 0 1 1 2 1 PO This instruction sets the address of the display data page Any RAM data bit can be accessed when its page address and column address are specified Changing the Page Address does not affect the display status P3 2 1 PO 0 0 0 0 page 0 0 0 0 1 page 1 0 1 1 1 page 7 1 0 0 0 page 8 Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address LSB 0 0 0 0 0 0 Y2 Y1 YO This instruction sets the address of the display data RAM When a read or write to or from the display data RAM occurs the addresses
6. 133 359454 sone Td ed 134 LCD Panel Used Full Graphics 134 LCD Panel Used in Character 135 Array Connector Numbering tense ni oa a 139 Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 XILINX www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Preface About This Guide This user guide describes the Virtex 5 FPGA ML561 Memory Interfaces Development Board Complete and up to date documentation of the Virtex 5 family of FPGAs is available on the Xilinx website at http www xilinx com virtexo5 Guide Contents This manual contains the following chapters Chapter 1 Introduction Chapter 2 Getting Started Chapter 3 Hardware Description Chapter 4 Electrical Requirements Chapter 5 Signal Integrity Recommendations Chapter 6 Configuration Chapter 7 ML561 Hardware Simulation Correlation Appendix A FPGA Pinouts Appendix B Bill of Materials Appendix C LCD Interface Additional Documentation The following documents are also available for download at http www xilinx com virtex5 Virtex 5 Family Overview The features and product selection of the Virtex 5 family are outlined in this overview
7. wn nin d amp S 181818 1818148 21441414 4 LCD Output N Qo gt 91 N R 0 So P D When a page is addressed all the bits representing dots on the LCD panel can be accessed in that page An array of 8x132 bits is available The line address dictates what line of the 15 going to be displayed on the first line of the glass panel Controller LCD Panel Connections The controller die KS0713 connects to the LCD glass panel and user connection pins via a small PCB Other necessary pins have default connections on the PCB Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 125 Appendix LCD Interface 57 XILINX Controller Power Supply Circuits Figure C 5 shows the power supply circuits The power supply is used in the five times boost mode where VDD 15 3 3 and VOUT 15 16 5V VOUT is the operating voltage of the operational amplifier delivering the operating voltage V0 tor the LCD panel VOUT VR MS 5 xVDD INTRS 2 17 VDD 18 VOUT 25 26 27 28 29 1 30 VSS1 VSS VSS 16 VSS DCDC5B UG199_C_05_050106 Figure C 5 Power Supply Circuits The LCD operating voltage VO is set with two resistors and Rg INTRS is driven Low when the resistors are external INTRS is driven High when the resistors are internal For the Virtex 5 FPGA ML561
8. Notes 1 DDR1_CKE signal has a weak 4 7KQ pull down resistor to meet the memory power up requirements Table 3 4 describes all signals associated with DDR2 Component memories For a complete list of FPGA 1 signals and their pin locations refer to Appendix A FPGA Pinouts Table 3 4 DDR2 Component Signal Summary Notes Board Signal Name s Bits Description DDR2 A 12 0 13 DDR2 Component Address DDR2 CK 1 0 BN 4 DDR2 Component Differential Clock DDR2 ODT 1 0 DDR2 RAS CAS WE 14 DDR2 Component Control Signals DDR2 CKE DDR2 BA 1 0 DDR2 CS 1 0 N DDR2 DM BY 3 0 DDR2 BYO B 7 0 DDR2 DOS BYO BN 10 DDR2 Data and Strobe Byte 0 DDR2 DO 1 B 7 0 DDR2 DOS BY1 BN 10 DDR2 Data and Strobe Byte 1 DDR2 DO BY2 B 7 0 DDR2 DOS BY2 DN 10 DDR2 Data and Strobe Byte 2 DDR2 B 7 0 DDR2 DOS BN 10 DDR2 Data and Strobe Byte 1 DDR2 CKE DDR2 ODTT1 0 signals have a weak 4 7KQ pull down resistor to meet the memory power up requirements XAPP851 DDR SDRAM Controller Using Virtex 5 FPGA Devices XAPP858 High Performance DDR2 SDRAM Interface in Virtex 5 Devices and the corresponding demos are included on the CD shipped with the ML561 Tool Kit For a complete list of FPGA 1 signals and their pin locations refer to Appendix A FPGA Pinouts 22 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19
9. 27 TET 27 Cle eee ee re eee 27 200 MHZ LV PEC Clocks kayana US ews Se eae pa 28 ibw Ol oe ee ede esa 28 Oo MZ tesa pees eee EX UP d es 28 33 MHz System ACE Controller 29 II Gi ele ee ee TE ES 29 NN UPS bi ee ee eee eb bbe bene bebe 29 General Purpose sake PEOR QE bees 29 IESU dc EE 29 Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 57 XILINX Severboeeimmehit Depla y Sesser pe tu opu d ee ok 30 Ieht Emit ng Diodes LEDE ed dem dd tha E 30 16514195 9 pde sua aaa awu aS uu ees dai 30 Power On or Off Slide Switch eum eer Bebe e 31 Soft Touch Probe Poms esos oS red Sheet ees 31 Power Measurement Header 31 Liquid Crystal Display Connector y ona d ptos IEEE ua au apaq 32 Power 33
10. 7SEG 4 16 FPGA1_LED2 17 7SEG 5 17 FPGA1_LED3 AF16 FPGA 1 External Interfaces FPGA1_LCD_BL_ON M6 FPGA1_LCD_E M5 FPGA1_LCD_CSB M7 FPGA1_LCD_R_WB N8 FPGA1_LCD_DBO K6 FPGA1 LCD RESET N L6 1 LCD DB1 K7 FPGA1 LCD RS 7 FPGA1_LCD_DB2 P6 FPGA1_RS232_CTS R11 1 LCD DB3 P7 FPGA1_RS232_RTS G5 1 LCD L5 1 RS232 RX P9 FPGA1 LCD DB5 L4 FPGA1_RS232_TX 5 FPGA1_LCD_DB6 5 FPGA1 TXNO 124 9 FPGA1_LCD_DB7 5 1_ _ 124 10 FPGA1_USB_CTS_N G6 FPGA1_USB_RTS_N G7 FPGA1_USB_DSR_N 6 1 USB RX 9 FPGA1_USB_DTR_N 7 FPGA1_USB_SUSPEND T11 FPGA1 USB T10 FPGA 1 USB TX U10 FPGA 1 Voltage Margining Interface VMARGIN DN 3V3 N 22 VMARGIN_UP_3V3_N AE23 VMARGIN_DN_HSTL_N AE13 VMARGIN_UP_HSTL_N 12 VMARGIN DN 551118 AF13 VMARGIN_UP_SSTL18_N AG12 VMARGIN_DN_SSTL2_N AF23 VMARGIN_UP_SSTL2_N AG23 VMARGIN DN AF20 VMARGIN UP AF21 VMARGIN DN VCC2V5 N 14 VMARGIN_UP_VCC2V5_N AF14 Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 99 Appendix Pinouts 42 Pinout Table 2 lists the connections for FPGA 2 U5 Table A 2 FPGA 2 Pinout 7 XILINX Signal Name Pin Signal Name Pin DDR2 DIMM Deep Interface DDR2_DIMM_AO AG30 DDR2_DIMM1_CK0_N M26 DDR2 DIMM A1 AH29 DDR2_DIMM1
11. m M Ol E 0123456 7 Data 199 10 050106 Figure 10 Block Organization When presenting byte value 30 hex character 0 must be displayed Shifting the value 00110000b 30h up three positions gives the value 180h or 348d Because each character uses eight byte locations character 0 in the character set starts from memory location 348 decimal For example character X has byte value 58h or 01011000b Shifting this value three positions gives the value 2 704d Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 137 Appendix LCD Interface XILINX Dataln Ena E 3 Rst Clk Figure C 11 shows a block diagram of the LCD character generator controller Character data is latched and then shifted left three positions This shifted value is the start byte for a counter that outputs an address to the block RAM The result is a stream of bytes representing a character for the display A small second counter determines when a new character is loaded into the block RAM address counter Position Register Page 8 DesRst Counter A Display gt Register DesRst Clk LUT ROM Counter B Display DesRst Initialization Count to 8 Stop both counters at TC RS Send character position and _ ine to the LoD Ena State Machine Load new value in counter
12. Min Ul 96 VREF VREF 127 570 mV 685 mV DDR2 Component Write 2 84 8 5 63 3 76 1 178 867 mV 349 mV DDR2 Component Read P T T 86 11 9 96 3 38 9 117 253 mV 981 mV DDR2 DIMM Write pis P x 82 7 8 28 1 109 0 224 546 mV 989 mV DDR2 DIMM Read T 82 14 9 60 7 109 9 313 687 mV 186 mV QDRII Write oo pe 83 18 8 76 3 20 7 85 509 mV 1183 mV QDRII Read 87 5 1 56 5 131 5 Here are some observations about extrapolated SI characteristics among these test signals The Data Valid Window DV W values already account for the degradation caused by ISI due to the PRBS6 test pattern For timing analysis two values need to be taken into consideration appropriately For PRBS6 test pattern the worst case DVW value after discounting for ISI is 82 UI for DDR2 DIMM operations DDR2 write operations as compared to ODRII write operations have a lower noise margin due to the always on nature of the DCI termination on the DQ signal for the 551118 II DCI I O standard at the FPGA Consequently the overshoot undershoot margin for DDR2 write operations is higher than for ODRII write operations The DDR2 DIMM write operation has the lowest VIL noise margin of 107 mV For read operations the sum of VIH and VIL noise margins beyond the AC value specifications is at least 509
13. 125 DDR2 DIMM BY4 Y34 DDR2 DIMM BYO U25 DDR2 DIMM BY4 AA34 DDR2 DIMM DQ BYO B2 126 DDR2 DIMM BY4 B2 A A33 DDR2 DIMM BYO U26 DDR2 DIMM BY4 Y33 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 101 Appendix Pinouts Table A 2 FPGA 2 Pinout Continued 57 XILINX Signal Name Pin Signal Name Pin DDR2 DIMM Deep Interface cont DDR2_DIMM_DQ_BY4_B4 V34 DDR2_DIMM_DQ_BY7_B7 Y32 DDR2 DIMM 4 B5 W34 DDR2_DIMM_DQ_CB0_7_B0 D34 DDR2_DIMM_DQ BY4 B6 V33 DDR2 DIMM 7 C34 DDR2 DIMM 4 B7 V32 DDR2 DIMM 7 B2 D32 DDR2 DIMM BY5 AP32 DDR2_DIMM_DQ_CB0_7_B3 C32 DDR2 DIMM DQ AN32 DDR2 7 B4 C33 DDR2 DIMM BY5 B2 AN33 DDR2 DIMM 7 B5 33 DDR2_DIMM_DQ BY5_B3 AN34 DDR2_DIMM_DQ_CB0_7_B6 A33 DDR2_DIMM_DQ_BY5_B4 AM32 DDR2_DIMM_DQ_CB0_7_B7 B32 DDR2 DIMM DO BY5 B5 AM33 DDR2_DIMM_DQS_BY0O_L_N N30 DDR2_DIMM_DQ_BY5_B6 AL33 DDR2_DIMM_DQS_BYO_L_P M31 DDR2_DIMM_DQ_BY5_B7 AL34 DDR2_DIMM_DQS_BY1_L_N P30 DDR2_DIMM_DQ_BY6_B0 U31 DDR2_DIMM_DQS_BY1_L_P P31 DDR2_DIMM_DQ BY6 P1 U32 DDR2 DQS BY2 L31 DDR2 DIMM BY6 B2 134 DDR2_DIMM_DQS_BY2_L_P K31 DDR2 DIMM DOQ BY6 B3 U33 DDR2 134 DDR2 DIMM BY6 B4
14. UG199_c7_49_071107 Figure 7 49 QDRII Read HW Measurement Eye Diagram Scope Shot at Probe Point FPGA3 Via 1800 0 1400 0 1200 0 sQ gt T d WA 1000 0 800 0 Voltage mV 600 0 t IN SR 4 4 Time ps UG199_c7_50_070907 300 MHz Slow PRBS6 59 UI Cursor 1 1 1007V 1 4881 ns Cursor 2 1 0029V 2 4719 ns Delta Voltage 97 9 mV Delta Time 983 8 ps 59 UI 9 9 Figure 7 50 QDRII Read Correlation Eye Diagram Scope Shot at Probe Point Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com 87 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX ejecis Markers Scales 5 00 ns UG199 c7 51 071107 Figure 7 51 QDRII Read HW Measurement Waveform Scope Shot at Probe Point FPGA3 Via Voltage mV a Smm LA EL UH i UH E gt Probe 3 7 1 US ANNE 30 000 40 000 50 000 60 000 70 000 Time ns UG199_c7_52_071007 Figure 7 52 QDRII Read Correlation Waveform Scope Shot at Probe Point Slow Corner 88 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results iz M O gt XX m 1000 0 1400 0 1800 0 2200 0 2600 0 5 90199
15. 59 stimuli Virtex 5 FPGA ML561 User Guide www xilinx com 57 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX VDDQ VSS UG199_c7_02_062707 Figure 7 2 Two Triangular Eye Mask Definitions for VIH and VIL DDR2 mask for nominal VDDQ 1 8V and VREF 0 9V VIH ac min VREF 200 mV 1 1V VIH dc min VREF 125 mV 1 025V VIL ac max VREF 200 mV 0 7V VIL dc max VREF 125 mV 0 775V QDRI mask for nominal values of VDDQ 1 8V and VREF 0 9V VIH ac min VREF 200 mV 1 1V VREF 100 mV 1 0V VIL ac max VREF 200 mV 0 7V VIL dc max VREF 100 mV 0 8V Signal Integrity Correlation Results This section presents SI results for each of the six chosen memory signals on the ML561 board The following information is presented for each memory signal e post layout IBIS schematics of the signal under test e description of the major circuit elements of this signal e A summary of four SI results hardware measurement correlation simulation slow weak corner driver simulation extrapolation and fast strong corner driver simulation extrapolation e A set of eight figures showing eye and waveform scope shots for each of the four SI results mentioned in the bulleted list in the previous section For an explanation of the different terms used to present these results refer to Terminology pag
16. Previous memory boards such as the ML461 had a DisplaytechQ 64128E FC BC 3LP 64x128 LCD panel This display was removed from the ML561 but the connection is still available for use with embedded systems if the user connects the display to connector P104 The LCD panel needs to hang off the edge of the board as shown in Figure 3 8 32 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Power Regulation 1 5232 SPY 7SEG1 TVer Serial Header 12V Input EE VCCAUX 5V Banana Jacks ON FPGA3 12V gt 5V r j aaa P VTT amp VREF Test Header3 System ACE T JTAG Test Header Controller LEDs Config3 OFF 7SEG3 DIP3 LCD Connector 1 5V Input INE Jack Pwr Measure Header r UG199 3 08 050106 Figure 3 8 LCD Panel Connector for Possible LCD Support The product specification at www displaytech com hk pdt graphic 64128e 20series v10 PDF provides more information Appendix C LCD Interface describes the LCD operation in detail Power Regulation This section describes the devices that supply power to the Virtex 5 FPGA ML561 Development Board For electrical requirements and power consumption see Chapter 4 Electrical Requirements Power Distribution The ML561
17. QDR2 QDR2 QDR2_Q 7 513 2 fF 96 3 fF 22 9 fF 22 9 fF 96 3 fF 500 01 06199 7 48 071907 Figure 7 48 Post Layout IBIS Schematics of QDRII Read Data Bit 2082 BYO B5 Table 7 13 Circuit Elements QDRII Read Data QDR2_Q_BY0_B5 Element Designation Description Driver U36 F11 ODRII memory Receiver U34 G33 FPGA HSTL I DCI 18 Probe Point C7 Via under U34 Termination None DCI at FPGA Trace Length TL 1 3 6 8 3 41 inches Table 7 14 QDRII Read Operation Correlation Results DVW ISI Noise Margin Overshoot Undershoot Measurement VIL Total Margin ce of of Hardware at probe point E 70 50 120 ps 7 270 ar 4 a T my Simulation correlation 984 ps 250 264 514 mV 532 518 1050 mV slow weak corner 59 0 prev a 55 57 1 105 5 Correlation Delta 106 ps HW vs Simulation 6 496 27 ps 1 6 386 mV 31 8 50 mV 5 6 Extrapolation at IOB 1 46 ns o 237 272 509 mV 608 575 2 1183 mV slow weak corner 8896 56 5 131 5 Extrapolation at IOB 1 45 ns 341 201 542 mV 532 661 1193 mV fast strong corner 87 60 3 132 6 86 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results
18. 1 B7 26 QDR2 5 P3 AB33 QDR2 1 B8 N28 QDR2 BY5 AC33 QDR2_Q G32 QDR2 5 B5 AB32 QDR2 D34 QDR2 BY5 B6 AC32 QDR2 B2 C34 QDR2 5 B7 AD34 ODR2 BY2 D32 ODR2 Q BY5 B8 AC34 QDR2 Q BY2 B4 C32 QDR2 BY6 Y32 ODR2 OQ BY2 B5 C33 ODR2 OQ BY6 Y34 QDR2 p33 QDR2 Q BY6 B2 AA34 QDR2 Q BY2 B7 A33 QDR2 Q BY6 P3 AA33 QDR2 B8 B32 QDR2 Q 6 B4 Y33 QDR2 Q BY3 H28 QDR2 Q BY6 B5 V34 QDR2 BY3 B1 H27 QDR2 Q BY6 B6 W34 110 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table A 3 FPGA 3 Pinout Continued FPGA 3 Pinout Signal Name Pin Signal Name Pin QDRII Memory Interface cont ODR2 OQ B7 V33 ODR2 B4 W29 ODR2 OQ B8 V32 ODR2 BY7 B5 Y31 ODR2 OQ AB31 ODR2 OQ BY7 B6 W31 QDR2 BY7 Y29 QDR2_Q BY7 B7 V27 QDR2 Q BY7 B2 Y28 QDR2 BY7 B8 V28 QDR2 BY7 B3 V29 RLDRAM Memory Interface RLD2 0 AD10 RLD2 CK BY2 3 N 11 RLD2_A1 AD9 RLD2 CK BY2 3 P AF11 RLD2_A10 8 RLD2 CS BYO 1 AK9 RLD2_A11 AP12 RLD2_CS_BY2_3_N AK8 RLD2_A12 9 RLD2 DK BYO 1 N 8 RLD2_A13 AA8 amp RLD2 DK BYO 1 P AGS8 RLD2 A14 13 RLD2_DK_BY2_3_N 10 RLD2_A15 AN13 RLD2 DK BY2 3 P 9 RLD2_A16 10 RLD2 BYO N C13 RLD2 A17 10 RLD2 O
19. 7 53 070907 300 MHz Slow PRBS6 88 UI Cursor 1 1 1008V 1 2758 ns Cursor 2 998 9 mV 2 7352 ns Delta Voltage 101 9 mV Delta Time 1 4594 ns 88 UI Figure 7 53 QDRII Read Extrapolation Eye Scope Shot at Receiver Slow Corner Voltage mV TE T LI IL 30 000 40 000 50 000 60 000 70 000 Time ns UG199 c7 54 071007 Figure 7 54 QDRII Read Extrapolation Waveform Scope Shot at Receiver IOB Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com 89 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX 90 S gt 1200 0 1600 0 0 EE 0 2800 0 90199 7 55 070907 200 MHz Fast PRBS6 87 UI Cursor 1 801 mV 2 7263 ns Cursor 2 697 0 1 2744 ns Delta Voltage 104 0 mV Delta Time 1 4519 ns 87 UD Figure 7 55 QDRII Read Extrapolation Eye Scope Shot at Receiver IOB Fast Corner 1900 0 1700 0 1500 0 _ HAHH HH 1100 0 900 0 PAR TERRE TF B EE GIG HI WOW Ut l j P 100 0 mig ass E 25 000 35 000 45 000 55 000 65 000 75 000 Voltage mV Time ns UG199_c7_56_071007 Figure 7 56 QDRII Read Extrapolation Waveform Scope Shot at Receiver Fast Corner www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 Summary and Recommendations Summary and Recommendations The first objective of this exercise
20. BYO AF12 FPGA2_SOFTTOUCH_BY0_B6 H15 FPGA2 TEST BYO B7 1 FPGA2 SOFITOUCH 0 B7 14 FPGA2 TEST 1 12 2 1 J19 FPGA2_TEST_HDR_BY1_B1 K13 FPGA2_SOFTTOUCH_BY1_B1 K18 FPGA2_TEST_HDR_BY1_B2 H23 FPGA2_SOFTTOUCH_BY1_B2 G16 FPGA2_TEST_HDR_BY1_B3 G23 FPGA2_SOFTTOUCH_BY1_B3 G15 FPGA2_TEST_HDR_BY1_B4 H12 FPGA2_SOFTTOUCH_BY1_B4 L18 FPGA2_TEST_HDR_BY1_B5 12 FPGA2_SOFTTOUCH_BY1_B5 17 FPGA2 TEST 1 B6 K22 FPGA2 SOFITOUCH 18 FPGA2 TEST 1 B7 K23 FPGA 42 Test Display Signals FPGA2 7SEG 0 N 17 FPGA2 7SEG 6 AF19 FPGA2 7SEG 1 18 2 75 AG21 FPGA2 7SEG 2 N 18 FPGA2 LEDO 19 2 7SEG 3 AF18 FPGA2_LED1 19 2 75 4 16 FPGA2_LED2 17 FPGA2 7SEG 5 17 FPGA2_LED3 AF16 FPGA 2 External Interfaces FPGA2 116 G2 FPGA2 120 RX1 P D1 2 116 2 2 124 10 2 120 2 2 124 9 2 120 FPGA2 124 TX1 N B6 FPGA2 120 RX1 C1 FPGA2 124 TX1 P 5 106 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Table A 2 FPGA 2 Pinout Continued FPGA 2 Pinout Signal Name Pin Signal Name Pin FPGA 2 External Interfaces cont FPGA2_TXNO_BK120 B3 FPGA2_USB_CTS_N L1
21. Mod XCONFIG JTAG 72 114 5 6 3 4 1 2 2 1 0 Master Serial 2 0 0 0 Slave Serial 1 1 1 Master SelectMAP 0 1 1 Slave SelectMAP 1 1 0 JTAG X 1 0 1 Virtex 5 FPGA ML561 User Guide www xilinx com 51 UG199 v1 2 April 19 2008 Chapter 6 Configuration XILINX JTAG Chain JTAG Port Table 6 1 Configuration Modes Continued Mode 50 4 Mod XCONFIG JTAG x P72 P114 5 6 3 gt 4 1 2 2 1 0 System ACE Card 1 1 1 Notes 1 X Supported 2 Not applicable 3 Corresponding jumper position is Closed 4 Corresponding jumper position is Open Four devices the System ACE chip and three XC5VLX50T FFG1136 FPGAs are connected via a JTAG chain on the Virtex 5 FPGA ML561 Development Board The order of the four devices the JTAG chain is System ACE chip U45 FPGA 1 U7 FPGA 2 U5 and FPGA 3 U34 The DONE pin of the FPGAs in the chain are tied together to a single LED D28 Each FPGA in the JTAG chain must be programmed for the board to be configured properly To program FPGAs in the JTAG chain that do not need functionality a blank design with no logic implementation can be used to compile to generate the corresponding configuration bitstream Three different sources can be used to drive this JTAG chain Port Xilinx Parallel Cable e System ACE Controller The Virtex
22. Regulator Resistor Select Set Reference Voltage End Initialization Wait longer than 1 ms between each instruction to let the voltages stabilize The on chip resistors are used Therefore the selection MUST be set to 101 Setting Reference Voltage is a two pass instruction Set Reference Voltage Mode Set Reference Voltage Register UG199_C_06_050106 Figure C 6 LCD Controller Initialization Flow Operation Example of the 64128EFCBC 3LP The 50713 LCD controller has several default settings of operation on the LCD panel PCB Some settings are forced through direct bonding on the chip The default settings are Master mode Parallel mode Internal oscillator Duty cycle ratio is set to 1 65 Voltage converter input is between 2 4V lt VDD 53 6 where VDD connects to 3 3V Internal voltage divider resistors Temperature coefficient is set to 0 05 Normal power mode is set Virtex 5 FPGA ML561 User Guide www xilinx com 127 UG199 v1 2 April 19 2008 Appendix LCD Interface XILINX The voltage follower and voltage regulator are set to Five times boost mode The V4 V3 V2 V1 and outputs depend on the bias settings of 1 9 or 1 7 Because of these default settings the following display controller connections are not used e DISP Turns into an output when Master mode is selected e FRS Static driver segment output e M Used in Master Slave display configurations e CL Clock p
23. 32 bit DDR2 SDRAM 72 bit SRAM UG199_c1_02_050106 Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 13 Chapter 1 Introduction 14 www xilinx com XILINX Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 2 Getting Started This chapter describes the items needed to configure the Virtex 5 ML561 Memory Interfaces Development Board The Virtex 5 FPGA ML561 Development Board is tested at the factory after assembly and should be received in working condition It is set up to load a bitstream from the CompactFlash card at socket J27 through the System ACE controller U45 This chapter contains the following sections e Documentation and Reference Design CD Initial Board Check Before Applying Power e Applying Power to the Board Documentation and Reference Design CD The CD included in the Virtex 5 FPGA ML561 Memory Interfaces Tool Kit contains the design files for the Virtex 5 FPGA ML561 Development Board including schematics board layout and reference design files Open the ReadMe rtf file on the CD to review the list of contents Initial Board Check Before Applying Power Perform these steps before applying board power 1 Setup the Configuration Mode jumpers P27 P46 and P112 for JTAG configuration See Configuration Modes on page 51 for all available modes for the Virtex 5 FPGA ML561 Developmen
24. 59 Chapter 7 ML561 Hardware Simulation Correlation _ XILINX 60 DDR2 DQ is a bidirectional signal To perform hardware measurements for a Write operation that is not interrupted by a Read response or a Refresh operation the testbench on is controlled DIP switches 5W2 as indicated in Table 7 3 Table 7 3 DIP 1 2 Settings Setting Description 2 600 or 2 b11 Normal alternating Write Read sequence 2 1 Write only Refresh disabled 25510 Write once then Read only Refresh disabled www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results UG199_c7_04_071107 Figure 7 4 DDR2 Component Write HW Measurement Eye Scope Shot at Probe Point DDR2 Memory Via AR o aa aay w TY N 800 0 Y Y 600 0 Voltage mV 400 0 TIL 200 0 0 000 1200 0 1600 0 Time ps 200 0 UG199_c7_05_070907 333 MHz Slow PRBS6 81 5 Cursor 1 1 1028V 123 6 ps Cursor 2 1 0253V 1 3458 ns Delta Voltage 77 5 mV Delta Time 1 2222 ns 81 5 Figure 7 5 DDR2 Component Write Correlation Eye Scope Shot at Probe Point Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com 61 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation 57 XILINX eje 5 00 ns 06199 7 06 071107
25. Hardware Description 7 XILINX Table 3 5 describes all the signals associated with DDR2 DIMM component memories For the Deep DIMM interface to four DIMMs the individual dedicated control signals are listed at the bottom of Table 3 5 Table 3 5 DDR2 DIMM Signal Summary Board Signal Name s Bits Description DDR2_DIMM_A 15 0 16 DDR2 DIMM Address DDR2 DIMM 5 1 CK 2 0 PN 30 DDR2 DIMM Differential Clocks Three copies per DIMM DDR2 RAS CAS WE RESET 37 DDR2 DIMM Common Control Signals DDR2 DIMM 5 1 CKE 1 0 DDR2 DIMM BA 2 0 DDR2 DIMM 5 1 CS 1 0 N DDR2 DIMM 5 1 ODT 1 0 DDR2 DIMM 1 5 CS 1 0 20 DDR2 DIMM Dedicated Control Signals DDR2 DIMM 1 5 CKE 1 0 DDR2_DIMM 1 5 _ODT 1 0 DDR2 DIMM LB BK 11 13 15 IN OUT 6 Deep DIMMs DIMMI through DIMM4 Loopback Signals DDR2 LB BK 12 18 20 3 Wide DIMM DIMMD Loopback Signals Total of six FPGA pins DDR2 DIMM 1 5 CNTL PAR 20 Miscellaneous Place Holder Signals to the Five DDR2 DIMM 1 5 CNTL PAR ERR DIMMs DDR2 DIMM 1 5 NC 019 DDR2 DIMM 1 5 NC 102 DDR2 BYT 0 15 B 7 0 176 DDR2 DIMM Doata Strobes and Data Mask Bytes 0 DDR2 DIMM DOS BY 0 15 D N through 15 DDR2 DM BY 0 15 DDR2 DIMM 7 B 7 0 1 DDR2 DIMM Data Strobes and Data Mask Check DDR2 DIMM DOQS 7 Byte 0 2 DIMM DM 7 DDR2 CBS
26. Rr DETUR 33 Vole caren attain orca wa au eae his ass are 34 Board Design 1 36 Chapter 4 Electrical Requirements Power Consumption 22 55245 T ERES Seeks 39 FPGA Internal Power 46 Chapter 5 Signal Integrity Recommendations Termination and Transmission Line Summaries 47 Chapter 6 Configuration Configuration Modes 51 TAG CDa nce Port dead dde Rar ERR 52 IPO I se Gee eae cee 52 Parallel IV Cable Port 52 System ACE Interface 52 Chapter 7 ML561 Hardware Simulation Correlation 22520505 ES ROTEPRHETERISRFIFRERPUREM amas 55 Test DEUD 222 56 Signal Integrity Correlation 5 58 DDR2 Component Write i oper Sa Hee ptr Een eus 59 DDR Component Read 65 DIMM Write Operations s sse a re Vh bre pes
27. SSTL18_II No termination 50Q pull up to 0 9V after the second CS CKE and others DIMM Notes 1 Due to use of DCI I O for DQ and DOS these signals have parallel termination at the source during Write operations Simulation results show that use of a weaker 750 ODT instead of a matching 500 setting gives better noise margin at the memory 2 The DIMM already contains 1200 differential termination A 5 pF capacitive termination is provided on the board as per Micron TN 47 01 Table 5 3 DDR2 SDRAM Component Terminations Signal FPGA Driver Termination at FPGA Termination at Memory Data SS5IL18 DCI No termination No termination use 75Q ODT Data Strobe DOS DOS DIFF SSTL18 II DCI No termination No termination use 75Q ODT Data Mask DM SSTL18 No termination No termination use 75Q ODT Clock CK CK SSTL18 II No termination 100Qdifferential termination between pair Address A BA SSTL18 II No termination 50Q pull up to 0 9V after the last component Control RAS CAS WE CS SSTL18_II No termination 50Q pull up to 0 9V after the last and CKE component 48 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table 5 4 QDRII SRAM Terminations Termination and Transmission Line Summaries Signal FPGA Driver Termination at FPGA Termination at Memory Write Data D HSIL I 18 No termination 50Q pull up to
28. See XAPP852 RLDRAM II Memory Interface for Virtex 5 FPGAs e One 9 5 232 port and one USB 2 0 port e System ACE CompactFlash CF Configuration Controller that allows storing and downloading of up to eight FPGA configuration image files On board power regulators with 5 output margin test capabilities 12 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Virtex 5 FPGA ML561 Memory Interfaces Development Board Figure 1 2 shows the Virtex 5 FPGA ML561 Development Board and indicates the locations of the resident memory devices 47 5 DIMM4 ODIMM2 ANI LI f ppop BUR 1 S XILINX VIRTEX 45 ADVANCED MEMORY 7 DEVELOPMENT SYSTEM 144 bits wide DDR2 SDRAM DIMM 72 bits wide up to 4 deep 36 bit RLDRAM II VIRTEX 4 zm XX 105 1 52 VP ML5 l REV 12 C574 5 pC 73 P CA Ke 5 Lad 3 pas e r c 545 XIUNX VIRTEX 4 XC5VLX50T val 9097 011 TIT DT a wee WE Figure 1 2 Virtex 5 FPGA ML561 Development Board FULLY BUFFERED DIMM LLL 11111111 LIII 32 bit DDR400 SDRAM
29. one FPGA for interfacing with a host PC The RS 232 interface is accessible through a male DB 9 serial connector P73 Table 3 8 RS 232 Jumper Settings To Connect FPGA to DB 9 P73 TX RX FPGA 1 P52 Pin 2 gt P52 Pin 1 P53 Pin 2 gt P53 Pin 1 FPGA 2 P52 Pin 2 gt P51 Pin 1 P53 Pin 2 gt P54 Pin 1 FPGA 3 P52 Pin 2 gt P52 Pin 3 P53 Pin 2 gt P53 Pin 3 USB Full speed 12 Mbps USB functionality is proved using a Silicon Laboratories CP2102 GM USB to RS 232 Bridge RS 232 and USB signals are converted between one another so a RS 232 core needs to be implemented in the FPGA for communication A level translator is used to convert between the 2 5V I O of the FPGA and the 3 3V I O the CP2102 uses Hooks are provided to connect and disconnect FPGAs to the USB connection by placing jumpers on headers based on the FPGA involved in the communication Only one FPGA is allowed in the communication and others must be disconnected before operation The USB interface is accessible through a female A USB connector J29 Table 3 9 USB Jumper Settings To Connect FPGA to DB 9 129 TX RX FPGA 1 P36 Pin 2 gt P36 Pin 1 P22 Pin2 gt P22 Pin 1 FPGA 2 P36 Pin 2 gt P35 Pin 1 P22 Pin2 gt P23 Pin 1 FPGA 3 P36 Pin 2 gt P36 Pin 3 P22 Pin2 gt P22 Pin 3 Clocks The ML561 board contains a 200 MHz LVPECL clock oscil
30. 1 5 0 8000 40 0 Bellus Power SPD 050 5 12V Power Supply 1 12 0 5000 60 0 CUI DTS120500U Power Consumed DDR400 Component Interface 17 gg DDR 16 Memory 2 2 6 210 11 Micron DDR Component Data Sheet DDR Comp Termination 60 1 2 16 12 All signals 4608 mV swing around DDR2 Component Interface XC5VLX50T FFG1136 1 1 0 1 8 S 1991 31 Xilinx Power Estimator FPGA 1 DDR2 245 DDR2 x16 Memory 2 1 8 250 0 9 Micron DDR2 Component Data Sheet DDR2 Comp Termination 25 1 2 16 0 5 Addr Cntl 603 mV swing around DDR2 DIMM Interface XC5VLX50T FFG1136 1 1 0 1 8 S 6420 102 Xilinx Power Estimator FPGA 2 DDR2 2 5 DDR2 DIMM 2 1 8 1755 63 Micron DDR2 DIMM Data Sheet DDR2 DIMM Termination 160 1 2 16 31 All signals 603 mV swing around QDRII Memory Interface XC5VLX50T FFG1136 1 1 0 1 8 H 3917 63 Xilinx Power Estimator FPGA 3 ODRITI 1 8 S 2 5 ODRII Memory 2 1 8 950 3 4 Samsung ODRII Data Sheet ODRII Termination 175 1 0 16 28 All signals 500 mV swing around RLDRAM 11 Memory Interface XC5VLX50T FFG1136 1 1 0 1 8 H 3069 45 Xilinx Power Estimator FPGA 3 RLDRAM II 2 5 RLDRAM II Memory 2 1 8 920 3 3 Micron RLDRAM II Data Sheet RLDRAM II Termination 60 1 0 16 10 All signals 500 mV swing around Miscellaneous Circuit Clock Buffer 1 3 3 23 0 1 ICS8304 Data Sheet Differential Clock Buffer 2 9 9
31. 15 7 0 1 DDR2 DIMM Data Strobes and Data Mask Check DDR2 DIMM DOQS 8 15 DN Byte 1 DDR2 DIMM DM 8 15 DDR2 DIMM 1 5 SA 2 0 15 Serial PROM Address DDR2 DIMM SCL SDA 2 Serial PROM interface CLK and Data Notes 1 DDR2 DIMM CKE DDR2 ODT signals are connected to a 4 7KQ pull down resistor to meet the memory power up requirements 858 High Performance DDR2 SDRAM Interface in Virtex 5 Devices and its corresponding demo are included on the CD shipped with the ML561 Tool Kit 24 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Memory Details QDRII and RLDRAM Memories Figure 3 5 summarizes the distribution of QDRII and RLDRAM II component interface signals among the different banks of the FPGA 3 device BANK 124 BANK 5 20 23 40 120 20 40 3 20 19 40 RLDII Data General I O QDRII Data DQ 0 1 amp DO Q1 3 amp D1 BANK 116 BANK 1 20 BANK 15 40 System ACE Controls Data D7 2 3 0 BANK 112 BANK 12 40 BANK 11 40 RLDII Data QDRII Data DQ 2 3 amp D1 Configuration QO 2 amp D6 BANK 114 BANK 0 BANK 13 40 QDRII Data Q4 5 6 BANK 118 BANK 18 40 BANK 2 20 BANK 17 40 RLDII Data Inter FPGA Links Data D2 3 Q7 amp D4 5 BANK 122 BANK 22 40 BANK 4 20 BANK 21 40 RLDII Address Global Clock Inputs QDRII Address and Contro
32. 2 990 0 7 17 2 Extrapolation at IOB 1 29 ns 96 82 178 ps 418 449 867 mV 304 265 569 mV slow weak corner 86 11 9 96 3 63 1 Extrapolation at IOB 1 32 ns 29 67 96 ps 455 435 890 mV 167 182 349 mV fast strong corner 88 6 7 98 9 38 9 To perform hardware measurements for a Read operation that is not interrupted by a Write a Refresh operation the testbench on FPGAT is controlled by the following DIP switch 5W2 setting e DIP 1 2 2 b10 Write once then Read only Refresh disabled Virtex 5 FPGA ML561 User Guide www xilinx com 65 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX e ec2s x UG199_c7_13_071107 Figure 7 13 DDR2 Component Read HW Measurement Eye Scope Shot at Probe Point FPGA1 Via on 1700 0 Pret gt IN a din 1500 0 ee Cr A Ht RW UNE ANCIEN wot WEL A Voltage mV Wm a paren ES 100 0 9229 n ui E s aon NETUS 100 0 Crane 5071 at P 800 0 1200 0 1600 0 2000 0 2400 0 2800 0 Time ns 333 MHz Slow PRBS6 85 9 UI Cursor 1 697 1 mV 1 2345 ns Cursor 2 774 6 mV 2 5191 ns Delta Voltage 77 5 mV Delta Time 1 2846 ns 85 995 UI UG199 c7 14 071107 9 Figure 7 14 DDR2 Component Read Correlation Eye Scope Shot at Probe Point Slow Corner 66 www xilinx
33. 2008 XILINX DDR2 SDRAM DIMM Memory Details The FPGA 2 device on the Virtex 5 FPGA ML561 Development Board is connected to DDR2 memories The DDR2 memory interface includes a 144 bit wide DIMM connection to up to five 240 pin DDR2 DIMM sockets For the 144 bit wide DIMM datapath the data bytes are spread across multiple banks of the FPGA 2 device Figure 3 4 summarizes the distribution of DDR2 DIMM interface signals among the different banks of the FPGA 2 device BANK 124 TX 0 1 BANK 120 RX 0 1 116 GTP CLK BANK 112 BANK 114 BANK 118 BANK 122 BANK 126 Figure 3 4 FPGA 2 Banks for DDR2 DIMM SSTL18 Interfaces Top View Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 BANK 20 40 DDR2 DIMM DQ 8 9 10 BANK 12 40 DDR2 DIMM DQ 11 12 CB8_15 BANK 18 40 DDR2 DIMM DQ 14 15 13 BANK 22 40 DDR2 DIMM DIMM 4 amp 5 www xilinx com lt Z N BANK 3 20 General I O BANK 1 20 General I O Configuration BANK 0 BANK 2 20 Inter FPGA MII Links BANK 4 20 Global Clock Inputs BANK 23 40 19 40 DDR2 DIMM Controls amp DIMM1 BANK 15 40 DDR2 DIMM DQ 0 1 2 BANK 11 40 DDR2 DIMM DQ 6 3 7 BANK 13 40 DDR2 DIMM DQ 5 7 4 BANK 17 40 DDR2 DIMM Common Controls BANK 21 40 DDR2 DIMM DIMM 1 2 3 Cntl UG199 c3 04 050106 23 Chapter 3
34. 28 5 ohms 71 0 ohms 49 0 ohms 58 3 ohms 2 132 148 590 21 2 ohms VIHGRE ROGA MB 4M8CB 579 ps 27 482 ps 24 721 ps 25 244 ps I5 ps 1 000 ps Irtex SAMBO ES 003 in AutoPadstk 3 0 164 in AutoPadstk 19 0 302 2 852 AutoPadstk 3 0 028 DDR2 DQ BY2 B3 DDR2 _DQ_BY2_B3 DDR2_DQ_BY2_B3 DDR2 DQ BY2_B3 DDR2 BY2_B3 DDR2 DO BY2 B3 4 DDR2_D DDR2 DDR2 D DDR2_D DDR2_D DDR2 D d 22 9 fF 58 1 fF 22 9 fF 22 9 fF fF 365 6 fF 500 0 fF UG199_c7_12_071907 Figure 7 12 Post Layout IBIS Schematics of the DDR2 Component Read Data Bit DDR2_DQ_BY2_B3 Table 7 4 Circuit Elements of DDR2 Component Read Data Bit DDR2_DQ_BY2_B3 Element Designation Description Driver U12 D3 DDR2 Memory Receiver U7 P25 FPGA 551118 II DCT I Probe Point C7 Via under FPGA1 Termination None DCI at receiver Trace Length 2 4 9 6 1 3 37 inches Table 7 5 DDR2 Component Read Operation Correlation Results ISI Noise Margin Overshoot Measurement DVW UI UI VIL Total Undershoot Margin of VREF of VREF 1 28 70 110 180 ps 423 416 2 839 mV 400 400 800 mV Hardware at probe point P 85 12 83 1 79 1 Simulation correlation 1 28 ns 132 91 223 ps 406 439 845 mV 279 277 556 mV slow weak corner 85 14 9 83 8 61 9 Correlation Delta 0 ps 43 ps 6 mV 244 mV HW vs Simulation 0 096
35. BK19 K27 ODR2 BW BY5 N AK34 ODR2 LB BK19 M28 ODR2 BW BY6 N AC29 ODR2 NC A3 AG25 ODR2 BW BY7 N AD30 ODR2 NC C6 AF24 ODR2 D BYO BO 128 ODR2 R N AJ26 ODR2 D BYO B1 U30 QDR2 540 AJ29 QDR2 D BYO0 B2 R31 ODR2 SA1 AK29 ODR2 D BYO B3 T31 QDR2_SA10 AC28 QDR2_D_BY0_B4 N30 108 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table A 3 FPGA 3 Pinout Continued FPGA 3 Pinout Signal Name Pin Signal Name Pin QDRII Memory Interface cont ODR2 D BYO B5 M31 ODR2 D BY4 AH29 ODR2 D BYO B6 P30 ODR2_D_BY4_B2 ODR2 D BYO B7 P31 ODR2_D_BY4_B3 AJ30 ODR2 D BYO B8 L31 ODR2 D 4 B4 AF30 ODR2 D BY 127 ODR2_D_BY4_B5 AF29 ODR2_D_BY1_B1 M26 ODR2 D 4 B6 AK31 ODR2 D B2 M25 ODR2 D 4 B7 AJ31 ODR2 D BY J25 ODR2 D BY4 B8 AD29 ODR2_D_BY1_B4 J24 ODR2_D_BY5_BO V30 ODR2_D_BY1_B5 1 26 ODR2_D_BY5_B1 W27 ODR2_D_BY1_B6 L25 ODR2_D_BY5_B2 Y27 ODR2 D 1 B7 L24 ODR2 D BY5 W25 ODR2 D BY B8 K24 ODR2 D BY5 V25 ODR2 D BY2 0 1 29 ODR2 D BY5 B5 W26 ODR2 D BY2 E31 ODR2 D BY5 Y26 ODR2 D BY2 B2 F31 ODR2 D BY5 B7 V24 ODR2 D BY2 P3 J29 ODR2_D_BY5_B8 W24 ODR2 D BY2 B4 H29 ODR2 D U31 ODR2 D BY2 B5 F30 ODR2 D BY6 P1 U32 ODR2 D BY2 B6 G30 ODR2 D B2 T34 QDR2_D_BY2_B7 F29 QDR2_D_BY6_B3 U33 QDR2_D_BY2_B8 E29 QDR2_D_BY6_B4 R32 QDR2_D_BY3_B0 K31 QDR2_D_BY6_B5
36. Cursor 2 1 0253V 2 4671 ns Delta Voltage 77 5 mV Delta Time 1 2272 ns 82 UI Figure 7 26 DDR2 DIMM Write Extrapolation Eye Scope Shot at Receiver Slow Corner Voltage mV 1800 0 1600 0 1400 0 LT ee 00 0 95 000 105 000 115 000 125 000 135 000 145 000 Time ns UG199_c7_27_071007 Figure 7 27 DDR2 DIMM Write Extrapolation Waveform Scope Shot at Receiver IOB Slow Corner 74 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results Voltage mV 9 9 9 9 u g s ss B wi T 1400 0 Gt N 47a 1200 0 1000 0 800 0 600 0 400 0 dmim m iisas ERE mE E lll m _ LLL 400 0 800 0 1200 0 1600 0 2000 0 2400 0 Time ps UG199 c7 28 071007 333 MHz Fast PRBS6 88 UI Cursor 1 1 1004V 646 3 ps Cursor 2 1 0273V 1 9659 ns Delta Voltage 73 1 mV Delta Time 1 3196 ns 88 UI Figure 7 28 DDR2 DIMM Write Extrapolation Eye Scope Shot at Receiver Fast Corner Voltage mV 95 000 105 000 115 000 125 000 135 000 145 000 Time ns 90199 c7 29 071007 Figure 7 29 DDR2 DIMM Write Extrapolation Waveform Scope Shot at Receiver IOB Fast Corner Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 75 Chapter 7 ML561 H
37. Development Board internal resistors are selected The LCD operating voltage and the Electronic Volume Voltage can be calculated in units of V using Equation C 1 and Equation C 2 R VO 1 Vey Equation C 1 RA Va jq e 300 In Equation C 2 Vpgg is equal to 2 0V at 25 C x Vere Equation C 2 The values of the reference voltage parameter and the ratio RA are determined with bit settings in the LCD controller s instruction registers Thus it is possible to change physical operating parameters of the LCD through register bit settings controlling the operating voltage and the electronic volume level 126 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Hardware Schematic Diagram The voltage and contrast settings must be configured before the LCD panel is ready for operation Figure C 6 shows the initialization procedure required to set up the LCD controller Setup Instruction Flow Board Power Supply Start RESETB Pin is Kept LOW Start FPGA Configuration RESETB Pin is Kept LOW FPGA Configured and Application Running RESETB Pin is Taken HIGH ADC Select 0 SEG1 gt SEG132 ADC Select o cua ADC 1 SEG132 gt SEG1 SHL Select U LCD Bias 0 1 7 SHL Select LCD Bias Select LCD Bias 1 1 9 SHL 0 COM1 gt COM64 SHL 1 COM64 gt COM1 Voltage Converter ON Voltage Regulator ON Voltage Follower ON
38. Figure 7 6 DDR2 Component Write HW Measurement Waveform Scope Shot at Probe Point DDR2 Memory Via 1800 0 1600 0 TUE TT exl ULL 600 0 200 0 0 000 gt Probe 3 C9 1 at pin lll MEME 65 000 75 000 85 000 95 000 105 000 Time ns Voltage mV UG199 c7 07 070907 Figure 7 7 DDR2 Component Write Correlation Waveform Scope Shot at Probe Point Slow Corner 62 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Signal Integrity Correlation Results Figure 7 8 DDR2 Component Write Extrapolation Eye Scope Shot at Receiver IOB Slow Corner 1600 0 Voltage mV 9 9 9 9 Voltage mV 200 0 200 0 200 0 600 0 1000 0 1400 0 1800 0 gt X ff v 1000 0 A 2 s A UA 200 0 1 1 333 MHz Slow 56 84 5 UI Cursor 1 1 1007V 123 7 ps Cursor 2 1 0253V 1 3921 ns Delta Voltage 75 4 mV Delta Time 1 2684 ns 84 5 UI w wot NL E LLLI N TCR 1200 0 AF 400 0 a 200 0 so mn en r L 0 0 65 000 75 000 85 000 95 000 105 000 Time ns UG199_c7_09_071007 UG199_c7_08_071007 Figure 7 9 DDR2 Component Write Extrapolation Wav
39. Headers The 16 pin test headers are surface mounted one per FPGA Of the two bytes of test signals traces are matched for signals within a byte Table 3 13 Test Headers Header Signal Description Header Pin FPGA1 TEST HDR BYO B 0 7 P20 TEST1 Odd pins 1 3 5 7 9 11 13 15 FPGA1 TEST HDR 1 B 0 7 P20 TEST1 Even pins 2 4 6 8 10 12 14 16 0 7 FPGA2 TEST B 0 7 P21 TEST2 Odd pins 1 3 5 7 9 11 13 15 2 TEST B 0 7 P21 TESI2 Even pins 2 4 6 8 10 12 14 16 FPGA3 TEST HDR BYO B 0 7 P93 TEST3 Odd pins 1 3 5 7 9 11 13 15 FPGA3 TEST B 0 7 P93 TEST3 Even pins 2 4 6 8 10 12 14 16 DIP Switch One four position DIP switch per FPGA for a total of three is available to externally pull up or pull down a signal on the FPGA This can be used to manually set values used by the design running on the FPGA Virtex 5 FPGA ML561 User Guide www xilinx com 29 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description 57 XILINX Seven Segment Displays One seven segment display per FPGA for a total of three is available for use The red Stanley Electric NAR131SB displays are active Low using seven inputs to display character or number plus another input for a decimal point 7SEG 0 1 7SEG 5 7SEG 1 7SEG 6 7SEG 4 75 2 7SEG 3 7SEG 06199 3 06 050106 Figur
40. IS INS 1 OT D ip ccc ERE ot pm 400 0 800 0 1200 0 1600 0 2000 0 2400 0 Time ps UG199_c7_37_071007 333 MHz Fast PRBS6 83 UI Cursor 1 697 0 m V 763 0 ps Cursor 2 776 6 mV 2 0052 ns Delta Voltage 79 5 mV Delta Time 1 2422 ns 83 UD XILINX Figure 7 37 DDR2 DIMM Read Extrapolation Eye Scope Shot at Receiver IOB Fast Corner Voltage mV 1800 0 1600 0 S Bar uL IL IL UL Tw 200 0 ll 30 000 40 000 50 000 60 000 70 000 Time ns UG199_c7_38_071007 Figure 7 38 DDR2 DIMM Read Extrapolation Waveform Scope Shot at Receiver IOB Fast Corner 80 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Signal Integrity Correlation Results QDRII Write Operation This subsection shows the test results for the ODR2 D BYO B5 signal from 034 to memory U35 measured at 300 MHz 600 Mb s where the unit interval UI 167 ns 49 0 ohms VCCOV7 5 283 ps C 0 9V 0 035 in R1586 QDR2 D BYO B5 4 49 9 ohms TL6 28 5 ohms 49 0 ohms 49 8 ohms 28 5 ohms 4 404 ps 71 0 ohms 11 902 ps 45 1 ohms 520 665 ps 70 8 ohms 4 473 U35 G11 0 027 in 27 482 ps 0 079 in 7 862 ps 3 333 in 16 339 ps 0 028 in U34 M31 QDR2 D BYO B5 AutoPadstk 3 QDR2 D BYO B5 AutoPadstk 19 QDR2 D BYO B5 AutoPadstk QDR
41. R32 DDR2 DIMM DQS P H34 DDR2 DIMM BY6 B5 R33 DDR2 DIMM DOQS BYA4 AE34 DDR2_DIMM_DQ_BY6_B6 R34 DDR2_DIMM_DQS_BY4_L_P AF34 DDR2_DIMM_DQ_BY6_B7 133 DDR2_DIMM_DQS_BY5_L_N 2 DDR2_DIMM_DQ BY7 AF33 DDR2_DIMM_DQS_BY5_L_P AD32 DDR2 DIMM DQ BY7 P1 A B33 DDR2 DIMM DOS BY6 K32 DDR2 DIMM BY7 B2 AC33 DDR2 DIMM DOS BY6 L P K33 DDR2 DIMM DO BY7 AB32 DDR2_DIMM_DQS_BY7_L_N AJ34 DDR2 DIMM DQ BY7 B4 AC32 DDR2_DIMM_DQS_BY7_L_P AH34 DDR2_DIMM_DQ_BY7_B5 AD34 DDR2_DIMM_DQS_CB0_7_L_N K34 DDR2_DIMM_DQ_BY7_B6 AC34 DDR2_DIMM_DQS_CB0_7_L_P L34 DDR2 DIMM Wide Interface DDR2 5 13 DDR2_DIMM5_CK2_N AP14 DDR2_DIMM5_CK0_P AN13 DDR2_DIMM5_CK2_P AN14 DDR2_DIMM5_CK1_N AA10 DDR2_DIMM5_CKEO 10 DDR2_DIMM5_CK1_P AB10 DDR2_DIMM5_CKE1 102 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX FPGA 2 Pinout Table A 2 FPGA 2 Pinout Continued Signal Name Pin Signal Name Pin DDR2 DIMM Wide Interface cont DDR2_DIMM5_CSO_N V24 DDR2 DIMM BY11 B5 G6 DDR2 DIMM5 CS1 W24 DDR2 DIMM DO BY11 T11 DDR2 DIMM 5 AA9 DDR2 DIMM DO BY11 B7 T10 DDR2_DIMM5_ODT1 8 DDR2 DIMM DQ 12 16 DDR2_DIMM_LB_BK12 5 DDR2_DIMM_DQ_BY12_B1 T6 DDR2_DIMM_LB_BK12 F6 DDR2_DIMM_DQ_BY12_B2 R6 DDR2_DIMM_LB_BK18 W10 DDR2_DIMM_DQ_BY12_B3 K6 DDR2_DIMM_L
42. R33 QDR2_D_BY3_B1 P29 QDR2_D_BY6_B6 R34 QDR2_D_BY3_B2 N29 QDR2_D_BY6_B7 T33 QDR2_D_BY3_B3 M30 QDR2_D_BY6_B8 N32 QDR2_D_BY3_B4 L30 QDR2_D_BY7_B0 T25 ODR2_D_BY3_B5 J31 ODR2 D BY7 P1 U25 ODR2 D BY3 B6 J30 ODR2_D_BY7_B2 126 ODR2 D BY3 B7 G31 ODR2 D BY7 U26 ODR2 D BY3 B8 H30 ODR2 D BY7 B4 R27 ODR2 D BY4 AG30 ODR2 D BY7 B5 R26 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 109 Appendix Pinouts Table A 3 FPGA 3 Pinout Continued 7 XILINX Signal Name Pin Signal Name Pin QDRII Memory Interface cont QDR2 D BY7 B6 U28 QDR2 Q BY3 B2 G27 QDR2 D BY7 B7 U27 QDR2 Q BY3 B3 F26 QDR2 D BY7 B8 T29 QDR2 Q BY3 B4 F25 QDR2 BYO BO QDR2 B5 24 ODR2_Q BYO B1 H34 QDR2 Q B6 H25 QDR2 0 B2 H33 QDR2 Q BY3 B7 G26 ODR2 BYO B3 J32 ODR2 Q B8 G25 QDR2 BYO_B4 F34 QDR2 BY4 AP32 ODR2 O BYO B5 G33 ODR2 Q AN32 ODR2 BYO B6 E33 ODR2 Q 4 B2 AN33 QDR2 BYO0 B7 E32 QDR2 BYA B3 AN34 QDR2 BYO B8 E34 QDR2 BYA B4 AM32 QDR2 1 BO T24 QDR2 4 B5 AM33 QDR2 1 B1 R24 QDR2 4 B6 AL33 QDR2 1 B2 N25 QDR2 4 B7 AL34 ODR2_Q BY1_B3 P25 QDR2 4 B8 AK32 QDR2 Q 1 B4 24 QDR2 BY5 4 ODR2 BY1_B5 N24 ODR2 Q AE33 QDR2 1 27 QDR2 BY5 B2 AF33 QDR2
43. Signal Name Pin Signal Name Pin DDR2 DIMM Deep Interface cont DDR2 DIMM3 CK2 P AA25 DDR2 DIMM BYO R27 DDR2 DIMM3 CKEO A E28 DDR2 DIMM DOQ BYO B5 R26 DDR2 DIMM3 CKE1 AH28 DDR2 DIMM DQ BYO B6 U28 DDR2 DIMM3 CS0 N W25 DDR2 DO BYO B7 U27 DDR2 DIMM3 V25 DDR2 DIMM IN29 DDR2 DIMM3 ODTO AB26 DDR2 BYI1 M30 DDR2 DIMM3 ODTI1 AB25 DDR2 DIMM B2 L30 DDR2 DIMMA AK9 DDR2_DIMM_DQ_BY1_B3 J31 DDR2_DIMM4_CKO_P AK8 DDR2_DIMM_DQ_BY1_B4 J30 DDR2 DIMMA DDR2_DIMM_DQ_BY1_B5 G31 DDR2_DIMM4_CK1_ DDR2_DIMM_DQ_BY1_B6 H30 DDR2 DIMMA CK2 DDR2_DIMM_DQ_BY1_B7 L29 DDR2_DIMM4_CK2_P AD10 DDR2_DIMM_DQ_BY2_B0 E31 DDR2_DIMM4_CKEO AG11 DDR2_DIMM_DQ BY2 F31 DDR2_DIMM4_CKE1 AG10 DDR2 DIMM BY2 B2 129 DDR2 DIMMA CS0 N W26 DDR2 DIMM BY2 H29 DDR2 DIMMA CS1 N Y26 DDR2 DIMM BY2 F30 DDR2 DIMMA 11 DDR2 DIMM DOQ BY2 B5 G30 DDR2_DIMM4_ODT1 AF11 DDR2_DIMM_DQ_BY2_B6 F29 DDR2 DIMM DM BYO U30 DDR2 DIMM BY2 B7 E29 DDR2 DIMM DM 1 R31 DDR2 DIMM 132 DDR2_DIMM_DM_BY2 T31 DDR2_DIMM_DQ_BY3_B1 4 DDR2_DIMM_DM_BY3 L33 DDR2_DIMM_DQ_BY3_B2 G33 DDR2_DIMM_DM_BY4 AK34 DDR2_DIMM_DQ_BY3_B3 E33 DDR2 DIMM DM BY5 AG32 DDR2_DIMM_DQ_BY3_B4 2 DDR2_DIMM_DM_BY6 P34 DDR2_DIMM_DQ_BY3_B5 E34 DDR2 DIMM DM BY7 AK33 DDR2 DIMM F33 DDR2 DIMM DM 7 M32 DDR2 DIMM B7 G32 DDR2 DIMM BYO
44. VTT Power Plane 0 9V Layer 7 SSTL2 VREF Power Plane 1 3V Layer 7 SSIL2 VTT Power Plane 1 3V 92 7 42 Each of the three Fairchild FN6555 Bus Terminator Regulators has two voltage outputs one each for and VT The FN6555 regulator is a push pull device rated at for the output and 3 mA for the output Because the voltage is used by the FPGA and memory devices only as reference the power supply does not source any real current Thus the mA capacity for the Vpgp output is considered sufficient The voltage is guaranteed to within 20 mV of the output by the FN6555 regulator minimum driver output voltage swing around is specified for the SSTL18 SSTL2 and HSTL I O standards as e SSIL2 608 mV SSTL18 603 mV 500 mV for HSTL18 For a given memory interface the maximum number of single ended non differential signals that might need to be pulled up or down at a time for QDRII is 144 data bits and approximately 30 address and control signals The differential pair signals offset for the sink and source of current With a continuous current capacity of 3A for the FN6555 regulator the regulator can supply up to 3000 175 17 mA of current per signal The maximum drive strength for a driver is specified at 16 mA For 500 termination this www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008
45. are automatically increased Y7 Y6 Y5 Y4 Y2 Y1 Y0 Col 0 0 0 0 0 0 0 0 Addr 0 Col 0 0 0 0 0 0 0 1 Addr 1 Col 1 1 1 1 1 1 1 0 Addr 130 Col 1 1 1 1 1 1 1 1 Addr 131 Te 3 3 11 15 This instruction changes the relationship between RAM column address and segment driver ADC 0 SEG1 gt SEG132 default mode ADC 1 SEG132 gt SEG1 Virtex 5 FPGA ML561 User Guide www xilinx com 131 UG199 v1 2 April 19 2008 Appendix LCD Interface 57 XILINX Table C 6 Display Instructions Continued Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Reverse display ON OFF 0 0 1 0 1 0 0 1 1 REV REV RAM bit data 1 RAM bit data 0 0 Pixel Pixel OFF 1 Pixel OFF Pixel Entire display ON OFF 0 0 1 0 1 0 0 1 0 EON This instruction forces the display to be turned on regardless the contents of the display data RAM The contents of the display data RAM are saved This instruction has priority over reverse display LCD bias select 0 0 1 0 1 0 0 0 1 BIAS This instruction selects the LCD bias Duty Bias 0 Bias 1 ratio 1 65 177 1 9 Set modify read 0 0 1 1 1 0 0 0 0 0 This instruction stops the automatic incrementing of the column address by a read ope
46. be performed Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 129 Appendix LCD Interface XILINX Instruction Set Table C 6 shows the instruction set for the LCD panel Table C 6 Display Instructions Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Read display data 1 1 Read Data 8 bit data specified by the column and page address can be read from the Display Data RAM The column address is increased automatically thus data can be read continuously from the addressed page Write display data 1 0 Write Data 8 bit data can be written into RAM location specified by the column and page address The column address is increased automatically thus data can be written continuously to the addressed page Read status 0 1 BUSY ADC ONOFF RESETB 0 0 0 0 BUSY Device is BUSY when internal operation or reset 0 active 1 ADC Indicates the relationship between RAM column address and segment driver ONOFF Indicates display ON or OFF status RESETB Indicates if initialization is in progress Display ON OFF 0 0 1 0 1 0 1 1 1 DON Turn display ON or OFF 1 ON 0 OFF Initial display line 0 0 0 1 ST5 914 ST3 ST2 ST1 STO Sets the line address of the display RAM to determine the initial line of the LCD panel
47. board uses 5V to drive numerous voltage regulators Figure 3 9 shows a general overview of the power distribution system 070 Devices Slide 3 3 Switch Power 12V o o 12V V FPGA Power To All FPGAs Slide F VccAUx Vcco Switch FPGA Power To FPGAs SSTL18 HSTL or SSTL2 To Memories Memory Power SSTL18 HSTL or SSTL2 VTT VREF 00199 3 09 050106 Figure 3 9 Virtex 5 FPGA ML561 Development Board Power Distribution System The Virtex 5 FPGA ML561 Development Board is powered through the 5V input jack 028 from the power supply included in the ML561 Tool Kit Alternatively the 5V can Virtex 5 FPGA ML561 User Guide www xilinx com 33 UG199 v1 2 April 19 2008 34 Chapter 3 Hardware Description XILINX also be supplied from bench supply using the two banana jacks J25 RED for 5V and J24 BLACK for GND Rev A assembly of the Virtex 5 FPGA ML561 Development Board does not support the 12V input via jack J23 or via banana jacks J18 RED for 12V and J17 BLACK for GND The memory and FPGAs use separate power supplies for SSTL18 HSTL and SSTL2 respectively Thus the power being consumed can be easily measured for each using the power measurement header provided on the 561 Voltage Regulators TRACK VMARGIN_DN_xxxx_N VMARGIN_UP_xxxx_N 5V The 5V voltage source is supplied as input to nine on board regulator modul
48. check button in the top toolbar Warnings are okay Open the 1136_5v1x50t pkg file using a text editor and locate the Define Package Model line Copy and paste this lineintothem1561 fpga3 u34 ibs file just above the line with the Package declaration Edit the copied line to change Define Package Model to Package Model Again check the file for correctness by clicking the check button in the top toolbar Multiple errors will appear The package model file defines I O definitions for all usable pins but now ibiswriter only declares pins defined under the UCF Thus errors are displayed for all the undefined pins for example ERROR Pin AK9 found in Package Model 1136 xc5vlx50t foea0106 Pin Numbers list not found in Component VIRTEX 5 Pin list Copy all these errors into a text file with a txt file type Open this text file with Excel and provide the delimiter as 9 which puts all the unused pin names in one column Delete all other columns before and after the one with the pin names In column 2 fill in IO for all pins Incolumn 3 in the name of one of the I O standards defined under the Model section of the m1561_fpga3_u34 ibs file for example LVCMOS25 5 12 Choose a name that is not an output only standard because it might conflict with other outputs in the same bank Right justify the indentation for all three columns and make sure that each column is
49. convention Typographical This document uses the following typographical conventions An example illustrates each convention Convention Italic font Underlined Text Meaning or Use References to other documents Example See the Virtex 5 Configuration Guide for more information Emphasis in text Indicates a link to a web page The address F is asserted after clock event 2 http www xilinx com virtex5 Online Document The following conventions are used in this document Convention Blue text Red text Terminology Blue underlined text Meaning or Use Cross reference link to a location in the current document Cross reference link to a location in another document Hyperlink to a website URL Example See the section Additional Documentation for details Refer to Clock Management Technology CMT in Chapter 2 for details See Figure 5 in the Virtex 5 FPGA Data Sheet Go to http www xilinx com for the latest documentation This section defines terms used in Chapter 7 561 Hardware Simulation Correlation of this document DVW is the data valid window opening measured by the VIH and VIL masks The Data Valid Window DVW of UI Unit Interval or bit time smaller of the two values are listed as absolute time as well as in terms of the percentage The ultimate goal of a design is to ascertain quality of signal at
50. depopulated on the ML561 board when DCI termination is implemented inside FPGA for received data Due to non fly by termination topology the result is a minimal stub for the signal thus preserving good signal integrity for read data 36 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Board Design Considerations For Write data and terminations at the memory if the trace length from the receiver pin to the termination resistor can be guaranteed to be within 0 3 inches then the tly by termination scheme is implemented Otherwise the non fly by termination topology is implemented for Write data at the memory end The physical dimensions of the raw PCB are 12 75 inches x 11 75 inches With the overhangs due to edge connectors the actual size of the fully assembled board is approximately 13 inches x 12 inches with 1 5 inches height allowance for the DIMM modules This 14 layer board has 6 signal layers 4 GND layers and 4 power planes and uses Polyclad 370HR material for lead free assembly Figure 3 11 shows a stack up diagram of the ML561 Revision A PCB Refer to UG203 Virtex 5 PCB Designer s Guide for more information on the PCB design using Virtex 5 devices 1 0 TOP 20 50Q width 6 mils 1 0 02 GND1 0 5 oz 03 Zo 500 width 4 5 mils cc C G 1 0 oz 04_PWR1 ZZ 0 5 oz 05_INR2 Zo 500 width 4 5 mils ZZ 1 0 oz 06_GND2 1 0 oz 07 PWR2 739
51. is to establish correlation between hardware measurements and the simulation at the probe point The intention was to validate the simulation model for the targeted signal The degree of correlation achieved is looked at in terms of absolute difference as well as relative percentage The relative percentage differences are presented in terms of unit interval UI for timing characteristics and in terms of VREF voltage for the voltage margin characteristics Correlation simulation is performed under ideal conditions that is the stimulus is generated without any jitter On the other hand the hardware measurements are subject to jitter which tends to increase ISI board level power fluctuation which can affect the eye amplitude and stability of the probing station Thus some correlation differences are expected The user ultimately uses his or her own judgment to account for these differences and adjusts the values extrapolated for quality of signal at the receiver IOB Table 7 15 contains this information for all six test signals Table 7 15 Summary of Correlation Differences Hardware vs Simulation Overshoot i ADVW AISI Noise Margin Operation Undershoot Margin UI Ul VREF 40 ps 47 ps 98 mV 69 mV DDR2 Component Write 2 6 3 2 10 9 7 6 0 6 mV 244 mV DDR2 Component Read ON P m w 0 2 9 0 7 17 2 218 ps 366 ps 112 mV 2 mV DDR2 DIMM
52. later revisions of this board Virtex 5 FPGA ML561 User Guide WWW xilinx com 11 UG199 v1 2 April 19 2008 Chapter 1 Introduction XILINX Virtex 5 FPGA ML561 Memory Interfaces Development Board A high level functional block diagram of the Virtex 5 ML561 Memory Interfaces Development Board is shown in Figure 1 1 External Interfaces System ACE Controller USB RS 232 LCD SSTL18 SSTL2 SSTL18 FPGA 1 FPGA 2 FPGA 3 XC5VLX50T XC5VLX50T XC5VLX50T FFG1136 FFG1136 FFG1136 QDRII SRAM DDR400 SDRAM DDR2 DIMM DDR2 DIMM DDR2 DIMM DDR2 DIMM DDR2 DIMM RLDRAM II CIO DDR2 SDRAM WIDE gt DEEP UG191_c1_01_020807 Figure 1 1 Virtex 5 FPGA ML561 Development Board Block Diagram The Virtex 5 FPGA ML561 Development Board includes the following major functional blocks Three XC5VLX50T FFG1136 FPGAs see 05100 Virtex 5 Family Overview e DDR400 components 128 MB 32M x 32 bits at 200 MHz clock speed See XAPP851 DDR SDRAM Controller Using Virtex 5 FPGA Devices e DDR2 DIMM Five PC2 5300 DIMM sockets for up to 2 GB 128M x 144 bits See XAPP858 High Performance DDR2 SDRAM Interface in Virtex 5 Devices DDR2 667 components 64 MB 16M x 32 bits at 333 MHz clock speed ODRII memory 16 MB 2M x 72 bits at up to 300 MHz clock speed See XAPP853 ODR II SRAM Interface for Virtex 5 Devices RLDRAM II memory 64 MB 16M x 36 bits at up to 300 MHz clock speed
53. perform hardware measurements for a Read operation that is not interrupted by a Write a Refresh operation the testbench on FPGAT is controlled by the following DIP switch SW1 setting DIP 1 2 2 b10 Write once then Read only Refresh disabled 76 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 7 XILINX Signal Integrity Correlation Results UG199_c7_31_071107 Figure 7 31 DDR2 DIMM Read HW Measurement Eye Scope Shot at Probe Point FPGA1 Via Voltage mV 9 9 9 9 1700 0 i 1500 0 A V I j TE AM _ Ad 1300 0 1100 0 m N BN b V 900 0 a p 700 0 L DS 500 0 Z um Th NN 4 N sss wA 100 0 100 0 2000 0 2400 0 2800 0 3200 0 3600 0 Time ps UG199_c7_32_071107 333 MHz Slow PRBS6 59 UI Cursor 1 1 0988V 2 5207 ns Cursor 2 1 0254V 3 3859 ns Delta Voltage 73 4 mV Delta Time 865 2 ps 59 UI Figure 7 32 DDR2 DIMM Read Correlation Eye Scope Shot at Probe Point Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation 57 XILINX 5 eje 5 00 ns 06199 7 33 071107 Figure 7 33 DDR2 DIMM Read HW Measurement Waveform Scope Shot at Probe Point FPGA1 Via Litt ty yt
54. 0 2750 1951 Number of Flip flops 2000 2000 7352 2000 1800 Number of Shift Register LUTs 50 50 143 750 400 Number of Block RAMs 5 5 17 14 21 Number of DCMs 2 2 2 2 Inputs 10 10 10 90 13 Outputs 50 50 90 160 92 Bidirectionals 36 40 192 0 36 Ambient Temperature C 25 25 25 25 25 Airflow LFM 0 0 250 250 0 Heat Sink Theta J n a n a 5 5 n a Junction Temperature C 67 60 78 58 76 Notes 1 For DDR2 DIMMs as well as QDRII memory interfaces with DCI MD35E 10B heat sink is needed A heat sink with Theta J 5 0 should be okay without airflow See http www alphanovatech com c md35e html for the heat sink profile A heat sink with Theta J 5 0 might need airflow of 250 LFM 46 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 5 Signal Integrity Recommendations Termination and Transmission Line Summaries The following are common recommendations for the signal termination scheme to all external memories implemented on the Virtex 5 FPGA ML561 Development Board Single ended signals Simulation indicates that for a single ended signal there is no significant performance difference for signal with split termination of 1000 1000 between Vpp and GND versus the Vyr termination of 50Qto the Vpgp voltage Because the power consumption for the split termination is considerably higher than the termination for the SSTL2 551118 I O s
55. 0 7mis 33misEr 44 1 0 oz 08 PWR3 1 0 oz 09 GND3 2 0 5 oz 10 5 Zo 500 width 4 5 mils 777777777777777777777777777777777777777777777777777777777 1 0 7 1 1 Z 0 5 oz 12 6 Zo 500 width 4 5 mils 1 0 oz 13 GND4 2 Yt 1 0 BOTTOM Zo 500 6 mils 199 c3 11 102407 Figure 3 11 ML561 Revision Stack Up Virtex 5 FPGA ML561 User Guide www xilinx com 37 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description XILINX Table 3 19 ML561 Revision PCB Controlled Impedance Table 3 19 shows the details of the dielectric material and construction for each layer and the controlled impedance values for the signal layers Layer Cu Substrate Test 2 eq Usage Weight Thickness Er Width ohms Comment mils mils 1 TOP Metal Signal 1 0 lt Auto gt 6 50 5 Microstrip Signal Top 2 Dielectric Substrate 3 8 4 4 3 02_GND1 Metal Plane 1 0 lt Auto gt Ground Plane 1 4 Dielectric Substrate 4 4 4 5 03 Metal Signal 0 5 lt Auto gt 4 5 50 5 Stripline Signal Inner 1 6 Dielectric Substrate 4 4 7 04 PWR1 Metal Plane 1 0 lt Auto gt Split Power Plane 1 8 Dielectric Substrate 8 4 4 9 05_INR2 Metal Signal 0 5 lt Auto gt 4 5 50 5 Stripline Si
56. 0 9V Read Data Q HSTL I DCI 18 No termination No termination Write Strobe K K HSTL I 18 No termination 50Q pull up to 0 9V Read Strobe CQ CQ HSTL I DCI 18 No termination No termination Clock CK CK HSTL I 18 No termination 1000 differential termination between pair Address A BA HSIL 18 No termination 50 pull up to 0 9V after the last component Control RAS CAS WE HSTL I 18 No termination 500 pull up to 0 9V after the last CS CKE and BW component Table 5 5 RLDRAM Terminations Signal FPGA Driver Termination at FPGA Termination at Memory Data DQ for CIO HSTL DCI 18 No termination 50Q pull up to 0 9V Data Q for SIO HSTL I DCI 18 No termination No termination Write Data D for SIO HSIL I 18 No termination 50Q pull up to 0 9V Write Strobe DK DK DIFF HSIL I 18 No termination 1000 differential termination between pair Read Strobe OK OK DIFF HSTL II DCI 18 for CIO No termination No termination DIFF 18 for SIO Data Valid OVLD 18 for CIO No termination No termination HSTL I DCI 18 for SIO Clock CK CK DIFF HSTL I 18 No termination 1000 differential termination between pair Address A BA HSIL I 18 No termination 50 pull up to 0 9V after the last component Control RAS CAS WE HSTL I 18 No termination 50Qpull up to 0 9V after the last CS and CKE component Virtex 5 FPGA ML561 User Guide U
57. 00 0 1600 0 fo SA WE 5 M M 1100 0 M 600 0 100 0 19005 A 800 0 1200 0 1600 0 2000 0 2400 0 2800 0 Time ps UG199_c7_46_070907 300 MHz Fast PRBS6 89 UI Cursor 1 699 1 m V 1 1440 ns Cursor 2 801 0 mV 2 6334 ns Delta Voltage 101 9 mV Delta Time 1 4894 ns 89 UI Figure 7 46 QDRII Write Extrapolation Eye Scope Shot at Receiver Fast Corner Voltage mV 2900 0 SF 2400 0 AH _ e 600 0 1100 0 1600 0 110 000 120 000 130 000 140 000 150 000 160 000 Time ns UG199_c7_47_070907 Figure 7 47 QDRII Write Extrapolation Waveform Scope Shot at Receiver Fast Corner Virtex 5 FPGA ML561 User Guide www xilinx com 85 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation QDRII Read Operation XILINX This subsection shows the test results for the 2 5 signal from ODRII memory U35 to FPGA3 1 34 measured at 300 MHz 600 Mb s where the unit interval UI 1 67 ns 28 5 ohms 49 1 ohms 49 1 ohms 28 5 ohms 4 473 ps 71 6 ohms 95 834 ps 427 654 ps 71 8 ohms 4 404 ps U34 G33 0 028 in 22 319 ps 0 613 in 2 737 in 22 319 ps 0 027 in QDR2 Q BYO B5 AutoPadstk 3 QDR2 Q BYO B5 QDR2 BYO B5 AutoPad QDR2 BYO B5 4 r4 CO HO TL1 TL2 TL3 TL6 TL7 TL8 Virtex 5 FPGA QDR2_Q_BY0_B5 QDR2_Q
58. 1 0 20 7 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 81 Chapter 7 ML561 Hardware Simulation Correlation UG199_c7_40_071107 XILINX Figure 7 40 QDRII Write HW Measurement Eye Scope Shot at Probe Point QDRII Memory Via Voltage mV Figure 7 41 82 9 1800 0 1600 0 1400 os UA N M 800 0 7 S 2 NC my AN LLL LZ DS BURN 200 0 0 000 mil Probe 3 gt Probe 3 7 1 at pin 1 at gt Probe 3 7 1 at pin re 0 000 400 0 800 0 1200 0 1600 0 Time ps 300 MHz Slow PRBS6 83 5 UI Cursor 1 699 1 mV 90 0 ps Cursor 2 801 0 mV 1 4770 ns Delta Voltage 101 9 mV Delta Time 1 3870 ns 83 5 UI UG199 c7 41 070907 QDRII Write Correlation Eye Scope Shot at Probe Point Slow Corner www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results eje 5 00 06199 7 42 071107 Figure 7 42 QDRII Write HW Measurement Waveform Scope Shot at Probe Point QDRII Memory Via 1900 0 1700 0 1500 0 Tum LEA A Ld ba nl LEE LUI ULC 1100 0 PEE EE BH fp ss 700 0 l A Lh I 100 0 E quce 110 000 120 000 130 000 140 000 150 000 160 000 Time ns UG1
59. 1 data strobe ratio for the ODRII device DDR400 SDRAM Components The Virtex 5 FPGA ML561 Development Board has two 200 MHz Micron MT46V32M16BN 5B 16 bit DDR400 SDRAM components that provide a 32 bit interface Each 16 bit device is packaged in a 60 ball FBGA package with a common address and control bus and separate clocks and DQS DQ signals DDR2 DIMM The Virtex 5 FPGA ML561 Development Board contains five PC 5300 240 pin DIMM sockets for a maximum data width of 144 bits or a maximum depth of four DIMMs The sockets are arranged in a row leading away from the FPGA so they can share common address and control signals DIMMI through DIMM4 share DO DOS signals to form deep 72 bit memory interface while DIMMS has separate DO DOS signals For the deep DDR2 interface the sockets are to be populated starting at socket DIMMA Table 3 2 illustrates how the sockets should be populated based on the interface wanted Table 3 2 Populating DDR2 DIMM Sockets DIMM Interface DIMM Sockets Interface Width Populated Populating the DIMMs in this order is necessary due to the placement of the termination on the signals being shared More detail on termination is given in Board Design Considerations page 36 Virtex 5 FPGA ML561 User Guide www xilinx com 19 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description XILINX DQ and DQS BY0 BY7 CB0_7 DQ and DQS BY8 BY15 CB8_15 Address and Commands DIMM1 Control DIMM2 Con
60. 115 0 8 1 5853006 Data Sheet System ACE Controller 1 3 3 200 0 7 5080 System ACE CompactFlash Solution 200 MHz Oscillator 1 2 5 30 0 1 Epson EG2121CA Data Sheet 33 MHz Oscillator 2 3 3 45 0 3 Epson SG 8002CA Data Sheet Total Power Consumed 93 2 40 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Power Consumption Table 4 1 ML561 Power Consumption Continued Device Description Quantity Voltage V mn n Source Power Modules Capacity Power Plane 1 0V 1 1 00 15000 15 0 TI PTHO05010 15A Module Data Sheet HSTL FPGA Power Plane 1 8V 1 1 80 15000 27 0 HSTL Memory Power Plane 1 8V 1 1 80 6000 10 8 TI PTH05000 6A Module Data Sheet VREF Power Plane 0 9V 1 0 90 3000 2 7 Fairchild FN6555 Data Sheet SSTL18 FPGA Power Plane 1 8V 1 1 80 15000 27 0 TI PTH05010 15A Module Data Sheet SSTL18 Memory Power Plane 1 8V 1 1 80 6000 10 8 TI PTH05000 6A Module Data Sheet SSTL18 _VREF Power Plane 0 9V 1 0 90 3000 2 7 Fairchild FN6555 Data Sheet SSTL2 FPGA Power Plane 2 6V 1 2 60 15000 39 0 TI PTH05010 15A Module Data Sheet SSTL2 Memory Power Plane 2 6V 1 2 60 6000 15 6 TI PTH05000 6A Module Data Sheet SSTL2 _VREF Power Plane 1 3V 1 1 30 3000 3 9 Fairchild FN6555 Data Sheet 2 5V Power Plane 1 2 50 15000 37 5 TI PTH05010 15A Module Data Sheet 3 3V Power Plane 1 3 30 15000 49 5 12
61. 2 SSTL18 VR1 VMARGIN_UP_SSTL18_N P4 1 gt 2 VMARGIN_DN_SSTL18_N P4 3 gt 2 SSTL2 VR9 VMARGIN_UP_SSTL2_N P450 1 gt 2 VMARGIN_DN_SSTL2_N P50 3 gt 2 HSTL VR10 VMARGIN_UP_HSTL_N P58 1 gt 2 VMARGIN_DN_HSTL_N P58 3 gt 2 VccAux VR12 VMARGIN_UP_VCC2V5_N P69 1 gt 2 VMARGIN_DN_VCC2V5_N P69 3 gt 2 The TI PTH05010 WAZ and TI PTH05000 ADJ regulator outputs can be enabled or inhibited through the use of on board two pin jumpers The inhibit jumpers use the following conventions e Jumper OFF Enabled e Jumper ON Inhibited Virtex 5 FPGA ML561 User Guide www xilinx com 35 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description XILINX Table 3 18 summarizes the inhibit headers Table 3 18 Headers for Voltage Regulator Inhibition Power Regulator Inhibit Header VR6 P63 SSTL18 1 11 SSTL18_M VR4 P32 SSTL2 VR9 P68 SSTL2_M VR2 P5 HSTL VR10 P74 HSTL_M VR14 105 VccAUx VR12 79 VCC3V3 VR13 P101 Board Design Considerations UG086 Memory Interface Generator MIG User Guide includes PCB implementation rules and guidelines to be followed for designing a board for a MIG reference design The Virtex 5 FPGA ML561 Development Board design allows implementation of DCI termination scheme at the FPGA for each of the memory interfaces on the board A preliminary analysis of the Weighted Average Simultaneously Switching Outputs WASSO f
62. 2 BO U31 DDR1 DOS BYO P AD32 DDR1 DOQ BY2 U32 DDR1 DOS 1 P AF33 DDR1 BY2 B2 T34 DDR1_DQS_BY2_P K33 DDR1_DQ_BY2_B3 U33 DDR1 DOS P 2 DDR2 Component Interface DDR2_A0 K12 DDR2_CAS_N J14 DDR2_A1 K13 DDR2_CKO_N K19 DDR2_A10 G22 DDR2 P L19 DDR2 A11 J15 DDR2 CK1 9 DDR2_A12 K16 DDR2 CK1 P K18 DDR2 A2 H23 DDR2 CKE K17 DDR2 A3 523 DDR2_CSO_N H20 DDR2_A4 12 DDR2_CS1_N H19 DDR2_A5 J12 DDR2_LB_BK15 T28 DDR2_A6 K22 DDR2_LB_BK15 129 DDR2 A7 K23 DDR2 LB 19 M28 DDR2 8 K14 DDR2 LB 19 N28 DDR2 A9 L14 DDR2 ODTO H18 DDR2 BAO K21 DDR2_ODT1 H17 DDR2_BA1 122 DDR2_RAS_N H13 96 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table 1 FPGA 1 Pinout Continued FPGA 1 Pinout Signal Name Pin Signal Name Pin DDR2 Component Interface cont DDR2_WE_N J21 DDR2_DQ_BY2_B2 N25 DDR2 DM BYO U30 DDR2 BY2 B3 P25 DDR2_DM_BY1 L29 DDR2_DQ_BY2_B4 P24 DDR2_DM_BY2 K27 DDR2_DQ_BY2_B5 N24 DDR2_DM_BY3 J27 DDR2_DQ_BY2_B6 P27 DDR2 BYO BO 125 DDR2 BY2 B7 26 DDR2_DO BYO B1 U25 DDR2 BO M26 DDR2 BYO B2 126 DDR2 M25 DDR2 BYO B3 U26 DDR2 B2 J25 DDR2 BYO B4 R27 DDR2 B3 J24 DDR2 DQ BYO B5 R26 DDR2 B4 L26 DDR2 BYO U28 DDR2 B5 L25 DDR2 BYO B7 U27 DDR2_DQ_BY3_B6 L24 DDR2_DQ_BY1_B0 E31 DDR2_DQ_BY3_B7 K24 DDR2_DQ_BY1
63. 2 D BYO B5 0 Wc L TL2 TL4 TL5 TL7 TL8 TL3 TL1 K7R323684M_1 8V Virtex 5 FPGA D5 QDR2_D_BY0_B5 2d QDR2 D C7 QDR2 D QDR2 QDR2 D QDR2 D QDR2 D 22 9 fF 22 9 fF 22 9 fF 500 0 fF 399 1 fF 177 3 fF 58 1 fF UG199 c7 39 070907 Figure 7 39 Post Layout IBIS Schematics of QDRII Write Data Bit QDR2 D BYO B5 Table 7 11 Circuit Elements of QDRII Write Data bit QDR2 D BYO B5 Element Designation Description Driver U34 M31 FPGA HSTL I 18 Receiver U35 G11 ODRII memory Probe Point C7 Via under Memory Termination 1586 External termination at memory Trace Length TL 2 5 8 41 3 46 inches Table 7 12 QDRII Write Operation Correlation Results Noise Margin Overshoot Undershoot Measurement CUP VIL Total Margin i of VREF of VREF Hardware at probe 1 40 ns 340 400 740 450 400 850 mV point pni u s s 82 2 94 5 Simulation correlation 1 39 ns 344 398 742 mV 483 452 2 935 mV slow weak corner 83 5 82 5 103 9 Correlation Delta 10 5 HW vs Simulation 0 6 107 ps 6 4 2 mV 0 3 85 mV 9 4 Extrapolation at IOB 1 38 ns 172 141 313 ps 329 358 687 mV 400 361 761 mV slow weak corner 83 18 8 76 3 84 5 Extrapolation at IOB 1 49 ns a 353 376 729 mV 156 30 186 mV 8995 126 91 217 ps 13 0 8
64. 4 fF R2 D R6 0 0 milliohms TL13 E E TL26 TL22 TL24 50 3 ohms 23 650 5 50 3 ohms 50 3 ohms 0019 23 650 5 23 650 C 50 3 ohms DQ19 DQ19 B 23 650 ps DQ19 06199 c7 30 071907 Figure 7 30 Post Layout IBIS Schematics of the DDR2 DIMM Read Data Bit DDR2 DIMM DQ B Table 7 9 Circuit Elements of DDR2 DIMM Read Data Bit DDR2 DIMM DQ BY2 B3 Element Designation Description Driver XP2 U3 J1 DDR2 DIMM Receiver U5 H29 FPGA 551118 II I Probe Point C8 Via under FPGA2 U5 H29 PCB Termination None DCI at load Trace Length Multiple TLs 8 975 inches Table 7 10 DDR2 DIMM Read Operation Correlation Results DVW ISI Noise Margin Overshoot Undershoot Measurement Ul UI VIL Total of VREF of VREF Hardware at probe 204 ps 107 62 169 ps 623 613 1236 mV point 60 11 2 137 396 Simulation correlation 865 ps 130 83 213 ps 524 504 1028 slow weak corner 59 14 2 114 2 Correlation Delta 39 ps HW vs Simulation 2 6 44 ps 2 9 90 mV 10 208 mV 23 1 Extrapolation at IOB 1 23 ns 139 75 224 ps 243 303 546 mV 594 544 1138 mV slow weak corner 82 14 9 60 7 116 5 Extrapolation at IOB 1 24 ns 131 60 191 ps 288 282 570 mV 481 508 989 mV fast strong corner 83 12 7 63 3 109 9 To
65. 5 FPGA2_TXN1_BK120 D2 FPGA2_USB_DSR_N K16 FPGA2 BK120 2 USB J15 FPGA2 TXP1 BK120 E2 FPGA2 USB RST N L21 FPGA2 RS232 CTS K14 FPGA2 USB RIS N L16 FPGA2 RS232 RIS L14 FPGA2 USB RX J22 FPGA2 RS232 RX G22 FPGA2 USB SUSPEND L20 FPGA2 RS232 TX H22 FPGA2 USB TX K21 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 107 Appendix Pinouts FPGA 3 Pinout Table A 3 lists the connections for FPGA 3 U34 Table 3 FPGA 3 Pinout 7 XILINX Signal Name Pin Signal Name Pin QDRII Memory Interface ODR2 CK BYO 3 N K34 ODR2 SA11 26 ODR2 CK BYO 3 P 528 ODR2_SA12 AB25 ODR2 CK BYO 3 P L34 ODR2 5413 AA24 ODR2 CK BY4 7 AJ34 ODR2 SA14 Y24 ODR2 4 7 P 1 ODR2_SA15 AC27 ODR2 CK 4 7 AH34 ODR2 SA16 AB27 ODR2 CO BYO 3 N E26 ODR2 5417 AA26 QDR2 BYO 3 K33 QDR2 SA2 AJ27 ODR2 4 7 AA29 ODR2_SA3 AK26 ODR2 4 7 AD32 ODR2 SA4 AF28 ODR2 DLL OFF N AK27 ODR2 545 AE28 ODR2 K BYO 3 N F28 ODR2 SA6 AH28 ODR2 K BYO 3 P E28 ODR2 SA7 AG28 ODR2_K_BY4_7_N AC30 ODR2 SAS8 A A28 ODR2 BY4 7 P 0 ODR2 SA9 28 ODR2 LB BK11 P32 QDR2_W_N AH27 QDR2_LB_BK11 P34 ODR2 BW BYO N M32 ODR2 LB BK13 AE34 ODR2 BW BY1 N L33 ODR2 LB BK13 AJ32 ODR2 BW BY2 N L28 ODR2 LB 17 A E29 ODR2 BW BY3 N K28 ODR2 LB 17 AF31 ODR2 BW 4 AK33 ODR2 LB
66. 5 FPGA ML561 Development Board provides connector 114 that can be used to program the Virtex 5 FPGAs and program and or configure other devices in the chain Parallel Cable Port The Virtex 5 FPGA ML561 Development Board provides a Parallel Cable connector P64 to configure the Virtex 5 FPGAs and program JTAG devices located in the JTAG chain System ACE Interface 52 The Virtex 5 FPGA ML561 Development Board provides a System ACE interface to configure the Virtex 5 FPGA The interface also gives software designers the ability to run code for soft processor IP within the FPGA from removable CompactFlash cards Refer to the DS080 System ACE CompactFlash Solution for detailed information on creating System ACE compatible ACE files formatting the CompactFlash card and storing multiple design images www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX System ACE Interface Table 6 2 shows the System ACE interface signal names descriptions and pin assignments Table 6 2 System ACE Interface Signal Descriptions System ACE Pin Number Signal Name 70 SYSACE 69 SYSACE MPA1 68 SYSACE 2 67 SYSACE 45 SYSACE 4 44 SYSACE_MPA5 43 SYSACE_MPA6 66 SYSACE MPDO 65 SYSACE MPD1 63 SYSACE MPD2 62 SYSACE MPD3 61 SYSACE 60 SYSACE MPD5 59 SYSACE MPD6 58 SYSACE MP
67. 5 ns 49 8 ohms 94 605 ps 0 606 in DDR2 DIMM 59 80hms 59 8 ohms 59 8 ohms 3 590 ps 31 503 ps 195i 59 8 ohms 78 962 ps 10 373 ps 0 490 i 0 06 49 8 ohms 49 8 ohms 49 8 ohms 864 365 ps 90 955 ps 90 340 ps 0 582 in 0 578 in 5 533 in DDR2 DIMM DDR2 DIMM DQ ppR2 DIMM 7 XILINX 49 1 ohms 49 1 ohms 28 5 ohms 59 1 ohms 78 216 ps 41 316 ps 71 6 ohms 4 473 ps 12 486 ps 22 319 0 501 0 264 s ps 05 00 29 AutoPadstk 12 DDR2_DIMM_DQ_ DDR2_DIMM_DQ_ AutoPadstk 3 0 028 in DDR2 DIMM 4 0 022 in 490 064 B01 31 B01 J1 MDQ19 01 MDQ19 01 MDQ19 01 RN6 BO 0019 01 gt TL15 TL16 TL17 TL18 TL19 TL20 TL7 TL6 d E C die 2 B00 31 XP3_B00 31 4 00 31 DDR2_DQ_BY2_B3 TL1 TL5 TL11 22 0 ohms TL12 lt 47 64 8 2222 BORADI DDR2_Dl d 4 M d DDR2 DI DDR2 DI x C8 MDQ19 C13 222 QE CO gt gt CO 99 22 9 fF 50 3 ohms g 50 3 ohms ll 50 3 ohms i 50 3 ohms 253 0 fF 46 4 fF 96 3 fF 999 fF 23 650 ps 23 650 ps 23 650 ps 23 650 ps 17 3 fF 500 0 fF DDR2 D DDR2 DDR2_D DDR2_D R_00179 R7 R5 R6 0 0 milliohms 0 0 milliohms 0 0 milliohms 0 0 milliohms TL13 1126 a TL22 TL24 50 3 ohms C 1D 23 650 ps 50 3 ohms 50 3 ohms a ee 199 7 21 071907 Figure 7 21 Post Layout IBIS Schematics of DDR2 DIMM Write Data Bit DD
68. 57 XILINX Power Consumption current can support a voltage swing of up to 16 mA 500 800 mV which is sufficient to meet the output voltage specifications for SSTL18 SSTL2 and HSTL18 I O standards Table 4 3 separates the power consumption information from Table 4 1 according to the nine TI power modules for the first set of nine power planes and the three Fairchild regulators for the power planes The positive values in the Excess Power column of Table 4 3 show that each of the 14 modules can supply the necessary power for the corresponding power plane Table 4 3 ML561 Power Plane Capacities FPGA 2 DDR2 DIMM Voltage Current Power bs Device Description Quantity 9 Source W W W Total Available Power 5V Power Supply 1 5 0 8000 40 0 Bellus Power SPD 050 5 12V Power Supply 1 12 0 5000 60 0 CUI DTS120500U Power Consumed by Power Plane XC5VLX50T FFG1136 FPGA 1 Xilinx Power Estimator DDR400 DDR2 1 1 0 2289 20 XC5VLX50T FFG1136 FPGA 2 Xilinx Power Estimator DDR2 DIMM 1 1 0 1945 1 9 XC5VLX50T FFG1136 FPGA 3 1 10 2675 27 Xilinx Power Estimator ODRII RLDRAM II Power Plane 1 0V Capacity 1 L0 15000 150 81 5010 15A Module Data Sheet XC5VLX50T FFG1136 FPGA 3 1 18 3876 70 Xilinx Power Estimator ODRII and RLDRAM II HSTL FPGA Pow
69. 7_03_071907 Figure 7 3 Post Layout IBIS Schematics of DDR2 Component Write Data Bit 0082 BY2 B3 Table 7 1 Circuit Elements of DDR2 Component Write Data Bit DDR2_DQ_BY2_B3 Element Designation Description Driver U7 P25 FPGA 551118 II 012 03 DDR2 Memory 75 2 ODT Probe Point C9 Via under the memory device PCB Termination None ODT75 at load Trace Length 2 4 9 6 1 3 37 inches Table 7 2 DDR2 Component Write Operation Correlation Results Notes 1 DVW Data Valid Window ISI Inter Symbol Interference Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com ISI Noise Margin Overshoot Undershoot Measurement Ul VIL Total Margin 9 of 95 VREF Hardware at probe 1 18 80 80 160 ps 274 384 658 mV 550 470 1020 m V point 78 7 10 7 73 1 113 3 Simulation correlation 122ns 77 36 113 ps 294 266 560 mV 461 490 951 mV slow weak corner 81 3 7 5 62 2 105 7 Correlation Delta 40 ps 47 ps 98 mV 69 mV HW vs Simulation 2 6 3 2 10 9 7 6 Extrapolation at IOB 1 27 ns 91 36 127 ps 300 270 570 mV 469 501 2 970 mV slow weak corner 84 8 5 63 396 107 8 Extrapolation at IOB 1 39 ns 34 20 54 ps 406 351 757 mV 304 381 685 mV fast strong corner 92 3 7 84 1 76 1
70. 8 bit DBO DB7 LCD interface Therefore the 65 bit rows are split into eight pages of eight lines The ninth page is a single line page DBO only Interface designs can read from or write to the RAM array The display page is changed through the 4 bit page address register The column address line address is set with a two byte register access The line address corresponds to the first line that is going to be displayed on the LCD panel This address is located in a 6 bit address register The RAM array is configured such that there are two characters per row page where each character pair uses eight rows of the display panel Table C 2 shows the input data bytes address lines ADC control and LCD outputs segments DB3 DB2 DB1 Data us N DBO mM 00H DB1 01H DB2 a 02H DB3 B 03H 0 0 0 0 Page 0 DB4 B 04H DB5 E 05H B 06H DB7 07H DBO I 08H DB1 09H DB DB3 OBH 0 0 0 1 Page 1 DB4 0CH DB6 DB7 Virtex 5 FPGA ML561 User Guide www xilinx com 123 UG199 v1 2 April 19 2008 Appendix LCD Interface XILINX Table C 2 LCD Panel Continued
71. 99 c7 43 071007 Figure 7 43 QDRII Write Correlation Waveform Scope Shot at Probe Point Slow Corner Voltage mV Virtex 5 FPGA ML561 User Guide www xilinx com 83 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX Voltage mV 1800 0 gt ENS I 1400 0 SS Ww ss x L PON N m a Zr M 7 gt 200 0 PZ 222 ma 0 000 gt Probe 6 U35 G11 at die 0 000 400 0 800 0 1200 0 1600 0 Time ps UG199_c7_44_070907 300 MHz Slow PRBS6 83 UI Cursor 1 699 1 mV 61 3 ps Cursor 2 801 0 mV 1 4433 ns Delta Voltage 101 9 mV Delta Time 1 3820 ns 83 UI Figure 7 44 QDRII Write Extrapolation Eye Scope Shot at Receiver Slow Corner Voltage mV 1900 0 1700 0 HHHeHHHS 1500 0 1300 0 H 1100 0 900 0 700 0 500 0 AY LELLT UI Probe 6 U35 G11 at gt lt Probe 6 035 011 at die 100 0 r T T 110 000 120 000 130 000 140 000 150 000 160 000 Time ns UG199_c7_45_071007 Figure 7 45 QDRII Write Extrapolation Waveform Scope Shot at Receiver IOB Slow Corner 84 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results Voltage mV 9 9 9 9 3100 0 2600 0 21
72. A E Switch to character ROM Enable counters UG199_C_11_050106 Figure C 11 LCD Character Generator Controller A state machine manages the processing order A minimum cycle time ot 400 ns on the E signal used as a reference The 200 MHz system clock frequency is used as reference system clock One E cycle uses at least 80 system clock cycles when the design is running at 200 MHz The E pulse is part of the state machine and the design only depends on the system clock Timing is met as long as the system clock does not exceed 200 MHz This design can be adapted easily to fit the MicroBlaze or PPC405 CoreConnect bus system 138 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Hardware Schematic Diagram Array Connector Numbering Figure C 12 shows the LCD connections for Bank 0 Bank 0 LCD_DO LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_RST LCD_D1 LCD_D2 LCD_D3 LCD_ENA LCD_R W LCD RSEL LCD CS1B N G d AON C Connector J32 Figure C 12 LCD Connections Bank 0 Virtex 5 FPGA ML561 User Guide www xilinx com 139 UG199 v1 2 April 19 2008 Appendix LCD Interface 57 XILINX 140 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008
73. AJ34 DDRI1 A1 L33 DDR1 DDR1_A10 E33 DDR1_CK2_N AE34 DDRI1 A11 E32 DDR1 CK2 P AF34 DDRI1 A12 E34 DDR1_CKE AC34 DDR1_A13 F33 DDR1_LB_BK11 N32 DDR1_A2 K32 LB BK11 P32 DDR1_A3 K34 DDR1_LB_BK13 AJ32 DDRI1 A4 L34 DDRI1 LB BK13 AK32 DDRI1 A5 DDR1_RAS_N AB32 DDR1_A6 H34 DDR1 WE AD34 DDR1_A7 H33 DDR1 DM BYO AG32 DDR1_A8 4 DDR1_DM_BY1 Y32 DDR1_A9 G33 DDR1_DM_BY2 P34 DDR1_BAO AK33 DDR1_DM_BY3 G32 DDR1_BA1 AK34 DDR1 BYO BO AP32 DDR1 BYO 1 CS AB33 DDR1 DOQ BYO B1 AN32 DDR1 BY2 3 CS AC33 DDR1 BYO B2 AN33 DDR1 CAS AC32 DDR1 BYO B3 AN34 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 95 Appendix Pinouts 57 XILINX Table 1 FPGA 1 Pinout Continued Signal Name Pin Signal Name Pin DDR400 Component Interface cont DDR1_DQ_BY0_B4 AM32 DDR1_DQ_BY2_B4 R32 DDR1_DQ_BY0_B5 AM33 DDR1_DQ_BY2_B5 R33 DDR1_DQ_BY0_B6 AL33 DDR1_DQ_BY2_B6 R34 DDR1_DQ_BY0_B7 AL34 DDR1_DQ_BY2_B7 133 DDR1_DQ_BY1_BO Y34 DDR1 BO D34 DDR1 BYI1 AA34 DDR1 DOQ BY3 B1 C34 DDR1 B2 A A33 DDR1 B2 D32 DDR1 1 B3 Y33 DDR1 BY3 B3 C32 DDR1 1 B4 V34 DDR1 B4 C33 DDR1_DQ_BY1_B5 W34 DDR1 B5 33 DDR1_DQ_BY1_B6 V33 DDR1_DQ_BY3_B6 A33 DDR1_DQ_BY1_B7 V32 DDR1_DQ_BY3_B7 B32 DDR1 BY
74. B_BK18 Y6 DDR2_DIMM_DQ_BY12_B4 K7 DDR2_DIMM_LB_BK20 DDR2_DIMM_DQ_BY12_B5 P6 DDR2_DIMM_LB_BK20 F11 DDR2 DIMM 12 P7 DDR2_DIMM_DM_BY10 511 DDR2_DIMM_DQ_BY12_B7 14 DDR2_DIMM_DM_BY11 R11 DDR2 DIMM BY13 AD7 DDR2 DM 12 G5 DDR2 BY13 AC7 DDR2 DIMM DM 13 DDR2_DIMM_DQ_BY13_B2 5 DDR2_DIMM_DM_BY14 DDR2_DIMM_DQ_BY13_B3 5 DDR2_DIMM_DM_BY15 W11 DDR2_DIMM_DQ_BY13_B4 DDR2_DIMM_DM_BY8 8 DDR2_DIMM_DQ_BY13_B5 AB6 DDR2_DIMM_DM_BY9 G12 DDR2_DIMM_DQ_BY13_B6 AC5 DDR2 DIMM DM CB8 15 H5 DDR2 DIMM BY13 B7 DDR2_DIMM_DQ_BY10_B0 H8 DDR2 DIMM DOQ BY14 BO V9 DDR2 DIMM BY10 G8 DDR2 14 V10 DDR2 DIMM BY10 B2 G10 DDR2 DIMM BY14 B2 AK6 DDR2 DIMM DO BY10 F10 DDR2 DIMM 14 AK7 DDR2 DIMM BY10 F8 DDR2 DIMM BY14 U8 DDR2_DIMM_DQ_BY10_B5 F9 DDR2 DIMM 14 B5 V8 DDR2 DIMM BY10 E8 DDR2 DIMM 14 AJ6 DDR2_DIMM_DQ_BY10_B7 9 DDR2_DIMM_DQ_BY14_B7 AJ7 DDR2_DIMM_DQ_BY11_B0 7 DDR2_DIMM_DQ_BY15_B0 W6 DDR2_DIMM_DO BYI11 B1 E6 DDR2 BY15 AE6 DDR2_DIMM_DQ_BY11_B2 U10 DDR2_DIMM_DQ_BY15_B2 AD6 DDR2_DIMM_DQ_BY11_B3 T9 DDR2_DIMM_DQ_BY15_B3 X7 DDR2 DIMM DO G7 DDR2 DIMM BY15 AA6 Virtex 5 FPGA ML561 User Guide www xilinx com 103 UG199 v1 2 April 19 2008 Appendix Pinouts Table A 2 FPGA 2 Pinout Continued 57 XILIN
75. D7 77 SYSACE 76 SYSACE CTRL1 MPWE 42 SYSACE CTRL2 MPCE 41 SYSACE CTRL3 MPIRO 39 SYSACE_CTRL4 MPBRDY 93 SYSACE Virtex 5 FPGA ML561 User Guide www xilinx com 53 UG199 v1 2 April 19 2008 Chapter 6 Configuration 54 www xilinx com XILINX Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 7 ML561 Hardware Simulation Correlation Introduction This chapter contains the following sections e Introduction e Test Setup e Signal Integrity Correlation Results e Summary and Recommendations e How to Generate a User Specific FPGA IBIS Model Signal integrity SI simulation is a very powerful tool that predicts the quality of signal at the receiver The quality of signal at the I O buffer of the receiver device is most important to the system designer The observation point is buried within the IC device and is not accessible for attaching a physical probe This signal can only be simulated It cannot be measured on the hardware with an oscilloscope Signals can only be measured on hardware at the via probe points of a printed circuit board PCB near the receiver device For a high level of confidence in the SI simulation results it is necessary to develop and validate the simulation model to get a good correlation with the hardware measurements at the probe points When the correlation is obtained the same simulation model is used
76. DING ANY LOSS OF DATA LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2007 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries PCI EXPRESS is a registered trademark of PCI SIG All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 02 12 07 1 0 Initial Xilinx release 08 09 07 1 1 Revised Read and Write Strobe in Table 5 4 page 49 Added Chapter 7 ML561 Hardware Simulation Correlation 04 19 08 1 2 Revised Figure 3 11 page 37 and Table 3 19 page 38 Corrected FPGA driver for Read Data and Read Strobe in Table 5 4 page 49 Updated Data and Strobe entries in Table 5 5 page 49 Updated manufacturers and links in Appendix B Bill of Materials Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 Table Contents Preface About This Guide Guide Contents 7 Additional 7 Additional Support 8 Conventions 9 gs usua DPP 9 Online
77. DR2 BYO B5 for read operations Hardware measurements were performed for the six specific signal nets and then signal integrity SI simulations were performed for correlation and extrapolation The test setup consisted of the following hardware equipment simulation software tools the stimulus test pattern and test criteria for determining the quality of signals The test bench is designed so that the test pattern is applied only to the signal under test and all other data bits to the same memory interface are kept in a quiet Low state This setup ensures that the hardware measurement is not altered due to any simultaneous switching output 55 effect Hardware measurement equipment Agilent D5O80604B 6 GHz oscilloscope Agilent 1131A 3 5 GHz Infiniimax probe amplifier Agilent E2675A Differential browser or E2677A Differential solder in probe or N5425A ZIF probe Virtex 5 FPGA ML561 Rev B2 board S N 103 SRS Model CG635 Synthesized Clock Generator for low jitter clock source e Simulation software Mentor Graphics HyperLynx EXT Version 7 5 with LineSim and BoardSim features Xilinx Virtex 5 FPGA IBIS package file 1136_5v1x50t pkg Rev 1 0 dated June 12 2006 ML561 Rev layout file ML561 B 041706 hyp Micron DDR2 667 IBIS model for output and ODT input Micron PC2 5300 RDIMM IBIS model Molex DDR2 DIMM socket specification P N 087705 1041 Samsung ODRII 1 8V IBIS model IBISWriter Utili
78. DR2 DIMM V7 Termination 160 12 16 31 signals 603 mV swing l around SSTL18 _VREF Power Plane 0 9V 1 0 9 3000 2 7 0 9 Fairchild FN6555 Data Sheet XC5VLX50T FFG1136 FPGA 1 1 25 609 15 Xilinx Power Estimator DDR400 DDR2 XC5VLX50T FFG1136 2 1 25 218 05 Xilinx Power Estimator DDR2 DIMM l XC5VLX50T FFG1136 FPGA 3 1 25 435 11 Xilinx Power Estimator ODRII RLDRAM IT Differential Clock Buffer 2 25 115 0 8 5853006 Data Sheet 200 MHz Osc 1 215 30 0 1 Epson EG2121CA Data Sheet 2 5V Power Plane Capacity 1 25 15000 375 341 TI PTH05010 15A Module Data i Sheet XC5VLX50T FFG1136 FPGA 1 Xilinx Power Estimator DDR400 1 2 6 950 2 5 oe SSTL2_FPGA Power Plane 2 6V 1 26 15000 39 0 36 5 5010 15A Module Data Capacity Sheet DDR x16 Memory 2 26 210 11 Micron DDR Component Data Sheet SSTL2 Mem Power Plane 2 6V 1 26 6000 15 6 145 TI 5010 15A Module Data Capacity Sheet DDR Comp Termination 60 12 16 12 All signals 608 mV swing around SSTL2 _VREF Power Plane 1 3V 1 1 3 3000 3 9 2 7 Fairchild FN6555 Data Sheet Clock Buffer 1 3 3 23 0 1 1 58304 Data Sheet 44 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Table 4 3 ML561 Power Plane Capacities Continued Power Consumption Voltage Current Power Device Description Quantity g Power Sourc
79. FPGA1 P EXT CLK TO FPGA1 33 MHz Clock A single ended 33 MHz Epson SG 8002CA oscillator is provided on the board Y2 for testing purposes Four copies of this clock are generated using a clock buffer 1 58304 on the board one per FPGA along with a probe point for testing P41 The application using this clock source as an input to the PLL on the Virtex 5 device has not yet been fully verified 28 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX External Interfaces Table 3 12 FPGA Slow Clock Sources FPGA Signal Name 1 FPGA1_LOW_FREQ CLK 2 FPGA2_LOW_FREQ CLK 3 FPGA3_LOW_FREQ CLK 33 MHz System ACE Controller Oscillator A single ended 33 MHz Epson SG 8002CA oscillator is provided on the board as a clock source for System ACE functionality GTP Clocks Two SMA connectors are provided for the input of an off board differential clock J16 and J21 A differential clock buffer ICS8543BG is used on the board U20 to generate four LVDS copies of the differential clock signal two for FPGA 1 one for FPGA 2 and one for FPGA 3 A header is used to select between a clock forwarded by the GTP or from the external clock source used to provide a clock to the FPGA logic User I Os This subsection describes the devices that connect to the User I Os of the ML561 board These I Os are provided to ease hardware development using the 561 General Purpose
80. G199 v1 2 April 19 2008 www xilinx com 49 Chapter 5 Signal Integrity Recommendations 50 www xilinx com XILINX Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 6 Configuration This chapter provides a brief description of the FPGA configuration methods used on the Virtex 5 FPGA ML561 Development Board This chapter contains the following sections e Configuration Modes JTAG Chain JTAG Port e Parallel IV Cable Port e System ACE Interface Configuration Modes The Virtex 5 FPGA ML561 Memory Interfaces Development Board includes several options to configure the Virtex 5 FPGAs The configuration modes are System ACE mode e mode Table 6 1 shows the Virtex 5 FPGA configuration modes Master and Slave Parallel SelectMAP configuration modes are not supported on the Virtex 5 FPGA ML561 Development Board separate 6 pin 3x2 header is provide for each FPGA to control the Mode bits setting The three headers are P27 P46 and P112 tor FPGA 1 FPGA 2 and FPGA 3 respectively The even pins 2 4 and 6 of the headers are to GND and the odd pins 1 3 and 5 are connected to the respective Mode bit FPGA inputs 1 and 2 respectively A weak 4 7KQ pull up is applied to each of these pins to set a logic by default Table 6 1 Configuration Modes Mode Jumpers 4
81. GA 2 MII Link Interface 1 TO FPGA2 TX 14 1 2 TX DATA3 AF20 1 2 TX DATAO AE16 1 2 TX EN AD20 1 2 MII_TX_DATA1 AF15 1 TO FPGA2 TX ERR AE21 1 FPGA2 TX DATA2 AF21 1 TO 2 TX SPARE AF14 FPGA 2 Configuration Signals FPGA INIT N14 FPGA2 D IN 15 22 FPGA2_DONE M15 FPGA TMS 14 FPGA2 AD15 VBATT L23 FPGA2 HSWAPEN M23 FPGA2 CCLK N15 FPGA2 TCK 15 2 0 AD21 FPGA2 TDI IN AC15 FPGA2 CNFG 1 AC22 FPGA2 TDO AD14 2 2 AD22 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 105 Appendix FPGA Pinouts XILINX Table A 2 FPGA 2 Pinout Continued Signal Name Pin Signal Name Pin FPGA 2 Test and Debug Signals FPGA2 DIPO AG18 FPGA2 SOFITOUCH 1 B7 17 FPGA2 AG15 FPGA2_SPYHOLE_BK15 P29 FPGA2_DIP2 15 FPGA2_SPYHOLE_BK18 W9 FPGA2_DIP3 AG20 FPGA2 TEST BYO AE23 FPGA2 SOFITOUCH BYO H20 FPGA2 TEST HDR BYO B1 AE22 FPGA2 SOFITOUCH 19 FPGA2 TEST BYO B2 AG12 FPGA2 SOFITOUCH BYO B2 H13 FPGA2 TEST HDR BYO B3 AF13 FPGA2_SOFTTOUCH_BY0_B3 J14 FPGA2 TEST HDR_BY0_B4 AG23 FPGA2_SOFTTOUCH_BY0_B4 J21 FPGA2 TEST HDR BYO B5 AF23 FPGA2 SOFITOUCH BYO B5 J20 FPGA2 TEST
82. I at VIH ac min and VIH dc min e Sum of ISI at VIL ac max and VIL dc max Inter Symbol Interference This is the noise margin available at the receiver Measurements are taken at the AC voltage levels as the minimum vertical opening of the eye in the vicinity of the center of the bit period Ideally the input voltage needs to remain above the DC voltage specifications However by considering the AC voltage specifications for the nominal voltage level for VREF these measurements are more conservative values that also Noise Margin include the effects of VREF variations e VIH margin Difference between the top of the eye opening and VIH ac min e VIL margin Difference between VIL ac max and the bottom of the eye opening These measurements are performed in stand alone fashion for the signal under test Thus no consideration of crosstalk or Simultaneously Switching Output SSO effects are accounted for Overshoot margin is the difference between the maximum allowable VIH per JEDEC specification and the maximum amplitude of the measured eye Similarly undershoot margin is the difference between the minimum amplitude of the measured eye and the Overshoot Undershoot minimum allowable VIL value per JEDEC specification For both SSTL18 and 1 8V Margin HSTL specifications VIH max lt VDDQ 300 mV 1 8 0 3V 21V gt 300 mV 0 3V The BoardSim utility of the HyperLynx simulator is used to extract the IBIS
83. K 13 RLD2_A18 14 RLD2 OK BY1 K9 RLD2 A19 AN14 RLD2_OK_BY1_P K8 RLD2_A2 AES8 RLD2 OK BY2 N J7 RLD2 A3 AL10 RLD2 OK 2 P H7 RLD2 A4 AL11 RLD2 OK 07 RLD2_A5 9 RLD2 OK BY3 P T8 RLD2 A6 10 RLD2 OVLD BYO 1 F11 RLD2_A7 RLD2 OVLD BY2 3 U10 RLD2 8 12 RLD2 REF AJ9 RLD2_A9 8 RLD2_WE_N AF9 RLD2_BAO RLD2 D BYO D11 RLD2 BAI RLD2 D BYO B1 H8 RLD2 BA2 AD11 RLD2 D BYO B2 G8 RLD2 CK BYO 1 N 11 RLD2 D BYO G10 RLD2 CK BYO 1 P AG10 RLD2 D BYO F10 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 111 Appendix Pinouts Table A 3 FPGA 3 Pinout Continued 7 XILINX Signal Name Pin Signal Name Pin RLDRAM II Memory Interface cont RLD2 D BYO B5 F8 RLD2 DM BY2 3 N 9 RLD2 D BYO B6 F9 RLD2 BYO BO G13 RLD2 D BYO B7 E8 RLD2 BYO F13 RLD2 D BYO B8 E9 RLD2 BYO B2 N9 RLD2 D BO R11 RLD2 BYO B3 N10 RLD2 D BY1 R7 RLD2 BYO B4 E13 RLD2 D B2 16 RLD2 BYO B5 E12 RLD2 D 1 T6 RLD2 BYO B6 L9 RLD2 D BY1 R6 RLD2 BYO B7 M10 RLD2_D_BY1_B5 K6 RLD2_DQ_BY0O_B8 RLD2_D_BY1_B6 K7 RLD2_DQ_BY1_BO J10 RLD2_D_BY1_B7 P6 RLD2 BYI1 B1 12 RLD2_D_BY1_B8 7 RLD2_DQ_BY1_B2 13 RLD2 D BY2 V9 RLD2 BYIl B3 H9 RLD2 D BY2 P1 V10 RLD2_DQ_BY1_B4 H10 RLD2_D_B
84. MII_TX_SPARE J9 FPGA3_TO_FPGA1_MII_TX_SPARE K11 FPGA 41 Configuration Signals FPGA INIT N14 1 D IN 15 PROGB 22 FPGA1_DONE M15 FPGA_TMS 14 FPGA1 DOUT AD15 VBATT L23 FPGA1 HSWAPEN M23 FPGA1 CCLK N15 1 15 AD21 FPGA1_TDI_IN 15 1 1 22 1 15 AD14 FPGA1_CNFG_M2 AD22 FPGA 1 Test and Debug Signals 1 DIPO 18 FPGA1 TEST BYO B6 E8 FPGA1_DIP1 AG15 FPGA1_TEST_HDR_BY0_B7 E9 FPGA1_DIP2 AH15 FPGA1_TEST_HDR_BY1_B0 E12 FPGA1_DIP3 20 FPGA1_TEST_HDR_BY1_B1 L9 FPGA1 SPYHOLE BK21 AF26 FPGA1 TEST B2 M10 FPGA1_TEST_HDR_BYO_BO H8 FPGA1 TEST HDR BY1 E11 1 TEST BYO G8 FPGA1 TEST B4 F11 FPGA1 TEST BYO B2 G10 FPGA1 TEST B5 L8 1 TEST BYO F10 FPGA1 TEST 8 1 TEST BYO B4 F8 1 TEST B7 G12 FPGA1 TEST BYO B5 F9 98 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table 1 FPGA 1 Pinout Continued FPGA 1 Pinout Signal Name Pin Signal Name Pin FPGA 1 Test Display Signals FPGA1_7SEG_0_N 17 FPGA1_7SEG_6_N AF19 1 7SEG 1 18 FPGA1_7SEG_DP_N AG21 FPGA1_7SEG_2_N 18 FPGA1 LEDO AD19 FPGA1_7SEG_3_N AF18 FPGA1_LED1 AE19
85. R2_DIMM_DQ_BY2_B3 Table 7 6 Circuit Elements of DDR2 DIMM Write Data Bit DDR2 DIMM DQ BY2 B3 Element Designation Description Driver U5 H29 FPGA 551118 II DCI O Receiver XP2 U3J1 DDR2 DIMM 75 QODT Probe Point C13 Via under memory on DIMM Termination None ODT at load Trace Length Multiple TLs 8 975 inches The IBIS schematics for DDR2 DIMM interface is extracted from a multi board project definition of the two board combination which includes the ML561 motherboard and the DDR2 DIMM at the XP2 connector of the motherboard The impedance characteristics of the Molex socket pin XP2 pin 31 is also included in the IBIS model as 11 13 00179 CONN 0001 TL14 combination The ML561 board under test S N 103 is assembled with DDR2 sockets XP3 XP4 and XP5 which can be utilized for deep DIMM interfaces as described in Table 3 2 page 19 and Figure 3 2 page 20 To accurately represent the IBIS model of the DDR2 DIMM DO BY2 B3signal the IBIS schematics in Figure 7 21 have added stubs for the three socket pins at the XP3 4 and XP5 connectors The DDR2 DIMM used for this correlation testing is a single rank DIMM part Micron part number MT9HTF6472xx 667 Thus for hardware measurements closest to the load probe point via on the DIMM for pin 1 is available Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 70 www xilinx com XILINX Signal Integrity Correlation Re
86. V to 5V Converter 1 5 00 12000 60 0 TI PTH12010 12A Module Data Sheet Notes 1 S 1 8V power for SSTL18 plane 2 1 8V power for HSTL18 plane Virtex 5 FPGA ML561 User Guide www xilinx com 41 UG199 v1 2 April 19 2008 Chapter 4 Electrical Requirements XILINX Table 4 2 lists the 12 different power planes on the Virtex 5 FPGA ML561 Development Board For the SSTL2 SSTL18 and HSTL power separate power modules are implemented for Vcco to FPGA and to memory allowing for ease of power measurement for the FPGAs The power modules for Vcco inputs are implemented with TI PTH05010 modules which have provisions for 5 voltage margining pins Table 4 2 Power Planes Voltage Regulator Module VRM Part Power Plane VRM REFDES ging Power Plane 1 0V VR6 Layer 4 SSTL18 FPGA Power Plane 1 8V Layer 7 HSTL FPGA Power Plane 1 8V VR10 Layer 8 TI PTH05010 15A Modules VccAux Power Plane 2 5V VR12 Layer 11 SSTL2 FPGA Power Plane 2 6V VR9 Layer 8 TTL Power Plane 3 3V VR13 Layer 11 SSTL18 Memory Power Plane 1 8V VR4 Layer 7 TI PTH05000 6A Modules HSTL Memory Power Plane 1 8V VR14 Layer 8 SSTL2 Memory Power Plane 2 6V VR2 Layer 8 SSTL18_VREF Power Plane 0 9V Layer 8 SSTL18_VTT Power Plane 0 9V wis Layer 8 Fairchild FN6555 Bus Term Regulators HSTL_VREF Power Plane 0 9V UA Layer 7 Separate outputs for and
87. Virtex 5 ML561 Memory Interfaces Development Board User Guide XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLU
88. Virtex 5 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 5 family Virtex 5 FPGA User Guide Chapters in this guide cover the following topics Clocking Resources Clock Management Technology CMT Phase Locked Loops PLLs Block RAM Virtex 5 FPGA ML561 User Guide www xilinx com 7 UG199 v1 2 April 19 2008 Preface About This Guide XILINX Configurable Logic Blocks CLBs SelectIO M Resources SelectIO Logic Resources Advanced SelectIO Logic Resources e Virtex 5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIOTM GTP transceivers available in the Virtex 5 LXT and SXT platforms e Virtex 5 FPGA GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex 5 FXT platform Virtex 5 FPGA Embedded Processor Block for PowerPC 440 Designs This reference guide is a description of the embedded processor block available in the Virtex 5 FXT platform e Virtex 5 FPGA Embedded Tri Mode Ethernet MAC User Guide This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in the Virtex 5 LXT SXT and platforms e Virtex 5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex 5 LXT SXT and FXT platforms used for PCI Exp
89. Writ 14 5 24 5 12 6 0 3 90 mV 208 mV DDR2 DIMM Read d M s 2 670 2 9 10 0 23 1 10 ps 107 ps 2mV 85 mV DRII Writ 2 a 0 6 6 4 0 3 9 4 106 ps 27 ps 386 mV 50 mV DRII Read 9 6 4 1 6 31 8 5 6 Virtex 5 FPGA ML561 User Guide Notes 1 Unit Interval UI 1 5 ns for DDR2 and 1 67 ns for QDRII VREF 0 9V for DDR2 and QDRII There are varying degrees of correlation differences among the six test signals In general there is a good match between hardware measurements and the correlation simulation except for some yet to be analyzed differences for example DDR2 DIMM Write DVW and ODRII read noise margin The remainder of this section summarizes the extrapolation results of the data bit interface for all six memory operations on the ML561 board The measure of SI characteristics of each signal is determined by the worst case extrapolation measurement from among the simulations with drivers at slow weak and fast strong corners The values chosen between these two corner cases are Minimum of DVW noise margin and overshoot undershoot margin Maximum of ISI www xilinx com 91 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation 57 XILINX Table 7 16 summarizes the extrapolated SI characteristics of all six test signals Table 7 16 Summary of Worst Case SI Characteristics Operation oid
90. X Signal Name Pin Signal Name Pin DDR2 DIMM Wide Interface cont DDR2 DIMM DOQ BY15 B5 AD5 DDR2 8 15 B4 7 DDR2_DIMM_DO BY15 AD4 DDR2_DIMM_DQ_CB8_15_B5 N8 DDR2_DIMM_DQ_BY15_B7 Y8 DDR2_DIMM_DQ_CB8_15_B6 M5 DDR2_DIMM_DQ G13 DDR2_DIMM_DQ_CB8_15_B7 M6 DDR2_DIMM_DQ F13 DDR2_DIMM_DQS_BY10_L_N 19 DDR2 DIMM B2 9 DDR2_DIMM_DQS_BY10_L_P J10 DDR2 DIMM DQ BY8 N10 DDR2 DIMM DOS J7 DDR2 DIMM 13 DDR2_DIMM_DQS_BY11_L_P H7 DDR2_DIMM_DQ_BY8_B5 12 DDR2_DIMM_DQS_BY12_L_N U7 DDR2_DIMM_DQ_BY8_B6 L9 DDR2 DIMM DOS BY12 P T8 DDR2 BY8 B7 10 DDR2_DIMM_DQS_BY13_L_N AF6 DDR2_DIMM_DQ_BY9_BO 13 DDR2_DIMM_DQS_BY13_L_P AE7 DDR2 DIMM DQ 9 H9 DDR2 DIMM DOQS BY14 V7 DDR2 DIMM BY9 B2 H10 DDR2 DIMM DOS 14 P W7 DDR2 BY9 C12 DDR2 DIMM DOS BY15 AF5 DDR2 DIMM 9 D12 DDR2 DIMM DOS BY15 L P 5 DDR2 DIMM DOQ BY9 B5 J11 DDR2_DIMM_DQS_BY8_L_N C13 DDR2 DIMM DQ BY9 B6 K11 DDR2 DIMM DOQS P 13 DDR2 DIMM DQ BY9 B7 D11 DDR2 DIMM DOS K9 DDR2 CBS8 15 20 5 DDR2_DIMM_DQS_BY9_L_P K8 DDR2_DIMM_DQ_CB8_15_B1 5 DDR2_DIMM_DQS_CB8_15_L_N R8 DDR2_DIMM_DQ_CB8_15_B2 L6 DDR2_DIMM_DQS_CB8_15_L_P R7 DDR2_DIMM_DQ_CB8_15_B3 M7 DDR2 DIMM Miscellaneous Signals DDR2_DIMM1
91. Y2_B2 AK6 RLD2 BY1 B5 C12 RLD2 D BY2 AK7 RLD2 BY1 B6 D12 RLD2 D BY2 U8 RLD2_DQ_BY1_B7 J11 RLD2_D_BY2_B5 V8 RLD2_DQ_BY1_B8 K11 RLD2 D 2 AJ6 RLD2_DQ_BY2_BO 7 RLD2 D BY2 7 AJ7 RLD2 E6 RLD2 D BY2 B8 W9 RLD2 BY2 B2 G7 RLD2 D BY3 BO Y8 RLD2_DQ_BY2_B3 G6 RLD2_D_BY3_B1 AD7 RLD2_DQ_BY2_B4 F6 RLD2_D_BY3_B2 AC7 RLD2_DQ_BY2_B5 5 RLD2_D_BY3_B3 RLD2_DQ_BY2_B6 Jd RLD2_D_BY3_B4 5 RLD2_DQ_BY2_B7 55 RLD2_D_BY3_B5 AB7 RLD2_DQ_BY2_B8 5 RLD2_D_BY3_B6 AB6 RLD2 BO RLD2 D B7 AC5 RLD2 RLD2_D_BY3_B8 AC4 RLD2 B2 N5 RLD2 DM BYO 1 G12 RLD2 L6 112 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table A 3 FPGA 3 Pinout Continued FPGA 3 Pinout Signal Name Pin Signal Name Pin RLDRAM II Memory Interface cont RLD2 B4 M7 RLD2 B7 M5 RLD2 BY3 B5 7 RLD2_DQ_BY3_B8 6 RLD2 B6 N8 FPGA 3 Clock and Reset Signals CLK N D4 EXT AG13 FPGA3 P 4 EXT 2 DIRECT AH22 FPGA3 LOW CLK 20 DIRECT AG22 FPGA3 RESET N IN 14 FPGA 3 L
92. _B1 F31 DDR2 DOQS BYO N N30 DDR2_DQ_BY1_B2 J29 DDR2_DQS_BYO_P M31 DDR2_DQ_BY1_B3 H29 DDR2_DQS_BY1_N P29 DDR2_DQ_BY1_B4 F30 DDR2_DQS_BY1_P N29 DDR2_DQ_BY1_B5 G30 DDR2_DQS_BY2_N E27 DDR2 1 29 DDR2_DQS_BY2_P E26 DDR2_DQ_BY1_B7 E29 DDR2 DOQS BY3 N H27 DDR2 BY2 BO 124 DDR2_DQS_BY3_P G27 DDR2_DQ_BY2_B1 23 R24 FPGA 1 Clock and Reset Signals CLK FPGA1 116 H3 DIRECT CLK TO FPGA P AG22 CLK FPGA1 116 4 EXT 1 AG13 TO FPGA1 118 AF3 EXT TO P 2 FPGA1 118 FPGA1 LOW CLK 20 DIRECT AH22 FPGA1_RESET_N 14 Virtex 5 ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 97 Appendix Pinouts 57 XILINX Table A 1 FPGA 1 Pinout Continued Signal Name Pin Signal Name Pin FPGA 1 Link Interface FPGA2_TO_FPGA1_MII_TX_CLK J10 FPGA3_TO_FPGA1_MII_TX_CLK D10 FPGA2_TO_FPGA1_MII_TX_DATAO C13 FPGA3 TO FPGA1 MII TX DATAO H10 2 1 TX DATAT1 B13 FPGA3_TO_FPGA1_MII_TX_DATA1 C12 FPGA2_TO_FPGA1_MII_TX_DATA2 K9 FPGA3_TO_FPGA1_MII_TX_DATA2 012 2 TO 1 TX DATA3 K8 FPGA3_TO_FPGA1_MII_TX_DATA3 J11 FPGA2_TO_FPGA1_MII_TX_EN L11 FPGA3_TO_FPGA1_MII_TX_EN A13 FPGA2_TO_FPGA1_MII_TX_ERR L10 FPGA3_TO_FPGA1_MII_TX_ERR H9 FPGA2_TO_FPGA1_
93. _CKO_P M25 DDR2_DIMM_A10 AF31 DDR2_DIMM1_CK1_N J25 DDR2 DIMM A11 AC29 DDR2 CK1 P J24 DDR2 DIMM A12 AD30 DDR2 CK2 L26 DDR2 DIMM A13 AA30 DDR2 DIMM1 CK2 P L25 DDR2 DIMM A14 AA29 DDR2 DIMM1 CKEO 528 DDR2_DIMM_A15 AC30 DDR2_DIMM1_CKE1 H28 DDR2_DIMM_A2 DDR2_DIMM1_CS0O_N V27 DDR2_DIMM_A3 AJ30 DDR2_DIMM1_CS1_N V28 DDR2_DIMM_A4 AF30 DDR2_DIMM1_ODT0 H24 DDR2_DIMM_A5 AF29 DDR2_DIMM1_ODT1 H25 DDR2_DIMM_A6 AK31 DDR2_DIMM2_CKO0O_N AF26 DDR2_DIMM_A7 AJ31 DDR2 DIMM 2 CKO0 P AF25 DDR2 DIMM A8 AD29 DDR2_DIMM2_CK1_N AG25 DDR2_DIMM_A9 AE29 DDR2_DIMM2_CK1_P AF24 DDR2 DIMM BAO 0 DDR2_DIMM2_CK2_ AJ26 DDR2_DIMM_BA1 1 DDR2 DIMMO2 CK2 P 27 DDR2_DIMM_BA2 AB31 DDR2 DIMM2 CKEO AE24 DDR2 DIMM CAS N V29 DDR2 DIMM 2 CKE1 AD24 DDR2 DIMM LB BK11 IN P32 DDR2 DIMMO2 CS0 W27 DDR2 DIMM LB BK11 OUT H33 DDR2 DIMM 2 Y27 DDR2 DIMM LB BK13 IN AJ32 DDR2_DIMM2_ODT0 AE26 DDR2_DIMM_LB_BK13_OUT AK32 DDR2_DIMM2_ODT1 AE27 DDR2 DIMM LB BK15 IN 128 DDR2 DIMM3 24 DDR2_DIMM_LB_BK15_OUT 129 DDR2 DIMM3 P Y24 DDR2 DIMM RAS Y28 DDR2 DIMM3 CK1 N AC27 DDR2 RESET Y29 2 DIMM3 P AB27 DDR2 DIMM WE N W29 DDR2 DIMM3 CK2 N AA26 100 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table A 2 FPGA 2 Pinout Continued FPGA 2 Pinout
94. _CNTL_PAR G27 DDR2_DIMM3_CNTL_PAR AA28 DDR2_DIMM1_CNTL_PAR_ERR H27 DDR2_DIMM3_CNTL_PAR_ERR AG28 DDR2_DIMM1_NC_019 K24 DDR2_DIMM3_NC_019 AK29 DDR2_DIMM1_NC_102 L24 DDR2 DIMM3 NC 102 AJ29 DDR2 DIMM2 CNTL PAR AD26 DDR2 CNTL PAR AG8 DDR2_DIMM2_CNTL_PAR_ERR AD25 DDR2_DIMM4_CNTL_PAR_ERR AH8 DDR2_DIMM2_NC_019 AK28 DDR2 DIMMA NC 019 AL10 DDR2_DIMM2 102 AK27 DDR2_DIMM4_NC_102 AE8 104 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Table A 2 FPGA 2 Pinout Continued FPGA 2 Pinout Signal Name Pin Signal Name Pin DDR2 DIMM Miscellaneous Signals cont DDR2_DIMM5_CNTL_PAR 8 DDR2_DIMM2_SA2 N24 DDR2_DIMM5_CNTL_PAR_ERR 12 DDR2_DIMM3_SA0 127 DDR2 5 NC 019 9 DDR2_DIMM3_SA1 P26 DDR2_DIMM5_NC_102 AL11 DDR2_DIMM3_SA2 28 DDR2_DIMM_SCL W31 DDR2 DIMMA 5 0 K27 DDR2 DIMM SDA Y31 DDR2 DIMMA 541 1 28 DDR2_DIMM1_SA0 124 DDR2_DIMM4 5 2 K28 DDR2_DIMM1_SA1 R24 DDR2_DIMM5_SAO E26 DDR2_DIMM1_SA2 N25 DDR2_DIMM5_SA1 F28 DDR2 2 5 0 p25 DDR2_DIMM5_SA2 E28 DDR2_DIMM2_SA1 P24 FPGA 2 Clock and Reset Signals FPGA2 N H3 EXT TO FPGA2 AG13 TO FPGA2 EXT FPGA2 12 DIRECT CLK FPGA2 ATH22 2 LOW FREQ CLK AH20 DIRECT CLK TO FPGA2 P 22 FPGA2 RESET N IN 14 FP
95. al Summary Board Signal Name s RLD2 A 19 0 RLD2 BA 2 0 Bits 23 RLDRAM II Address Description RLD2 CK BYO 1 PN 2 RLDRAM II Differential Clock RLD2 CK BY2 3 PN RLD2 CS BY 0 1 2 3 N RLD2 REEWE RLD2 1 2 3 N RLD2 QVLD 0 12 3 RLD2 BY 1 0 B 8 0 RLD2 DK BYO 1 PN RLD2 BY 1 0 PN L N 2 2 8 0 RLD2_DK_BY0_1_ P N RLD2 BY 3 2 PN 2 RLDRAM II Differential Clock 8 RLDRAM II Control Signals 24 RLDRAM II Data and Strobes Bytes 1 0 24 RLDRAMII Data and Strobes Bytes 3 2 XAPP852 REDRAM II Memory Interface for Virtex 5 FPGAs and its corresponding demo are included on the CD shipped with the ML561 Tool Kit 26 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 External Interfaces 57 XILINX External Interfaces The external interfaces of the Virtex 5 FPGA ML561 Development Board are described this section RS 232 ML561 board provides an 5 232 serial interface using a Maxim MAX3316ECUP device The maximum speed of this device is 460 Kbps Hooks are provided to connect and disconnect FPGAs to the RS 232 serial interface by placing jumpers on headers based on the FPGA involved in the communication Only FPGA isallowed in the communication and others must be disconnected before operation The ML561 toolkit CD contains code to implement UART core
96. apply the digital controls to the margin input pins of the PTH05010 either from FPGA 1 or manually with jumpers www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Power Regulation The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals where xxxx indicates of the six main power regulators SSTL2 551118 2 5 and Table 3 16 Manual Voltage Margining VMARGIN_UP_N VMARGIN_DN_N Output Voltage High High Nominal High Low 5 Low High 5 Low Low Not Applicable If both voltage margining inputs to the power regulator are pulled Low the output voltage is close to nominal but has the possibility of a slightly higher error in the output voltage The power modules use a low leakage open drain control signal to control the voltage margining In the FPGA this can be approximated by using a control signal that drives the output Low when active and does not drive the signal at all when inactive high impedance output Three pin headers are available for performing manual voltage margining using jumpers to select between Nominal 5 and 5 Table 3 17 shows the jumper settings Table 3 17 FPGA 1 Signals and On Board Jumpers for Voltage Margining Power Regulator Signal Name Jumper Setting VR6 VMARGIN_UP_VCC1V0_N P48 1 gt 2 VMARGIN_DN_VCC1V0_N P48 3 gt
97. ardware Simulation Correlation XILINX DDR2 DIMM Read Operation This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from the DDR2 DIMM XP2 to FPGA2 U5 measured at 333 MHz 667 Mb s where the unit interval UI 1 5 ns 49 8 ohms 49 8 ohms 49 8 ohms 49 8 ohms 49 1 ohms 94 605 ps 90 955 ps 90 340 ps 49 1 ohms 28 5 ohms 864 365 ps 59 1 ohms 78 216 ps 41 316 ps 71 6 ohms 4 473 ps i 12 486 ps 0 501 i i i 0 606 in 0 582 in 0 578 5 533 in in 0 264 1319 ps 0 028 in U5 B H DDR2 DIMM DQ DDR2 DIMM DDR2 DIMM AutoPadstk 12 B DDR2 DIMM 0082 DIMM AutoPadstk 3 DDR2 DIMM 5 00 29 59 8 59 8 59 8 ohms 59 8 PMM LAU 3 590 5 31 503 ps 78 962 10 373 ps mm Eo M ue EB om Uni 0 MDQ19 01 MDQ19 01 MDQ19_B01 RNG B DQ19_B01 TL15 TL16 TL17 TL18 TL19 TL20 TL7 TL6 TL3 Virtex 5 FPGA e gt 0 C8 C D pros xes soos d Ma TL1 115 TL11 2200 gt MT47H64M8CB_C 2999 DDR2_DI DQ6 DDR2_DI E d Cd Pr as DDR2_DI DDR2_DI MDQ19_ C13 2999 Orr CU 50 3 ohms 50 3 50 3 50 3 23 650 ps 23 650 23 650 ps 23 650 ps 17 3 fF fF DDR2 D DDR2 DDR2_D DDR2 D R_00179 0 0 milliohms 96 3 fF 500 01F 22918 253 01 46
98. ator circuitry e On chip voltage converter x2 x3 x4 and x5 e lt A 64 step electronic contrast control function Virtex 5 FPGA ML561 User Guide www xilinx com 119 UG199 v1 2 April 19 2008 Appendix LCD Interface Table C 1 summarizes the controller specifications Table C 1 Display Controller Specifications 5 XILINX Parameter Specification Supply Voltage 2 4V to 3 6V Vpp LCD Driving Voltage 4V to 15V Vi cp VO Power Consumption 70 uA typical x4 boost 11V internal supply ON Sleep Mode 2 Standby Mode 10 The on chip RAM size is 65 x 132 8580 bits Hardware Schematic Diagram Figure C 1 illustrates the schematic for the display LCD BUS SamArray LCD_D 7 0 I ENA R W RSEL CS1B 3 3V 3 3V 3 3V i 69 E Default Resistor to Gnd 68 Default 68 Backlight ON OFF Figure C 1 Display Schematic Diagram UG199_C_01_050106 120 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX Hardware Schematic Diagram Peripheral Device 50713 Figure C 2 15 a block diagram of the Samsung 50713 33 Common 132 Segment 33 Common Driver Driver Driver Circuits Circuits Circuits V F Circuit Page Display Data RAM Line Address 65 x132 Address Display Circuit 8580 Bits Circuit Timing Generator Circuit V R Circuit Column Address Cir
99. c AC line cord for the universal input 5V desktop power supply Follow these steps to power up the Virtex 5 FPGA ML561 Development Board 1 Confirm that the ON OFF switch SW5 is in the OFF position 2 Plug the 5V desktop power supply into the 5V DC input barrel jack J28 on the Virtex 5 FPGA ML561 Development Board Plug the desktop power supply AC line cord into an electrical outlet supplying the appropriate voltage 3 Turn SW5 to the ON position The power indicators for all regulator modules should come on indicating output from the regulators The System ACE status LED D37 comes on when the System ACE controller U45 extracts the BIT configuration file from the CompactFlash card to the If no CompactFlash card is installed in the card socket J27 on the Virtex 5 ML561 Development Board the red System ACE error LED D38 flashes 4 CompactFlash card is not installed in socket J27 JTAG cable must be used to configure the FPGAs To use a Parallel IV cable or other JTAG pod download the FPGA configuration bitstream into each FPGA After the DONE LED D28 comes on the FPGAs are configured and ready to use 5 Pushthe reset button SWA www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 3 Hardware Description This chapter describes the major hardware blocks the Virtex 5 ML561 Development Board and provides useful design consideration It contains
100. com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results 5 00 ns UG199_c7_15_071107 Figure 7 15 DDR2 Component Read HW Measurement Waveform Scope Shot at Probe Point FPGA1 Via 1100 0 900 0 500 0 mi in lw P ovi tu w ti T 65 000 75 000 85 000 95 000 105 000 1900 0 Voltage mV Time ns UG199 c7 16 071007 Figure 7 16 DDR2 Component Read Correlation Waveform Scope Shot at Probe Point Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com 67 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX 1900 0 1700 0 k cone 1300 0 gt 1 900 0 5 5 700 0 V 0 1 d 1 1000 f lt 1 Pr al 800 0 1200 0 1600 0 2000 0 0 2800 0 5 06199 7 17 071007 333 MHz Slow PRBS6 85 5 UI Cursor 1 1 0988V 1 2170 ns Cursor 2 1 0254V 2 5029 ns Delta Voltage 73 4 mV Delta Time 1 2859 ns 85 5 UI Figure 7 17 DDR2 Component Read Extrapolation Eye Scope Shot at Receiver IOB Slow Corner 1800 0 1600 0 Voltage mV A 1 11 400 0 200 0 0 000 200 0 65 000 75 000 85 000 95 000 105 000 Time ns UG199_c7_18_071007 Figure 7 18 DDR2 Component Read Extrapolation Waveform Scope Shot at Rec
101. cuit V C Circuit Status Register l Instruction Register Bus Holder Instruction Decoder MPU Interface Parallel amp Serial 5 50713 Samsung 55 GE 5 06199 02 050106 Figure 2 50713 Block Diagram Virtex 5 FPGA ML561 User Guide www xilinx com 121 UG199 v1 2 April 19 2008 Appendix LCD Interface 57 XILINX Figure C 3 shows only the signals of interest for the LCD controller The data sheet from the Samsung web pages provides a complete signal listing 1 Jumper J3 2 Parallel or Serial Selection Default is Parallel 5 6 7 5128 8 S 10 11 e C64 12 LCD Panel 13 14 15 16 LED Backlight UG199_C_03 050106 Figure C 3 64128EFCBC XLP Block Diagram Figure C 4 shows the dimensions for the 64128EFCBC XLP LCD panel 74 00 69 00 56 00 HERR 72 41 70 128 x 64 DOTS 36 70 2 50 2 54 Dimensions in mm 8 00 Max Hiss 06199 04 050106 Figure 4 64128EFCBC XLP Dimensions 122 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Table C 2 LCD Panel Hardware Schematic Diagram Controller Operation The pixels for the LCD panel are stored in the controller data RAM This RAM is a 65 row by 132 column array Each display pixel is represented by a single bit in the RAM array The interface to the RAM array goes through the
102. e W mw W System ACE Controller 1 33 200 07 05080 System CompactFlash Solution 33 MHz Oscillator 2 3 3 45 0 3 Epson SG 8002CA Data Sheet 3 3V Power Plane Capacity 1 33 15000 495 478 TI 5010 15A Module Data Sheet Total Power Consumed 93 2 12V to 5V Power Module Capacity 1 50 12000 600 6 8 12A Module Data Notes 1 S 1 8V power for SSTL18 plane 2 H 1 8V power for HSTL18 plane Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 45 Chapter 4 Electrical Requirements FPGA Internal Power Budget Table 4 4 summarizes power consumption estimates by each of the three XC5VLX50T FFG1136 FPGAs on the Virtex 5 FPGA ML561 Development Board This estimate derives the FPGA utilization information from the respective map report of a fully configured reference design Table 4 4 ML561 FPGA Power Estimate Summary XILINX FPGA FPGA 1 FPGA 420 FPGA 3 DDR400 Comp DDR2 Comp DDR2 DIMM RLDRAM Il Interface DCI DCI QDRII Standard SSTL 18 HSTL 18 HSTL 18 Total Power W 3 7 3 1 10 2 6 3 4 5 1 0 mW 763 763 1945 1160 1515 2 5V mW 435 544 544 544 544 SSTL_18 Veco 1 8V mW 1819 7664 HSTL_18 Veco 1 8V mW 4571 2406 I O Frequency MHz 200 400 400 400 400 Fabric Frequency MHz 200 200 200 200 200 Number of Slices 1500 1500 591
103. e 3 6 Seven Segment Display Signal Mapping Light Emitting Diodes LEDs Each FPGA is able to control four active high green LEDs The green is used to distinguish the User LEDs from the blue system LEDs on the Virtex 5 FPGA ML561 Development Board Pushbuttons The ML561 board contains two momentary pushbuttons Their functions and locations are described in Table 3 14 Table 3 14 User Pushbuttons Button Description Pin Connection SW7 PROG_B Configure FPGA System ACE Controller Pin 33 SW4 RESET_N Reset the FPGA designs FPGA 1 AH14 FPGA 2 AH14 FPGA 3 AH14 The Reset signal goes to a buffer U32 that provides a separate copy of Reset to each FPGA 30 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 57 XILINX External Interfaces Power On or Off Slide Switch The power on or off slide switch is a DPST slide switch used to apply input power to the board While the board contains two such switches the 5V switch is primarily used to supply 5V power to the board whereas the 12V switch is available for testing only Soft Touch Probe Points Soft Touch E5396A Probeless connection points are provided for monitoring FPGA 2 and FPGA 3 test signals with a compatible Agilent logic analyzer FPGA 2 uses separate test signals for soft touch pins while FPGA 3 shares the general purpose test header signals with soft touch pins due to lack of available I O pins Power Measurem
104. e 9 for some definitions and routing terminologies 1 With regard to transmission line impedance Table 3 19 in the Board Design Considerations section lists controlled impedance values of all routing layers The design goal for the ML561 board is to keep the characteristic impedance for all routing layers as close to 50Qas possible Manufacturing tolerance is usually 10 The characteristic impedance of DIMM PCB is derived from the Micron DIMM layout file 58 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX DDR2 Component Write Operation Signal Integrity Correlation Results This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from FPGA1 U7 to the DDR2 memory component U12 measured at 333 MHz 667 Mb s where the unit interval UI 1 5 ns 28 5 ohms 49 0 ohms 49 1 ohms 49 1 ohms 28 5 ohms 3 579 ps 71 0 ohms 24 721 ps 58 3 ohms 47 132 ps 445 560 ps 21 2 ohms 4 473 ps U12 D3 0 022 in 27 482 ps 0 164 25 244 ps 0 302 in 2 852 in 1 000 ps 0 028 in U7 P25 0082 DQ BY2 B3 AutoPadstk 3 DDR2 DQ BY2 B3 AutoPadstk 19 DDR2 BY2 DDR2 BY2 AutoPadstk 3 DDR2 DQ BY2 B3 4 C O LU auo au SNB TL3 TL4 TL8 TL9 TL6 TL5 TL1 MT47H32M16CC Virtex 5 FPGA DQ11 DDR2 DQ BY2 B3 74 DDR2_D i DDR2_D DDR2_D U DDR2_D c9 DDR2_D C7 22 9 fF 1 fF 140 8 fF 22 9 fF 22 9 fF 500 0 fF i 365 6 fF fF UG199_c
105. e Digikey RUE600 ND F1 F2 SMA for Ext Clock Inputs AMPHENOL RF 901 144 8RFX 116 J19 J20 J21 116 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 7 XILINX Table B 1 Bill of Materials Continued Category Description Manufacturer Mfr Part Number Reference Designators DIP Test Inputs ITT_INDUSTRIES SDA04H1KD SW1 SW2 SW6 System Reset Black Panasonic EVQ11L07K SW4 Switch Configuration Reset Red Panasonic EVQ11L05K SW7 Power Input 12V and 5V APEM 25336NA SW3 SW5 Rotary 8 position Digikey GH3311 ND SW8 0402 Assorted Values Panasonic ECJ xxx MLC_CAP_0402 0603 Assorted Values Panasonic ECJ xxx MLC_CAP_0603 0805 Assorted Values Panasonic ECJ xxx MLC_CAP_0805 Capacitor Tantalum C Kemet T520xxx Tantalum D Kemet T520xxx TANT CAP Tantalum E Kemet T520xxx TANT CAP E DO3316 Coilcraft DO3316 Lxx Inductor Ferrite Bead TDK MPZ16085221A FBxx 0805 assorted values Digikey HZ0805E601R 00 Lxx 0402 assorted values Panasonic Resistor 0603 assorted values Panasonic ERJ xxx Rxxx 0805 assorted values Panasonic ERJ xxx Rxxx Transistor MOSFET Diodes BSS138 Virtex 5 FPGA ML561 User Guide www xilinx com 117 UG199 v1 2 April 19 2008 Appendix of Materials 57 XILINX 118 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Appendix C LCD In
106. eference design It contains the tollowing sections e About the Virtex 5 FPGA ML561 Memory Interfaces Tool Kit Virtex 5 FPGA ML561 Memory Interfaces Development Board About the Virtex 5 FPGA ML561 Memory Interfaces Tool Kit The Virtex 5 FPGA ML561 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex 5 LXT FPGA platform This kit allows designers to implement high speed applications with extreme flexibility using IP cores and customized modules The Virtex 5 LXT FPGA with its column based architecture makes it possible to develop highly flexible memory interface applications The Virtex 5 FPGA ML561 Memory Interfaces Tool Kit includes the following e Virtex 5 FPGA ML561 Memory Interfaces Development Board XC5VLX50T FFG1136 FPGA e 5V 6 5 DC power supply e Country specific power supply line cord e RS 232 serial cable DB9 F to DB9 F e Documentation and reference design CD ROM Optional items that also support development efforts include Xilinx ISE software e JTAG cable e Xilinx Parallel IV cable For assistance with any of these items contact your local Xilinx distributor or visit the Xilinx online store at www xilinx com The heart of the Virtex 5 FPGA ML561 Memory Interfaces Tool Kit is the Virtex 5 FPGA ML561 Development Board This manual provides comprehensive information on Rev A3 and
107. eform Scope Shot at Receiver IOB Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com UG199 v1 2 April 19 2008 63 Chapter 7 ML561 Hardware Simulation Correlation 57 XILINX 1900 0 1700 0 N 2 1500 0 i ras i LL N wf FV mt A 500 0 II NEBERERER Z LLLINE DI 100 0 LLLI 800 0 1200 0 1600 0 2000 0 2400 0 2800 0 Voltage mV Time ps 333 MEZ Fast PRBS6 92 5 UI Cursor 1 701 2 mV 1 0026 ns Cursor 2 774 6 mV 2 3908 ns Delta Voltage 73 4 mV Delta Time 1 3883 ns 92 590 UI 06199 c7 10 071007 9 9 Figure 7 10 DDR2 Component Write Extrapolation Eye Scope Shot at Receiver Fast Corner 1900 0 eo YY EMI gt Probe 1 U12 D3 at die 01205 D3 65 000 m 95 000 105 000 Time ns 1300 0 Voltage mV UG199_c7_11_071007 Figure 7 11 DDR2 Component Write Extrapolation Waveform Scope Shot at Receiver IOB Fast Corner 64 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results DDR2 Component Read Operation This subsection shows the test results for the DDR2 2 signal from the DDR2 memory component U12 to FPGA1 U7 measured at 333 667 Mb s where the unit interval UI 1 5 ns U12 n TL2 TL3 TL4 TL8 TL9 TL6 TL5 TL1 U7 P25
108. eiver IOB Slow Corner 68 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results Voltage mV 1900 0 e i 1500 0 yG Probe gt Probe 1 U7 P25 at die 1 U7 P25 at 8 N 1100 0 m u JA Le TII 700 0 4 JN ON 300 0 i 7 LL h 100 0 c 800 0 1200 0 1600 0 2000 0 2400 0 2800 0 Time ps UG199 c7 19 071007 333 MHz Fast PRBS6 88 UI Cursor 1 701 2 mV 1 0772 ns Cursor 2 774 6 mV 2 3980 ns Delta Voltage 73 4 mV Delta Time 1 3208 ns 88 UT Figure 7 19 DDR2 Component Read Extrapolation Eye Scope Shot at Receiver IOB Fast Corner 1900 0 1700 0 1500 0 1300 0 1100 0 gt 900 0 gt 100 0 gt Probe 1 07 25 at die 65 000 75 000 85 000 95 000 105 000 Time ns UG199_c7_20_071007 Figure 7 20 DDR2 Component Read Extrapolation Waveform Scope Shot at Receiver IOB Fast Corner Virtex 5 FPGA ML561 User Guide www xilinx com 69 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation DDR2 DIMM Write Operation This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from FPGA2 U5 to the DDR2 DIMM XP2 measured at 333 MHz 667 Mb s where the unit interval UI 1
109. ent Header The ML561 comes with a 3M Pak 100 power measurement header to enable easy measurement of the power being consumed by the devices on the ML561 Each power regulator uses an Isotek Kelvin current sense resistor 010 0 5 in the path from the output of the regulator to the power plane The power can be computed by measuring the voltage drop across each of these resistors RKELVIN 10 5V 12V oda Very ore IN OUT Other Device Voltage 1KQ Regulator Vccxx Mon To Vccxx Sense Monitor Vccxx Sense Cable V UG199 c3 07 050106 Figure 3 7 Virtex 5 FPGA ML561 Development Board Power Measurement System Table 3 15 Power Measurement Header Pins P102 Header Signal Power Header Pin VCC1V0_SENSE 1 VCC1V0_SENSE 2 VCC1V0 MON 3 VCC2V5_SENSE 5 VCC2V5_SENSE 6 VCC2V5_MON 7 VCC3V3_SENSE 9 VCC3V3_SENSE 10 VCC3V3_MON 11 Virtex 5 FPGA ML561 User Guide www xilinx com 31 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description XILINX Table 3 15 Power Measurement Header Pins P102 Continued Header Signal Power Header Pin VCC1V8_SENSE 13 VCC1V8_SENSE 14 VCC1V8_MON 15 VCC1V5_SENSE 17 VCC1V5_SENSE 16 VCC1V5_MON 19 VCC2V6_SENSE 21 VCC2V6_SENSE 22 VCC2V6_MON 23 VCC5_SENSE 25 VCC5_SENSE 26 VCC5_MON 24 VCC5 20 GND 4 GND 8 GND 12 GND 16 Liquid Crystal Display Connector
110. er Plane 1 8V 1 18 15000 270 200 5010 15A Module Data Capacity Sheet ODRII Memory H 2 1 8 950 3 4 Samsung QDRII Data Sheet RLDRAM Memory 2 1 8 920 3 3 Micron RLDRAM II Data Sheet HSTL_Mem Power Plane 1 8V 1 18 6000 10 8 41 TI 5000 6A Module Data Capacity Sheet ODRII Termination 175 10 16 28 signals 500 mV swing around V em RLDRAM II Termination 60 10 16 10 All signals 500 mV swing around V4 HSTL Power Plane 0 9V 1 0 9 3000 2 7 0 1 Fairchild FN6555 Data Sheet XC5VLX50T FFG1136 Xilinx Power Estimator FPGA 1 DDR2 1 1 8 1011 1 8 XC5VLX50T FFG1136 1 18 4258 77 Xilinx Power Estimator Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 43 Chapter 4 Electrical Requirements Table 4 3 ML561 Power Plane Capacities Continued 57 XILINX Voltage Current Power Eee Device Description Quantity v mA W Power Source W 55 18 FPGA Power Plane 1 8V 1 18 15000 270 175 TI 5010 15A Module Data Capacity Sheet DDR2 x16 Memory 18 250 09 Micron DDR2 Component Data l Sheet DDR2 DIMM 2 1 8 1755 6 3 Micron DDR2 DIMM Data Sheet SSTL18_Mem Power Plane 1 8V 1 18 6000 108 36 TI 5010 15 Module Data Capacity Sheet DDR2 Comp Vrr Termination 25 12 16 0 5 Addr Cntl 603 mV swing around D
111. es Six of those modules TI 5010 7 are used to generate the 1 0V 2 5V and 1 8V for SSTL18 at FPGA 1 and FPGA 2 1 8V for HSTL18 at FPGA 3 2 6V for SSTL2 at FPGA 1 and 3 3V voltages for the power supplies LEDs etc The remaining three modules TI PTH05000 ADJ are used to generate 1 8V for SSTL18 at the memories 1 8V for HSTL at the memories and 2 6V for SSTL2 at the memories An additional three bulk voltage regulators Fairchild FN6555 are used to generate termination and reference voltages each for the SSTL2 SSTL18 power levels By design these voltage levels are half of the input reference voltage being supplied by the memory power supplies The TI PTH05010 WAZ and TI PTH05000 ADJ regulator modules require a fixed 5V input The output is adjustable over a range of 0 9V to 3 6V by changing the resistor tied between pin 4 and GND The difference between these two modules is that the PTH05010 WAZ output voltage can be margined up to 5 of the nominal value by driving pin 10 to GND or digital Low or margined down to 5 of the nominal value by driving pin 9 Low The PTHO05010 WAZ also has a tracking feature that can be used to track another voltage source PTH05010 Voltage Regulator INHIBIT Vo Vo SENSE Cour Cin Inhibit Rae Mil 470 uF Jumper optional UG199 c3 10 050106 Figure 3 10 PTHO05010 Voltage Regulator There are two ways to
112. gnal Inner 2 10 Dielectric Substrate 2 2 4 4 11 06_GND2 Metal Plane 1 0 lt Auto gt Ground Plane 2 12 Dielectric Substrate 3 4 4 13 07 PWR2 Metal Plane 1 0 lt Auto gt Split Power Plane 2 14 Dielectric Substrate 3 3 4 4 15 08_PWR3 Metal Plane 1 0 lt Auto gt Split Power Plane 3 16 Dielectric Substrate 3 4 4 17 09_GND3 Metal Plane 1 0 lt Auto gt Ground Plane 3 18 Dielectric Substrate 3 2 4 4 19 10_INR5 Metal Signal 0 5 lt Auto gt 4 5 50 5 Stripline Signal Inner 3 20 Dielectric Substrate 8 4 4 21 11_PWR4 Metal Plane 1 0 lt Auto gt Split Power Plane 4 22 Dielectric Substrate 5 3 4 4 23 12 INR6 Metal Signal 0 5 lt Auto gt 4 5 50 5 Stripline Signal Inner 4 24 Dielectric Substrate 4 4 4 25 13_GND4 Metal Plane 1 0 lt Auto gt Ground Plane 4 26 Dielectric Substrate 3 8 4 4 27 Metal Signal 1 0 lt Auto gt 6 50 5 Microstrip Signal Bottom 38 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 4 Electrical Requirements This chapter provides the electrical requirements for the Virtex 5 FPGA ML561 Development Board It contains the following sections e Power Consumption e FPGA Internal Power Budget Power Consumption Table 4 1 lists the operating voltages maximum currents power consumption used by the ML561 board devices The Virtex 5 FPGA ML561 Development Board has provisions for two power inputs a 5V p
113. hapter 7 ML561 Hardware Simulation Correlation XILINX 06199 7 22 071107 Figure 7 22 DDR2 DIMM Write HW Measurement Eye Scope Shot at Probe Point 1 DDR2 Memory Via Voltage mV 800 0 1200 0 m d 2000 0 2400 0 2800 0 Time ps UG199 c7 23 070907 333 MHz Slow PRBS6 77 UI Cursor 1 1 1004V 1 2553 ns Cursor 2 1 0253V 2 4105 ns Delta Voltage 75 2 mV Delta Time 1 1582 ns 77 UI Figure 7 23 DDR2 DIMM Write Correlation Eye Scope Shot at Probe Point 1 Slow Corner 72 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Signal Integrity Correlation Results 38 1010 ns 06199 7 24 071107 Figure 7 24 DDR2 DIMM Write HW Measurement Waveform Scope Shot at Probe Point 1 DDR2 Memory Via Voltage mV SAR EAP 0 0 95 000 105 000 15 125 000 135 000 145 000 Time ns UG199_c7_23_071007 Figure 7 25 DDR2 DIMM Write Correlation Waveform Scope Shot at Probe Point 1 Slow Corner Virtex 5 FPGA ML561 User Guide www xilinx com 73 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX Voltage mV 1800 0 1600 0 A lam Za Ng N 1000 0 1400 0 1800 0 0 2600 0 Time ps 00199 c7 26 071007 333 MHz Slow PRBS6 82 UI Cursor 1 1 1028V 1 2399 ns
114. ice GTP I O gt gt m 21 40 4 20 22 4 122 Global Clock Inputs BANK 17 40 BANK 2 20 BANK 18 4 BANK 118 Voltage Control BANK 13 40 BANK 114 DDR Components DQ 0 1 2 Configuration BANK 11 40 BANK 0 BANK 12 40 BANK 112 DDR Components USB Controls DQ 3 amp Controls BANK 15 40 BANK 1 20 BANK 116 DDR2 Component DDR2 Component DQ 0 1 Address BANK 19 40 BANK 3 20 BANK 20 40 BANK 120 DDR2 Component DDR2 Component RS232 DQ2 3 Controls Inter FPGA MII Links UG199_c3_03_050106 Figure 3 3 FPGA 1 Banks for DDR400 and DDR2 Component Top View Virtex 5 FPGA ML561 User Guide www xilinx com 21 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description 7 XILINX Table 3 3 describes all signals associated with DDR400 Component memories Table 3 3 DDR400 Component Signal Summary Board Signal Name s Bits Description DDR1_A 13 0 14 DDR400 Component Address DDR1 CK 2 1 BN 4 DDR400 Component Differential Clock DDR1 RAS CASWE DDR1 12 DDR400 Component Control Signals DDR1_BA 1 0 DDR1 0 1 2 3 CS DDRi1 BY 3 0 DDR1 DO BYO B 70 DDR1 DOS 9 DDR400 Data and Strobe Byte 0 DDR1 DO 1 B 70 DDR1 DOS 9 DDR400 Data and Strobe Byte 1 DDR1 DO BY2 B 70 DDR1 DOS 2 9 DDR400 Data and Strobe Byte 2 DDR1 DO 7 0 DDR1 DOS 9 DDR400 Data and Strobe Byte
115. in used in Master Slave display configurations When RESETB is Low the display controller is initialized as indicated in Table C 3 Table C 3 Display Controller Initialization RESETB is Low Parameter Initial Value Display OFF Entire Display OFF ADC Select OFF Reverse Display OFF Power Control 0 0 0 VC VR VF LCD Bias 1 7 Read Modify Write OFF SHL Select OFF Static Indicator Mode OFF Static Indicator Register 0 0 S1 SO Display Start First line Column Address 0 Page Address 0 Regulator Select 0 0 0 R2 R1 Reference Voltage OFF Reference Voltage Register 1 0 0 0 0 0 SV5 SV4 SV3 SV2 SV1 SV0 When is High the display must be initialized The first steps to be taken to guarantee correct operation of the display and the controller are e Configure the ADC bit This bit determines the scanning direction of the segments When the RESETB signal is active ADC is reset to 0 meaning that the segments are scanned from SEG1 up to SEG132 When ADC is set to 1 the segments are scanned in opposite direction e Configure the SHL bit This bit sets the scanning direction of the COM lines When the RESETB signal is active SHL is reset to 0 meaning that the segments are scanned from up to COM64 When SHL is set to 1 the common lines are scanned in opposite direction 128 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 A
116. ink Interface FPGA1 TO MII TX AF14 FPGA1 TO TX DATA3 AF20 FPGA1 FPGA3 TX DATAO AE16 1 TO FPGA3 TX EN AD20 1 TO FPGA3 TX DATAT AF15 1 TO TX ERR 21 1 TX DATA2 21 1 TX SPARE AF14 FPGA 3 Configuration Signals FPGA INIT N14 D IN 15 22 FPGA3_DONE M15 FPGA_TMS 14 FPGA3_DOUT_B AD15 VBATT 1 23 FPGA3 HSWAPEN M23 FPGA3 CCLK N15 FPGA3 TCK AB15 FPGA3 CNFG AD21 15 22 TDO AD14 FPGA3 CNFG M2 AD22 FPGA 3 Test and Debug Signals DIPO 18 FPGA3 TEST BYO B3 AF13 15 FPGA3 TEST BYO B4 AG23 FPGA3_DIP2 15 FPGA3 TEST BYO B5 AF23 DIP3 AG20 FPGA3 TEST BYO B6 AE12 FPGA3 SPYHOLE BK12 R8 FPGA3 TEST BYO B7 AE13 FPGA3 SPYHOLE BK13 AG32 FPGA3 TEST HDR BY1 BO AE24 FPGA3 TEST BYO A E23 FPGA3 TEST AD24 FPGA3 TEST BYO 22 TEST BY1 B2 AD25 FPGA3 TEST HDR BYO B2 12 TEST BY1 AD26 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com Appendix Pinouts Table A 3 FPGA 3 Pinout Continued 7 XILINX
117. l and Control BANK 126 Figure 3 5 FPGA 3 Banks for QDRII SRAM and RLDRAM II Interfaces Top View UG199_c3_05_050106 Virtex 5 FPGA ML561 User Guide www xilinx com 25 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description 57 XILINX Table 3 6 describes all the signals associated with ODRII component memories Table 3 6 QDRII Component Signal Summary ODR2 4 7 Board Signal Bits Description ODR2 SA 18 0 19 ODRII Address ODR2 CK BYO 3 DN 4 ODRII Differential Clock ODR2 CK 4 7 BN ODR2 RW DLL OFF 3 ODRII Control Signals ODR2 D BY 3 0 8 0 42 ODRII Write Data Strobes and Byte Write Bytes 3 0 ODR2 BYO 3 PN ODR2 BW BY 3 0 ODR2 BY 3 0 B 8 0 38 ODRII Read Data and Strobes Bytes 3 0 ODR2 CO BYO 3 D N ODR2 D BY 7 4 B 8 0 42 ODRII Write Data Strobes and Byte Write Bytes 7 4 ODR2 4 7 ODR2 BW BY 3 0 ODR2 BY 7 4 B 8 0 38 ODRII Read Data and Strobes Bytes 7 4 Notes 1 QDR2_SA 18 is incorrectly labeled ODR2 A3 in the ML561 schematics and layout file XAPP853 QDR II SRAM Interface for Virtex 5 Devices and its corresponding demo are included on the CD shipped with the ML561 Tool Kit For a complete list of FPGA 3 signals and their pin locations refer to Appendix A FPGA Pinouts Table 3 7 describes all signals associated with RLDRAM II devices Table 3 7 RLDRAM II Component Sign
118. lator and connectors for external clock inputs for use as system clocks J19 and J20 The GTP transceivers use their own clock source that can be provided through SMA connectors on the board J16 and J21 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com 27 Chapter 3 Hardware Description XILINX 200 MHz LVPECL Clock The 200 MHz LVPECL clock source is an Epson EG 2121CA200M PCHS oscillator 1 with a differential output The oscillator runs at 200 MHz 100 PPM with an operating voltage of 2 5V 5 This output is fed into an ICS853006 LVPECL buffer for generating a separate differential copy for each FPGA as well as a test point P59 Table 3 10 FPGA 200 MHz IDELAY Reference Clock Source FPGA Signal Name 1 DIRECT CLK TO_FPGA1_P 1 DIRECT CLK TO FPGA1 N 2 DIRECT CLK TO FPGA2 P 2 DIRECT FPGA2 3 DIRECT 3 DIRECT FPGA3 SMA Two SMA connectors are provided for the input of an off board differential clock 119 J20 A differential clock buffer ICS853006 is used on the board U17 and U18 to generate four LVPECL copies of the differential clock signal one for each FPGA along with a probe point P40 for testing The traces from the buffer are routed as a differential pair to each FPGA where they are terminated with 100Q differential termination Table 3 11 FPGA External Clock Sources EXT CLK TO
119. llustrates a general block diagram of the LCD panel in full graphics mode www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 7 XILINX Hardware Schematic Diagram RData 8 gnd Dataln 8 DataOut 8 DB 8 lorD 1 Instruction lorD bit 9 CS1B E RS Rw Clock Block RAM E Clock _ TC State Machine Reset Design for Full Graphics Interface Attached to CoreConnect Bus UG199_C_08_050106 Figure C 8 General Block Diagram of LCD Panel in Full Graphics Mode LCD Panel Used in Character Mode This design example requires a byte representing a command or data to be displayed as Input e When the Enable signal is Low nothing happens The display interface design is locked e When the Enable signal is High and the data_or_command control signal is Low the byte written is a display command e When the Enable signal and the data_or_command control signal are High the byte written is the ASCII character code of the character to be put on the display Display Command Byte The command set of the display can be found in Table C 6 page 130 When the LCD interface is enabled for the first time a set of command bytes is sent to the LCD This command set provides the basic initialization of the LCD controller When this initialization is done the normal LCD interface is freed for normal use Command bytes from the valid command set can be sent to the display controller The Toplevel vhd txt file pr
120. mV 56 6 of VREF ODRII read operations have the lowest VIL noise margin of 201 mV six signals have positive values for overshoot and undershoot margins ODRII write operations have the lowest undershoot margin value of 30 mV For Table 5 1 page 48 through Table 5 5 page 49 the recommendations remain the same except for a clarification for DDR2 ODT as 75 ohm ODT 92 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com XILINX How to Generate a User Specific FPGA IBIS Model How to Generate a User Specific FPGA IBIS Model The tollowing steps indicate how to generate an IBIS model 1 2 10 Under ISE open your fully compiled project Go to the Shell tab and issue an ibiswriter command as ibiswriter allmodels your top level project design file gt ncd name up to 24 lowercase characters ibs For example ibiswriter allmodels mem interface top ncd ml561 fpga3 u34 ibs Unzip the Virtex 5 FPGA IBIS models ZIP file located at the Xilinx Download Center under the Device Models sidebar link Then unzip the ZIP file containing the device package files and extract a package file for your device for example 1136_5v1lx50t pkg Place this file in the same directory as the FPGA IBIS file for example m1561 fpga3 u34 ibs Open the m1561 fpga3 u34 ips file generated by ibiswriter HyperLynx Visual IBIS Editor Check the file for correctness by clicking on the
121. or all three Virtex 5 devices indicates that the SSO guidelines are met for the current pinout The following factors helped to reduce the SSO noise as compared to the Virtex 4 FPGA ML461 board implementation e SparseChevron pinout resulting in larger number of Power GND pin pairs per bank e A revised higher SSO allowance Power GND pair for SparseChevron packages e Reduced thickness of the board 74 mils vs 98 mils resulting in reduced via inductance External terminations at both the memory and FPGA are provided for data signals for most of the memory interfaces on the Virtex 5 FPGA ML561 Development Board layout The external termination is implemented with a single 500 termination to the level See Chapter 5 Signal Integrity Recommendations for specific recommendations and guidelines for terminations These are end terminations to the respective voltage levels for SSTL2 SSTL18 and HSTL signals There are two topologies of end terminations for data signals 1 Fly by termination The parallel termination is placed after the receiver pin 2 Non fly by termination The parallel termination is placed between the driver and the receiver along the trace as close to the receiver pin as possible Also the stub from signal trace to the termination resistor is kept very short within 0 1 inch For Read data terminations at the FPGA have non fly by termination topology These terminations can be selectively
122. ovides a detailed description of the LCD controller interface Virtex 5 FPGA ML561 User Guide www xilinx com 135 UG199 v1 2 April 19 2008 Appendix LCD Interface XILINX Display Data Byte The supplied byte must be a valid ASCII representation of a character as shown in Figure 9 upper bits ooo 0010 0011 0100 0101 0110 0111 1001 1010 1011 1100 1101 1110 1 E xxxx 00D 4 XXXX xxxx 0111 E E xxxx 1010 FM mum 16 UG199_C_09_050106 Figure 9 ASCII Character Representations The character set is stored in block RAM used as ROM The CharacterSet xl1s file contains the layout of the block RAM character set The block RAM see Figure C 10 is organized as small arrays of eight bytes which is easy for address calculation 136 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Hardware Schematic Diagram Data 7 0 2047 10 1F 1280 Addr 10 0 109 1024 1023 256 255 16 59 array is divided pages of eight bytes by 16 forming an array of 128 bytes This array represents one column of standard ASCII table A character is stored as TT TT TTT fT N E Shift LE ttt Direction Addr
123. ower supply and a 12V power supply The maximum rating of a commercially available 5V power supply is limited to 8A or a 40W maximum capacity This power supply is similar to the 5V brick used for previous memory tool kits for example ML461 This tool kit expects the Virtex 5 FPGA ML561 Development Board to exercise only one external memory interface at a time In this case the total power consumption of the board stays within the 40W limit As shown in Table 4 1 if all three FPGA devices and their associated memory devices are activated simultaneously then the total power consumption is approximately 57W which exceeds the 40W capacity of the 5V power brick So an alternate 12V power input jack J23 is provided on the Virtex 5 ML561 Development Board to hook up a 12V power brick for example CUI 0151205000 with 60W capacity The 12V is converted to 5V using the TI PTH12010WAS power module VR11 which can supply up to 12A of current at 5V or a 60W capacity Virtex 5 FPGA ML561 User Guide WWW xilinx com 39 UG199 v1 2 April 19 2008 Chapter 4 Electrical Requirements Table 4 1 ML561 Power Consumption 57 XILINX Device Description Total Available Power Quantity Voltage V mA Current Power Source W 5V Power Supply
124. pril 19 2008 7 XILINX Hardware Schematic Diagram After the SHL bit is configured these settings normally are not changed e Select the LCD bias settings The duty cycle is selected as 1 65 by hardwiring the controller IC pads on the display PCB The LCD bias is set to 1 7 when the BIAS bit is 0 1 9 when the BIAS bit is 1 The following steps are performed next e Start the onboard converter regulator and follower Setthe regulator resistor values see Table C 4 e Configure the reference voltage register parameters see Table C 5 Table C 4 Resistor Value Settings 3 Bit Data Settings R2 R1 RO 000 001 010 011 100 101 110 111 1 Rb Ra 1 90 2 19 2 25 3 02 3 61 4 35 5 29 6 48 Table C 5 Reference Voltage Parameters SV5 SV4 SV3 SV2 5 1 SVO Reference Voltage Parameter 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 At startup of the LCD controller after RESETB operation the resistor and reference voltage values are e Resistor selection is 0 0 0 e Reference voltage is 1 0 0 0 0 0 The resistor selection value MUST be set to 101b when using this LCD panel After the display is brought to operational mode it is best to wait at least 1 ms to ensure the stabilization of power supply levels After this time all other necessary display initializations can
125. ration The automatic increment is still done with a write operation Reset modify read 0 0 1 1 1 0 1 1 1 0 This instruction resets the changed modify read to the normal Reset 0 0 1 1 1 0 0 0 1 0 This instruction resets the LCD controller registers to the default values The instruction CANNOT initialize the LCD power supply initialized with RESETB SHL select 0 0 1 1 0 0 SHL x x x This instruction sets the COM output scanning direction SHL 0 1 gt 64 default SHL 1 COM64 gt COM1 Power Control 0 0 0 0 1 0 1 VC VR VE This instruction selects of the eight power circuit functions In the case of the DisplayTech 64128EFC BC display these must be kept at 000 This instruction selects the resistor ratio Rb Ra Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator register 0 0 x x x x x S1 S0 This is a two byte instruction The first instruction enables the second instruction The second instruction update the contents of the static indicator register 132 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Read Write Characteristics 6800 Mode Table 7 list the read and write timing parameters in 6800 mode The associated waveforms for these parame
126. ress designs e Virtex 5 XtremeDSP Design Considerations User Guide This guide describes the XtremeDSP slice and includes reference designs for using the DSP48E e Virtex 5 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces e Virtex 5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex 5 devices is outlined in this guide Virtex 5 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications e Virtex 5 FPGA Designer s Guide This guide provides information on PCB design for Virtex 5 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support 8 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Conventions Conventions This document uses the following conventions An example illustrates each
127. rstand the expected signal integrity of the memory interface signals When the Virtex 5 device IBIS models are available the results of post layout IBIS simulations and characterization results will be reported Virtex 5 FPGA ML561 User Guide www xilinx com 47 UG199 v1 2 April 19 2008 Chapter 5 Signal Integrity Recommendations XILINX Table 5 1 DDR400 SDRAM Component Terminations Signal FPGA Driver Termination at FPGA Termination at Memory Data DQ 2 II DCI No termination 50Q pull up to 1 3V Data Strobe DOS SSIL2 II DCI No termination 50Q pull up to 1 3V Clock CK CK SSTL2 II No termination 100 2 differential termination between pair Address A BA SSTL2 II No termination 50Q pull up to 1 3V after the last component Control RAS CAS WE CS DM and SSTL2_II No termination 500 pull up to 1 3V after the last CKE component Table 5 2 DDR2 SDRAM DIMM Terminations Signal FPGA Driver Termination at FPGA Termination at Memory Data DQ SSTL18_II_ DCI No termination No termination use 750 ODT Data Strobe DQS DQS DIFF 5517118 II DCI termination No termination use 75Q ODT Data Mask DM SSTL18 No termination No termination use 75Q ODT 6 Pairs of Clocks CK CK SSTLI1S II No termination No termination 3 each per DIMM Address A BA 551118 termination 50Q pull up to 0 9V after the second DIMM Control RAS CAS WE
128. s p 1 7SEG3 Measure Header LCD Connector HSTL ini CG vss JTAG Jack UG199 c3 01 050106 Figure 3 1 ML561 XC5VLX50T FFG1136 Board Placement Diagram FPGA The ML561 uses three Virtex 5 XC5VLX50T FFG1136 devices each in a 1136 pin 35 mm x 35 mm BGA package Figure 1 1 page 12 shows the memory devices associated with the three FPGAs Refer to Appendix A FPGA Pinouts for a complete pinout of all Virtex 5 devices on the board Refer to Appendix B Bill of Materials for a list of major components on the Virtex 5 FPGA ML561 Development Board including their reference designators and links to their corresponding data sheets 18 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Hardware Overview Memories Table 3 1 lists the types of memories that the ML561 board suppotts Table 3 1 Summary of NIL561 Memory Interfaces Memory Type Maximum Speed Data Rate Data Width Standard DDR400 SDRAM 200 MHz 400 Mbps 32 SSTL2 8 1 DDR2 DIMM 333 MHz 667 Mbps 144 SSTL18 8 1 DDR2 SDRAM 333 MHz 667 Mbps 22 SSTL18 8 1 ODRII SRAM 300 MHz 1 2 Gbps 72 HSTL18 18 1 36 1 RLDRAM II 300 MHz 600 Mbps 36 HSTL18 9 1 18 1 When a larger data strobe ratio is implemented for example a x36 ODRII device the smaller configurations can also be demonstrated by programming the FPGA for a smaller data width such as a 9
129. schematics of the same signal net for which hardware measurements are made To replicate the hardware measurement probe set up at the probe point a 0 5 pF probe capacitance is added based on Agilent probe loading specifications to the extracted IBIS schematics of the memory signal For the FPGA devices soldered on the ML561 board under test the process corner slow typical or fast is not known Thus simulation is performed for all three corners slow weak typical and fast strong and the results of the case that best fits with hardware measurement is selected for tabulation Simulation Correlation This term is the minimum input level at which the receiver must recognize input logic High When the input signal reaches VIH ac min the receiver continues to interpret the VIH dc min input as a logic High as long as the signal remains above this voltage This parameter is basically the hysteresis for a logic 1 This term is the maximum input level at which the receiver must recognize input logic ViL ac max Low When the input signal reaches the receiver continues to interpret the input VIL dc max as a logic Low as long as the signal remains below this voltage This parameter is basically the hysteresis for logic 0 10 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Chapter 1 Introduction This chapter introduces the Virtex 5 FPGA ML561 r
130. sults Table 7 7 DDR2 DIMM Write Operation Correlation Results DVW ISI Noise Margin Overshoot Undershoot Measurement Ul UI VIH VIL Total Margin of VREF of VREF Hardware at Probe 942 5 300 200 500 5 110 100 210 mV 620 620 1240 mV Point 62 8 33 3 23 3 137 7 simulation correlation 80 54 134 ps 172 150 322 mV 606 636 1242 mV at memory via C13 77 3 o o I slow weak corner 8 9 Yo 35 9 138 70 Correlation Delta 218 ps 366 ps 112 mV 2mV HW vs Simulation 14 590 24 4 12 6 0 3 Extrapolation at 1 23 ns 85 32 er ps 178 137 315 mV 604 632 1236 mV slow weak corner 82 7 8 35 0 137 3 Extrapolation at IOB 1 32 ns 54 46 100 ps 146 107 253 mV 457 524 981 mV fast strong corner 88 6 7 28 1 109 0 DDR2 DQ is a bidirectional signal To perform hardware measurements for a Write operation that is not interrupted by a Read response or a Refresh operation the testbench on 2 is controlled by DIP switches SW1 as indicated in Table 7 8 Table 7 8 DIP 1 2 Settings Setting 2 b000r2 b11 Description Normal alternating Write Read sequence 2501 Write only Refresh disabled 2 b10 Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 Write once then Read only Refresh disabled www xilinx com 71 C
131. t Board 2 Confirm that theJTAG chain jumpers P38 P44 and P109 are connecting pins 1 to 2 and pins 3 to 4 This way all three devices are in the chain Otherwise the ISE iMPACT software will not find all three devices to configure For more information see JTAG Chain on page 52 3 Make sure that no inhibit jumpers are present on any of the power supply regulator modules For more information see Voltage Regulators on page 34 4 The Virtex 5 FPGA ML561 Development Board has a 200 MHz on board oscillator which provides a copy of a differential LVPECL clock to each of the three FPGAs through a differential clock buffer 1 5853006 There is also a connection to a pair of SMA connectors 19 J20 to provide a differential LVDS clock from an off board signal generator Another differential clock buffer IC5853006 provides a copy of this clock to each of the three FPGAs These clocks are available after configuration for the design to use for various system clocks Virtex 5 FPGA ML561 User Guide WWW xilinx com 15 UG199 v1 2 April 19 2008 Chapter 2 Getting Started XILINX 5 Insert the CompactFlash card included in the kit into socket J27 on the Virtex 5 FPGA ML561 Development Board To select the startup file check that SW8 is set to position 0 Applying Power to the Board 16 The Virtex 5 FPGA ML561 Development Board is now ready to power on The Virtex 5 FPGA ML561 Development Board is shipped with a country specifi
132. tandards Vyr termination is recommended for single ended signals on the board such as data address and control For bidirectional single ended signals for example DDR2 DQ the termination is provided at both ends of the signal at the FPGA as well as at the memory Differential signals For differential pair signals 1000 differential termination is provided between the two legs of the differential pair This termination is placed closest to the load For bidirectional ditferential signals for example DDR2 DOS the differential SelectIO M primitives in Virtex 5 FPGAs for example DIFF SSTL II 18 account for the differential termination within the So external differential termination is required only at the memory Multiload signals Address and control signals are driven by the FPGA and they have multiple loads The termination is placed at the end of the trace after the last load Table 5 1 through Table 5 5 summarize the specific termination schemes used on the Virtex 5 FPGA ML561 Development Board for the following five different memory interfaces For each signal category these tables include reference to the preliminary IBIS simulation results 1 qw DDR400 SDRAM Components Table 5 1 DDR2 SDRAM DIMM Table 5 2 DDR2 SDRAM Components Table 5 3 ODRII SRAM Table 5 4 RLDRAM II Table 5 5 1 Virtex 4 device IBIS models were used during the development of the ML561 board to unde
133. te Ert rns 70 DDR2 DIMM Read ead sd 76 ODRI Write Operation papuana quq sae Ro Popes 81 ODRU Read 86 Summary 91 How to Generate a User Specific FPGA IBIS Model 93 Appendix A FPGA Pinouts 255555259 eae aca nee 95 FPGA 2 ns a ee ee eee ee ee aa 100 FPGA 3 M m 108 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Appendix Bill of Materials Appendix C LCD Interface ee ee eee 119 Display Hardware 119 Hardware Schematic 120 Penphera Device KO0715 ipw saco aat bar Oban tone coats dar ae ER dS GU 121 Controller Operation bana acie esas 123 Controller LCD Panel Connections 125 Controller Power Supply Circuits 126 Operation Example of the 64128 127 130 Read Write Characteristics 6800
134. tegory Description Manufacturer Mfr Part Number Reference Designators 15A Power Module Texas Instruments PTH05010 WAZ d M 6A Power Module Texas Instruments PTH05000 WAZ VR2 VR4 VR14 4A LDO Maxim MAX8556ETE VR3 VR5 VR7 VR8 1 5A VLDO Regulator Linear Technology LTC3026EMSEZPBF U15 Power Measurement Header 3M 3429 6002 P102 500 mA VLDO Regulator Linear Technology LT3021ES8 U16 U22 5A LDO Texas Instruments TPS75501 U23 Power Sensing Resistor Isotek Corp SMV RO10 0 5 USB to 5 232 Bridge Silicon Labs CP2102GM U43 Schmitt Inverter Toshiba TC74LCX14FTCT ND U32 Glue Logic Level Translator Maxim MAX3008 U10 RS 232 Compatible Transceiver Maxim MAX3316ECUP U31 CMOS Octal Buffer ON Semiconductor MC74LCX541DT U37 U38 LVCMOS 1 to 4 T 158304 019 LVCMOS 1 0 4 5V Tolerant ICS553MI U30 U44 Clock Buffer Differential VPECL 1 to 5 11 878180 Device ICS853006 U17 U18 Technology Diff LVPECL to LVDS 1 0 4 ICS8543BG U20 Diff HCSL 1 to 4 7 1 9557 06 024 Display 7 Segment LED Stanley Electric NAR131SB D17 D23 D35 Banana Jack Red Hirschmann 973 582 101 J18 J25 Banana Jack Black Hirschmann 973 582 100 J17 J24 RS232 DB 9 Port Tyco Electronics 747250 4 P73 USB Port KYCON KUSB AS 1 N BLK J29 Sadket Test Headers 2x8 Tyco Electronics 146130 7 ND P20 P21 P93 Connector CompactFlash Holder Molex 55358 5038 27 CompactFlash Molex 55364 0011 5V Power Input Jack CUI Inc PJ 002AH J28 Power Fus
135. terface This appendix describes the LCD interface for the Virtex 5 ML561 Development Board General The Virtex 5 FPGA ML561 Development Board has a full graphical LCD panel This display was chosen because of its possible use in embedded systems A character type display also can be connected because the graphical LCD has the same interface as the character type LCD panels A hardware character generator must be designed to display characters on the screen Display Hardware Design The FPGA I O functioning at 2 5V is connected to the graphic LCD panel through a set of voltage level converting devices These switches translate the 2 5 I O voltage to a 3 3V voltage for the LCD panel A graphics based LCD panel from DisplayTech 64128EFCBC XLP is used on the Virtex 5 FPGA ML561 Development Board The control for this LCD panel is based on the 50713 controller from Samsung The K50713 is a 65 column 132 segment driver controller device for graphic dot matrix LCD systems The chip accepts serial or parallel display data The 8 bit parallel interface is compatible with most LCD panel manufacturers The serial connection mode is write only Extra features added to the interface in addition to the normal parallel signals are Intel or Motorola compatible interface External reset of the chip e External chip select The interface also contains the following built in options for the display and controller e On chip oscill
136. ters are illustrated in Figure C 7 Hardware Schematic Diagram Table C 7 Read Write Characteristics in 6800 Mode Parameter Signal Symbol Min Typ Max Unit Address Setup Time TAS 13 ns RS Address Hold Time Tay 17 ns Data Setup Time Tps 35 ns DB7 to DBO Data Hold Time 13 ns Access Time 125 ns Output Disable Time Top 10 90 ns System Cycle Time RS 400 ns lpwR 125 ns Enable Pulse Width Read Write E RD lpww 55 ns s w Tas TAH CS1B TOYE XL DBO DB7 TACC READ UG199_C_07_050106 Figure C 7 Read Write Timing Waveforms 6800 Mode Virtex 5 FPGA ML561 User Guide www xilinx com 133 UG199 v1 2 April 19 2008 134 Appendix LCD Interface XILINX Design Examples LCD Panel Used in Full Graphics Mode The LCD controller RAM has eight 132 byte pages in fact there are nine pages page 9 is special Each page is one byte wide If all the pages are put in one memory block the needed space is 8 pages x 8 bits x 132 pixels or 8448 bits 1056 bytes One Virtex 5 FPGA block RAM can be configured as 8 1 by 2048 One block RAM can be used to store one complete pixel view of the LCD panel There is enough space left for commands The ninth bit in the block RAM indicates whether the data in the block RAM is real data to be displayed or is a command for the controller The interface
137. the following sections e Hardware Overview e Memory Details e External Interfaces e Power Regulation e Board Design Considerations Hardware Overview The 561 Development Evaluation system reference design is implemented with three XC5VLXS50T FFG1136 devices from the Virtex 5 FPGA family to demonstrate high speed external memory application interfaces The memory technologies supported by the Virtex 5 FPGA ML561 Development Board are DDR2 SDRAM DDR400 SDRAM ODRII SRAM and RLDRAM II SDRAM Figure 3 1 provides a view of all the major components on ML561 board It shows the placement of the three Virtex 5 FPGAs and the position of the associated major interfaces for each FPGA Virtex 5 FPGA ML561 User Guide www xilinx com 17 UG199 v1 2 April 19 2008 Chapter 3 Hardware Description XILINX EL 8 MGT Connections FPGA 1 LEDs amp UP OE FPGA 1 FPGA 1 LEDs T Header 1 FPGA 2 bo VTT amp VREF Config2 12V O Em O Clocks amp 7SEG2 o External Buffers DIP2 CLK und osme 1 232 1 SPY Jack B 12V gt 5V r E a 5V Banana ON e testHeader3 1 133 J System ACE Jacks T JTAG Test Header Controller OFF FPGA 3 LEDs pole
138. the receiver I O Buffer IOB This measurement can only be simulated When the hardware measurements are correlated with the simulation at the probe point the extra probe capacitance is removed from the IBIS schematics and the simulation is repeated at two extreme Extrapolation corners slow weak and fast strong Removal of probe capacitance is important to represent the actual hardware If the SI characteristics of these simulations are proved to be within the acceptable range with sufficient margin then the performance requirements for data signal interface of the corresponding memory operation at the target clock frequency are proved to have been met Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 www xilinx com Preface About This Guide XILINX These measurements are the actual real time measurements of an eye diagram and a Hardware Measurements segment of the test pattern PRBS6 waveform captured on ML561 hardware at the designated probe point using an Agilent scope As the frequency of operation increases the signal delay is affected by the data pattern that precedes the current data bit This is called the inter symbol interference ISI effect testing is performed with a pseudo random bitstream 5 of order 6 that is PRBS6 ISI is the jitter represented by the eye at all four voltage thresholds The worst of the following two sum values listed this table e Sum of IS
139. thresholds at the receiver input VIH ac min at the rising edge VIH dc min at the falling edge VIL dc max at the rising edge VIL ac max at the falling edge Refer to Figure 7 1 for the definition of voltage levels with regard to the trapezoidal eye mask Refer to Terminology page 9 for definitions of the voltage thresholds Because the HyperLynx SI simulation software does not support a trapezoidal mask definition two separate triangular masks for VIH and VIL are defined as shown in Figure 7 2 such that the third vertex of triangle falls on the VREF axis VDDQ VSS UG199_c7_01_062707 Figure 7 1 Single Trapezoid Eye Mask Definition 1 maximal length PRBS test sequence of order generates all 28 1 n bit combinations of test sequences except all 05 Thus the test sequence contains one n bit long consecutive string of 1s and two n 1 bit long consecutive strings of 05 With the PRBS6 test pattern at the highest test frequency of 333 MHz that is the bit time is 1 5 ns measurements in this setup result in a maximum settling time of 1 5 ns 5 7 5 ns for a logic Low and a maximum settling time of 1 5 ns 6 9 ns for a logic High 7 5 ns is sufficient time for the test signal to reach a steady state before the next transition Thus a PRBS test pattern of higher order such as 7 or 9 does not change the eye pattern as proven by sample simulation of one test signal with PRBS6 PRBS7 and
140. to extrapolate and accurately predict the signal quality at the I O buffer of the receiver device for the two significant corner driver conditions slow weak and fast strong The Virtex 5 FPGA ML561 Development Board implements five different memory interfaces e 32 bit DDR2 component e 144 bit DDR2 DIMM 72 bit ODRII SRAM e 32 bit DDR component e 36 bit RLDRAM II Each of these interfaces consists address control clock data and strobe signals The ML561 board has over 500 unique signals DDR2 SDRAMs and ODRII SRAM represent the large majority of Virtex 5 FPGA memory applications The dual data rate DDR data bits are the most critical signals to analyze This chapter presents SI analysis for only six representative data bit signals The procedure Virtex 5 FPGA ML561 User Guide www xilinx com 55 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation XILINX Test Setup 56 illustrated here for these signals can be easily adopted to perform SI analysis for any other memory interface signal on the ML561 board This chapter presents the SI results for the following six data bit signals e DDR2 component DQ bit DDR2_DQ_BY2_B3 for write operations e DDR2 component DQ bit DDR2_DQ_BY2_B3 for read operations e DDR2 DIMM DQ bit DDR2_DIMM_DQ_BY2_B3 for write operations e DDR2 DIMM DO bit DDR2 DIMM DO BY2 for read operations e ODRII bit ODR2 D BYO B5 for write operations e ODRII O bit O
141. to the LCD panel is slow The E signal can be used as the controller clock signal This signal has a minimum cycle time of 400 ns for displaying 8 bits equal to 8 dots on the LCD One full page of the display takes up to 132 x 400 ns 52 8 us Updating the full display takes 52 8us x 8 423us If using the dual port and data width capabilities of the block RAM then writes to the block RAM can be 32 bits 4 control bits and reads from the block RAM on the LCD side can be 8 bits 1 control bit An entire LCD page is updated in 33 write operations The interface on the LCD panel side sequentially reads the block RAM and thus updates the screen contiguously like a television screen The controller microcontroller or other side of the block RAM can be written at any time The write operation happens on the rising edge of the clock and the read LCD update happens on the falling edge of the clock Normally write and read operations at the same address give corrupt read data when the read and write clock edges do not respect the clock to clock setup timing This problem is solved by using both edges of the clock A state machine provides correct timing of the signals on the LCD panel side The panel can be used in write only mode or in read write mode Most of the time LCD panels operate in write only mode At first the block RAM must be initialized with some data instructions to the LCD to make the LCD operate correctly Figure 8 i
142. trol DIMM3 Control DIMM4 Control DIMM5 Control UG199_c3_02_050106 Figure 3 2 DDR2 Deep and Wide DIMM Sockets DDR2 SDRAM Components The ML561 board contains two 333 MHz Micron MT47H32M16CC 3 16 bit DDR2 SDRAM components that provide a 32 bit interface to FPGA 1 Each 16 bit device is packaged in an 84 ball FBGA package with a common address and control bus and separate clocks DQS DQ signals QDRII SRAM ML561 board contains 300 MHz ODRII SRAM interface with a 72 bit Read interface and a 72 bit Write interface using two Samsung K7R643684M FC30 components x36 They are packaged in a 165 ball FBGA package with a body size of 15 x 17 mm These two components share the same address control signals but have separate clock and data signals RLDRAM II Devices The ML561 contains a 300 MHz 36 bit RLDRAM II interface using two Micron MT49H16M18BM 25 devices x18 packaged in a 144 ball PBGA package They share a common address and control bus but have separate clocks and DQS DQ signals 20 www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Memory Details Memory Details DDR400 and DDR2 Component Memories The FPGA 1 device on the Virtex 5 FPGA ML561 Development Board is connected to DDR and DDR2 component memories as shown in Figure 3 3 Figure 3 3 summarizes the distribution of DDR and DDR2 discrete component interface signals among the different banks of the FPGA 1 dev
143. ty of ISE software suite to create customized IBIS model of the U7 U34 devices on the ML561 board Model files ml1561 fpgal u7 ibs andm1561_fpga3_u34 ibs See How to Generate User Specific IBIS Model page 93 for steps on how to create a customized IBIS model of Virtex 5 FPGA for your design e Stimulus 9 9 Pseudo Random Bit Stream PRBS is accepted the most effective test pattern to measure the quality of data signals because unlike the periodic signals like clock and www xilinx com Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX Test Setup strobe a random value can be applied to data bits from one cycle to another A 63 bit PRBS6 1 PRBS of order 6 test pattern stimulus is used for this analysis The value of this PRBS6 string 1563 5 66ED 2717 9461 that is 6563 5000001111110101011001101110110100100111000101111001010001100001 The HyperLynx stimulus setup is for a 2 sequence repeat 10 bits skipped 1 eye and 0 Jitter e Test criteria Quality of a signal is measured in terms of the opening of the signal eye at the receiver input for both the amplitude and the width DDR2 SDRAM Component and DIMM interfaces utilize the SSTL_18 I O standard and ODRII SRAM interface utilizes the HSTL 1 8V I O standard For each of these two I O standards the eye mask is defined by the trapezoid enclosed by the following four voltage
144. velopment Board Revision A Wherever feasible and practical the associated reference designators are also listed for each part The component part number in the Mfr Part Number column includes a link to the corresponding manufacturer or supplier s web page Check with the manufacturer for current information regarding the location and status of component data sheets Table B 1 Bill of Materials Category Description Manufacturer Mfr Part Number Reference Designators FPGA Virtex 5 FPGA Xilinx XC5VLX50T FFG1136 2 speed grade U5 U7 U34 DDR2 Registered DIMM Micron MT9HTF6472Y 667 RDIMM que DDR2 Unbuffered DIMM Micron MT9HTF6472AY 667 UDIMM AES DDR400 SDRAM Micron MT46V32M16BN 5B U6 U9 DDR2 SDRAM Micron MT47H32M16CC 3 U11 U12 ODRII Samsung K7R643684M FC30 U35 U41 RLDRAM II Micron MT49H16M18BM 25 U25 U33 DIMM Socket SMP Technology B037 2401 010 0 Z l C Socket 33 Oscillator Epson SG 8002CA 33 0000M PCC Y2 Y3 Clock 200 Oscillator EG2121CA 200 0000M PHPAB 1 System Controller Xilinx XCCACE TOG144I U45 Configuration Port Molex 87832 1420 P114 Virtex 5 FPGA ML561 User Guide www xilinx com 115 UG199 v1 2 April 19 2008 Appendix B of Materials XILINX Table B 1 Bill of Materials Continued Ca
145. wider by a few spaces than the longest string in that column Save this file with the Save As command in Excel using the Formatted Text space delimited prn option to create a text file with text columns separated by spaces The IBIS checker gives a warning if the ibs file contains tabs Open the prn file with a text editor and copy all these lines to the ibs file at the end of the Pin definitions section just above the Diff Pin declarations Check the ibs file again There should not be any errors Again warnings okay The result is an accurate custom made IBIS model of a Virtex 5 device specific to your design Virtex 5 FPGA ML561 User Guide www xilinx com 93 UG199 v1 2 April 19 2008 Chapter 7 ML561 Hardware Simulation Correlation 94 www xilinx com XILINX Virtex 5 FPGA ML561 User Guide UG199 v1 2 April 19 2008 XILINX FPGA Pinouts This appendix provides the pinouts for the three FPGAs on the Virtex 5 FPGA ML561 Appendix A Development Board The toolkit CD shipped with every ML561 contains sample UCFs for each memory interface These UCFs are for pinout reference only and do not include other constraints like I O standards FPGA 1 Pinout Table A 1 lists the connections for FPGA 1 U7 Table A 1 FPGA 1 Pinout Signal Name Pin Signal Name Pin DDR400 Component Interface DDRI1 AO M32 DDR1_CK1_N

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