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Xilinx 8.2i User's Manual

1. Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Patera ends haryon ngdbuild design_name enter in a syntactical statement oe that you select File gt Open Helvetica bold ai had Keyboard shortcuts Ctrl C Variables in a syntax statement for which you must ngdbuild design_name supply values See the Development System Italic font References to other manuals Reference Guide for more information If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected An optional entry or Square brackets parameter However in bus ngdbuild option_name specifications such as design_name bus 7 0 they are required Braden 4 A list of items from which you idupex Stonjorti must choose one or more Vertical bar e EE TOE lowpwr on off choices 8 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Conventions XILINX Convention Vertical ellipsis Meaning or Use Repetitive material that has been omitted Example IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetit
2. Signal Interface VO Description IM_BE 0 3 IOPB O Instruction interface OPB byte enables IM_busLock IOPB O Instruction interface OPB bus lock IM_DBus 0 31 IOPB O Instruction interface OPB write data bus always 0x00000000 IM_request IOPB O Instruction interface OPB bus request IM_RNW IOPB O Instruction interface OPB read not write tied to IM_select IM_select IOPB O Instruction interface OPB select IM_seqAddr IOPB O Instruction interface OPB sequential address IOPB_DBus 0 31 IOPB I Instruction interface OPB read data bus IOPB_errAck IOPB Instruction interface OPB error acknowledge IOPB_MGrant IOPB I Instruction interface OPB bus grant IOPB_retry IOPB I Instruction interface OPB bus cycle retry IOPB_timeout IOPB I Instruction interface OPB timeout error IOPB_xferAck IOPB I Instruction interface OPB transfer acknowledge Data_Addr 0 31 DLMB O Data interface LMB address bus Byte_Enable 0 3 DLMB O Data interface LMB byte enables Data_Write 0 31 DLMB O Data interface LMB write data bus D_AS DLMB O Data interface LMB address strobe Read_Strobe DLMB O Data interface LMB read strobe Write_Strobe DLMB O Data interface LMB write strobe Data_Read 0 31 DLMB I Data interface LMB read data bus DReady DLMB I Data interface LMB data ready Instr_Addr 0 31 ILMB O Instruction interface LMB address bus LAS ILMB O Instruction interface LMB address strobe IFetch ILMB O Instruction interface
3. Reg_Addr Core O Trace Destination register MSR_Reg Core O Trace Current MSR register value New_Reg_ Value Core O Trace Destination register write data Pipe_Running Core O Trace Processor pipeline to advance Interrup_Taken Core O Trace Unmasked interrupt has occurred Jump_Taken Core O Trace Branch instruction evaluated true Prefetch_Addr Core O Trace OF stage pointer into prefetch buffer MB Halted Core O Trace Pipeline is halted Trace_ Core O Trace signals for real time HW analysis On Chip Peripheral Bus OPB Interface Description The MicroBlaze OPB interfaces are implemented as byte enable capable masters Please refer to the Xilinx OPB design document OPB Usage in Xilinx FPGA for details 48 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 XILINX Local Memory Bus LMB Interface Description Local Memory Bus LMB Interface Description The LMB is a synchronous bus used primarily to access on chip block RAM It uses a minimum number of control signals and a simple protocol to ensure that local block RAM are accessed in a single clock cycle LMB signals and definitions are shown in the following table All LMB signals are active high LMB Signal Interface Table 2 2 LMB Bus Signals Signal Data Interface gata Type Description Addr 0 31 Data_Addr 0 31
4. 000666 39 Data Cache Operations isc ices ieaies fa ote PVG a eG eee aaa eee eae 39 Data Cache Software Support 00 0 ee 40 Floating Point Unit FPU uuaa nunua annur nid iwnsdecneescinacvivdes 40 OVVIE Wc ens eta ete etd E E E E A EEE 40 F ormal eek hed ce Sanh he wid God broad Ee eE era eE wm E my EEE OE A 41 ROUMGIN G5 ie eseng is dd sem esimin WOE pieeniena es ea Peau ena AA dation gather ae Aeon 41 Operations spiccate devs hey ie deeds Me Cones Poe Reade EEE nan ew dyid eae eles 41 EXGEP HONS se forse aa ces niles Re a ote keai a epi a b Mate aaa EA ahs 42 Fast Simplex Link FSL vinci disci weve neevierar yes niyevevercaGd cw nvascatdas 42 Hardware Acceleration using FSL 6 66 eee eens 42 Debug and TratO 2 1015 54405 ious tee eG beri ees ie eens 43 Debus OVERVIEW messege Tyri a dug tl pie eae p eea n E hue ade enV ate nee 43 Trace OVCLVICW ciesrerieiri tit eE ERER REDERE ae ketene ER EE EE EE 43 Chapter 2 MicroBlaze Signal Interface Description OVERVIEW e a ienna na gies eats OE E EEA Halen E sates E E nee 45 UG081 v6 0 June 1 2006 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 Features 6 fac ccecsowe cats whee a witecna ara e a Anta tate wren tate te Gracia eed ow Siena sec EE E 45 MicroBlaze I O Overview sosc5 ude ciady ewer eae sthaw esate vente laere Mangels 45 On Chip Peripheral Bus OPB Interface Description 48 Local Memory Bus LMB Interface
5. 106 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX id iv Integer Divide idiv rD rA rB divide rB by rA signed idivu rD rA rB divide rB by rA unsigned 010010 rD rA rB 0 000 00 00 0000U0 0 6 11 16 21 31 Description The contents of register rB is divided by the contents of register rA and the result is placed into register rD If the U bit is set rA and rB is considered unsigned values If the U bit is clear rA and rB is considered signed values If the value of rA is 0 the divide_by_zero bit in MSR will be set and the value in rD will be 0 Pseudocode if rA Othen cD 0 else cD rB rA Registers Altered e rD unless Divide by zero exception is generated in which case the register is unchanged e MSR Divide_By_Zero Latency 1 cycle if rA 0 otherwise 32 cycles Note This instruction is only valid if MicroBlaze is configured to use a hardware divider C_USE_DIV 1 MicroBlaze Processor Reference Guide www xilinx com 107 UG081 v6 0 June 1 2006 1 800 255 7778 X XILINX Chapter 4 MicroBlaze Instruction Set Architecture imm Immediate imm IMM 0 1 1 0 0 0 000000000 IMM Description The instruction imm loads the IMM value into a temporary register It also locks this value so it can be used by the following instruction and f
6. A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 86 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX bit Branch if Less Than bit rA rB Branch if Less Than bltd rA rB Branch if Less Than with Delay 100141 1 D001 0 rA rB 00000000000 0 6 11 16 21 31 Description Branch if rA is less than 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic bltd will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA lt 0 then PC lt PC rB else PC lt PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if
7. srl Shift Right Logical srl rD rA 100100 rD rA 0000000001000001 0 6 11 16 31 Description Shifts logically the contents of register rA one bit to the right and places the result in rD A zero is shifted in the shift chain and placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in the Carry flag Pseudocode cD 0 0 xD 1 31 lt rA 0 30 MSR C lt rA 31 Registers Altered e rD e MSRIC Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 141 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture SW Store Word sw rD rA rB 110110 rD rA rB 0000000000 0 0 6 11 16 21 31 Description Stores the contents of register rD into the word aligned memory location that results from adding the contents of registers rA and rB Pseudocode Addr lt rA rB Addr 30 31 lt 00 Mem Addr lt rD OEIL Registers Altered e ESR S Latency 1 cycle 142 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX swi Store Word Immediate swi rD rA IMM 11111 0 rD rA IMM 0 6 11 16 31 Description Stores the contents of register rD into the word aligned memory location that results from adding the contents of registers rA and the value IMM sign extended to 32 bits Pseu
8. By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values This instruction is only valid if the target architecture has multiplier primitives and if present the MicroBlaze parameter C_USE_HW_MUL is set to 1 120 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX or Logical OR or rD rA rB 100000 rD rA rB 00000000000 0 6 11 16 21 31 Description The contents of register rA are ORed with the contents of register rB the result is placed into register rD Pseudocode rD lt rA Registers Altered e rD Latency 1 cycle v rB MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 121 XILINX Chapter 4 MicroBlaze Instruction Set Architecture ori Logical OR with Immediate ori rD rA IMM 101000 rD rA IMM 0 6 11 16 31 Description The contents of register rA are ORed with the extended IMM field sign extended to 32 bits the result is placed into register rD Pseudocode rD lt rA V IMM Registers Altered e rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM
9. IXCL_M Gai Program Counter Special IXCL_S gt Purpose Registers y e9 q J Xx O a o Instruction Buffer Instruction Decode Register File 32 X 32b Optional MicroBlaze feature Figure 2 1 MicroBlaze Core Block Diagram Table 2 1 Summary of MicroBlaze Core I O Signal Interface 1 0 Description DM_ABus 0 31 DOPB O Data interface OPB address bus DM_BE 0 3 DOPB O Data interface OPB byte enables DM_busLock DOPB O Data interface OPB bus lock DM_DBus 0 31 DOPB O Data interface OPB write data bus DM_ request DOPB O Data interface OPB bus request DM_RNW DOPB O Data interface OPB read not write DM_select DOPB O Data interface OPB select DM_segAddr DOPB O Data interface OPB sequential address DOPB_DBus 0 31 DOPB I Data interface OPB read data bus DOPB_errAck DOPB I Data interface OPB error acknowledge DOPB_MGrant DOPB I Data interface OPB bus grant DOPB_retry DOPB I Data interface OPB bus cycle retry DOPB_timeout DOPB I Data interface OPB timeout error DOPB_xferAck DOPB I Data interface OPB transfer acknowledge IM_ABus 0 31 IOPB O Instruction interface OPB address bus 46 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 MicroBlaze I O Overview XILINX Table 2 1 Summary of MicroBlaze Core I O Continued
10. e Read from and write to memory general purpose registers and special purpose register except ESR and EAR which can only be read e Support for multiple processors e Write to instruction and data caches Trace Overview The MicroBlaze trace interface exports a number of internal state signals for performance monitoring and analysis Xilinx recommends that users only use the trace interface through Xilinx developed analysis cores This interface is not guaranteed to be backward compatible in future releases of MicroBlaze MicroBlaze Processor Reference Guide www xilinx com 43 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture 44 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 S7 XILINX Chapter 2 MicroBlaze Signal Interface Description Overview The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data accesses and instruction accesses The following three memory interfaces are supported Local Memory Bus LMB IBM s On chip Peripheral Bus OPB and Xilinx CacheLink XCL The LMB provides single cycle access to on chip dual port block RAM The OPB interface provides a connection to both on chip and off chip peripherals and memory The CacheLink interface is intended for use with specialized external memory controllers MicroBlaze also supports up to 8 Fast Simplex Link FSL ports each
11. rA Registers Altered e rD unless an FP exception is generated in which case the register is unchanged e ESR EC e FSR IO UROF DO Latency 4 cycles Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1 102 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX fdiv Floating Point Arithmetic Division fdiv rD rA rB Divide 010110 rD rA rB 00110000000 0 6 11 16 21 31 Description The floating point value in rB is divided by the floating point value in rA and the result is placed into register rD Pseudocode if isDnz rA or isDnz rB then rD lt OxFFC00000 FSR DO 1 ESR EC lt 00110 else if isSigNaN rA or isSigNaN rB or isZero rA and isZero rB or isInfinite rA and isInfinite rB then rD OxFFC0O0000 FSR IO lt 1 ESR EC lt 00110 else if isQuietNaN rA or isQuietNaN rB then rD lt OxFFC0O0000 else if isZero rA and not isInfinite rB then rD signInfinite rB rA FSR DZ amp 1 ESR EC lt 00110 else if isDnz rB rA then rD signZero rA rB FSR UF lt 1 ESR EC lt 00110 else if isNaN rB rA and then rD signInfinite rB rA FSR OF 1 ESR EC e 00110 else rD amp rB rA Registers Altered e rD unless an FP exception is generated in which ca
12. 0 Table 1 21 Processor Version Register 6 PVR6 Bits 0 31 Name ICBA Description Instruction Cache Base Address Value C_ ICACHE BASEADDR Table 1 22 Processor Version Register 7 PVR7 Bits 0 31 Name ICHA Description Instruction Cache High Address Value C_ ICACHE HIGHADDR Table 1 23 Processor Version Register 8 PVR8 Bits 0 31 Name DCBA Description Data Cache Base Address Value C DCACHE BASEADDR Table 1 24 Processor Version Register 9 PVR9 Bits 0 31 Name DCHA Description Data Cache High Address Value C DCACHE_ HIGHADDR 30 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Pipeline Architecture XILINX Table 1 25 Processor Version Register 10 PVR10 Bits Name Description Value 0 7 ARCH Target architecture Defined by option C_TARGET 0x4 Virtex2 0x5 Virtex2Pro 0x6 Spartan3 0x7 Virtex4 0x8 Virtex5 0x9 Spartan3E 8 31 Reserved 0 Table 1 26 Processor Version Register 11 PVR11 Bits Name Description Value 0 20 DO Reset value for MSR 0 21 31 RSTMSR Reset value for MSR C_RESET_MSR Pipeline Architecture MicroBlaze instruction execution is pipelined The pipeline is divided into five stages Fetch IF Decode OF Execute EX Access Memo
13. IMM The mnemonic bneid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC sext IMM else PC lt PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 90 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778
14. 0011 Instruction Bus exception 0100 Data Bus exception 0101 Div by Zero exception 0110 FPU exception 1001 Debug exception 1010 Interrupt 1011 External non maskable break 1100 External maskable break MicroBlaze Core Configurability The MicroBlaze core has been developed to support a high degree of user configurability This allows tailoring of the processor to meet specific cost performance requirements Configuration is done via parameters that typically enable size or select certain processor features E g the instruction cache is enabled by setting the C_LUSE_ICACHE parameter The size of the instruction cache and the cacheable memory range are all configurable using C_CACHE_BYTE_SIZE C_ICACHE BASEADDR and C_ICACHE HIGHADDR respectively MicroBlaze Processor Reference Guide www xilinx com 61 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description Parameters valid for MicroBlaze v5 00a are listed in Table 2 12 Note that not all of these are recognized by older versions of MicroBlaze however the configurability is fully backward compatibility Table 2 12 MPD Parameters Parameter Name Feature Description Allowable Detault EDI tet YNDE p Values Value Assigned Type C_FAMILY Target Family qrvirtex2 virtex2 yes string qvirtex2 spartan3 spartan3e virtex2 virtex2p virtex4 vir
15. 1 if Rb 0 7 Ra 0 7 else Rd 2 if Rb 8 15 Ra 8 15 else Rd 3 if Rb 16 23 Ra 16 23 else Rd 4 if Rb 24 31 Ra 24 31 else Rd 0 PCMPEQ Rd Ra Rb 100010 Rd Ra Rb 10000000000 Rd 1 if Rd Ra else Rd 0 PCMPNE Rd Ra Rb 100011 Rd Ra Rb 10000000000 Rd 1 if Rd Ra else Rd 0 SRA Rd Ra 100100 Rd Ra 0000000000000001 Rd s Ra gt gt 1 C Ra 31 SRC Rd Ra 100100 Rd Ra 0000000000100001 Rd C amp Ra gt gt 1 C Ra 31 SRL Rd Ra 100100 Rd Ra 0000000001000001 Rd 0 amp Ra gt gt 1 C Ra 31 SEXTS8 Rd Ra 100100 Rd Ra 0000000001100000 Rd s Ra 24 31 SEXT16 Rd Ra 100100 Rd Ra 0000000001100001 Rd s Ra 16 31 WIC Ra Rb 100100 00000 Ra Rb 01101000 ICache_Tag Ra WDC Ra Rb 100100 00000 Ra Rb 01100100 DCache_Tag Ra MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 17 X XILINX Table 1 6 MicroBlaze Instruction Set Summary Continued Chapter 1 MicroBlaze Architecture Type A 0 5 6 10 11 15 16 20 21 31 Semantics Type B 0 5 6 10 11 15 16 31 MTS Sd Ra 100101 00000 Ra 11 amp Sd SPR Sd Ra where e SPR 0x0001 is MSR e SPR 0x0007 is FSR MFS Rd Sa 100101 Rd 00000 10 amp Sa Rd SPR Sa where e SPR 0x0000 is PC e SPR 0x0001 is MSR e SPR 0x0003
16. Registers 0s 20 csi gece teed iti entikan ee ae cedar baa ws 21 Special Purpose Registers 0 21 Pipeline Architecture lt iohd0 2 eed cea nkereesiawenguwtagendie wees eres Eea 31 Branches renner aee EE EEE E EE E RE enc ea ERE T altace ENT E EEE N 32 Memory Architectine ciciic isd odie nse ieuds etuk civeyrvveriwwns oben teed han den 32 Reset Interrupts Exceptions and Break 0 0 c cece eee eee 33 Resell bide desce ter andere eaeee dette arid acne Ban deeed beanie dobre Vee bea ne a E A arnt Wut a E ead dete 34 Hardware Exceptions sasies sie ate sist metado i wa tie aeons Honea gle Sa a E tienes 34 Bigaks erered So beeen sie een so aay eana E AEE e St aedees ta Ana e one Snead 35 TEEPE ere cat etna asec aerate sis ini sa6t uate agualale go pie abel auesaate A E E E EE ES 36 User Vector EXcepHOn o sirot Maa aneih daie AG Dpi a Gilden atone aenel 36 Instruction Cache 00 ccc cece eee eee bebe ebb eens 37 OVervieW neire eeri a ernea oP Ge aoa A Reet bed ah ead cache Be ache dee Recent de arene cece 37 General Instruction Cache Functionality 00 0 c cece 37 Instruction Cache Operation 0 00000 38 Instruction Cache Software Support 0 0 0 c cee eee eee eens 38 Data Cache sic 325h 6 008 2 oes es ns eh hes Ree 6 eed Aes ns Boca ouia Bates eas 38 COVOT VIEW seinen wautin dnd une bE Stine beatae Bleed ce took a tee Retain eaa 38 General Data Cache Functionality
17. gt gt Imm5 Imm5 BSRAI Rd Ra Imm 011001 Rd Ra 00000010000 amp Rd s Ra gt gt Imm5 Imm5 BSLLI Rd Ra Imm 011001 Rd Ra 00000100000 amp Rd Ra lt lt Imm5 amp 0 Imm5 IDIV Rd Ra Rb 010010 Rd Ra Rb 00000000000 Rd Rb Ra IDIVU Rd Ra Rb 010010 Rd Ra Rb 00000000010 Rd Rb Ra unsigned FADD Rd Ra Rb 010110 Rd Ra Rb 00000000000 Rd Rb Ra float FRSUB Rd Ra Rb 010110 Rd Ra Rb 00010000000 Rd Rb Ra float FMUL Rd Ra Rb 010110 Rd Ra Rb 00100000000 Rd Rb Ra float FDIV Rd Ra Rb 010110 Rd Ra Rb 00110000000 Rd Rb Ra float FCMP UN Rd Ra Rb 010110 Rd Ra Rb 01000000000 Rd 1 if Rb NaN or Ra NaN float else Rd 0 FCMP LT Rd Ra Rb 010110 Rd Ra Rb 01000010000 Rd 1 if Rb lt Ra float else Rd 0 FCMP EQ Rd Ra Rb 010110 Rd Ra Rb 01000100000 Rd 1 if Rb Ra float else Rd 0 FCMP LE Rd Ra Rb 010110 Rd Ra Rb 01000110000 Rd 1 if Rb lt Ra float else Rd 0 FCMP GT Rd Ra Rb 010110 Rd Ra Rb 01001000000 Rd 1 if Rb gt Ra float else Rd 0 FCMP NE Rd Ra Rb 010110 Rd Ra Rb 01001010000 Rd 1 if Rb Ra float else Rd 0 FCMP GE Rd Ra Rb 010110 Rd Ra Rb 01001100000 Rd 1 if Rb gt Ra float else Rd 0 GET Rd FSLx 011011 Rd 00000 0000000000000 amp Rd FSLx blocking data read FSLx MSR FSL 1 if FSLx_S_Control 1 16 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081
18. is EAR e SPR 0x0005 is ESR e SPR 0x0007 is FSR e SPR 0x000B is BTR e SPR 0x2000 0x200B is PVR 0 to PVR 11 MSRCLR Rd Imm 100101 Rd 00001 00 amp Imm14 Rd MSR MSR MSR and Imm14 MSRSET Rd Imm 100101 Rd 00000 00 amp Imm14 Rd MSR MSR MSR or Imm14 BR Rb 100110 00000 00000 Rb 00000000000 PC PC Rb BRD Rb 100110 00000 10000 Rb 00000000000 PC PC Rb BRLD Rd Rb 100110 Rd 10100 Rb 00000000000 PC PC Rb Rd PC BRA Rb 100110 00000 01000 Rb 00000000000 PC Rb BRAD Rb 100110 00000 11000 Rb 00000000000 PC Rb BRALD Rd Rb 100110 Rd 11100 Rb 00000000000 PC Rb Rd PC BRK Rd Rb 100110 Rd 01100 Rb 00000000000 PC Rb Rd PC MSRIBIP 1 BEQ Ra Rb 100111 00000 Ra Rb 00000000000 PC PC Rb if Ra 0 BNE Ra Rb 100111 00001 Ra Rb 00000000000 PC PC Rb if Ra 0 BLT Ra Rb 100111 00010 Ra Rb 00000000000 PC PC Rb if Ra lt 0 BLE Ra Rb 100111 00011 Ra Rb 00000000000 PC PC Rb if Ra lt 0 BGT Ra Rb 100111 00100 Ra Rb 00000000000 PC PC Rb if Ra gt 0 BGE Ra Rb 100111 00101 Ra Rb 00000000000 PC PC Rb if Ra gt 0 BEQD Ra Rb 100111 10000 Ra Rb 00000000000 PC PC Rb if Ra 0 BNED Ra Rb 100111 10001 Ra Rb 00000000000 PC PC Rb if Ra 0 BLTD Ra Rb 100111 10010 Ra Rb 00000000000 PC PC Rb if Ra lt 0 BLED Ra Rb 100111 10011 Ra Rb 00000000000 PC PC Rb if
19. shift instructions C_USE_BARREL 1 MicroBlaze Processor Reference Guide www xilinx com 97 UG081 v6 0 June 1 2006 1 800 255 7778 X XILINX Chapter 4 MicroBlaze Instruction Set Architecture bsi Barrel Shift Immediate bsrli rD rA IMM Barrel Shift Right Logical Immediate bsrai rD rA IMM Barrel Shift Right Arithmetical Immediate bslli rD rA IMM Barrel Shift Left Logical Immediate 01100 1 rD rA 0 0000S T0000 IMM 0 6 11 16 21 27 31 Description Shifts the contents of register rA by the amount specified by IMM and puts the result in register rD The mnemonic bsll sets the S bit Side bit If the S bit is set the barrel shift is done to the left The mnemonics bsrl and bsra clear the S bit and the shift is done to the right The mnemonic bsra will set the T bit Type bit If the T bit is set the barrel shift performed is Arithmetical The mnemonics bsrl and bsll clear the T bit and the shift performed is Logical Pseudocode if S 1 then rD amp rA lt lt IMM else if T 1 then if IMM 0 then rD 0 IMM 1 lt rA 0 rD IMM 31 lt rA gt gt IMM else rD lt rA else rD amp rA gt gt IMM Registers Altered e rD Latency 1 cycle Notes These are not Type B Instructions There is no effect from a preceding imm instruction These instructions are optional To use them MicroBlaze has to be configured to use barrel shift instructions C_USE_BA
20. 1 1 MicroBlaze Core Block Diagram Features The MicroBlaze soft core processor is highly configurable allowing users to select a specific set of features required by their design The processor s fixed feature set includes e Thirty two 32 bit general purpose registers e 32 bit instruction word with three operands and two addressing modes e 32 bit address bus e Single issue pipeline MicroBlaze Processor Reference Guide www xilinx com 11 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture In addition to these fixed features the MicroBlaze processor is parametrized to allow selective enabling of additional functionality Older deprecated versions of MicroBlaze support a subset of the optional features described in this manual Only the latest active version of MicroBlaze v5 00a supports all options Xilinx recommends that all new designs use the latest active version of the MicroBlaze processor Table 1 1 Configurable Feature Overview by MicroBlaze Version MicroBlaze Versions Feature v2 10a v3 00a v4 00a v5 00a Version Status deprecated deprecated deprecated active Processor pipeline depth 3 3 3 5 On chip Peripheral Bus OPB data side interface option option option option On chip Peripheral Bus OPB instruction side interface option option option option Local Memory Bus LMB data side interface option opti
21. 6 ESR Table 1 11 Exception Status Register ESR Bits Name Description Reset Value 0 18 Reserved 19 DS Exception in delay slot 0 0 not caused by delay slot instruction 1 caused by delay slot instruction Read only 20 26 ESS Exception Specific Status See Table 1 12 For details refer to Table 1 12 Read only 27 31 EC Exception Cause 0 00001 Unaligned data access exception 00010 Illegal op code exception 00011 Instruction bus error exception 00100 Data bus error exception 00101 Divide by zero exception 00110 Floating point unit exception Read only MicroBlaze Processor Reference Guide www xilinx com 25 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Table 1 12 Exception Specific Status ESS Exception Bits Name Description Reset Value Cause Unaligned 20 W Word Access Exception 0 Data Access 0 unaligned halfword access 1 unaligned word access 21 S Store Access Exception 0 0 unaligned load access 1 unaligned store access 22 26 Rx Source Destination Register 0 General purpose register used as source Store or destination Load in unaligned access Illegal 20 26 Reserved 0 Instruction Instruction 20 26 Reserved 0 bus error Data bus 20 26 Reserved 0 error Divide by 20 26 Reserved 0 zero Floating 20 26 Reserved 0 point unit Branch Target Register BTR The Branch Target R
22. Description Return from interrupt will branch to the location specified by the contents of rA plus the IMM field sign extended to 32 bits It will also enable interrupts after execution This instruction always has a delay slot The instruction following the RTID is always executed before the branch target That delay slot instruction has interrupts disabled Pseudocode PC rA sext IMM allow following instruction to complete execution MSR IE amp 1 Registers Altered e PC e MSRIIE Latency 2 cycles Note Convention is to use general purpose register r14 as rA A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 130 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX rted Return from Exception rted rA IMM 10110110100 rA IMM 0 6 11 16 31 Description Return from exception will branch to the location specified by the contents of rA plus the IMM field sign extended to 32 bits The instruction will also enable exceptions after execution This instruction always has a delay slot The instruction following the RTED is always executed before the branch target Pseu
23. FSLn_S_Data Data value currently std_logic_vector input available at the top of the input FSL FSLn_S_Control Control Bit value currently std_logic input available at the top of the input FSL FSLn_S_Exists Flag indicating that data std_logic input exists in the input FSL 54 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Xilinx CacheLink XCL Interface Description XILINX FSL Transactions FSL BUS Write Operation A write to the FSL bus is performed by MicroBlaze using one of the flavors of the put instruction A write operations transfers the register contents to an output FSL bus The transfer is completed in a single clock cycle for blocking mode writes to the FSL put and cput instructions as long as the FSL FIFO does not become full If the FSL FIFO is full the processor stalls until the FSL full flag is lowered The non blocking instructions nput and ncput will always complete in a single clock cycle even if the FSL was full If the FSL was full the write is inhibited and the carry bit is set in the MSR FSL BUS Read Operation A read from the FSL bus is performed by MicroBlaze using one of the flavors of the get instruction A read operations transfers the contents of an input FSL to a general purpose register The transfer is typically completed in 2 clock cycles for blocking mode reads from the FSL get and cget instructions as long as data exists
24. PC breakpoints C_NUMBER_OF_PC_BRK 7 9 Reserved 10 12 RDADDR_ Number of read address C_NUMBER_OF_RD_ADDR_B breakpoints RK 13 15 Reserved 16 18 WRADDR_ Number of write address C_NUMBER_OF_WR_ADDR_B breakpoints RK 19 21 Reserved 22 24 FSL Number of FSLs C_FSL_LINKS 25 31 Reserved Table 1 19 Processor Version Register 4 PVR4 Bits Name Description Value 0 ICU Use instruction cache C_USE_ICACHE 1 5 ICTS Instruction cache tag size C_ADDR_TAG_BITS 6 Reserved 1 7 ICW Allow instruction cache write C_ALLOW_ICACHE WR MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 29 XILINX Chapter 1 MicroBlaze Architecture Table 1 19 Processor Version Register 4 PVR4 Continued Bits Name Description Value 8 10 ICLL Instruction cache line length C_ICACHE_LINE_LEN 2 n 11 15 ICBS Instruction cache byte size 2 n C_CACHE_BYTE_SIZE 16 31 Reserved 0 Table 1 20 Processor Version Register 5 PVR5 Bits 0 Name DCU Description Use data cache Value C_USE_DCACHE 1 5 DCTS Data cache tag size C_DCACHE_ADDR_TAG 6 Reserved 1 7 DCW Allow data cache write C_ALLOW_DCACHE_WR 8 10 DCLL Data cache line length 24n C_DCACHE_LINE_LEN 11 15 DCBS Data cache byte size 2 n C_DCACHE_BYTE_SIZE 16 31 Reserved
25. Rb Rd Addr SB Rd Ra Rb 110100 Rd Ra Rb 00000000000 Addr Ra Rb Addr 0 8 Rd 24 31 SH Rd Ra Rb 110101 Rd Ra Rb 00000000000 Addr Ra Rb Addr 0 16 Rd 16 31 SW Rd Ra Rb 110110 Rd Ra Rb 00000000000 Addr Ra Rb Addr Rd LBUI Rd Ra Imm 111000 Rd Ra Imm Addr Ra s Imm Rd 0 23 0 Rd 24 31 Addr 0 7 LHUI Rd Ra Imm 111001 Rd Ra Imm Addr Ra s Imm Rd 0 15 0 Rd 16 31 Addr 0 15 LWI Rd Ra Imm 111010 Rd Ra Imm Addr Ra s Imm Rd Addr SBI Rd Ra Imm 111100 Rd Ra Imm Addr Ra s Imm Addr 0 7 Rd 24 31 SHI Rd Ra Imm 111101 Rd Ra Imm Addr Ra s Imm Addr 0 15 Rd 16 31 SWI Rd Ra Imm 111110 Rd Ra Imm Addr Ra s Imm Addr Rd 1 Due to the many different corner cases involved in floating point arithmetic only the normal behavior is described A full description of the behavior can be found in Chapter 4 MicroBlaze Instruction Set Architecture Registers 20 MicroBlaze has an orthogonal instruction set architecture It has thirty two 32 bit general purpose registers and up to seven 32 bit special purpose registers depending on configured options www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Registers XILINX General Purpose Registers The thirty two 32 bit General Purpose Registers are numbered RO through R31 The register file is reset on bit stream download reset val
26. address to I side read 0 to 31 access FSL ICACHE_FSL_OUT_Control FSL control bit to I side std_logic output read access FSL Reserved for future use ICACHE_FSL_OUT_Full FSL access buffer for I std_logic input side read accesses is full DCACHE_FSL_IN_Clk Clock output to D side std_logic output return read data FSL 56 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Xilinx CacheLink XCL Interface Description XILINX Table 2 8 MicroBlaze Cache Link signals Signal Name Description VHDL Type Direction DCACHE_FSL_IN_Read Read signal to D side std_logic output return read data FSL DCACHE_FSL_IN_Data Read data from D side std_logic_vector input return read data FSL 0 to 31 DCACHE_FSL_IN_Control FSL control bit from D std_logic input side return read data FSL DCACHE_FSL_IN_Exists More read data existsin std_logic input D side return FSL DCACHE_FSL_OUT_Clk Clock output to D side std_logic output read access FSL DCACHE_FSL_OUT_Write Write new cache miss std_logic output access request to D side read access FSL DCACHE_FSL_OUT_Data Cache miss access read std_logic_vector output address or write address 0 to 31 write data byte write enable to D side read access FSL DCACHE_FSL_OUT_Control FSL control bit to D side std_logic output read access FSL Used with address bits 30 to 31
27. area can also be accessed using an absolute address Data area Comparatively large initialized variables are allocated to the data area which can either be accessed using the read write SDA anchor R13 or using the absolute address depending on the command line option given to the compiler Common un initialized area Un initialized global variables are allocated in the common area and can be accessed either using the absolute address or using the read write small data area anchor R13 Literals or constants Constants are placed into the read only small data area and are accessed using the read only small data area anchor R2 The compiler generates appropriate global pointers to act as base pointers The actual values of the SDA anchors are decided by the linker in the final linking stages For more information on the various sections of the memory please refer to the Address Management chapter The compiler generates appropriate sections depending on the command line options Please refer to the GNU Compiler Tools chapter for more information about these options MicroBlaze Processor Reference Guide www xilinx com 69 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 3 MicroBlaze Application Binary Interface Interrupt and Exception Handling MicroBlaze assumes certain address locations for handling interrupts and exceptions as indicated in Table 3 3 At these locations code is written to jump to the appropria
28. branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 87 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture biti Branch Immediate if Less Than biti rA IMM Branch Immediate if Less Than bitid rA IMM Branch Immediate if Less Than with Delay 10111 1D0 00 10 rA IMM 0 6 11 16 31 Description Branch if rA is less than 0 to the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC IMM The mnemonic bltid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA lt 0 then PC lt PC sext IMM else PC P
29. calls Registers R3 through R12 are volatile of which R3 and R4 are used for returning values to the caller function if any Registers R5 through R10 are used for passing parameters between sub routines e Registers R19 through R31 retain their contents across function calls and are hence termed as non volatile registers a k a callee save The callee function is expected to save those non volatile registers which are being used These are typically saved to the stack during the prologue and then reloaded during the epilogue 66 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Stack Convention XILINX Stack Convention Certain registers are used as dedicated registers and programmers are not expected to use them for any other purpose Registers R14 through R17 are used for storing the return address from interrupts sub routines traps and exceptions in that order Sub routines are called using the branch and link instruction which saves the current Program Counter PC onto register R15 Small data area pointers are used for accessing certain memory locations with 16 bit immediate value These areas are discussed in the memory model section of this document The read only small data area SDA anchor R2 Read Only is used to access the constants such as literals The other SDA anchor R13 Read Write is used for accessing the values in the small data read write secti
30. delay slot branch has been completed 80 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX bge Branch if Greater or Equal bge rA rB Branch if Greater or Equal bged rA rB Branch if Greater or Equal with Delay 10011 1D0 101 rA rB 0000000000 0 0 6 11 16 21 31 Description Branch if rA is greater or equal to 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic bged will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA gt 0 then PC PC rB else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g
31. field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 122 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX pcmpbf Pattern Compare Byte Find pcempbf rD rA rB bytewise comparison returning position of first match 100000 rD rA rB 10000000000 0 6 11 16 21 31 Description The contents of register rA is bytewise compared with the contents in register rB e rDis loaded with the position of the first matching byte pair starting with MSB as position 1 and comparing until LSB as position 4 e Ifnone of the byte pairs match rD is set to 0 Pseudocode if rB 0 7 rA 0 7 then xD 1 else if rB 8 15 rA 8 15 then xD 2 else if rB 16 23 rA 16 23 then rD amp 3 else if rB 24 31 rA 24 31 then rD 4 else rD amp 0 Registers Altered e D Latency 1 cycle Note MicroBlaze Processor Reference Guide www xilinx com 123 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture pcmpeq Pattern Compare Equal pcmpeq rD rA rB equality comparison with a positive boolean result 100010 rD rA rB 10000000000 0 6 11 16 21 31 Description The contents of regis
32. immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 96 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions 2 XILINX bs Barrel Shift bsrl rD rA rB Barrel Shift Right Logical bsra rD rA rB Barrel Shift Right Arithmetical bsll rD rA rB Barrel Shift Left Logical 0100041 rD rA rB S T0000000 00 0 6 11 16 21 31 Description Shifts the contents of register rA by the amount specified in register rB and puts the result in register rD The mnemonic bsll sets the S bit Side bit If the S bit is set the barrel shift is done to the left The mnemonics bsrl and bsra clear the S bit and the shift is done to the right The mnemonic bsra will set the T bit Type bit If the T bit is set the barrel shift performed is Arithmetical The mnemonics bsrl and bsll clear the T bit and the shift performed is Logical Pseudocode if S 1 then rD amp rA lt lt rB 27 31 else if T 1 then if rB 27 31 0 then cD 0 rB 27 31 1 lt rA 0 D rB 27 31 31 lt rA gt gt rB 27 31 else rD amp rA else rD amp rA gt gt rB 27 31 Registers Altered e D Latency 1 cycle Note These instructions are optional To use them MicroBlaze has to be configured to use barrel
33. immediate values MicroBlaze Processor Reference Guide www xilinx com 147 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture 148 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006
34. isQuietNaN rA or isQuietNaN rB then rD lt 0xFFC00000 else if isDnz rA rB then rD amp signZero rA rB FSR UF lt 1 ESR EC lt 00110 else if isNaN rA rB and then rD signInfinite rA rB FSR OF amp 1 ESR EC lt 00110 else rD lt rA rB Registers Altered e rD unless an FP exception is generated in which case the register is unchanged e ESR EC e FSR IO UROF DO Latency 4 cycles Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1 100 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX frsub Reverse Floating Point Arithmetic Subtraction frsub rD rA rB Reverse subtract 01011 0 rD rA rB 00010000000 0 6 11 16 21 31 Description The floating point value in rA is subtracted from the floating point value in rB and the result is placed into register rD Pseudocode if isDnz rA or isDnz rB then cD OxFFCO0O0000 FSR DO amp 1 ESR EC lt 00110 else if isSigNaN rA or isSigNaN rB or isPosInfinite rA and isPosInfinite rB or isNegInfinite rA and isNegInfinite rB then rD OxFFC0O0000 FSR IO amp 1 ESR EC lt 00110 else if isQuietNaN rA or isQuietNaN rB then rD lt OxFFCO0O0000 else if isDnz rB rA then rD signZero rB rA FSR UF amp 1 ES
35. that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 89 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture bnei Branch Immediate if Not Equal bnei rA IMM Branch Immediate if Not Equal bneid rA IMM Branch Immediate if Not Equal with Delay 10111 1D00 0 1 rA IMM 0 6 11 16 31 Description Branch if rA not equal to 0 to the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC
36. value and the target is the value in IMM otherwise it is a relative branch and the target will be PC IMM The mnemonics brid braid brlid and bralid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode if L 1 then rD lt PC if A 1 then PC lt IMM else PC lt PC IMM if D 1 then allow following instruction to complete execution Registers Altered e rD e PC Latency 2 cycles if the D bit is set 3 cycles if the D bit is not set MicroBlaze Processor Reference Guide www xilinx com 93 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Notes The instructions brli and brali are not available By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instru
37. values 110 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX Ihu Load Halfword Unsigned Ihu rD rA rB 110001 rD rA 0000000000 0 11 16 21 31 Description Loads a halfword 16 bits from the halfword aligned memory location that results from adding the contents of registers rA and rB The data is placed in the least significant halfword of register rD and the most significant halfword in rD is cleared Pseudocode Addr lt rA Addr 31 lt 0 cD 16 31 lt Mem Addr YD 0 15 lt Q Registers Altered rB rD unless unaligned data access exception is generated in which case the register is unchanged e ESR W Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com UG081 v6 0 June 1 2006 111 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Ihui Load Halfword Unsigned Immediate Ihui rD rA IMM 111001 rD rA IMM 0 6 11 16 31 Description Loads a halfword 16 bits from the halfword aligned memory location that results from adding the contents of register rA and the value in IMM sign extended to 32 bits The data is placed in the least significant halfword of register rD and the most significant halfword in rD is cleared Pseudocode Addr lt rA sext IMM Addr 31 lt 0 cD 16 31 lt Mem Add
38. will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC lt PC rB else PC lt PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 79 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture beqi Branch Immediate if Equal beqi rA IMM Branch Immediate if Equal beqid rA IMM Branch Immediate if Equal with Delay 10111 34 D00 00 rA IMM 0 6 11 16 31 Description Branch if rA is equal to 0 t
39. with one master and one slave FSL interface Features The MicroBlaze can be configured with the following bus interfaces A 32 bit version of the OPB V2 0 bus interface see IBM s 64 Bit On Chip Peripheral Bus Architectural Specifications Version 2 0 LMB provides simple synchronous protocol for efficient block RAM transfers FSL provides a fast non arbitrated streaming communication mechanism XCL provides a fast slave side arbitrated streaming interface between caches and external memory controllers Debug interface for use with the Microprocessor Debug Module MDM core Trace interface for performance analysis MicroBlaze I O Overview The core interfaces shown in Figure 2 1 and the following Table 2 1 are defined as follows DOPB Data interface On chip Peripheral Bus DLMB Data interface Local Memory Bus BRAM only IOPB Instruction interface On chip Peripheral Bus ILMB Instruction interface Local Memory Bus BRAM only MESL 0 7 FSL master interfaces SFSL 0 7 FSL slave interfaces IXCL Instruction side Xilinx CacheLink interface FSL master slave pair DXCL Data side Xilinx CacheLink interface FSL master slave pair Core Miscellaneous signals for clock reset debug and trace MicroBlaze Processor Reference Guide www xilinx com 45 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description Instruction side Data side bus interface bus interface
40. 2 MicroBlaze Signal Interface Description Table 2 12 MPD Parameters Parameter Name Feature Description Allowable DAAU ERI tool WHEE p Values Value Assigned Type C_ICACHE_HIGHADDR Instruction cache high 0x00000000 0x3FFF std_logi address OxFFFFFFFF FFFF c_vector C_USE_ICACHE Instruction cache 0 1 0 integer C_ALLOW_ICACHE WR Instruction cache write 0 1 1 integer enable C_ICACHE LINELEN Instruction cache line 4 8 4 integer length C_ADDR_TAG _ BITS Instruction cache address 0 21 17 yes integer tags C_CACHE BYTE SIZE Instruction cache size 2048 4096 8192 integer 8192 16384 32768 65536 C_ICACHE_USE_FSL Cache over CacheLink 1 1 integer instead of OPB for instructions C_DCACHE_BASEADDR Data cache base address 0x00000000 0x0000 std_logi OxFFFFFFFF 0000 c_vector C_ DCACHE HIGHADDR Data cache high address 0x00000000 Ox3FFF std_logi OxFFFFFFFF FFFF c_vector C_USE_DCACHE Data cache 0 1 0 integer C_ALLOW_DCACHE WR Data cache write enable 0 1 1 integer C_DCACHE_LINELEN Data cache line length 4 8 4 integer C_DCACHE_ADDR_TAG Data cache address tags 0 20 17 yes integer C_DCACHE BYTE_SIZE Data cache size 2048 4096 8192 integer 8192 16384 32768 655362 C_DCACHE_USE_FSL Cache over CacheLink 1 1 integer instead of OPB for data 1 Not all sizes are permitted in all architectures The cache will use between 1 and 32 RAMB primitives 2 Not all sizes ar
41. 24 04 4 0 Xilinx EDK 6 3 release 09 21 04 4 1 Minor corrections for EDK 6 3 SP1 release 11 18 04 4 2 Minor corrections for EDK 6 3 SP2 release 01 20 05 5 0 Xilinx EDK 7 1 release 04 02 05 5 1 Minor corrections for EDK 7 1 SP1 release 05 09 05 5 2 Minor corrections for EDK 7 1 SP2 release 10 05 05 5 3 Minor corrections for EDK 8 1 release 02 21 06 5 4 Corrections for EDK 8 1 SP2 release 06 01 06 6 0 Xilinx EDK 8 2 release UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide www xilinx com UG081 v6 0 June 1 2006 1 800 255 7778 Preface About This Guide Manual Contents 0 0 ccc cee cece een e eee beeen een eeneans 7 Additional Resources 00 cece ec ccc eee een e een eee ne en een eens 7 Conventions ooer bow bd cd Rin des E Ghd eA a Gnd Rtas b bine unre ba BS 8 Typographical spsg cour iiai ee s Won Pe E dona ated shy elongated aie as 8 Online Documents cresie caw bo Ha wA Re aks PANG De aka VENER Swe ERA OEE 9 Chapter 1 MicroBlaze Architecture OVCEVICW be ob dren dee ns bien Gabe thee Bares ater E EE aE E E Pewee cutaeg heeded ok 11 FR AEUEOS iernii s co alae E EEEE ata eae desk geal Pea eae aces 11 Data Types and Endianness 0 6 0 o ccc eee 13 DIDS EP UCEL ONS eee oceans tes res ea neg kd ooh ee seen Aeneas en Ata 13 Registers ceili nd hen ee e G Ges GuG lh pubis Gur dete E AS 20 General Purpose
42. 7778 UG081 v6 0 June 1 2006 Instructions XILINX sh Store Halfword sh rD rA rB 110101 rD rA rB 0000000000 0 0 6 11 16 21 31 Description Stores the contents of the least significant halfword of register rD into the halfword aligned memory location that results from adding the contents of registers rA and rB Pseudocode Addr lt rA rB Addr 31 lt 0 Mem Addr rD 16 31 Registers Altered e ESR S Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 137 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture shi Store Halfword Immediate shi rD rA IMM 1 1 1 1 0 1 rD rA IMM 0 6 11 16 31 Description Stores the contents of the least significant halfword of register rD into the halfword aligned memory location that results from adding the contents of register rA and the value IMM sign extended to 32 bits Pseudocode Addr lt rA sext IMM Addr 31 lt 0 Mem Addr lt rD 16 31 Registers Altered e ESR S Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 138 www xilinx com MicroBlaze Processor Referen
43. BIP 1 BEQI Ra Imm 101111 00000 Ra Imm PC PC s Imm if Ra 0 BNEI Ra Imm 101111 00001 Ra Imm PC PC s Imm if Ra 0 BLTI Ra Imm 101111 00010 Ra Imm PC PC s Imm if Ra lt 0 BLEI Ra Imm 101111 00011 Ra Imm PC PC s Imm if Ra lt 0 BGTI Ra Imm 101111 00100 Ra Imm PC PC s Imm if Ra gt 0 BGEI Ra Imm 101111 00101 Ra Imm PC PC s Imm if Ra gt 0 BEQID Ra Imm 101111 10000 Ra Imm PC PC s Imm if Ra 0 BNEID Ra Imm 101111 10001 Ra Imm PC PC s Imm if Ra 0 BLTID Ra Imm 101111 10010 Ra Imm PC PC s Imm if Ra lt 0 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 19 X XILINX Table 1 6 MicroBlaze Instruction Set Summary Continued Chapter 1 MicroBlaze Architecture Type A 0 5 6 10 11 15 16 20 21 31 Semantics Type B 0 5 6 10 11 15 16 31 BLEID Ra Imm 101111 10011 Ra Imm PC PC s Imm if Ra lt 0 BGTID Ra Imm 101111 10100 Ra Imm PC PC s Imm if Ra gt 0 BGEID Ra Imm 101111 10101 Ra Imm PC PC s Imm if Ra gt 0 LBU Rd Ra Rb 110000 Rd Ra Rb 00000000000 Addr Ra Rb Rd 0 23 0 Rd 24 31 Addr 0 7 LHU Rd Ra Rb 110001 Rd Ra Rb 00000000000 Addr Ra Rb Rd 0 15 0 Rd 16 31 Addr 0 15 LW Rd Ra Rb 110010 Rd Ra Rb 00000000000 Addr Ra
44. C 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 88 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX bne Branch if Not Equal bne rA rB Branch if Not Equal bned rA rB Branch if Not Equal with Delay 10011 1D00 0 1 rA rB 00000000000 0 6 11 16 21 31 Description Branch if rA not equal to 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic bned will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means
45. CMP Rd Ra Rb 000101 Rd Ra Rb 00000000001 Rd Rb Ra 1 Rd 0 0 if Rb gt Ra else Rd 0 1 CMPU Rd Ra Rb 000101 Rd Ra Rb 00000000011 Rd Rb Ra 1 unsigned Rd 0 0 if Rb gt Ra unsigned else Rd 0 1 ADDI Rd Ra Imm 001000 Rd Ra Imm Rd s Imm Ra RSUBI Rd Ra Imm 001001 Rd Ra Imm Rd s Imm Ra 1 ADDIC Rd Ra Imm 001010 Rd Ra Imm Rd s Imm Ra C RSUBIC Rd Ra Imm 001011 Rd Ra Imm Rd s Imm Ra C ADDIK Rd Ra Imm 001100 Rd Ra Imm Rd s Imm Ra RSUBIK Rd Ra Imm 001101 Rd Ra Imm Rd s Imm Ra 1 MicroBlaze Processor Reference Guide www xilinx com 15 UG081 v6 0 June 1 2006 1 800 255 7778 X XILINX Table 1 6 MicroBlaze Instruction Set Summary Continued Chapter 1 MicroBlaze Architecture Type A 0 5 6 10 11 15 16 20 21 31 Semantics Type B 0 5 6 10 11 15 16 31 ADDIKC Rd RaImm 001110 Rd Ra Imm Rd s Imm Ra C RSUBIKC Rd Ra JImm_ 001111 Rd Ra Imm Rd s Imm Ra C MUL Rd Ra Rb 010000 Rd Ra Rb 00000000000 Rd Ra Rb BSRL Rd Ra Rb 010001 Rd Ra Rb 00000000000 Rd 0 amp Ra gt gt Rb BSRA Rd Ra Rb 010001 Rd Ra Rb 01000000000 Rd s Ra gt gt Rb BSLL Rd Ra Rb 010001 Rd Ra Rb 10000000000 Rd Ra lt lt Rb amp 0 MULI Rd Ra Imm 011000 Rd Ra Imm Rd Ra s Imm BSRLI Rd Ra Imm 011001 Rd Ra 00000000000 amp Rd 0 amp Ra
46. D FSLx get data from FSL x blocking nget rD FSLx get data from FSL x non blocking cget rD FSLx get control from FSL x blocking ncget rD FSLx get control from FSL x non blocking 0110 11 rD 0 00000 nc 000000000 0 FSLx 0 6 11 16 29 31 Description MicroBlaze will read from the FSLx interface and place the result in register rD The get instruction has four variants The blocking versions when n bit is 0 will stall microblaze until the data from the FSL interface is valid The non blocking versions will not stall microblaze and will set carry to 0 if the data was valid and to 1 if the data was invalid In case of an invalid access the destination register contents is undefined The get and nget instructions expect the control bit from the FSL interface to be 0 If this is not the case the instruction will set MSR FSL_Error to 1 The cget and ncget instructions expect the control bit from the FSL interface to be 1 If this is not the case the instruction will set MSR FSL_Error to 1 Pseudocode rD lt FSLx if n 1 then MSR Carry lt not FSLx Exists bit if FSLx Control bit c then MSR FSL_Error lt 1 Registers Altered e rD e MSRI FSL_Error e MSR Carry Latency 2 cycles For blocking instructions MicroBlaze will first stall until valid data is available Note For nget and ncget a rsubc instruction can be used for counting down a index variable
47. Description 05 49 LMB Signal Interlace x sigs poe nese a Ua ye he ete cea eG avg REE oe 49 EMB Transact ons s seie epet aaao ieia en eee hone eetlete a ag mets EE 51 Read and Write Data Steering 6 666 enn ees 53 Fast Simplex Link FSL Interface Description 0 008 54 Master PSL Signal Interface 6 a A E 54 Slave FSL Signal Interface seien Aea i enn eens 54 FSL Transactions serce cts aloes a cee desks dees Se ede ESE ed ee EERE EERE HES 55 Xilinx CacheLink XCL Interface Description 0005 55 CacheLink Signal Interface sece enseia aa a E O aE EA k 56 CacheLink Transactions 0 00 c cece a 57 Debug Interface Description 2 cis cise cea ivan ene aden oo wen minke oie 59 Trace Interface DescriptiOt 66 ciicees pases head bh iiG bes peL EEN Ee be 59 MicroBlaze Core Configurability 0 00 cece cece eee eee 61 Chapter 3 MicroBlaze Application Binary Interface SCOPE ccicnxviiensgusieiucistucitvaextescstdetaeeeeiedsreaiseiecstaanciees 65 Data TY POS e A pagan Minne punt E E EE Renee ereke hd E gts 65 Register Usage Conventions 0 0 06 e cece ete nee 66 Stack Convention esi iiels wedi Le Oe eda ara eed ke eda be ede eee 67 Calling GOnVentlOn cipi iari e a E te fares cartels Hae Geeta ene ants seve 69 Memory Model gaia ces fetid Lhe Ae oe ee eee xed Seed eneid ee 69 Small data at a c eiise ces dees Ae ees Reese y aai KE
48. Instr_Addr 0 31 O Address bus Byte_Enable 0 3 Byte_Enable 0 3 not used O Byte enables Data_Write 0 31 Data_Write 0 31 not used O Write data bus AS D_AS ILAS O Address strobe Read_Strobe Read_Strobe IFetch O Read in progress Write_Strobe Write_Strobe not used O Write in progress Data_Read 0 31 Data_Read 0 31 Instr 0 31 I Read data bus Ready DReady IReady I Ready for next transfer Clk Clk Clk I Bus clock Addr 0 31 The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer It is valid only when AS is high In multicycle accesses accesses requiring more than one clock cycle to complete Addr 0 31 is valid only in the first clock cycle of the transfer Byte_Enable 0 3 The byte enable signals are outputs from the core and indicate which byte lanes of the data bus contain valid data Byte_Enable 0 3 is valid only when AS is high In multicycle accesses accesses requiring more than one clock cycle to complete Byte_Enable 0 3 is valid only in the first clock cycle of the transfer Valid values for Byte_Enable 0 3 are shown in the following table Table 2 3 Valid Values for Byte_Enable 0 3 Byte Lanes Used Byte_Enable 0 3 Data 0 7 Data 8 15 Data 16 23 Data 24 31 0000 0001 x 0010 x 0100 x MicroBlaze Processor Reference Guide www xilinx com 49 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapt
49. LMB instruction fetch Instr 0 31 ILMB I Instruction interface LMB read data bus IReady ILMB I Instruction interface LMB data ready FSLO_M FSL7_M MFSL O Master interface to output FSL channels FSLO_S FSL7_S SFSL I Slave interface to input FSL channels ICache_FSL_ in IXCL_S IO Instruction side CacheLink FSL slave interface MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 47 XILINX Chapter 2 MicroBlaze Signal Interface Description Table 2 1 Summary of MicroBlaze Core I O Continued Signal Interface 1 0 Description ICache_FSL_out IXCL_M IO Instruction side CacheLink FSL master interface DCache_FSL_in DXCL_S IO Data side CacheLink FSL slave interface DCache_FSL_out DXCL_M IO Data side CacheLink FSL master interface Interrupt Core I Interrupt Reset Core I Core reset active high Should be held for at least 16 cycles Clk Core I Clock Debug_Rst Core I Reset signal from OPB JTAG UART active high Should be held for at least 16 cycles Ext_BRK Core I Break signal from OPB JTAG UART Ext_NM_BRK Core I Non maskable break signal from OPB JTAG UART Dbg_ Core IO Debug signals from OPB MDM Valid_Instr Core O Trace Valid instruction in EX stage PC_Ex Core O Trace Address for EX stage instruction Reg_Write Core O Trace EX stage instruction writes to the register file
50. MSR Continued Bits 22 Name EIP Description Exception In Progress 0 No hardware exception in progress 1 Hardware exception in progress Read Write Reset Value 0 23 EE Exception Enable 0 Hardware exceptions disabled 1 Hardware exceptions enabled Read Write 24 DCE Data Cache Enable 0 Data Cache is Disabled 1 Data Cache is Enabled Read Write 25 DZ Division by Zero 0 No division by zero has occurred 1 Division by zero has occurred Read Write 26 ICE Instruction Cache Enable 0 Instruction Cache is Disabled 1 Instruction Cache is Enabled Read Write 27 FSL FSL Error 0 FSL get put had no error 1 FSL get put had mismatch in control type Read Write 28 BIP Break in Progress 0 No Break in Progress 1 Break in Progress Source of break can be software break instruction or hardware break from Ext_Brk or Ext_NM_Brk pin Read Write MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 23 XILINX Chapter 1 MicroBlaze Architecture Table 1 9 Machine Status Register MSR Continued Bits Name Description Reset Value 29 C Arithmetic Carry 0 0 No Carry Borrow 1 Carry No Borrow Read Write 30 IE Interrupt Enable 0 0 Interrupts disabled 1 Interrupts enabled Read Write 31 BE Buslock Enable 0 0 Buslock disabled on data side OPB 1 Buslock enab
51. MicroBlaze Processor Reference Guide Embedded Development Kit EDK 8 2i UG081 v6 0 June 1 2006 XILINX 2006 Xilinx Inc All Rights Reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners NOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this feature application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose MicroBlaze Processor Reference Guide www xilinx com UG081 v6 0 June 1 2006 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 The following table shows the revision history for this document Date Version Revision 10 01 02 1 0 Xilinx EDK 3 1 release 03 11 03 2 0 Xilinx EDK 3 2 release 09 24 03 3 0 Xilinx EDK 6 1 release 02 20 04 3 1 Xilinx EDK 6 2 release 08
52. NESE Cad etn EERE ARE BEES 69 Wate at Cass eii wield cue tng Bidet wg Bing tek einen aye E a lice pede Bee iors NE ag aiaa 69 Common un initialized area 0 0 ccc cece eee eee eee 69 Literals or COnStANMtS rees cies Wea ces Oa Ae eee a ghee Pada A 69 Interrupt and Exception Handing iii dea tet ey taiaenetageween eens 70 Chapter 4 MicroBlaze Instruction Set Architecture SUMMATY occ ci evnade Hance here REEE EREE EED E adh eee ecee atau 71 Nb atOny 5 545076 0 arnt Ret Martie ee Ha Mea ees Aenea hd or ER ee A Base aes 71 FOETUS a cece ac te hove ee a e e area ace tee Reece te tee ens 72 THSEEUCHLONS srann di ocaeas actis nathan Metin s Ree Saeed EREEREER EE ERA 72 UG081 v6 0 June 1 2006 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 S7 XILINX Preface About This Guide Welcome to the MicroBlaze Processor Reference Guide This document provides information about the 32 bit soft processor MicroBlaze which is part of the Embedded Processor Development Kit EDK The document is intended as a guide to the MicroBlaze hardware architecture Manual Contents This manual discusses the following topics specific to MicroBlaze soft processor e Core Architecture e Bus Interfaces and Endianness e Application Binary Interface e Instruction Set Architecture Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access f
53. Processor Version Register PVR The Processor Version Register is controlled by the C_PVR configuration option on MicroBlaze When C_PVR is set to 0 the processor does not implement any PVR and MSR PVR 0 If C_PVR is set to 1 then MicroBlaze implements only the first register PVRO and if set to 2 all 12 PVR registers PVRO to PVR11 are implemented When read with the MFS instruction the PVR is specified by setting Sa 0x200x with x being the register number between 0x0 and OxB MicroBlaze Processor Reference Guide www xilinx com 27 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Table 1 15 Processor Version Register 0 PVRO Bits Name Description Value 0 CFG PVR implementation 0 basic Based on C_PVR 1 full 1 BS Use barrel shifter C_USE_BARREL 2 DIV Use divider C_USE_DIV 3 MUL Use hardware multiplier C_USE_HW_MUL 4 FPU Use FPU C_USE_FPU 5 EXC Use any type of exceptions Based on C_ _EXCEPTION 6 ICU Use instruction cache C_USE_ICACHE 7 DCU Use data cache C_USE_DCACHE 8 15 Reserved 0 16 23 MBV MicroBlaze release version code Release Specific 0x1 v5 00 a 24 31 USR1 User configured value 1 C_PVR_USER1 Table 1 16 Processor Version Register 1 PVR1 Bits Name Description Value 0 31 USR2 User configured value 2 C_PVR_USER2 Table 1 17 Processor Version Register 2 P
54. R EC lt 00110 else if isNaN rB rA and then rD signInfinite rB rA FSR OF amp 1 ESR EC lt 00110 else rD amp rB rA Registers Altered e rD unless an FP exception is generated in which case the register is unchanged e ESR EC e FSR IO UROF DO Latency 4 cycles Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1 MicroBlaze Processor Reference Guide www xilinx com 101 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture fmul Floating Point Arithmetic Multiplication fmul rD rA rB Multiply 010110 rD rA rB 00100000000 0 6 11 16 21 31 Description The floating point value in rA is multiplied with the floating point value in rB and the result is placed into register rD Pseudocode if isDnz rA or isDnz rB then rD lt OxFFCO0O0000 FSR DO amp 1 ESR EC lt 00110 else if isSigNaN rA or isSigNaN rB or isZero rA and isInfinite rB or isZero rB and isInfinite rA then rD OxFFC0O0000 FSR IO amp 1 ESR EC lt 00110 else if isQuietNaN rA or isQuietNaN rB then rD OxFFCO0O0000 else if isDnz rB rA then rD signZero rA rB FSR UF amp 1 ESR EC lt 00110 else if isNaN rB rA and then rD signInfinite rB rA FSR OF amp 1 ESR EC lt 00110 else rD lt rB
55. RREL 1 98 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Instructions XILINX cmp Integer Compare cmp rD rA rB compare rB with rA signed cmpu rD rA rB compare rB with rA unsigned 00010 1 rD rA rB 000000000U 1 0 6 11 16 21 31 Description The contents of register rA is subtracted from the contents of register rB and the result is placed into register rD The MSB bit of rD is adjusted to shown true relation between rA and rB If the U bit is set rA and rB is considered unsigned values If the U bit is clear rA and rB is considered signed values Pseudocode cD lt rB fA 1 cD MSB lt rA gt rB Registers Altered e rD Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 99 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture fadd Floating Point Arithmetic Add fadd rD rA rB Add 010110 rD rA rB 0000000000 0 0 6 11 16 21 31 Description The floating point sum of registers rA and rB is placed into register rD Pseudocode if isDnz rA or isDnz rB then rD lt OxFFC0O0000 FSR DO amp 1 ESR EC lt 00110 else if isSigNaN rA or isSigNaN rB or isPosInfinite rA and isNegInfinite rB or isNegInfinite rA and isPosInfinite rB then rD O0OxFFC00000 FSR IO amp 1 ESR EC lt 00110 else if
56. Ra lt 0 18 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX Table 1 6 MicroBlaze Instruction Set Summary Continued Type A 0 5 6 10 11 15 16 20 21 31 Semantics Type B 0 5 6 10 11 15 16 31 BGTD Ra Rb 100111 10100 Ra Rb 00000000000 PC PC Rb if Ra gt 0 BGED Ra Rb 100111 10101 Ra Rb 00000000000 PC PC Rb if Ra gt 0 ORI Rd Ra Imm 101000 Rd Ra Imm Rd Ra or s Imm ANDI Rd Ra Imm 101001 Rd Ra Imm Rd Ra and s Imm XORI Rd Ra Imm 101010 Rd Ra Imm Rd Ra xor s Imm ANDNI Rd Ra Imm 101011 Rd Ra Imm Rd Ra and s Imm IMM Imm 101100 00000 00000 Imm Imm 0 15 Imm RTSD Ra Imm 101101 10000 Ra Imm PC Ra s Imm RTID Ra Imm 101101 10001 Ra Imm PC Ra s Imm MSRI IE 1 RTBD Ra Imm 101101 10010 Ra Imm PC Ra s Imm MSRIBIP 0 RTED Ra Imm 101101 10100 Ra Imm PC Ra s Imm MSR EE 1 MSRI EIP 0 ESR 0 BRI Imm 101110 00000 00000 Imm PC PC s Imm BRID Imm 101110 00000 10000 Imm PC PC s Imm BRLID Rd Imm 101110 Rd 10100 Imm PC PC s Imm Rd PC BRAI Imm 101110 00000 01000 Imm PC s Imm BRAID Imm 101110 00000 11000 Imm PC s Imm BRALID Rd Imm 101110 Rd 11100 Imm PC s Imm Rd PC BRKI Rd Imm 101110 Rd 01100 Imm PC s Imm Rd PC MSRI
57. Register Usage Conventions The register usage convention for MicroBlaze is given in Table 3 2 Table 3 2 Register usage conventions Register Type Enforcement Purpose RO Dedicated HW Value 0 R1 Dedicated SW Stack Pointer R2 Dedicated SW Read only small data area anchor R3 R4 Volatile SW Return Values Temporaries R5 R10 Volatile SW Passing parameters Temporaries R11 R12 Volatile SW Temporaries R13 Dedicated SW Read write small data area anchor R14 Dedicated HW Return address for Interrupt R15 Dedicated SW Return address for Sub routine R16 Dedicated HW Return address for Trap Debugger R17 Dedicated HW if configured Return Address for Exceptions to support HW exceptions else SW R18 Dedicated SW Reserved for Assembler R19 R31 Non volatile SW Must be saved across function calls Callee save RPC Special HW Program counter RMSR Special HW Machine Status Register REAR Special HW Exception Address Register RESR Special HW Exception Status Register RFSR Special HW Floating Point Status Register RBTR Special HW Branch Target Register RPVRO Special HW Processor Version Register 0 thru 11 RPVR11 The architecture for MicroBlaze defines 32 general purpose registers GPRs These registers are classified as volatile non volatile and dedicated e The volatile registers a k a caller save are used as temporaries and do not retain values across the function
58. Reserved by Xilinx for 0x00000028 future use 0x0000004F MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 33 XILINX Chapter 1 MicroBlaze Architecture Reset When a Reset or Debug _Rst 1 occurs MicroBlaze will flush the pipeline and start fetching instructions from the reset vector address 0x0 Both external reset signals are active high and should be asserted for a minimum of 16 cycles Equivalent Pseudocode PC lt 0x00000000 SR lt C_RESET_MSR see MicroBlaze Core Configurability in Chapter 2 EAR amp 0 ESR lt 0 FSR lt 0 Hardware Exceptions MicroBlaze can be configured to trap the following internal error conditions illegal instruction instruction and data bus error and unaligned access The divide by zero exception can only be enabled if the processor is configured with a hardware divider C_USE_DIV 1 When configured with a hardware floating point unit C_USE_FPU 1 it can also trap the following floating point specific exceptions underflow overflow float division by zero invalid operation and denormalized operand error A hardware exception will cause MicroBlaze to flush the pipeline and branch to the hardware exception vector address 0x20 The exception will also load the decode stage program counter value into the general purpose register R17 The execution stage instruction in the exception cyc
59. SL_OUT_Data with the control bit set low DCACHE_FSL_OUT_Control 0 to indicate a read access 3 Wait until DCACHE_FSL_IN_Exists goes high to indicate that data is available 4 Store the word from DCACHE_FSL_IN_Data to the cache 5 Forward the critical word to the execution unit in order to resume execution 6 Repeat 3 and 4 for the subsequent 3 words in the cache line Data Cache Write Note that writes to the data cache always are write through and thus there will be a write over the CacheLink regardless of whether there was a hit or miss in the cache On a write the cache controller will perform the following sequence 1 If DCACHE_FSL_OUT_Full 1 then stall until it goes low 2 Write the missed address to DCACHE_FSL_OUT_Data with the control bit set high DCACHE_FSL_OUT_Control 1 to indicate a write access The two least significant bits 30 31 of the address are used to encode byte and half word enables 0b00 byte0 1 Byte and halfword read misses are naturally expected to return complete words the cache controller then provides the execution unit with the correct bytes 58 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Debug Interface Description XILINX 0b01 byte1 or halfword0 0x10 byte2 and 0x11 byte3 or halfword1 The selection of half word or byte access is based on the control bit for the data word in step 4 If DCACHE_FSL_OUT_Full 1 then stall until it g
60. UG081 v6 0 June 1 2006 Instructions XILINX br Unconditional Branch br rB Branch bra rB Branch Absolute brd rB Branch with Delay brad rB Branch Absolute with Delay brid rD rB Branch and Link with Delay brald rD rB Branch Absolute and Link with Delay 100110 rD DA LOO rB 00000000000 0 6 11 16 21 31 Description Branch to the instruction located at address determined by rB The mnemonics brid and brald will set the L bit If the L bit is set linking will be performed The current value of PC will be stored in rD The mnemonics bra brad and brald will set the A bit If the A bit is set it means that the branch is to an absolute value and the target is the value in rB otherwise it is a relative branch and the target will be PC rB The mnemonics brd brad brld and brald will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode if L 1 then rD PC if A 1 then PC lt rB else PC lt PC B if D 1 then allow following instruction to complete execution Registers Altered e rD e PC Lat
61. VR2 Bits Name Description Value 0 DOPB Data side OPB in use C_D_OPB 1 DLMB Data side LMB in use C_D_LMB 2 IOPB Instruction side OPB in use C_I_OPB 3 IOPB Instruction side OPB in use C_I_LMB 4 TRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE 5 TROPOS Interrupt edge is positive C_EDGE_IS_POSITIVE 6 16 Reserved 17 BS Use barrel shifter C_USE_BARREL 18 DIV Use divider C_USE_DIV 19 MUL Use hardware multiplier C_USE_HW_MUL 20 FPU Use FPU C_USE_FPU 21 24 Reserved 28 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Registers XILINX Table 1 17 Processor Version Register 2 PVR2 Continued Bits Name Description Value 25 OPOEXEC Generate exception for 0x0 C_OPCODE_0x0_ILLEGAL illegal opcode 26 UNEXEC Generate exception for C_UNALIGNED_EXCEPTION unaligned data access 27 OPEXEC Generate exception for any C_ILL_OPCODE_EXCEPTION illegal opcode 28 IOPBEXEC Generate exception for IOPB C_IOPB_BUS_EXCEPTION error 29 DOPBEXEC Generate exception for DOPB C_DOPB_BUS_EXCEPTION error 30 DIVEXEC Generate exception for division C_DIV_ZERO_EXCEPTION by zero 31 FPUEXEC Generate exceptions from FPU C_FPU_EXCEPTION Table 1 18 Processor Version Register 3 PVR3 Bits Name Description Value 0 DEBUG Use debug logic C_DEBUG_ENABLED 1 2 Reserved 3 6 PCBRK Number of
62. aced into register rD Bit 3 of the instruction labeled as K in the figure is set to a one for the mnemonic rsubik Bit 4 of the instruction labeled as C in the figure is set to a one for the mnemonic rsubic Both bits are set to a one for the mnemonic rsubikc When an rsubi instruction has bit 3 set rsubik rsubikc the carry flag will Keep its previous value regardless of the outcome of the execution of the instruction If bit 3 is cleared rsubi rsubic then the carry flag will be affected by the execution of the instruction When bit 4 of the instruction is set to a one rsubic rsubikc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared rsubi rsubik the content of the carry flag does not affect the execution of the instruction providing a normal subtraction Pseudocode if C 0 then rD lt sext IMM rA 1 else rD lt sext IMM rA MSR C if K 0 then MSR C lt CarryOut Registers Altered e rD e MSR C Latency 1 cycle Notes In subtractions Carry Borrow When the Carry is set by a subtraction it means that there is no Borrow and when the Carry is cleared it means that there is a Borrow By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for deta
63. and illegal operation as well as for the MicroBlaze specific exception denormalized operand error A floating point exception will inhibit the write to the destination register Rd This allows a floating point exception handler to operate on the uncorrupted register file Fast Simplex Link FSL MicroBlaze can be configured with up to eight Fast Simplex Link FSL interfaces each consisting of one input and one output port The FSL channels are dedicated uni directional point to point data streaming interfaces For detailed information on the FSL interface please refer to the FSL Bus data sheet DS449 The FSL interfaces on MicroBlaze are 32 bits wide A separate bit indicates whether the sent received word is of control or data type The get instruction in the MicroBlaze ISA is used to transfer information from an FSL port to a general purpose register The put instruction is used to transfer data in the opposite direction Both instructions come in 4 flavours blocking data non blocking data blocking control and non blocking control For a detailed description of the get and put instructions please refer to Chapter 4 MicroBlaze Instruction Set Architecture Hardware Acceleration using FSL Each FSL provides a low latency dedicated interface to the processor pipeline Thus they are ideal for extending the processors execution unit with custom hardware accelerators A simple example is illustrated in Figure 1 12 42 www xi
64. at can no longer be represented with full precision in a 32 bit format Rounding The MicroBlaze FPU only implements the default rounding mode Round to nearest specified in IEEE 754 By definition the result of any floating point operation should return the nearest single precision value to the infinitely precise result If the two nearest representable values are equally near then the one with its least significant bit zero is returned Operations All MicroBlaze FPU operations use the processors general purpose registers rather than a dedicated floating point register file see General Purpose Registers Arithmetic The FPU implements the following floating point operations e addition fadd e subtraction fsub e multiplication fmul e division fdiv MicroBlaze Processor Reference Guide www xilinx com 41 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Comparison The FPU implements the following floating point comparisons e compare less than femp It e compare equal femp eq e compare less or equal femp le e compare greater than femp gt e compare not equal femp ne e compare greater or equal femp ge e compare unordered femp un used for NaN Exceptions The floating point unit uses the regular hardware exception mechanism in MicroBlaze When enabled exceptions are thrown for all the IEEE standard conditions underflow overflow divide by zero
65. ata Type Table 1 3 Half Word Data Type Table 1 4 Byte Data Type Instructions Byte address n n 1 n 2 n 3 Byte label 0 1 2 3 Byte MSByte LSByte significance Bit label 0 31 Bit significance MSBit LSBit Byte address n n 1 Byte label 0 1 Byte MSByte LSByte significance Bit label 0 15 Bit significance MSBit LSBit Byte address n Bit label 0 7 Bit significance MSBit LSBit All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B Type A instructions have up to two source register operands and one destination register operand Type B instructions have one source register and a 16 bit immediate operand which can be extended to 32 bits by preceding the Type B instruction with an IMM instruction Type B instructions have a single destination register operand Instructions are provided in the following functional categories arithmetic logical branch load store and special Table 1 6 lists the MicroBlaze instruction set Refer to Chapter 4 MicroBlaze Instruction Set Architecture for more information on these instructions Table 1 5 describes the instruction set nomenclature used in the semantics of each instruction MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 13 X XILINX Chapter 1 MicroBlaze Architecture Table 1 5 Instruction Set Nom
66. bit in the Machine Status Register MSR is set to 1 On an interrupt the instruction in the execution stage will complete while the instruction in the decode stage is replaced by a branch to the interrupt vector address 0x10 The interrupt return address the PC associated with the instruction in the decode stage at the time of the interrupt is automatically loaded into general purpose register R14 In addition the processor also disables future interrupts by clearing the IE bit in the MSR The IE bit is automatically set again when executing the RTID instruction Interrupts are ignored by the processor if either of the break in progress BIP or exception in progress EIP bits in the MSR are set to 1 Latency The time it will take MicroBlaze to enter an Interrupt Service Routine ISR from the time an interrupt occurs depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors If MicroBlaze is configured to have a hardware divider the largest latency will happen when an interrupt occurs during the execution of a division instruction Equivalent Pseudocode ri4 amp PC PC lt 0x00000010 MSR IE amp 0 User Vector Exception The user exception vector is located at address 0x8 A user exception is caused by inserting a BRALID Rx 0x8 instruction in the software flow Although Rx could be any general purpose register Xilinx recommends using R15 for storing the user e
67. byte devices MicroBlaze does not support transfers that are larger than the addressed device These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface Data steering for read cycles is shown in Table 2 4 and data steering for write cycles is shown in Table 2 5 Table 2 4 Read Data Steering load to Register rD Register rD Data f A o rD 0 7 rD 8 15 rD 16 23 rD 24 31 11 0001 byte Byte3 10 0010 byte Byte2 01 0100 byte Bytel 00 1000 byte Byte0 10 0011 halfword Byte2 Byte3 00 1100 halfword Byte0 Byte1 00 1111 word Byte0 Bytel Byte2 Byte3 Table 2 5 Write Data Steering store from Register rD Write Data Bus Bytes Address Byte_Enable Transfer 30 31 0 3 Size Byte0 Bytel Byte2 Byte3 11 0001 byte rD 24 31 10 0010 byte rD 24 31 01 0100 byte rD 24 31 00 1000 byte rD 24 31 10 0011 halfword rD 16 23 rD 24 31 00 1100 halfword rD 16 23 rD 24 31 00 1111 word rD 0 7 rD 8 15 rD 16 23 rD 24 31 Note that other OPB masters may have more restrictive requirements for byte lane placement than those allowed by MicroBlaze OPB slave devices are typically attached left justified with byte devices attached to the most significant byte lane and halfword devices attached to the most significant halfword lane The MicroBlaze steering logic fully supports
68. ce Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX sra Shift Right Arithmetic sra rD rA 100100 rD rA 000000000000000 1 0 6 11 16 31 Description Shifts arithmetically the contents of register rA one bit to the right and places the result in rD The most significant bit of rA i e the sign bit placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in the Carry flag Pseudocode xD 0 lt rA 0 xD 1 31 lt rA 0 30 MSR C lt rA 31 Registers Altered e rD e MSRI C Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 139 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Src Shift Right with Carry src rD rA 100100 rD rA 000000000010000 1 0 6 11 16 31 Description Shifts the contents of register rA one bit to the right and places the result in rD The Carry flag is shifted in the shift chain and placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in the Carry flag Pseudocode cD 0 lt MSR C xD 1 31 lt rA 0 30 MSR C lt rA 31 Registers Altered e rD e MSRIC Latency 1 cycle 140 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX
69. ched The lookup is successful if the word and line valid bits are set and the tag address matches the instruction address tag segment On a cache miss the cache controller will request the new instruction over the instruction CacheLink IXCL interface and wait for the memory controller to return the associated cache line Instruction Cache Software Support MSR Bit The ICE bit in the MSR provides software control to enable and disable caches The contents of the cache are preserved by default when the cache is disabled The user can invalidate cache lines using the WIC instruction or using the hardware debug logic of MicroBlaze WIC Instruction Data Cache Overview 38 The optional WIC instruction C_ALLOW_ICACHE_WR 1 is used to invalidate cache lines in the instruction cache from an application For a detailed description please refer to Chapter 4 MicroBlaze Instruction Set Architecture The cache must be disabled MSR ICE 0 when the instruction is executed MicroBlaze may be used with an optional data cache for improved performance The cached memory range must not include addresses in the LMB address range The data cache has the following features e Direct mapped 1 way associative e Write through e User selectable cacheable memory address range e Configurable cache size and tag size e Caching over CacheLink XCL interface e Option to use 4 or 8 word cache lines www xilinx com MicroBlaze Process
70. croBlaze Signal Interface Description 32 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Reset Interrupts Exceptions and Break XILINX Reset Interrupts Exceptions and Break MicroBlaze supports reset interrupt user exception break and hardware exceptions The following section describes the execution flow associated with each of these events The relative priority starting with the highest is oo o oe p Noe Reset Break Interrupt Hardware Exception Non maskable Break User Vector Exception Table 1 27 defines the memory address locations of the associated vectors and the hardware enforced register file locations for return address Each vector allocates two addresses to allow full address range branching requires an IMM followed by a BRAI instruction The address range 0x28 to 0x4F is reserved for future software support by Xilinx Allocating these addresses for user applications is likely to conflict with future releases of EDK support software Table 1 27 Vectors and Return Address Register File Location Register File Event Vector Address Return Address Reset 0x00000000 0x00000004 User Vector Exception 0x00000008 0x0000000C Interrupt 0x00000010 R14 0x00000014 Break Non maskable hardware 0x00000018 Big Break Hardware 0x0000001C Break Software Hardware Exception 0x00000020 0x00000024 RE OEDI
71. ctions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 94 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX brk Break brk rD rB 100110 rD 0 1100 rB 00000000000 0 6 11 16 21 31 Description Branch and link to the instruction located at address value in rB The current value of PC will be stored in rD The BIP flag in the MSR will be set Pseudocode cD lt PC PC lt rB MSR BIP amp 1 Registers Altered e rD e PC e MSRIBIP Latency 3 cycles MicroBlaze Processor Reference Guide www xilinx com 95 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture brki Break Immediate brki rD IMM 101110 rD 01100 IMM 0 6 11 16 31 Description Branch and link to the instruction located at address value in IMM sign extended to 32 bits The current value of PC will be stored in rD The BIP flag in the MSR will be set Pseudocode cD amp PC PC lt sext IMM MSR BIP amp 1 Registers Altered e rD e PC e MSRIBIP Latency 3 cycles Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the
72. docode Addr lt rA sext IMM Addr 30 31 lt 00 Mem Addr lt rD 0 31 Register Altered e ESR S Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values MicroBlaze Processor Reference Guide www xilinx com 143 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture wdc Write to Data Cache wdc rA rB 10010000000 rA rB 00001100100 0 6 11 16 31 Description Write into the data cache tag The register rB value is not used Register rA contains the instruction address Bit 30 in rA is the new valid bit The WDC instruction should only be used when the data cache is disabled i e MSR DCE 0 Pseudocode DCache Tag rA Registers Altered e None Latency 1 cycle 144 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX wic Write to Instruction Cache wic rA rB 1 0010000 0 000 rA rB 0 0001101000 0 6 11 16 31 Description Write into the instruction cache tag The register rB value is not used Register rA contains the instruction address Bit 30 in rA is the new valid bit The WIC i
73. docode PC lt rA sext IMM allow following instruction to complete execution SR EE lt 1 SR EIP lt 0 ESR amp 0 Registers Altered e PC e MSR EE e MSR EIP e ESR Latency 2 cycles Note Convention is to use general purpose register r17 as rA This instruction requires that one or more of the MicroBlaze parameters C_ _EXCEPTION are set to 1 A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 131 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture rtsd Return from Subroutine rtsd rA IMM 101 10 314 1 00 0 0 rA IMM 0 6 11 16 31 Description Return from subroutine will branch to the location specified by the contents of rA plus the IMM field sign extended to 32 bits This instruction always has a delay slot The instruction following the RTSD is always executed before the branch target Pseudocode PC lt rA sext IMM allow following instruction to complete execution Registers Altered e PC Latency 2 cycles Note Convention is to use general purpose register r15 as rA A delay slot must not b
74. e D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 82 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX bgt Branch if Greater Than bgt rA rB Branch if Greater Than bgtd rA rB Branch if Greater Than with Delay 10011 1D0100 rA rB 0 000 00 000 000 000 0 6 11 16 21 31 Description Branch if rA is greater than 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic bgtd will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means t
75. e MicroBlaze parameter C_USE_FPU is set to 1 118 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX mul Multiply mul rD rA rB 010000 rD rA rB 00000000000 0 6 11 16 21 31 Description Multiplies the contents of registers rA and rB and puts the result in register rD This is a 32 bit by 32 bit multiplication that will produce a 64 bit result The least significant word of this value is placed in rD The most significant word is discarded Pseudocode rD lt LSW rA X rB Registers Altered e rD Latency 1 cycle Note This instruction is only valid if the target architecture has multiplier primitives and if present the MicroBlaze parameter C_USE_HW_MUL is set to 1 MicroBlaze Processor Reference Guide www xilinx com 119 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture muli Multiply Immediate muli rD rA IMM 011000 rD rA IMM 0 6 11 16 31 Description Multiplies the contents of registers rA and the value IMM sign extended to 32 bits and puts the result in register rD This is a 32 bit by 32 bit multiplication that will produce a 64 bit result The least significant word of this value is placed in rD The most significant word is discarded Pseudocode rD lt LSW rA X sext IMM Registers Altered e rD Latency 1 cycle Notes
76. e carry flag will Keep its previous value regardless of the outcome of the execution of the instruction If bit 3 is cleared rsub rsubc then the carry flag will be affected by the execution of the instruction When bit 4 of the instruction is set to a one rsubc rsubkc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared rsub rsubk the content of the carry flag does not affect the execution of the instruction providing a normal subtraction if C else 0 then rD amp rB rA 1 rD rB rA MSR C if K 0 then MSR C lt CarryOut e rD e MSR C Latency 1 cycle Notes In subtractions Carry Borrow When the Carry is set by a subtraction it means that there is no Borrow and when the Carry is cleared it means that there is a Borrow MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 127 XILINX Chapter 4 MicroBlaze Instruction Set Architecture rsubi Arithmetic Reverse Subtract Immediate rsubi rD rA IMM Subtract Immediate rsubic rD rA IMM Subtract Immediate with Carry rsubik rD rA IMM Subtract Immediate and Keep Carry rsubikc rD rA IMM Subtract Immediate with Carry and Keep Carry 001K C1 rD rA IMM 0 6 11 16 31 Description The contents of register rA is subtracted from the value of IMM sign extended to 32 bits and the result is pl
77. e permitted in all architectures The cache will use between 1 and 32 RAMB primitives 64 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 S7 XILINX Chapter 3 MicroBlaze Application Binary Interface Scope Data Types This document describes MicroBlaze Application Binary Interface ABI which is important for developing software in assembly language for the soft processor The MicroBlaze GNU compiler follows the conventions described in this document Hence any code written by assembly programmers should also follow the same conventions to be compatible with the compiler generated code Interrupt and Exception handling is also explained briefly in the document The data types used by MicroBlaze assembly programs are shown in Table 3 1 Data types such as data8 data16 and data32 are used in place of the usual byte half word and word egister Table 3 1 Data types in MicroBlaze assembly programs MicroBlaze data types Corresponding Size bytes for assembly programs ANSI C data types data8 char 1 data16 short 2 data32 int 4 data32 long int 4 data32 float 4 data32 enum 4 data16 data32 pointer 2 4 a Pointers to small data areas which can be accessed by global pointers are MicroBlaze Processor Reference Guide www xilinx com 65 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 3 MicroBlaze Application Binary Interface
78. e signals were last updated for MicroBlaze v5 00 a and are listed in Table 2 10 Table 2 10 MicroBlaze Trace signals Signal Name Description VHDL Type Direction Trace_Valid_Instr Valid instruction on trace std_logic output port Trace_Instruction Instruction code std_logic_vector output 0 to 31 Trace_PC Program counter std_logic_vector output 0 to 31 MicroBlaze Processor Reference Guide www xilinx com 59 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX 60 Chapter 2 MicroBlaze Signal Interface Description Table 2 10 MicroBlaze Trace signals Signal Name Description VHDL Type Direction Trace_Reg_Write Instruction writes to the std_logic output register file Trace_Reg_ Addr Destination register std_logic_vector output address 0 to 4 Trace_MSR_Reg Machine status register std_logic_vector output 0 to10 Trace_New_Reg_Value Destination register std_logic_vector output update value 0 to 31 Trace_Exception_Taken Instruction result in taken std_logic output exception Trace_Exception_Kind Exception type The std_logic_vector output description for the 0 to 3 exception type is documented in Table 2 11 Trace_Jump_Taken Branch instruction std_logic output evaluated true i e taken Trace_Delay_Slot Instruction is in delay slot std_logic output Trace_Data_Access Valid D side memory std_logic o
79. e used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 132 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX sb Store Byte sb rD rA rB 110100 rD rA rB 0000000000 0 0 6 11 16 21 31 Description Stores the contents of the least significant byte of register rD into the memory location that results from adding the contents of registers rA and rB Pseudocode Addr amp rA xB Mem Addr lt rD 24 31 Registers Altered e None Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 133 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture sbi Store Byte Immediate sbi rD rA IMM 111100 rD rA IMM 0 6 11 16 31 Description Stores the contents of the least significant byte of register rD into the memory location that results from adding the contents of register rA and the value IMM sign extended to 32 bits Pseudocode Addr lt rA sext IMM Mem Addr lt rD 24 31 Registers Altered e None Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field
80. egister only exists if the MicroBlaze processor is configured to use exceptions The register stores the branch target address for all delay slot branch instructions executed while MSR EIP 0 If an exception is caused by an instruction in a delay slot i e ESR DS 1 then the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in r17 When read with the MFS instruction the BTR is specified by setting Sa 0x000B BTR Figure 1 7 BTR 26 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Registers XILINX Table 1 13 Branch Target Register BTR Bits Name Description Reset Value 0 31 BTR Branch target address used by handler 0x00000000 when returning from an exception caused by an instruction in a delay slot Read only Floating Point Status Register FSR The Floating Point Status Register contains status bits for the floating point unit It can be read with an MFS and written with an MTS instruction When read or written the register is specified by setting Sa 0x0007 RESERVED IO DZ OF UF DO Figure 1 8 FSR Table 1 14 Floating Point Status Register FSR Bits Name Description Reset Value 0 26 Reserved undefined 27 IO Invalid operation 0 28 DZ Divide by zero 0 29 OF Overflow 0 30 UF Underflow 0 31 DO Denormalized operand error 0
81. ence Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX Table 1 5 Instruction Set Nomenclature Symbol Description lt lt x Bit shift left x bits and Logic AND or Logic OR xor Logic exclusive OR op if cond else op2 Perform op1 if condition cond is true else perform op2 amp Concatenate E g 0000100 amp Imm7 is the concatenation of the fixed field 0000100 and a 7 bit immediate value signed Operation performed on signed integer data type All arithmetic operations are performed on signed word operands unless otherwise specified unsigned Operation performed on unsigned integer data type float Operation performed on floating point data type Table 1 6 MicroBlaze Instruction Set Summary Type A 0 5 6 10 11 15 16 20 21 31 i Type B 0 5 6 10 11 15 16 31 anea ADD Rd Ra Rb 000000 Rd Ra Rb 00000000000 Rd Rb Ra RSUB Rd Ra Rb 000001 Rd Ra Rb 00000000000 Rd Rb Ra 1 ADDC Rd Ra Rb 000010 Rd Ra Rb 00000000000 Rd Rb Ra C RSUBC Rd Ra Rb 000011 Rd Ra Rb 00000000000 Rd Rb Ra C ADDK Rd Ra Rb 000100 Rd Ra Rb 00000000000 Rd Rb Ra RSUBK Rd Ra Rb 000101 Rd Ra Rb 00000000000 Rd Rb Ra 1 ADDKC Rd Ra Rb 000110 Rd Ra Rb 00000000000 Rd Rb Ra C RSUBKC Rd Ra Rb 000111 Rd Ra Rb 00000000000 Rd Rb Ra C
82. ence Guide www xilinx com 51 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description Back to Back Write Operation Clk i ee i er Addr Al Byte_Enable 1 BEI T T Data_Write AS iy i i I I I I I I Read_Strobe i Write_Strobe Data_Read Ready _ Figure 2 4 LMB Back to Back Write Operation Single Cycle Back to Back Read Operation Clk Sie Addr i ao N AD i Byte Enable X m COO Data_Write i i i i AS _if O lt 7 Read_Strobe iy i i i Write_Strobe l l Data_Read i DO DI D2 Ready l l l Figure 2 5 LMB Single Cycle Back to Back Read Operation Back to Back Mixed Read Write Operation Clk TD eT O a O Addr i AO Al i Byte_Enable CECE e aS S Data_Write X DO X i i X AS COS a a j i i I Read_Strobe i I I Write_Strobe l i Data_Read X D1 LA X I I I Ready i 1 i 1 I Figure 2 6 Back to Back Mixed Read Write Operation 52 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 XILINX Local Memory Bus LMB Interface Description Read and Write Data Steering The MicroBlaze data side bus interface performs the read steering and write steering required to support the following transfers e byte halfword and word transfers to word devices e byte and halfword transfers to halfword devices e byte transfers to
83. enclature Symbol Description Ra RO R31 General Purpose Register source operand a Rb RO R31 General Purpose Register source operand b Rd RO R31 General Purpose Register destination operand SPR x Special Purpose Register number x MSR Machine Status Register SPR 1 ESR Exception Status Register SPR 5 EAR Exception Address Register SPR 3 FSR Floating Point Unit Status Register SPR 7 PVRx Processor Version Register where x is the register number SPR 8192 x BTR Branch Target Register SPR 11 PC Execute stage Program Counter SPR 0 x y Bit y of register x x y z Bit range y to z of register x x Bit inverted value of register x Imm 16 bit immediate value Immx x bit immediate value FSLx 3 bit Fast Simplex Link FSL port designator where x is the port number C Carry flag MSR 29 Sa Special Purpose Register source operand Sd Special Purpose Register destination operand s x Sign extend argument x to 32 bit value Addr Memory contents at location Addr data size aligned Assignment operator Equality comparison l Inequality comparison gt Greater than comparison gt Greater than or equal comparison lt Less than comparison lt Less than or equal comparison Arithmetic add Arithmetic multiply Arithmetic divide gt gt x Bit shift right x bits 14 www xilinx com MicroBlaze Processor Refer
84. ency 2 cycles if the D bit is set 3 cycles if the D bit is not set MicroBlaze Processor Reference Guide www xilinx com 91 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Note The instructions brl and bral are not available A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 92 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX bri Unconditional Branch Immediate bri IMM Branch Immediate brai IMM Branch Absolute Immediate brid IMM Branch Immediate with Delay braid IMM Branch Absolute Immediate with Delay brlid rD IMM Branch and Link Immediate with Delay bralid rD IMM Branch Absolute and Link Immediate with Delay 10111 0 rD D ALO O IMM 0 6 11 16 31 Description Branch to the instruction located at address determined by IMM sign extended to 32 bits The mnemonics brlid and bralid will set the L bit If the L bit is set linking will be performed The current value of PC will be stored in rD The mnemonics brai braid and bralid will set the A bit If the A bit is set it means that the branch is to an absolute
85. er 2 MicroBlaze Signal Interface Description Table 2 3 Valid Values for Byte_Enable 0 3 Byte Lanes Used Byte_Enable 0 3 Data 0 7 Data 8 15 Data 16 23 Data 24 31 ooo aawo e a e e S 0011 x x 1100 x x 1111 x x x x Data_Write 0 31 The write data bus is an output from the core and contains the data that is written to memory It becomes valid when AS is high and goes invalid in the clock cycle after Ready is sampled high Only the byte lanes specified by Byte_Enable 0 3 contain valid data AS The address strobe is an output from the core and indicates the start of a transfer and qualifies the address bus and the byte enables It is high only in the first clock cycle of the transfer after which it goes low and remains low until the start of the next transfer Read_ Strobe The read strobe is an output from the core and indicates that a read transfer is in progress This signal goes high in the first clock cycle of the transfer and remains high until the clock cycle after Ready is sampled high If a new read transfer is started in the clock cycle after Ready is high then Read_Strobe remains high Write_Strobe The write strobe is an output from the core and indicates that a write transfer is in progress This signal goes high in the first clock cycle of the transfer and remains high until the clock cycle after Ready is sampled high If a new write transfer is started in the clock cycle afte
86. for FSR The value read from MSR may not include effects of the immediately preceding instruction dependent on pipeline stall behavior A NOP should be inserted before the MFS instruction to guarantee correct MSR value EAR and ESR are only valid as operands when at least one of the MicroBlaze C_ _ EXCEPTION parameters are set to 1 FSR is only valid as an operand when the C_USE_FPU and C_FPU_EXCEPTION parameters are set to 1 MicroBlaze Processor Reference Guide www xilinx com 115 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture ms relr Read MSR and clear bits in MSR msrelr rD Imm 100101 rD 0000 1 0 0 imm14 0 6 11 16 17 18 3i Description Copies the contents of the special purpose register MSR into register rD Bit positions in the IMM value that are 1 are cleared in the MSR Bit positions that are 0 in the IMM value are left untouched Pseudocode rD lt MSR MSR lt MSR A IMM Registers Altered e rD e MSR Latency 1 cycle Note MSRCLR will affect some MSR bits immediately e g Carry while the remaining bits will take effect one cycle after the instruction has been executed The immediate values has to be less than 214 Only bits 18 to 31 of the MSR can be cleared 116 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX m
87. for read write and byte enable encoding DCACHE_FSL_OUT_Full FSL access buffer for D std_logic input side read accesses is full CacheLink Transactions All individual CacheLink accesses follow the FSL FIFO based transaction protocol Access information is encoded over the FSL data and control signals e g DCACHE_FSL_OUT_Data DCACHE_FSL_OUT_Control ICACHE_FSL_IN_Data and ICACHE_FSL_IN_Control Information is sent stored by raising the write enable signal e g DCACHE_FSL_OUT_Write The sender is only allowed to write if the full signal from the receiver is inactive e g DCACHE_FSL_OUT_Full 0 The full signal is not used by the instruction cache controller Information is received loaded by raising the read signal e g ICACHE_FSL_IN_Read The receiver is only allowed to read as long as the sender signals that new data exists e g ICACHE_FSL_IN_Exists 1 For details on the generic FSL protocol please refer to the Fast Simplex Link FSL bus data sheet DS449 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 57 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description The CacheLink solution uses one incoming slave and one outgoing master FSL per cache controller The outgoing FSL is used to send access requests while the incoming FSL is used for receiving the requested cache lines CacheLink also uses a specific encoding of
88. from adding the contents of register rA and the value IMM sign extended to 32 bits The data is placed in register rD Pseudocode Addr lt rA sext IMM Addr 30 31 lt 00 rD lt Mem Addr Registers Altered e rD unless unaligned data access exception is generated in which case the register is unchanged e ESR W Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 114 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX mfs Move From Special Purpose Register mfs rD rS 10010 1 rD 0000 0 1 0 rs 0 6 11 16 18 31 Description Copies the contents of the special purpose register rS into register rD Pseudocode switch rs case 0x0000 rD lt PC case 0x0001 rD lt MSR case 0x0003 rD lt EAR case 0x0005 rD lt ESR case 0x0007 rD amp FSR case 0x000B rD lt BIR case 0x200x rD lt PVR x where x 0 to 11 default rD lt Undefined Registers Altered e rD Latency 1 cycle Note To refer to special purpose registers in assembly language use rpc for PC rmsr for MSR rear for EAR resr for ESR and rfsr
89. gure 1 3 PC Table 1 8 Program Counter PC Bits Name Description Reset Value 0 31 PC Program Counter 0x00000000 Address of executing instruction i e mfs r2 0 will store the address of the mfs instruction itself in R2 Machine Status Register MSR The Machine Status Register contains control and status bits for the processor It can be read with an MFS instruction When reading the MSR bit 29 is replicated in bit 0 as the carry copy MSR can be written using either an MTS instruction or the dedicated MSRSET and MSRCIR instructions When writing to the MSR some of the bits will takes effect immediately e g Carry and the remaining bits take effect one clock cycle later Any value written to bit 0 is discarded When used with an MTS or MFS instruction the MSR is specified by setting Sx 0x0001 CA EEE CC RESERVED PVR EIP EE DCE DZ ICE FSL BIP C IE BE Figure 1 4 MSR Table 1 9 Machine Status Register MSR Bits Name Description Reset Value 0 CC Arithmetic Carry Copy 0 Copy of the Arithmetic Carry bit 29 CC is always the same as bit C 1 20 Reserved 21 PVR Processor Version Register exists Based on 0 No Processor Version Register option 1 Processor Version Register exists C_PVR Read only 22 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Registers XILINX Table 1 9 Machine Status Register
90. hat there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA gt 0 then PC lt PC rB else PC lt PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 83 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture bgti Branch Immediate if Greater Than bgti rA IMM Branch Immediate if Greater Than bgtid rA IMM Branch Immediate if Greater Than with Delay 10111 1D0100 rA IMM 0 6 11 16 31 Description Branch if rA is greater than 0 to the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC IMM The mnemonic bgtid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruct
91. hed when executing a taken branch The fetch pipeline stage is then reloaded with a new instruction from the calculated branch address A taken branch in MicroBlaze takes three clock cycles to execute two of which are required for refilling the pipeline To reduce this latency overhead MicroBlaze supports branches with delay slots Delay Slots When executing a taken branch with delay slot only the fetch pipeline stage in MicroBlaze is flushed The instruction in the decode stage branch delay slot is allowed to complete This technique effectively reduces the branch penalty from two clock cycles to one Branch instructions with delay slots have a D appended to the instruction mnemonic For example the BNE instruction will not execute the subsequent instruction does not have a delay slot whereas BNED will execute the next instruction before control is transferred to the branch location A delay slot must not contain the following instructions IMM branch or break Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed Instructions that could cause recoverable exceptions e g unaligned word or halfword load and store are allowed in the delay slot If an exception is caused in a delay slot the ESR DS bit will be set and the exception handler is responsible for returning the execution to the branch target stored in the special purpose register BTR rather than the sequential return addre
92. how the stack is maintained are shown in Figure 3 2 High Memory SP a ee al SP SP SP Low Memory X9584 68 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Memory Model XILINX Figure 3 2 Stack Frame Calling Convention The caller function passes parameters to the callee function using either the registers R5 through R10 or on its own stack frame The callee uses the caller s stack area to store the parameters passed to the callee Refer to Figure 3 2 The parameters for Func 2 are stored either in the registers R5 through R10 or on the stack frame allocated for Func 1 Memory Model The memory model for MicroBlaze classifies the data into four different parts Small data area Global initialized variables which are small in size are stored in this area The threshold for deciding the size of the variable to be stored in the small data area is set to 8 bytes in the MicroBlaze C compiler mb gcc but this can be changed by giving a command line option to the compiler Details about this option are discussed in the GNU Compiler Tools chapter 64K bytes of memory is allocated for the small data areas The small data area is accessed using the read write small data area anchor R13 and a 16 bit offset Allocating small variables to this area reduces the requirement of adding Imm instructions to the code for accessing global variables Any variable in the small data
93. ils on using 32 bit immediate values 128 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX rtbd Return from Break rtbd rA IMM 10110110010 rA IMM 0 6 11 16 a Description Return from break will branch to the location specified by the contents of rA plus the IMM field sign extended to 32 bits It will also enable breaks after execution by clearing the BIP flag in the MSR This instruction always has a delay slot The instruction following the RTBD is always executed before the branch target That delay slot instruction has breaks disabled Pseudocode PC rA sext IMM allow following instruction to complete execution MSR BIP lt 0 Registers Altered e PC e MSR BIP Latency 2 cycles Note Convention is to use general purpose register r16 as rA A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 129 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture rtid Return from Interrupt rtid rA IMM 011011000 1 rA IMM 6 11 16 31
94. in the FSL FIFO If the FSL FIFO is empty the processor stalls at this instruction until the FSL exists flag is set In the non blocking mode nget and ncget instructions the transfer is completed in two clock cycles irrespective of whether or not the FSL was empty In the case the FSL was empty the transfer of data does not take place and the carry bit is set in the MSR Xilinx CacheLink XCL Interface Description Xilinx CacheLink XCL is a high performance solution for external memory accesses The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL buffers e g the MCH_OPB_SDRAM This method has the lowest latency and minimal number of instantiations see Figure 2 7 Schematic Example MHS code BEGIN microblaze Memory BUS_INTERFACE IXCL myIXCL Controller END BEGIN mch_opb_sdram BUS_INTERFACE MCH0 myIXCL END MicroBlaze Figure 2 7 CacheLink connection with integrated FSL buffers only Instruction cache used in this example MicroBlaze Processor Reference Guide www xilinx com 55 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description The MicroBlaze CacheLink interface can also connect to an Fast Simplex Link FSL interfaced memory controller via explicitly instantiated FSL master slave pair however this topology is considered deprecated and is not recommended for new designs The
95. ing the 512 instruction words and 1 RAMB16 for 128 cache line entries each consisting of 3 bits of tag 4 word valid bits 1 line valid bit In total 2 RAMB16 primitives Data Cache Operation The MicroBlaze data cache implements a write through protocol A store to an address within the cacheable range will provided that the cache is enabled generate an equivalent byte halfword or word write over the data CacheLink DXCL to external memory The write will also update the cached data if the target address word is in the cache i e the write is a cache hit A write cache miss does not load the associated cache line into the cache MicroBlaze Processor Reference Guide www xilinx com 39 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture A load from an address within the cacheable range will provided that the cache is enabled trigger a check to determine if the requested data is currently cached If it is i e on a cache hit the requested data is retrieved from the cache If not i e on a cache miss the address is requested over data CacheLink DXCL and the processor pipeline will stall until the cache line associated to the requested address is returned from the external memory controller Data Cache Software Support MSR Bit The DCE bit in the MSR controls whether or not the cache is enabled When disabling caches the user must ensure that all the prior writes within the cacheable
96. interface is only available on MicroBlaze when caches are enabled It is legal to use a CacheLink cache on the instruction side or the data side without caching the other Memory locations outside the cacheable range are accessed over OPB or LMB Cached memory range is accessed over OPB whenever the caches are software disabled i e MSR DCE 0 or MSR ICE 0 The CacheLink cache controllers handle 4 or 8 word cache lines with critical word first At the same time the separation from the OPB bus reduces contention for non cached memory accesses CacheLink Signal Interface The CacheLink signals on MicroBlaze are listed in Table 2 8 Table 2 8 MicroBlaze Cache Link signals Signal Name Description VHDL Type Direction ICACHE_FSL_IN_Clk Clock output to I side std_logic output return read data FSL ICACHE_FSL_IN_Read Read signal to I side std_logic output return read data FSL ICACHE_FSL_IN_Data Read data from I side std_logic_vector input return read data FSL 0 to 31 ICACHE_FSL_IN_Control FSL control bit from I std_logic input side return read data FSL Reserved for future use ICACHE_FSL_IN_Exists More read data exists in I std_logic input side return FSL ICACHE_FSL_OUT_Clk Clock output to I side std_logic output read access FSL ICACHE_FSL_OUT_Write Write new cache miss std_logic output access request to I side read access FSL ICACHE_FSL_OUT_Data Cache miss access std_logic_vector output
97. ion following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA gt 0 then PC lt PC sext IMM else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed 84 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX ble Branch if Less or Equal ble rA rB Branch if Less or Equal bled rA rB Branch if Less or Equal with De
98. ive material that has allow block block_name been omitted loci loc2 locn Online Document The following conventions are used in this document Convention Meaning or Use Example Cross reference link to a See the section Additional location in the current file or Resources for details Blue text a in another file in the current Refer to Title Formats in document Chapter 1 for details Bad dave Cross reference link to a See Figure 2 5 in the Virtex II location in another document Handbook Go to http www xilinx com Blue underlined text Hyperlink to a web site URL for the latest speed files MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 XILINX Preface About This Guide 10 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 XILINX Chapter 1 MicroBlaze Architecture Overview The MicroBlaze embedded processor soft core is a reduced instruction set computer RISC optimized for implementation in Xilinx field programmable gate arrays FPGAs Figure 1 1 shows a functional block diagram of the MicroBlaze core Instruction side Data side bus interface bus interface IXCL_M Lm Program Counter Special IXCL_S gt Purpose Registers Instruction Buffer Instruction Decode Register File 32 X 32b Optional MicroBlaze feature Figure
99. ization The cacheable instruction address consists of two parts the cache address and the tag address The MicroBlaze instruction cache can be configured from 2kB to 64 kB This corresponds to a cache address of between 11 and 16 bits The tag address together with the cache address should match the full address of cacheable memory MicroBlaze Processor Reference Guide www xilinx com 37 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture For example in a MicroBlaze configured with C_ICACHE_BASEADDR 0x00300000 C_ICACHE_HIGHADDR 0x0030ffff C_CACHE_BYTE_SIZE 4096 and C_ICACHE_LINELEN 8 the cacheable memory of 64 kB uses 16 bits of byte address and the 4 kB cache uses 12 bits of byte address thus the required address tag width is 16 12 4 bits The total number of block RAM primitives required in this configuration is 2 RAMBI16 for storing the 1024 instruction words and 1 RAMB16 for 128 cache line entries each consisting of 4 bits of tag 8 word valid bits 1 line valid bit In total 3 RAMB16 primitives Instruction Cache Operation For every instruction fetched the instruction cache detects if the instruction address belongs to the cacheable segment If the address is non cacheable the cache controller ignores the instruction and lets the OPB or LMB complete the request If the address is cacheable a lookup is performed on the tag memory to check if the requested address is currently ca
100. lable in the FSL interface The non blocking versions will not stall microblaze and will set carry to 0 if space was available and to 1 if no space was available The put and nput instructions will set the control bit to the FSL interface to 0 and the cput and ncput instruction will set the control bit to 1 Pseudocode FSLx lt rA if n 1 then MSR Carry lt lt FSLx Full bit ESL Control bit lt C Registers Altered e MSR Carry Latency 2 cycles For blocking accesses MicroBlaze will first stall until space is available on the FSL interface 126 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX rsub Arithmetic Reverse Subtract rsub rD rA rB Subtract rsubc rD rA rB Subtract with Carry rsubk rD rA rB Subtract and Keep Carry rsubkc rD rA rB Subtract with Carry and Keep Carry 0 00kKC 1 rD rA rB 0000000000 0 0 6 11 16 21 31 Description Pseudocode Registers Altered The contents of register rA is subtracted from the contents of register rB and the result is placed into register rD Bit 3 of the instruction labeled as K in the figure is set to a one for the mnemonic rsubk Bit 4 of the instruction labeled as C in the figure is set to a one for the mnemonic rsubc Both bits are set to a one for the mnemonic rsubkc When an rsub instruction has bit 3 set rsubk rsubkc th
101. lay 10011 1D00 1 1 rA rB 0000000000 0 0 6 11 16 21 31 Description Branch if rA is less or equal to 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic bled will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA lt 0 then PC lt PC rB else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 85 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set A
102. le is not executed If the exception is caused by an instruction in a branch delay slot then the ESR DS bit will be set In this case the exception handler should resume execution from the branch target address stored in BTR The EE and EIP bits in MSR are automatically reverted when executing the RTED instruction Exception Causes e Instruction Bus Exception The instruction On chip Peripheral Bus exception is caused by an active error signal from the slave IOPB_errAck or timeout signal from the arbiter IOPB_timeout The instructions side local memory ILMB and CacheLink IXCL interfaces can not cause instruction bus exceptions e Illegal Opcode Exception The illegal opcode exception is caused by an instruction with an invalid major opcode bits 0 through 5 of instruction Bits 6 through 31 of the instruction are not checked Optional processor instructions are detected as illegal if not enabled e Data Bus Exception The data On chip Peripheral Bus exception is caused by an active error signal from the slave DOPB_errAck or timeout signal from the arbiter DOPB_timeout The data side local memory DLMB and CacheLink DXCL interfaces can not cause data bus exceptions 1 Reset input controlled by the XMD debugger via MDM 34 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Reset Interrupts Exceptions and Break XILINX e Unaligned Exception The unaligned excepti
103. led on data side OPB Buslock Enable does not affect operation of IXCL DXCL ILMB DLMB or IOPB Read Write 1 This bit is only used for integer divide by zero signaling There is a floating point equivalent in the FSR The DZ bit will flag divide by zero conditions regardless if the processor is configured with exception handling or not 2 For a details on the OPB protocol please refer to the IBM CoreConnect specification 64 Bit On Chip Peripheral Bus Architectural Specifications Version 2 0 Exception Address Register EAR The Exception Address Register stores the full load store address that caused the exception For an unaligned access exception that means the unaligned access address and for an DOPB exception the failing OPB data access address The contents of this register is undefined for all other exceptions When read with the MFS instruction the EAR is specified by setting Sa 0x0003 EAR Figure 1 5 EAR Table 1 10 Exception Address Register EAR Bits Name Description Reset Value 0 31 EAR Exception Address Register 0x00000000 24 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Registers XILINX Exception Status Register ESR The Exception Status Register contains status bits for the processor When read with the MFS instruction the ESR is specified by setting Sa 0x0005 RESERVED DS ESS EC Figure 1
104. linx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Debug and Trace XILINX Example code Configure f Custom HW Accelerator cput Rc RFSLXx Store operands oes Op1Reg Op2Reg put Ra RFSLx op 1 Register Conf gReg aS ConfigReg put Rb RFSLx op 2 ty Load result get Rt RFSLX Figure 1 12 FSL used with HW accelerated function f X This method is similar to extending the ISA with custom instructions but has the benefit of not making the overall speed of the processor pipeline dependent on the custom function Also there are no additional requirements on the software tool chain associated with this type of functional extension Debug and Trace Debug Overview MicroBlaze features a debug interface to support JTAG based software debugging tools commonly known as BDM or Background Debug Mode debuggers like the Xilinx Microprocessor Debug XMD tool The debug interface is designed to be connected to the Xilinx Microprocessor Debug Module MDM core which interfaces with the JTAG port of Xilinx FPGAs Multiple MicroBlaze instances can be interfaced with a single MDM to enable multiprocessor debugging The debugging features include e Configurable number of hardware breakpoints and watchpoints and unlimited software breakpoints e External processor control enables debug tools to stop reset and single step MicroBlaze
105. ll be affected by the execution of the instruction When bit 4 of the instruction is set to a one addc addkc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared add addk the content of the carry flag does not affect the execution of the instruction providing a normal addition Pseudocode if C 0 then rD lt rA rB else rD lt rA rB MSR C if K 0 then MSR C lt CarryOut Registers Altered e rD e MSRIC Latency 1 cycle Note The C bit in the instruction opcode is not the same as the carry bit in the MSR The add r0 r0 r0 0x00000000 instruction is never used by the compiler and usually indicates uninitialized memory If you are using illegal instruction exceptions you can trap these instructions by setting the MicroBlaze option C_OPCODE_0x0_ILLEGAL 1 MicroBlaze Processor Reference Guide www xilinx com 73 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture addi Arithmetic Add Immediate addi rD rA IMM Add Immediate addic rD rA IMM Add Immediate with Carry addik rD rA IMM Add Immediate and Keep Carry addikc rD rA IMM Add Immediate with Carry and Keep Carry 001KC0 rD rA IMM 0 6 11 16 31 Description The sum of the contents of registers rA and the value in the IMM field sign extended to 32 bits is placed into register rD Bit 3 of the instruc
106. nstruction should only be used when the instruction cache is disabled i e MSR ICE 0 Pseudocode ICache Tag lt rA Registers Altered e None Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 145 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture xor Logical Exclusive OR xor rD rA rB 100010 rD rA rB 00000000 00 0 i n 16 21 31 Description The contents of register rA are XORed with the contents of register rB the result is placed into register rD Pseudocode rD amp rA rB Registers Altered e D Latency 1 cycle 146 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX xori Logical Exclusive OR with Immediate xori rA rD IMM 101010 rD rA IMM 0 6 11 16 31 Description The IMM field is extended to 32 bits by concatenating 16 0 bits on the left The contents of register rA are XORed with the extended IMM field the result is placed into register rD Pseudocode rD lt rA sext IMM Registers Altered e rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit
107. nts of register rB the result is placed into register rD Pseudocode rD amp rA A rB Registers Altered e rD Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 77 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture andni Logical AND NOT with Immediate andni rD rA IMM 1010 1 41 rD rA IMM 0 6 11 16 31 Description The IMM field is sign extended to 32 bits The contents of register rA are ANDed with the logical complement of the extended IMM field the result is placed into register rD Pseudocode rD lt rA A sext IMM Registers Altered e rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 78 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX beq Branch if Equal beq rA rB Branch if Equal beqd rA rB Branch if Equal with Delay 10011 1D0000 rA rB 00000000000 0 6 11 16 21 31 Description Branch if rA is equal to 0 to the instruction located in the offset value of rB The target of the branch will be the instruction at address PC rB The mnemonic beqd
108. o the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC IMM The mnemonic begid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC lt PC sext IMM else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values A delay slot must not be used by the following IMM branch or break instructions This also applies to instructions causing recoverable exceptions e g unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the
109. ode Destination Reg Source Reg A Source RegB 0 0 0 0 0 0 0 0 0 0 0 0 6 11 16 21 31 Type B Type B is used for register immediate instructions It contains the opcode one destination and one source registers and a source 16 bit immediate value Opcode Destination Reg Source Reg A Immediate Value 0 6 11 16 31 Instructions MicroBlaze instructions are described next Instructions are listed in alphabetical order For each instruction Xilinx provides the mnemonic encoding a description of it pseudocode of its semantics and a list of registers that it modifies 72 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX add Arithmetic Add add rD rA rB Add addc rD rA rB Add with Carry addk rD rA rB Add and Keep Carry addkc rD rA rB Add with Carry and Keep Carry 000K CO rD rA rB 0000000000 0 0 6 11 16 21 31 Description The sum of the contents of registers rA and rB is placed into register rD Bit 3 of the instruction labeled as K in the figure is set to a one for the mnemonic addk Bit 4 of the instruction labeled as C in the figure is set to a one for the mnemonic addc Both bits are set to a one for the mnemonic addkc When an add instruction has bit 3 set addk addkc the carry flag will Keep its previous value regardless of the outcome of the execution of the instruction If bit 3 is cleared add addc then the carry flag wi
110. oes low Write the data to be stored to DCACHE_FSL_OUT_Data For byte and halfword accesses the data is mirrored accordingly onto byte lanes The control bit should be low DCACHE_FSL_OUT_Control 0 for a word or halfword access and high for a byte access Debug Interface Description The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor Debug Module MDM IP core The MDM is controlled by the Xilinx Microprocessor Debugger XMD through the JTAG port of the FPGA The MDM can control multiple MicroBlaze processors at the same time The debug signals on MicroBlaze are listed in Table 2 9 Table 2 9 MicroBlaze Debug signals Signal Name Description VHDL Type Direction Dbg_Clk JTAG clock from MDM std_logic input Dbg_TDI JTAG TDI from MDM std_logic input Dbg_TDO JTAG TDO to MDM std_logic output Dbg_Reg_En Debug register enable from std_logic input MDM Dbg_Capture JTAG BSCAN capture signal std_logic input from MDM Dbg_Update JTAG BSCAN update signal std_logic input from MDM Trace Interface Description The MicroBlaze core exports a number of internal signals for trace purposes This signal interface is not standardized and new revisions of the processor may not be backward compatible for signal selection or functionality Users are recommended not to design custom logic for these signals but rather to use them via Xilinx provided analysis IP The current set of trac
111. on Register R1 stores the value of the stack pointer and is updated on entry and exit from functions Register R18 is used as a temporary register for assembler operations MicroBlaze includes special purpose registers such as program counter rpc machine status register rmsr exception status register resr exception address register rear and floating point status register rfsr These registers are not mapped directly to the register file and hence the usage of these registers is different from the general purpose registers The value of a special purpose registers can be transferred to a general purpose register by using mts and mfs instructions For more details refer to the MicroBlaze Application Binary Interface chapter The stack conventions used by MicroBlaze are detailed in Figure 3 1 The shaded area in Figure 3 1 denotes a part of the caller function s stack frame while the unshaded area indicates the callee function s frame The ABI conventions of the stack frame define the protocol for passing parameters preserving non volatile register values and allocating space for the local variables in a function Functions which contain calls to other sub routines are called as non leaf functions These non leaf functions have to create a new stack frame area for its own use When the program starts executing the stack pointer will have the maximum value As functions are called the stack pointer is decremented by the n
112. on is caused by a word access where the address to the data bus has bits 30 or 31 set or a half word access with bit 31 set e Divide by Zero Exception The divide by zero exception is causes by an integer division idiv or idivu where the divisor is zero e FPU Exception An FPU exception is caused by an underflow overflow divide by zero illegal operation or denormalized operand occurring with a floating point instruction Underflow occurs when the result is denormalized Overflow occurs when the result is not a number NaN The divide by zero FPU exception is caused by the rA operand to fdiv being zero when rB is not infinite Illegal operation is caused by a signaling NaN operand or by illegal infinite or zero operand combinations Equivalent Pseudocode r17 lt PC PC lt 0x00000020 SR EE lt 0 EIP amp 1 DS lt exception in delay slot EC lt exception specific value ESS lt exception specific value EAR lt exception specific value FSR lt exception specific value Breaks There are two kinds of breaks e Hardware external breaks e Software internal breaks Hardware Breaks Hardware breaks are performed by asserting the external break signal i e the Ext_BRK and Ext_NM_BRK input ports On a break the instruction in the execution stage will complete while the instruction in the decode stage is replaced by a branch to the break vect
113. on option option Local Memory Bus LMB instruction side interface option option option option Hardware barrel shifter option option option option Hardware divider option option option option Hardware debug logic option option option option Fast Simplex Link FSL interfaces 0 7 0 7 0 7 0 7 Machine status set and clear instructions option option option Yes Instruction cache over IOPB interface option option option No Data cache over IOPB interface option option option No Instruction cache over CacheLink IXCL interface option option option Data cache over CacheLink DXCL interface option option option 4 or 8 word cache line on XCL 4 4 option Hardware exception support option option option Pattern compare instructions option Yes Floating point unit FPU option option Disable hardware multiplier option option Hardware debug readable ESR and EAR Yes Yes Processor Version Register PVR option 1 Used in Virtex II and subsequent families for saving MUL18 and DSP48 primitives 12 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 Data Types and Endianness XILINX Data Types and Endianness MicroBlaze uses Big Endian bit reversed format to represent data The hardware supported data types for MicroBlaze are word half word and byte The bit and byte organization for each type is shown in the following tables Table 1 2 Word D
114. or address 0x18 The break return address the PC associated with the instruction in the decode stage at the time of the break is automatically loaded into general purpose register R16 MicroBlaze also sets the Break In Progress BIP flag in the Machine Status Register MSR A normal hardware break i e the Ext__BRK input port is only handled when there is no break in progress i e MSR BIP is set to 0 The Break In Progress flag disables interrupts A non maskable break i e the Ext_NM_BRK input port will always be handled immediately The BIP bit in the MSR is automatically cleared when executing the RTBD instruction MicroBlaze Processor Reference Guide www xilinx com 35 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Software Breaks To perform a software break use the brk and brki instructions Refer to Chapter 4 MicroBlaze Instruction Set Architecture for detailed information on software breaks Latency The time it will take MicroBlaze to enter a break service routine from the time the break occurs depends on the instruction currently in the execution stage and the latency to the memory storing the break vector Equivalent Pseudocode rig lt PC PC lt 0x00000018 MSR BIP lt 1 Interrupt MicroBlaze supports one external interrupt source connecting to the Interrupt input port The processor will only react to interrupts if the Interrupt Enable IE
115. or Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Data Cache XILINX e Cache on and off controlled using a bit in the MSR e Optional WDC instruction to invalidate data cache lines General Data Cache Functionality When the data cache is used the memory address space in split into two segments a cacheable segment and a non cacheable segment The cacheable area is determined by two parameters CDCACHE_BASEADDR and C_DCACHE_HIGHADDR All addresses within this range correspond to the cacheable address space All other addresses are non cacheable Data Address Bits Tag Address Cache Word Address Cache_Hit Addr Data Cache_data BRAM Figure 1 10 Data Cache Organization The cacheable data address consists of two parts the cache address and the tag address The MicroBlaze data cache can be configured from 2kB to 64 kB This corresponds to a cache address of between 11 and 16 bits The tag address together with the cache address should match the full address of cacheable memory For example in a MicroBlaze configured with C_ICACHE_BASEADDR 0x00400000 C_ICACHE_HIGHADDR 0x00403fff CCACHE_BYTE_SIZE 2048 and C_ICACHE_LINELEN 4 the cacheable memory of 16 kB uses 14 bits of byte address and the 2 kB cache uses 11 bits of byte address thus the required address tag width is 14 11 3 bits The total number of block RAM primitives required in this configuration is 1 RAMB16 for stor
116. ordered 000 rD amp 0 rD lt 0 rD amp 0 rD amp 1 Less than 001 xD amp 0 rD 1 rD amp 0 rD 0 FSR IO 1 ESR EC lt 00110 Equal 010 rD e 0 rD lt 0 rD e 1 rD e 0 Less or equal 011 rD 0 rD amp 1 rD amp 1 rD 0 FSR IO 1 ESR EC lt 00110 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 104 www xilinx com 1 800 255 7778 Instructions XILINX Table 4 2 Floating Point Comparison Operation Comparison Type Operand Relationship Description OpSel rB gt rA rB lt rA rB rA isNaN rA or isNaN rB Greater than 100 f rD amp 1 rD lt 0 rD amp 0 rD amp 0 FSR IO 1 ESR EC lt 00110 Not equal 101 rD amp 1 rD 1 xD lt 0 xD 1 Greater or equal 110 z0 1 rD lt 0 xD e 1 rD 0 FSR IO amp 1 ESR EC lt 00110 Registers Altered e rD unless an FP exception is generated in which case the register is unchanged e ESR EC e FSR IO DO Latency 1 cycle Note These instructions are only available when the MicroBlaze parameter C_LUSE_FPU is set to 1 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 105 XILINX Chapter 4 MicroBlaze Instruction Set Architecture get get from fsl interface get r
117. orm a 32 bit immediate value The instruction imm is used in conjunction with Type B instructions Since Type B instructions have only a 16 bit immediate value field a 32 bit immediate value cannot be used directly However 32 bit immediate values can be used in MicroBlaze By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction The imm instruction locks the 16 bit IMM value temporarily for the next instruction A Type B instruction that immediately follows the imm instruction will then form a 32 bit immediate value from the 16 bit IMM value of the imm instruction upper 16 bits and its own 16 bit immediate value field lower 16 bits If no Type B instruction follows the IMM instruction the locked value gets unlocked and becomes useless Latency 1 cycle Notes The imm instruction and the Type B instruction following it are atomic hence no interrupts are allowed between them The assembler provided by Xilinx automatically detects the need for imm instructions When a 32 bit IMM value is specified in a Type B instruction the assembler converts the IMM value to a 16 bit one to assemble the instruction and inserts an imm instruction before it in the executable file 108 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 In
118. outines to be located at any address location addressable using 32 bits The user exception handler code starts with the label _exception_handler the hardware exception handler starts with hw_exception_handler while the interrupt handler code starts with the label _interrupt_handler In the current MicroBlaze system there are dummy routines for interrupt and exception handling which you can change In order to override these routines and link your interrupt and exception handlers you must define the interrupt handler code with an attribute interrupt_handler For more details about the use and syntax of the interrupt handler attribute please refer to the GNU Compiler Tools chapter in the document UG111 Embedded System Tools Reference Manual 70 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 S7 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Summary This chapter provides a detailed guide to the Instruction Set Architecture of MicroBlaze Notation The symbols used throughout this document are defined in Table 4 1 Table 4 1 Symbol notation Symbol Meaning Add Subtract x Multiply Bitwise logical AND v Bitwise logical OR Bitwise logical XOR x Bitwise logical complement of x amp Assignment gt gt Right shift lt lt Left shift rx Register x xi Bit i in register x x i Bits i thro
119. r D 0 15 0 Registers Altered e rD unless unaligned data access exception is generated in which case the register is unchanged e ESR W Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 112 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX Iw Load Word lw rD rA rB 110010 rD rA rB 00000000000 0 6 11 16 21 31 Description Loads a word 32 bits from the word aligned memory location that results from adding the contents of registers rA and rB The data is placed in register rD Pseudocode Addr rA rB Addr 30 31 lt 00 rD lt Mem Addr Registers Altered e rD unless unaligned data access exception is generated in which case the register is unchanged e ESR W Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 113 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Iwi Load Word Immediate Iwi rD rA IMM 111010 rD rA IMM 0 6 11 16 31 Description Loads a word 32 bits from the word aligned memory location that results
120. r Ready is high then Write_Strobe remains high Data_Read 0 31 The read data bus is an input to the core and contains data read from memory Data_Read 0 31 is valid on the rising edge of the clock when Ready is high Ready The Ready signal is an input to the core and indicates completion of the current transfer and that the next transfer can begin in the following clock cycle It is sampled on the rising edge of the clock For reads this signal indicates the Data_Read 0 31 bus is valid and for writes it indicates that the Data_Write 0 31 bus has been written to local memory Clk All operations on the LMB are synchronous to the MicroBlaze core clock 50 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Local Memory Bus LMB Interface Description XILINX LMB Transactions The following diagrams provide examples of LMB bus operations Generic Write Operation Clk ro AE Addr i ao i i i T T T Byte_Enable no LE Data Write ME po a AS L r Read_Strobe i i Write_Strobe Data_Read i i i 1 i Ready a i i Figure 2 2 LMB Generic Write Operation Generic Read Operation Clk Addr I T T T T Byte_Enable E 111 X l j l Data_Write bo U s a a AS ye Read_Strobe I I I I Write_Strobe l l l l Data_Read X DO X Ready i i Figure 2 3 LMB Generic Read Operation MicroBlaze Processor Refer
121. range has been completed in external memory before reading back over OPB This can be done by writing to a semaphore immediately before turning off caches and then in a loop poll the semaphore until it has been written The contents of the cache is preserved when the cache is disabled WDC Instruction The optional WDC instruction C_ALLOW_DCACHE_WR 1 is used to invalidate cache lines in the data cache from an application For a detailed description please refer to Chapter 4 MicroBlaze Instruction Set Architecture Floating Point Unit FPU Overview The MicroBlaze floating point unit is based on the IEEE 754 standard e Uses IEEE 754 single precision floating point format including definitions for infinity not a number NaN and zero e Supports addition subtraction multiplication division and comparison instructions e Implements round to nearest mode e Generates sticky status bits for underflow overflow and invalid operation For improved performance the following non standard simplifications are made e Denormalized operands are not supported A hardware floating point operation on a denormalized number will return a quiet NaN and set the denormalized operand error bit in FSR see Floating Point Status Register FSR on page 27 e Adenormalized result is stored as a signed 0 with the underflow bit set in FSR This method is commonly referred to as Flush to Zero FTZ e An operation on a quiet NaN will retu
122. rchitecture blei Branch Immediate if Less or Equal blei rA IMM Branch Immediate if Less or Equal bleid rA IMM Branch Immediate if Less or Equal with Delay 10111 1D O00 1 1 rA IMM 0 6 11 16 31 Description Branch if rA is less or equal to 0 to the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC IMM The mnemonic bleid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA lt 0 then PC lt PC sext IMM else PC lt PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and the D bit is not set Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values
123. rn the fixed NaN 0xFFC00000 rather than one of the NaN operands e Overflow as a result of a floating point operation will always return signed o even when the exception is trapped 1 Numbers that are so close to 0 that they cannot be represented with full precision i e any number n that falls in the following ranges 1 17549 10 8 gt n gt 0 or 0 gt n gt 1 17549 10 38 40 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Floating Point Unit FPU XILINX Format An IEEE 754 single precision floating point number is composed of the following three fields 1 1 bit sign 2 8 bit biased exponent 3 23 bit fraction a k a mantissa or significand The fields are stored in a 32 bit word as defined in Figure 1 11 CEE a sign exponent fraction Figure 1 11 IEEE 754 Single Precision format The value of a floating point number v in MicroBlaze has the following interpretation If exponent 255 and fraction lt gt 0 then v NaN regardless of the sign bit If exponent 255 and fraction 0 then v 1 8 8 oo If 0 lt exponent lt 255 then v 1 5i8 2 exponent 127 1 fraction If exponent 0 and fraction lt gt 0 then v 1 5 8 2 126 fraction If exponent 0 and fraction 0 then v 1 8 0 oF eo N A For practical purposes only 3 and 5 are really useful while the others all represent either an error or numbers th
124. rom this web site You can also directly access these resources using the provided URLs Resource Tutorials Description URL Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xInx xil_ans_browser jsp Application Notes Descriptions of device specific design techniques and approaches http www xilinx com xInx xweb xil_publications_index jsp c ategory Application Notes Data Book Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com xInx xweb xil_publications_index jsp MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 7 1 800 255 7778 XILINX Preface About This Guide Resource Problem Solvers Description URL Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xInx xil_tt_home jsp GNU Manuals The entire set of GNU manuals http www gnu org manual
125. ry MEM and Writeback WB For most instructions each stage takes one clock cycle to complete Consequently it takes five clock cycles for a specific instruction to complete and one instruction is completed on every cycle A few instructions require multiple clock cycles in the execute stage to complete This is achieved by stalling the pipeline cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 instruction 1 IF OF EX MEM WB instruction 2 IF OF EX MEM MEM MEM WB instruction 3 IF OF EX Stall Stall MEM WB When executing from slower memory instruction fetches may take multiple cycles This additional latency will directly affect the efficiency of the pipeline MicroBlaze implements an instruction prefetch buffer that reduces the impact of such multi cycle instruction memory latency While the pipeline is stalled by a multi cycle instruction in the execution stage the prefetch buffer continues to load sequential instructions Once the pipeline resumes execution the fetch stage can load new instructions directly from the prefetch buffer rather than having to wait for the instruction memory access to complete MicroBlaze Processor Reference Guide www xilinx com 31 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Branches Normally the instructions in the fetch and decode stages as well as prefetch buffer are flus
126. se the register is unchanged e ESR EC e FSR IO UROF DO DZ Latency 28 cycles Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1 MicroBlaze Processor Reference Guide www xilinx com 103 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture fcmp Floating Point Number Comparison fcmp un rD rA rB Unordered floating point comparison fcmp lt rD rA rB Less than floating point comparison fcmp eq rD rA rB Equal floating point comparison fcmp le rD rA rB Less or Equal floating point comparison fcmp gt rD rA rB Greater than floating point comparison fcmp ne rD rA rB Not Equal floating point comparison fcmp ge rD rA rB Greater or Equal floating point comparison 0101 0 rD rA rB 0 1 0 0 OpSel 0 0 0 O 0 6 11 16 21 25 28 31 Description The floating point value in rB is compared with the floating point value in rA and the comparison result is placed into register rD The OpSe1 field in the instruction code determines the type of comparison performed Pseudocode if isDnz rA or isDnz rB then rD e 0 FSR DO amp 1 ESR EC lt 00110 else read out behavior from Table 4 2 Table 4 2 Floating Point Comparison Operation Comparison Type Operand Relationship Description OpSel rB gt rA rB lt rA rB rA isNaN rA or isNaN rB Un
127. srset Read MSR and set bits in MSR msrset rD Imm 100101 rD o0 00 oloo Imm14 0 6 11 16 18 T Description Copies the contents of the special purpose register MSR into register rD Bit positions in the IMM value that are 1 are set in the MSR Bit positions that are 0 in the IMM value are left untouched Pseudocode rD lt MSR MSR lt MSR V IMM Registers Altered e rD e MSR Latency 1 cycle Note MSRSET will affect some MSR bits immediately e g Carry while the remaining bits will take effect one cycle after the instruction has been executed The immediate values has to be less than 214 Only bits 18 to 31 of the MSR can be set MicroBlaze Processor Reference Guide www xilinx com 117 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture mts Move To Special Purpose Register mts rS rA 10010100000 rA 1100000000000 rs 0 6 11 16 29 31 Description Copies the contents of register rD into the MSR or FSR Pseudocode cS lt rA Registers Altered e S Latency 1 cycle Notes When writing MSR using MTS some bits take effect immediately e g Carry while the remaining bits takes effect one cycle after the instruction has been executed To refer to special purpose registers in assembly language use rmsr for MSR and rfsr for FSR The PC ESR and EAR cannot be written by the MTS instruction The FSR is only valid as a destination if th
128. ss stored in R17 Memory Architecture MicroBlaze is implemented with a Harvard memory architecture i e instruction and data accesses are done in separate address spaces Each address space has a 32 bit range i e handles up to 4 GByte of instructions and data memory respectively The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory The latter is useful e g for software debugging Both instruction and data interfaces of MicroBlaze are 32 bit wide and use big endian bit reversed format MicroBlaze supports word halfword and byte accesses to data memory Data accesses must be aligned i e word accesses must be on word boundaries halfword on halfword bounders unless the processor is configured to support unaligned exceptions All instruction accesses must be word aligned MicroBlaze does not separate between data accesses to I O and memory i e it uses memory mapped I O The processor has up to three interfaces for memory accesses Local Memory Bus LMB On Chip Peripheral Bus OPB and Xilinx CacheLink XCL The LMB memory address range must not overlap with OPB or XCL ranges MicroBlaze has a single cycle latency for accesses to local memory LMB and for cache read hits A data cache write normally has two cycles of latency more if the posted write buffer in the memory controller is full For details on the different memory interfaces please refer to Chapter 2 Mi
129. structions 1 1 integer MSRSET and MSRCLR C_USE_PCMP_INSTR Enable use of instructions 1 1 integer PCMPBF PCMPEQ and PCMPNE C_UNALIGNED_EXCEPTION Enable exception handling 0 1 0 integer for unaligned data accesses C_ILL_OPCODE_EXCEPTION Enable exception handling 0 1 0 integer for illegal op code C_IOPB_BUS_EXCEPTION Enable exception handling 0 1 0 integer for IOPB bus error C_DOPB_BUS_EXCEPTION Enable exception handling 0 1 0 integer for DOPB bus error C_DIV_ZERO_EXCEPTION Enable exception handling 0 1 0 integer for division by zero C_FPU_EXCEPTION Enable exception handling 0 1 0 integer for hardware floating point unit exceptions C_OPCODE_0x0_ILLEGAL Detect opcode 0x0 as an 0 1 0 integer illegal instruction C_DEBUG_ENABLED MDM Debug interface 0 1 0 integer C_NUMBER_OF_PC_BRK Number of hardware 0 8 1 integer breakpoints C_NUMBER_OF_RD_ ADDR BRK Number of read address 0 4 0 integer watchpoints C_ NUMBER _OF_WR_ADDR BRK Number of write address 0 4 0 integer watchpoints C_INTERRUPT_IS_EDGE Level Edge Interrupt 0 1 0 integer C_EDGE_IS_ POSITIVE Negative Positive Edge 0 1 1 integer Interrupt C_FSL_LINKS Number of FSL interfaces 0 8 0 yes integer C_FSL_DATA_SIZE FSL data bus size 32 32 NA integer C_ICACHE BASEADDR Instruction cache base 0x00000000 0x0000 std_logi address OxFFFFFFFF 0000 c_vector MicroBlaze Processor Reference Guide www xilinx com 63 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter
130. structions XILINX Ibu Load Byte Unsigned Ibu rD rA rB 110000 rD rA rB 0000000000 0 0 6 11 16 21 31 Description Loads a byte 8 bits from the memory location that results from adding the contents of registers rA and rB The data is placed in the least significant byte of register rD and the other three bytes in rD are cleared Pseudocode Addr rA rB rD 24 31 lt Mem Addr rD 0 23 lt 0 Registers Altered e rD Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 109 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Ibui Load Byte Unsigned Immediate Ibui rD rA IMM 0 0 0 rD rA IMM Description Loads a byte 8 bits from the memory location that results from adding the contents of register rA with the value in IMM sign extended to 32 bits The data is placed in the least significant byte of register rD and the other three bytes in rD are cleared Pseudocode Addr rA sext IMM rD 24 31 lt Mem Addr rD 0 23 lt 0 Registers Altered e D Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate
131. te handlers Table 3 3 Interrupt and Exception Handling On Hardware jumps to Software Labels Start Reset 0x0 _start User exception 0x8 _exception_handler Interrupt 0x10 _interrupt_handler Break HW SW 0x18 Hardware exception 0x20 _hw_exception_handler Reserved by Xilinx for 0x28 Ox4F future use The code expected at these locations is as shown in Figure 3 3 For programs compiled without the xl mode xmdstub compiler option the crt0 o initialization file is passed by the mb gcc compiler to the mb ld linker for linking This file sets the appropriate addresses of the exception handlers For programs compiled with the xl mode xmdstub compiler option the crt1 o initialization file is linked to the output program This program has to be run with the xmdstub already loaded in the memory at address location 0x0 Hence at run time the initialization code in crt1 o writes the appropriate instructions to location 0x8 through 0x14 depending on the address of the exception and interrupt handlers Figure 3 3 Code for passing control to exception and interrupt handlers 0x00 bri _startl 0x04 nop 0x08 imm high bits of address user exception handler 0x0c bri _exception_handler 0x10 imm high bits of address interrupt handler 0x14 bri _interrupt_handler 0x20 imm high bits of address HW exception handler 0x24 bri _hw_exception_handler MicroBlaze allows exception and interrupt handler r
132. ter rA is compared with the contents in register rB e rDis loaded with 1 if they match and 0 if not Pseudocode if rB rA then ED lt I else rD amp 0 Registers Altered e rD Latency 1 cycle Note 124 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX pcmpne Pattern Compare Not Equal pcmpne rD rA rB equality comparison with a negative boolean result 10001 1 rD rA rB 10000000000 0 6 11 16 21 31 Description The contents of register rA is compared with the contents in register rB e rDis loaded with 0 if they match and 1 if not Pseudocode if rB rA then rD lt 0 else xD amp 1 Registers Altered e rD Latency 1 cycle Note MicroBlaze Processor Reference Guide www xilinx com 125 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture put put to fsl interface put rA FSLx put data to FSL x blocking nput rA FSLx put data to FSL x non blocking cput rA FSLx put control to FSL x blocking ncput rA FSLx put control to FSL x non blocking 01101100000 rA 1 nc 000000000 0 FSLx 0 6 11 16 29 31 Description MicroBlaze will write the value from register rA to the FSLx interface The put instruction has four variants The blocking versions when r is 0 will stall microblaze until there is space avai
133. tex5 C_DATA SIZE Data Size 32 32 NA integer C_DYNAMIC_BUS_SIZING Legacy 1 1 NA integer C_ SCO Xilinx internal 0 0 NA integer C_ PVR Processor version register 0 1 2 0 integer mode selection C_PVR_USER1 Processor version register 0x00 Oxff 0x00 std_logi USER1 constant c_vector 0 to 7 C_PVR_USER2 Processor version register 0x00000000 0x0000 std_logi USER2 constant Oxffffffff 0000 c_vector 0 to 31 C_RESET_MSR Reset value for MSR 0x00 0x20 0x00 std_logi register 0x80 0xa0 c_vector C_INSTANCE Instance Name Any microb yes string instance laze name C_D_OPB Data side OPB interface 0 1 1 yes integer C_D_LMB Data side LMB interface 0 1 1 yes integer C_I _OPB Instruction side OPB 0 1 1 yes integer interface C_I_LMB Instruction side LMB 0 1 1 yes integer interface C_USE_BARREL Include barrel shifter 0 1 0 integer C_USE_DIV Include hardware divider 0 1 0 integer C_USE_HW_MUL Include hardware 0 1 1 integer multiplier Virtex2 and later 62 www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 MicroBlaze Core Configurability XILINX Table 2 12 MPD Parameters Parameter Name Feature Description Allovable Detault EDI tool WHEE p Values Value Assigned Type C_USE_FPU Include hardware floating 0 1 0 integer point unit Virtex2 and later C_USE_MSR_INSTR Enable use of in
134. the transaction information over the FSL data and control signals The cache lines used for reads in the CacheLink protocol are 4 words long Each cache line is expected to start with the critical word first I e if an access to address 0x348 is a miss then the returned cache line should have the following address sequence 0x348 0x34c 0x340 0x344 The cache controller will forward the first word to the execution unit as well as store it in the cache memory This allows execution to resume as soon as the first word is back The cache controller then follows through by filling up the cache line with the remaining 3 words as they are received All write operations to the data cache are single word write through Instruction Cache Read Miss On a read miss the cache controller will perform the following sequence 1 Write the word aligned missed address to ICACHE_FSL_OUT_Data with the control bit set low ICACHE_FSL_OUT_Control 0 to indicate a read access Wait until ICACHE_FSL_IN_Exists goes high to indicate that data is available Store the word from ICACHE_FSL_IN_Data to the cache Forward the critical word to the execution unit in order to resume execution m e YN Repeat 3 and 4 for the subsequent 3 words in the cache line Data Cache Read Miss On a read miss the cache controller will perform the following sequence 1 If DCACHE_FSL_OUT_Full 1 then stall until it goes low 2 Write the word aligned missed address to DCACHE_F
135. this attachment method MicroBlaze Processor Reference Guide 53 UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 XILINX Chapter 2 MicroBlaze Signal Interface Description Fast Simplex Link FSL Interface Description The Fast Simplex Link bus provides a point to point communication channel between an output FIFO and an input FIFO For details on the generic FSL protocol please refer to the Fast Simplex Link FSL bus data sheet DS449 Master FSL Signal Interface MicroBlaze may contain up to 8 master FSL interfaces The master signals are depicted in Table 2 6 Table 2 6 Master FSL signals Signal Name Description VHDL Type Direction FSLn_M_Clk Clock std_logic input FSLn_M_Write Write enable signal std_logic output indicating that data is being written to the output PSL FSLn_M_Data Data value written to the std_logic_vector output output FSL FSLn_M_Control Control bit value written to std_logic output the output FSL FSLn_M_Full Full Bit indicating output std_logic input FSL FIFO is full when set Slave FSL Signal Interface MicroBlaze may contain up to 8 slave FSL interfaces The slave FSL interface signals are depicted in Table 2 7 Table 2 7 Slave FSL signals Signal Name Description VHDL Type Direction FSLn_S_Clk Clock std_logic input FSLn_S_Read Read acknowledge signal std_logic output indicating that data has been read from the input FSL
136. tion labeled as K in the figure is set to a one for the mnemonic addik Bit 4 of the instruction labeled as C in the figure is set to a one for the mnemonic addic Both bits are set to a one for the mnemonic addikc When an addi instruction has bit 3 set addik addikc the carry flag will Keep its previous value regardless of the outcome of the execution of the instruction If bit 3 is cleared addi addic then the carry flag will be affected by the execution of the instruction When bit 4 of the instruction is set to a one addic addikc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared addi addik the content of the carry flag does not affect the execution of the instruction providing a normal addition Pseudocode if C 0 then rD lt rA sext IMM else rD lt rA sext IMM MSR C if K 0 then MSR C lt CarryOut Registers Altered e rD e MSR C Latency 1 cycle Notes The C bit in the instruction opcode is not the same as the carry bit in the MSR By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 74 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instruc
137. tions XILINX and Logical AND and rD rA rB 100001 rD rA rB 00000000000 0 6 11 16 21 31 Description The contents of register rA are ANDed with the contents of register rB the result is placed into register rD Pseudocode rD lt rA rB Registers Altered e rD Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 75 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture andi Logial AND with Immediate andi rD rA IMM 101001 rD rA IMM 0 6 11 16 31 Description The contents of register rA are ANDed with the value of the IMM field sign extended to 32 bits the result is placed into register rD Pseudocode rD amp rA A sext IMM Registers Altered e rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an IMM instruction See the imm instruction for details on using 32 bit immediate values 76 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX andn Logical AND NOT andn rD rA rB O D rA rB 00000000000 0 6 11 16 21 31 Description The contents of register rA are ANDed with the logical complement of the conte
138. ue is 0x00000000 Note The register file is not reset by the external reset inputs reset and debug_rst T RO R31 Figure 1 2 RO R31 Table 1 7 General Purpose Registers RO R31 Bits Name Description Reset Value 0 31 RO RO is defined to always have the value 0x00000000 of zero Anything written to RO is discarded 0 31 R1 through R13 R1 through R13 are 32 bit general purpose registers 0 31 R14 32 bit used to store return addresses for interrupts 0 31 R15 32 bit general purpose register E 0 31 R16 32 bit used to store return addresses for breaks 0 31 R17 If MicroBlaze is configured to support hardware exceptions this register is loaded with HW exception return address see also Branch Target Register BTR if not it is a general purpose register 0 31 R18 through R31 R18 through R31 are 32 bit general purpose registers Please refer to Table 3 2 for software conventions on general purpose register usage Special Purpose Registers Program Counter PC The Program Counter is the 32 bit address of the execution instruction It can be read with an MFS instruction but it can not be written to using an MTS instruction When used with the MFS instruction the PC register is specified by setting Sa 0x0000 MicroBlaze Processor Reference Guide www xilinx com 21 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 1 MicroBlaze Architecture Fi
139. ugh j in register x Equal comparison Not equal comparison gt Greater than comparison gt Greater than or equal comparison lt Less than comparison lt Less than or equal comparison sext x Sign extend x MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 www xilinx com 1 800 255 7778 71 XILINX Chapter 4 MicroBlaze Instruction Set Architecture Table 4 1 Symbol notation Symbol Meaning Mem x Memory location at address x FSLx FSL interface x LSW x Least Significant Word of x isDnz x Floating point true if x is denormalized isInfinite x Floating point true if x is or oo isPosInfinite x Floating point true if x is isNegInfinite x Floating point true if x co isNaN x Floating point true if x is a quiet or signalling NaN isZero x Floating point true if x is 0 or 0 isQuietNaN x Floating point true if x is a quiet NaN isSigNaN x Floating point true if x is a signaling NaN signZero x Floating point return 0 for x gt 0 and 0 if x lt 0 signInfinite x Floating point return c for x gt 0 and c if x lt 0 Formats MicroBlaze uses two instruction formats Type A and Type B Type A Type A is used for register register instructions It contains the opcode one destination and two source registers Opc
140. umber of words required by every function for its stack frame The stack pointer of a caller function will always have a higher value as compared to the callee function MicroBlaze Processor Reference Guide www xilinx com 67 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 3 MicroBlaze Application Binary Interface Figure 3 1 Stack Convention Function Parameters for called sub routine Arg n Arg1 Optional Maximum number of arguments required for any called procedure from the current procedure Old Stack Pointer Link Register R15 Callee Saved Register R31 R19 Optional Only those registers which are used by the current procedure are saved Local Variables for Current Procedure Optional Present only if Locals defined in the procedure Functional Parameters Arg n Arg 1 Optional Maximum number of arguments required for any called procedure from the current procedure New Stack Link Register Pointer Low Address Consider an example where Func1 calls Func2 which in turn calls Func3 The stack representation at different instances is depicted in Figure 3 2 After the call from Func 1 to Func 2 the value of the stack pointer SP is decremented This value of SP is again decremented to accommodate the stack frame for Func3 On return from Func 3 the value of the stack pointer is increased to its original value in the function Func 2 Details of
141. unalignement when hardware exceptions are enabled Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed MicroBlaze Processor Reference Guide www xilinx com 81 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture bgei Branch Immediate if Greater or Equal bgei rA IMM Branch Immediate if Greater or Equal bgeid rA IMM Branch Immediate if Greater or Equal with Delay 10111 1D0 10 1 rA IMM 0 6 11 16 31 Description Branch if rA is greater or equal to 0 to the instruction located in the offset value of IMM The target of the branch will be the instruction at address PC IMM The mnemonic bgeid will set the D bit The D bit determines whether there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch i e in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA gt 0 then PC lt PC sext IMM else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered e PC Latency 1 cycle if branch is not taken 2 cycles if branch is taken and the D bit is set 3 cycles if branch is taken and th
142. utput access Trace_Data_Address Address for D side std_logic_vector output memory access 0 to 31 Trace_Data_Write_Value Value for D side memory std_logic_vector output write access 0 to 31 Trace_Data_Byte_Enable Byte enables for D side std_logic_vector output memory access 0 to 3 Trace_Data_Read D side memory access isa std_logic output read Trace_Data_Write D side memory access isa std_logic output write Trace_DCache_Req Data memory address is std_logic output within D Cache range Trace_DCache_Hit Data memory address is std_logic output present in D Cache Trace_ICache_Req Instruction memory std_logic output address is in I Cache range Trace_ICache_Hit Instruction memory std_logic output address is present in I Cache www xilinx com 1 800 255 7778 MicroBlaze Processor Reference Guide UG081 v6 0 June 1 2006 MicroBlaze Core Configurability XILINX Table 2 10 MicroBlaze Trace signals Signal Name Description VHDL Type Direction Trace_OF_PipeRun Pipeline advance for std_logic output Decode stage Trace_EX_PipeRun Pipeline advance for std_logic output Execution stage Trace_MEM_PipeRun Pipeline advance for std_logic output Memory stage 1 Valid only when Trace_Valid_Instr 1 Table 2 11 Type of Trace Exception Trace_Exception_Kind 0 3 Description 0001 Unaligned execption 0010 Illegal Opcode exception
143. v6 0 June 1 2006 Instructions Table 1 6 MicroBlaze Instruction Set Summary Continued XILINX Type A 0 5 6 10 11 15 16 20 21 31 Semantics Type B 0 5 6 10 11 15 16 31 PUT Ra FSLx 011011 00000 Ra 1000000000000 amp FSLx Ra blocking data write FSLx NGET Rd FSLx 011011 Rd 00000 0100000000000 amp Rd FSLx non blocking data read FSLx MSR FSL 1 if FSLx_S_Control 1 MSR C not FSLx_S_Exists NPUT Ra FSLx 011011 00000 Ra 1100000000000 amp FSLx Ra non blocking data write FSLx MSR C FSLx_M_Full CGET Rd FSLx 011011 Rd 00000 0010000000000 amp Rd FSLx blocking control read FSLx MSRI FSL 1 if FSLx_S_Control 0 CPUT Ra FSLx 011011 00000 Ra 1010000000000 amp FSLx Ra blocking control write FSLx NCGET Rd FSLx 011011 Rd 00000 0110000000000 amp Rd FSLx non blocking control read FSLx MSR FSL 1 if FSLx_S_Control 0 MSRIC not FSLx_S_Exists NCPUT Ra FSLx 011011 00000 Ra 1110000000000 amp FSLx Ra non blocking control write FSLx MSR C FSLx_M_Full OR Rd Ra Rb 100000 Rd Ra Rb 00000000000 Rd Ra or Rb AND Rd Ra Rb 100001 Rd Ra Rb 00000000000 Rd Ra and Rb XOR Rd Ra Rb 100010 Rd Ra Rb 00000000000 Rd Ra xor Rb ANDN Rd Ra Rb 100011 Rd Ra Rb 00000000000 Rd Ra and Rb PCMPPBEF Rd Ra Rb 100000 Rd Ra Rb 10000000000 Rd
144. value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type B instruction with an imm instruction See the imm instruction for details on using 32 bit immediate values 134 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instructions XILINX sexti 6 Sign Extend Halfword sext16 rD rA 100100 rD rA 0o 0 0000000 110000 1 0 6 11 16 x Description This instruction sign extends a halfword 16 bits into a word 32 bits Bit 16 in rA will be copied into bits 0 15 of rD Bits 16 31 in rA will be copied into bits 16 31 of rD Pseudocode rD 0 15 lt rA 16 cD 16 31 lt rA 16 31 Registers Altered e rD Latency 1 cycle MicroBlaze Processor Reference Guide www xilinx com 135 UG081 v6 0 June 1 2006 1 800 255 7778 XILINX Chapter 4 MicroBlaze Instruction Set Architecture sext8 Sign Extend Byte sext8 rD rA 1 00 1 0 0 rD rA 0000000001417 00 0 0 0 6 11 16 31 Description This instruction sign extends a byte 8 bits into a word 32 bits Bit 24 in rA will be copied into bits 0 23 of rD Bits 24 31 in rA will be copied into bits 24 31 of rD Pseudocode cD 0 23 lt rA 24 cD 24 31 lt rA 24 31 Registers Altered e rD Latency 1 cycle 136 www xilinx com MicroBlaze Processor Reference Guide 1 800 255
145. xception return address and to use the RTSD instruction to return from the user exception handler Pseudocode rx lt PC 36 www xilinx com MicroBlaze Processor Reference Guide 1 800 255 7778 UG081 v6 0 June 1 2006 Instruction Cache XILINX PC lt 0x00000008 Instruction Cache Overview MicroBlaze may be used with an optional instruction cache for improved performance when executing code that resides outside the LMB address range The instruction cache has the following features e Direct mapped 1 way associative e User selectable cacheable memory address range e Configurable cache and tag size e Caching over CacheLink XCL interface e Option to use 4 or 8 word cache line e Cache on and off controlled using a bit in the MSR e Optional WIC instruction to invalidate instruction cache lines General Instruction Cache Functionality When the instruction cache is used the memory address space in split into two segments a cacheable segment and a non cacheable segment The cacheable segment is determined by two parameters C_ICACHE_BASEADDR and C_ICACHE_HIGHADDER All addresses within this range correspond to the cacheable address segment All other addresses are non cacheable Instruction Address Bits Tag Address Cache Address Line Addr Cache_Hit l Valid word and line Instruction BRAM Word Addr Cache_instruction_data Figure 1 9 Instruction Cache Organ

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