Xilinx Pico Blaze Frequency Generator User's Manual
Contents
1. frequency_aligned_dcm 109 31 CLKIN x16 CLKFX_MULTIPLY 256 BUF G CLKFX_DIVIDE 16 dds_scaling_word D CLKFX Jdcm_clean_clk gt 5 u f sma_out A simple binary counter is used to divide the low jitter clock by powers of 2 and a multiplexer selects the appropriate course division factor N x 200MHz x 16 O D 1 x 932 In the example D 4 so the 153MHz from the DCM is divided by 2 4 1 32 Fo 4 7499999869MHz The second DCM is used in a frequency aligned mode At the time of writing this reference design this mode is not an officially documented or supported feature However it is hoped that this reference design will enable you to see this mode in action and evaluate it for yourself In this mode the DCM not only multiplies the input clock but also has the effect of reducing cycle to cycle jitter This is because the normal phase alignment mode of the DCM has been disabled and the DCM is tracking the average of the input frequency instead 10 or 11 l I 10 or 11 cycles I l l l i I cycles E In the example the input to the DCM will have 5ns of cycle to cycle jitter as the square wave is formed from 21 cycles of 200MHz The DCM will generate 153MHz square wave with lt 300ps of jitter S7 XILINX PicoBlaze Circuit Diagram PicoBlaze provides the user interface and performs the calculations required to generate the 32 bit DDS control word N and 5 bit DDS2. XILINX Frequency Generator for the Spartan 3E Starter Kit 4 PicoBlaze Design Size The images and statistics on this page show that the design occupies just 172 slices 1 BRAM and 2 DCMs This is only 3 7 of the slices available in an XC38S500E device More significantly this slice count can be reduced to less than 32 when implementing a fixed frequency version MAP report PicoBlaze makes extensive use of the distributed memory features of the Number of occupied Slices Lp 2 Ole Ue 4 656 Spartan 3E device leading to very high design efficiency If this design Number of Block RAMs Mon Ore ZU was replicated to fill the XC3S500E device it would represent the DCMs 2 Ce Ole 4 equivalent of over 1 5 million gates Not bad for a device even marketing claims to be 500 thousand gates Totalveguivalentjgake Count ior design 91 537 FPGA Editor view Figorplanner ven XC3S500E a to i aa ma kot r xX 2 XILINX Frequency Generator for the Spartan 3E Starter Kit 5 Design Files The source files provided for the reference design are Top level file and main description of hardware frequency_generator vhd Contains I O required to disable StrataFLASH memory device on the board which may otherwise interfere with the LCD display I O constraints file for Spartan 3E Starter Kit Timing specifications for 50MHz PicoBlaze controller 200MHz DDS circuits Location constraint for DCM used for Jitter reduction kc
3. There is clearly 5ns of cycle to cycle jitter in this situation because each output cycle really should be formed of 16 113 periods of the 200MHz clock which is impossible Therefore what the phase accumulator is doing is to provide the correct average frequency by making some cycles of 16 periods and then make approximately 1 in every 9 cycles have 17 periods a mix of 12 5MHz and 11 767MHz waveforms D aa ee S aa S aa OO OO LI LI gt 16 cycles 17 cycles 200MHz 200MHz Note that to force this frequency at the phase accumulator actually dialled in a frequency of 99 3MHz on to the LCD display such that N OFE353F7 hex ons of cycle to cycle jitter is often acceptable when synthesizing lower frequencies especially if the waveform is only used as a digital clock for control and timing of slower events However for higher frequencies such jitter becomes acceptable i e at 1OOMHz the cycle period is only 10ns Frequency Generator for the Spartan 3E Starter Kit 9 S7 XILINX Phase Accumulator Spectrum An alternative way to observe the quality of the waveforms synthesised by the phase accumulator is to look at the frequency spectrum was lucky enough to have a 2048 point FFT feature on my oscilloscope which allows some simple observations to be made Once again have set the display to infinite persistence in order capture the spectrum over a long period of time gt 15 seconds suggest that you do not look for exact values but
4. compare the plots which have been captured using the same scales in each case On the left are plots that show the spectrum up to 50MHz and on the right the plots show are zoomed in to show 5MHz centred on 12 5MHz Tek mile Trig d Pos 25 00MHz MATH 3rd Operation FFT 12 5MHz Harmonic Fundamental Sem A CH1 Mt I I I 1 Window eer I I FFT Zoom Flattop 15 Jul 06 15 52 12 5000MHz Tek SE Trig d Pos 25 00MHz MATH 12 4125MHz Heise Fundamental 2 Source CH1 Window Flattop FFT Zoom I m CH1 10 006 C OOMHz TOM 52 Flattop 13 Jul 06 15 55 12 4125MHz Frequency Generator for the Spartan 3E Starter Kit 10 As we know the 12 5MHz signal is Tek JL Trig d Pos 12 48MH2z MATH nominally clean in terms of the synthesis ae process and this Is reflected by a distinct 12 5MHz FFT 12 5MHz component which is gt 45dB above Fundamental the noise floor The zoomed plot shows how the fundamental covers only a narrow bandwidth keeping in mind that the resolution of the FFT is only 50KHz d Note the third harmonic of a square wave is window dgan i Flattop also very distinct at 37 5MHz and is even close to being the theoretical 9 54dB down esse aoaia ibe FFT Zoom from the fundamental 1 3 amplitude Flattop 5MHz division 1MHz division Leelee el ey 10dB division 10dB division Tek Jia Trig d Pos 12 48MHz MATH 12 4125MHz Operation When we move to the less th
5. of the DCM is really doing something special is to turn it off remove the special BITGEN option and then look at the output waveform on an oscilloscope particularly at frequencies gt 50MHz How fast is yours The PicoBlaze controller does not limit the upper frequency that you can enter to see how high the frequency is that your board can generate Hint 1 Although the display supports up to 999MHz the largest valid value you can enter is 212 499999MHz because this sets N OFFFFFEA Hint 2 The output from the second DCM is always divided by at least 2 before it reaches the output pin so internally a clock can be faster Hint 3 As you increase the frequency you will reach the limit of I O performance Experiment with increasing output drive strengths and FAST slew rates Save Oscillators and Save This reference design could be the way to save money by replacing a set of different crystal oscillators required to support multiple standards etc This design together with the board allows you to directly try the output with your own products and see if it works for you The plots shown in this document clearly show that the final output has very low cycle to cycle jitter compared with the output from a phase accumulator DDS circuit However it is also shown that the output still has some additional frequency components as it tracks the average frequency In some applications this will have no effect whilst others may find it an issue Some a
6. then it does NOT make sense to use a DCM in frequency aligned mode In all non integer division cases the DCM will dramatically help jitter performance but some frequency tracking must be accepted Frequency Generator for the Spartan 3E Starter Kit 12 Zu setting DCM Frequency Aligned Mode To set the DCM into the frequency aligned mode of operation a special option must be used during configuration file generation This can be set in the ISE tools as shown in these screen shots from an ISE v8 1i project for this reference design Processes CI Add Existing Source 1 In the Processes window select Generate Programming File Then PS Create New Source right click and select Properties to open the Process Properties box Yew Design Summary H Design Utilities 2 The Process Properties box should open with the General Options being oe User Constraints shown otherwise select General Options on the left Move to the line Other Spnthesize XST Bitgen Command Line Options and enter the text string shown below H EY AA Implement Design EE rt Generate Proop Ei Hint You may need to set Property display level to Advanced and scroll down a Programmi ot Run to see this line G Generate f Rerun Configure et Rerun Al 3 Select Apply and then use OK to exit the box xf Stop LR ETNO TEK IOC Hint Reopen the box and confirm the option really was set cor
7. will be uninterrupted or error free or that defects in the Designs will be corrected Furthermore Xilinx does not warrant or make any representations regarding use or the results of the use of the designs in terms of correctness accuracy reliability or otherwise Limitation of Liability In no event will Xilinx or its licensors be liable for any loss of data lost profits cost or procurement of substitute goods or services or for any special incidental consequential or indirect damages arising from the use or operation of the designs or accompanying documentation however caused and on any theory of liability This limitation will apply even if Xilinx has been advised of the possibility of such damage This limitation shall apply not withstanding the failure of the essential purpose of any limited remedies herein This design module is not supported by general Xilinx Technical support as an official Xilinx Product Please refer any issues initially to the provider of the module Any problems or items felt of value in the continued improvement of KCPSM3 or this reference design would be gratefully received by the author Ken Chapman senior Staff Engineer Spartan Applications Specialist email chapman xilinx com The author would also be pleased to hear from anyone using KCPSMs with information about your application and PicoBlaze has been useful S7 XILINX Frequency Generator for the Spartan 3E Starter Kit 2 Design Overvi
8. a Y Ma AAL U I Lule Wid Tad EO o0 S Noa vou GOTI HOO VoD POC oe OD OSU eS Oe 001 DET og H DOP DRO ag Peele G VPO EON GL oer ag Moye MBps i lelel Wich bles n EEEE AN eA eT pee Tapto T DO TOOT OOOO Od o ad ain 1 SX L ee u Oooo u VOD OoT Too o ODE Tao PO POO 7 TD 71 Oe cio aera ghn age cater id 2 XILINX SPARTAN 3E el s q m 1 F i E f 2 i j G I e F a du r r s i x j MJ s a C i E TM U F r P E E j i 1 Ti 1 FI 3 a i z MI b J i Tr f i 7 i i i i i ME U r Ti i 1 PEDE ae i Ma h E P j i y 5 im i a ie Meal a i se o i F a u F lj i ey f 4 i F F u 4 Ej i f fe i f F Frequency Generator for Spartan 3E Starter Kit bo e222 NA Ken Chapman Xilinx Ltd 18 July 2006 With special thanks to Peter Alfke and Alireza Kaviani Rev 1 100110011007 1001109 1001 1001100 TOO TTD Tad 007 aay chins te G01 GO 1100110041001 TOG 1 1007 100 TOO HOT BONO Limitations Limited Warranty and Disclaimer These designs are provided to you as is Xilinx and its licensors make and you receive no warranties or conditions express implied statutory or otherwise and Xilinx specifically disclaims any implied warranties of merchantability non infringement or fitness for a particular purpose Xilinx does not warrant that the functions contained in these designs will meet your requirements or that the operation of these designs
9. an perfect Fundamental 12 4125 40 74MHz ail 12 4125MHz waveform the effects of that mj Pattee 5ns of cycle jitter and jumping between CH 12 5MHz and 11 76MHz waveforms is obviously having an impact on the Me spectrum Although the fundamental frequency component is good if a little MS NI wider in bandwidth there are significant modulation effects leading to a family of spectral components and raised noise floor FFT Zoom Hint 12 5MHz 11 76MHz 0 74MHz CH1 IOOdE 1 00MiHz CIOUMS s Flattop 13 Jul 06 1606 12 4125MHz 7 XILINX Final Output Waveforms These waveforms were obtained from stake pin J4 l012 and reflect the final output of the frequency generator Once again the digital storage oscilloscope was set to infinite persistence in order capture any fluctuations over time and therefore observe the envelope of operation Mi Pos 44 00ns MEASURE CH1 Freg 12 46MHz CH1 Period oO CH1 Pos Width 40 76ns CH1 Meg Width 1 39 48ns CH1 Rise Time 3 400ns CH1 S 2 25 12 459 96MHz MEASURE CH1 Freg 12 44MHz CH1 Period o0 dins CH1 Pos Width JU on CH1 Neg Width 1 39 5205 CH1 Rise Time zen CH1 S 2 25 12 4726MHz Tek al le Tria d BA 10 0ns 13 Jul 06 15 55 Trig d Mi Pos 44 00ns CHI 1 00 Tek i BA 10 0ns 13 Jul 06 1600 CHI 1 00 In these cases the frequency shown on the LCD display directly corresponds to the frequency provided at the output However it is usefu
10. ase Accumulator Waveforms The following waveforms were obtained by monitoring the output of the phase accumulator presented on stake pin J4 IO9 In each case the digital storage oscilloscope was set to infinite persistence in order capture any fluctuations over time and therefore observe the envelope of operation Trig d BA Pos 44 00ns MEASURE CH1 Freg 12 48MHz CH1 Period oO Tens CH1 Pos Width 40 64n5 CH1 Meg Width 1 39 5205 CH1 Rise Time Sein CH1 S 224 12 5000MHz M Pos 44 00ns MEASURE CH1 Freg 12 45MHz CH1 Period UL CH1 Pos Width 40 72n5 CH1 Neg Width 1 39 5615 UH1 Rise Time 3 7 20ns CH1 Lf 2 247 12 9725MHz Tek Jla CHI 1 00 ha 10 0ns 13 Jul 06 15 58 Tek M las Tria d CHI 1 00 Mi 10 0ns 13 Jul 06 15 57 This waveform shows a pretty clean 12 5MHz square wave The reason the waveform is so clean is because 12 5MHz is a perfect division of the 200MHz clock used by the phase accumulator and it means that the synthesized waveform is always formed of 16 clock periods of the 200mHz clock with 8 Low and 8 High 12 5MHz l l l l o o o l l l l 8 cycles 8 cycles 16 cycles 200MHz 200MHz 200MHz Note that to force this frequency at the phase accumulator actually dialled in a frequency of 100MHz on to the LCD display such that N 10000000 hex This waveform shows what happens when you try to synthesize a 12 4125MHz clock using the phase accumulator
11. ator that produces the variable frequency being synthesized The remaining circuits only multiply divide and clean this synthesized frequency or are involved with selecting and generating the DDS control words The frequency of the most significant bit is defined by the 32 bit value applied to the input of the accumulator This value is shown as N on the LCD display and is applied to the bus dds_control_ word in the circuit The value of N is computed in such a way that the synthesized frequency is nominally in the range 6 25MHz to 12 5MHz so that it is always a suitable input to the second DCM Fuse 032 N x 200MHz freq_scaling frequency_divider 31 0 32 Bit Counter synth clk In this example N 204010946 decimal so the output from the phase accumulator is 9 5MHz a period of approximately 105ns That means that the accumulator synthesizes one output cycle for approximately 21 cycles of the 200MHz clock from which the accumulator runs phase_accumulator 31 0 phase_acc N dds control word 3130 gt phase_acc_dcm SOMHz elk BUF G 200MHz DCM CLKIN x4 CLKFX cik_200mhz gt CLKFX_MULTIPLY 4 BUFG CLKFX_DIVIDE 1 The first DCM is used to multiply the 50MHz clock by a factor or 4 and form a 200MHz clock This gives the l soa I phase accumulator a timing resolution of 5ns I l Frequency Generator for the Spartan 3E Starter Kit 7 A i
12. ct the DCM is only using the frequency information from the input waveform and the output cycle jitter is totally independent of the input cycle jitter Hint When using a DCM in frequency aligned mode you must accept that it does NOT maintain phase lock as it does in all other normal modes More significantly the output frequency is the average of the input frequency which means there will often be a slight difference as it tracks the input Frequency Generator for the Spartan 3E Starter Kit 11 S7 XILINX Final Output Spectrum Observing the frequency spectrum of the final output reveals that you can not get something for nothing and helps us to understand when the frequency aligned mode should and should not be used have used the infinite persistence display again and this time it was even more useful to do so As before plots on the left cover up to up to 50MHz and on plots on the right show 5MHz centred on 12 5MHz Tek num Trig d Pos 25 00MHz MATH sa grd Uperation FFT 12 5MHz Harmonic Fundamental ae A CH1 FH I I Window Flattop FFT Zoom l Flattop 13 Jul 06 TEA 12 50 00MHz Tek Pun Trig d Pos 25 00MHz MATH sa 12 4125MHz St Fundamental ve SOUCE CH1 Window Flattop IT d et ee ee ee PRN FFT Zoom Flattop 13 Jul 06 16 0 12 49725MHz These plots show that the 12 5MHz signal is debe patel UAE PR ak were actually not as good as that generated 12 5MHz re directly at the out
13. et and it may proves a cost effective solution for many real product applications too SOMHz Reference Crystal Oscillator Output Frequency oo on Spartan XC3S500E SMA socket Load it now it only takes 30 seconds Pampo Ue SD SUCA VENA FRED it wes 1 a dm bls ret It is recommended that you try this to become A 2 fDIdILENT oe dal ooon familiar with what the design does operating Ma lt u ier pro romani U am T pene rues instructions on the next page g pN ee Mpa 4 C ES STN she j i i J4 IO9 As well as the source design files a compiled fae iam configuration bit file is provided which you can Test Point immediately download into the Spartan XC3S500E device on your board To make this task really easy the first time unzip all the files J4 1012 provided into a directory and then Copy of Output double click on install_frequency_generator bat hi ai d Assuming you have the Xilinx software installed your board connected with the USB cable and the board powered don t forget the switch then this should open a DOS window and run IMPACT in batch mode to configure the Spartan 3E with the design LEDs indicate frequency editing mode Press and rotate knob DDS control values Frequency display to set frequency bottom line top line S7 XILINX Frequency Generator for the Spartan 3E Starter Kit 3 parmin we u ar iit Oh Fo Output frequency provided o
14. ew This design converts the Spartan 3E Starter Kit into a reasonably accurate frequency generator covering the nominal range 1Hz to 100MHz The design allows you to attempt generation of higher frequencies to allow you to experiment with the maximum performance of the Spartan device on your board The rotary control is used to edit the frequency displayed on the upper line of the LCD display and the corresponding frequency will then be output on the SMA connector J17 as well as the stake pin J4 lO12 Internally to the device the frequency range is twice that provided externally nominally up to 200MHz As well as providing the basic instructions to use the frequency counter this document provides details of the Direct Digital Synthesis DDS techniques used in the design such that the can be transplanted into your own designs PicoBlaze is used to provide the human interface and perform so high precision calculations which are passed to a simple but high performance 200MHZz frequency synthesizer formed from pure hardware and two Digital Clock Managers DCMs The lower line of the LCD display provides the information passed from PicoBlaze to the hardware which means that you can use this design with your board to determine the exact values required to implement a fixed frequency synthesizer without requiring PicoBlaze the knob and LCD display On this board the technique provides a convenient alternative to fitting a special oscillator in the IC16 sock
15. l to understand what the phase accumulator is generating to appreciate if the second DCM in frequency aligned mode is helping For this 12 5MHz waveform N 08000000 hex and D 02 hex So in fact the phase accumulator is synthesizing 6 25MHz This is again a perfect division of the 200MHz clock and means that the synthesized waveform is always formed of 32 clock periods with 16 Low and 16 High There is therefore no obvious cycle jitter introduced and therefore it is not surprising that the final output 6 25MHz x 16 2 1 12 5MHz is also nice and clean You may have to look closely to notice that this second plot really is 12 4125MHz It is immediately clear that there is no obvious cycle to cycle jitter present To confirm that this isn t just a coincidence we must again consider what the phase accumulator is doing at the same time With 12 4125MHz set N OFE353F7 hex and D 03 hex So in fact the phase accumulator is actually synthesizing 12 4125MHz as well More significantly it means that the phase accumulator is generating exactly the same waveform as we observed previously on page 9 in which there was 5ns of cycle to cycle jitter present see right Phase Actumulator The final output 12 1425MHz x 16 2 1 12 1245MHz shows that the frequency aligned mode of the DCM is tracking the average frequency of the input waveform and totally ignoring the phase of the input waveform resulting in a very low cycle to cycle jitter In fa
16. n SMA connector J17 pom a out TEN ha and J4_1012 Mi Flash giin TE ia al ik nstructions LEDs indicate the editing mode U U U U U U U U Edit cursor position mode OOOOODOBMO Edit digit value mode oo The cursor is the small black line under the digit in the top line The cursor can be moved into the Press and release knob to toggle between frequency editing modes 10MHz and 100MHz digit positions but these positions are blanked when zero Edit cursor position mode In this mode rotating the knob to the left or right will cause the display cursor to move in the corresponding direction on the upper line of the display Use this mode to position the cursor below the digit you wish to adjust and then press and release the knob to change mode The cursor automatically skips past the decimal point and space separator and hits end stops if you over rotate the knob Edit digit value mode In this mode rotating the knob to the left or right will decrement or increment the value of the digit located at the cursor position The controller will automatically borrow from or carry to the more significant digits to the left of the digit being adjusted Every adjustment will immediately result in the corresponding frequency change at the output which is also reflected by the changes to the computed DDS control values on the lower line of the display Press and release the knob to revert to cursor position mode when complete
17. pplications can actually benefit from the partial soread spectrum effect i e reduced EMC Fixed Frequency Modules If you know which frequencies you require then reduce the design to a phase accumulator driven by a constant N the DCMs and a fixed counter divider no multiplexer Hint If you still operate the phase accumulator at 2O0MHz then use the supplied design on the board to calculate your N and D values for you Hint Remember to share the 200MHz fast clock between several phase accumulators to save DCMs Accurate Measurements If you have access to superior measurement equipment then measure the frequency generator output for yourself and observe the tracking nature of the output Be careful not to confuse I O and PCB effects with what you are attempting to measure using such good equipment Simple Frequency Measurements using the Spartan 3E Starter Kit Create a fixed frequency version of the design for a frequency of your choice Then insert that module into the reference design called PicoBlaze Frequency Counter for the Spartan 3E Starter Kit Board in place of one of the existing sources so that you can observe the output frequency Hint The output frequency should be correct but you should be observing a variation above and below as the DCM tracks the average frequency value Design Throttling This term is given to the concept of changing the frequency depending on the demands of an application ove
18. psm3 vhd PicoBlaze processor for Spartan 3E devices fg_ctrl vhd Assembled program for PicoBlaze stored in a Block memory Cease fg_ctrl psm PicoBlaze program source assembler code This design contains an otherwise undocumented and unspecified mode of operation for a DCM Before this design can be processed a special BITGEN option needs to be set Please read the notes provided on page 13 as well as those contained in frequency_generator vhd for details of this special requirement Note The file shown in green is not included with the reference design as it is provided with PicoBlaze download Please visit the PicoBlaze Web site for your free copy of PicoBlaze assembler JTAG_loader and documentation www xilinx com picoblaze Hint The JTAG_Loader utility supplied with PicoBlaze has been included in this design This enables the new programs to be written for PicoBlaze using the configuration file provided Hint You do not need PicoBlaze if you use this design as the basis for implementing a fixed frequency module However I m sure you will want PicoBlaze for other parts of your design now that you have seen what it is capable of doing S7 XILINX Frequency Generator for the Spartan 3E Starter Kit 6 Direct Digital Synthesis DDS Circuit Diagram The phase accumulator is a standard 32 bit accumulator operating at 200MHz This accumulator is really the heart of the DDS as it is the most significant bit of the accumul
19. put of the phase Fundamental_ ij accumulator Although clearly centred at CITER 12 5MHz the spectrum shows that there is TM CH1 an increased bandwidth This reflects that the DCM is tracking the input frequency H even though it doesn t really need to do anything It is rather like balancing on a wall aire we know the wall isn t moving but we stil s s GM Flattop wobble a bit to stay balanced because we are unable to freeze completely due to other iaemmmanill FFT Zoom influences on us and the need to breath etc Flattop 5MHz division 1MHZz division PSUs Uae ee 10dB division 10dB division Tek S Tu Pos 12 48MHz MATH The full spectrum of the 12 4125MHz case i oe shows how the previous family of spectral components associated with the 5ns of cycle sale jitter have been removed and that the noise 1 3MHz au floor has been returned to normal levels The zoomed plot now shows a fundamental with Ta what looks like modulation sidebands rather MAREE CER than fixed spectral components at 0 74MHz window This again reflects average frequency 2 quantis MENE deiae tracking as well as the removal of the Sns geld MRC RL al FFT Zoom cycle jitter Note that an agile frequency i component has a lower energy W Hz thana cui node 00MHs CTUUMS 5 Flattop static component 13 Jul 06 16 02 42 41 25MHz Hint If you can synthesize a perfect waveform with a phase accumulator or other direct clock division circuit
20. r time This is a way to Save power since power consumption is directly proportional to operating frequency The frequency aligned mode allows you to switch between frequencies without causing glitches and you can prove this with the design provided Hint Increasing CCount read notes in frequency_generator vhd will provide very smooth but relatively slow rates of change in frequency S7 XILINX Frequency Generator for the Spartan 3E Starter Kit 14
21. rectly Open without Updating aL Properties z Process Properties x Se Category General Options Configuration Options af Processes Startup Options Readback Options Property Name Create Binary Configuration File Create ASCII Configuration File Create IEEE 1532 Configuration File Enable BitStream Compression Enable Debugging of Serial Mode BitStream Enable Cyclic Redundancy Checking CRC Iv gctg_dfs_s_ Hint The format of this special DOM option are described in some detail in the frequency_generator vhd file from which you can also copy and paste to avoid typing errors 197 171100007111111 1 sxx 1 1 xxexe xx MERKEREREM RERERRERERERERERRRERRR T OOOOOD Property display level Advanced Default Cancel Apply Help Other Bitgen Command Line Options g cCfg_dfs_s_ x1y1 1111000011111111xxx111XXxxXxX1XXXXXXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXO1 000000 S7 XILINX Frequency Generator for the Spartan 3E Starter Kit 13 Exercises Experiments and Suggestions Here are some exercises experiments and suggestions for you to consider based on this reference design Although several are specific to the Spartan 3E Starter Kit most are portable to your own boards and designs where hope you will find the design concept useful Turn it off Probably the best way to convince yourself that the frequency aligned mode
22. scaling word D Hint The fg_cirl osm file contains significant comments to explain the operations and calculations that the PicoBlaze program is performing to generate N and D from the BCD value displayed on the LCD rolLary press x rotary_press_in 50MHz clock to all items on this page clk rotary_filter amp direction See reference 1 design called rotary a Rotary Encoder rotary b Interface for i Kit for details of I rotary_left I i rotary event Spartan 3E Starter l I this section Frequency Generator for the Spartan 3E Starter Kit 8 led 7 output_ports JTAG_loader allows rapid PicoBlaze code development HMA program_rom to err proc_reset bidirectional LCD data instruction l clk address kcpsm3_reset kcpsm3 processor address Instruction input_ports instruction address H out port ut p rt i lcd_rs in_port NO CW os O1 J write_strobe S it write strobe read_strobe read_strobe porte aid aa interrupt JO N V7 O VIS interrupt interrupt_ack dds_scaling_word D S interrupt_control Sh324 OR IU interrupt_ack dds_control_word StrataFLASH memory N must be disabled to prevent interference with the LCD display strataflash_oe strataflash_ce strataflash_we Ph
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