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Texas Instruments TVP5147M1PFP User's Manual

1. 37 AVID Start Pixel Register 37 AVID Stop Pixel Register WAWA 38 HSYNC Start Pixel Register ii aaa 38 HSYNC Stop Pixel Register aa 38 VSYNC Start Line Register 38 VSYNC Stop Line Register AA KUA EA 39 VBLK Start Line Register oooooococcoccccccccocn ees 39 VBLK Stop Line Register 39 CTI Delay Register 220202 veshim ese Se eres dd eyed eee 39 CTI Control Register AA aa 40 Sync Control Register ANA wa 40 Output Formatter 1 Register aa 41 Output Formatter 2 Register AI Wa ohi 41 Output Formatter 3 Register 42 Output Formatter 4 Register 43 Output Formatter 5 Register aa 44 Output Formatter 6 Register 45 Clear Lost Lock Detect Register 45 Status 1 Register causa ia quedes pied erba ewe 46 Status 2 Register AAA nbn aee asta eodd xr a RE ed quss 47 AGC Gain Status Register 47 Video Standard Status Register 48 GPIO Input 1 Register cece eR Re 48 GPIO Input 2 Register IA WAA eens 49 AFE Coarse Gain for CH 1 Register
2. 19 2 15 Horizontal Synchronization Signals for 20 Bit 4 2 2 Mode 20 2 16 VSYNC Position With Respect to HSYNC 21 2 11 VBUS ACCESS it et ce areata adhue LL piu Mu M LE 23 2 18 Reset Timing ii terere nt eek pore o dn di e bed dee olo doe RAD ER de send 26 2 19 Teletext Filter Function AA piae i aina a ie adoa RII RI rns 63 3 1 Clocks Video Data and Sync Timing 0 0 ccc eect nee n teens 81 3 2 eC Host POR TIBI a rad IIIA 81 5 1 Example Application CIFCUIL s a ai kd ou eR I dd 87 July 2005 3 TEXAS SLES140 vii INSTRUMENTS List of Tables List of Tables Table Title Page 1 1 Terminal FUNCIONS IAA ii sa 6 2 1 Output Format s c t iio ted dee h hd An ead 16 2 2 Summary of Line Frequencies Data Rates and Pixel Line Counts 16 2 3 EAV and SAV Sequence ii AAA 21 2 4 I2C Host Interface Terminal Description umwwwnms 22 2 5 2C Address Selection vdes edu tdi it deberi a d LARA d bue ope oh Bad dios dadas gigs 22 2 6 Supported VBI System s si siteu kiai aa cece nen hh hh 24 2 7 Ancillary Data Format and Sequence n 25 2 8 VBI Raw Data Output Format AA KWa 26 2 9 Reset Sequelic iia deci winks AA ene ee ae herd ade 26 2 10 12C Register Summary na jau ake A AA RA 27 2 11 VBUS Register Summary IIIA
3. 2 11 44 AFE Fine Gain for Pb Register Subaddress 4Ah 4Bh 900h FGAIN 1 7 0 FGAIN 1 11 8 FGAIN 1 11 0 This fine gain applies to component Pb Fine_Gain 1 2048 FGAIN 1 where 0 lt FGAIN 1 lt 4095 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 1111 1111 1 9995 1100 0000 0000 1 5 1001 0000 0000 1 125 default 1000 0000 0000 1 0100 0000 0000 0 5 0011 1111 1111 to 0000 0000 0000 Reserved 2 11 45 AFE Fine Gain for Y Chroma Register Subaddress 4Ch 4Dh 900h Subaddress FGAIN 2 7 0 FOAN ATTE FGAIN 2 11 0 This gain applies to component Y channel or S video chroma see AFE fine gain for Pb register Section 2 11 44 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 1111 1111 1 9995 1100 0000 0000 1 5 1001 0000 0000 1 125 default 1000 0000 0000 1 0100 0000 0000 0 5 0011 1111 1111 to 0000 0000 0000 Reserved 2 11 46 AFE Fine Gain for Pr Register Subaddress 4Eh 4Fh 900h Subaddress FGAIN 3 7 0 FANI FGAIN 3 11 0 This fine gain applies to component Pr see AFE fine gain for Pb register Section 2 11 44 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 1111 1111 1 9995 1100 0000 0000 1 5 1001 0000 0000 1 125 default 1000 0000 0000 1 0100 0000 000
4. 2 11 61 Chip ID LSB Register Subaddress 81h Read only L Y s s 2 o Chip ID LSB 7 0 Chip ID LSB 7 0 This register identifies the LSB of the device ID Value 47h 2 11 62 CPLL Speed Control Register Subaddress 83h Default Speed T Speed 3 0 Color PLL speed control 1001 Faster default 1010 1011 Slower Other Reserved SLES140A March 2007 X TEXAS TVP5147M1PFP 59 INSTRUMENTS Functional Description 2 11 63 Status Request Register Subaddress 97h ERE LE WA LA qno LI 4 Reserved Capture Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count registers Since this capture is not immediate it is necessary to check for completion of the capture by reading the capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor Once the capture bit is Ob the AGC status and vertical line counters 3Ch 3Dh and 9Ah 9Bh have been updated and can be safely read in any order 2 11 64 Vertical Line Count Register Read only Subaddress 7 6 8 3 2 1 o 9Ah Vertical line 7 0 9Bh Reserved Vertical line 9 8 Vertical line 9 0 represents the detected a total number of lines from the previous frame This can be used with nonstandard video signals such as a VCR in trick mode to synchronize downstream video circuitry Since this re
5. CTI delay 2 0 Sets the delay of the Y channel with respect to Cb Cr in the CTI block 011 3 pixel delay 001 1 pixel delay 000 0 delay default 111 1 pixel delay 100 4 pixel delay di SLES140A March 2007 TEXAS TVP5147M1PFP 39 INSTRUMENTS Functional Description 2 11 25 CTI Control Register Subaddress 2Eh gt PEO SA o X NI A E 9 CTI coring 3 0 CTI gain 3 0 CTI coring 3 0 4 bit CTI coring limit control value unsigned linear control range from 0 to 60 step size 4 1111 60 0001 4 0000 0 default CTI gain 3 0 4 bit CTI gain control values unsigned linear control range from 0 to 15 16 step size 1 16 1111 15 16 0001 1 16 0000 0 disabled default 2 11 26 Sync Control Register Subaddress 32h Polarity FID Polarity VS Polarity HS VS VBLK HS CS Polarity FID determines polarity of FID terminal 0 First field high second field low default 1 First field low second field high Polarity VS determines polarity of VS terminal 0 Active low default 1 Active high Polarity HS determines polarity of HS terminal 0 Active low default 1 Active high VS or VBLK 0 VS terminal outputs vertical sync default 1 VS terminal outputs vertical blank HS or CS 0 HS terminal outputs horizontal sync default 1 HS terminal outputs composite sync 40 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 1
6. vi SLES140 3 TEXAS INSTRUMENTS July 2005 List of Illustrations List of Illustrations Figure Title Page 1 1 Functional Block Diagram IIIA a a a di 4 1 2 Terminal Assignments Diagram 0 000 o 5 2 1 Analog Processors and A D Converters 9 2 2 Digital Video Processing Block Diagram 11 2 3 Composite and S Video Processing Block Diagram 12 2 4 Color Low Pass Filter Frequency Response 13 2 5 Color Low Pass Filter With Filter Characteristics NTSC PAL ITU R BT 601 Sampling 13 2 6 Chroma Trap Filter Frequency Response NTSC ITU R BT 601 Sampling 13 2 7 Chroma Trap Filter Frequency Response PAL ITU R BT 601 Sampling 13 2 8 Luminance Edge Enhancer Peaking Block Diagram 14 2 9 Peaking Filter Response NTSC PAL ITU R BT 601 Sampling 14 2 10 Reference Clock Configurations 15 2M RIG TIMING sock Pr 15 2 12 Vertical Synchronization Signals for 525 Line System 17 2 13 Vertical Synchronization Signals for 625 Line System 18 2 14 Horizontal Synchronization Signals for 10 Bit 4 2 2 Mode
7. M 2 0 and five bits of row address R 4 0 interlaced with eight Hamming protection bits H 7 0 The mask bits enable filtering using the corresponding bit in the pattern register For example a 1 in the LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to the first data bit on the transaction If these match then a true result is returned A 0 in a bit of mask means that the filter module must ignore that data bit of the transaction If all Os are programmed in the mask bits then the filter matches all patterns returning a true result default 00h SLES140A March 2007 X TEXAS TVP5147M1PFP 61 INSTRUMENTS Functional Description 2 11 67 VDP TTX Filter Control Register Subaddress BBh CAERSE A EA AE E A Filter logic 1 0 TTX filter 2 enable TTX filter 1 enable Filter logic 1 0 Allow different logic to be applied when combining the decision of filter 1 and filter 2 as follows 00 NOR default 01 NAND 10 OR 11 AND Mode indicates which teletext mode is in use 0 Teletext filter applies to 2 header bytes default 1 Teletext filter applies to 5 header bytes TTX filter 2 enable provides for enabling the teletext filter function within the VDP 0 Disabled default 1 Enabled TTX filter 1 enable provides for enabling the teletext filter function within the VDP 0 Disabled default 1 Enabled If the filter matches or if the filter mas
8. March 2007 X TEXAS TVP5147M1PFP 65 INSTRUMENTS Functional Description 2 11 77 VDP Full Field Enable Register Subaddress D9h Default 00h 7 e 5 4 3 2 3 o Reserved Full field enable Full field enable 0 Disabled full field mode default 1 Enabled full field mode This register enables the full field mode In this mode all lines outside the vertical blank area and all lines in the line mode register programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh Values other than FFh in the line mode registers allow a different slice mode for that particular line 2 11 78 VDP Full Field Mode Register Subaddress DAh Default FFh L v s p s p 2 1 e Full field mode 7 0 Full field mode 7 0 This register programs the specific VBI standard for full field mode It can be any VBI standard Individual line settings take priority over the full field register This allows each VBI line to be programmed independently but have the remaining lines in full field mode The full field mode register has the same bit definition as line mode registers default FFh Global line mode has priority over the full field mode 2 11 79 VBUS Data Access With No VBUS Address Increment Register Subaddress EOh Default 00h x s J s x AA p pw II VBUS data 7 0 VBUS data 7 0 VBUS data register for VBUS single byte read write transaction 2 11 80
9. No effect default 1 Clear bit 2 Macrovision status changed in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h Standard changed Clear standard changed flag 0 No effect default 1 Clear bit 1 video standard changed in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h FIFO full Clear FIFO full flag 0 No effect default 1 Clear bit 0 FIFO full flag in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h 72 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 12 VBUS Register Definitions 2 12 1 VDP Closed Caption Data Register Read only 80 051Ch Closed caption field 1 byte 1 80 051Dh Closed caption field 1 byte 2 80 051Eh Closed caption field 2 byte 1 80 051Fh Closed caption field 2 byte 2 These registers contain the closed caption data arranged in bytes per field 2 12 2 VDP WSS Data Register WSS NTSC CGMS Read only som p soosezn ooo soo These registers contain the wide screen signaling data for NTSC Bits 0 1 represent word 0 aspect ratio Bits 2 5 represent word 1 header code for word 2 Bits 6 13 represent word 2 copy control Bits 14 19 represent word 3 CRC PAL SECAM Read only 7 4 3 7 p soosesh JI ws Jese on eo t PAL SE
10. Not available 1 Available WSS WSS data available unmasked 0 Not available 1 Available VPS VPS data available unmasked 0 Not available 1 Available VITC VITC data available unmasked 0 Not available 1 Available CC F2 CC field 2 data available unmasked 0 Not available 1 Available is SLES140A March 2007 TEXAS TVP5147M1PFP 67 INSTRUMENTS Functional Description CC F1 CC field 1 data available unmasked 0 Not available 1 Available Line Line number interrupt unmasked 0 Not available 1 Available The host interrupt raw status 0 and 1 registers represent the interrupt status without applying mask bits 2 11 84 Interrupt Raw Status 1 Register Read only H V lock Macrovision status changed Standard changed FIFO full H V lock unmasked 0 H V lock status unchanged 1 HIV lock status changed Macrovision status changed unmasked 0 Macrovision status unchanged 1 Macrovision status changed Standard changed unmasked 0 Video standard unchanged 1 Video standard changed FIFO full unmasked 0 FIFO not full 1 FIFO was full during write to FIFO The FIFO full error flag is set when the current line of VBI data cannot enter the FIFO For example if the FIFO has only 10 bytes left and teletext is the current VBI line then the FIFO full error flag is set but no data is written because the entire teletext line does not fit However if the next VBI line is closed caption
11. PLASTIC QUAD FLATPACK Thermal Pad See Note D S ho 0 9 50 TYP 3 y lose Plane T y 1220 lt 0 m 11 80 0 25 14 20 13 80 SQ Seating Plane 710 08 4146925 B 08 03 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAO02 for information regarding recommended board layout This document is available at www ti com http www ti com gt E Falls within JEDEC MS 026 PowerPAD is a trademark of Texas Instruments 435 TEXAS INSTRUMENTS www ti com WA TEXAS THERMAL PAD MECHANICAL DATA INSTRUMENTS PFP S PQFP G80 THERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes
12. VL3_C Figure 2 1 Analog Processors and A D Converters 2 1 1 Video Input Switch Control The TVP5147M1 decoder has two analog channels that accept up to 10 video inputs The user can configure the internal analog video switches via the 12C interface The 10 analog video inputs can be used for different input configurations some of which are via SLES140A March 2007 TEXAS TVP5147M1PFP 9 INSTRUMENTS Functional Description e Upto 10 selectable individual composite video inputs e Up to four selectable S video inputs e Upto three selectable analog YPbPr video inputs and one CVBS input e Up to two selectable analog YPbPr video inputs two S video inputs and two CVBS inputs The input selection is performed by the input select register at IC subaddress 00h see Section 2 11 1 2 1 2 Analog Input Clamping An internal clamping circuit restores the ac coupled video signal to a fixed dc level The clamping circuit provides line by line restoration of the video sync level to a fixed dc reference voltage The selection between bottom and mid clamp is performed automatically by the TVP5147M1 decoder 2 1 3 Automatic Gain Control The TVP5147M1 decoder uses two programmable gain amplifiers PGAs one per channel The PGA can scale a signal with a voltage input compliance of 0 5 Vpp to 2 0 Vpp to a full scale 10 bit A D output code range A 4 bit code sets the coarse gain with individual adjustment per channel Minimum gain corre
13. minimum 2 11 7 Luminance Processing Control 1 Register Subaddress 06h A jw pls eee O m d Pedestal not present Luminance signal delay 3 0 Pedestal not present 0 7 5 IRE pedestal is present on the analog video input signal default 1 Pedestal is not present on the analog video input signal VBI raw 0 Disabled default 1 Enabled During the duration of the vertical blanking as defined by the VBLK start and stop line registers at subaddresses 22h through 25h see Sections 2 11 22 and 2 11 23 the chroma samples are replaced by luma samples This feature can be used to support VBI processing performed by an external device during the vertical blanking interval In order to use this bit the output format must be 10 bit ITU R BT 656 mode Luminance signal delay 3 0 Luminance signal delays with respect to the chroma signal in 1x pixel clock increments 0111 Reserved 0110 6 pixel delay 0001 1 pixel delay 0000 0 delay default 1111 1 pixel delay 1000 8 pixel delay 34 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 8 Luminance Processing Control 2 Register Subaddress 07h LoT 8 J s j 4 3 23 1 0 Luma filter select 1 0 Peaking gain 1 0 Luma filter selected 1 0 00 Luminance adaptive comb enabled default on CVBS 01 Luminance adaptive comb disabled trap filter selected 10 Luma comb trap filter bypassed default on S vide
14. solder stencil thicknesses COO ibni zs A MONON Defined Pad See Note C D 13 2 See Note E Example Center Power Pad Solder Stencil Opening SCENE Stencil Thickness See Note F 0 127mm 0 152mm 0 178mm Example Pad Geometry 4208544 3 A 03 07 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAOO2 SLMAO04 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com Publication IPC SM 782 is recommended for alternate designs E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Example stencil design based on a 50 volumetric metal load solder paste Refer to IPC 7525 for other stencil recommendations F Customers should contact their board fabrication site for solder mask tolerances between and around signal pads cos 35 TEXAS INSTRUMENTS www ti com
15. 2 17 VBUS Access SLES140A March 2007 X TEXAS TVP5147M1PFP 23 INSTRUMENTS Functional Description 2 7 VBI Data Processor The TVP5147M1 VBI data processor VDP slices various data services like teletext WST NABTS closed caption CC wide screen signaling WSS program delivery control PDC vertical interval time code VITC video program system VPS copy generation management system CGMS data and electronic program guide Gemstar 1x 2x Table 2 6 shows the supported VBI system These services are acquired by programming the VDP to enable the reception of one or more vertical blank interval VBI data standard s during the VBI The VDP can be programmed on a line per line basis to enable simultaneous reception of different VBI formats one per line The results are stored in a FIFO and or registers Because of the high data bandwidth teletext results are stored in FIFO only The TVP5147M1 decoder provides fully decoded V Chip data to the dedicated registers at subaddresses 80 0540h 80 0543h Table 2 6 Supported VBI System VBI SYSTEM STANDARD LINE NUMBER NUMBER OF BYTES PAL 6 22 Fields 1 and 2 Closed Caption NTSC 21 Fields 1 and 2 2 wm 0 a WA WA VPS PDC PAL V Chip decoded 21 Fields 1 and 2 mw se UR Any Programmable Programmable 24 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 7 1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be outpu
16. AAA 30 2 12 Analog Channel and Video Mode Selection aa 31 viii SLES140 3 TEXAS July 2005 INSTRUMENTS Introduction 1 Introduction The TVP5147M1 device is a high guality single chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video The TVP5147M1 decoder supports the analog to digital A D conversion of component YPbPr signals as well as the A D conversion and decoding of NTSC PAL and SECAM composite and S video into component YCbCr This decoder includes two 10 bit 30 MSPS A D converters ADCs Preceding each ADC in the device the corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and applies a programmable gain and offset A total of 10 video input terminals can be configured to a combination of YPbPr CVBS or S video video inputs Composite or S video signals are sampled at 2x the ITU R BT 601 clock frequency line locked alignment and are then decimated to the 1x pixel rate CVBS decoding uses five line adaptive comb filtering for both the luma and chroma data paths to reduce both cross luma and cross chroma artifacts A chroma trap filter is also available On CVBS and S video inputs the user can control video characteristics such as contrast brightness saturation and hue via an I2C host port interface Furthermore luma peaking sharpness with programmable gain is included as well as a patented chro
17. Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Low Power Wireless www ti com lpw Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright O 2007 Texas Instruments Incorporated Contents Contents Section 1 MU AI A A A aa 1 1 Detailed Functionality 1 2 TVP5147M1 Applications net nee 1 3 Related ProOdUCIS nani dk EAEE AREENA REDA 1 4 Ordering Informatlon AI osua a Aa ka 1 5 Functional Block Diagram i22 td yn ence ted m e s 1 6 Terminal Assignments s hs 1 7 Terminal F hctions wi aum AA A dede aod AA e EAD EEA 2 Functional Description AA A ede We ee 2 1 Analog Processing and A D Converters 2 1 1 Video Input Switch Control 2 1 2 Analog Input Clamping se seisean a aeara eens 2 1 3 Automatic Gain Control 0 0 WA 2 1 4 Analog Video Output UA een e eens 2 1 5 A D Converters s kd
18. Data transfers occur using the following illustrated formats Read from 12C control registers s sero ack Subadaess ack J rono Ack Receive ata Nak P S 12C bus start condition P 12C bus stop condition ACK Acknowledge generated by the slave NAK Acknowledge generated by the master for multiple byte read master with ACK each byte except last byte Subaddress Subaddress byte Data Data byte If more than one byte of data is transmitted read and write the subaddress pointer is automatically incremented I2C bus address Example shown that 12CA is in default mode Write B8h read B9h 2 6 3 VBUS Access The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24 bit address wide VBUS Figure 2 17 shows the VBUS register access 22 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 12C Registers VBUS Registers 00 0000h HOST 80 051Ch Processor 80 0520h 80 052Ch h VBUS 80 0600 Data 700h VBUS 80 0700 Address 90 1904h FF FFFEh VBUS VVrite Single Byte eT dec e Tee pe em Te Multiple Bytes e eT TT epe Te Te e epe Te e Pa ee T VBUS Read Single Byte eT Te Tee Te Te e Tee Te e Ten TT Multiple Bytes e pee epo en e e Sp T Te n n en ne os NOTE Examples use default I2C address ACK Acknowledge generated by the slave NAK No acknowledge generated by the master Figure
19. F bit and V bit adaptation to detected lines per frame F bit mode 1 0 00 Auto mode If lines per frame is standard decoded F and V bits as per 656 standard from line count else decode F bit from VSYNC input and set V bit O default 01 Decode F and V bits from input syncs 10 Reserved 11 Always decode F and V bits from line count This register is used in conjunction with the F bit and V bit control 2 register subaddress 75h as indicated below a so amo foe ee TE Po o o o Reserved Resowed Reseved Reseved Resend aa wee Swee Po fo 0 mee s s Pe o TI es e tego swo 99 sees Po E Po Resevea Reserved Reserved Reserved Reserved To o Reseved Reserved Reserved Reserved Reserved Le pee m T m aae o mesas e Jese Pulse Switch T 656 ITU R BT 656 standard Toggle Toggles from field to field Pulse Pulses low for 1 line prior to field transition Switch V bit switches high before the F bit transition and low after the F bit transition Switch9 V bit switches high 1 line prior to F bit transition then low after 9 lines Reserved Not used 1 54 TVP5147M1PFP X TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 50 Back End AGC Control Register Subaddress 6Ch This register disables the back end AGC when the front end AGC uses specific amplitude references sync height color burst or compo
20. Line alternating status 0 Nonline alternating 1 Line alternating Field rate status 0 60 Hz 1 50 Hz Lost lock detect 0 No lost lock since this bit was cleared 1 Lost lock since this bit was cleared Color subcarrier lock status 0 Color subcarrier is not locked 1 Color subcarrier is locked Vertical sync lock status 0 Vertical sync is not locked 1 Vertical sync is locked Horizontal sync lock status 0 Horizontal sync is not locked 1 Horizontal sync is locked TV VCR status 0 TV 1 VCR wa 46 TVP5147M1PFP TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 35 Status 2 Register Read only ETA EA o ES A aaa Signal present Weak signal detection PAL switch polarity Field sequence status Color killed Macrovision detection 2 0 Signal present detection 0 Signal not present 1 Signal present Weak signal detection 0 No weak signal 1 Weak signal mode PAL switch polarity of first line of odd field 0 PAL switch is zero 1 PAL switch is one Field sequence status 0 Even field 1 Odd field Color killed 0 Color killer not active 1 Color killer activated Macrovision detection 2 0 000 No copy protection 001 AGC pulses pseudo syncs present type 1 010 2 line color stripe only present 011 AGC pulses pseudo syncs and 2 line color stripe present type 2 100 Reserved 101 Reserved 110 4 line color stripe onl
21. U 5 Line Adaptive Comb Filter Burst Accumulator V Color LPF 12 CVBS C NTSC PAL Delay Delay Demodulation Figure 2 3 Composite and S Video Processing Block Diagram 2 2 2 1 Color Low Pass Filter High filter bandwidth preserves sharp color transitions and produces crisp color boundaries However for nonstandard video sources that have asymmetrical U and V side bands it is desirable to limit the filter bandwidth to avoid UV crosstalk The color low pass filter bandwidth is programmable to enable one of the three notch filters Figure 2 4 and Figure 2 5 represent the frequency responses of the wideband color low pass filters 12 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description Filter 2 3 dB 844 kHz Filter 0 3 dB 1 41 MHz Filter 3 m 3 dB 554 kHz I I o o Filter 1 E E 3 dB 2 ri E E lt lt 0 0 05 10 15 20 25 30 35 4 0 00 05 10 15 20 25 30 35 4 0 f Frequency MHz f Frequency MHz Figure 2 4 Color Low Pass Filter Frequency Figure 2 5 Color Low Pass Filter With Filter Response Characteristics NTSC PAL ITU R BT 601 Sampling 2 2 2 2 Y C Separation Y C separation can be done using adaptive 5 line 5 H delay comb filters or a chroma trap filter The comb filer can be selectively bypassed in the luma or chroma path If the comb filter is bypass
22. VBUS Data Access With VBUS Address Increment Register Subaddress Eth Default 00h ee fs _ w VBUS data 7 0 VBUS data 7 0 VBUS data register for VBUS multibyte read write transaction VBUS address is autoincremented after each data byte read write 6 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS o Functional Description 2 11 81 FIFO Read Data Register E2h Read only EAS s E 1238 1 ee ee FIFO read data 7 0 FIFO read data 7 0 This register is provided to access VBI FIFO data through the 12C interface All forms of teletext data come directly from the FIFO while all other forms of VBI data can be programmed to come from registers or from the FIFO If the host port is to be used to read data from the FIFO then bit O host access enable in the VDP FIFO output control register at subaddress COh must be set to 1 see Section 2 11 71 2 11 82 VBUS Address Access Register Subaddress E8h E9h EAh Swadres 7 6 5 4 383 2 1 9 Es VBUS address 7 0 E8h E9h VBUS address 15 8 VBUS address 23 16 VBUS address 23 0 VBUS is a 24 bit wide internal bus The user needs to program in these registers the 24 bit address of the internal register to be accessed via host port indirect access mode 2 11 83 Interrupt Raw Status 0 Register FOh Read only FIFO THRS FIFO THRS FIFO threshold passed unmasked 0 Not passed 1 Passed TTX Teletext data available unmasked 0
23. and other output control signals such as genlock for CVBS and S video inputs Additionally it can provide field identification horizontal and vertical lock vertical blanking and active video window indication signals The digital data output can be programmed to two formats 20 bit 4 2 2 with external syncs or 10 bit 4 2 2 with embedded separate syncs The circuit detects pseudosync pulses AGC pulses and color striping in Macrovision encoded copy protected material Information present in the VBI interval can be retrieved and either inserted in the ITU R BT 656 output as ancillary data or stored in internal FIFO and or registers for retrieval via the host port interface Copy VBI Data Protection Slice VBI Data Detector Processor Y 9 0 Output E Formatter CH1 A D x Decimation CVBS Y C 9 0 Composite X CIChCr Processor CH2 A D Decimation XTAL1 FID XTAL2 VS VBLK ee Host RESETB T HS CS os diac Interface SDA PWDN GLCO DATACLK AVID Figure 2 2 Digital Video Processing Block Diagram 2 2 1 2x Decimation Filter All input signals are typically oversampled by a factor of 2 27 MHz The A D outputs initially pass through decimation filters that reduce the data rate to 1x the pixel rate The decimation filter is a half band filter Oversampling and decimation filtering can effectively increase the overall signal to noise ratio by 3 dB 2 2 2 Composite Processor Figure 2 3 is a block di
24. data to this register clears the FIFO and VDP data register CC WSS VITC and VPS After clearing this register is automatically cleared 2 11 71 VDP FIFO Output Control Register Subaddress COh Default 00h L x e a 3 221 4 o Reserved Host access enable Host access enable This register is programmed to allow the host port access to the FIFO or to allow all VDP data to go out the video output 0 Output FIFO data to the video output Y 9 2 default 1 Allow host port access to the FIFO data 2 11 72 VDP Line Number Interrupt Register Subaddress Cih Default 00h z7 e 5 4 a 2 o Field 1 enable Field 2 enable Line number 5 0 Field 1 interrupt enable 0 Disabled default 1 Enabled Field 2 interrupt enable 0 Disabled default 1 Enabled Line number 5 0 Interrupt line number default 00h This register is programmed to trigger an interrupt when the video line number exceeds this value in bits 5 0 This interrupt must be enabled at address F4h NOTE The line number value of 0 or 1 is invalid and does not generate an interrupt i TVP5147M1PFP alg TEXAS SLES140A March 2007 INSTRUMENTS o R Functional Description 2 11 73 VDP Pixel Alignment Register Subaddress C2h C3h O1Eh Pixel alignment 7 0 Pixel alignment 9 8 Pixel alignment 9 8 These registers form a 10 bit horizontal pixel position from the falling edge of horizontal sync where the VDP
25. default 1 DATACLK outputs are enabled SLES140A March 2007 X TEXAS TVP5147M1PFP 41 INSTRUMENTS Functional Description 2 11 29 Output Formatter 3 Register MRS EEN a IST E IA Jp pow y ow GPIO 1 0 FSS terminal function select 00 GPIO is logic 0 output 01 GPIO is logic 1 output 10 Reserved 11 GPIO is logic input default AVID 1 0 AVID terminal function select 00 AVID is logic O output 01 AVID is logic 1 output 10 AVID is active video indicator output 11 AVID is logic input default GLCO 1 0 GLCO terminal function select 00 GLCO is logic O output 01 GLCO is logic 1 output 10 GCLO is genlock output 11 GCLO is logic input default FID 1 0 FID terminal function select 00 FID is logic O output 01 FID is logic 1 output 10 FID is FID output 11 FID is logic input default 42 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 30 Output Formatter 4 Register 7 5 4 3 2 1 o VS NBLK 1 0 HS CS 1 0 C 1 1 0 C O 1 0 VS VBLK 1 0 VS terminal function select 00 VS VBLK is logic O output 01 VS VBLK is logic 1 output 10 VS VBLK is vertical sync or vertical blank output corresponding to bit 1 VS VBLK in the sync control register at subaddress 32h see Section 2 11 26 11 VS VBLK is logic input default HS CS 1 0 HS terminal function select 00 HS CS is logi
26. housed in a high performance thermally enhanced 80 terminal PowerPAD package TI package designator 80PFP Use of the PowerPAD package does not require any special considerations except to note that the thermal pad which is an exposed die pad on the bottom of the device is a metallic thermal and electrical conductor Therefore if not implementing the PowerPAD PCB features the use of solder masks or other assembly techniques can be required to prevent any inadvertent shorting by the exposed thermal pad of connection etches or vias under the package The recommended option however is not to run any etches or signal vias under the device but to have only a grounded thermal land as in the following explanation Although the actual size of the exposed die pad may vary the minimum size required for the keep out area for the 80 terminal PFP PowerPAD package is 8 mm x 8 mm It is recommended that there be a thermal land which is an area of solder tinned copper underneath the PowerPAD package The thermal land varies in size depending on the PowerPAD package being used the PCB construction and the amount of heat that needs to be removed In addition the thermal land may or may not contain numerous thermal vias depending on PCB construction Other requirements for using thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report SLMA002 available via the TI Web pages beginn
27. 0 0 5 0011 1111 1111 to 0000 0000 0000 Reserved 52 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 47 AFE Fine Gain for CVBS Luma Register Subaddress 50h 51h 900h Subaddress OT son FGAIN 4 7 0 FGAIN 4 11 8 FGAIN 4 11 0 This fine gain applies to CVBS or S video luma see AFE fine gain for Pb register Section 2 11 44 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 1111 1111 2 1 9995 1100 0000 0000 1 5 1001 0000 0000 1 125 default 1000 0000 0000 1 0100 0000 0000 0 5 0011 1111 1111 to 0000 0000 0000 Reserved 2 11 48 Field ID Control Register Subaddress 57h x Jp uw s gqpnow Jg s ee 656 version FID contro 656 Version 0 ITU R BT 656 4 default 1 ITU R BT 656 3 FID control 0 0 1 adapts to field 1 1 0 adapts to field 1 field 2 default 1 0 1 adapts to field 2 1 0 adapts to field 1 field 2 for TVP5147M1 EVM SLES140A March 2007 X TEXAS TVP5147M1PFP 53 INSTRUMENTS Functional Description 2 11 49 F bit and V bit Control 1 Register Subaddress 69h 7 J e J 5 a 3 2 13 0 VPLL Adaptive F bit mode 1 0 VPLL VPLL time constant control 0 VPLL adapts the time constant to the input signal default 1 VPLL time constants are fixed Adaptive 0 Enable F bit and V bit adaptation to detected lines per frame default 1 Disable
28. 1 Bit 0 1 Transaction video line number 9 8 Bit 2 Match 2 flag Bit 3 Match 1 flag Bit 4 1 if an error was detected in the EDC block 0 if no error was detected CS Sum of DO D7 of first data through last data byte Fill byte Fill bytes make a multiple of 4 bytes from byte O to last fill byte For teletext modes byte 8 is the sync pattern byte Byte 9 is the first data byte wa SLES140A March 2007 TEKAS INSTRUMENTS TVP5147M1PFP 25 Functional Description 2 7 2 VBI Raw Data Output The TVP5147M1 decoder can output raw A D video data at twice the sampling rate for external VBI slicing This is transmitted as an ancillary data block although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2 7 1 The samples are transmitted during the active portion of the line VBI raw data uses ITU R BT 656 format having only luma data The chroma samples are replaced by luma samples The TVP5147M1 decoder inserts a four byte preamble 000h 3FFh 3FFh 180h before data start There are no checksum bytes and fill bytes in this mode Table 2 8 VBI Raw Data Output Format BYTE D9 DO DESCRIPTION NO MSB VBI raw data preamble 2x pixel rate luma data i e NTSC 601 n 1707 n 4 Data 2 8 Reset and Initialization Reset is initiated at power up or any time terminal 34 RESETB is brought low Table 2 9 describes the status of the TVP5147M1 terminals durin
29. 1 27 Output Formatter 1 Register Subaddress 33h 40h ese ll e 4 3 dq YCbCr code range CbCr code Output format 2 0 YCbCr output code range 0 ITU R BT 601 coding range Y ranges from 64 to 940 Cb and Cr range from 64 to 960 1 Extended coding range Y Cb and Cr range from 4 to 1016 default CbCr code format 0 Offset binary code 2s complement 512 default 1 Straight binary code 2s complement Output format 2 0 000 10 bit 4 2 2 pixel x 2 rate with embedded syncs ITU R BT 656 default 001 20 bit 4 2 2 pixel rate with separate syncs 010 Reserved 011 10 bit 4 2 2 with separate syncs 100 111 Reserved NOTE 10 bit mode is also used for the raw VBI output mode when bit 4 VBI raw in the luminance processing control 1 register at subaddress 06h is set see Section 2 11 7 2 11 28 Output Formatter 2 Register Subaddress 34h Data enable Black Screen 1 0 CLK polarity Clock enable Data enable Y 9 0 AND C 9 0 output enable 0 Y 9 0 and C 9 0 high impedance default 1 Y 9 0 and C 9 0 active Black Screen 1 0 00 Normal operation default 01 Black screen out when TVP5147M1 detects lost lock using with tuner input but not with VCR 10 Black screen out 11 Black screen out CLK polarity 0 Data clocked out on the falling edge of DATACLK default 1 Data clocked out on the rising edge of DATACLK Clock enable 0 DATACLK outputs are high impedance
30. 1 Absolute Maximum Ratingst Supply voltage range lOVpp to V O GND 0 5 Vto4 V DVpptoDGND 22 12 54 ied ee Idee wed s abd 0 2Vto2V A33VDD see Note 1 to A33GND see Note 2 0 3V to 3 6 V A18VDD see Note 3 to A18GND see Note 4 0 2Vto2V Digital input voltage Vj to DGND WI 0 5 V to 4 5 V Digital output voltage Ve to DGND ssssssee III 0 5 V to 4 5 V Analog input voltage range AIN to AGND 0 2 V to 2 V Operating free air temperature TA wanananannanunaananan 0 C to 70 C Storage temperature Tai o iade AA AA CIR Rd 65 C to 150 C T Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 CH1_A33VDD CH2_A33VDD 2 CH1_A33GND CH2_A33GND 3 CH1_A18VDD CH2_A18VDD A18VDD_REF PLL_A18VDD 4 CH1_A18GND CH2_A18GND A18GND 3 2 Recommended Operating Conditions AA AI ONT NOTES 1 Exception 0 7 AVDD18 for XTAL1 terminal 2 Exception 0 3 AVDD18 for XTAL1 terminal 3 2 1 Crystal Specifications CRYSTAL SPECIFICATIONS MN NOM
31. 1C 3 vio 58 d 750 3 0 1 uF 3 e 4 CH1_A33GND 57 C8 5 CH1_A33VDD EG C9 0 1 uF 2 e CH2_A33VDD 5 TIJ ou dd 7 CH2_A33GND E VI 2A 0 8 VI 53 gt YO 10 1 uF VI 2B O T 9 V 52 EA aan VL 2C O io V 2 5 L gt vey 75 Q 3 Nj cnim TVP5147M1 50 L YA t z CH2 A18VDD 49 b d Pj 3 A18VDD REF Ag TI 0 1 uF 3 2 186ND REF i NC gt Y5 0 1uF VVV 15 ac 46 Sy VI_3A O e x VI 3A m gt YIN VI 3B 1 1a VL3 B 43 gt Y8 VI 3C 19 VLS C 4d gt YI 750 8 0 1 uF 3 NC 41 3 20 uc l 0 1 uF 0 1 uF V S X V S po a Lu Goad lt ZENnLOSEGE 25 2 822922005095 T O CO s 10 CO O0 OD O QN CO SF LO CO OC OO O OA QI OL LOL OL Q1 09 100 CO CO OD CO OD CO CO CO F La e e 0 1 uF 4 VI 4A O 750 y L HE Ale 2 2 KQ 2 END Z 04 uF M V V V 0 1 uF L gt DATACLK IOVDD gt XTAL1 0 1 uF GLCO I2CA lt 1 XTAL2 AVID 10K I2C Addre ection FSS 1431818 MHz SLCO 2CA rer pene RESETB ee LA 1 2 Base Addr 0xBA PWDN 3 2 3 Base Addr 0xB8 gt INTREQ CL1 CL2 10kQ 4 SDA V V SCL NOTE If XTAL1 is connected to clock source input voltage high must be 1 8 V TVP5147 can be a drop in replacement for TVP5146 Terminals 69 and 71 must be connected to ground through pulldown resistors Figure 5 1 Example Application Circuit Jd SLES140A March 2007 TEXAS TVP5147M1PFP 87 INSTRUMENTS Application Information 5 2 Designing With PowerPAD Devices The TVP5147 device is
32. 2007 vi TEXAS INSTRUMENTS TVP5147M1PFP 17 Functional Description 625 Line s YAA s AA s AAA RARA FID EE EE m E MR VBLK LO R rE IE lt gt lt M VBLK Start VBLK Stop 310 311 312 313 314 315 316 317 318 319 320 336 337 338 es ft sVUVU i rn uuuuuu FID BE EN __ VBLK _ far _s VBLK Start VBLK Stop NOTE Line numbering conforms to ITU R BT 470 Figure 2 13 Vertical Synchronization Signals for 625 Line System 18 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description DATACLK L 4 L Eu Nj ya Wa x HS Start HS Stop Eo AA c es ld D gt AVID lt M _ lt M AVID Stop AVID Start DATACLK 2x Pixel Clock ede Ja Te Te To NOTE ITU R BT 656 10 bit 4 2 2 timing with 2x pixel clock reference Figure 2 14 Horizontal Synchronization Signals for 10 Bit 4 2 2 Mode SLES140A March 2007 wi TEKAS TVP5147M1PFP 19 INSTRUMENTS Functional Description 0 WA 4 4 I ds eee Lidia od LL forefoot or 1 MET c r gt HS Start HS Stop ERN CC lt q A gt a C gt B 2 gt kq D gt AVID lt M AVID Stop AVID Start NOTE AVID rising edge occurs 4 clock cycles early DATACLK 1x Pixel Clock CE
33. 35 TEXA INSTRUMENTS TVP5147M1PFP NTSC PAL SECAM 2x10 Bit Digital Video Decoder With Macrovision Detection YPbPr Inputs and 5 Line Comb Filter Data Manual March 2007 Digital Audio Video SLES140A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any li
34. 4h The TVP5147M1 gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress 78h and the AGC increment delay register located at subaddress 79h 2 1 4 Analog Video Output One of the analog input signals is available at the analog video output terminal which is shared with input selected by 12C registers The signal at this terminal must be buffered by a source follower The nominal output voltage is 2 V p p thus the signal can be used to drive a 75 O line The magnitude is maintained with an AGC in 16 steps controlled by the TVP5147M1 decoder In order to use this function terminal VI 1 A must be set as an output terminal The input mode selection register also selects an active analog output signal 2 1 5 A D Converters All ADCs have a resolution of 10 bits and can operate up to 30 MSPS All A D channels receive an identical clock from the on chip phase locked loop PLL at a frequency between 24 MHz and 30 MHz All ADC reference voltages are generated internally TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 2 Digital Video Processing Figure 2 2 is a block diagram of the TVP5147M1 digital video decoder processing This block receives digitized video signals from the ADCs and performs composite processing for CVBS and S video inputs and YCbCr signal enhancements for CVBS and S video inputs It also generates horizontal and vertical syncs
35. 50 AFE Coarse Gain for CH 2 Register 50 AFE Coarse Gain for CH 3 Register 51 AFE Coarse Gain for CH 4 Register 51 AFE Fine Gain for Pb Register 52 AFE Fine Gain for Y Chroma Register 52 AFE Fine Gain for Pr Register 52 AFE Fine Gain for CVBS Luma Register 53 Field ID Control Register II WA 53 F bit and V bit Control 1 Register 54 Back End AGC Control Register 55 AGC Decrement Speed Control Register 55 ROM Version Register 55 AGC White Peak Processing Register 56 F and V Bit Control Register aaa 57 VCR Trick Mode Control Register 58 Horizontal Shake Increment Register 58 AGC Increment Speed Register 58 AGC Increment Delay Register 58 35 TEXAS July 2005 INSTRUMENTS Contents Section Page 2 11 59 Analog Output Control 1 Register 59 2 11 60 Chip
36. 5147M1PFP Gemstar is a trademark of Gemstar TV Guide Intermational PowerPAD is a trademark of Texas Instruments i SLES140A March 2007 435 TEXAS TVP5147M1PFP 3 INSTRUMENTS Introduction 1 5 Functional Block Diagram Copy VBI Protection CVBSIY Data Detector Processor Analog Front End CVBS Composite and S Video Processor CPb 4 4 ve 1 Y Luma Separation Processing Output 5 line EN C CbCr Chroma E CVBS Clamping Adaptive Processing y e AGC Comb 2 x 11 Bit ADC CVBS C Pr CVBS Y Sampling Clock Timing Processor Host With Sync Detector Lv lvvvvvv Low NZMXNDOXNO a JJ Sh 232 293 o 5 N lt gt o x x aui lt I AC 2 Figure 1 1 Functional Block Diagram i 4 TVP5147M1PFP ki TEXAS INSTRUMENTS SLES140A March 2007 Introduction 1 6 Terminal Assignments PFP PACKAGE TOP VIEW O Qon 2928 69 2223 8092 pese X a w a cmotpoonaaoococoS88 ve so SS zonat TEXTE EDO UI AANS gt O000L0xXxxXx gt TITLOOODOOOOOXX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 vL1B 1 9 C_6 GPIO VI 1 C l2 C 7 GPIO CH1_A33GND 3 C 8 GPIO CH1_A33VDD lla C 9 GPIO CH2_A33VDD 5 DGND CH2_A33GND f6 DVDD vi2 A 7 Y 0 VI 2 B ls Y vl2 C Y 2 CH2_A18GND Y 3 CH2_A18VDD Y_4 A18VDD_REF IOGND A18GND_REF IOVDD NC Y 5 NC Y 6 VI 3 A Y 7 VI 3 B Y 8 VI 3C Y 9 NC DGND NC DVDD 21 22 23 24 25 2
37. 6 27 28 29 30 31 32 33 34 35 36 37 38 39 oOo onoonoa ocooazmooxnaoo x zz zaoazzoauazac ggonazzd jO c m lon sos mms c TI E so Figure 1 2 Terminal Assignments Diagram wi SLES140A March 2007 TEXAS TVP5147M1PFP 5 INSTRUMENTS Introduction 1 7 Terminal Functions Table 1 1 Terminal Functions TERMINAL 1 0 DESCRIPTION NAME NUMBER Analog Video VI_1_A Analog video input for CVBS Pb C or analog video output see Section 2 11 59 T VI 1 x Analog video input for CVBS Pb C I VI 2 x Analog video input for CVBS Y I VI 3 x Analog video input for CVBS Pr C I I I I I I VI 4 A Analog video input for CVBS Y Up to 10 composite 4 S video and 2 composite or 3 component video inputs or a combination thereof can be supported The inputs must be ac coupled The recommended coupling capacitor is 0 1 uF The possible input configurations are listed in the input select register at IC subaddress 00h see Lm d Section 2 11 1 Clock Signals DATACLK Line locked data output clock External clock reference input It can be connected to an external oscillator with a 1 8 V compatible clock XTAL1 RI signal or a 14 31818 MHz crystal oscillator External clock reference output Not connected if XTAL1 is driven by an external single ended oscillator Digital Video C 9 01 Digital video output of CbCr C 9 is MSB and C 0 is LSB Also these terminals can be programmable GPIO 9 0 general purpose 1 0 j For the 8 bi
38. 7M1PFPRG4 ACTIVE HTQFP PFP 80 1000 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhe
39. 80h L qp s 5 a 3 2 0o Saturation 7 0 Saturation 7 0 This register works for CVBS S video and component video luminance 1111 1111 255 maximum 1000 0000 128 default 0000 0000 0 no color 2 11 13 Chroma Hue Register Subaddress OCh 7 j e j s a 3 2 13 0 Hue 7 0 Hue 7 0 does not apply to component video 0111 1111 180 degrees 0000 0000 0 degrees default 1000 0000 180 degrees 2 11 14 Chrominance Processing Control 1 Register Subaddress ODh oe sopas po 3 y 2 3 o Chrominance adaptive Color PLL reset 0 Color subcarrier PLL not reset default 1 Color subcarrier PLL reset Chrominance adaptive comb enable This bit is effective on composite video only 0 Enabled default 1 Disabled Automatic color gain control ACGC 1 0 00 ACGC enabled default 01 Reserved 10 ACGC disabled ACGC set to the nominal value 11 ACGC frozen to the previous set value 435 36 TVP5147M1PFP TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 15 Chrominance Processing Control 2 Register Subaddress OEh E Y ee a E wor PAL compensation Chrominance filter select 1 0 PAL compensation 0 Disabled 1 Enabled default Wideband chroma LPF filter WCF 0 Disabled 1 Enabled default Chrominance filter select 1 0 00 Disabled 01 Notch 1 10 Notch 2 default 11 Notch 3 See
40. CAM Bits 0 3 represent group 1 aspect ratio Bits 4 7 represent group 2 enhanced services Bits 8 10 represent group 3 subtitles Bits 11 13 represent group 4 others SLES140A March 2007 X TEXAS TVP5147M1PFP 73 INSTRUMENTS Functional Description 2 123 VDP VITC Data Register Read only PSubadavess 7 J s s 3 0 These registers contain the VITC data 2 12 4 VDP V Chip TV Rating Block 1 Register Read only oT 6 J 8 4 3 j 2 1 0 TV parental guidelines rating block 1 14 D When incoming video program is TV 14 D rated then this bit is set high PG D When incoming video program is TV PG D rated then this bit is set high MA L When incoming video program is TV MA L rated then this bit is set high 14 L When incoming video program is TV 14 L rated then this bit is set high PG L When incoming video program is TV PG L rated then this bit is set high 2 12 5 VDP V Chip TV Rating Block 2 Register Read only E pc MAS Y7 FV TV parental guidelines rating block 2 MA S When incoming video program is TV MA S rated then this bit is set high 14 S When incoming video program is TV 14 S rated then this bit is set high PG S When incoming video program is TV PG S rated then this bit is set high MA V When incoming video program is TV MA V rated then this bit is set high 14 V When incoming video program is TV 14 V rated then this bit is set high PG V When incoming video program is TV PG S rated
41. Figure 2 6 and Figure 2 7 for characteristics 2 11 16 AVID Start Pixel Register Subaddress 16h 17h 055h Subaddress OTO ieh AVID start 7 0 wm Reseved AV ID active AVID start 9 8 AVID active 0 AVID out active in VBLK default 1 AVID out inactive in VBLK AVID start 9 0 AVID start pixel number this is an absolute pixel location from HSYNC start pixel 0 NTSC 601 NTSC Sap PAL 601 PAL Sap default 85 55h 86 56h 88 58h 103 67h The TVP5147M1 decoder updates the AVID start only when the AVID start MSB byte is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this device resets The AVID start pixel register also controls the position of the SAV code SLES140A March 2007 X TEXAS TVP5147M1PFP 37 INSTRUMENTS Functional Description 2 11 17 AVID Stop Pixel Register Subaddress 18h 19h 325h Subaddress 18h AVID stop 7 0 19h AVID stop 9 8 AVID stop 9 0 AVID stop pixel number The number of pixels of active video must be an even number This is an absolute pixel location from HSYNC start pixel 0 NTSC 601 NTSC Sqp PAL 601 PAL Sqp default 805 325h 726 2D6h 808 328h 696 2B8h The TVP5147M1 decoder updates the AVID stop only when the AVID stop MSB byte is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this device resets The AVID start pixel re
42. ID MSB Register 59 2 11 01 Chip ID LSB Register oococcoccccccccnnccnc n 59 2 11 62 CPLL Speed Control Register 59 2 11 63 Status Request Register AWA es 60 2 11 64 Vertical Line Count Register 60 2 11 65 AGC Decrement Delay Register 60 2 11 66 VDP TTX Filter And Mask Registers 61 2 11 67 VDP TTX Filter Control Register 62 2 11 68 VDP FIFO Word Count Register 63 2 11 69 VDP FIFO Interrupt Threshold Register 64 2 11 70 VDP FIFO Reset Register aa 64 2 11 71 VDP FIFO Output Control Register 64 2 11 72 VDP Line Number Interrupt Register aaa 64 2 11 73 VDP Pixel Alignment Register 65 2 11 74 VDP Line Start Register 65 2 11 5 VDP Line Stop Register AA ai mi dd e tes Seed rra 65 2 11 76 VDP Global Line Mode Register 65 2 11 77 VDP Full Field Enable Register aa 66 2 11 78 VDP Full Field Mode Register 66 2 11 79 VBUS Data Access With No VBUS Addr
43. MAXJ UNIT SLES140A March 2007 X TEXAS TVP5147M1PFP 79 INSTRUMENTS Electrical Specifications 3 3 Electrical Characteristics For minimum maximum values OVpp 3 V to 3 6 V DVpp 1 65 V to 1 95 V AVppasa 3 V to 3 6 V AVDD18 1 65 V to 1 95 V Ta 0 C to 70 C For typical values IOVpp 3 3 V DVpp 1 8 V AVpp33 3 3 V AVppig 1 8 V Ta 25 C 3 3 1 DC Electrical Characteristics see Note 1 PARAMETER TEST CONDITIONS MIN TYP X UNIT 4 MAX UNIT 7 CVBS IDDIO D 3 3 V IO digital supply current MA TO CVBS 55 A E CVBS r CVBS i 0 m F PsAvE Total poverdissipation power save TJ DOWN Total power dissipation power down TJ Pika rputleakage cures i NOTE 1 Measured with a load of 10 kQ in parallel to 15 pF 3 3 2 Analog Processing and A D Converters 3 3 2 1 Fg 2 30 MSPS for CH1 CH2 DG Ganeemiame TT Z NOTE 1 Component inputs only 80 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Electrical Specifications 3 3 3 Timing 3 3 3 1 Clocks Video Data Sync Timing PARAMETER TS NOTE D S MIN TYP MAX UNIT Duty cycle DATACLK Ps 455 50 55 fig Lowe DATACLK C s 9 uu Grey sine 1 lw NOTE 1 CL 15pF lt t2 gt le ty gt VOH DATACLK VOL lt lt t3 t4 VOH Y C AVID VS HS FID Valid Data Valid Data VOL it t5 gt Figure 3 1 Clocks Video Data and Sync Timing 3 3 3 2 12C Ho
44. SEE EE NOTE 20 bit 4 2 2 timing with 1x pixel clock reference Figure 2 15 Horizontal Synchronization Signals for 20 Bit 4 2 2 Mode 20 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description First Field W B h B vs HS Second Field 4 H 2 4 B 2 4 H 2 B 2 o E 10 Bit PCLK 2x Pixel Clock 20 Bit PCLK 1x Pixel Clock Figure 2 16 VSYNC Position With Respect to HSYNC 2 5 2 Embedded Syncs Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID These codes contain the V and F bits which also define vertical timing Table 2 3 gives the format of the SAV and EAV codes H equals 1 always indicates EAV H equals 0 always indicates SAV The alignment of V and F to the line and field counter varies depending on the standard The P bits are protection bits P3 V xor H P2 F xor H P1 F xor V PO F xor V xor H Table 2 3 EAV and SAV Sequence jpe Mse ps dr pe ps pa ps o2 b po Preamble 0 o o o o o o jo o o Preamble o o o o o o o o 0o o Stausword E v du rs P m P o o 2 6 12C Host Interface Communication with the TVP5147M1 decoder is via an 12C host interface The 12C standard consists of two signals the serial input output data SDA line and the serial input clock line SCL which carry information between the de
45. ad only W Write only R W Read and write Reserved register addresses must not be written to SLES140A March 2007 i TEXAS TVP5147M1PFP 29 INSTRUMENTS Functional Description 30 Table 2 10 12C Register Summary Continued VBUS data access with VBUS address increment FIFO read data NOTE R Read only W Write only R W Read and write Reserved register addresses must not be written to E2h Table 2 11 VBUS Register Summary VDP general line mode and line address VDP VPS PDC Gemstar data 12C SUBADDRESS 00 0000h 80 051Bh 80 051Ch 80 051Fh 80 0520h 80 0526h 80 0527h 80 052Bh 80 052Ch 80 0534h 80 0535h 80 053Fh 80 0540h 80 0543h 80 0544h 80 O5FFh 80 0600h 80 0611h 80 0612h 80 06FFh 80 0700h 80 070Ch 80 070Dh 90 1903h 90 1904h 90 1905h A0 005Dh AO O5Eh AO 005Fh BO 005Fh BO 0060h BO 0061h FF FFFFh DEFAULT NOTE Writing any value to a reserved register may cause erroneous operation of the TVP5147M1 decoder It is recommended not to access any data to from reserved registers TVP5147M1PFP vi TEXAS INSTRUMENTS SLES140A March 2007 Functional Description 2 11 Register Definitions 2 11 1 Input Select Register A PE A 4 3 O TAS Input select 7 0 Table 2 12 Analog Channel and Video Mode Selection INPUT SELECT 7 0 OUTPUT bi a e Js 4 3 2 11 0 Hex see Note 1 wes it ofefefojofofoli a wis wine Japo te te to lo roje vic wea Jofofofofop
46. agram of the TVP5147M1 digital composite video processing circuit This processing circuit receives a digitized composite or S video signal from the ADCs and performs Y C separation bypassed for S video input chroma demodulation for PAL NTSC and SECAM and YUV signal enhancements The 10 bit composite video is multiplied by the subcarrier signals in the quadrature demodulator to generate color difference signals U and V The U and V signals are then sent to low pass filters to achieve the desired bandwidth An adaptive 5 line comb filter separates UV from Y based on the unique property of color phase shifts from line to line The chroma is remodulated through a quadrature modulator and subtracted from line delayed composite video to generate luma This form of Y C separation is completely complementary thus there is no loss of information However in some applications it is desirable to limit the U V bandwidth to avoid crosstalk In that case notch filters can be turned on To accommodate some viewing preferences a peaking filter is also available in the luma path Contrast brightness sharpness hue and saturation controls are programmable through the host port SLES140A March 2007 vi TEXAS TVP5147M1PFP 11 INSTRUMENTS Functional Description Y Line Delay NTSC PAL SECAM Luma Remodulation Contrast Brightness Saturation Adjust SECAM CVBS Color Demodulation Color LPF l2 Burst Accumulator
47. ance signal Figure 2 9 shows the characteristics of the peaking filter at four different Gain gain settings that are user programmable via the 12C interface Peak Bandpass Peaking Detector Filter Filter Figure 2 8 Luminance Edge Enhancer Peaking Block Diagram OUT Peak at f 2 64 MHz Gain 2 Amplitude dB 0 1 2 3 4 5 6 7 f Frequency MHz Figure 2 9 Peaking Filter Response NTSC PAL ITU R BT 601 Sampling 2 2 4 Color Transient Improvement Color transient improvement CTI enhances horizontal color transients The color difference signal transition points are maintained but the edges are enhanced for signals which have bandwidth limited color components 14 TVP5147M1PFP 35 TEXA S SLES140A March 2007 INSTRUMENTS 2 3 24 RTC NOTE 2 5 Functional Description Clock Circuits An internal line locked PLL generates the system and pixel clocks A 14 318 MHz clock is required to drive the PLL This can be input to the TVP5147M1 decoder at the 1 8 V level on terminal 74 XTAL1 or a crystal of 14 318 MHz fundamental resonant frequency can be connected across terminals 74 and 75 XTAL2 If a parallel resonant circuit is used as shown in Figure 2 10 then the external capacitors must have the following relationship Ci 1 Ci 2 201 CSTRAY where Cstpay is the terminal capacitance with respect to ground Figure 2 10 shows the reference clock config
48. c O output 01 HS CS is logic 1 output 10 HS CS is horizontal sync or composite sync output corresponding to bit O HS CS in the sync control register at subaddress 32h see Section 2 11 26 11 HS CS is logic input default C_1 1 0 C 1 terminal function select 00 C 1 is logic O output 01 2C 1 is logic 1 output 10 Reserved 11 C 1 is logic input default C O 1 0 C 0 terminal function select 00 C Oiis logic O output 01 2 C Ois logic 1 output 10 Reserved 11 C Ois logic input default C_x functions are only available in the 10 bit output mode SLES140A March 2007 x TEXAS TVP5147M1PFP 43 INSTRUMENTS Functional Description 2 11 31 Output Formatter 5 Register C_5 1 0 C_5 terminal function select 00 C_5is logic 0 output 01 C_5is logic 1 output 10 Reserved 11 C_5is logic input default C_4 1 0 C_4 terminal function select 00 C_4 is logic 0 output 01 C_4 is logic 1 output 10 Reserved 11 C_4 is logic input default C_3 1 0 C_3 terminal function select 00 C Sis logic 0 output 01 C Sis logic 1 output 10 Reserved 11 C_3 is logic input default C_2 1 0 C_2 terminal function select 00 C 2is logic 0 output 01 2 C 2is logic 1 output 10 Reserved 11 C_2 is logic input default C_x functions are only available in the 10 bit output mode 44 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Fun
49. cense either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com
50. controller initiates the program from one line standard to the next line standard for example the previous line of teletext to the next line of closed caption This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP but early enough to allow the new values to be programmed before the current settings are required The default value is Ox1E and has been tested with every standard supported here A new value is needed only if a custom standard is in use 2 11 74 VDP Line Start Register Subaddress D6h US CU A 5 4 2 1 o VDP line start 7 0 VDP line start 7 0 Set the VDP line starting address This register must be set properly before enabling the line mode registers The VDP processor works only the VBI region set by this register and the VDP line stop register 2 11 75 VDP Line Stop Register Subaddress D7h Default L 7 te 5 w e 2 o VDP line stop 7 0 VDP line stop 7 0 Set the VDP stop line address 2 11 76 VDP Global Line Mode Register Subaddress D8h Default FFh 7 6 5 4 3 2 1 0 Global line mode 7 0 Global line mode 7 0 VDP processing for multiple lines set by the VDP start line register at subaddress D6h and the VDP stop line register at subaddress D7h Global line mode register has the same bit definition as the general line mode registers General line mode has priority over the global line mode SLES140A
51. ction circuit Type 1 2 3 and separate color stripe detection e 3 3 V tolerant digital I O ports Macrovision is a trademark of Macrovision Corporation Other trademarks are the property of their respective owners SLES140A March 2007 X TEXAS TVP5147M1PFP 1 INSTRUMENTS Introduction 11 2 Detailed Functionality Two 30 MSPS 10 bit A D channels with programmable gain control Supports NTSC J M 4 43 PAL B D G H M N Nc 60 and SECAM B D G K K1 L CVBS and S video Supports analog component YPbPr video format with embedded sync 10 analog video input terminals for multisource connection Supports analog video output User programmable video output formats 10 bit ITU R BT 656 4 2 2 YCbCr with embedded syncs 10 bit 4 2 2 YCbCr with separate syncs 20 bit 4 2 2 YCbCr with separate syncs 2x sampled raw VBI data in active video during a vertical blanking period Sliced VBI data during a vertical blanking period or active video period full field mode HSYNC VSYNC outputs with programmable position polarity width and field ID FID output Composite and S video processing Adaptive 2 D 5 line adaptive comb filter for composite video inputs chroma trap available Automatic video standard detection NTSC PAL SECAM and switching Luma peaking with programmable gain Patented chroma transient improvement CTI Patented architecture for locking to weak noisy or unstable signals Single 14 31818 MHz r
52. ctional Description 2 11 32 Output Formatter 6 Register C_9 1 0 C_9 terminal function select 00 C 9 is logic O output 01 2 C 9 is logic 1 output 10 Reserved 11 C_9 is logic input default C_8 1 0 C 8 terminal function select 00 C_8 is logic O output 01 C_8is logic 1 output 10 Reserved 11 C_8 is logic input default C_7 1 0 C_7 terminal function select 00 C_7 is logic 0 output 01 C_7 is logic 1 output 10 Reserved 11 C_7 is logic input default C_6 1 0 C_6 terminal function select 00 C_6 is logic 0 output 01 C_6is logic 1 output 10 Reserved 11 C_6 is logic input default C_x functions are only available in the 10 bit output mode 2 11 33 Clear Lost Lock Detect Register Subaddress 39h ope J 5 a s 2 t x _ 7 Reserved Clear lost lock detect Clear bit 4 lost lock detect in the status 1 register at subaddress 3Ah see Section 2 11 34 0 No effect default 1 Clears bit 4 in the status 1 register SLES140A March 2007 X TEXAS TVP5147M1PFP 45 INSTRUMENTS Functional Description 2 11 34 Status 1 Register Read only Er gt ES a s e t o Peak white Line alternating Field rate Lost lock Color subcarrier Vertical sync Horizontal sync TV VCR detect status status status detect lock status lock status lock status status Peak white detect status 0 Peak white is not detected 1 Peak white is detected
53. e a N ai OT C_x input status 0 Input is a low 1 Input is a high These status bits are only valid when terminals are used as input and its states updated at every line 48 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 39 GPIO Input 2 Register Read only 7 eo J s j a 3 2 1 o GPIO input terminal status 0 Input is a low 1 Input is a high AVID input terminal status 0 Input is a low 1 Input is a high GLCO input terminal status 0 Input is a low 1 Input is a high VS input terminal status 0 Input is a low 1 Input is a high HS input status 0 Input is a low 1 Input is a high FID input status 0 Input is a low 1 Input is a high C_x input status 0 Input is a low 1 Input is a high These status bits are only valid when terminals are used as input and its states updated at every line SLES140A March 2007 X TEXAS TVP5147M1PFP 49 INSTRUMENTS Functional Description 2 11 40 AFE Coarse Gain for CH 1 Register Subaddress 46h 20h LoT 89 j 8 j 2 j 3 23 J 1 0 CGAIN 1 5 0 CGAIN 1 3 0 Coarse Gain 0 5 CGAIN 1 10 where 0 lt CGAIN 1 lt 15 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 2 1110 1 1101 1 1100 1 1011 1 1010 1 1001 1000 0111 1 0110 1 0101 1 0100 0 9 0011 0 8 0010 0 7 defaul
54. ed 12C writes For the given assumptions only one write is required All other registers are set up by default 12C register address 08h Luminance processing control 3 register I2C data 00h Optimizes the trap filter selection for NTSC and PAL 12C register address OEh Chrominance processing control 2 register I2C data 04h Optimizes the chrominance filter selection for NTSC and PAL 12C register address 34h Output formatter 2 register I2C data 11h Enables YCbCr output and the clock output NOTE HS CS VS VBLK AVID FID and GLCO are logic inputs by default See output formatter 3 and 4 registers at addresses 35h and 36h respectively 4 2 Example 2 4 2 1 Assumptions Input connector S video VI 2 C luma VI 1 C chroma Video format NTSC J M 443 PAL B D G H N Nc 60 or SECAM default Output format 10 bit ITU R BT 656 with discrete sync outputs 4 2 2 Recommended Settings Recommended 12C writes This setup requires additional writes to output the discrete sync 10 bit 4 2 2 data HS and VS and to autoswitch between all video formats mentioned above SLES140A March 2007 X TEXAS TVP5147M1PFP 83 INSTRUMENTS Example Register Settings 12C register address 00h Input select register 12C data 46h Sets luma to VI 2 C and chroma to VI 1 C 12C register address 04h Autoswitch mask register I2C data 3Fh Includes NTSC 443 and PAL M Nc 60 in the autoswitch 12C register address 08h Luminance p
55. ed in the luma path then chroma trap filters are used which are shown in Figure 2 6 and Figure 2 7 The TI patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries It detects and properly handles false colors in high frequency luminance images such as a multiburst pattern or circle pattern 10 5 Notch 3 Filter 0 5 a a x T 10 co co 3 3 45 Notch 1 Filter TM Notch 2 Filter 25 No Noten pi 30 No Notch Filter 35 40 0 1 2 3 4 5 6 7 f Frequency MHz f Frequency MHz Figure 2 6 Chroma Trap Filter Frequency Figure 2 7 Chroma Trap Filter Frequency Response NTSC ITU R BT 601 Sampling Response PAL ITU R BT 601 Sampling RT SLES140A March 2007 EXAS INSTRUMENTS TVP5147M1PFP 13 Functional Description 2 2 3 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter either of which removes chrominance information from the composite signal to generate a luminance signal The luminance signal is then fed into the input of a peaking circuit Figure 2 8 illustrates the basic functions of the luminance data path In the case of S video the luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit A peaking filter edge enhancer amplifies high frequency components of the lumin
56. eference crystal for all standards Line locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs Genlock output RTC format for downstream video encoder synchronization Certified Macrovision copy protection detection i TVP5147M1PFP 35 TEXAS SLES140A March 2007 INSTRUMENTS Introduction VBI data processor Teletext NABTS WST CC and extended data service EDS Wide screen signaling WSS Copy generation management system CGMS Video program system VPS PDC Vertical interval time code VITC Gemstar 1x 2x mode V Chip decoding Register readback of CC WSS CGMS VPS PDC VITC and Gemstar 1x 2x sliced data 12C host port interface Reduced power consumption 1 8 V digital core 3 3 V for digital 1 0 and 1 8 V 3 3 V analog core with power save and power down modes 80 terminal TQFP PowerPAD package 1 2 TVP5147M1 Applications DLP projectors Digital TV LCD TV monitors DVD recorders PVR PC video cards Video capture video editing Video conferencing 1 3 Related Products TVP5146M2 NTSC PAL SECAM 2x10 Bit Digital Video Decoder With Macrovision Detection YPbPr RGB Inputs and 5 Line Comb Filter SLES141 TVP5150AM1 Ultralow Power NTSC PAL SECAM Video Decoder With Robust Sync Detector SLES098 1 4 Ordering Information PACKAGEDDEVICES DEVICES TA 80 TERMINAL PLASTIC FLAT PACK PowerPAD PACKAGE 0 C to 70 C TVP
57. egister 75 2 12 8 VDP General Line Mode and Line Address Register 76 2 12 9 VDP VPS Gemstar Data Register 77 2 12 10 Analog Output Control 2 Register 78 2 12 11 Interrupt Configuration Register 78 3 Electrical Specifications 1 i na aa aaa aaa cece ees 79 3 1 Absolute Maximum RatingSt sssssssssssssssse sm 79 3 2 Recommended Operating Conditions 79 3 2 1 Crystal Specifications ii AA 79 July 2005 3 TEXAS SLES140 v INSTRUMENTS Contents Section 3 3 Electrical Characteristics aaa 3 3 1 DC Electrical Characteristics AI II eese 3 3 2 Analog Processing and A D Converters 3 3 3 TIMING v s a a dd dd ca ii 4 Example Register Settings oooooccoocnnncrronnn eee eee eens 4 1 cea a E 4 1 1 ASSUMPUONS nee lcd 4 1 2 Recommended Settings aaa 4 2 EKAM PIS 2 FP ri ed li a as iaa 4 2 1 ASSUImpLUOTIS IA t e ERA ade 4 2 2 Recommended Settings ii aaa 4 3 EXAMple 3 ai AA a o Dae eit ead A la dae adore 4 3 1 ASSUMPUIONS 20 HT 4 3 2 Recommended Settings ua aaa 5 Application Information Aa 5 1 Application Example aa ca dis ursi cane a onpa a d a A ae 5 2 Designing With PowerPAD Devices
58. egister Subaddress 77h Default ER ES dp AE ESA 2 ET o Horizontal shake increment 7 0 Horizontal shake increment 7 0 000 0000 0 000 1010 64h default 111 1111 2 FFh 2 11 57 AGC Increment Speed Register Subaddress 78h Default 06h EE 4 e _ e 2 e gt Reserved AGC increment speed 3 0 AGC increment speed Adjusts gain increment speed 111 7 slowest 110 6 default 000 0 fastest 2 11 58 AGC Increment Delay Register I Subaddress 79h Default 7 e j s a 3 2 13 0 AGC increment delay 7 0 AGC increment delay Number of frames to delay gain increments 1111 1111 2 255 0001 1110 30 default 0000 0000 0 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS al 00 Functional Description 2 11 59 Analog Output Control 1 Register Subaddress 7Fh Default 00h 7 j e s 4 3 2 31 Reserved AGC enable Input select Analog Output enable AGC enable 0 Enabled default 1 Disabled manual gain mode see Section 2 12 10 Input select 00 Input selected by TVP5147M1 decoder see Section 2 11 1 default 01 Input selected manually see Section 2 12 10 Analog output enable 02VI 1 Ais input default 1 VI 1 Ais analog video output 2 11 60 Chip ID MSB Register Subaddress Read only Lm E l 4 12 2a t Chip ID MSB 7 0 Chip ID MSB 7 0 This register identifies the MSB of the device ID Value 51h
59. equence bit S PAL 1 R Y line normal 0 R Y line inverted NTSC 1 no change Figure 2 11 RTC Timing Output Formatter The output formatter sets how the data is formatted for output on the TVP5147M1 output buses Table 2 1 shows the available output modes i SLES140A March 2007 435 TEXAS TVP5147M1PFP 15 INSTRUMENTS Functional Description Table 2 1 Output Format NUMBER YCbCr YCbCr PIXEL COLOR STANDARDS FREQUENCY SUBCARRIER ONE ENE UR FREQUENCY MHz 601 sampling Dr 4 406250 SECAM 720 625 13 5 Db 4 250000 15 625 2 5 1 Separate Syncs VS HS and VBLK are independently software programmable to a 1x pixel count This allows any possible alignment to the internal pixel count and line count The default settings for 525 line and 625 line video outputs are given as examples below FID changes at the same transient time when the trailing edge of vertical sync occurs The polarity of FID is programmable by an 12C interface 16 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS First Field Video HS VS cs FID VBLK VBLK Start 262 263 Second Field Video HS VS cs FID VBLK 525 Line 264 265 266 267 268 269 270 271 VBLK Start NOTE Line numbering conforms to ITU R BT 470 272 Functional Description VBLK Stop AU VBLK Stop Figure 2 12 Vertical Synchronization Signals for 525 Line System SLES140A March
60. er ai AAA IA eee teens 2 11 6 Color Killer Register 02 00 cece cet RII 2 11 7 Luminance Processing Control 1 Register 2 11 8 Luminance Processing Control 2 Register 2 11 9 Luminance Processing Control 3 Register 2 11 10 Luminance Brightness Register July 2005 3 TEXAS SLES140 INSTRUMENTS RU Y Q 5 aonnnhrWWWD C2 TT CD Q0 Q0 002 CO C2 CO CO CO IO IO IO IO IO IO IO IO lD IO lO 2 ua n onc O10101 kK KO 00 lO lO 1 4 OO C1 KDDD 0 C1O101 2 200000 Contents Section 2 11 2 11 2 11 2 11 2 11 2 11 2 11 2 11 2 11 11 12 13 14 15 16 17 18 19 2 11 20 2 11 21 2 11 22 2 11 23 2 11 24 2 11 25 2 11 26 2 11 27 2 11 28 2 11 29 2 11 30 2 11 31 2 11 32 2 11 33 2 11 34 2 11 35 2 11 36 2 11 37 2 11 38 2 11 39 2 11 40 2 11 41 2 11 42 2 11 43 2 11 44 2 11 45 2 11 46 2 11 47 2 11 48 2 11 49 2 11 50 2 11 51 2 11 52 2 11 53 2 11 54 2 11 55 2 11 56 2 11 57 2 11 58 iv SLES140 Page Luminance Contrast Register 36 Chrominance Saturation Register 36 Chroma Hue Register 66 00 cece ete teen tenes 36 Chrominance Processing Control 1 Register 36 Chrominance Processing Control 2 Register
61. ess Increment Register 66 2 11 80 VBUS Data Access With VBUS Address Increment Register 66 2 11 81 FIFO Read Data Register 67 2 11 82 VBUS Address Access Register 67 2 11 83 Interrupt Raw Status 0 Register 67 2 11 84 Interrupt Raw Status 1 Register 68 2 11 85 Interrupt Status 0 Register aa 68 2 11 86 Interrupt Status 1 Register 69 2 11 87 interrupt Mask 0 Register 0 0 c Aaa 70 2 11 88 Interrupt Mask 1 Register 71 2 11 89 Interrupt Clear 0 Register aa 71 2 11 90 Interrupt Clear 1 Register 72 2 12 VBUS Register Definitions 73 2 12 1 VDP Closed Caption Data Register 73 2 12 2 VDP WSS Data Register aaa 73 2 12 3 VDP VITC Data Register cece eee eee tenes 74 2 12 4 VDP V Chip TV Rating Block 1 Register 74 2 12 5 VDP V Chip TV Rating Block 2 Register 74 2 12 6 VDP V Chip TV Rating Block 3 Register 75 2 12 7 VDP V CHIP MPAA Rating Data R
62. g and immediately after reset Table 2 9 Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED Y 9 0 C 9 0 High impedance RESETB PWDN SDA SCL FSS AVID GLCO HS VS FID np DATACLK High impedance POWER 3 3 V and 1 8 V 1 ms min l 200 ns min Di Normal Operation RESETB Pin 34 Reset 4 1 ms min gt SDA gt 4 2 Pin 29 Invalid 1 C Cycle Valid Figure 2 18 Reset Timing The following register writes must be made before normal operation of the device STEP I2C SUBADDRESS I2C DATA 26 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 9 Adjusting External Syncs The proper sequence to program the following external syncs is e To set NTSC PAL M NTSC 443 PAL60 525 line modes Set the video standard to NTSC register 02h Set HSYNC VSYNC VBLK and AVID external syncs registers 16h through 24h e To set PAL PAL N SECAM 625 line modes Set the video standard to PAL register 02h Set HSYNC VSYNC VBLK and AVID external syncs registers 16h through 24h e For autoswitch set the video standard to autoswitch register 02h 2 10 Internal Control Registers The TVP5147M1 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device Communication between the external controller and the TVP5147M1 is through a standard 12C host port i
63. gister also controls the position of the EAV code 2 11 18 HSYNC Start Pixel Register Subaddress 1Ah 1Bh 000h Subaddress HSYNC start 7 0 HSYNC start 9 8 HSYNC start pixel 9 0 This is an absolute pixel location from HSYNC start pixel 0 The TVP5147M1 decoder updates the HSYNC start only when the HSYNC start MSB is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this device resets 2 11 19 HSYNC Stop Pixel Register Subaddress 1Ch 1Dh 040h Subaddress HSYNC stop 7 0 HSYNC stop 9 8 HSYNC stop 9 0 This is an absolute pixel location from HSYNC start pixel 0 The TVP5147M1 decoder updates the HSYNC stop only when the HSYNC stop MSB is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this device resets 2 11 20 VSYNC Start Line Register Subaddress 1Eh 1Fh Default 004h Subaddress 7 6 8 4a s 2 1 o VSYNC start 7 0 VSYNC start 9 8 VSYNC start 9 0 This is an absolute line number The TVP5147M1 decoder updates the VSYNC start only when the VSYNC start MSB is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this decoder resets NTSC default 004h PAL default 001h 38 TVP5147M1PFP kis TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 21 VSYNC Stop Line Reg
64. gister is a double byte register it is necessary to capture the setting into the register to ensure that the value is not updated between reading the lower and upper bytes In order to cause this register to capture the current settings bit O of the status request register subaddress 97h must be set to a 1b Once the internal processor has updated and can be read Either byte may be read first since no further update will occur until bit O of 97h is set to 1b again 2 11 65 AGC Decrement Delay Register Subaddress 9Eh sm AE LAA ER EE ESAS j AGC decrement delay 7 0 AGC decrement delay 7 0 Number of frames to delay gain decrements 1111 1111 255 0001 1110 30 default 0000 0000 0 0 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS o Functional Description 2 11 66 VDP TTX Filter And Mask Registers memes 7 6 s a 2 0 F F I For an NABTS system the packet prefix consists of five bytes Each byte contains 4 data bits D 3 0 interlaced with 4 Hamming protection bits H 3 0 Biz Bte Bits Bia Bts Biz Bin Bito oa ma om wa om mu Do mo Only data portion D 3 0 from each byte is applied to a teletext filter function with corresponding pattern bits P 3 0 and mask bits M 3 0 The filter ignores the Hamming protection bits For WST system PAL or NTSC the packet prefix consists of two bytes The two bytes contain three bits of magazine number
65. his state is valid default AGC luma enable Controls automatic gain in the embedded sync channel of CVBS S video component video 0 Manual gain AFE coarse and fine gain frozen to the previous gain value set by AGC when this bit is set to 0 1 Enabled auto gain applied to only the embedded sync channel default These settings only affect the analog front end AFE The brightness and contrast controls are not affected by these settings 2 11 3 Video Standard Register Subaddress 02h 7 6 5s 3 2 0 Video standard 20 Video standard 2 0 CVBS and S Video Component Video 000 Autoswitch mode default Autoswitch mode default 001 M J NTSC Component 525 010 B D G H I N PAL Component 625 011 M PAL Reserved 100 Combination N PAL Reserved 101 NTSC 4 43 Reserved 110 SECAM Reserved 111 PAL 60 Reserved With the autoswitch code running the user can force the decoder to operate in a particular video standard mode by writing the appropriate value into this register Changing these bits causes the register settings to be reinitialized 32 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 4 Operation Mode Register Subaddress 03h rr L e 5 a 3 23 1 o Reserved Power save Power save 0 Normal operation default 1 Power save mode Reduces the clock speed of the internal processor and switches off the ADC
66. inance processing control 2 register I2C data 04h Optimizes the chrominance filter selection for NTSC and PAL 12C register address 33h Output formatter 1 register I2C data 41h Selects the 20 bit 4 2 2 output format 12C register address 34h Output formatter 2 register I2C data 11h Enables YCbCr output and the clock output 12C register address 36h Output formatter 4 register 12 data AFh Enables HS and VS sync outputs SLES140A March 2007 X TEXAS TVP5147M1PFP 85 INSTRUMENTS Example Register Settings 86 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Application Information Application Information 5 1 Application Ekample FID KO lt gt co 22ko VSNBLK lt Hi i lt gt HS CS lt IOVDD3 3V A3 3VDD S O E XTALI gt c4 DVDD1 8V A1 8VDD XTAL2 lt lt lt gt 05 9 220 12kQ 7 e 1 VOUT al L 1 0 1 uF 2 VENIN oolojolnjoloi HS OO AN e OO MD CO BM O LO st OO AY 750 VV 5282832288 Tko 22ko O S ssskke o x q lt lt gt 7 Sda VL1A 0 1 60 VI 1B i 2 VLI_B 59 c6 VL
67. ing at URL hitp www ti com For the TVP5147 device this thermal land must be grounded to the low impedance ground plane of the device This improves not only thermal performance but also the electrical grounding of the device It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land The land size must be as large as possible without shorting device signal terminals The thermal land can be soldered to the exposed thermal pad using standard reflow soldering techniques While the thermal land can be electrically floated and configured to remove heat to an external heat sink it is recommended that the thermal land be connected to the low impedance ground plane for the device More information can be obtained from the TI application note PHY Layout SLLAO20 PowerPAD is a trademark of Texas Instruments 88 TVP5147M1PFP X TEXAS SLES140A March 2007 INSTRUMENTS K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 26 Feb 2007 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TVP5147M1PFP ACTIVE HTQFP PFP 80 96 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TVP5147M1PFPG4 ACTIVE HTQFP PFP 80 96 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TVP5147M1PFPR ACTIVE HTQFP PFP 80 1000 Green RoHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TVP514
68. ister Subaddress 20h 21h 007h Subaddress 7 6 5 4 3 2 3 o VSYNC stop 7 0 VSYNC stop 9 8 VSYNC stop 9 0 This is an absolute line number The TVP5147M1 decoder updates the VSYNC stop only when the VSYNC stop MSB is written to If the user changes these registers the TVP5147M1 decoder retains values in different modes until this decoder resets NTSC default 007h PAL default 004h 2 11 22 VBLK Start Line Register Subaddress 22h 23h 001h Subaddress 7 6 8 J 4 3 2 1 0 VBLK start 7 0 VBLK start 9 8 VBLK start 9 0 This is an absolute line number The TVP5147M1 decoder updates the VBLK start line only when the VBLK start MSB is written to If the user changes these registers the TVP5147M1 decoder retains values in different modes until this resets see Section 2 11 16 NTSC default 001h PAL default 623 26Fh 2 11 23 VBLK Stop Line Register Subaddress 24h 25h 015h Subaddress 7 6 8 4 3 2 J 1 o VBLK stop 7 0 VBLK stop 9 8 VBLK stop 9 0 This is an absolute line number The TVP5147M1 decoder updates the VBLK stop only when the VBLK stop MSB is written to If the user changes these registers then the TVP5147M1 decoder retains values in different modes until this device resets see Section 2 11 16 NTSC default 21 015h PAL default 23 017h 2 11 24 CTI Delay Register Subaddress 2Dh ETE 5 4a 3 2 v EY CTI delay 2 0
69. ita id hha adesto bed eds 2 2 Digital Video Processing st bir duat ksi ts xe RR ERU Eat E a Ee a ti 2 2 1 2y Decimation Filter AIKA eee eee eens 2 2 2 Composite Processor oocococcccccccc ess 2 2 3 Luminance Processing IA ne 2 2 4 Color Transient Improvement 2 3 Glock Circuits ecc de 2 4 Real Time Control RTC aaa 2 5 Output Formatter c n rori d hdd eda eae der Da Ai aaa 2 5 1 Separate SYNCS tas serie roe A d erba b edd ee ede pq 2 5 2 Embedded Syrnics asser RR A da WEE REX TETS 2 6 eC Mesh A A nti iL KM LOS 2 6 1 Reset and I2C Bus Address Selection 2 6 2 e o IA IINE LIP ELI kwake 2 6 3 VBUS ACCESS Mi IAA aa 2 7 VBI Data Processor r n e z n as 2 7 1 VBI FIFO and Ancillary Data in Video Stream 2 7 2 VBI Raw Data Output ii de kaw ae i bea Arad eed 2 8 Reset and Initialization wa teen hn 2 9 Adjusting External SYNCS siniri pa niia a da 2 10 Internal Control Registers ene e eee 2 11 Register Definillons cei v0 4 teed eed bowed eh ened beeen bee EE NUNA UMEE Ee ERE TE best 2 11 1 Input Select Register 2 11 2 AFE Gain Control Register 2 11 3 Video Standard Register ia aa Ka kwa 2 11 4 Operation Mode Register 2 11 5 Autoswitch Mask Regist
70. k Macrovision status changed Standard changed FIFO full HN lock H V lock status changed mask 0 H V lock status unchanged 1 H V lock status changed Macrovision status changed Macrovision status changed masked 0 Macrovision status not changed 1 Macrovision status changed Standard changed Standard changed masked 0 Video standard not changed 1 Video standard changed FIFO full full status of FIFO masked 0 FIFO not full 1 FIFO was full during write to FIFO see the interrupt mask 1 register at subaddress F5h for details see Section 2 11 88 via SLES140A March 2007 TEXAS TVP5147M1PFP 69 INSTRUMENTS Functional Description 2 11 87 Interrupt Mask 0 Register Subaddress F4h ER db cp WA AA ee E FIFO THRS FIFO THRS FIFO threshold passed mask 0 Disabled default 1 Enabled FIFO_THRES interrupt TTX Teletext data available mask 0 Disabled default 1 Enabled TTX available interrupt WSS WSS data available mask 0 Disabled default 1 Enabled WSS available interrupt VPS VPS data available mask 0 Disabled default 1 Enabled VPS available interrupt VITC VITC data available mask 0 Disabled default 1 Enabled VITC available interrupt CC F2 CC field 2 data available mask 0 Disabled default 1 Enabled CC_field 2 available interrupt CC F1 CC field 1 data available mask 0 Disabled default 1 Enabled CC_field 1 available interrupt Line Line number i
71. k is all Os then a true result is returned 62 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 1P1 3 D1 3 i BI 1M1 3 1P1 2 D1 2 E 1M1 2 rn oe Dili n 1M1 1 1P1 0 1M1 0 NIBBLE 1 D2 3 0 1P2 3 0 NIBBLE 2 1M2 3 0 PASS 1 D3 3 0 M 1P3 3 0 NIBBLE 3 _ E 1M3 3 0 D4 3 0 1P4 3 0 NIBBLE 4 1M4 3 0 D5 3 0 1P5 3 0 NIBBLE 5 Ll 1M5 3 0 FILTER 1 Filter Logic D1 D5 l 2P1 2P5 FILTER 2 2M1 2M5 Filter 2 Enable Figure 2 19 Teletext Filter Function 2 11 68 VDP FIFO Word Count Register BCh Read only EEE SE A oa s Jq n9 FIFO word count 7 0 FIFO word count 7 0 This register provides the number of words in the FIFO NOTE 1 word equals 2 bytes SLES140A March 2007 X TEXAS TVP5147M1PFP 63 INSTRUMENTS Functional Description 2 11 69 VDP FIFO Interrupt Threshold Register Subaddress BDh Default 80h 7 e j 5 a 3 j 2 13 0o Threshold 7 0 Threshold 7 0 This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value NOTE 1 word equals 2 bytes 2 11 70 VDP FIFO Reset Register Subaddress BFh Default 00h 7 8 j 5 a s 2 1 o Reserved FIFO reset FIFO reset Writing any
72. lor burst amplitude as a video amplitude reference for the back end NOTE Not available for SECAM component and B W video sources 0 Enabled default 1 Disabled Sync height A Use of the sync height as a video amplitude reference for the back end feed forward type AGC algorithm 0 Enabled default 1 Disabled Luma peak B Use of the luma peak as a video amplitude reference for the front end feedback type AGC algorithm 0 Enabled default 1 Disabled Composite peak Use of the composite peak as a video amplitude reference for the front end feedback type AGC algorithm NOTE Required for CVBS video sources 0 Enabled default 1 Disabled Color burst B Use of the color burst amplitude as a video amplitude reference for the front end feedback type AGC algorithm NOTE Not available for SECAM component and B W video sources 0 Enabled default 1 Disabled Sync height B Use of the sync height as a video amplitude reference for the front end feedback type AGC algorithm 0 Enabled default 1 Disabled NOTE If all 4 bits of the lower nibble are set to logic 1 that is no amplitude reference selected then the front end analog and digital gains are automatically set to nominal values of 2 and 2304 respectively If all 4 bits of the upper nibble are set to logic 1 that is no amplitude reference selected then the back end gain is set automatically to unity If the input sync height is g
73. ma transient improvement CTI circuit The following output formats can be selected 20 bit 4 2 2 YCbCr or 10 bit 4 2 2 YCbCr The TVP5147M1 decoder generates synchronization blanking field active video window horizontal and vertical syncs clock genlock for downstream video encoder synchronization host CPU interrupt and programmable logic VO signals in addition to digital video outputs The TVP5147M1 decoder includes methods for advanced vertical blanking interval VBI data retrieval The VBI data processor VDP slices parses and performs error checking on teletext closed caption CC and other VBI data A built in FIFO stores up to 11 lines of teletext data and with proper host port synchronization full screen teletext retrieval is possible The TVP5147M1 decoder can pass through the output formatter 2x sampled raw luma data for host based VBI processing The main blocks of the TVP5147M1 decoder include e Robust sync detection for weak and noisy signals as well as VCR trick modes e Y C separation by 2 D 5 line adaptive comb or chroma trap filter e Two 10 bit 30 MSPS A D converters with analog preprocessors clamp and automatic gain control AGC e Analog video output e Luminance processor e Chrominance processor e Clock timing processor and power down control e Software controlled power saving standby mode e Output formatter e C host port interface e VBI data processor e Macrovision copy protection dete
74. nly Gemstar NTSC only 101 USER 1 110 USER 2 111 Reserved active video default 76 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 12 9 VDP VPS Gemstar Data Register VPS Read only ai These registers contain the entire VPS data line except the clock run in code or the start code Gemstar Read only mms 7 s Ja 2 7 SLES140A March 2007 X TEXAS TVP5147M1PFP 77 INSTRUMENTS Functional Description 2 12 10 Analog Output Control 2 Register Subaddress AO 005Eh ES WAA a e Input Select 1 0 Gain 3 0 Analog input select 1 0 These bits are effective wnen manual input select bit is set to 1 at subaddress 7Fh bit 1 00 CH1 selected 01 CH2 selected 0 CH3 selected 11 CH4 selected default Analog output PGA gain 3 0 These bits are effective when analog output AGC is set to 1 at subaddress 7Fh bit 2 Gain 3 0 Mode 1 0000 1 30 0001 1 56 0010 default 1 82 0011 2 08 0100 2 34 0101 2 60 0110 2 86 0111 3 12 0000 3 38 0001 3 64 0010 3 90 0011 4 16 0100 4 42 0101 4 68 0110 4 94 0111 5 20 2 12 11 Interrupt Configuration Register Subaddress BO 0060h 7 6 5 4 3 2 1 0 Polarity Polarity Interrupt terminal polarity 0 Active high default 1 Active low 78 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Electrical Specifications 3 Electrical Specifications 3
75. nterface as described earlier Table 2 10 shows the summary of these registers Detailed programming information for each register is described in the following sections Additional registers are accessible through an indirect procedure involving access to an internal 24 bit address wide VBUS Table 2 11 shows the summary of the VBUS registers NOTE Do not write to reserved registers Reserved bits in any defined register must be written with Os unless otherwise noted Table 2 10 12C Register Summary Presea OJ JO VSYNC stop line 20h 21h 007h NOTE R Read only W Write only R W Read and write Reserved register addresses must not be written to SLES140A March 2007 i TEXAS TVP5147M1PFP 27 INSTRUMENTS Functional Description Table 2 10 12C Register Summary Continued NOTE R Read only W Write only R W Read and write Reserved register addresses must not be written to DEFAULT 001h 015h z 00h ojo gt Blo SP mnj gt gt eoimim s5 s s5 SIs m nmj nm o o mm Ex 2 E S EN 28 TVP5147M1PFP wy TEXAS SLES140A March 2007 INSTRUMENTS Functional Description Table 2 10 12C Register Summary Continued KA KAZ JO O AI meis AT a eewd KA KA C KA J eewd Sw J Verica meson S ow AI Vreservea ws emewd W amp m J TS o JURI eewd Jem L eewd dT DBh DFh NOTE R Re
76. nterrupt mask 0 Disabled default 1 Enabled Line INT interrupt The host interrupt mask 0 and 1 registers can be used by the external processor to mask unnecessary interrupt sources for the interrupt status 0 and 1 register bits and for the external interrupt terminal The external interrupt is generated from all nonmasked interrupt flags 70 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 88 Interrupt Mask 1 Register Subaddress F5h H V lock Macrovision status changed Standard changed FIFO full H V lock H V lock status changed masked 0 H V lock status unchanged default 1 H V lock status changed Macrovision status changed Macrovision status changed mask 0 Macrovision status unchanged 1 Macrovision status changed Standard changed Standard changed mask 0 Disabled default 1 Enabled video standard changed FIFO full FIFO full mask 0 Disabled default 1 Enabled FIFO full interrupt 2 11 89 Interrupt Clear 0 Register Subaddress F6h FIFOTHRS TTX FIFO THRS FIFO threshold passed clear 0 No effect default 1 Clear bit 7 FIFO_THRS in the interrupt status O register at subaddress F2h TTX Teletext data available clear 0 No effect default 1 Clear bit 6 TTX available in the interrupt status O register at subaddress F2h WSS WSS data available clear 0 No effect default 1 Clear bit 5 WSS available in the interrupt s
77. o component mode and SECAM 11 Reserved Peaking gain 1 0 00 0 default 01 0 5 10 1 11 2 2 11 9 Luminance Processing Control 3 Register Subaddress 08h lr j e j s j a 83 2 j 3 j 0 Trap filter select 1 0 Trap filter select 1 0 selects one of the four trap filters to produce the luminance signal by removing the chrominance signal from the composite video signal The stop band of the chroma trap filter is centered at the chroma subcarrier frequency with the stop band bandwidth controlled by the two control bits Trap filter stop band bandwidth MHz Filter select 1 0 NTSC ITU R BT 601 PAL ITU R BT 601 00 1 2129 1 2129 01 0 8701 0 8701 10 default 0 7183 0 7383 11 0 5010 0 5010 2 11 10 Luminance Brightness Register Subaddress 09h 7 e s a4 83 2 1 0 Brightness 7 0 Brightness 7 0 This register works for CVBS S video and component video luminance 1111 1111 2 255 bright 1000 0000 128 default 0000 0000 0 dark SLES140A March 2007 X TEXAS TVP5147M1PFP 35 INSTRUMENTS Functional Description 2 11 11 Luminance Contrast Register Subaddress OAh 80h LE o e 5 4a a 2 1 0o Contrast 7 0 Contrast 7 0 This register works for CVBS S video and component video luminance 1111 1111 255 maximum contrast 1000 0000 128 default 0000 0000 0 minimum contrast 2 11 12 Chrominance Saturation Register Subaddress OBh
78. oming video program is R rated in MPAA rating then this bit is set high PG 13 When incoming video program is PG 13 rated in MPAA rating then this bit is set high PG When incoming video program is PG rated in MPAA rating then this bit is set high G When incoming video program is G rated in MPAA rating then this bit is set high N A When incoming video program is N A rated in MPAA rating then this bit is set high i SLES140A March 2007 435 TEXAS TVP5147M1PFP 75 INSTRUMENTS Functional Description 2 12 8 VDP General Line Mode and Line Address Register default line mode FFh address 00h Subadaress 7 8 l 3 2 0 Line address 7 0 Line number to be processed by a VDP set by a line mode register default 00h Line mode register 7 0 Bit 7 0 Disabled filters 1 Enabled filters for teletext and CC null byte filter default Bit 6 0 Send sliced VBI data to registers only default 1 Send sliced VBI data to FIFO and registers teletext data only goes to FIFO default Bit 5 0 Allow VBI data with errors in the FIFO 1 Do not allow VBI data with errors in the FIFO default Bit 4 0 Disabled error detection and correction 1 Enabled error detection and correction teletext only default Bit 3 0 Field 1 1 Field 2 default Bits 2 0 000 Teletext WST625 Chinese teletext NABTS 525 001 CC US Europe Japan China 010 WSS 525 625 011 VITC 100 VPS PDC PAL o
79. onnect to 3 3 V DGND Digital return DVDD Digital power Connect to 1 8 V Digital power return Digital power Connect to 3 3 V or less for reduced noise Analog power return Analog power Connect to 1 8 V Horizontal sync output or digital composite sync output Programmable general purpose l O Vertical sync output for modes with dedicated VSYNC or VBLK output Programmable general purpose l O Odd even field indicator output This terminal needs a pulldown resistor see Figure 5 1 Programmable general purpose l O y o yo y o y o Active video indicator output Programmable general purpose l O SLES140A March 2007 X TEXAS TVP5147M1PFP 7 INSTRUMENTS Introduction 8 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 Functional Description 2 1 Analog Processing and A D Converters Figure 2 1 shows a functional diagram of the analog processors and A D converters which provide the analog interface to all video inputs It accepts up to 10 inputs and performs source selection video clamping video amplification A D conversion and gain and offset adjustments to center the digitized video signal The TVP5147M1 supports one analog video output for the selected analog input video y o DRE Analog Front End CH1 A D CVBS E ci Pb C VI 1 B amp VIT C 4 VI2 A CH2 A D CVBSI vi2c aid Line Locked Sampling Clock VL3_A gt CVBS
80. pojfojo wea view it oijfofofoj o 71fol o ves mes Jepe te to to rrot es v waa if ofeofofo 1fofolfol o Jua wag i oijfofofo fofo l o vse __ wise lt i ofeofofo 1fo zfoloa usc e 15 EC E CA a ESA BA ZA vesno o 3 pe ps KA KA KC e ju iIi ven Mean vi sate o o op pofoj os v wzsmwssQ Jote njo ron s veem Iwzomwaop 9 9 9 ve eene p EESTI pepe pe pe SS E camo pp pp pre lul VI 1 Pb VI 2 2 AY VI 3 A Pr ii VI 2 B Y VI 3 B Pr VI 2 B Y VI 1 C Pb VI 2 C Y VI 3 C Pr VI 2 C Y NOTE 1 When VI 1 A is set to output the total number of inputs is nine The video output can be either CVBS or luma Ten input terminals can be configured to support composite S video and component YPbPr as listed in Table 2 12 User must follow this table properly for S video and component applications because only the terminal configurations listed in Table 2 12 are supported SLES140A March 2007 X TEXAS TVP5147M1PFP 31 INSTRUMENTS Functional Description 2 11 2 AFE Gain Control Register AGC chroma AGC luma Bit 3 1 must be written to this bit Bit 2 1 must be written to this bit AGC chroma enable Controls automatic gain in the chroma PbPr channel 0 Manual if AGC luma is set to manual AGC chroma is forced to be in manual 1 Enabled auto gain applied a gain value acquired from the sync channel for S video and component mode When AGC luma is set t
81. reater than 100 and the AGC adjusted output video amplitude becomes less than 100 then the back end scale factor attempts to increase the contrast in the back end to restore the video amplitude to 100 4 TVP5147M1PFP TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 54 F and V Bit Control Register Subaddress 75h Default ET l a 3 2 d i Rabbit Fast lock F and V 1 0 Phase Det HPLL Rabbit Enable rabbit ear 0 Disabled default 1 Enabled Fast lock Enable fast lock where vertical PLL is reset and a 2 second timer is initialized when vertical lock is lost during time out the detected input VSYNC is output 0 Disabled 1 Enabled default F and V 1 0 Fadv Linespertrame EBRO 00 dela ae AA Wa i meer I Phase detector Enable integral window phase detector 0 Disabled 1 Enabled default HPLL Enable horizontal PLL to free run 0 Disabled default 1 Enabled SLES140A March 2007 X TEXAS TVP5147M1PFP 57 INSTRUMENTS Functional Description 2 11 55 VCR Trick Mode Control Register Subaddress 76h Switch header Horizontal shake threshold 6 0 Switch header When in VCR trick mode the header noisy area around the head switch is skipped 0 Disabled 1 Enabled default I Horizontal shake threshold 6 0 000 0000 Zero threshold 000 1010 OAh default 111 1111 2 Largest threshold 2 11 56 Horizontal Shake Increment R
82. requiring only 2 bytes of data plus the header then this goes into the FIFO even if the full error flag is set 2 11 85 Interrupt Status 0 Register F2h Read only LT E s 2 0 FIFO THRS FIFO THRS FIFO threshold passed masked 0 Not passed 1 Passed TTX Teletext data available masked 0 Not available 1 Available WSS WSS data available masked 0 Not available 1 Available ki 68 TVP5147M1PFP TEXAS SLES140A March 2007 INSTRUMENTS Functional Description VPS VPS data available masked 0 Not available 1 Available VITC VITC data available masked 0 Not available 1 Available CC F2 CC field 2 data available masked 0 Not available 1 Available CC F1 CC field 1 data available masked 0 Not available 1 Available Line Line number interrupt masked 0 Not available 1 Available The interrupt status O and 1 registers represent the interrupt status after applying mask bits Therefore the status bits are the result of a logical AND between the raw status and mask bits The external interrupt terminal is derived from this register as an OR function of all nonmasked interrupts in this register Reading data from the corresponding register does not clear the status flags automatically These flags are reset using the corresponding bits in interrupt clear 0 and 1 registers 2 11 86 Interrupt Status 1 Register Fsh Read only pt 6 18 148 18 j 2 1 00 H V loc
83. rocessing control 3 register I2C data 00h Optimizes the trap filter selection for NTSC and PAL 12C register address OEh Chrominance processing control 2 register I2C data 04h Optimizes the chrominance filter selection for NTSC and PAL 12C register address 33h Output formatter 1 register I2C data 41h Selects the 10 bit 4 2 2 output format 12C register address 34h Output formatter 2 register 12C data 11h Enables YCbCr output and the clock output 12C register address 36h Output formatter 4 register I2C data 11h Enables HS and VS sync outputs 4 3 Example 3 4 3 1 Assumptions Input connector Component VI 1 B Pb VI 2 B Y VI 3 B Pr Video format 4801 5761 Output format 20 bit ITU R BT 656 with discrete sync outputs 4 3 2 Recommended Settings Recommended 12C writes This setup requires additional writes to output the discrete sync 20 bit 4 2 2 data HS and VS and to autoswitch between all video formats mentioned above 84 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Example Register Settings 12C register address 00h Input select register 12C data 95h Sets Pb to VI 1 B Y to VI 2 B and Pr to VI 3 B 12C register address 04h Autoswitch mask register 12C data 3Fh Includes NTSC 443 and PAL M Nc 60 in the autoswitch 12C register address 08h Luminance processing control 3 register I2C data 00h Optimizes the trap filter selection for NTSC and PAL 12C register address OEh Chrom
84. s 12C interface is active and all current operating settings are preserved 2 11 5 Autoswitch Mask Register Subaddress 04h 23h 7 6 s a4 j 3 2 1 0 PAL 60 SECAM NTSC 4 43 Nc PAL M PAL M J NTSC Autoswitch mode mask Limits the video formats between which autoswitch is possible PAL 60 0 Autoswitch does not include PAL 60 default 1 Autoswitch includes PAL60 SECAM 0 Autoswitch does not include SECAM 1 Autoswitch includes SECAM default NTSC 4 43 0 Autoswitch does not include NTSC 4 43 default 1 Autoswitch includes NTSC 4 43 Nc PAL 0 Autoswitch does not include Nc PAL default 1 Autoswitch includes Nc PAL M PAL 0 Autoswitch does not include M PAL default 1 Autoswitch includes M PAL PAL 0 Reserved 1 Autoswitch includes B D G H 1 N PAL default M J NTSC 0 Reserved 1 Autoswitch includes M J NTSC default NOTE Bits 1 and 0 must always be 1 SLES140A March 2007 wa TEXAS TVP5147M1PFP 33 INSTRUMENTS Functional Description 2 11 6 Color Killer Register Subaddress 05h Lou A E E IESO O AN EA A A Automatic color killer Color killer threshold 4 0 Automatic color killer 00 Automatic mode default 01 Reserved 10 Color killer enabled the UV terminals are forced to a zero color state 11 Color killer disabled Color killer threshold 4 0 1 1111 31 maximum 1 0000 16 default 0 0000 0
85. site peak to decrement the front end gain For example writing 0x09 to this register disables the back end AGC whenever the front end AGC uses the sync height to decrement the front end gain Peak Disables back end AGC when the front end AGC uses the composite peak as an amplitude reference 0 Disabled default 1 Enabled Color Disables back end AGC when the front end AGC uses color burst as an amplitude reference 0 Disabled default 1 Enabled Sync Disables back end AGC when the front end AGC uses the sync height as an amplitude reference 0 Disabled default 1 Enabled 2 11 51 AGC Decrement Speed Control Register Subaddress 6Fh ARE E se ee ee a AGC decrement speed 2 0 AGC decrement speed Adjusts gain decrement speed Only used for composite luma peaks 111 7 slowest 110 6 default 000 0 fastest 2 11 52 ROM Version Register 70h Read only LoT 8 j s j 4 3 23 o1 j 0 ROM version 7 0 ROM Version 7 0 ROM revision number SLES140A March 2007 X TEXAS TVP5147M1PFP 55 INSTRUMENTS Functional Description 2 11 53 AGC White Peak Processing Register Subaddress 74h ET E E 4 LEE EA A Luma peak A Color burstA Sync height A Luma peakB Composite peak Color burst B Sync height B 56 Luma peak A Use of the luma peak as a video amplitude reference for the back end feed forward type AGC algorithm 0 Enabled default 1 Disabled Color burst A Use of the co
86. sive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA PFP S PQFP G80 PowerPAD
87. sponds to a code 0x0 2 0 Vpp full scale input 6 dB gain while maximum gain corresponds to code OxF 0 5 Vpp full scale 6 dB gain The TVP5147M1 decoder also has 12 bit fine gain controls for each channel and applies independently to coarse gain controls For composite video the input video signal amplitude can vary significantly from the nominal level of 1 Vpp The TVP5147M1 decoder can adjust its PGA setting automatically an automatic gain control AGC can be enabled and can adjust the signal amplitude such that the maximum range of the ADC is reached without clipping Some nonstandard video signals contain peak white levels that saturate the ADC In these cases the AGC automatically cuts back gain to avoid clipping If the AGC is on then the TVP5147M1 decoder can read the gain currently being used The TVP5147M1 AGC comprises the front end AGC before Y C separation and the back end AGC after Y C separation The back end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak which is only relevant before Y C separation forces the front end AGC to set the gain too low The front end and back end AGC algorithms can use up to four amplitude references sync height color burst amplitude composite peak and luma peak The specific amplitude references being used by the front end and back end AGC algorithms can be independently controlled using the AGC white peak processing register located at subaddress 7
88. st Port Timing Bus es me beton STOP and START Cd gr Data Po tive TJ goal a Data set tin OOOO o o J u Setup time ora epee START coran JO og Ju fis Sewp ime tora STOP conan J o Te CA ea Rise time VC1 m and eni signal Po 250 ns gal tine VISOR ana veo sna 0 op _Gapactveoadforeashbustine aa fig PC dockreaueney AO Stop Start Stop vies TPN foe XT t4 Jep us t ie ip Es aL to om s ta pug t5 je t MCN Change ts M VCO SCL Data 7 Figure 3 2 12C Host Port Timing SLES140A March 2007 we TEXAS TVP5147M1PFP 81 INSTRUMENTS Electrical Specifications 82 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Example Register Settings 4 Example Register Settings The following example register settings are provided only as a reference These settings given the assumed input connector video format and output format set up the TVP5147M1 decoder and provide video output Example register settings for other features and the VBI data processor are not provided here 4 1 Example 1 4 1 1 Assumptions Input connector Composite VI 1 A default Video format NTSC J M PAL B G H I N or SECAM default NOTE NTSC 443 PAL Nc PAL M and PAL 60 are masked from the autoswitch process by default See the autoswitch mask register at address 04h Output format 10 bit ITU R BT 656 with embedded syncs default 4 1 2 Recommended Settings Recommend
89. t 0001 0 6 0000 0 5 9 8 I 6 5 4 3 2 1 2 11 41 AFE Coarse Gain for CH 2 Register Subaddress 47h Default 20h Lor 8 j s a j 3 23 J 1 0 CGAIN 2 5 0 CGAIN 2 3 0 Coarse Gain 0 5 CGAIN 2 10 where 0 x CGAIN 2 x 15 This register works only in manual gain control mode When AGC is active writing to any value is ignored 1111 2 0010 0 7 default 0001 0 6 0000 0 5 435 50 TVP5147M1PFP TEXAS SLES140A March 2007 INSTRUMENTS Functional Description 2 11 42 AFE Coarse Gain for CH 3 Register Subaddress 48h 20h ET e s a LT or CGAIN 3 3 0 CGAIN 3 3 0 Coarse Gain 0 5 CGAIN 3 10 where 0 lt CGAIN 3 lt 15 This register works only in the manual gain control mode When AGC is active writing to any value is ignored 1111 2 0011 0 8 0010 0 7 default 0001 0 6 0000 0 5 2 11 43 AFE Coarse Gain for CH 4 Register Subaddress 49h 20h L T ve s s dq s 1 8 7 CGAIN 4 3 0 CGAIN 4 3 0 Coarse Gain 0 5 CGAIN 4 10 where O lt CGAIN 4 lt 15 This register works only in the manual gain control mode When AGC is active writing to any value is ignored 1111 es 1110 1 1101 1100 1011 1010 1001 1000 0111 0110 1 0101 1 0100 0 9 0011 0 8 0010 0 7 default 0001 0 6 0000 0 5 9 1 8 17 1 6 1 5 1 4 1 3 1 2 M SLES140A March 2007 X TEXAS TVP5147M1PFP 51 INSTRUMENTS Functional Description
90. t as ancillary data in the video stream in ITU R BT 656 mode VBI data is output on the Y 9 2 terminals during the horizontal blanking period Table 2 7 shows the header format and sequence of the ancillary data inserted into the video stream This format is also used to store any VBI data into the FIFO The size of the FIFO is 512 bytes Therefore the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard Table 2 7 Ancillary Data Format and Sequence BYTE D7 DO DESCRIPTION ee JW e 2 Ls oo ss oo o pa we e rs re ra re ri Fo Second cata SDB A A s E Video line 7 0 Internal data IDO IDIDO data IDO IDIDO Data Match Match Video line 9 8 Internal data ID1 IDID1 error 1 2 1 Data Data byte 1St word Ancillary data preamble irc cc rm L Is 13515 3 e O NOTE The number of bytes m varies depending on the VBI data service EP Even parity for DO D5 NEP Negated even parity DID 91h Sliced data of VBI lines of first field 53h Sliced data of line 24 to end of first field 55h Sliced data of VBI lines of second field 97h Sliced data of line 24 to end of second field SDID This field holds the data format taken from the line mode register bits 2 0 of the corresponding line NN Number of Dwords beginning with byte 8 through 4N 7 Note this value is the number of Dwords where each Dword is 4 bytes IDIDO Transaction video line number 7 0 IDID
91. t mode the two LSBs are ignored Unused outputs can be left unconnected Digital video output of Y YCbCr Y 9 is MSB and Y 0 is LSB For the 8 bit mode the two LSBs are ignored Unused outputs can be left unconnected Miscellaneous sane GPIO Programmable general purpose I O GLCO I2CA Genlock control output GLCO uses real time control RTC format During reset this terminal is an input used to program the 12C address LSB INTREQ PWDN 0 Normal mode RESETB Reset input active low see Section 2 8 Host Interface ia I2C data bus Interrupt request terminals internally floating Power down input 1 Power down ja Not connected These terminals can be connected to power or ground compatible with TVP5146 6 TVP5147M1PFP wa TEXAS SLES140A March 2007 INSTRUMENTS Introduction Table 1 1 Terminal Functions Continued TERMINAL 1 0 DESCRIPTION NAME NUMBER Power Supplies AGND 26 Analog ground Connect to analog ground A18GND_REF 13 _ Analog 1 8 V return A18VDD_REF 12 Analog power for reference 1 8 V CH1_A18GND CH2_A18GND A18GND CH1_A18VDD CH2_A18VDD A18VDD CH1_A33GND CH2_A33GND CH1_A33VDD 4 CH2_A33VDD 5 27 32 42 56 68 31 41 55 67 IOGND 39 49 62 IOVDD 38 48 61 PLL A18GND 77 PLL_A18VDD 76 Sync Signals HS CS GPIO 72 VS VBLK GPIO 73 71 FID GPIO AVID GPIO 36 Analog 1 8 V return Analog power Connect to 1 8 V Analog 3 3 V return Analog power C
92. tatus O register at subaddress F2h VPS VPS data available clear 0 No effect default 1 Clear bit 4 VPS available in the interrupt status O register at subaddress F2h VITC VITC data available clear 0 Disabled default 1 Clear bit 3 VITC available in the interrupt status O register at subaddress F2h CC F2 CC field 2 data available clear 0 Disabled default 1 Clear bit 2 CC field 2 available in the interrupt status O register at subaddress F2h CC F1 CC field 1 data available clear 0 Disabled default 1 Clear bit 1 CC field 1 available in the interrupt status O register at subaddress F2h wi SLES140A March 2007 TEXAS TVP5147M1PFP 71 INSTRUMENTS Functional Description Line Line number interrupt clear 0 Disabled default 1 Clear bit 0 line interrupt available in the interrupt status O register at subaddress F2h The host interrupt clear O and 1 registers are used by the external processor to clear the interrupt status bits in the host interrupt status O and 1 registers When no nonmasked interrupts remain set in the registers the external interrupt terminal also becomes inactive 2 11 90 Interrupt Clear 1 Register Subaddress F7h pr TJ 6 fos T 4 18 1 2 po 1 HIV lock Macrovision status changed Standard changed FIFO tull HIV lock Clear H V lock status changed flag 0 H V lock status unchanged 1 HIV lock status changed Macrovision status changed Clear Macrovision status changed flag 0
93. the heat transfer from the integrated circuit IC For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMA002 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAO04 Both documents are available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 60 4 61 40 Exposed Thermal Pad 6 20 4 69 80 21 1 20 6 20 b 4 69 Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206326 3 C 09 07 LAND PATTERN PFP S PQFP G80 PowerPAD Example Board Layout Stencil Openings Via pattern and copper area under solder mask Based on a stencil thickness may vary depending on layout constraints of 127mm 005inch Reference table below for other
94. then this bit is set high Y7 FV When incoming video program is TV Y7 FV rated then this bit is set high is 4 TVP5147M1PFP X TEXAS SLES140A March 2007 INSTRUMENTS N 2 12 6 Functional Description VDP V Chip TV Rating Block 3 Register Subaddress 80 0542h Read only TV parental guidelines rating block 3 2 12 7 None no block intended TV MA When incoming video program is TV MA rated in TV parental guidelines rating then this bit is set high TV 14 When incoming video program is TV 14 rated in TV parental guidelines rating then this bit is set high TV PG When incoming video program is TV PG rated in TV parental guidelines rating then this bit is set high TV G When incoming video program is TV G rated in TV parental guidelines rating then this bit is set high TV Y7 When incoming video program is TV Y7 rated in TV parental guidelines rating then this bit is set high TV Y When incoming video program is TV G rated in TV parental guidelines rating then this bit is set high None no block intended VDP V CHIP MPAA Rating Data Register Subaddress 80 0543h Read only Er s AA o Not Rated NC 17 MPAA rating block E5h Not rated When incoming video program is not rated in MPAA rating then this bit is set high X When incoming video program is X rated in MPAA rating then this bit is set high NC 17 When incoming video program is NC 17 rated in MPAA rating then this bit is set high R When inc
95. urations The TVP5147M1 decoder generates the DATACLK signal used for clocking data TVP5147M1 TVP5147M1 14 318 MHz Crystal CL1 74 14 318 MHz Clock E c 75 La Figure 2 10 Reference Clock Configurations Real Time Control RTC Although the TVP5147M1 decoder is a line locked system the color burst information is used to determine accurately the color subcarrier frequency and phase This ensures proper operation with nonstandard video signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video line frequency The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 GLCO for optional use in an end system for example by a video encoder The frequency control word is a 23 bit binary number The instantaneous frequency of the color subcarrier can be calculated using the following equation F et FPLE T geg E Sclk where Fp is the frequency of the subcarrier PLL Fei is the 23 bit PLL frequency control word and Fac is two times the pixel frequency This information can be generated on the GLCO terminal Figure 2 11 shows the detailed timing diagram Valid Invalid Sample Sample Reserved XXX AL AL pa DA AL D KANT 128 CLK p I 18 CLK pa 45 CLK P4 gt 3 CLK I 23 Bit Fsc PLL Increment gt I 1CLK Start Bit RTC reset bit R is active low S
96. vices connected to the bus A third signal I2CA is used for slave address selection Although an 12C system can be multimastered the TVP5147M1 decoder functions as a slave device only Because SDA and SCL are kept open drain at a logic high output level or when the bus is not driven the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board The slave addresses select signal terminal 37 I2CA enables the use of two TVP5147M1 devices tied to the same 12C bus because it controls the least significant bit of the 12C device address via SLES140A March 2007 TEXAS TVP5147M1PFP 21 INSTRUMENTS Functional Description Table 2 4 12C Host Interface Terminal Description SIGNAL TYPE DESCRIPTION 12CA OJ Slave address selection SCL PJ Input clock line SDA 1 0 Input output data line 2 6 1 Reset and I12C Bus Address Selection The TVP5147M1 decoder can respond to two possible chip addresses The address selection is made at reset by an externally supplied level on the I2CA terminal The TVP5147M1 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I2C bus address bit AO The I2CA terminal has an internal pulldown resistor to pull the terminal low to set a zero Table 2 5 12C Address Selection ww WE 0 default B9 B8 BB BA T If terminal 37 is strapped to DVDD via a 2 2 kQ resistor I2C device address AO is set to 1 2 6 2 12C Operation
97. y present 111 AGC pulses pseudo syncs and 4 line color stripe present type 3 2 11 36 AGC Gain Status Register Read only Fine gain 7 0 Coarse gain 3 0 Fine gain 11 8 Fine gain 11 0 This register provides the fine gain value of sync channel 1111 1111 1111 1 9995 1000 0000 0000 1 0010 0000 0000 0 5 Coarse gain 3 0 This register provides the coarse gain value of sync channel 1111 2 0101 1 0000 0 5 These AGC gain status registers are updated automatically by the TVP5147M1 decoder with AGC on In manual gain control mode these register values are not updated by the TVP5147M1 decoder via SLES140A March 2007 TEXAS TVP5147M1PFP 47 INSTRUMENTS Functional Description 2 11 37 Video Standard Status Register Read only Autoswitch Video standard 2 0 Autoswitch mode i 0 Stand alone forced video standard mode 1 Autoswitch mode Video standard 2 0 CVBS and S video Component video 000 Reserved Reserved 001 M J NTSC Component 525 010 B D G H I N PAL Component 625 011 M PAL Reserved 100 Combination N PAL Reserved 101 NTSC 4 43 Reserved 110 SECAM Reserved 111 PAL 60 Reserved This register contains information about the detected video standard that the device is currently operating When autoswitch code is running this register must be tested to determine which video standard has been detected 2 11 38 GPIO Input 1 Register 40h Read only a

Texas Instruments TVP5147M1PFP User's Manual

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