Texas Instruments TPS62065 User's Manual
Contents
1. Vu 3 6 V Cour 10 uF 0603 size a Vw 4 2 V Vout 71 8 V Vn 5 0V Mode Auto PFM PWM 50 0 02 04 06 08 10 12 14 16 18 20 lour A Figure 4 TPS62065 TPS62067 Efficiency vs Load Current 6 2 Start up TPS62065 Figure 5 shows the typical start up performance for the TPS62065 using the TPS62065EVM TPS62065 Startup 2 Vidiv a 1 V div vouTt 2 A div 500 mAy div IInductor 3 L 2 1 2 uH Cour 10 uF Vin 3 6 V 500 mA div I IN Vout 1 8 V Load R2R Time 100 us div Conditions VIN 3 6 V Voy 1 8 V Figure 5 TPS62065 Startup into 2 2 O Load 8 TPS62065 67EVM SLVUS364 March 2010 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62065 67EVM Test Data 6 3 Start up and Shutdown TPS62067 Figure 6 and Figure 7 illustrate the typical start up and shutdown behavior respectively for the TPS62067 using the TPS62067EVM TPS62067 Startup 2 Vidiv 2 Vidiv 1 A div ji Inductor Vin 4 2V Vout 83V 2 Vidiv Load 2R2 PG PG Pull up Resistor 10 KQ EPEE EE EEEE E EES ENE E CEE ig Ng a Be EENE tg Time 100 us div Conditions VIN 4 2 V Vout 3 3 V Figure 6 TPS62067 Startup into 2 2 O Load TPS62067 Shutdown 2 V div EN Vn 4 2V Vour 3 8 V Load No Load PG Pull up Resistor 10 kQ 2 V div vour 5 V div pc Time 1 ms div Co2. Figure 10 and Figure 11 illustrate typical TPS62065 gain and phase performance versus frequency at VIN 3 6 V and 5 0 V respectively using the TPS62025EVM MKR 1 224 838 4kHz PHASE MKR 1 224 838 4kHz 8 88 deg 45 88 deg 59 32 deg 224 830 4kHz 0 001 dB START 18kHz C 8 6 dBm STOP 2MHz Conditions VIN 3 6 V VOUT 1 8 V loy 1 6 A bandwidth 224 kHz phase margin 59 Figure 10 TPS62065 Gain and Phase vs Frequency MKR 1 271 837kKHZ SE MKR 1 271 837kHz 8 88 deg 45 88 deg 54 61 deg 271 83 7kH2 0 010 dB START 18kHz 8 0 dBm STOP 2MHz Conditions VIN 5 0 V VOUT 1 8 V loy 1 6 A bandwidth 271 kHz phase margin 54 Figure 11 TPS62065 Gain and Phase vs Frequency SLVUS64 March 2010 TPS62065 67EVM 11 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS TPS62065 67EVM 347 Assembly Drawings and Layout 7 TPS62065 67EVM 347 Assembly Drawings and Layout Figure 12 through Figure 16 show the design of the TPS62065 67EVM 347 printed circuit boards This EVM has been designed using a four layer 1 ounce copper clad PCB 3 81 cm by 4 57 cm with all components in an active area on the top side of the board All active traces to the top and bottom layers to allow the user to easily view probe and evaluate the TPS62025 67 control ICs in a practical double sided application environment Moving components to both sides of the PCB or us
3. INSTRUMENTS TPS62065 67EVM 347 Assembly Drawings and Layout www ti com Figure 15 TPS62065 67EVM Internal Layer 1 X Ray View from Top 16 TPS62065 67EVM SLVU364 March 2010 Copyright 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62065 67EVM 347 Assembly Drawings and Layout Figure 16 TPS62065 67EVM Bottom Side Copper Bottom View SLVU364 March 2010 TPS62065 67EVM 17 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS Bill of Materials www ti com 8 Bill of Materials Table 2 lists the bill of materials for the TPS62065 67EVM Table 2 TPS62065 67EVM Bill of Materials 9 Count RefDes Value Description Size Part Number MFR 2 C10 C20 22 uF Capacitor ceramic 10 V X7R 10 1210 GRM32ER71A226K MuRata 2 C11 C21 22 pF Capacitor ceramic 10 V NGO 596 0603 Standard Standard C12 C13 i GRM188R60J106ME47 4 C22 C23 10 uF Capacitor ceramic 6 3 V X5R 20 0603 D muRata 0 C14 C24 Open Capacitor ceramic 6 3 V X5R 20 Qegg QRM188R60J106ME47 nual 0 J16 J27 Open Connector SMA straight PC mount 0 210 in 901 144 8RFX AMP 2 L10 L20 1 0 uH Inductor chip coil 30 1515 LQH44PN1RONPOL Murata 1 R10 360 kQ Resistor chip 1 16W 196 0603 Standard Std 2 R11 R21 180 kQ Resistor chip 1 16W 196 0603 Standard Std 1 R20 820 kQ Resistor chip 1 16W 196 0603 Standard Std 4 FUSE 1 00 M
4. Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DLP Products www dlp com Communications and www ti com communications Telecom DSP dsp ti com Computers and www ti com computers Peripherals Clocks and Timers www ti com clocks Consumer Electronics www ti com consumer apps Interface interface ti com Energy www ti com energy Logic logic ti com Industrial www ti com industrial Power Mgmt power ti com Medical www ti com medical Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Space Avionics amp www ti com space avionics defense Defense RF IF and ZigBee Solutions www ti com Iprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2010 Texas Instruments Incorporated
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7. 14 S S J14 S S are the sense connections for the output of the converter Connect a voltmeter or the sense connection of an electronic load or oscilloscope to this header 4 1 6 J15 GND J15 is the return connection of the converter A load can be connected between J15 and J13 Vout The converter is capable of carrying a load current up to 2000 mA 4 1 7 JP10 EN This jumper enables disables the TPS62065 on the EVM Shorting jumper JP10 between the center pin and On turns on the unit Shorting the jumper between center pin and Off turns the unit off A 1 MO pull up resistor is connected between VIN and EN Removing jumper JP10 turns on the converter 4 1 8 JP11 MODE This jumper enables disables the power saving mode under light loads Shorting jumper JP11 between the center pin and PWM disables the power saving mode If the power save mode is disabled the converter operates in forced PWM mode over the entire load current range Shorting the jumper between the center pin and PWM PSM enables the power saving mode The device operates in power saving mode under light load conditions See the TPS6206x data sheet SLVS833 for a detailed description of this configuration A 1 MO pulldown resistor is connected between GND and MODE By removing JP11 the converter operates in power saving mode under light load conditions 4 TPS62065 67EVM SLVU364 March 2010 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated l
8. DE 3 3 Hardware Board Connection aee eroe nort remet nna a UEM ENSE FREE aa NERIS ERU 6 4 TPS62065 TPS62067 Efficiency vs Load CUITeNt eceeee eee eee e ee eee eee e eee eee eens tease eee eee eee teen nenne 8 5 IPS62065 Start p into 2 2 O Load 24e cereo e ei Reed reed exe spem eo ees DE EEE EEEN 8 6 TPS62067 Startup into 22 O OA apes euros enum E cus du DUE NES DuECeEERNu Mus E 9 7 TPS62067 Shutdown NO EO8d oe neun inuenit e netu nIc a RE RUNDE n URN ipa ER ERA EEE E cU EUN RE NN EE DNE TEE 9 8 TPS62065 Output Voltage Ripple PFM Mode ceeeeeeeennIIIIIIHIIHIIIIHIIH HH nn 10 9 TPS62065 Output Voltage Ripple PWM Mode cceeseeenI III nnn 10 10 TPS62065 Gain and Phase vs Frequency cseesseeseeeeeeeene hne nnne nnn nne nennen nnne 11 11 TPS62065 Gain and Phase vs Frequency cseesseeseeeeeleene seen ene nnne nnne 11 12 TPS62065 67EVM Component Placement Top View ceeeeseeee HII 13 13 TPS62065 67EVM Top Side Copper Top View 1 0 ececeeeee cece ee ee eens eee eeeeeeeeeeeeeeeeeeeeeeeeneeeeeenaeeee 14 14 TPS62065 67EVM Internal Layer 2 X Ray View from Top esee HH 15 15 TPS62065 67EVM Internal Layer 1 X Ray View from TOP ssceeeeeeeeeeeee reese eee eee HH 16 16 TPS62065 67EVM Bottom Side Copper Bottom View ccceeceee cence eee eee eee eee e eee eee sees eeeeeeeeeenaeeee 17 List of Tables 1 TPS62065 67EVM Performance Characte
9. IA TEXAS User s Guide INSTRUMENTS SLVU364 March 2010 TPS62065 67EVM This users guide describes the characteristics operation and use of the TPS62065 67EVM 347 evaluation module EVM The TPS62065 67EVM 347 is a fully assembled and tested platform for evaluating the performance of both the TPS62065 and TPS62067 2 A step down converters This document includes schematic diagrams printed circuit board PCB layout bill of materials and test data Throughout this document the abbreviations EVM TPS62065 67EVM and the term evaluation module are synonymous with the TPS62065 67EVM 347 unless otherwise noted Contents 1 Tniigee ce i ee he ee 2 2 Electrical Performance Specifications 4 ic ce aee e re Eee eunte ex a nma aede a rea kE EE 2 3 TPS62056 67 EVM SCHEMALIC ss usus eue Seu pue EEEE EAR ERR RRRCeRR MER Es cde erst E cua Cose 3 4 Connector and Test Point Descriptions cceceeee eee ee eee eee eee eee II II nm nemen emn hene 4 5 TESUCONIQUIAUON te M 6 6 TIPS62065 67EVM Test Dala secius cause Sie esu xoc De UM DEM MO Mm ER AERE EM EE UEM EE 8 7 TPS62065 67EVM 347 Assembly Drawings and Layout ceseeeseeeen III 12 8 Bill f II 18 List of Figures 1 TPSG2065EVM SCNEMALC m I Mrm 3 2 TPS62067EVM SClieIrialiC esee edicxiciacs ei uten stance nae E cist recu x E A UE qoEip dr mus RUD KR E RR
10. Q Resistor chip 1 16W 1 0603 Standard Std R22 R23 Cop nds 1 U10 TPS62065DSG IC step down converter 3 MHz 1 6 A SON 8 TPS62065DSG TI 1 U20 TPS62067DSG IC step down converter 3 MHz 1 6 A SON 8 TPS62067DSG TI ESTS R 18 These assemblies are ESD sensitive ESD precautions must be observed These assemblies must be clean and free from flux and all contaminants Use of no clean flux is not acceptable These assemblies must comply with workmanship standards IPC A 610 Class 2 Reference designators marked with an asterisk cannot be substituted All other components can be substituted with equivalent manufacturing components TPS62065 67EVM Copyright 2010 Texas Instruments Incorporated SLVUS364 March 2010 Submit Documentation Feedback Evaluation Board Kit Important Notice Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically fo
11. TE These diagrams are provided for reference only See Table 2 the Bill of Materials for specific component values SLVUS64 March 2010 TPS62065 67EVM 3 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS Connector and Test Point Descriptions www ti com 4 Connector and Test Point Descriptions 41 Enable Jumpers Switches TPS62065E VM 4 1 1 J10 VIN This header is the positive connection to the input power supply The power supply must be connected between J10 and J12 GND The leads to the input supply should be twisted and kept as short as possible The input voltage must be between 3 0 V and 6 0 V 4 1 2 J11 S S J11 S S are the sense connections for the input of the converter Connect a voltmeter or the sense connection of a power supply or oscilloscope to this header 4 1 3 J12 GND This header is the return connection to the input power supply Connect the power supply between J12 and J10 VIN The leads to the input supply should be twisted and kept as short as possible The input voltage must be between 3 0 V and 6 0 V 4 1 4 J13 VOUT This header is the positive output of the step down converter The output voltage of the TPS62065 is adjustable with feedback resistors R10 and R11 On the EVM the output voltage is set to 1 8 V by default NOTE A feed forward capacitor is required Refer to the TPS6206x data sheet SLVS833 for detailed information 4 1 5 J
12. TEXAS INSTRUMENTS www ti com Connector and Test Point Descriptions 4 1 9 J16 VOUT SMA This SMA connector is connected to the output voltage of the TPS62065 It can be used to easily analyze the noise spectrum of the output voltage with a spectrum analyzer By default J16 is not assembled on the EVM 42 Enable Jumpers Switches TPS62067EVM 4 2 1 J20 VIN This header is the positive connection to the input power supply The power supply must be connected between J10 and J12 GND The leads to the input supply should be twisted and kept as short as possible The input voltage must be between 3 0 V and 6 0 V 4 2 2 J21 S S J21 S S are the sense connections for the converter input Connect a voltmeter or the sense connection of a power supply or an oscilloscope to this header 4 2 3 J22 GND This header is the return connection to the input power supply Connect the power supply between J22 and J20 VIN The leads to the input supply should be twisted and kept as short as possible The input voltage must be between 3 0 V and 6 0 V 4 2 4 J23 VOUT This header is the positive output of the step down converter The output voltage of the TPS62067 is adjustable with the feedback resistors R20 and R21 On the EVM the output voltage is set to 3 3 V by default NOTE There is a feed forward capacitor required Refer to the TPS6206x data sheet SLVS833 for detailed information 4 2 5 J24 S S J24 S S are the sens
13. age range of 3 0 V to 6 0 V and the output voltage range of 0 8 V to 6 0 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655308 Dallas Texas 75265 Copyright O 2010 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modificat
14. ance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference EVM Warnings and Restrictions It is important to operate this EVM within the input volt
15. e connections for the converter output Connect a voltmeter or the sense connection of an electronic load or an oscilloscope to this header 4 2 6 J25 GND J25 is the return connection of the converter A load can be connected between J25and J23 Vout The converter is capable of a load up to 2 000 mA load current 4 2 7 J26 PG PG Power Good is an open drain output A 1 MQ pull up resistor is connected between VIN and PG This circuit is active once the device is enabled It is driven by an internal comparatir that is connected to the FB voltage The PG output provides a high level output once the FB voltage reaches 95 of its nominal value The PG output provides a low level output when the FB voltage falls below 90 of its nominal value NOTE This function is only available on the TPS62067EVM SLVU364 March 2010 TPS62065 67EVM 5 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS Test Configuration www ti com 4 2 8 JP20 EN This jumper enables disables the TPS62067 device on the EVM Shorting jumper JP20 between the center pin and On turns on the unit Shorting the jumper between center pin and Off turns the unit off A 1 MO pull up resistor is connected between VIN and EN Removing jumper JP20 also turns on the converter 4 2 9 J27 VOUT SMA This SMA connector is connected to the output voltage of the TPS62067 It can be used to easily analyze the noise spectrum of the output v
16. ing additional internal layers can offer additional size reduction for space constrained systems www ti com NOTE Board layouts are not to scale These figures are intended to show how the board is laid out they are not intended to be used for manufacturing TPS62065 67EVM 347 PCBs 12 TPS62065 67E VM SLVU364 March 2010 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62065 67EVM 347 Assembly Drawings and Layout 38 10 mm 1 50 inch TEXAS INSTRUMENTS TPS62067 EVM HPA347 Rev A 2010 Y 38 10 mm 1 50 inch TEXAS INSTRUMENTS TPS62065 EVM HPA347 Rev A 2010 Y 45 72 mm 1 80 inch Figure 12 TPS62065 67EVM Component Placement Top View SLVU364 March 2010 TPS62065 67EVM 13 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS TPS62065 67EVM 347 Assembly Drawings and Layout www ti com Figure 13 TPS62065 67EVM Top Side Copper Top View 14 TPS62065 67EVM SLVU364 March 2010 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62065 67EVM 347 Assembly Drawings and Layout Figure 14 TPS62065 67EVM Internal Layer 2 X Ray View from Top SLVU364 March 2010 TPS62065 67EVM 15 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated 1 TEXAS
17. ions enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use
18. nd J25 on the TPS62067EVM 4 To enable the converter connect the shorting bar on JP10 JP20 between EN and ON on the TPS62065EVM TPS62067EVM 5 The TPS62065EVM has a feature to allow the user to switch between Power Save Mode under light loads and forced PWM mode this feature is enabled or disabled with jumper JP11 This feature is only available on the TPS62065EVM 6 The TPS62067EVM has a PG Power Good output The PG pin on the TPS62067 is connected to J26 PG is an open drain output The output is pulled up with a 1 MO pull up resistor R22 to VIN This feature is only available on the TPS62067EVM SLVUS64 March 2010 TPS62065 67EVM 7 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS TPS62065 67EVM Test Data www ti com 6 TPS62065 67EVM Test Data Figure 4 through Figure 11 present typical performance curves for the TPS62065 67EVM Actual performance data can be affected by measurement techniques and environmental variables therefore these curves are presented for reference and may differ from actual results obtained by some users 6 1 Efficiency Figure 4 shows the typical efficiency performance for the TPS62065 and TPS62067 EFFICIENCY vs LOAD CURRENT 100 95 90 _ 85 go gt E 75 o E 70 H Viy 3 0V 65 H Vin 3 3V L 1 0 uH LQH441RO eo
19. nditions VIN 4 2 V Voy 3 3 V Figure 7 TPS62067 Shutdown No Load SLVUS64 March 2010 TPS62065 67EVM 9 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS TPS62065 67EVM Test Data www ti com 6 4 Output Voltage Ripple Power Save Mode Figure 8 and Figure 9 show the typical output voltage ripple for the TPS62065 in PFM and PWM modes respectively with the TPS62065EVM TYPICAL OUTPUT VOLTAGE RIPPLE PFM MODE T P T r r TT TU T T ee Vy 23 6V Igyp 20mA L 1 2 uH Vout Vou E 1 8V MODE GND Cour 10 uF 50 mV div m Pa Zn Sn y n SW 2 Vidiv Icoi 200 mA div Time 4 us div Figure 8 TPS62065 Output Voltage Ripple PFM Mode TYPICAL OUTPUT VOLTAGE RIPPLE PWM MODE v s our PALAAN etagining lainat i p M hue Vou Muri eint dude iA SII PN AES tini iiy leen 50 mV div f at i SW 2 Vidiv Feioiai ami pn en E leoi 500 dak Pia tain Mg ut Poe art mA div M att reas Vin 3 6V loyr 500 MA L 1 2 uH Vour 1 8 V MODE GND Coy 10 uF Time 100 ns div Figure 9 TPS62065 Output Voltage Ripple PWM Mode 10 TPS62065 67EVM SLVUS364 March 2010 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62065 67EVM Test Data 6 5 Control Loop Bode Diagrams TPS62065
20. oltage with a spectrum analyzer By default J27 is not assembled on the EVM 5 Test Configuration 5 1 Hardware Setup Figure 3 illustrates a typical hardware test configuration Oscilloscope ON EN OFF Load DC Power Supply TPS62065 67EVM 347 Figure 3 Hardware Board Connection 6 TPS62065 67EVM SLVUS364 March 2010 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com Test Configuration 5 2 Testing Procedure Follow these procedures when configuring the EVM for testing CAUTION Many of the components on the TPS62065 67EVM 347 are susceptible to damage by electrostatic discharge ESD Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM including the use of a grounded wrist strap bootstraps or mats at an approved ESD workstation An electrostatic smock and safety glasses should also be worn 1 Connect a dc power supply between J10 and J12 on the TPS62065EVM or J20 and J22 on the TPS62067EVM Please note that the input voltage should be between 3 0 V and 6 0 V Keep the wires from the input power supply to the EVM as short as possible and twisted 2 Connect a dc voltmeter or oscilloscope to the output sense connection of the EVM J14 on the TPS62065EVM J24 on the TPS62067EVM 3 A load can be connected between J13 and J15 on the TPS62065EVM or J23 a
21. ristics c eceeeeeeeeee ee ee neces eens eeeeee sees me mne nnne 2 2 TPS62065 67EVM Bill of Materials cceeee eee eee eee eee eee eee I I I m ne hne e nnn nene nnn nnns 18 All trademarks are the property of their respective owners SLVUS64 March 2010 TPS62065 67EVM 1 Submit Documentation Feedback Copyright O 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS Introduction www ti com 1 Introduction The TPS62065 67EVM 347 is a fully assembled and tested pair of PCBs for evaluating the TPS62065 and TPS62067 2 A step down converters The EVM comes configured with both a TPS62065 IC anda TPS62067 IC there are two PCBs one for each respective step down converter IC 1 1 Features Input voltage range 3 0 V to 6 0 V Adjustable output voltage 0 8 V to VIN Up to 2 0 A output current 3 MHz switching frequency Power Good output TPS62067EVM only Clock dithering 1 2 TPS62065 67 Applications The TPS62065 and TPS62067 step down converters are ideal for these applications POL Digital cameras PDAs pocket PCs Portable media players DSP supply 2 Electrical Performance Specifications Table 1 summarizes the TPS62065 67EVM performance specifications Table 1 TPS62065 67EVM Performance Characteristics Notes and Parameter Symbol Conditions Min Typ Max Units Input Characteristics Input Voltage VIN 3 0 6 0 V Inp
22. und in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assist
23. ut Undervoltage Lockout V Falling 1 73 1 78 1 83 V UVLO NV Rising 1 9 1 95 1 98 V Output Characteristics Line Regulation 0 9e N Load Regulation 0 5 SIA Output Current 1 lourt VIN 3 0 V to 6 0 V 2000 mA Forward Current Limit High Side and Low Side liue VIN 3 0 V to 6 0 V 2300 2750 3300 mA MOSFET Systems Characteristics Switching Frequency few 2600 3000 3400 kHz Peak Efficiency Npk VIN Nom 95 VIN 5 0 V VIN Full Load Efficiency n 1 8 V loy 2 000 82 mA 2 TPS62065 67EVM SLVU364 March 2010 Submit Documentation Feedback Copyright 2010 Texas Instruments Incorporated I TEXAS INSTRUMENTS www ti com TPS62056 67EVM Schematic 3 TPS62056 67EVM Schematic Figure 1 shows the TPS62065EVM schematic Figure 2 illustrates the TPS62067EVM schematic SPI L10 J16 2 A J10 TPS620650SG 1 8uH sb J13 VIN i VOU 2 2 2 9V to 6V E tere Jc mo leii c13 c14 a lout m iE i 22uF aig eur 22pF 10uF A al M 2 2 S LES M ON 120M WA WA Mi gt JS J12 EN J15 i JP10 i GND PWM ore cae GND Mone SUP WA Psm R12 WA 1 00M A Not Installed Vi Figure 1 TPS62065EVM Schematic J20 VIN 1 2 2 9V to 6V c2 J21 T iu f 22uF 1 GND 2 J26 cL NA PG 2 MA A Not Installed Figure 2 TPS62067EVM Schematic NO
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