Texas Instruments TPS54810 User's Manual
Contents
1. EFFICIENCY LOAD REGULATION LINE REGULATION vs vs vs OUTPUT CURRENT OUTPUT CURRENT INPUT VOLTAGE 1 003 1 001 Vi 5V Vi 5V NEEN Vo 18V Vo 1 8V 1 0008 ak Vo 18V fs 700 kHz 1 002 Ta 25 C 10006 TA 25 C z fs 700 kHz S fs 700 kHz 8 T 5 1 0004 S E a 3 H 1 0002 S 4 1 Ka kel S 0 9998 4A W fei d 0A 0 999 0 9996 Ge 0 9994 0 9992 0 997 0 999 0 2 4 6 8 10 0 2 4 6 8 10 45 47 49 51 53 55 57 59 lo Output Current A lo Output Current A Vi Input Voltage V Figure 12 Figure 13 Figure 14 AMBIENT TEMPERATURE vs OUTPUT CURRENT 1 OUTPUT RIPPLE VOLTAGE TRANSIENT RESPONSE 2 i Ty 25 C Miz BN ZS Miz BN e fs 700 kHz 3 Vos 1 8V E E lo 6A S 1 gt o g Va EN E amp r70kz i 2 3 E o ke 5 S d B E S i 6 E E E 3 k 2 ji E 5 2At06 5A i 9 o 0 1 2 3 4 5 6 7 8 t Time 1 us div t Time 20 us div lo Output Current A Figure 15 Figure 16 Figure 17 SLOW START TIMING Vi 5V 0 04 yr gt Slow start Cap reesen a AAT 1 Pi o Pd o F d gt be s 3 gt a Z L Ca eege E g x E 7 8 5 a 5 o 4 0 ms div Figure 18 1 Safe operating area is applicable to the test board conditions in the Dissipation Ratings 12 d TEXAS INSTRUMENTS www ti com DETAILED DESCRIPTION Under Voltage Lock Out UVLO The TPS54810 incorporates an under voltage lockout circu2. Input bias current VSENSE VSENSE Vref Output voltage slew rate symmetric COMP pr MM x 1 0 1 4 PWM COMPARATOR PWM comparator propagation delay time PWM comparator input to PH pin excluding dead 10 mV overdrive 1 time SLOW START ENABLE Emewenog SE 98 32 v Enable hysteresis votage SNA 9 v EE ERNEUT N 3 8 Charge current SS ENA SS ENA 0V POWER GOOD oe Power good hysteresis voltage 96Viet CURRENT LIMIT c output shorted 9 11 EEN Drettel THERMAL SHUTDOWN Thermal shutdown trip point P85 150 165 Thermal shutdown hysteresis 10 C OUTPUT POWER MOSFETS f Vi 6 VO 26 47 eran Power MOSFET switches Vi 45 VO 30 60 mo 1 Specified by design 2 Matched MOSFETs low side DS on Production tested high side rps on production tested A d Texas INSTRUMENTS TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 PWP PACKAGE TOP VIEW AGND 10 RT VSENSE 2 SYNC COMP 3 SS ENA PWRGD 4 VBIAS BOOT 5 VIN PH 6 VIN PH 7 THERMAL VIN PH 8 PAD VIN PH VIN PH PGND PH PGND PH PGND PH PGND PH PGND Terminal Functions TERMINAL NAME AGND Analog ground Return for compensation network output divider slow start capacitor VBIAS capacitor RT resistor and SYNC pin Connect PowerPAD to AGND Bootstrap input 0 022 uF to 0 1 uF low ESR capacitor connected from BOOT to PH generates floating drive for the high side FET d
3. A Figure 3 Figure 4 Figure 5 OUTPUT VOLTAGE REGULATION INTERNAL SLOW START TIME vs ERROR AMPLIFIER Vs INPUT VOLTAGE OPEN LOOP RESPONSE JUNCTION TEMPERATURE 140 0 3 80 RL 10 kQ 120 C 160 pF 20 3 85 TA 25 C 40 2 100 e 60 a 3 50 m 80 Phase 80 E 5 S 3 35 g 60 109 8 E 40 1208 8 3 20 e Gain 140 E 3 05 160 t 0 180 2 90 20 200 2 75 45 48 51 5 4 5 7 6 1 10 100 1k 10k 100k 1M 10M 40 0 25 85 125 Vi Input Voltage V f Frequency Hz Ty Junction Temperature C Figure 6 Figure 7 Figure 8 TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 d TEXAS INSTRUMENTS www ti com APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54810 application The TPS54810 U1 can provide up to 8 A of output current at a nominal output voltage of 1 8 V For proper thermal performance the PowerPAD underneath the integrated circuit TPS54810 needs to be soldered well to the printed circuit board Vi e e e C10 C12 U1 gt X10uF gt S10uF TPS54810PWP E RT R5 SYNC 10 kQ SS ENA VBIAS PWRGD s 65 p a R2 R3 e COMP e e e Vo 1000 pF 3010 VSENSE AGND C8 C7 CR e TET res esi t 0 047 uF R7 2 40 e Ci 3300 pF Analog and Power Grounds are Tied at the Pad Under the Package of IC Figure 9 Application Circuit COMPONENT SELECTION The values
4. 3 TEXAS INSTRUMENTS www ti com 6 4 mm X 9 7 mm TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 4 V TO 6 V INPUT 8 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETS SWIFT FEATURES 30 mQ MOSFET Switches for High Efficiency at 8 A Continuous Output 0 9 V to 3 3 V Adjustable Output Voltage Range With 1 Accuracy Externally Compensated Fast Transient Response Wide PWM Frequency Fixed 350 kHz 550 kHz or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS Low Voltage High Density Systems With Power Distributed at 5 V Point of Load Regulation for High Performance DSPs FPGAs ASICs and Microprocessors A PowerPAD and SWIFT are trademarks of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Broadband Networking and Optical Communications Infrastructure Portable Computing Notebook PCs SIMPLIFIED SCHEMATIC Input PH TPS54810 BOOT DESCRIPTION As a member of the SWIFT family of dc dc regulators the TPS54810 low input voltage high output current synchronous buck PWM converter integrates all
5. temperature exceeds 150 C The device is released from shutdown automatically when the junction temperature decreases to 10 C below the thermal shutdown trip point and starts up under control of the slow start circuit Thermal shutdown provides protection when an overload condition is sustained for several milliseconds With a persistent fault condition the device cycles continuously starting up by control of the soft start circuit heating up due to the fault condition and then shutting down upon reaching the thermal shutdown trip point This sequence repeats until the fault condition is removed Power Good PWRGD The power good circuit monitors for under voltage conditions on VSENSE If the voltage on VSENSE is 10 below the reference voltage the open drain PWRGD output is pulled low PWRGD is also pulled low if VIN is less than the UVLO threshold or SS ENA is low When VIN UVLO threshold SS ENA 2 enable threshold and VSENSE gt 90 of Viet the open drain output of the PWRGD pin is high A hysteresis voltage equal to 3 of Vref and a 35 us falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 5 Feb 2007 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Di Type Drawing Qty TPS54810PWP ACTIVE HTSSOP PWP 28 50 Green RoHS amp CU NIP
6. 0 1 uF to 1 0 uF ceramic capacitor VIN 20 24 Input supply for the power MOSFET switches and internal bias regulator Bypass VIN pins to PGND pins close to device package with a high quality low ESR 10 uF ceramic capacitor VSENSE 2 Error amplifier inverting input Connect to output voltage through compensation network output divider x TEXAS TPS54810 ipie eee SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 FUNCTIONAL BLOCK DIAGRAM Slow Start Internal Slow Start Time 3 35 ms Adaptive Dead Time and Control Logic Error Amplifier PWM Comparator Powergood Comparator ck r AGND VBIAS EE E EE E de VIN d Enable Comparator SIENA GE VBIAS REG Falling SHUTDOWN LT Fdge ILIM Tun Deglitch Thermal Comparator hd e 1 3 6V Hysteresis 0 03 V 2 5 us Shutdown Leading i Le ok 150 C Edge VIN UVLO Blanking Comparator Falling 100 ns and v v Rising l BOOT EI Ce mo Ee SHUTDOWN ec OUT Vi Internal External e 1 9 Falling Edge Deglitch TPS54810 RELATED DC DC PRODUCTS e TPS56300 dc dc controller PT6600 series 9 A plugin modules
7. 16 V Rising and falling edge deglitch UVLO 1 2 5 us BIAS VOLTAGE Output voltage VBIAS lvBIAS 0 2 70 2 80 2 90 V Output curent VBIAS CC C 00 9 CUMULATIVE REFERENCE ESCHER REGULATION IL 4A f 2350kHz Ty 85 C IL 4A f 2 550kHz Ty 85 C I_ OAto8A fs 350kHz Ty 85 C IL 0Ato8A fs 2 550kHz Ty 85 C Line regulation 3 Load regulation 3 OSCILLATOR SYNC lt 0 8V RT open SYNC 22 5 V RT open RT 180 kQ 1 resistor to AGND Externally set free running frequency range RT 100 kQ 1 resistor to AGND RT 68 kQ 1 resistor to AGND Internally set free running frequency range High level threshold SYNC Low level threshold SYNC Pulse duration external sychronization SYNC 1 Frequency range SYNC 1 Ramp valley 1 Ramp amplitude peak to peak 1 Minimum controllable on time Maximum duty cycle 1 1 Specified by design 2 Static resistive loads only 3 Specified by the circuit used in Figure 9 d TEXAS TPS54810 Ge SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS CONTINUED Ty 40 C to 125 C V 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kO COMP to AGND 90 110 dB Error amplifier unity gain bandwidth Parallel 10 kQ 160 pF COMP to AGND rLe ee common mode input voltage Powered by internal LDO VBIAS RM
8. tolerances between and around signal pads PowerPAD is a trademark of Texas Instruments 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask
9. work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal
10. 260 65 8x0 25 ET Im See Note E Y 2 35 g X L IIT RA 6 46 Example Solder Mask 26x0 65 Defined Pad 3 7 See Note C D over copper Example Non Soldermask Defined Pad Example Solder Mask Opening See Note F Center Power Pad Solder Stencil Opening omm 68 2 235 Y 6 il 1 99 NOO All Around Se Pa 4207609 13 E 10 07 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAQ02 SLMAO004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com Publication IPC 7351 is recommended for alternate designs E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Example stencil design based on a 50 volumetric metal load solder paste Refer to IPC 7525 for other stencil recommendations F Customers should contact their board fabrication site for solder mask
11. DAU Level 2 260C 1 YEAR no Sb Br TPS54810PWPG4 ACTIVE HTSSOP PWP 28 50 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br TPS54810PWPR ACTIVE HTSSOP PWP 28 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br TPS54810PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures
12. OWN A Thermal Pad See Note D i Gage Plane 4 4 Y Seating Plane L 1 20 MAX us f A 010 PINS DIM 4073225 H 12 05 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusions Mold flash and protrusion shall not exceed 0 15 per side D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com http www ti com gt E Falls within JEDEC MO 1535 PowerPAD is a trademark of Texas Instruments 3 TEXAS INSTRUMENTS www ti com d Texas THERMAL PAD MECHANICAL DATA INSTRUMENTS www ti com PWP R PDSO G28 THERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed t external heatsink The thermal pad must be soldered directly to the printed circu o be attached directly to an it board PCB After soldering the PCB can be used as a heatsink In addition thro
13. RT value for 85 nized frequency signal of external synchro nization frequency Error Amplifier The high performance wide bandwidth voltage error amplifier sets the TPS54810 apart from most dc dc converters The user is given the flexibility to use a wide range of output L and C filter components to suit the 13 TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 particular application needs Type 2 or type 3 compensa tion can be employed using external compensation components PWM Control Signals from the error amplifier output oscillator and current limit circuit are processed by the PWM control logic Referring to the internal block diagram the control logic includes the PWM comparator OR gate PWM latch and portions of the adaptive dead time and control logic block During steady state operation below the current limit threshold the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch Once the PWM latch is reset the low side FET remains on for a minimum duration set by the oscillator pulse width During this period the PWM ramp discharges rapidly to its valley voltage When the ramp begins to charge back up the low side FET turns off and high side FET turns on As the PWM ramp voltage exceeds the error amplifier output voltage the PWM comparator resets the latch thus turning off the high side FET and turning on the low side FET The low side FET remains on until the ne
14. TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event sh
15. The inductor is a low dc resistance 0 017 type Pulse Engineering PAO277 The capacitors used are 22 uF 6 3 V ceramic types with X5R dielectric The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz d TEXAS INSTRUMENTS www ti com PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54810 The VIN pins are connected together on the printed circuit board PCB and bypassed with a low ESR ceramic bypass capacitor Care should be taken to minimize the loop area formed by the bypass capacitor connections the VIN pins and the TPS54810 ground pins The minimum recommended bypass capacitance is 10 uF ceramic capacitor with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins The TPS54810 has two internal grounds analog and power Inside the TPS54810 the analog ground ties to all of the noise sensitive signals while the power ground ties to the noisier power signals Noise injected between the two grounds can degrade the performance of the TPS54810 particularly at higher output currents Ground noise on an analog ground plane can also cause problems with some of the control and bias signals For these reasons separate analog and power ground traces are recommended There is an area of ground on the top layer directly under the IC with an exposed area for connection to the PowerPAD Use vias to connect this ground area to any inte
16. all TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 11 Mar 2008 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS A Heel Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 mm BO mm KO mm P1 W Pin1 Type Drawing Diameter Width mm mm Quadrant mm W1 mm TPS54810PWPR HTSSOP PWP 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 Pack Materials Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 11 Mar 2008 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPS54810PWPR HTSSOP PWP 28 2000 346 0 346 0 33 0 Pack Materials Page 2 MECHANICAL DATA PWP R PDSO G PowerPAD PLASTIC SMALL OUTLINE PACKAGE 20 PIN SH
17. d TEXAS INSTRUMENTS www ti com Vo Output Voltage Regulation V f Externally Set Oscillator Frequency kHz 800 700 600 500 400 300 200 0 895 0 893 0 891 0 889 0 887 0 885 TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN SOURCE INTERNALLY SET ON STATE RESISTANCE OSCILLATOR FREQUENCY vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE N 750 e x E 1 2 g 9 5 650 o L 5 550 2 S S i 2 5 O 450 E 2 B B 350 o S S a 1 4 250 40 15 10 35 60 85 110 135 40 0 25 85 125 Ty Junction Temperature C Ty Junction Temperature C Figure 1 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY VOLTAGE REFERENCE DEVICE POWER LOSSES vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE LOAD CURRENT 0 895 Ty 125 C fs 700 kHz 7 0 893 z E 0 891 3 5 g z Fs EE S 0 889 amp S 2 1 3 5 a 0 887 0 885 40 0 25 85 125 40 0 25 85 125 0 1 2 3 4 5 6 7 8 Ty Junction Temperature C Ty Junction Temperature C lp Load Current
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19. for the components used in this design example were selected for low output ripple voltage and small PCB area Additional design information is available at www ti com INPUT FILTER The input voltage is a nominal 5 VDC The input filter C10 is a 10 uF ceramic capacitor Taiyo Yuden C12 also a 10 uF ceramic capacitor Taiyo Yuden provides high frequency decoupling of the TPS54810 from the input supply and must be located as close as possible to the device Ripple current is carried in both C10 and C12 and the return path to PGND should avoid the current circulating in the output capacitors C5 C7 and C8 FEEDBACK CIRCUIT The values for these components have been selected to provide low output ripple voltage The resistor divider network of R1 and R4 sets the output voltage for the circuit 8 at 1 8 V R1 along with R2 R3 C1 C2 and C4 forms the loop compensation network for the circuit For this design a Type 3 topology is used OPERATING FREQUENCY In the application circuit RT is grounded through a 71 5 kQ resistor to select the operating frequency of 700 kHz To set a different frequency place a 68 kQ to 180 kQ resistor between RT pin 28 and analog ground or leave RT floating to select the default of 350 kHz The resistance can be approximated using the following equation 500 kHz Switching Frequency X00 IR 1 OUTPUT FILTER The output filter is composed of a 0 65 uH inductor and 3 x 22 uF capacitor
20. g through the vias Eight vias should be in the PowerPAD area with four additional vias located under the device package The size of the vias under the package but not in the exposed thermal pad area can be increased to 0 018 Additional vias beyond the twelve recommended that enhance thermal performance should be included in areas not under the device package Minimum Recommended Thermal Vias 8 x 0 013 Diameter Inside 8PL 400 0130 4PL 90 0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance Y 0 0339 I 0 0650 y 0 3820 0 3478 0 0500 Powerpad Area 4 x 0 018 Diameter Under Device as Shown Additional 0 018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended lt 0 06 0 0150 0 2090 0 0256 Minimum Recommended Exposed r 0 1700 Pe 0 1340 Copper Area for Powerpad 5 mil Stencils May Require 10 Percent Larger Area 0 0630 0 0400 Figure 11 Recommended Land Pattern for the 28 Pin PWP PowerPAD 11 TEXAS TPS54810 eT SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 PERFORMANCE GRAPHS FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9
21. he MOSFET drivers The high side driver does not turn on until the voltage at the gate of the low side 14 d TEXAS INSTRUMENTS www ti com FET is below 2 V While the low side driver does not turn on until the voltage at the gate of the high side MOSFET is below 2 V The high side and low side drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates The low side driver is supplied from VIN while the high side drive is supplied from the BOOT pin A bootstrap circuit uses an external BOOT capacitor and an internal 2 5 Q bootstrap switch connected between the VIN and BOOT pins The integrated bootstrap switch improves drive efficiency and reduces external component count Overcurrent Protection The cycle by cycle current limiting is achieved by sensing the current flowing through the high side MOSFET and comparing this signal to a preset overcurrent threshold The high side MOSFET is turned off within 200 ns of reaching the current limit threshold A 100 ns leading edge blanking circuit prevents false tripping of the current limit when the high side switch is turning on Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter Load protection during current sink operation is provided by thermal shutdown Thermal Shutdown The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
22. injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non
23. it to keep the device disabled when the input voltage VIN is insufficient During power up internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 3 80 V Once the UVLO start threshold is reached device start up begins The device operates until VIN falls below the nominal UVLO stop threshold of 3 5 V Hysteresis in the UVLO comparator and a 2 5 us rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN Slow Start Enable SS ENA The slow start enable pin provides two functions First the pin acts as an enable shutdown control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1 2 V When SS ENA exceeds the enable threshold device start up begins The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0 891 V in 3 35 ms Similarly the converter output voltage reaches regulation in approximately 3 35 ms Voltage hysteresis and a 2 5 us falling edge deglitch circuit reduce the likelinood of triggering the enable due to noise The second function of the SS ENA pin provides an external means of extending the slow start time with a low value capacitor connected between SS ENA and AGND Adding a capacitor to the SS ENA pin has two effects on start up First a delay occurs between release of the SS ENA pin and start up of the output The delay is proportional to the
24. kage and the device pin out they must be routed close but maintain as much separation as possible while still Keeping the layout compact Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace If a slow start capacitor or RT resistor is used or if the SYNC pin is used to select 350 kHz operating frequency connect them to this trace TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 10 COMPENSA TION NETWORK BOOT CAPAGTORT Figure 10 PCB Layout Q VIAto Ground Plane da TEXAS INSTRUMENTS www ti com d TEXAS INSTRUMENTS www ti com LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current the analog ground plane must provide adequate heat dissipating area A 3 inch by 3 inch plane of 1 ounce copper is recommended though not mandatory depending on ambient temperature and airflow Most applications have larger areas of internal ground plane available and the PowerPAD should be connected to the largest area available Additional areas on the top or bottom layers also help dissipate heat and TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 any area available should be used when 8 A or greater operation is desired Connection from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0 013 inch diameter vias to avoid solder wickin
25. nductive foam during fy A storage or handling to prevent electrostatic damage to the MOS gates ORDERING INFORMATION Ta OUTPUT VOLTAGE PACKAGE PART NUMBER 40 C to 85 C 0 9 V to 3 3 V PLASTIC HTSSOP WE TPS54810PWP 1 The PWP package is also available taped and reeled Add an R suffix to the device type i e TPS54810PWPR See the application section of the data sheet for PowerPAD drawing and layout information 2 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI website at www ti com ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted TPS54810 UNIT VIN SS ENA SYNC 0 3107 RT 0 3 to 6 Inout voltage range V eeneg TY Y BOOT 0 3 to 17 VBIAS COMP PWRGD 0 3 t07 Output voltage range Vo Ty RSC V PH Internally Limited Source current lo COMP VBIAS 6 mA PH 12 A Sink current Ig COMP 6 A SS ENA PWRGD 10 m Voltage differential AGND to PGND 0 3 Operating virtual junction temperature range Ty 40 to 125 V 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affec
26. ng the output of a temperature stable bandgap circuit During manufacture the bandgap and scaling circuits are trimmed to produce 0 891 V at the output of the error amplifier with the amplifier connected as a voltage follower The trim procedure adds to the high precision regulation of the TPS54810 since it cancels offset errors in the scale and error amplifier circuits Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a static digital input If a different frequency of operation is required for the application the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor between the RT pin and AGND and floating the SYNC pin The switching frequency is approximated by the following equation where R is the resistance from RT to AGND 100 kQ R x 500 kHz 4 External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving a synchronization signal into SYNC and connecting a resistor from RT to AGND Choose an RT resistor which sets the free running frequency to 80 of the synchronization signal The following table summarizes the frequency selection configurations SWITCHING FRE SYNC PIN RT PIN QUENCY 350 kHz internally set Float or AGND Switching Frequency Externally set 280 kHz Float R 68 k to 180 k to 700 kHz Externally synchro Synchronization R
27. required active components Included on the substrate with the listed features are a true high performance voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components an under voltage lockout circuit to prevent start up until the input voltage reaches 3 8 V an internally or externally set slow start circuit to limit in rush currents and a power good output useful for processor logic reset fault signaling and supply sequencing The TPS54810 is available in a thermally enhanced 28 pin TSSOP PWP PowerPAD package which eliminates bulky heatsinks TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high performance power supply designs to meet aggressive equipment development cycles EFFICIENCY AT 700 HZ Efficiency 96 0 1 2 3 4 5 6 7 8 9 10 IL Load Current A Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Copyright 2002 Texas Instruments Incorporated TEXAS NSTRUMENTS TPS5481 0 www ti com SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 A These devices have limited built in ESD protection The leads should be shorted together or the device placed in co
28. river COMP 3 Error amplifier output Connect frequency compensation network from COMP to VSENSE 15 19 Power ground High current return for the low side driver and power MOSFET Connect PGND with large copper areas to the input and output supply returns and negative terminals of the input and output capacitors A single point connection to AGND is recommended pco Phase input output Junction of the internal high side and low side power MOSFETS and output inductor PWRGD Power good open drain output High Z when VSENSE 9096 Vier otherwise PWRGD is low Note that output is low when SS ENA is low or the internal shutdown signal is active DESCRIPTION Frequency setting resistor input Connect a resistor from RT to AGND to set the switching frequency When using the SYNC pin set the RT value for a frequency at or slightly lower than the external oscillator frequency SS ENA Slow start enable input output Dual function pin which provides logic input to enable disable device operation and capacitor input to externally set the start up time Synchronization input Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies When used to synchronize to an external signal a resistor must be connected to the RT pin Internal bias regulator output Supplies regulated voltage to internal circuitry Bypass VBIAS pin to AGND pin with a high quality low ESR
29. rnal ground planes Additional vias are also used at the ground side of the input and output filter capacitors The AGND and PGND pins are tied to the PCB ground by connecting them to the ground area under the device as shown The only components that tie directly to the power ground plane are the input capacitors the output TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 capacitors the input voltage decoupling capacitor and the PGND pins of the TPS54810 Use a separate wide trace for the analog ground signal path The analog ground is used for the voltage set point divider timing resistor RT slow start capacitor and bias capacitor grounds Connect this trace directly to AGND Pin 1 The PH pins are tied together and routed to the output inductor Since the PH connection is the switching node the inductor is located close to the PH pins The area of the PCB conductor is minimized to prevent excessive capacitive coupling Connect the boot capacitor between the phase node and the BOOT pin as shown Keep the boot capacitor close to the IC and minimize the conductor trace lengths Connect the output filter capacitor s as shown between the VOUT trace and PGND It is important to keep the loop formed by the PH pins Lour Cour and PGND as small as practical Place the compensation components from the VOUT trace to the VSENSE and COMP pins Do not place these components too close to the PH trace Due to the size of the IC pac
30. slow start capacitor value and lasts until the SS ENA pin reaches the enable threshold The start up delay is approximately 1 2 V Css i 5 uA 2 t d Second as the output becomes active a brief ramp up at the internal slow start rate may be observed before the externally set slow start rate takes control and the output rises at a rate proportional to the slow start capacitor The ramp up time set by the capacitor is approximately 0 7 V tg iS 5 ux e The actual ramp up time is likely to be less than the above approximation due to the brief ramp up at the internal rate VBIAS Regulator VBIAS The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage A high quality TPS54810 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 low ESR ceramic bypass capacitor is required on the VBIAS pin X7R or X5H grade dielectrics are recommended because their values are more stable over temperature The bypass capacitor should be placed close to the VBIAS pin and returned to AGND External loading on VBIAS is allowed with the caution that internal circuits require a minimum VBIAS of 2 70 V and external loads on VBIAS with ac or digital switching noise may degrade performance The VBIAS pin may be useful as a reference voltage for external circuits Voltage Reference The voltage reference system produces a precise Vier signal by scali
31. t device reliability RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Operating junction temperature T 40 125 DISSIPATION RATINGS 2 PACKAGE THERMAL IMPEDANCE Ta lt 25 C Ta 70 C Ty 85 C JUNCTION TO AMBIENT POWER RATING POWER RATING POWER RATING 28 Pin PWP with solder 18 2 C W 5 49 W2 3 02 W 2 20 W 28 Pin PWP without solder 40 5 C W 2 48 W 1 36 W 0 99 W 1 For more information on the PWP package refer to TI technical brief literature number SLMAOO02 2 Test Board Conditions 1 9 x 3 4 layers thickness 0 062 2 1 5 oz copper traces located on the top of the PCB 3 1 5 oz copper ground plane on the bottom of the PCB 4 0 5 oz copper ground planes on the 2 internal layers 5 12 thermal vias see Recommended Land Pattern in applications section of this data sheet 3 Maximum power dissipation may be limited by over current protection 2 x TEXAS NSTRUMENTS www ti com TPS5481 0 SLVS420B MARCH 2002 R EVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS Ty 40 C to 125 C V 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE VIN Input voltage range VIN PH pin open lQ Quiescent current fs 550 kHz SYNC 2 2 5 V RT open mA 16 23 5 PH pin open 4 Shutdown SENA OV UNDER VOLTAGE LOCK OUT V fs 350 kHz SYNC x 0 8 V RT open T 158 Stop threshold voltage UVLO 3 40 3 50 Hysteresis voltage UVLO 0 14 0
32. ugh the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This desi from the integrated circuit IC gn optimizes the heat transfer For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMAO02 and Application Brief PowerPAD Made Easy Texas Instruments Litera Both documents are available at www ti com ure No SLMAOO04 The exposed thermal pad dimensions for this package are shown in the following illustration 28 15 Exposed Thermal Pad 6 46 5 35 Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206332 14 H 10 07 LAND PATTERN PWP R PDSO G28 PowerPAD Example Board Layout Stencil Openings Via pattern and copper pad size Based on a stencil thickness may vary depending on layout constraints of 127mm 005inch Reference table below for other Increasing copper area will solder stencil thicknesses enhance thermal performance See Note D 7
33. xt oscillator pulse discharges the PWM ramp During transient conditions the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage If the error amplifier is high the PWM latch is never reset and the high side FET remains on until the oscillator pulse signals the control logic to turn the high side FET off and the low side FET on The device operates at its maximum duty cycle until the output voltage rises to the regulation set point setting VSENSE to approximately the same voltage as VREF If the error amplifier output is low the PWM latch is continually reset and the high side FET does not turn on The low side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states The TPS54810 is capable of sinking current continuously until the output reaches the regulation set point If the current limit comparator trips for longer than 100 ns the PWM latch resets before the PWM ramp exceeds the error amplifier output The high side FET turns off and low side FET turns on to decrease the energy in the output inductor and consequently the output current This process is repeated each cycle in which the current limit comparator is tripped Dead Time Control and MOSFET Drivers Adaptive dead time control prevents shoot through current from flowing in both N channel power MOSFETs during the switching transitions by actively controlling the turnon times of t
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