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Texas Instruments TMS320DM355 User's Manual

1. Address Accessibility UART1 0x01C2 0400 0x01C2 07FF 1K V Timer4 5 0x01C2 0800 0x01C2 OBFF 1K V V Real time out 0x01C2 0C00 0x01C2 OFFF 1K V V 12C 0x01C2 1000 0x01C2 13FF 1K v V Timer0 1 0x01C2 1400 0x01C2 17FF 1K Vy V Timer2 3 0x01C2 1800 0x01C2 1BFF 1K V V WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K V V PWMO 0x01C2 2000 0x01C2 23FF 1K V PWM1 0x01C2 2400 0x01C2 27FF 1K V PWM2 0x01C2 2800 0x01C2 2BFF 1K V V PWM3 0x01C2 2C00 0x01C2 2FFF 1K V V System Module 0x01C4 0000 0x01C4 07FF 2K V V PLL Controller 0 0x01C4 0800 0x01C4 OBFF 1K V V PLL Controller 1 0x01C4 0C00 0x01C4 OFFF 1K V V Power Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K V V ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K V V USB OTG 2 0 Regs RAM 0x01C6 4000 0x01C6 5FFF 8K V SPIO 0x01C6 6000 0x01C6 67FF 2K V V SPI1 0x01C6 6800 0x01C6 6FFF 2K Vy V GPIO 0x01C6 7000 0x01C6 77FF 2K V SPI2 0x01C6 7800 0x01C6 FFFF 2K V V VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K V V VPSS Clock Control 0x01C7 0000 0x01C7 007F 128 V V Hardware 3A 0x01C7 0080 0x01C7 00FF 128 V V Image Pipe IPIPE Interface 0x01C7 0100 0x01C7 01FF 256 V V On Screen Display 0x01C7 0200 0x01C7 02FF 256 V V High Speed Serial IF 0x01C7 0300 0x01C7 03FF 256 V V Video Encoder 0x01C7 0400 0x01C7 05FF 512 V V CCD Controller 0x01C7 0600 0x01C7 07FF 256 V V VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 v V Reserved 0x01C7 0900 0x01C7 09FF 256 V V Image Pipe IPIPE 0x0
2. INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 10 DDR Terminal Functions continued Me TYPE OTHER O DESCRIPTION NAME NO DDR_A10 V6 VO Z VDD_DDR DDR Address Bus bit 10 DDR_A09 W6 VO Z VDD_DDR DDR Address Bus bit 09 DDR_A08 w5 VO Z VDD_DDR DDR Address Bus bit 08 DDR_A07 V5 VO Z VDD_DDR DDR Address Bus bit 07 DDR_A06 U5 VO Z VDD_DDR DDR Address Bus bit 06 DDR_A05 W4 VO Z VDD_DDR DDR Address Bus bit 05 DDR_A04 V4 VO Z VDD_DDR DDR Address Bus bit 04 DDR_A03 W3 VO Z VDD_DDR DDR Address Bus bit 03 DDR_A02 W2 VO Z VDD_DDR DDR Address Bus bit 02 DDR_A01 V3 VO Z VDD_DDR DDR Address Bus bit 01 DDR_A00 V2 VO Z VDD_DDR DDR Address Bus bit 00 DDR_DQ15 W17 VO Z Von opp DDR Data Bus bit 15 DDR_DQ14 V16 VO Z VDD_DDR DDR Data Bus bit 14 DDR_DQ13 W16 VO Z Von opp DDR Data Bus bit 13 DDR_DQ12 U16 VO Z VDD_DDR DDR Data Bus bit 12 DDR_DQ11 W15 VO Z Von opp DDR Data Bus bit 11 DDR_DQ10 W14 VO Z VDD_DDR DDR Data Bus bit 10 DDR_DQ09 V14 VO Z Von opp DDR Data Bus bit 09 DDR_DQ08 U13 VO Z VDD_DDR DDR Data Bus bit 08 DDR_DQ07 W13 VO Z VDD_DDR DDR Data Bus bit 07 DDR_DQ06 V13 VO Z VDD_DDR DDR Data Bus bit 06 DDR_DQ05 W12 VO Z VDD_DDR DDR Data Bus bit 05 DDR_DQ04 U12 VO Z VDD_DDR DDR Data Bus bit 04 DDR_DQ03 T11 VO Z VDD_DDR DDR Data Bus bit 03 DDR_DQ02 U11 VO Z VDD_DDR DDR Data Bus bit 02 DDR_DQ01 W11 VO Z Von opp DDR Data Bus bit 01 DDR_DQ00 V
3. NO DM355 UNIT MIN TYP MAX 1 teat Cycle time MXI1 CLKIN1 27 79 41 56 ns 2 tw MXI1H Pulse duration MXI1 CLKIN1 high 0 45C 0 55C ns 3 twmxnL Pulse duration MXI1 CLKIN1 low 0 45C 0 55C ns 4 ben Transition time MXI1 CLKIN1 0 05C ns D Gen Period jitter MXI1 CLKIN1 0 02C ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and Vum MIN 2 C MXI1 CLKIN1 cycle time in ns For example when MXI1 CLKIN1 frequency is 24 MHz use C 41 6 ns 3 te MXI1 41 6 ns and tc MXI1 27 7 ns are the only supported cycle times for MXI1 CLKIN1 5 gt Ie 1 gt 4 H k 2 a oe k 3 aol le Figure 5 7 MXI1 CLKIN1 Timing Table 5 6 Timing Requirements for MXI2 CLKIN2 see Figure 5 7 NO DM355 UNIT MIN TYP MAX 1 Laus Cycle time MXI2 CLKIN2 37 037 37 037 ns 2 twoxi2H Pulse duration MXI2 CLKIN2 high 0 45C 0 55C ns 3 twMXI2L Pulse duration MXI2 CLKIN2 low 0 45C 0 55C ns 4 bas Transition time MXI2 CLKIN2 0 05C ns D Une Period jitter MXI2 CLKIN2 0 02C ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and Vu MIN SC 2 C MXI2 CLKIN2 cycle time in ns For example when MXI2 CLKIN2 frequency is 27 MHz use C 37 037 ns 3 tc MXI2 37 037 ns is the only supported cycle time for MXI2 CLKIN2 5 j Le 1 gt i 8 k 2 S ce aaa Lem DE em D emm D emm D em E k
4. NO DM355 iin MIN MAX 1 to PCLK Cycle time PCLK 13 33 160 ns 2 tw PCLKH Pulse duration PCLK high 5 7 ns 3 tw PCLKL Pulse duration PCLK low 5 7 ns 4 tyPcLk Transition time PCLK 3 ns 5 te EXTCLK Cycle time EXTCLK 13 33 160 ns 6 tw EXTCLKH Pulse duration EXTCLK high 57 ns 7 tw EXTCLKL Pulse duration EXTCLK low 5 7 ns 8 tyEXTCLK Transition time EXTCLK 3 ns 1 When the CCDC is used the PCLK frequency must be less than or equal to half the VPSS clock frequency i e PCLK lt SYSCLK4 2 es WR 2 gt r 1 H ek NX NA NN al le 4 4 SS ee Ee gt les al eg Figure 5 27 VPBE PCLK and EXTCLK Timing Table 5 22 Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK 203 see Figure 5 28 DM355 NO UNIT MIN MAX 9 tsu VCTLV VCLKIN Setup time VCTL valid before VCLKIN edge 2 ns 10 th VCLKIN VCTLV Hold time VCTL valid after VCLKIN edge 1 ns 1 The VPBE may be configured to operate in either positive or negative edge clocking mode When in positive edge clocking mode the rising edge of VCLKIN is referenced When in negative edge clocking mode the falling edge of VCLKIN is referenced 2 VCTL HSYNC VSYNC and FIELD 3 VCLKIN PCLK or EXTCLK 122 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www
5. 3 5 3 1 2 DM355 270 PLL2 24 MHz reference All supported clocking configurations for DM355 270 PLL2 with 24 MHz reference clock are shown in Table 3 3 Table 3 7 PLL2 Supported Clocking Configurations for DM355 270 24 MHz reference PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock n programmable m 1 fixed MHz PLLDIV1 SYSCLK1 DDR_CLK programmable 1 fixed MHz MHz bypass bypass bypass bypass 1 24 12 8 144 1 432 1 432 216 8 138 1 414 1 414 207 8 132 1 396 1 396 198 8 126 1 378 1 378 189 8 120 1 360 1 360 180 8 114 1 342 1 342 171 Submit Documentation Feedback Detailed Device Description 69 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 7 PLL2 Supported Clocking Configurations for DM355 270 24 MHz reference continued PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock 8 108 1 324 1 324 162 8 102 1 306 1 306 153 8 96 1 288 1 288 144 12 133 1 266 1 266 133 12 100 1 200 1 200 100 15 100 1 160 1 160 80 3 5 3 2 Supported Clocking Configurations for DM355 270 36 MHz reference 3 5 3 2 1 DM355 270 PLL1 36 MHz reference All supported clocking configurations for DM355 270 PLL1 with 36 MHz reference clock are shown in Table 3 4 Table 3 8 PLL1 Supported Clocking
6. MASTER NO UNIT MIN MAX M30 tsu DRV CKXL Setup time DR valid before CLKX low 11 ns M31 th CKXL DRV Hold time DR valid after CLKX low 0 ns Table 5 38 ASP as SPI Switching Characteristics CLKSTP 10b CLKXP 0 see Figure 5 42 MASTER NO PARAMETER UNIT MIN MAX M33__ te CKX Cycle time CLKX Bae ns M24 tackxL FXH Delay time CLKX low to FSX high T 2 T 3 ns M25 taexL cKxH Delay time FSX low to CLKX high Cc 2 C 2 ns M26 ta CkKXH DXV Delay time CLKX high to DX valid 2 6 ns M27 tdis CKXL DXHZ Disable time DX high impedance following last data bit from CLKX low C 3 C 3 ns 1 P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 2 T BCLKX period 1 CLKGDV x 2P C BCLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 x 2P when CLKGDV is even Use which ever value is greater 4 FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX CLKX i f V f k 24 mas e m33 gt L May of je M26 DX ___ Bito L Bit n 1 X m AC m AC n 4 X M a0 k M31 DR _ Bito L Bit n 1 A m AV n 3 X m X Figure 5 42 ASP as SPI CLKSTP 10b CLKXP 0 140 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Ch
7. INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 10 11 12 13 14 15 16 17 18 19 DDOR WE DDR_DQ01 DDR_DQ05 DDR_DQ07 DDR_DQ10 DDR_DA11 DDR_DQ13 DDR_DQ15 DDR_GATEO CVpp w DDR_CKE DDR_DQ00 DDR_DQS 0 DDR_DQ06 DDR_DQ09 DDR_DQS 1 DDR_DQ14 DDR_GATE1 Vss EM_A13 v DDR_VREF DDR_DQ02 DDR_DQ04 DDR_DQ08 Vss DDR_DQM 1 DDR_DQ12 Vss UARTO_RXD EM_A12 U DDR_DQ03 DDR_DQM 0 Vpp_ppR Vss CVpp UARTO_TXD EM_A08 T Vppa33_DDRDLL Vegan DU Vop opp 12C_SDA DC SCL UART1_RXD EM_A11 UART1_TXD EM_A10 EM_A05 R Von opp Vop opp Von op Von pop Von opp EM_A04 EM_A07 EM_A09 EM_A06 EM_BA1 P Von Von Vss EM_A02 EM A0 EM_A03 EM_BAO N Von Von Von Von Vss EM_D13 EM AO0 Vss EM_D15 EM_D14 M Vss CVpp CVpp Von Vss EM_D04 EM DO EM Di EM_D12 EM_D10 L Vss CVpp CVpp Vss Von EM DOG EM DO9 EM DO K Figure 2 3 Pin Map Quadrant C Submit Documentation Feedback Device Overview 11 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Vss CVpp CVpp CVpp Vss EM_WE EM CEO EM DO B EM DOS J Con Vss Vssa_PLL1 CVpp Vss ASP0_DX EM_ADV CVpp EM_D00 EM_D02 H CVpp VDDA PLL1 Vpp G10003 ASPO_FSX EM WAIT EM_cE1 Io Von Von Von Von Von Gl0002 ASPO_
8. PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock n programmable m 1 fixed MHz PLLDIV1 SYSCLK1 DDR_CLK programmable 1 fixed MHz MHz bypass bypass bypass bypass 1 36 18 12 144 1 432 1 432 216 12 138 1 414 1 414 207 12 132 1 396 1 396 198 12 126 1 378 1 378 189 12 120 1 360 1 360 180 12 114 1 342 1 342 171 12 108 1 324 1 324 162 12 102 1 306 1 306 153 12 96 1 288 1 288 144 18 133 1 266 1 266 133 27 150 1 200 1 200 100 27 120 1 160 1 160 80 3 5 4 Peripheral Clocking Considerations 3 5 4 1 Video Processing Back End Clocking The Video Processing Back End VPBE is a sub module of the VPSS Video Processing Subsystem The VPBE is designed to interface with a variety of LCDs and an internal DAC module There are two asynchronous clock domains in the VPBE an internal clock domain and an external clock domain The internal clock domain is driven by the VPSS clock PLL1 SYSCLK4 The external clock domain is configurable you can select one of five source e 24 MHz crystal input at MAI e 27 MHz crystal input at MXI2 optional feature not typically used e PLL1 SYSCLK3 e EXTCLK pin external VPBE clock input pin e PCLK pin VPFE pixel clock input pin See the TMS320DM355 DMSoC Video Processing Back End VPBE User s Guide for complete information on VPBE clocking 3 5 4 2 USB Clocking The USB Controller is driven by two clocks an output clock of PLL1 SYSCLK2 and an output clock of the
9. DM355 NO UNIT MIN MAX 1 tw GPIH Pulse duration GPIx high 52 ns 2 tw GPIL Pulse duration GPIx low 52 ns Table 5 11 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs see Figure 5 12 DM355 NO PARAMETER UNIT MIN MAX 3 twiGPoH Pulse duration GPOx high 26 ns 4 twiGPOL Pulse duration GPOx low 26 ns 1 This parameter value should not be used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity 104 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 ebe GP Aa ge k3 GPOx f f Figure 5 12 GPIO Port Timing 5 6 2 GPIO Peripheral External Interrupts Electrical Data Timing Table 5 12 Timing Requirements for External Interrupts EDMA Events see Figure 5 13 DM355 NO UNIT MIN MAX tw ILOw Width of the external interrupt pulse low 52 ns 2 twIHIGH Width of the external interrupt pulse high 52 ns 1 The pulse width given is sufficient to generate an interrupt or an EDMA event However if a user wants to have to recognize the GPIO changes through software polling of the GPIO register the GPIO duration must be extended to allow enough time to access
10. 3 11 4 ARM Boot Mode Configuration The input pins BTSEL 1 0 determine whether the ARM will boot from its ROM or from the Asynchronous EMIF AEMIF When ROM boot is selected BTSEL 1 0 00 10 or 11 a jump to the start of internal ROM address 0x0000 8000 is forced into the first fetched instruction word The embedded ROM boot loader code RBL then performs certain configuration steps reads the BOOTCFG register to determine the desired boot method and branches to the appropriate boot routine i e a NAND MMC SD or UART loader routine If AEMIF boot is selected BTSEL 1 0 01 a jump to the start of AEMIF address 0x0200 0000 is forced into the first fetched instruction word The ARM then continues executing from external asynchronous memory using the default AEMIF timings until modified by software NOTE For AEMIF boot the OneNAND must be connected to the first AEMIF chip select space EM_CEO0 Also the AEMIF does not support direct execution from NAND Flash Boot modes are further described in Section 3 12 3 11 5 AEMIF Configuration 3 11 5 1 AEMIF Pin Configuration The input pins AECFG 3 0 determine the AEMIF configuration immediately after reset Use AECFG 3 0 to properly configure the pins of the AEMIF Refer to the section on pin multiplexing in Section 3 9 Also see the Asynchronous External Memory Interface AEMIF Peripheral Reference Guide SPRUEE8 for more information on the AEMIF 3 11
11. RTO0 1 2 3 2 NSA N 3 t gt 3 Figure 5 49 RTO Output Timing TINT12 TINT34 Timer3 k 4 gt pro INVALID X_N VALID 4 4 gt pro INVALID CU ks 4 gt RTO INVALID T Oo VALID w 4 gt RTOS maD X VALID Figure 5 50 RTO Output Delay Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 147 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 18 www ti com IEEE 1149 1 JTAG The JTAG interface is used for BSDL testing and emulation of the device The device requires that both TRST and RESET be asserted upon power up to be properly initialized While RESET initializes the device TRST initializes the device s emulation logic Both resets are required for proper operation While both TRST and RESET need to be asserted upon power up only RESET needs to be released for the device to boot properly TRST may be asserted indefinitely for normal operation keeping the JTAG port interface and device s emulation logic in the reset state TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device s boundary scan functionality Note TRST is synchronous and must be clocked by TCK otherwise the boundary scan logic may not respond as expected after TRST is asserted RES
12. DDR2 and mDDR SDRAM 16 bit wide EMIF With 256 MByte Address Space 1 8 V I O Asynchronous16 8 bit Wide EMIF AEMIF e Flash Memory Interfaces NAND 8 16 bit Wide Data OneNAND 16 bit Wide Data Flash Card Interfaces Two Multimedia Card MMC Secure Digital SD SDIO SmartMedia Enhanced Direct Memory Access EDMA Controller 64 Independent Channels USB Port with Integrated 2 0 High Speed PHY that Supports USB 2 0 Full and High Speed Device USB 2 0 Low Full and High Speed Host Three 64 Bit General Purpose Timers each configurable as two 32 bit timers One 64 Bit Watch Dog Timer Three UARTs One fast UART with RTS and CTS Flow Conirol Three Serial Port Interfaces SPI each with two Chip Selects One Master Slave Inter Integrated Circuit CH Bus Two Audio Serial Port ASP 12S and TDM 12S AC97 Audio Codec Interface S PDIF via Software Standard Voice Codec Interface AIC12 SPI Protocol Master Mode Only Four Pulse Width Modulator PWM Outputs Four RTO Real Time Out Outputs Up to 104 General Purpose I O GPIO Pins Multiplexed with Other Device Functions On Chip ARM ROM Bootloader RBL to Boot From NAND Flash MMC SD or UART Configurable Power Saving Modes Crystal or External Clock Input typically 24 MHz or 36 MHz Flexible PLL Clock Generators Debug Interface Support Please be aware that an important notice concerning availability standard warranty an
13. Delay time SPI_EN 1 0 output falling edge to first SPI_CLK output rising or falling 2P 0 me edge 10 taENL CLKH L P 5C i 2 11 ta CLKH L ENH Delay time SPI_CLK output rising or falling edge to SPI_EN 1 0 output rising edge ns 1 The delay time can be adjusted using the SPI module register C2TDELAY See the TMS320DM355 DMSoC Serial Peripheral Interface SPI User s Guide SPRUED4 2 The delay time can be adjusted using the SPI module register T2CDELAY See the TMS320DM355 DMSoC Serial Peripheral Interface SPI User s Guide SPRUED4 jt 11 gt SPI_EN A SPI_CLK d d d Clock Polarity 0 A W0 SPI_CLK Clock Polarity 1 lt gt 6 gt 7 A 4 gt 5 A Ce oam E GE Output MSB OUT LSB OUT Figure 5 37 SPI Master Mode External Timing Clock Phase 0 132 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 d TEXAS INSTRUMENTS www ti com SPI Master Mode Timings Clock Phase 1 Table 5 31 Timing Requirements for SPI Master Mode Clock Phase 1 see Figure 5 38 DM355 NO UNIT MIN MAX 13 tsu DIV CLKL peas SPI_DI input valid before SPI_CLK output Clock Polarity 0 5P 3 ns Setup time SPI_DI i t valid before SPI_CLK output e 14 tsu DI
14. LSB 0 Example for External Circuit A Connect IOUT to a high impedance video buffer device Place capacitors and resistors as close as possible to the DM355 C Configure the VDAC_CONFIG register in the system control module as follows DINV 0 PWD_GBZ 1 PWD_VBUFZ 0 ACCUP_EN X See theTMS320DM355 ARM Subsystem Reference Guide and the TMS320DM355 DMSoC Video Processing Back End VPBE User s Guide for more information on VDAC_CONFIG D Figure 5 31 DAC Only Application Example Submit Documentation Feedback Peripheral Information and Electrical Specifications 125 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Video DAC and Buffer BE IBIAS IOUT VFB Cge RBIas T 0 1 pF 2550 Q AWV WV Rip 1000 Q Rout 1070 Q DAC Digital Input DIN lt 9 0 gt TVOUT EE TV monitor Video Buffer Output Voltage TVOUT V A A IMSSB cca SE IT Mou ben LSBL Moama ol ee A Place capacitors and resistors as close as possible to the DM355 B You must use the circuit shown in this diagram Also you must configure the VDAC_CONFIG register in the System Control module as follows TRESB4R4 0x3 TRESB4R2 0x8 TRESB4R1 0x8 TRIMBITS 0x34 PWD_BGZ 1 power up VREF SPEED 1 faster TVINT don t care PWD_VBUFZ 1 power up video buffer VREFSET don t car
15. 104 5 7 External Memory Interface EMIF seseeeees 106 5 8 MMO SD cece cece cece ee eee e eee eeeeeeeeee 113 5 9 Video Processing Sub System VPSS Overview 115 510 US 127 5 11 Universal Asynchronous Receiver Transmitter UART E 129 5 12 Serial Port Interface Pl EE KEEN 5 13 Inter Integrated Circuit I2C eessen 134 5 14 Audio Serial Port AG EE 137 5 45 Min TE 144 5 16 Pulse Width Modulator PWM 0seeeeeeeeeees 145 5 17 Real Time Out RTO ccceeeeeeeeeeeeeeeeeeees 147 5 18 IEEE 1149 1 JTAG EE 148 Revision History EN 151 Mechanical Data 153 7 1 Thermal Data for ZCE e 153 7 1 1 Packaging Information 153 Contents 5 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 2 Device Overview 2 1 Device Characteristics da TEXAS INSTRUMENTS www ti com Table 2 1 provides an overview of the DMSoC The table shows significant features of the device including the peripherals capacity of on chip RAM ARM operating frequency the package type with pin count etc Table 2 1 Characteristics of the Processor HARDWARE FEATURES DM355 DDR2 mDDR Memory Controller DDR2 mDDR 16 bit bus width Asynchronous 8 16 bit bus width Asynchronous EMIF AEMIF RAM Flash NAND OneNAND Two MMC SD Flash Card Interfaces One SmartMedia xD 64 independent DMA channels EDMA Eight EDMA channels
16. 5 3 1 1 Power Supply Design Considerations Core and I O supply voltage regulators should be located close to the DM355 to minimize inductance and resistance in the power delivery path Additionally when designing for high performance applications utilizing the device the PC board should include separate power planes for core I O and ground all bypassed with high quality low ESL ESR capacitors 5 3 1 2 Power Supply Decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to These caps need to be close to the power pins no more than 1 25 cm maximum distance to be effective Physically smaller caps such as 0402 are better because of their lower parasitic inductance Proper capacitance values are also important Small bypass caps near 560 pF should be closest to the power pins Medium bypass caps 220 nF or as large as can be obtained in a small package should be next closest Tl recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias using the interior BGA space and at least the corners of the exterior Larger caps for each supply can be placed further away for bulk decoupling Large bulk caps on the order of 100 uF should be furthest away but still as close as possible Large caps for each supply should be placed outside of the BGA footprint Any cap selection needs to be evaluated from a yield manufacturing p
17. EM_A13 Async EMIF Address bus bit 13 GI0067 vig uo e GIO GIO 067 BTSEL 1 Von System BTSEL 1 0 sampled at power on reset to determine boot method Used to drive boot status LED signal active low in ROM boot modes EM_A12 PD Async EMIF Address bus bit 12 GIO066 U19 VO Z V GIO GIO 066 BTSEL 0 DD System BTSEL 1 0 sampled at power on reset to determine boot method Async EMIF Address bus bit 11 EM_A11 PU GIO GIO 065 GIO065 R16 VO Z V System AECFG 3 0 sampled a power on reset to set AEMIF configuration AECFG 3 DD AECFG 3 sets default fo PinMux2 EM_D15_8 AEMIF default bus width 16 or 8 bits Async EMIF Address bus bit 10 EM_A10 PU GIO GIO 064 GIO064 R18 VO Z V System AECFG 3 0 sampled a power on reset to set AEMIF configuration AECFG 2 DE AECFG 2 1 sets default fo PinMux2 EM_BAO AEMIF EM BAO definition EM BAO EM_A14 GOP 054 rsvd Async EMIF Address bus bit 09 EM_A09 PD GIO GIO 063 GIO063 P17 VO Z V System AECFG 3 0 sampled a power on reset to set AEMIF configuration AECFG 1 DD AECFG 2 1 sets default fo PinMux2 EM_BAO AEMIF EM BAO definition EM _BA0 EM_A14 GOP 054 rsvd SBS 34 Device Overview l Input O Output Z High impedance S Supply voltage GND Ground A Analog signal Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail PD pull down PU pull up To pull up a signal to the oppos
18. OTHER 3 DESCRIPTION BEE F17 VO Z V ASPO Receive Clock Glo026 DD GIO GIO 026 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback Device Overview 29 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 14 ASP Terminal Functions continued da TEXAS INSTRUMENTS www ti com TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO ER F18 O Z Vbo ASPO Transmit Clock Glo029 GIO GIO 029 ee E18 VOIZ Was ASPO Receive DataF GIO027 GIO GIO 027 jae H15 VO Z Von ASPO Transmit Data GI0030 GIO GIO 030 ASP0_FS ASPO Receive Frame Synch R F16 VO Z Von GIO GIO 025 GI0025 ASPO_FS X G17 VO Z Vop ASPO Transmit Frame SynchGIlO GIO 028 Gl0028 or D18 Oz Was ASP1 Receive Clock oe D17 VZ Vbo ASP1 Master Clock ER D19 Volz Van ASP1 Transmit Clock ASP1_DR C19 VO Z Vpop ASP1 Receive Data ASP1_DX C18 VO Z Vpp ASP1 Transmit Data SE E17 Oz Vou ASP1 Receive Frame Synch oe E16 Volz Vp ASP1 Transmit Frame Sync 2 4 9 UART Interface T
19. PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID UI Supply PD State COUT5 G2 C1 UO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 5 4 COU GIO079 GIO function T5 PWM2A RTOO PWM2 RTO GIO GIO 079 PWM2A RTOO COUT4 B7 D3 VO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 7 6 COU GIO078 GIO function T_4 PWM2B RTO1 PWM2 RTO GIO GIO 078 PWM2B RTO1 4 COUT3 B6 E3 VO NENG Vpp vout in Digital Video Out VENC settings determine PINMUX1 9 8 COU GIO077 GIO function T_3 PWM2C RTO2 PWM2 RTO GIO GIO 077 PWM2C RTO2 COUT2 B5 E4 VO NENG Vpp vout in Digital Video Out VENC settings determine PINMUX1 11 10 CO GIO076 GIO function UT_2 PWM2D RTO3 PWM2 RTO GIO GIO 076 PWM2D RTO3 4 COUT1 B4 F3 VO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 13 12 cCO GIO075 GIO function UT_1 PWM3A PWM3 GIO GIO 075 PWM3A4 COUT0 B3 F4 VO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 15 14 cO GIO074 GIO function UT_O PWM3B PWM3 GIO GIO 074 PWM3B4 HSYNC F5 VO NENG Vpp vout PD in Video Encoder Horizontal
20. TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 www ti com The write buffer is used for all writes to a noncachable bufferable region write through region and write misses to a write back region A separate buffer is incorporated in the Dcache for holding write back for cache line evictions or cleaning of dirty cache lines The main write buffer has 16 word data buffer and a four address buffer The Dcache write back has eight data word entries and a single address entry 3 2 4 Tightly Coupled Memory TCM ARM internal RAM is provided for storing real time and performance critical code data and the Interrupt Vector table ARM internal ROM enables non AEMIF boot options such as NAND UART and HPI The RAM and ROM memories interfaced to the ARM926EU S via the tightly coupled memory interface that provides for separate instruction and data bus connections Since the ARM TCM does not allow instructions on the D TCM bus or data on the I TCM bus an arbiter is included so that both data and instructions can be stored in the internal RAM ROM The arbiter also allows accesses to the RAM ROM from extra ARM sources e g EDMA or other masters The ARM926EJ S has built in DMA support for direct accesses to the ARM internal memory from a non ARM master Because of the time critical nature of the TCM link to the ARM internal memory all accesses from non ARM devices are treated as
21. This section describes the only supported device clocking configurations for DM355 216 The DM355 supports either 24 MHz typical or 36 MHz reference clock crystal or external oscillator input Configurations are shown for both cases 3 5 2 1 Supported Clocking Configurations for DM355 216 24 MHz reference 3 5 2 1 1 DM355 216 PLL1 24 MHz reference All supported clocking configurations for DM355 216 PLL1 with 24 MHz reference clock are shown in Table 3 2 Table 3 2 PLL1 Supported Clocking Configurations for DM355 216 24 MHz reference PREDI PLLM POSTDIV PLL1 ARM Peripherals Venc VPSS v VCO MPEG and JPEG Co Processor 8 m 2 or 1 MHz PLLDIV SYSC PLLDIV SYSCLK2 PLLDIV3 SYSCL PLLDIV4 SYSCLK fixed programmable programma 1 LK1 2 MHz n K3 4 or 2 4 ble 2 MHz 4 programma MHz programmable MHz fixed fixed ble bypass bypass bypass bypas 2 12 4 6 10 2 4 4 6 s 8 144 1 432 2 216 4 108 16 27 4 108 8 135 1 405 2 202 5 4 101 25 15 27 4 101 25 8 126 1 378 2 189 4 94 5 14 27 4 94 5 8 117 1 351 2 175 5 4 87 75 13 27 4 87 75 8 108 1 324 2 162 4 81 12 27 4 81 8 99 1 297 2 148 5 4 74 25 11 27 4 74 25 8 180 2 270 2 135 4 67 5 10 27 2 135 8 162 2 243 2 121 5 4 60 75 9 27 2 121 5 8 144 2 216 2 108 4 54 8 27 2 108 8 126 2 189 2 94 5 4 47 25 7 27 2 94 5 8 108 2 162 2 81 4 40 5 6 27 2 81 3 5 2 1 2 DM355 216 PLL2 24
22. 3 A dk Figure 5 8 MXI2 CLKIN2 Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 101 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 7 Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 see Figure 5 9 DM355 UNI NO PARAMETER MIN TYP MAX T 1 to cLKOUTI Cycle time CLKOUT1 te MXI1 ns 2 tw CLKOUT1H Pulse duration CLKOUT1 high 0 45P 0 55P ns 3 twCLKOUTIL Pulse duration CLKOUT1 low 0 45P 0 55P ns 4 tycLKouT1 Transition time CLKOUT1 0 05P ns 5 tamxiH Delay time MXI1 CLKIN1 high to CLKOUT1 high 1 8 ns CLKOUT1H e tamxnL Delay time MXI1 CLKIN1I low to CLKOUT1 low 1 8 ns CLKOUTIL 1 The reference points for the rise and fall transitions are measured at Vo MAX and VoyMIN 2 P 1 CLKOUT1 clock frequency in nanoseconds ns For example when CLKOUT1 frequency is 24 MHz use P 41 6 ns 5 gt 6 gt ft MXI CLKIN x kt ff Nf HE mme ST emm E k 2 i E d 1 gt 8 acu F Nf _ f _f NS k 3 asl le Figure 5 9 CLKOUT1 Timing Table 5 8 Switching Characteristics Over Recommended Operating Conditions for CLKOUT2 see Figure 5 10 DM355 NO PARAMETER UNIT MIN TYP MAX 1 tc cL
23. QDMA Channels Triggered by a configuration bus write to a designated QDMA trigger word QDMAs allow a minimum number of linear writes optimized for GEM IDMA feature to be issued to the CC to force a series of transfers to take place EDMA Channel Synchronization Events The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory Table 3 19 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels For the device the association of an event to a channel is fixed each of the EDMA channels has one specific event associated with it These specific events are captured in the EDMA event registers ER ERH even if the events are disabled by the EDMA event enable registers EER EERH For more detailed information on the EDMA module and how EDMA events are enabled captured processed linked chained and cleared etc see the Document Support section for the Enhanced Direct Memory Access EDMA Controller Reference Guide Table 3 19 EDMA Channel Synchronization Events EE EVENT NAME EVENT DESCRIPTION 0 TIMERS TINT6 Timer 3 Interrupt TINT6 Event 1 TIMER3 TINT7 Timer 3 Interrupt TINT7 Event 2 ASPO XEVT ASPO Transmit Event 3 ASPO REVT ASPO Receive Event 4 VPSS EVT1 VPSS Event 1 5 VPSS EVT2 VPSS Event 2 6 VPSS EVT3 VPSS Event 3 7 VPSS EVT4 VPSS Event 4 8 ASPI ENA TIMERZ ASP1 T
24. Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 1H 7 eege aak een a en ME emm D men GE mm DE LO Sp CMD START XMIT Valid X Valid vaia 7 END 1 D Figure 5 19 MMC SD Host Command Timing 9 gt r f l P ep SD_CLK J Lee E ween dE seg ZE vm E ps ber 1 k 2 SD_CMD START H OI Valid END ___ Figure 5 20 MMC SD Card Response Timing Loi b te scuff NS D e D e D em D wg E 14 4 lel 14 TE as 14 SD_DATx WS Rig D CXC Dx wn Figure 5 21 MMC SD Host Write Timing 9 7 Fi Sh E a a E e E e E E ec CR Ge a k3 SD_DATx Start To X D Y Dx J En ____ Figure 5 22 MMC SD Host Read and Card CRC Status Timing 114 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 9 Video Processing Sub System VPSS Overview 5 9 1 The contains a Video Processing Sub System VPSS that provides an input interface Video Processing Front End or VPFE for external imaging peripherals such as image sensors video decoders etc and an output interface Video Processing Back End or VPBE for display devices such as analog SDTV displays digital LCD panels HDTV video encoders etc In addition to these peripherals there is a set of common
25. g 15 Ee EM CED OI d ew saa FH k 16 y e 17 gt lt 18 k 19 gt k 20 A 21 gt 22 1 9g __ EM_WE NY vg 27 m 26 gt Figure 5 15 Asynchronous Memory Write Timing for EMIF Submit Documentation Feedback Peripheral Information and Electrical Specifications 109 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 110 www ti com SETUP STROBE Extended Due to EM_WAIT EM_CE 1 0 STROBE HOLD a a eo Figure 5 16 EM_WAIT Read Timing Requirements 1 U STROBE Extended Due to EM_WAIT STROBE HOLD 1 EM_CE 1 0 E SETUP EM BAD OI lee e SES a h g d SE EM WE d d _ 2 E eh a a Figure 5 17 EM_WAIT Write Timing Requirements Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 _ gt _ 33 EM_CLK ee 39 J EM_CE 1 0 Sage geese eee pees pee 34 EM_ADV gt ke 35 k 34 WR 36 EM _BAO EM_A 13 0 EM BA 37 30 k Datn 1 EM_D 15 0 Xt tnt 0 003 X00d008 Xen EM_WAIT d Figure 5 18 Synchronou
26. quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully TI s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate is undefined Only qualified production devices are to be used in production Submit Documentation Feedback Device Overview 55 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTEMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 TI device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example ZCE the temperature range for example Blank is the commercial temperature range and the device speed range in megahertz for example 202 is 202 5
27. 5 3 3 V Vpp IO Vpp for LVCMOS VppsHv Von IO Vpp for MXI O1 VppsHv Von IO Von for MXI O2 VppsHVv1 Von IO Von for ISB DRVVBUS VppsHv2 Vppass_pproLL DDR DLL analog Vpp VDDA33_USB Analog 3 3 V power USB PHY VDpa33 uep pu Common mode 3 3 V power for USB PHY PLL Vpop IO Vpp for peripherals 3 3 V 5 3 3 V VDD ViN IO Vpp for VideolN I F Vop vom IO Vpop for VideoOUT I F 1 8 V 5 1 8 V VDD opp 1 8 V 5 1 8V Vppais Analog 1 8 V power 1 8V 5 1 8 V Vppais pac Place decoupling caps 0 1uF 10pf close to chip OV n a DV Vas Ma Connect to external crystal capacitor ground OV n a DV Vss_mx2 Connect to external crystal capacitor ground OV n a OV Vss Chip ground USB ESD ground ground Vss oV n a DV Vssa ground Keep separate from digital ground Vss DV n a OV Van PLL PLL1 Vssa DV n a OV Vssa_PLL2 PLL2 Vssa OV n a OV Vssa_DLL DLL ground DV n a DV Vss_usB USB ground Vssa13_USB Vssa13_USB Vssa33_USB Vsga33_USB_PLL OV n a DV Vss_USB_REF USB PHY reference ground VSSREF OV n a OV Vssa_DAG DAC ground Keep separate from digital ground Vss Vpps 0 5 Vpps 0 5 Vrersstt DRR ref voltage Vpps divided by 2 through board resistors 5V 5V USB_VBUS VBUS Connect to external charge pump 96 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 3 1 Power Supply Sequencing In
28. EM_D11 L17 VO AEMI Vpp in Async EMIF Data Bus bit 11 PINMUX2 4 EM_D1 GIO049 F _ 8 GIO GIO GIO 049 default set by AECFG 3 EM_D10 L19 VO AEMI Vpp in Async EMIF Data Bus bit 10 PINMUX2 4 EM_D1 GI0048 F _ 8 GIO GIO GIO 048 default set by AECFG 3 Submit Documentation Feedback Device Overview 45 PRODUCT PREVIEW MalAddd LONGOUd Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID UI Supply PD State EM_D09 K18 VO AEMI Vpp in Async EMIF Data Bus bit 09 PINMUX2 4 EM_D1 GIO047 F 8 GIO GIO GIO 047 default set by AECFG 3 EM_D08 L16 VO AEMI Vpp in Async EMIF Data Bus bit 08 PINMUX2 4 EM_D1 GIO046 F 8 GIO GIO GIO 046 default set by AECFG 3 EM_DO07 K19 VO AEMI Vpp in Async EMIF Data Bus bit 07 PINMUX2 5 EM_D7 GIlO045 F 0 GIO GIO GIO 045 EM_DO6 K17 VO AEMI Vpp in Async EMIF Data Bus bit 06 PINMUX2 5 EM_D7 GIO044 F 0 GIO GIO GIO 044 EM_D05 J19 VO AEMI Vpp in Async EMIF Data Bus bit 05 PINMUX2 5 EM_D7 GIO043 F 0 GIO GIO GIO 043 EM_D04 L15 VO AEMI Vpp in Async EMIF Data Bus bit 04 PINMUX2 5 EM_D7 GIlO042 F 0 GIO GIO GIO 042 EM_D03 J18 VO AEMI Vpp in Async EMIF Data Bus bit 03 PINMUX2 5 EM_D7 GIO041 F 0 GIO GIO GIO 041 EM_D02
29. GIO069 B2 PWM3D VCLK VCLK VCLK VCLK VCLK GIO068 YOUT7 Y7 Y7 Cb7 Cr7 R7 Data7 YOUT6 Y6 Y6 Cb6 Cr6 R6 Data6 YOUT5 Y5 Y5 Cb5 Cr5 R5 Data5 YOUT4 Y4 Y4 Cb4 Cr4 R4 Data4 YOUT3 Y3 Y3 Cb3 Cr3 R3 Data3 YOUT2 Y2 Y2 Cb2 Cr2 G7 Data2 YOUT1 Y1 Y1 Cb1 Cr1 G6 Data YOUTO YO Y0 Cb0 CrO G5 DataO COUT7 C7 LCD_AC G4 LCD_AC GIO081 PWMO COUT6 C6 LCD_OE G3 LCD_OE GIO080 PWM1 COUT5 C5 BRIGHT G2 BRIGHT GIO079 PWM2A RTOO COUT4 C4 PWM B7 PWM GIO078 PWM2B RTO1 COUT3 C3 CSYNC B6 CSYNC GIO077 PWM2C RTO2 COUT2 C2 B5 GIO076 PWM2D RTO3 COUT1 C1 B4 GIO075 PWM3A COUTO Co B3 GIO074 PWM3B 16 Device Overview Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 7 Digital Video Terminal Functions TERMINAL TYPE OTHER 3 DESCRIPTION NAME NO YOUT7 R7 C3 VO Z Vop vour Digital Video Out VENC settings determine function YOUT6 R6 A4 VO Z Vop vour Digital Video Out VENC settings determine function YOUT5 R5 B4 VO Z Vop vour Digital Video Out VENC settings determine function YOUT4 R4 B3 VO Z Vop vour Digital Video Out VENC settings determine function YOUT3 R3 B2 VO Z Vop vour Digital Video Out VENC settings determine function YOUT2 G7 A3 VO Z Vop vour Digital Video Out VENC settings determi
30. N TMS D8 EMUL Vop PU in JTAG test mode select ATIO N TRST CO EMUL Vpp PD in JTAG test logic reset active low ATIO N RTCK E11 O EMUL Vop out L JTAG test clock output ATIO N EMUO E8 VO EMUL Vop PU in JTAG emulation 0 UO ATIO V N DD VoD EMU1 E7 VO EMUL Vpp PU in JTAG emulation 1 UO SE EMUf 1 0 00 Force Debug Scan chain ARM and ARM ETB TAPs connected EMUf 1 0 11 Normal Scan chain ICEpick only RSV01 Ji A Reserved This signal should be left as a No VO Z Connect or connected to Vss RSV02 K1 A Reserved This signal should be left as a No VO Z Connect or connected to Vss Submit Documentation Feedback Device Overview 51 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID UI Supply PD State RSV03 L1 A Reserved This signal should be left as a No VO Z Connect or connected to Vss RSV04 M1 A Reserved This signal should be left as a No VO Z Connect or connected to Vss RSV05 N2 A Reserved This signal should be connected VO Z to Vss RSV06 M2 PWR Reserved This signal should be connected
31. TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 13 1 1 Inter Integrated Circuits 12C Timing Table 5 33 Timing Requirements for DC Timings see Figure 5 39 DM355 STANDARD NO MODE FAST MODE UNIT MIN MAX MIN MAX 1 te SCL Cycle time SCL 10 2 5 us Setup time SCL high before SDA low for a repeated START 2 tsu SCLH SDAL ae es 9 H 4 7 0 6 us Hold time SCL low after SDA low for a START and a repeated 3 thscLL sDAL START condition j 4 0 6 us 4 tw SCLL Pulse duration SCL low 4 7 1 3 us 5 tw SCLH Pulse duration SCL high 4 0 6 us 6 tsu SDAV SCLH Setup time SDA valid before SCL high 250 100 2 ns 7 thspa ScLL Hold time SDA valid after SCL low For I C bus devices 0 08 0 9 us Pulse duration SDA high between STOP and START 8 tw SDAH conditions 4 7 1 3 us H tyspa Rise time SDA 1000 20 0 1Cp 300 ns 10 tyscLy Rise time SCL 1000 20 0 1C 300 ns 11 tispa Fall time SDA 300 20 0 1C 300 ns 12 hee Fall time SCL 300 20 0 1Cp 300 ns 13 tsu SCLH SDAH Setup time SCL high before SDA high for STOP condition 4 0 6 US 14 tw SP Pulse duration spike must be suppressed 0 50 ns 15 C Capacitive load for each bus line 400 400 pF d own The 12C pins SDA and SCL do not feature fail safe I O buffers These pins could potentially draw current when the device is p
32. The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of lt 4 Volts per nanosecond 4 V ns at the device pin Figure 5 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals This load capacitance value does not indicate the maximum load the device is capable of driving 5 1 1 Signal Transition Levels All input and output timing parameters are referenced to Na for both 0 and 1 logic levels For 3 3 V I O Vret 1 65 V For 1 8 V I O Ve 0 9 V Vref Figure 5 2 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to Vu MAX and Vu MIN for input clocks Vo MAX and Voy MIN for output clocks 7 Vref Vin MIN or Von MIN Vref Vit MAX or VoL MAX Figure 5 3 Rise and Fall Transition Time Voltage Reference Levels 94 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 1 2 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board rou
33. tsuc_WEV PCLK Setup time C_WE valid before PCLK edge 3 ns 12 thipctk c_wev Hold time C_WE valid after PCLK edge 2 ns 13 tsu c_FIELDV PCLk Setup time C_FIELD valid before PCLK edge 3 ns 14 th pcLk c_FlELDv Hold time C_FIELD valid after PCLK edge 2 ns 118 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 PCLK Positive Edge Clocking NO fF FY PK w A EE AL Negative Edge Clocking lt gt 8 10 le 7 9 gt je 11 13 gt a gt 12 14 a 5 gt gt pn Cl 7 0 YI 7 0 CCD 13 0 Figure 5 24 VPFE CCD Slave Mode Input Data Timing Table 5 19 Timing Requirements for VPFE CCD Master Mode see Figure 5 25 DM355 NO UNIT MIN MAX 15 tsu CCDV PCLK Setup time CCD valid before PCLK edge 3 ns 16 th PCLK CCDV Hold time CCD valid after PCLK edge 2 ns 23 tsu CWEV PCLK Setup time C_WE valid before PCLK edge 3 ns 24 th PCLK CWEV Hold time C_WE valid after PCLK edge 2 ns 1 The VPFE may be configured to operate in either positive or negative edge clocking mode When in positive edge clocking mode the rising edge of PCLK is referenced When in negative edge clocking mode the falling edge of PCLK is referenced PCLK Positive Edge Clocking T Sf Sf __ PCLK P
34. 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 2 9 Asynchronous EMIF NAND OneNAND Terminal Functions continued TERMINAL i a NANE NG TYPE OTHER 9 DESCRIPTION Async EMIF Lowest numbered chip select Can be programmed to be used for EM CEO J16 VO Z V standard asynchronous memories example flash OneNAND or NAND GI0037 Dp memory Used for the default boot and ROM boot modes GIO GIO 037 EM CE1 Async EMIF Second chip select Can be programmed to be used for standard GIO036 G19 1 O Z Vpp asynchronous memories example flash OneNAND or NAND memory GIO GIO 036 EM WEI Async EMIF Write Enable Gl0035 J15 VO Z Von NAND SM xD WE Write Enable output GIO GIO 035 EM OE Async EMIF Output Enable GlO034 F19 VO Z Vpp NAND SM xD RE Read Enable output GIO GIO 034 Async EMIF Async WAIT Ace GIS Volz Vbo NAND SM xD RDY BSY input GIO GIO 033 EM_ADV H16 VO Z V OneNAND Address valid detect for OneNAND interface GIO032 DD GIO GIO 032 EM_CLK OneNAND Clock for OneNAND flash interface GIO031 E19 Ge Von GIO GIO 031 2 4 4 DDR Memory Interface The DDR EMIF supports DDR2 and mobile DDR Table 2 10 DDR Terminal Functions TERMINAL TYPE OTHER DESCRIPTION NAME NO DDR_CLK Wa VO Z VDD_DDR DDR Data Clock DDR_CLK W VO Z Von opp DDR Complementary Data Clock DDR_RAS T6 VO
35. 3 19 EDMA Channel Synchronization Events continued ER EVENT NAME EVENT DESCRIPTION 21 UART1 UTXEVT1 UART 1 Transmit Event 22 UART2 URXEVT2 UART 2 Receive Event 23 UART2 UTXEVT2 UART 2 Transmit Event 24 Reserved 25 GPIO GPINT9 GPIO 9 Interrupt Event 26 ee MMC SDO Receive Event 27 MMCOTXEVT MMC SDO Transmit Event 28 I2CREVT 12C Receive Event 29 I2CXEVT 12C Transmit Event 30 MMC1RXEVT MMC SD1 Receive Event 31 MMC1TXEVT MMC SD1 Transmit Event 32 GPINTO GPIO 0 Interrupt Event 33 GPINT1 GPIO 1 Interrupt Event 34 GPINT2 GPIO 2 Interrupt Event 35 GPINT3 GPIO 3 Interrupt Event 36 GPINT4 GPIO 4 Interrupt Event 37 GPINT5 GPIO 5 Interrupt Event 38 GPINT6 GPIO 6 Interrupt Event 39 GPINT7 GPIO 7 Interrupt Event 40 GPBNKINTO GPIO Bank 0 Interrupt Event 41 GPBNKINT1 GPIO Bank 1 Interrupt Event 42 GPBNKINT2 GPIO Bank 2 Interrupt Event 43 GPBNKINT3 GPIO Bank 3 Interrupt Event 44 GPBNKINT4 GPIO Bank 4 Interrupt Event 45 GPBNKINT5 GPIO Bank 5 Interrupt Event 46 GPBNKINT6 GPIO Bank 6 Interrupt Event 47 GPINT8 GPIO 8 Interrupt Event 48 TIMERO TINTO Timer 0 Interrupt Event 49 TIMERO TINT1 Timer 1 Interrupt Event 50 TIMER1 TINT2 Timer 2 Interrupt Event 51 TIMER1 TINTS Timer 3 Interrupt Event 52 PWMO PWM 0 Event 53 PWM1 PWM 1 Event 54 PWM2 PWM 2 Event 55 PWM3 PWM 3 Event 56 63 Reserved 3 15 MPEG JPEG Overview The DM35
36. 4 7 Universal Serial Bus USB Interface e Deleted NOTE about OTG supplies not being supported Updated Table 2 13 USB Terminal Functions Table 2 17 SPI Terminal Functions e Changed Terminal No of GIO007 SPIO_SDENA 1 from B12 to C17 Table 2 21 System Boot Terminal Functions e Updated all Terminal Names changed GOP to GIO Updated Table 2 23 DM355 Pin Descriptions Section 3 1 1 Components of the ARM Subsystem e Updated the Video Processing Front End VPFE sub list Updated Table 3 7 PLL2 Supported Clocking Configurations for DM355 270 24 MHz reference Table 3 9 e Changed title from PLL2 Supported Clocking Configurations for DM355L 36 MHz reference to PLL2 Supported Clocking Configurations for DM355 270 36 MHz reference e Updated table Section 3 12 1 Boot Modes Overview e If BTSEL 1 0 01 bulleted item Changed Asynchronous EMIF AEMIF or NOR Flash boot to Asynchronous EMIF AEMIF boot Section 4 2 Recommended Operating Conditions e Changed Von e to Vpopa PLL1 e Changed Vpp iso Vppa_PLL2 e Added Vppa33_ppro t Supply voltage DDR DLL Analog e Removed Vppaig Supply voltage Analog e Changed Vssa_uss to Vss_uss e Removed Vssa Supply ground Analog e Updated descriptions of Vss_mx1 and Vss mx2 Submit Documentation Feedback Revision History 151 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Di
37. 8 e Invalidate TLB entry selected by MVA using CP15 register 8 e Lockdown of TLB entries using CP15 register 10 3 2 3 Caches and Write Buffer The size of the Instruction Cache is 16KB Data cache is 8KB Additionally the Caches have the following features e Virtual index virtual tag and addressed using the Modified Virtual Address MVA e Four way set associative with a cache line length of eight words per line 32 bytes per line and with two dirty bits in the Dcache e Dcache supports write through and write back or copy back cache operation selected by memory region using the C and B bits in the MMU translation tables e Critical word first cache refilling e Cache lockdown registers enable control over which cache ways are used for allocation on a line fill providing a mechanism for both lockdown and controlling cache corruption e Dcache stores the Physical Address TAG PA TAG corresponding to each Dcache entry in the TAG RAM for use during the cache line write backs in addition to the Virtual Address TAG stored in the TAG RAM This means that the MMU is not involved in Dcache write back operations removing the possibility of TLB misses related to the write back address e Cache maintenance operations provide efficient invalidation of the entire Dcache or Icache regions of the Dcache or Icache and regions of virtual memory Submit Documentation Feedback Detailed Device Description 61 PRODUCT PREVIEW MalAddd LONGOUd
38. ARM Subsystem Block Diagram 3 2 ARM926EJ S RISC CPU 60 The ARM Subsystem integrates the ARM926EJ S processor The ARM926EU S processor is a member of ARM9 family of general purpose microprocessors This processor is targeted at multi tasking applications where full memory management high performance low die size and low power are all important The ARM926EUJ S processor supports the 32 bit ARM and 16 bit THUMB instruction sets enabling the user to trade off between high performance and high code density Specifically the ARM926EJ S processor supports the ARMv5TEu instruction set which includes features for efficient execution of Java byte codes providing Java performance similar to Just in Time JIT Java interpreter but without associated code overhead The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug The ARM926EU S processor has a Harvard architecture and provides a complete high performance subsystem including e ARM926E S integer core e CP15 system control coprocessor e Memory Management Unit MMU e Separate instruction and data Caches e Write buffer e Separate instruction and data Tightly Coupled Memories TCMs internal RAM interfaces e Separate instruction and data AHB bus interfaces Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com 3 2 1 S
39. CLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 x P when CLKGDV is even D CLKX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 x P when CLKGDV is even Use which ever value is greater 4 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output CLKXM FSXM 1 CLKRM FSRM 0 for master ASP 5 FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX CLKX d Y a E 3 Man al M44 gt FSX l E WE ME M46 gt ke M45 px O Bo J i RL A ea eaU A Figure 5 44 ASP as SPI CLKSTP 10b CLKXP 1 142 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 43 ASP as SPI Timing Requirements CLKSTP 11b CLKXP 1 see Figure 5 45 MASTER NO UNIT MIN MAX M58 tsu DRV CKXL Setup time DR valid before CLKX low 11 ns M59 th CKXL DRV Hold time DR valid after CLKX low 0 ns Table 5 44 ASP as SPI Switching Characteristics CLKSTP 11b CLKXP 1 see Figure 5 45 MASTER NO PARAMETER UNIT MIN MAX M62 tc CKX Cycle time CLKX Bae ns M53 tackxH EXH Delay time CLKX high to FSX high D 1 D 3 ns M54 taexL ckxL
40. Configurations for DM355 270 36 MHz reference PREDI PLLM POSTDI PLL1 ARM Peripherals Venc VPSS V Vv vco MPEG and JPEG Co Processor 8 m 2 fixed MHz PLLDIV SYSC PLLDIV SYSCLK2 PLLDIV3 SYSCL PLLDIV4 SYSCLK4 fixed programmable 1 LK1 2 MHz n K3 2 fixed MHz 2 MHz 4 programmable MHz fixed fixed bypas bypass bypass bypas 2 18 4 9 10 3 6 4 18 s s 8 120 1 540 2 270 4 135 20 27 4 135 8 114 1 513 2 256 5 4 128 25 19 27 4 128 25 8 108 1 486 2 243 4 121 5 18 27 4 121 5 8 102 1 459 2 229 5 4 114 75 17 27 4 114 75 8 96 2 432 2 216 4 108 16 27 4 108 8 180 2 405 2 202 5 4 101 25 15 27 2 202 5 8 168 2 378 2 189 4 94 5 14 27 2 189 8 156 2 351 2 175 5 4 87 75 13 27 2 175 5 8 144 2 324 2 162 4 81 12 27 2 162 8 132 2 297 2 148 5 4 74 25 11 27 2 148 5 8 120 2 270 2 135 4 67 5 10 27 2 135 8 108 2 243 2 121 5 4 60 75 9 27 2 121 5 8 96 2 216 2 108 4 54 8 27 2 108 70 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 5 3 2 2 DM355 270 PLL2 36 MHz reference All supported clocking configurations for DM355 270 PLL2 with 36 MHz reference clock are shown in Table 3 5 Table 3 9 PLL2 Supported Clocking Configurations for DM355 270 36 MHz reference
41. Control and Data Output With Respect to PCLK and EXTCLK Submit Documentation Feedback Peripheral Information and Electrical Specifications 123 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 24 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK see Figure 5 30 NO PARAMETER DMA UNIT MIN MAX 17 teveLk Cycle time VCLK 13 33 160 ns 18 twvcLKH Pulse duration VCLK high 5 7 ns 19 tw VCLKL Pulse duration VCLK low 5 7 ns 20 tyvcLk Transition time VCLK 3 ns 21 ta vcLKINH VcLKH Delay time VCLKIN high to VCLK high 2 12 ns 22 tavcLKINL vcLkKL Delay time VCLKIN low to VCLK low 2 12 ns 23 ta VCLK VCTLV Delay time VCLK edge to VCTL valid 4 ns 24 ta VCLK VCTLIV Delay time VCLK edge to VCTL invalid 0 ns 25 ta VCLK VDATAV Delay time VCLK edge to VDATA valid 4 ns 26 ta VCLK VDATAIV Delay time VCLK edge to VDATA invalid 0 ns 1 The VPBE may be configured to operate in either positive or negative edge clocking mode When in positive edge clocking mode the rising edge of VCLK is referenced When in negative edge clocking mode the falling edge of VCLK is referenced 2 VCLKIN PCLK or EXTCLK Note that if the CCDC is used the PCLK frequency must be less than or equal to half th
42. DDR clock and data 42 Device Overview Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State DDR_VREF U10 PWR DDRI VDD_DDR DDR Voltage input for the SSTL_18 IO O buffers Vssa DLL R11 GND DDRD VDpp DDR DDR Ground for the DDR DLL 8 gp a VDDA33_DDRDLL R10 PWR DDRD VDD_DDR DDR Power 3 3 Volts for the DDR DLL LL DDR_ZN T9 UO DDRI VDD_DDR DDR Reference output for drive strength O calibration of N and P channel outputs Tie to ground via 50 ohm resistor 0 5 tolerance EM_A13 VI UO AEMI Von PD inL Async EMIF Address Bus bit 13 PINMUX2 0 EM_A1 GIO067 F 3 BTSEL 1 GIO syste m GIO GIO 067 default set by AECFG 0 System BTSEL 1 0 sampled at Power on Reset to determine Boot method 00 NAND 01 Flash 10 UART 11 SD EM_A12 U19 VO AEMI Von PD inL Async EMIF Address Bus bit 12 PINMUX2 0 EM_A1 GIOO066 Ei A BTSEL 0 GIO syste m GIO GIO 066 default set by AECFG 0 System BTSEL 1 0 sampled at Power on Reset to determine Boot method 00 NAND 01 Flash 10 UART 11 SD EM_A11 R16 VO AEMI Von PU inH Async EMIF Address Bus bit 11 PINMUX2 0 EM_A1 GIO065 EI A AECFG 3 GIO syste
43. Data Bus bit 06 Glo044 Kiz 1 O Z Von GIO GIO 044 EM_D07 Async EMIF Data Bus bit 07 Gl0045 Go die Vos GIO GIO 045 EM_D08 Async EMIF Data Bus bit 08 Gl0046 E16 ge Vos GIO GIO 046 EM_D09 Async EMIF Data Bus bit 09 G10047 K18 vOIZ Von GIO GIO 047 EM_D10 Async EMIF Data Bus bit 10 Gl0048 EI dee Vos GIO GIO 048 EM_D11 Async EMIF Data Bus bit 11 GIO049 S VOZ VoD GIO GIO 049 EM_D12 Async EMIF Data Bus bit 12 GIO050 L18 O Vos GIO GIO 050 EM_D13 Async EMIF Data Bus bit 13 GIO051 Mis VOl Vos GIO GIO 051 EM_D14 Async EMIF Data Bus bit 14 GIO052 M19 HO Vos GIO GIO 052 EM_D15 Async EMIF Data Bus bit 15 GIO053 Mig OIE Vos GIO GIO 053 EM BAO Async EMIF Bank Address 0 signal 8 bit address In 8 bit mode lowest GIO054 N19 VO Z V address bit Or can be used as an extra Address line bit 14 when using 16 bit DD memories EM_A14 GIO GIO 054 EM BA Async EMIF Bank Address 1 signal 16 bit address In 16 bit mode lowest GlO055 P19 VO Z Vpp address bit In 8 bit mode second lowest address bit GIO GIO 055 EM A00 Async EMIF Address Bus bit 00 Note that the EM_AO is always a 32 bit Ze M16 VO Z V address GIO056 E GIO GIO 056 EM_AO03 Async EMIF Address Bus bit 03 GI0057 N18 der Vos GIO GIO 057 EM_A04 Async EMIF Address Bus bit 04 GIO058 PiS de Vos GIO GIO 058 EM_A05 Async EMIF Address Bus bit 05 GIO059 Ale sca Vos GIO GIO 059 EM AO6G Async EMIF Address Bus bit 06
44. EM_D15_8 AEMIF Default 3 Bus Width 16 or 8 bits EM_A12 PD Async EMIF Address Bus bit 12 GIO066 U19 VO Z V GIO GIO 066 System BTSEL 1 0 sampled at Power on Reset to determine BTSEL 0 DD Boot method EM A13 Async EMIF Address Bus bit 13 GIO067 v19 VO Z PD GIO GIO 067 System BTSEL 1 0 sampled at Power on Reset to determine Von Boot method Used to drive Boot Status LED signal active low in ROM boot BTSEL 1 modes VCLK S Video Encoder Video Output Clock GIO068 He ie Vo vo GIO GIO 068 GH PD Video Encoder External clock input used if clock rates gt 27 MHz are needed B2 G3 VO Z Vbo vout e g 74 25 MHz for HDTV digital output PWM3D GIO GIO 069 Digital Video Out B2 PWM3D FIELD GIO070 H4 VO Z V Video Encoder Field identifier for interlaced display formats R2 DD_VOU GIO GIO 070 Digital Video Out R2 PWM3C PWM3C VSYNC G5 VO Z PD Video Encoder Vertical Sync Glo072 Vpp_vout GIO GIO 072 HSYNC F5 VO Z PD Video Encoder Horizontal Sync GIO073 Vop vour GIO GIO 073 COUTO B3 F4 VO Z V S Digital Video Out VENC settings determine function GIO GIO 074 GI0074 DD VOU PWM3B PWM3B COUT1 B4 Digital Video Out VENC settings determine function GIO GIO 075 GI0075 e dee Von vom PWM3A PWM3A COUT2 B5 SH A i G10076 E4 VOIZ Beggen GE Video Out VENC settings determine function GIO GIO 076 PWM2D PWM2D RTO3 COUT3 B6 D i f GI0077 E3 VO Z aset GE Video Out VENC settings d
45. GP timers and can be programmed in 64 bit mode dual 32 bit unchained mode or dual 32 bit chained mode Timer 2 is used only as a watchdog timer The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access EDMA synchronization events and Real Time Output RTO events Timer 3 only The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition such as a non exiting code loop TMS320DM35x DMSoC General Purpose Input Output GPIO Reference Guide This document describes the general purpose input output GPIO peripheral in the TMS320DM35x Digital Media System on Chip DMSoC The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an input you can detect the state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin Submit Documentation Feedback Device Overview 57 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 58 SPRUEE7 SPRUEH7 SPRUF71 SPRUF72 SPRUF74 SPRUFC8 da TEXAS www ti com TMS320DM35x DMSoC Pulse Width Modulator PWM Reference Guide This document describes the pulse width modulator PWM peripheral in the TMS320DM35x Digital Medi
46. MHz reference All supported clocking configurations for DM355 216 PLL2 with 24 MHz reference clock are shown in Table 3 3 Table 3 3 PLL2 Supported Clocking Configurations for DM355 216 24 MHz reference PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock n programmable m 1 fixed MHz PLLDIV1 SYSCLK1 DDR_CLK programmable 1 fixed MHz MHz bypass bypass bypass bypass 1 24 12 8 114 1 342 1 342 171 8 108 1 324 1 324 162 8 102 1 306 1 306 153 8 96 1 288 1 288 144 12 133 1 266 1 266 133 12 100 1 200 1 200 100 15 100 1 160 1 160 80 Submit Documentation Feedback Detailed Device Description 67 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 5 2 2 Supported Clocking Configurations for DM355 216 36 MHz reference 3 5 2 2 1 DM355 216 PLL1 36 MHz reference All supported clocking configurations for DM355 216 PLL1 with 36 MHz reference clock are shown in Table 3 4 Table 3 4 PLL1 Supported Clocking Configurations DM355 216 36 MHz reference PREDI PLLM POSTDIV PLL1 ARM Peripherals Venc VPSS V VCO MPEG and JPEG Co Processor 8 m 2 or 1 MHz PLLDIV SYSCL PLLDIV SYSCLK PLLDIV3 SYSCLK PLLDIV4 SYSCLK fixed programmable programma 1 K1 2 2 n 3 4 or 2 4 ble 2 MHz 4 MHz progra
47. PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate Leakage or standby power is unavoidable while power is applied and scales roughly with the operating junction temperatures Leakage power can only be avoided by removing power completely from a device or subsystem The DM355 includes several power management features which are briefly described in Table 12 1 Refer to the ARM Subsystem User s Guide for more information on power management Table 3 17 Power Management Features Power Management Features Description Clock Management Module clock disable Module clocks can be disabled to reduce switching power Module clock frequency scaling Module clock frequency can be scaled to reduce switching power PLL power down The PLLs can be powered down when not in use to reduce switching power ARM Sleep Mode ARM Wait for Interrupt sleep mode Disable ARM clock to reduce active power System Sleep Modes Deep Sleep mode Stop all device clocks and power down internal oscillators to reduce active power to a minimum Registers and memory are preserved UO Management USB Phy power down The USB Phy can be powered down to reduce USB I O power DAC power down The DAC s can be powered down to reduce DAC power DDR sel
48. Submit Documentation Feedback Device Overview 33 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 2 20 PWM Terminal Functions continued TERMINAL TYPE OTHER DESCRIPTION NAME NO COUT3 B6 Digital Video Out VENC settings determine function GIO GIO 077 GIO077 E3 1 O Z Vop vouT PWM2C PWM2C R RTO2 RTO2 COUT2 B5 Digital Video Out VENC settings determine function GIO GIO 076 GIO076 E4 VO VDD vom PWM2D PWM2D 7 RTO3 RTO3 COUT1 B4 Digital Video Out VENC settings determine function GIO GIO 075 GIO075 SS de Von vom PWM3A PWM3A COUTO B3 F4 VO Z V Digital Video Out VENC settings determine function GIO GIO 074 GI0074 Do your PWM3B PWM3B FIELD l TA GIO070 Video Encoder Field identifier for interlaced display formats GIO GIO 070 H4 VO Z VDD vouT Digital Video Out R2 R2 K PWM3C PWM3C oe PD Video Encoder External clock input used if clock rates gt 27 MHz are needed G3 VO Z e g 74 25 MHz for HDTV digital output GIO GIO 069 Digital Video Out B2 B2 Vpp_vout PWM3D PWM3D 2 4 15 System Configuration Interface The provides interfaces for system configuration and boot load Table 2 21 System Boot Terminal Functions TERMINAL TYPE OTHER DESCRIPTION NAME NO
49. These support the following range of values TA 4 1 RS 16 1 RST 64 1 RH 8 1 WS 16 1 WST 64 1 WH 8 1 and MEW 1 256 See the TMS320DM355 DMSoC Asynchronous External Memory Interface EMIF User s Guide SPRUED1 for more information E PLLC1 SYSCLK2 period in ns SYSCLK2 is the EMIF peripheral clock SYSCLK2 is one fourth the PLLC output clock For example when PLLC output clock 432 MHz E 9 259 ns See Section 3 5 for more information EWC external wait cycles determined by EM_WAIT input signal EWC supports the following range of values EWC 256 1 Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register See the TMS320DM355 DMSoC Asynchronous External Memory Interface EMIF User s Guide GSPRUED1 for more information Submit Documentation Feedback Peripheral Information and Electrical Specifications 107 PRODUCT PREVIEW MalAddd LONAOYd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 5 14 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module see Figure 5 14 and Figure 5 15 continued DM355 UNI NO PARAMETER MIN Nom MAX T Output setup ti
50. Three 64 Bit General Purpose each e configurable as two separate 32 bit Peripherals Timers timers One 64 Bit Watch Dog Not all peripherals pins are g available at the same time UART Three one with RTS and CTS flow For more detail see the control Device Configuration SPI Three each supports two slave section devices C One Master Slave Audio Serial Port ASP Two ASP General Purpose Input Output Port Up to 104 Pulse width modulator PWM Four outputs Configurable Video Ports One Input VPFE One Output VPBE USB 2 0 High Full Speed Device High Full Low Speed Host On Chip CPU Memory Organization ARM 16 KB l cache 8 KB D cache 32 KB RAM 8 KB ROM JTAG BSDL_ID JTAGID register address location 0x01C4 0028 0x0B73B01F CPU Frequency Maximum MHz ARM 216 MHz and 270 MHz Core V 1 3V Voltage 1 0 V 3 3 V 1 8 V PLL Options Reference frequency options 24 MHz typical 36 MHz Configurable PLL controller PLL bypass programmable PLL BGA Package 13 x 13 mm 337 Pin BGA ZCE Process Technology 90 nm Product Preview PP Product Status Advance Information Al PP or Production Data PD 1 PRODUCT PREVIEW information concerns products in the formative or design phase of development Characteristic data and other specifications are design goals Texas Instruments reserves the right to change or discontinue these products without notic
51. USB PHY NOTE For proper USB function SYSCLK2 must be greater than 60 MHz The USB PHY takes an input clock that is configurable by the USB PHY clock source bits PHYCLKSRC in the USB PHY control register USB_PHY_CTL in the System Control Module When a 24 MHz crystal is used at MXI1 MXO1 set PHYCLKSRC to 0 This will present a 24 MHz clock to the USB PHY When a 36 MHz crystal is used at MXI1 MXO1 set PHYCLKSRC to 1 This will present a 12 MHz clock 36 MHz Submit Documentation Feedback Detailed Device Description 71 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 72 www ti com divided internally by three to the USB PHY The USB PHY is capable of accepting only 24 MHz and 12 MHz thus you must use either a 24 MHz or 36 MHz crystal at MXI1 MXO1 See the TMS320DM355 DMSoC Univeral Serial Bus USB Controller User s Guide SGPRUED2 for more information See the TMS320DM355 DMSoC ARM Subsystem User s Guide for more information on the System Control Module Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 6 PLL Controller PLLC This section describes the PLL Controllers for PLL1 and PLL2 See the TMS320DM355 Digital Media System on Chip ARM Subsystem User s Guide for
52. Up to 104 3 3v GPIO pins GPIO 103 0 e Interrupts Up to 10 unique GPIO 9 0 interrupts from Bank 0 Upto 7 GPIO bank aggregated interrupt signals one from each of the 7 banks of GPIOs Interrupts can be triggered by rising and or falling edge specified for each interrupt capable GPIO signal e DMA events Upto 10 unique GPIO DMA events from Bank 0 Upto 7 GPIO bank aggregated DMA event signals one from each of the 7 banks of GPIOs e Set clear functionality Firmware writes 1 to corresponding bit position s to set or to clear GPIO signal s This allows multiple firmware processes to toggle GPIO output signals without critical section protection disable interrupts program GPIO re enable interrupts to prevent context switching to anther process during GPIO programming e Separate Input Output registers e Output register in addition to set clear so that if preferred by firmware some GPIO output signals can be toggled by direct write to the output register s e Output register when read reflects output drive status This in addition to the input register reflecting pin status and open drain UO cell allows wired logic be implemented For more detailed information on GPIOs see the Documentation Support section for the General Purpose Input Output GPIO Reference Guide 5 6 1 GPIO Peripheral Input Output Electrical Data Timing Table 5 10 Timing Requirements for GPIO Inputs see Figure 5 12
53. Z Von opp DDR Row Address Strobe DDR_CAS Vo VO Z Von opp DDR Column Address Strobe DDR_WE W10 VO Z Von opp DDR Write Enable DDR_CS T8 VO Z Von opp DDR Chip Select DDR_CKE V10 VO Z Von opp DDR Clock Enable Co U15 VO Z Von opp Data mask outputs e DQMO For DDR_DQ 7 0 ici T12 VO Z VDD DDR e DQM1 For DDR_DQ 15 8 DDR_DQS V15 Volz Viibis Data strobe input outputs for each byte of the 16 bit data bus used to 1 synchronize the data transfers Output to DDR when writing and inputs when reading Ste V12 VO Z Vop Cp e DQS1 For DDR_DQ 15 8 e DQSO For DDR_DQ 7 0 DDR_BA 2 V8 VO Z VDD_DDR Bank select outputs Two are required for 1Gb DDR2 memories DDR_BA 1 U7 VO Z VDD_DDR Bank select outputs Two are required for 1Gb DDR2 memories DDR_BA 0 U8 VO Z VDD_DDR Bank select outputs Two are required for 1Gb DDR2 memories DDR_A13 U6 VO Z VDD_DDR DDR Address Bus bit 13 DDR_A12 V7 VO Z Von opp DDR Address Bus bit 12 DDR_A11 W7 VO Z Von opp DDR Address Bus bit 11 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 20 Device Overview 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback d TEXAS TMS320DM355
54. allows serial communication with other SPI devices through a 3 or 4 wire interface Clock Data In Data Out and Enable The SPI supports the following features e Master mode operation e 2 chip selects for interfacing to multiple slave SPI devices e 30or4 wire interface Clock Data In Data Out and Enable e Unique interrupt for each SPI port e Separate DMA events for SPI Receive and Transmit e 16 bit shift register e Receive buffer register e Programmable character length 2 to 16 bits e Programmable SPI clock frequency range e 8 bit clock prescaler e Programmable clock phase delay or no delay e Programmable clock polarity The SPI modules do not support the following features e Slave mode Only Master mode is supported in DM355 Master mode means that DM355 provides the serial clock e GPIO mode GPIO functionality is supported by the GIO modules for those SPI pins that are multiplexed with GPIO signals 5 12 1 SPI Electrical Data Timing Table 5 28 Timing Requirements for SPI All Modes see Figure 5 36 NO DM355 SE MIN MAX 1 Late Cycle time SPI_CLK 37 037 ns ns 2 tw CLKH Pulse duration SPl_CLK high All Master Modes 0 45 T 0 55 T ns 3 tw CLKL Pulse duration SPI_CLK low All Master Modes 0 45 T 0 55 T ns 1 Tse SPI_CLK period is equal to the SPI module clock divided by a configurable divider lt 4 1 gt 2 J 4 3 SPIx_CLK Clock Polarity 0 SPIx_
55. an C two wire serial interface for control of external peripherals This interface is multiplexed with GIO signals Table 2 16 EC Terminal Functions TERMINAL i ge TYPE OTHER DESCRIPTION NAME NO I12C_SDA 12C Serial data GIO015 RIS dee Vos GIO GIO015 12C_SCL 12C Serial clock GIO014 Rig de Vos GIO GIO014 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 2 4 11 Serial Interface The includes three independent serial ports These interfaces are multiplexed with GIO and other signals Table 2 17 SPI Terminal Functions TERMINAL TYPE OTHER 3 DESCRIPTION NAME NO SPIO_SCLK C12 V O Z Von SPIO Clock SPIO_SDENAJ 0 SPIO Chip select 0 GIO103 B12 Ge Von GIO GIO 103 GIO007 GIO GIO 007 SPI0_ SDENA 1 SR Oz Von SP10 Chip select 1 SPIO_SDI SPIO Data in GIO102 Ale aler Voo GIO GIO 102 SPIO_SDO B11 VO Z Vop SPIO Data out SPI1_SCLK SPI1 Clock GIO010 C13 aler Voo Teo GIO 010 SPI1 Chip select 0 Ge E13 VOZ Vbo GIO GIO 011 Active low during MMC SD boot can be used as MMC SD power control SPI1_SDI SPI1 Data in or GIO009 A13 VO Z Vop SPI1 Chip select SPI1_SDENAI 1
56. bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 00 GIO GIO 086 GIO GIO 087 YINO GIO086 P5 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE PINMUX0 10 YIN_7 GIO raw 00 0 YCC 16 bit time multiplexed between luma Y 00 38 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID UI Supply PD State CAM_HD N5 VO CCDC Vpp_vIN PD in Horizontal synchronization signal that can be PINMUX0 11 CAM_ GIO085 GIO either an input slave mode or an output HD master mode Tells the CCDC when a new line starts GIO GIO 085 CAM_VD R4 VO CCDC VDD_VIN PD in Vertical synchronization signal that can be PINMUXO 12 CAM_ GIO084 GIO either an input slave mode or an output VD master mode Tells the CCDC when a new frame starts GIO GIO 084 CAM_WEN_FIE R5 VO CCDC VDD_VIN PD in Write enable input signal is used by external PINMUX0 13 CAM_ LD GIO083 GIO device AFE TG to gate the DDR output of WEN the CCDC module Alternately the field identification input plus signal is used by external devic
57. buffer memory and DMA control to ensure efficient use of the DDR2 burst bandwidth The shared buffer logic memory is a unique block that is tailored for seamlessly integrating the VPSS into an image video processing system It acts as the primary source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from to DDR2 In order to efficiently utilize the external DDR2 bandwidth the shared buffer logic memory interfaces with the DMA system via a high bandwidth bus 64 bit wide The shared buffer logic memory also interfaces with all the VPFE and VPBE modules via a 128 bit wide bus The shared buffer logic memory divided into the read amp write buffers and arbitration logic is capable of performing the following functions It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large bandwidth requirements and the real time requirements of the VPSS modules Because it is possible to configure the VPSS modules in such a way that DDR2 bandwidth is exceeded a set of user accessible registers is provided to monitor overflows or failures in data transfers Video Processing Front End VPFE The VPFE or Video Processing Front End block is comprised of the CCD Controller CCDC Image Pipe IPIPE and Hardware 3A Statistic Generator H3A These modules are described in the sections that follow 5 9 1 1 CCD Controller CCDC The CCDC is responsible for accepting raw unprocessed image video
58. clamp circuit or an intrinsic diode Positive current results from an applied input or output voltage that is more than 0 5 V higher more positive than the supply voltage Vpp Vopa_pLL Vpp_usB Vpp_ppr for dual supply macros Negative current results from an applied voltage that is more than 0 5 V less more negative than the Vss voltage Submit Documentation Feedback Device Operating Conditions 91 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 da TEXAS Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 4 2 Recommended Operating Conditions MIN NOM MAX UNIT CVpp Supply voltage Core 1 235 1 3 1 365 V VDDA PU Supply voltage PLL1 1 235 1 3 1 365 V VDDA bz Supply voltage PLL2 1 235 1 3 1 365 V VDDD13_USB Supply voltage USB Digital 1 235 1 3 1 365 V VDDA13_USB Supply voltage USB Analog 1 235 1 3 1 365 V VDDA33_USB Supply voltage USB Analog 3 135 3 3 3 465 V Supply Voltage VDDA33_USB_PLL Supply voltage USB Common PLL 3 135 3 3 3 465 V VDD_DDR Supply voltage DDR2 MDDR 1 71 1 8 1 89 V VDDA33_DDRDLL Supply voltage DDR DLL Analog 3 135 3 3 3 465 V Vop vw Supply voltage Digital video In 3 1385 3 3 3 465 V Von vom Supply voltage Digital Video Out 3 135 3 3 3 465 V VDDA18_DAC Supply voltage DAC Analog 1 71 1 8 1 89 V Vnp Supply voltage I Os 3 135 3 3 3 465 V Vss Supply ground Co
59. data from a sensor CMOS or CCD In addition the CCDC can accept YUV video data in numerous formats typically from so called video decoder devices In the case of raw inputs the CCDC output requires additional image processing to transform the raw input image to the final processed image This processing can be done either on the fly in the Preview Engine hardware ISP or in software on the ARM and MPEG JPEG co processor subsystems In parallel raw data input to the CCDC can also used for computing various statistics 3A Histogram to eventually control the image video tuning parameters The CCDC is programmed via control and parameter registers DM355 performance is enhanced by its dedicated hard wired MPEG JPEG co processor MJCP The MJCP performs all the computational operations required for JPE and MPEG4 compression These operations can be invoked using the xDM xDIAS for Digital Media APIs For more information refer to the xDIAS DM xDIAS for Digital Media User s Guide SPRUEC8 The following features are supported by the CCDC module e Support for conventional Bayer pattern e Generates HD VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator e Support for progressive and interlaced sensors hardware support for up to 2 fields and firmware support for higher number of fields typically 3 4 and 5 field sensors e Support for up to 67 5 MHz sensor clock 270 MHz speed
60. following products support development of DM355 based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Hardware Development Tools Extended Development System XDS Emulator supports TMS320DM355 DMSoC multiprocessor system debug EVM Evaluation Module For a complete listing of develooment support tools for the TMS320DM355 DMSoC platform visit the Texas Instruments web site on the Worldwide Web at http www ti com For information on pricing and availability contact the nearest TI field sales office or authorized distributor 2 6 2 Device Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed
61. internal oscillator input e PLL pre divider value is fixed to 8 e PLL multiplier value is programmable e PLL post divider e Only SYSCLK 4 1 are used e SYSCLK1 divider value is fixed to 2 e SYSCLK2 divider value is fixed to 4 e SYSCLK3 divider value is programmable e SYSCLK4 divider value is programmable to 4 or 2 e SYSCLKBP divider value is fixed to 3 e SYSCLK1 is routed to the ARM Subsystem e SYSCLK2 is routed to peripherals e SYSCLK3 is routed to the VPBE module e SYSCLK4 is routed to the VPSS module e AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1 e SYSCLKBP is routed to the output pin CLKOUT2 Table 3 10 PLLC1 Output Clocks Output Clock Used By PLLDIV Notes Divider SYSCLK1 ARM Subsystem MPEG and JPEG Co Processor 2 Fixed divider SYSCLK2 Peripherals 4 Fixed divider SYSCLK3 VPBE VENC module n Programmable divider used to get 27 MHz for VENC SYSCLK4 VPSS 4 or 2 Programmable divider AUXCLK Peripherals CLKOUT1 none No divider SYSCLKBP CLKOUT2 13 Fixed divider 74 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 CLKMODE PLLEN CLKIN SYSCLK1 ARM and MPEG JPEG Coprocessor SYSCLK2 peripherals SYSCLK3 VPBE Post DIV 2 or 1 OSCIN PLL
62. is handled by hardware control and does not involve the ROM In the case of OneNAND the user is responsible for putting any necessary boot code in the OneNAND s boot page This code shall configure the AEMIF module for the OneNAND device After the AEMIF module is configured booting will continue immediately after the OneNAND s boot page with the AEMIF module managing pages thereafter Furthermore in case of Fast Boot from AEMIF OneNAND the user is responsible for checking the state of the FASTBOOT bit in the BOOTCFG register in the System Module in order to respond properly by executing any required device init bringing mDDR out of self refresh and branching to user entry point in mDDR The RBL supports 3 distinct boot modes BTSEL 1 0 00 ARM NAND Boot BTSEL 1 0 10 ARM MMC SD Boot BTSEL 1 0 11 ARM UART Boot If NAND boot fails then MMC SD mode is tried If MMC SD boot fails then MMC SD boot is tried again If UART boot fails then UART boot is tried again RBL uses GIO61 to indicate boot status can use to blink LED After reset GIO61 is initially driven low e g LED off If NAND boot fails and then MMC SD boot fails then GIO61 shall toggle at 4Hz while MMC SD boot is retried If MMC SD boot fails then GIO61 shall toggle at 4Hz while MMC SD boot is retried If UART boot fails then GIO61 shall toggle at 2Hz while UART boot is retried When boot is successful just before prog
63. m GIO GIO 062 default set by AECFG 0 AECFG 0 sets default for PinMux2 EM_A0O_BA1 AEMIF Address Width OneNAND or NAND PinMux2 EM_A13_3 AEMIF Address Width OneNAND or NAND O AEMIF address bits 1 GIO 67 57 EM AO P16 VO AEMI Vpp out L Async EMIF Address Bus bit 07 PINMUX2 0 EM_A1 GIO061 F 3 GIO GIO GIO 061 Used by ROM Bootloader to default set by provide progress status via LED active low AECFG 0 EM AO6G P18 VO AEMI Vpp out L Async EMIF Address Bus bit 06 PINMUX2 0 EM_A1 GIO060 F 3_3 GIO GIO GIO 060 default set by AECFG 0 EM_A05 R19 VO AEMI Vpp out L Async EMIF Address Bus bit 05 PINMUX2 0 EM_A1 GIO059 F 3 GIO GIO GIO 059 default set by AECFG 0 EM_A04 P15 VO AEMI Vpp out L Async EMIF Address Bus bit 04 PINMUX2 0 EM_A1 GIO058 F 3 GIO GIO GIO 058 default set by AECFG 0 EM_AO03 N18 VO AEMI Vpp out L Async EMIF Address Bus bit 03 PINMUX2 0 EM_A1 GIO057 F 3 GIO GIO GIO 057 default set by AECFG 0 EM_A02 N15 VO AEMI Vpp out L Async EMIF Address Bus bit 02 F NAND SM xD CLE Command Latch Enable output 44 Device Overview Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type
64. m GIO GIO 065 default set by AECFG 0 System AECFG 3 0 sampled at Power on Reset to set AEMIF Configuration AECFG 3 sets default for PinMux2 EM_D15_8 AEMIF Default Bus Width 0 16 or 1 8 bits EM_A10 R18 VO AEMI Von PU inH Async EMIF Address Bus bit 10 PINMUX2 0 EM_A1 GIO064 F 3 AECFG 2 GIO syste m GIO GIO 064 default set by AECFG 0 System AECFG 3 0 sampled at Power on Reset to set AEMIF Configuration AECFG 2 1 sets default for PinMux2 EM_BAO AEMIF EM_BAO Definition 00 EM_BAO 01 EM_A14 10 GIO 054 11 rsvd Submit Documentation Feedback Device Overview 43 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State EM_AO9 P17 VO AEMI Vpp PD inL Async EMIF Address Bus bit 09 PINMUX2 0 EM_A1 GIO063 F 3 AECFG 1 GIO syste m GIO GIO 063 default set by AECFG 0 System AECFG 3 0 sampled at Power on Reset to set AEMIF Configuration AECFG 2 1 sets default for PinMux2 EM_BAO AEMIF EM_BAO Definition 00 EM_BAO 01 EM_A14 10 GIO 054 11 rsvd EM AO T19 VO AEMI Vpp PU in H Async EMIF Address Bus bit 08 PINMUX2 0 EM_A1 GIO062 F 3 AECFG 0 GIO syste
65. more information on the PLL controllers 3 6 1 PLL Controller Module The DM355 has two PLL controllers that provide clocks to different components of the chip PLL controller 1 PLLC1 provides clocks to most of the components of the chip PLL controller 2 PLLC2 provides clocks to the DDR PHY As a module the PLL controller provides the following e Glitch free transitions on changing PLL settings e Domain clocks alignment e Clock gating e PLL bypass e PLL power down The various clock outputs given by the PLL controller are as follows e Domain clocks SYSCLKn e Bypass domain clock SYSCLKBP e Auxiliary clock from reference clock AUXCLK Various dividers that can be used are as follows e Pre PLL divider PREDIV e Post PLL divider POSTDIV e SYSCLK divider PLLDIV1 PLLDIVn e SYSCLKBP divider BPDIV Multipliers supported are as follows e PLL multiplier control PLLM Submit Documentation Feedback Detailed Device Description 73 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 6 2 PLLC1 da TEXAS INSTRUMENTS www ti com PLLC1 provides most of the DM355 clocks Software controls PLLC1 operation through the PLLC1 registers The following list Table 3 10 and Figure 3 3 describe the customizations of PLLC1 in the DM355 e Provides primary DM355 system clock e Software configurable e Accepts clock input or
66. of the signals is inverted then the timing references of that signal are also inverted P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 3 Use which ever value is greater The ASP does not have a duty cycle specification just ensure that the minimum pulse duration specification is met 138 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 36 Switching Characteristics Over Recommended Operating Conditions for ASP see Figure 5 41 DM355 NO PARAMETER UNIT MIN MAX 2 te CkRX Cycle time CLKR X CLKR X int 38 5 or 2P ns 17 td CLKS CLKRX Delay time CLKS high to internal CLKR X CLKR X int 1 24 3 tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X int C 1 C 1 ns 4 t Delay ti CLKR high to int FSR valid Seidl SS g elay time igh to internal vali ns d CKRH FRV y g CLKR ext 3 25 9 t Delay ti CLKX high to int FSX valid aoe i elay time igh to internal vali ns SEEEN 7 S CLKX ext 3 25 42 tdis CKXH Disable time DX high impedance following last data CLKX int 12 ns DXHZ bit from CLKX high CLKX ext 12 ns 13 It Delay ti CLKX high to DX valid GE 12 d i elay time igh to vali SE S S CLKX ext 3 25 ns Delay time FSX high to DX valid FSX i
67. order to ensure device reliability the DM355 requires the following power supply power on and power off sequences See table Table 5 1 for a description of DM355 power supplies Power On 1 Power on 1 3 V CVpp Vppa ps Vonpaa use Vopa13_USB 2 Power on 1 8 V Vpp opp Vpopaug Vopais_ DAC 3 Power on 3 3 V Dypp Vopass_pprott Vppass use Vonaaa uses PLL Voo vins Nep vout You may power on the 1 8 V and 3 3 V power supplies simultaneously Power Off 1 Power off 3 3 V Dypp Vopas3_pproLt Vopaaa use Vopa33_usB PLL Von vin Vpop vout 2 Power off 1 8 V Von opp Vopais Vopais_pac 3 Power off 1 3 V CVpp Vopa paus VDDD13_USB VDDA13_USB You may power off the 1 8 V and 3 3 V power supplies simultaneously Note that when booting the DM355 from OneNAND you must ensure that the OneNAND device is ready with valid program instructions before the DM355 attempts to read program instructions from it In particular before you release DM355 reset you must allow time for OneNAND device power to stabilize and for the OneNAND device to complete its internal copy routine During the internal copy routine the OneNAND device copies boot code from its internal non volatile memory to its internal boot memory section Board designers typically achieve this requirement by design of the system power and reset supervisor circuit Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization times and for OneNAND boot copy times
68. programmable hardware image processing module that is responsible for transforming raw unprocessed image video data from a sensor CMOS or CCD into YCbCr 422 data that is amenable for compression or display The IPIPE can also be configured to operate in a resize only mode which allows YCbCr 422 to be resized without applying the processing of every module in the IPIPE Typically the output of the IPIPE is used for both video compression and displaying it on an external display device such as a NTSC PAL analog encoder or a digital LCD The IPIPE is programmed via control and parameter registers The following features are supported by the IPIPE The input interface extracts valid raw data from the CCD raw data and then various modules in IPIPE process the raw CCD data The 2D noise filter module reduces impulse noise in the raw data and adjusts the resolution of the input image The 2D pre filter adjusts the resolution of the input image and remove line crawl noise The white balance module applies two gain adjustments to the data a digital gain total gain and a white balance gain The Color Filter Array CFA interpolation module implements CFA interpolation The output from the CFA interpolation module is always RGB formatted data The RGB2RGB blending module applies a 3x3 matrix transform to the RGB data generated by the CFA interpolation module The gamma correction module independently applies gamma correction to each RGB componen
69. the chip is in its default configuration This section highlights the default configurations associated with PLLs clocks ARM boot mode and AEMIF NOTE Default configuration is the configuration immediately after POR warm reset and max reset and just before the boot process begins The boot ROM updates the configuration See Section 3 12 for more information on the boot process 3 11 1 Device Configuration Pins The device configuration pins are described in Table 3 15 The device configuration pins are latched at reset and allow you to configure all of the following options at reset e ARM Boot Mode e Asynchronous EMIF pin configuration These pins are described further in the following sections NOTE The device configuration pins are multiplexed with AEMIF pins After the device configuration pins are sampled at reset they automatically change to function as AEMIF pins Pin multiplexing is described in Section 3 8 Table 3 15 Device Configuration Default Setting by internal Device Sampled pull up Configuration Input Function Pin pull down Device Configuration Affected BTSEL 1 0 Selects ARM boot mode EM_A 13 12 00 If any ROM boot mode is selected GIO61 00 Boot from ROM NAND NAND is used to indicated boot status 01 Boot from AEMIF If NAND boot is selected CEO is used for 10 Boot from ROM NAND Use AECFG 3 0 to configure MMC SD AEMIF pins for NAND 11 Boot from ROM UART If AEMI
70. ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 VCLKIN Positive Edge Clocking TN ff NO VCLKIN A ef YF YW fF Negative Edge Clocking je 9 gt l A VCLKIN PCLK or EXTCLK B VCTL HSYNC VSYNC and FIELD Figure 5 28 VPBE Input Timing With Respect to PCLK and EXTCLK Table 5 23 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK see Figure 5 29 DM355 NO PARAMETER UNIT MIN MAX 11 ta vCLKIN VCTLV Delay time VCLKIN edge to VCTL valid 13 3 ns 12 ta VCLKIN VCTLIV Delay time VCLKIN edge to VCTL invalid 2 ns 13 ta VCLKIN VDATAV Delay time VCLKIN edge to VDATA valid 13 3 ns 14 tavcLKIN vpaTalv Delay time VCLKIN edge to VDATA invalid 2 ns 1 The VPBE may be configured to operate in either positive or negative edge clocking mode When in positive edge clocking mode the rising edge of VCLKIN is referenced When in negative edge clocking mode the falling edge of VCLKIN is referenced 2 VCLKIN PCLK or EXTCLK 3 VCTL HSYNC VSYNC FIELD and LCD_OE VCLKIN f _ YY _ Positive Edge Clocking VCLKIN Negative Edge Clocking COO if NXS Sf Sf 11 WK 12 gc 13 lt gt 14 mmm TAO A X A VCLKIN PCLK or EXTCLK B VCTL HSYNC VSYNG FIELD and LCD_OE C VDATA COUT 7 0 YOUT 7 0 R 7 3 G 7 2 and B 7 3 Figure 5 29 VPBE
71. to Vss RSV07 K2 GND Reserved This signal should be connected to Vss NC H8 No connect Vpp_vIN P6 PWR Power for Digital Video Input IO 3 3 V Vop vn P7 PWR Power for Digital Video Input IO 3 3 V Vpp_vIN P8 PWR Power for Digital Video Input IO 3 3 V Vpp_vout F6 PWR Power for Digital Video Output IO 3 3 V Vop vour F7 PWR Power for Digital Video Output IO 3 3 V VDD_vouT F8 PWR Power for Digital Video Output IO 3 3 V VDD_DDR M9 PWR Power for DDR I O 1 8 V VDD_DDR P9 PWR Power for DDR I O 1 8 V VDD_DDR P10 PWR Power for DDR I O 1 8 V VDD_DDR P11 PWR Power for DDR I O 1 8 V VDD_DDR P12 PWR Power for DDR I O 1 8 V VDD_DDR P13 PWR Power for DDR I O 1 8 V VDD_DDR P14 PWR Power for DDR I O 1 8 V VDD_DDR RQ PWR Power for DDR I O 1 8 V VDD_DDR R12 PWR Power for DDR I O 1 8 V VDD_DDR T14 PWR Power for DDR I O 1 8 V VDDA PLL1 G12 PWR Analog Power for PLL1 1 3 V VDDA ps H9 PWR Analog Power for PLL2 1 3 V CVpp A1 PWR Core power 1 3 V CVpp A10 PWR Core power 1 3 V CVpp B19 PWR Core power 1 3 V CVpp C4 PWR Core power 1 3 V CVpp G6 PWR Core power 1 3 V CVpp G11 PWR Core power 1 3 V CVpp H10 PWR Core power 1 3 V CVpp H13 PWR Core power 1 3 V CVpp H17 PWR Core power 1 3 V CVpp J11 PWR Core power 1 3 V CVpp J12 PWR Core power 1 3 V CVpp J13 PWR Core power 1 3 V CVpp K6 PWR Core power 1 3 V CVpp K11 PWR Core powe
72. to e N EM_CE 1 0 high SS 1 Output setup time EM BA OI valid to 20 tsu EMBAV EMWEL EM WE on BA 1 0 WS E ns Output hold time EM_WE high to 5 21 th EMWEH EMBAIV EM_BA T 0 invalid WH E ns Output setup time EM_A 13 0 valid to p 22 tsu EMAV EMWEL EM WE E A 13 0 WS E ns Output hold time EM_WE high to 23 thEMWEHEMAI MAD ZO invalid GER ns EM_WE active low width EW 0 WST E ns 24 twEMWEL EE SCHEER EM_WE active low width EW 1 WST EWC 16 E ns 25 ta EMWAITH Delay time from EM_WAIT deasserted to 4E ns EMWEH EM_WE high Output setup time EM_D 15 0 valid to x 26 tsu EMDV EMWEL EM WE E HIH WS E ns 108 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 14 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module see Figure 5 14 and Figure 5 15 continued DM355 UNI NO PARAMETER MIN Nom MAX T Output hold time EM_WE high to X 27 th EMWEH EMDIV EM_D 15 0 invalid WH E ns r 3 GE EM_CE 1 0 d ee gt gt ew ats D kA 5 k 8 9 Le k 7 4 Li 10 gt EM_OE S y 113 12 ba EM_D 15 0 EM_WE Figure 5 14 Asynchronous Memory Read Timing for EMIF
73. 11 VO Z VDD_DDR DDR Data Bus bit 00 DDR_GATE wis Volz VDD DDR DDR Loopback signal for external DQS gating Route to DDR and back to 0 DDR_GATEO with same constraints as used for DDR clock and data DDR_GATE V17 Volz Vee aed DDR Loopback signal for external DQS gating Route to DDR and back to 1 DDR_GATEO with same constraints as used for DDR clock and data Seege Vio a0 Mio ee ect nee mre Vssa_DLL R11 VO Z VDD_DDR DDR Ground for the DDR DLL GER R10 VO Z VDD_DDR DDR Power 3 3 V for the DDR DLL DDR_ZN T9 Volz Vis cap DDR Reference output for drive strength calibration of N and P channel outputs Tie to ground via 50 ohm resistor 0 5 tolerance Submit Documentation Feedback Device Overview 21 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 2 4 5 GPIO The General Purpose I O signals provide generic I O to external devices Most of the GIO signals are multiplexed with other functions da TEXAS INSTRUMENTS www ti com Table 2 11 GPIO Terminal Functions TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO GIO GIO 000 Active low during MMC SD boot can be used as MMC SD power GIO000 C16 VO Z Von control Can be used as external clock input for Timer 3 GIO001 E14 VO Z Vop GIO GIO 001 Can be used as external clock input for
74. 1C7 1000 0x01C7 3FFF 12K V d Reserved 0x01CC 0000 0x01CD FFFF 128K V q Multimedia SD 1 0x01E0 0000 0x01E0 1FFF 8K v V ASPO 0x01E0 2000 0x01E0 3FFF 8K V V ASP1 0x01E0 4000 0x01E0 5FFF 8K v V UART2 0x01E0 6000 0x01E0 63FF 1K Vy V Reserved 0x01E0 6400 0x01E0 FFFF 39K V V ASYNC EMIF Control 0x01E1 0000 0x01E1 OFFF 4K V V Multimedia SD 0 0x01E1 1000 0x01E1 FFFF 60K V Reserved 0x01E2 0000 0x01FF FFFF 1792K V V ASYNC EMIF Data CE0 0x0200 0000 0x03FF FFFF 32M d d ASYNC EMIF Data CE1 0x0400 0000 0x05FF FFFF 32M d d Reserved 0x0A00 0000 OxOBFF FFFF 32M V V Reserved 0x0C00 0000 OxOFFF FFFF 64M V q 8 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 3 Pin Assignments TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings 2 3 1 Pin Map Bottom View Figure 2 1 through Figure 2 4 show the pin assignments in four quadrants A B C and D Note that micro vias are not required Contact your TI representative for routing recommendations J RSV01 Vss CINO CIN3 CIN2 Vss VREF VDDA33_USB Vssa_PLL2 H Vss V
75. 2 CIN2 PD i MR GIO096 J5 O Z Bee e YCC 8 bit which allows for two simultaneous decoder inputs it is time E multiplexed between luma and chroma of the upper channel Y CB CR 02 GIO GIO 097 Standard CCD Analog Front End AFE Raw 09 e YCC 16 bit Time multiplexed between chroma CB SR 01 CIN1 L VOZ PD ee SE GIO095 3 Wi VDD VIN e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 01 GIO GIO 095 Standard CCD Analog Front End AFE Raw 08 e YCC 16 bit Time multiplexed between chroma CB SR 00 CINO uo PD i saith it Glo094 J3 Wi VBD viN e YCC 8 bit which allows for two simultaneous decoder inputs it is time e multiplexed between luma and chroma of the upper channel Y CB CR 00 GIO GIO 094 Standard CCD Analog Front End AFE Raw 07 e YCC 16 bit Time multiplexed between chroma Y 07 YIN7Z PD eg GIO093 L5 O Z VDD NIN e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 07 GIO GIO 093 Standard CCD Analog Front End AFE Raw 06 e YCC 16 bit Time multiplexed between chroma Y 06 YIN6 PD oo GIO092 M4 VOlZ Vov e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 06 GIO GIO 092 1 I Input O Output Z High im
76. 2048 SDRAM autoinitialization Self refresh mode Partial array self refresh for mDDR Power down mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Little endian For details on the DDR2 Memory Controller refer to the DDR mDDR Peripheral Reference Guide 5 7 2 1 DDR2 mDDR Memory Controller Electrical Data Timing TI only supports DDR2 mDDR board designs that follow the guidelines described in the application note titled TMS320DM355 DDR2 mDDR Board Design Application Note Refer to this application note for information on board design recommendations and guidelines for DDR2 and mDDR 112 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 8 MMC SD TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 The DM355 includes two separate MMC SD Controllers which are compliant with MMC V3 31 Secure Digital Part 1 Physical Layer Specification V1 1 and Secure Digital Input Output SDIO V1 0 specifications The MMC SD Controller has following features e MultiMediaCard MMC e Secure Digital SD Memory Card e MMC SD protocol support e SDIO protocol support e Programmable clock frequency e 256 bit Read Write FIFO to lower system overhead e Slave EDMA transfer capability The MMC SD Controller does not support SPI mode 5
77. 3 3 V Von M13 PWR Power for Digital IO 3 3 V Von N11 PWR Power for Digital IO 3 3 V Von N12 PWR Power for Digital IO 3 3 V Vase Mai C10 GND System oscillator 24 MHz ground Vss_mx2 P1 GND Video oscillator 27 MHz ground Vasen PU H12 GND Analog Ground for PLL1 Vssa_PLL2 J9 GND Analog Ground for PLL2 Vss A5 GND Digital ground Vss A8 GND Digital ground Vss A19 GND Digital ground Vss B5 GND Digital ground Vss B8 GND Digital ground Vss B10 GND Digital ground Vss D1 GND Digital ground Vss E2 GND Digital ground Vss E15 GND Digital ground Vss G2 GND Digital ground Vss G9 GND Digital ground Vss H1 GND Digital ground Vss H2 GND Digital ground Vss H6 GND Digital ground Vss H11 GND Digital ground Vss H14 GND Digital ground Vss J2 GND Digital ground Vss J6 GND Digital ground Vss J10 GND Digital ground Vss J14 GND Digital ground Vss K3 GND Digital ground Submit Documentation Feedback Device Overview 53 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State Vss K9 GND Digital ground Vss K10 GND Digital ground Vss K14 GND Digi
78. 320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State DDR_DQSj 0 V12 UO DDR VDD_DDR in Data strobe input outputs for each byte of the 16 bit data bus used to synchronize the data transfers Output to DDR when writing and inputs when reading DQSO0 For DDR_DQ 7 0 DDR_BA 2 V8 UO DDR Vop opp out L Bank select outputs Two are required for 1Gb DDR2 memories DDR BA U7 VO DDR VDD DDR out L Bank select outputs Two are required for 7 1Gb DDR2 memories DDR_BA 0 u8 UO DDR VDD_DDR out L Bank select outputs Two are required for 1Gb DDR2 memories DDR_A13 U6 VO DDR Vop opp out L DDR Address Bus bit 13 DDR_A12 V7 UO DDR VDD_DDR out L DDR Address Bus bit 12 DDR_A11 W7 UO DDR VDD_DDR out L DDR Address Bus bit 11 DDR_A10 V6 VO DDR VDD_DDR out L DDR Address Bus bit 10 DDR_A09 W6 VO DDR VDD_DDR out L DDR Address Bus bit 09 DDR_A08 W5 UO DDR Vpp_ppR out L DDR Address Bus bit 08 DDR_A07 V5 VO DDR Vop opp out L DDR Address Bus bit 07 DDR_A06 U5 UO DDR Vpp_ppR out L DDR Address Bus bit 06 DDR_A05 WA UO DDR Vop opp out L DDR Address Bus bit 05 DDR_A04 V4 UO DDR Vpp_ppR
79. 355 Digital Media System on Chip DMSoC The ARM subsystem is designed to give the ARM926EJ S ARM9 master control of the device In general the ARM is responsible for configuration and control of the device including the components of the ARM Subsystem the peripherals and the external memories TMS320DM35x DMSoC Asynchronous External Memory Interface EMIF Reference Guide This document describes the asynchronous external memory interface EMIF in the TMS320DM35x Digital Media System on Chip DMSoC The EMIF supports a glueless interface to a variety of external devices TMS320DM35x DMSoC Universal Serial Bus USB Controller Reference Guide This document describes the universal serial bus USB controller in the TMS320DM35x Digital Media System on Chip DMSoC The USB controller supports data throughput rates up to 480 Mbps It provides a mechanism for data transfer between USB devices and also supports host negotiation TMS320DM35x DMSoC Audio Serial Port ASP Reference Guide This document describes the operation of the audio serial port ASP audio interface in the TMS320DM35x Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com SPRUED4 SPRUED9 SPRUEEO SPRUEE2 SPRUEE4 SPRUEES5 SPRUEE6 TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Digital Media System on Chip DMSoC The primary audio modes that are supported by the ASP ar
80. 5 2 AEMIF Timing Configuration 3 12 When AEMIF is enabled the wait state registers are reset to the slowest possible configuration which is 88 cycles per access 16 cycles of setup 64 cycles of strobe and 8 cycles of hold Thus with a 24 MHz clock at MXI the AEMIF is configured to run at 6 MHz 88 which equals approximately 68 kHz by default See the Asynchronous External Memory Interface AEMIF Peripheral Reference Guide for more information on the AEMIF Device Boot Modes The DM355 ARM can boot from either Async EMIF AEMIF OneNandq or from ARM ROM as determined by the setting of the device configuration pins BTSEL 1 0 The BTSEL 1 0 pins can define the ROM boot mode further as well Submit Documentation Feedback Detailed Device Description 83 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 www ti com The boot selection pins BTSEL 1 0 determine the ARM boot process After reset POR warm reset or max reset ARM program execution begins in ARM ROM at 0x0000 8000 except when BTSEL 1 0 indicating AEMIF AEMIF OneNand boot See Section 3 11 1 for information on the boot selection pins 3 12 1 Boot Modes Overview DM355 s ARM ROM boot loader RBL executes when the BOOTSEL 1 0 pins indicate a condition other than the normal ARM EMIF boot If BTSEL 1 0 01 Asynchronous EMIF AEMIF boot This mode
81. 5 supports the computational operations used for image processing JPEG compression and MPEG1 2 4 video and imaging standards 90 Detailed Device Description Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 4 Device Operating Conditions 4 1 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted All 1 3 V supplies 0 5 V to 1 7 V All digital 1 8 V supplies 0 5 V to 2 5 V Supply voltage ranges All analog 1 8 V supplies 0 5 V to 1 89 V All 3 3 V supplies 0 5 V to 4 4 V All 1 8 V I Os 0 5 V to 2 3 V Input voltage ranges All 3 3 V I Os 0 5 V to 3 8 V VBUS 0 0 V to 5 5 V Clamp current for input or output lclamp 20 mA to 20 mA Operating case temperature ranges To 0 C to 85 C Storage temperature ranges Tstg 65 C to 150 C 3 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 4 All voltage values are with respect to Vss 1 Clamp current flows from an input or output pad to a supply rail through a
82. 60 3 3 Memory Mappimg EE 62 3 4 ARM Interrupt Controller AINTCI neen 63 3 5 Device CIOCking NENNEN r 65 3 6 PLL Controller PLLC sceeeeeeeeeeeeeeeen eee Ke 3 7 Power and Sleep Controller DCH ee K i 3 8 System Control Module 77 3 9 Pin Multiplexing cccseeeeeeeeeeeeeeeeeneeeeeees 78 3 10 Device ReSet EE EEN EE 79 3 11 Default Device ConfigurationS cceeeeeeeeees 80 3 12 Device Boot Modes ENEE EEN 83 3 13 Power Management 85 3 14 64 Bit Crossbar Architecture EN 87 3 15 MPEG JPEG Overview ceeeeeeeeeeeeseeeeeneees 90 Device Operating Conditions ese0 91 4 1 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted aen 91 Submit Documentation Feedback Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 4 2 Recommended Operating Conditions 92 4 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted 93 Peripheral Information and Electrical Specifications ccceee eee e cece eeeeeeeeees 94 5 1 Parameter Information Device Specific Information 94 5 2 Recommended Clock and Control Signal Transition Bebtervl t ag eeeeteiee e ee ge e e 96 5 3 Power SupplieS cccceeeeeeee seen eee eeeeeeeneeee 96 BA B sse See Eege ege 98 5 5 Oscillators and Clocks enee 99 5 6 General Purpose Input Output GPIO
83. 70 The DM355 supports either 24 MHz typical or 36 MHz reference clock crystal or external oscillator input Configurations are shown for both cases 3 5 3 1 Supported Clocking Configurations for DM355 270 24 MHz reference 3 5 3 1 1 DM355 270 PLL1 24 MHz reference All supported clocking configurations for DM355 270 PLL1 with 24 MHz reference clock are shown in Table 3 2 Table 3 6 PLL1 Supported Clocking Configurations for DM355 270 24 MHz reference PRED PLLM POSTDIV PLL1 ARM Peripherals Venc VPSS IV VCO MPEG and JPEG Co Processor 8 m 2 fixed MHz PLLDIV1 SYSC PLLDI SYSCLK2 PLLDIV3 SYSCLK PLLDIV4 SYSCLK4 fixed programmable 2 fixed Ui V2 MHz n 3 2 fixed MHz MHz 4 programmable MHz fixed bypas bypass bypass bypas 2 12 4 6 10 2 4 4 6 s s 8 180 1 540 2 270 4 135 20 27 4 135 8 171 1 513 2 256 5 4 128 25 19 27 4 128 25 8 162 1 486 2 243 4 121 5 18 27 4 121 5 8 153 1 459 2 229 5 4 114 75 17 27 4 114 75 8 144 1 432 2 216 4 108 16 27 4 108 8 135 1 405 2 202 5 4 101 25 15 27 4 101 25 8 126 1 378 2 189 4 94 5 14 27 4 94 5 8 117 1 351 2 175 5 4 87 75 13 27 4 87 75 8 108 1 324 2 162 4 81 12 27 4 81 8 99 1 297 2 148 5 4 74 25 11 27 4 74 25 8 180 2 270 2 135 4 67 5 10 27 2 135 8 162 2 243 2 121 5 4 60 75 9 27 2 121 5 8 144 2 216 2 108 4 54 8 27 2 108 8 126 2 189 2 94 5 4 47 25 7 27 2 94 5 8 108 2 162 2 81 4 40 5 6 27 2 81
84. 8 1 MMC SD Electrical Data Timing Table 5 15 Timing Requirements for MMC SD Module see Figure 5 20 and Figure 5 22 DM355 NO FAST MODE STANDARD MODE UNIT MIN MAX MIN MAX 1 tsucmDVv CLKH Setup time SD_CMD valid before SD_CLK high 6 5 ns 2 trctkH cmpv Hold time SD_CMD valid after SD_CLK high 2 5 5 ns 3 tsuDATV CLKH Setup time SD_DATx valid before SD_CLK high 6 5 ns 4 th CLKH DATV Hold time SD_DATx valid after SD_CLK high 2 5 5 ns 1 For this parameter you may include margin in your board design so that the toh 2 5 ns of the MMC SD device is not degraded at the DM355 input pin Table 5 16 Switching Characteristics Over Recommended Operating Conditions for MMC SD Module see Figure 5 19 through Figure 5 22 DM355 STANDARD NO PARAMETER FAST MODE MODE UNIT MIN MAX MIN MAX 7 f cLK Operating frequency SD_CLK 0 50 0 25 MHz 8 fex m Identification mode frequency SD_CLK 0 400 0 400 KHz 9 tweLkL Pulse width SD_CLK low 7 10 ns ID tw cLkH Pulse width SD_CLK high 7 10 ns II tycLk Rise time SD_CLK 3 10 ns 12 thcLk Fall time SD_CLK 3 10 ns 13 901 Delay time SD_CLK low to SD_CMD transition 7 5 4 75 14 ns MD 14 tycikL pat Delay time SD_CLK low to SD_DATx transition 7 5 4 7 5 14 ns Submit Documentation Feedback Peripheral Information and Electrical Specifications 113 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 d
85. 8 bit address EM_BAO 8 e Glo054 N19 VO Z Wing e In 8 bit mode lowest address bit or can be used as an extra address line EM A14 bit14 when using 16 bit memories GIO GIO 054 EM_D15 Async EMIF Data bus bit 15 G10053 Mi Giz Vos GIO GIO 053 EM_D14 Async EMIF Data bus bit 14 Gl0052 we de Vos GIO GIO 052 EM_D13 Async EMIF Data bus bit 13 GIO051 Mis VOZ Vos GIO GIO 051 EM_D12 Async EMIF Data bus bit 12 GIO050 Ef ue Vos GIO GIO 050 EM_D11 Async EMIF Data bus bit 11 Gl0049 SE BS Vos GIO GIO 049 EM_D10 Async EMIF Data bus bit 10 Gl0048 r VOZ Vos GIO GIO 048 EM_D09 Async EMIF Data bus bit 09 GIO047 SIS vO Z Von GIO GIO 047 EM_D08 Async EMIF Data bus bit 08 Glo046 Fie ue Vos GIO GIO 046 EM_D07 Async EMIF Data bus bit 07 Gl0045 me ya Vos GIO GIO 045 EM_D06 Async EMIF Data bus bit 06 Glo044 Ka Geer Vos GIO GIO 044 EM_D05 Async EMIF Data bus bit 05 G10043 J19 O A Vos GIO GIO 043 EM_D04 Async EMIF Data bus bit 04 GIO042 L15 VOA Vos GIO GIO 042 EM_D03 Async EMIF Data bus bit 03 GIO041 SCH doe Vos GIO GIO 041 EM_D02 Async EMIF Data bus bit 02 10040 g oe Vos GIO GIO 040 EM_D01 Async EMIF Data bus bit 01 G10039 SE ge Vos GIO GIO 039 EM DO Async EMIF Data bus bit 00 GI0038 SS de Vos GIO GIO 038 Submit Documentation Feedback Device Overview 19 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER
86. AIS EM AIS EM AIS GPIO 57 EM A EM_A 3 EM A EM AIS EM AIS GPIO 58 EM Aal EM A4 EM A4 EM A4 EM AM GPIO 59 EM AIS EM AIS EM AIS EM AIS EM AIS GPIO 60 EM_A 6 EM_A 6 EM_A 6 EM_AI6 EM AIgl GPIO 61 EM A EM A EM A EM A EM A GPIO 62 EM_A 8 EM_A 8 EM AIS EM AIS EM AIS GPIO 63 EM AIS EM AIS EM AIg EM Al EM_AI9 GPIO 64 EM AD OI EM_A 10 EM_A 10 EM_A 10 EM_A 10 GPIO 65 EM AD1 EM Ai EM An EM Ai EM Ai GPIO 66 EM_A 12 EM_A 12 EM_A 12 EM_A 12 EM_A 12 GPIO 67 EM AD 3 EM_A 13 EM_A 13 EM_A 13 EM_A 13 GPIO 46 GPIO 46 GPIO 46 GPIO 46 EM_D 8 EM_D 8 GPIO 47 GPIO 47 GPIO 47 GPIO 47 EM Dia EM Dia GPIO 48 GPIO 48 GPIO 48 GPIO 48 EM_D 10 EM_D 10 GPIO 49 GPIO 49 GPIO 49 GPIO 49 EM_D 11 EM_D 11 GPIO 50 GPIO 50 GPIO 50 GPIO 50 EM_D 12 EM_D 12 GPIO 51 GPIO 51 GPIO 51 GPIO 51 EM_D 13 EM_D 13 GPIO 52 GPIO 52 GPIO 52 GPIO 52 EM_D 14 EM_D 14 GPIO 53 GPIO 53 GPIO 53 GPIO 53 EM_D 15 EM_D 15 3 9 2 Software Controlled Pin Multiplexing All pin multiplexing options are configurable by software via pin mux registers that reside in the System Control Module The PinMux0 Register controls the Video In muxing PinMux1 register controls Video Out signals PinMux2 register controls AEMIF signals PinMux3 registers control the multiplexing of the GIO signals the PinMux4 register controls the SPI and MMC SDO0 signals Refer to the ARM Subsystem User s Guide for complete descriptions of
87. Acronym Source Interrupt Acronym Source Number Number 0 VPSSINTO VPSS INTO 32 TINTO Timer 0 TINT12 Configurable via VPSSBL register INTSEL 1 VPSSINT1 VPSS INT1 33 TINT1 Timer 0 TINT34 2 VPSSINT2 VPSS INT2 34 TINT2 Timer 1 TINT12 3 VPSSINT3 VPSS INT3 35 TINT3 Timer 1 TINT34 4 VPSSINT4 VPSS INT4 36 PWMINTO PWMO 1 The total number of interrupts in DM355 exceeds 64 which is the maximum value of the AINTC module Therefore several interrupts are multiplexed and you must use the register ARM_INTMUxX in the System Control Module to select the interrupt source for multiplexed interrupts Refer to the ARM Subsystem Guide for more information on the System Control Module register ARM_INTMUX Submit Documentation Feedback Detailed Device Description 63 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 1 AINTC Interrupt Connections continued Interrupt Acronym Source Interrupt Acronym Source Number Number 5 VPSSINT5 VPSS INT5 37 PWMINT1 PWM 1 6 VPSSINT6 VPSS INT6 38 PWMINT2 PWM2 7 VPSSINT7 VPSS INT7 39 I2CINT 12C 8 VPSSINT8 VPSS INT8 40 UARTINTO UARTO 9 Reserved 41 UARTINT1 UART1 10 Reserved 42 SPINTO O SPIO 11 Reserved 43 SPINTO 1 SPIO 12 USBINT USB OTG Collector 44 GPIOO GPIO 13 RTOINT or RTO or 45 G
88. Analog Front End AFE Raw 12 CIN4 e YCC 16 bit time multiplexed between chroma CB CR 04 GIO098 i Voz PD e YCC 8 bit which allows for two simultaneous decoder inputs it is SPI2 SDI V time multiplexed between luma and chroma of the upper channel 2 DD_VIN SPI2_SDENA 1 Y CB CR 04 SPI SPI2 Data in GIO GIO 0998 Standard CCD Analog Front End AFE Not used e YCC 16 bit time multiplexed between chroma CB CR 06 CIN6 PD e YCC 8 bit which allows for two simultaneous decoder inputs it is GIO100 KS 1 O Z VOD VIN time multiplexed between luma and chroma of the upper channel SPI2_SDO S Y CB CR 06 SPI SPI2 Data out GIO GIO 100 2 4 12 Clock Interface The provides interface with the system clocks Table 2 18 Clocks Terminal Functions TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO CLKOUT1 CLKOUT Output Clock 1 Gooi 14 we Von GIO GIO 018 CLKOUT2 CLKOUT Output Clock 2 jaiooi7 AH ge Vos GIO GIO 017 CLKOUT3 CLKOUT Output Clock 3 Gooise Hi VO Z Von GIO GIO 016 MXI1 A9 l Von Crystal input for system oscillator 24 MHz or 36 MHz Output for system oscillator 24 MHz or 36 MHz When the MX02 is not used pe B9 o Von the MX02 signal can be left open Crystal input for video oscillator 27 MHz Optional use only if 27MHz derived MXI2 R1 V from MXI1 and PLL does not provide sufficient performance for Video DAC DD When the MX12 is not used and powered down the MXI2 s
89. BER 2007 Table 5 34 Switching Characteristics for 12C Timings see Figure 5 40 DM355 NO PARAMETER STANDARD FAST MODE UNIT MODE MIN MAX MIN MAX 16 te SCL Cycle time SCL 10 2 5 us Delay time SCL high to SDA low for a repeated START 17 ta ScLH SDAL erations 9 P 4 7 0 6 us Delay time SDA low to SCL low for a START and a repeated 18 tueDaL scL START condition i 0 6 Ve 19 tw SCLL Pulse duration SCL low 4 7 1 3 US 20 tw SCLH Pulse duration SCL high 4 0 6 US 21 ta SDAV SCLH Delay time SDA valid to SCL high 250 100 ns 22 tv SCLL SDAV Valid time SDA valid after SCL low For 12C devices 0 0 0 9 us Pulse duration SDA high between STOP and START 23 twsDaH conditions i a e ps 28 ta SCLH SDAH Delay time SCL high to SDA high for STOP condition 4 0 6 US 29 Cp Capacitance for each I2C pin 10 10 pF 1 C total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed CAUTION The DM355 DC pins use a standard 4 mA LVCMOS buffer not the slow I OP buffer defined in the UC specification Series resistors may be necessary to reduce noise at the system level et ol 18 Cea khan m Stop Start Repeated Stop Start Figure 5 40 DC Transmit Timings 136 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Me
90. CCD Analog Front End AFE raw 04 YCC 16 bit time multiplexed YIN4 PD between luma Y 04 YCC 08 bit which allows for 2 simultaneous decoder GIO090 P3 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel GE Y CB CR 04 GIO GIO 090 Standard CCD Analog Front End AFE raw 05 YCC 16 bit time multiplexed YINS PD between luma Y 05 YCC 08 bit which allows for 2 simultaneous decoder GIO091 M5 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel SR Y CB CR 05 GIO GIO 091 Standard CCD Analog Front End AFE raw 06 YCC 16 bit time multiplexed YING PD between luma Y 06 YCC 08 bit which allows for 2 simultaneous decoder Glo092 M4 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel DDEVIN Y CB CR 06 GIO GIO 092 26 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 11 GPIO Terminal Functions continued TERMINAL NANE N TYPE OTHER 9 DESCRIPTION Standard CCD Analog Front End AFE raw 07 YCC 16 bit time multiplexed YIN7 PD between luma Y 07 YCC 08 bit which allows for 2 simultaneous decoder GlO0093 L5 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel H Y CB CR O7 GIO GIO 093 Standard CCD Analog
91. CLK Clock Polarity 1 Figure 5 36 SPI_CLK Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 131 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 SPI Master Mode Timings Clock Phase 0 Table 5 29 Timing Requirements for SPI Master Mode Clock Phase 0 see Figure 5 37 DM355 NO UNIT MIN MAX Setup time SPI_DI input valid before SPI_CLK output F 4 su DIV CLKL falling So DI input output Clock Polarity 0 5P 3 ns Setup time SPI_DI i t valid before SPI_CLK output 5 tsu DIV CLKH Pete DI in put output Clock Polarity 1 5P 3 ns e lieki a SPI_DI input valid after SPI_CLK output falling Clock Polarity 0 5P 43 7 eier Gd SPI_DI input valid after SPI_CLK output rising Clock Polarity 1 2 5P 3 e 1 P Period of the SPI module clock in nanoseconds P PLL1 6 Table 5 30 Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode Clock Phase 0 see Figure 5 37 DM355 NO PARAMETER MIN MAX UNIT Delay time SPI_CLK output rising edge to SPI_DO Soe S 8 tacLkH Dov output transition Clock Polarity 0 4 5 ns Delay time SPI_CLK output falling edge to SPI_DO ne S H tacLKL Dov output transition Clock Polarity 1 4 5 ns
92. CLKIN MXI low to CLKOUT3 low 1 8 ns CLKOUTSL 1 The reference points for the rise and fall transitions are measured at Vo_ MAX and VoyMIN Z 2 P 1 CLKOUT3 clock frequency in nanoseconds ns For example when CLKOUT3 frequency is 3 MHz use P 333 3 ns MXI CLKIN x V d Ee kee I l i CS j l KEE gt e4 I I l l apie SVS PDI PAPILIO le 2 ql 3 gt e4 Figure 5 11 CLKOUT3 Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 103 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 6 General Purpose Input Output GPIO The GPIO peripheral provides general purpose pins that can be configured as either inputs or outputs When configured as an output a write to an internal register can control the state driven on the output pin When configured as an input the state of the input is detectable by reading the state of an internal register In addition the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt event generation modes The GPIO peripheral provides generic connections to external devices The GPIO pins are grouped into banks of 16 pins per bank i e bank 0 consists of GPIO 0 15 There are a total of 7 GPIO banks in the because the has 104 GPIOs The GPIO peripheral supports the following e
93. D SM xD RE Read Enable output GIO GIO 034 EM_WAIT G18 VO AEMI Vpp PU in H Async EMIF Async WAIT PINMUX2 9 EM_W GIO033 Ei AIT GIO NAND SM xD RDY _BSY input GIO GIO 033 EM_ADV H16 VO AEMI Vpp PD inL OneNAND Address Valid Detect for PINMUX2 10 EM_A GIO032 F OneNAND interface DV GIO GIO GIO 032 EM_CLK E19 VO AEMI Vpp out L OneNAND Clock signal for OneNAND flash PINMUX2 11 EM_C GIO031 F interface LK Glo GIO GIO 031 ASPO_DX H15 VO ASP5 Vpp in ASPO Transmit Data PINMUX3 0 GIO30 GIO030 120 GIO GIO GIO 030 ASPO_CLKX F18 VO ASP5 Vpp in ASPO Transmit Clock PINMUX3 1 GIlO29 Glo029 120 GIO GIO GIO 029 ASPO_FSX G17 VO ASP5 Vpp in ASPO Transmit Frame Synch PINMUX3 2 GIO28 GlO028 120 GIO GIO GIO 028 ASPO_DR E18 VO ASP5 Vpp in ASPO Receive Data PINMUX3 3 GlO27 GlO027 120 GIO GIO GIO 027 ASPO_CLKR F17 VO ASP5 Vpp in ASPO Receive Clock PINMUX3 4 GIO26 GIO026 120 GIO GIO GIO 026 ASPO_FSR F16 VO ASP5 Vpp in ASPO Receive Frame Synch PINMUX3 5 GIO25 Gloo25 120 GIO GIO GIO 025 MMCSD1_CLK C15 VO MMC Vpp in MMCSD1 Clock PINMUX3 6 GIO24 Glo024 SD GIO GIO GIO 024 MMCSD1_CMD A17 VO MMC Vpp in MMCSD1 Command PINMUX3 7 GIO23 GlO023 SD Glo GIO GIO 023 Submit Documentation Feedback Device Overview 47 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 d Texas Digit
94. DIV1 2 PLLDIV2 4 PLLDIV3 3 programmable PLLDIV4 SYSCLK4 4 or 2 VPSS AUXCLK e Peripherals CLKOUT1 SYSCLKBP BPDIV 3 CLKOUT2 Figure 3 3 PLLC1 Configuration In DM355 Submit Documentation Feedback Detailed Device Description 75 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INST MENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 6 3 PLLC2 PLLC2 provides the DDR PHY clock and CLKOUTS Software controls PLLC2 operation through the PLLC2 registers The following list Table 3 11 and Figure 3 4 describe the customizations of PLLC2 in the DM355 Provides DDR PHY clock and CLKOUT3 Software configurable Accepts clock input or internal oscillator input Same input as PLLC1 PLL pre divider value is programmable PLL multiplier value is programmable PLL post divider value is fixed to 1 Only SYSCLK 1 is used SYSCLK1 divider value is fixed to 1 SYSCLKBP divider value is fixed to 8 SYSCLK1 is routed to the DDR PHY SYSCLKBP is routed to the output pin CLKOUT3 AUXCLK is not used Table 3 11 PLLC2 Output Clocks Output Clock Used by PLLDIV Divider Notes SYSCLK1 DDR PHY IW Fixed divider SYSCLKBP CLKOUT3 8 Fixed divider CLKIN OSCIN 76 Detailed Device Description PLLC2 Configuration in DM355 CLKMODE Pre DIV Post DIV programmable 1 PLLDI
95. DMA transfers Instruction and Data accesses are differentiated via accessing different memory map regions with the instruction region from 0x0000 through Ox7FFF and data from 0x10000 through 0x17FFF Placing the instruction region at Ox0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000 as required by the ARM architecture The internal 32 KB RAM is split into two physical banks of 16KB each which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks 3 2 5 Advanced High performance Bus AHB The ARM Subsystem uses the AHB port of the ARM926EJ S to connect the ARM to the configuration bus and the external memories Arbiters are employed to arbitrate access to the separate D AHB and I AHB by the configuration bus and the external memories bus 3 2 6 Embedded Trace Macrocell ETM and Embedded Trace Buffer ETB 3 3 3 3 1 62 To support real time trace the ARM926EU S processor provides an interface to enable connection of an Embedded Trace Macrocell ETM The ARM926ES J Subsystem in DM355 also includes the Embedded Trace Buffer ETB The ETM consists of two parts e Trace Port provides real time trace capability for the ARM9 e Triggering facilities provide trigger resources which include address and data comparators counter and sequencers The DM355 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer The
96. Delay time FSX low to CLKX low T 2 T 2 ns M55 ta ckxL DXxv Delay time CLKX low to DX valid 2 6 ns Disable time DX high impedance following last data bit from M56 tdis CKXH DXHZ CLKX high ee g 3 3 ns M57 taFxL pxv Delay time FSX low to DX valid C 1 C 10 ns 1 P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 2 T CLKX period 1 CLKGDV x P C CLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 x P when CLKGDV is even D CLKX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 x P when CLKGDV is even Use which ever value is greater 4 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output CLKXM FSXM 1 CLKRM FSRM 0 for master ASP 5 FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX CLKX f eA E a a a k M53 k lms4 M62 gt FSX y 4 M56 a le Mera le le M55 DX __ Bito _ Bit n 1 X n 2 X m X m X M584 4 Mes pp CR BE ECH Figure 5 45 ASP as SPI CLKSTP 11b CLKXP 1 Submit Documentation Feedback Peripheral Information and Electrical Specifications 143 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 d Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 SE 5 15 Timer The contains f
97. ET must be released only in order for boundary scan JTAG to read the variant field of IDCODE correctly Other boundary scan instructions work correctly independent of current state of RESET For maximum reliability includes an internal pulldown PD on the TRST pin to ensure that TRST will always be asserted upon power up and the device s internal emulation logic will always be properly initialized JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations Following the release of RESET the low to high transition of TRST must be seen to latch the state of EMU1 and EMUO The EMU 1 0 pins configure the device for either Boundary Scan mode or Emulation mode For more detailed information see the terminal functions section of this data sheet 1 IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture 148 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 18 1 JTAG Test Port Electrical Data Timing Table 5 48 Timing Requiremen
98. ETB has a 4KB buffer memory ETB enabled debug tools are required to read interpret the captured trace data Memory Mapping The ARM memory map is shown in Table 2 2 and Table 2 3 This section describes the memories and interfaces within the ARM s memory map ARM Internal Memories The ARM has access to the following ARM internal memories e 32KB ARM Internal RAM on TCM interface logically separated into two 16KB pages to allow simultaneous access on any given cycle if there are separate accesses for code I TCM bus and data D TCM to the different memory regions e 8KB ARM Internal ROM Detailed Device Description Submit Documentation Feedback R3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 3 2 External Memories The ARM has access to the following External memories DDR2 mDDR Synchronous DRAM Asynchronous EMIF OneNAND NAND Flash Flash card devices MMC SD xD SmartMedia 3 3 3 Peripherals The ARM has access to all of the peripherals on the device 3 4 ARM Interrupt Controller AINTC The DM355 ARM Interrupt Controller AINTC has the following features e Supports up to 64 interrupt channels 16 external channels e Interrupt mask for each channel e Each interrupt channel can be mapped to a Fast Interrupt Request FIQ or to an Interrupt Request IRQ type of interrupt e Hardware prioritization of simultaneous interru
99. F boot is selected CEO is used for AEMIF device OneNAND ROM Use AECFG 3 0 to configure AEMIF pins for NAND If MMC SD boot is selected MMC SDO is used AECFG 3 0 Selects AEMIF pin EM_A 11 8 1101 Selects the AEMIF pin configuration Refer configuration NAND to pin muxing information in Section 3 9 1 Note that AECFG 3 0 affects both AEMIF BTSEL 1 0 01 and NAND BTSEL 1 0 00 boot modes 80 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 11 2 PLL Configuration After POR warm reset and max reset the PLLs and clocks are set to their default configurations The PLLs are in bypass mode and disabled by default This means that the input reference clock at MXI1 typically 24 MHz drives the chip after reset For more information on device clocking see Section 3 5 and Section 3 6 The default state of the PLLs is reflected in the default state of the register bits in the PLLC registers Refer the the ARM Subsystem User s Guide for PLLC register descriptions 3 11 3 Power Domain and Module State Configuration Only a subset of modules are enabled after reset by default Table 3 16 shows which modules are enabled after reset Table 3 16 as shows that the following modules are enabled depending on the sampled state of the device configuration pins EDMA CC and TCO AE
100. FSR ASPO_CLKR ASPO_CLKX emoe f TCK RTCK SPI1_SDO SECH 10001 Vss ASP1_FSX ASP1_FSR ASPO_DR EM_CLK Je RESET CLKOUT1 Re G10005 ASP1_CLKS ASP1_CLKR ASP1_CLKX p Ven Moi cLKouT3 SPIO SCLK sp SCUk MmMcsDo_cmD mMcsD1_cLK Gogo GI0007 ASP1_DX ASP1_DR c Vss SPI0_SDO SECHS RE TE RE ea GIO004 G10006 CVpp B 10 1 12 13 14 15 16 17 18 19 Figure 2 4 Pin Map Quadrant D 12 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 4 Pin Functions TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 The pin functions tables Table 2 4 through Table 2 22 identify the external signal names the associated pin ball numbers along with the mechanical package designator the pin type whether the pin has any internal pullup or pulldown resistors and a functional pin description For more detailed information on device configuration peripheral selection multiplexed shared pins and debugging considerations see Section 3 For the list of all pin in chronological order see Section 2 5 2 4 1 Image Data Input Video Processing Front End The CCD Controller module in the Video Processing Front End has an external signal interface for image data input It supports YUV YC inputs as well as Bayer RGB and complementary input signals e image data input The definition of the CCD controller data input signals depend on the input mode selected e
101. Front End AFE raw 08 YCC 16 bit time multiplexed CINO PD between chroma CB CR 00 YCC 08 bit which allows for 2 simultaneous Glo094 J3 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper GEN channel Y CB CR 00 GIO GIO 094 Standard CCD Analog Front End AFE raw 09 YCC 16 bit time multiplexed CIN1 PD between chroma CB CR 01 YCC 08 bit which allows for 2 simultaneous GlO095 L3 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper PRIM channel Y CB CR 01 GIO GIO 095 Standard CCD Analog Front End AFE raw 10 YCC 16 bit time multiplexed CIN2 PD between chroma CB CR 02 YCC 08 bit which allows for 2 simultaneous GIO096 J5 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper DD VIN channel Y CB CR 02 GIO GIO 096 Standard CCD Analog Front End AFE raw 11 YCC 16 bit time multiplexed CIN3 PD between chroma CB CR 03 YCC 08 bit which allows for 2 simultaneous Gong J4 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper D channel Y CB CR 03 GIO GIO 097 on Standard CCD Analog Front End AFE raw 12 YCC 16 bit time multiplexed SPI2 SDI PD between chroma CB CR 04 YCC 08 bit which allows for 2 simultaneous L4 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper SPI2 SDE DDEWIN channel Y CB CR 04 SPI SPI2 Data In NAT GIO GIO 098 CINS Standard CCD A
102. GB YCbCr data output and timing signals and c the timing generator The video encoder for analog video supports the following features Master Clock Input 27 MHz x2 Upsampling Programmable Timing Generator SDTV Support Composite NTSC M PAL B D G H Non Interlace option CGMS WSS Line 21 Closed Caption Data Encoding Chroma Low Pass Filter 1 5MHz 3MHz Programmable SC H phase 10 bit Over Sampling D A Converter 27MHz Internal analog video buffer Optional 7 5 Pedestal 16 235 0 255 Input Amplitude Selectable Programmable Luma Delay Master Slave Operation Internal Color Bar Generation 75 The digital LCD controller supports the following features Programmable DCLK Programmable Timing Generator Various Output Format YCbCr 16bit YCbCr 8bit ITU R BT 656 Parallel RGB 16 bit 18 bit Serial 8 bit RGB Low Pass Filter for Digital RGB Output Master Slave Operation Submit Documentation Feedback Peripheral Information and Electrical Specifications 121 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 e Internal Color Bar Generation 100 75 e YUV RGB modes support HDTV output 720p 1080i with 74 25 MHz external clock input 5 9 2 3 VPBE Electrical Data Timing Table 5 21 Timing Requirements for VPBE CLK Inputs see Figure 5 27
103. GIO GIO 09 SPI1_SDO SPI1 Data out GIO008 Ges uel Von GIO GIO 008 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback Device Overview 31 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 2 17 SPI Terminal Functions continued TERMINAL NANE 0 TYPE OTHER DESCRIPTION Standard CCD Analog Front End AFE Not used e YCC 16 bit time multiplexed between chroma CB CR 07 CIN7 PD e YCC 8 bit which allows for two simultaneous decoder inputs it is GIO101 N3 VO Z VOD VIN time multiplexed between luma and chroma of the upper channel SP12_SCLK Y CB CR 07 SPI SPI2 clock GIO GIO 101 Standard CCD Analog Front End AFE Raw 13 e YCC 16 bit time multiplexed between chroma CB CR 05 CNS PD e YCC 8 bit which allows for two simultaneous decoder inputs it is GIO099 M3 VO Z VOD ViN time multiplexed between luma and chroma of the upper channel SPI2_SDENA 0 7 Y CB CR 07 SPI SPI2 chip select GIO GIO 099 Standard CCD
104. GIO060 EIS de Vos GIO GIO 060 EM AO P16 VO Z V Async EMIF Address Bus bit 07 GIO061 DO GIO GIO 061 Used by ROM Bootloader to provide progress status via LED EM A08 Async EMIF Address Bus bit 08 Glove T19 VO Z PU GIO GIO 062 AECFG 0 sets default for PinMux2 EM_A0_BA1 AEMIF AECFGIO Von Address Width OneNAND or NAND PinMux2 EM_A13_3 AEMIF Address 0 Width OneNAND or NAND 24 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 11 GPIO Terminal Functions continued TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO EM A09 Async EMIF Address Bus bit 09 Gl0063 P17 VOIZ PD GIO GIO 063 System AECFG 3 0 sampled at Power on Reset to set AEMIF AECFGI1 Von Configuration AECFG 2 1 sets default for PinMux2 EM_BAO AEMIF EM_BAO m Definition EM_BAO EM_A14 GIO 054 rsvd EM A10 Async EMIF Address Bus bit 10 Glo064 R18 VO Z PU GIO GIO 064 System AECFG 3 0 sampled at Power on Reset to set AEMIF AECFGI2 Von Configuration AECFG 2 1 sets default for PinMux2 EM_BAO AEMIF EM_BAO 2 Definition EM_BAO EM_A14 GIO 054 rsvd EM A11 Async EMIF Address Bus bit 11 GIO065 R16 VO Z PU GIO GIO 065 System AECFG 3 0 sampled at Power on Reset to set AEMIF AECFGI3 Von Configuration AECFG 3 sets default for PinMux2
105. GlO034 F19 VO Z Vpp NAND SM xD RE Read Enable output GIO GIO 034 EM WEI Async EMIF Write Enable GIE J15 VO Z Vpp NAND SM xD WE Write Enable output GIO GIO 035 EM CE1 Async EMIF Second Chip Select Can be programmed to be used for standard GIO036 G19 VO Z Von asynchronous memories example flash OneNand or NAND memory GIO GIO 036 Async EMIF Lowest numbered Chip Select Can be programmed to be used for EM_CE0 J16 VO Z V standard asynchronous memories example flash OneNand or NAND memory GI0037 DO Used for the default boot and ROM boot modes GIO GIO 037 EM_D0O0 Async EMIF Data Bus bit 00 GI0038 ne dE Vos GIO GIO 038 Submit Documentation Feedback Device Overview 23 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 2 11 GPIO Terminal Functions continued TERMINAL i om NANE NG TYPE OTHER 9 DESCRIPTION EM_D01 Async EMIF Data Bus bit 01 GIO039 g ue Vos GIO GIO 039 EM_D02 Async EMIF Data Bus bit 02 GIO040 Gier dee Vos GIO GIO 040 EM_D03 Async EMIF Data Bus bit 03 Gl0041 J18 die Voo GIO GIO 041 EM_D04 Async EMIF Data Bus bit 04 Gloo042 is vO Z Von GIO GIO 042 EM_D05 Async EMIF Data Bus bit 05 G10043 J19 O Vos GIO GIO 043 EM_D0O6 Async EMIF
106. Group Power PU Reset Description Mux Control ID 1 Supply PD State EM AO N17 VO AEMI Vpp out L Async EMIF Address Bus bit 01 F NAND SM xD ALE Address Latch Enable output EM_AOO M16 UO AEMI Vpp out L Async EMIF Address Bus bit 00 Note that PINMUX2 1 EM_AO GIO056 F the EM_A0O is always a 32 bit address _BA1 GIO GIO GIO 056 default set by AECFG 0 EM_BA1 P19 VO AEMI Vpp out H Async EMIF Bank Address 1 signal 16 bit PINMUX2 1 EM_AO GIO055 F address _BA1 GIO In 16 bit mode lowest address bit default set by AECFG 0 In 8 bit mode second lowest address bit GIO GIO 055 EM_BAO N19 VO AEMI Vpp out H Async EMIF Bank Address 0 signal 8 bit PINMUX2 3 2 EM_ GIO054 F address BAO EM_A14 GIO EMIF2 20 In 8 bit mode lowest address bit default set by AECFG 2 1 Or can be used as an extra Address line bit 14 when using 16 bit memories GIO GIO 054 EM_D15 M18 VO AEMI Vpp in Async EMIF Data Bus bit 15 PINMUX2 4 EM_D1 GIO053 F _ 8 GIO GIO GIO 053 default set by AECFG 3 EM_D14 M19 VO AEMI Vpp in Async EMIF Data Bus bit 14 PINMUX2 4 EM_D1 GIO052 F _ 8 GIO GIO GIO 052 default set by AECFG 3 EM_D13 M15 VO AEMI Vpp in Async EMIF Data Bus bit 13 PINMUX2 4 EM_D1 GIO051 F _ 8 GIO GIO GIO 051 default set by AECFG 3 EM_D12 L18 VO AEMI Vpp in Async EMIF Data Bus bit 12 PINMUX2 4 EM_D1 GIO050 F 5 8 GIO GIO GIO 050 default set by AECFG 3
107. H19 VO AEMI Vpp in Async EMIF Data Bus bit 02 PINMUX2 5 EM_D7 GIO040 F 0 GIO GIO GIO 040 EM_D01 J17 VO AEMI Vpp in Async EMIF Data Bus bit 01 PINMUX2 5 EM_D7 GIO039 F 0 GIO GIO GIO 039 EM_DO0O0 H18 VO AEMI Vpp in Async EMIF Data Bus bit 00 PINMUX2 5 EM_D7 GIO038 F 0 GIO GIO GIO 038 EM_CE0 J16 VO AEMI Vpp out H Async EMIF Lowest numbered Chip Select PINMUX2 6 EM_CE GIO037 F Can be programmed to be used for standard 0 GIO asynchronous memories example flash OneNand or NAND memory Used for the default boot and ROM boot modes GIO GIO 037 EM_CE1 G19 VO AEMI Vpp out H Async EMIF Second Chip Select Can be PINMUX2 7 EM_CE GIO036 F programmed to be used for standard 1 GIO asynchronous memories example flash OneNand or NAND memory GIO GIO 036 46 Device Overview Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State EM_WE J15 VO AEMI Vpp out H Async EMIF Write Enable PINMUX2 8 EM_W GIO035 Ei E OE GIO NAND SM xD WE Write Enable output GIO GIO 035 EM_OE F19 VO AEMI Vpp out H Async EMIF Output Enable PINMUX2 8 EM_W GlO034 Ei E OE GIO NAN
108. In 16 bit YCbCr mode the Cb and Cr signals are multiplexed on the CI signals and the order is configurable i e Cb first or Cr first e In 8 bit YCbCr mode the Y Cb and Cr signals are multiplexed and not only is the order selectable but also the half of the bus used Table 2 4 CCD Controller Signals for Each Input Mode PIN NAME CCD 16 BIT YCbCr 8 BIT YCbCr Cl7 Cb7 Cr7 Y7 Cb7 Cr7 CG Cb6 Cr6 Y6 Cb6 Cr6 eh CCD13 Cb5 Cr5 Y5 Cb5 Cr5 CH CCD12 Cb4 Cr4 Y4 Cb4 Cr4 Cl3 CCD11 Cb3 Cr3 Y3 Cb3 Cr3 cl2 CCD10 Cb2 Cr2 Y2 Cb2 Cr2 CH CCD9 Cb1 Cr1 Y1 Cb1 Cr1 Clo CCD8 Cb0 CrO Y0 Cb0 CrO YI7 CCD7 Y7 Y7 Cb7 Cr7 YI6 CCD6 Y6 Y6 Cb6 Cr6 YI5 CCD5 Y5 Y5 Cb5 Cr5 M I CCD4 Y4 Y4 Cb4 Cr4 ME CCD3 Y3 Y3 Cb3 Cr3 M I CCD2 Y2 Y2 Cb2 Cr2 Yi CcD1 Y1 Y1 Cb1 Cr1 YIO CCDO YO Y0 Cb0 CrO Submit Documentation Feedback Device Overview 13 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 5 CCD Controller Video Input Terminal Functions TERMINAL a 2 3 NAME NO TYPE OTHER DESCRIPTION Standard CCD Analog Front End AFE NOT USED CNS e YCC 16 bit Time multiplexed between chroma CB SR 07 GIO101 N3 VO Z PD e YCC 8 bit which allows for two simultaneous decoder inputs it is time SPI2_SCLK Vop vn multiplexed
109. KOUT2 Cycle time CLKOUT2 Laun 3 2 tw CLKOUT2H Pulse duration CLKOUT2 high 0 45P 0 55P ns 3 twotkouT2L Pulse duration CLKOUT2 low 0 45P 0 55P ns 4 tycLKout2 Transition time CLKOUT2 0 05P ns 5 tamxiH Delay time MXI1 CLKIN1 high to CLKOUT2 high 1 8 ns CLKOUT2H e owent Delay time MXI1 CLKIN1 low to CLKOUT2 low 1 8 ns CLKOUT2L 1 The reference points for the rise and fall transitions are measured at Vo MAX and VoyMIN 2 P 1 CLKOUT2 clock frequency in nanoseconds ns For example when CLKOUT2 frequency is 8 MHz use P 125 ns gt l gt LW ere l l r 2 i l l jh gt s i l l cLkouT2 INASI NIAN IAA AAN AAN l l lt gt 3 gt 4 Figure 5 10 CLKOUT2 Timing 102 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 9 Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 see Figure 5 11 DM355 NO PARAMETER UNIT MIN TYP MAX 1 teicLkouts Cycle time CLKOUT3 temx 1 8 2 twcLKouTsH Pulse duration CLKOUTS high 0 45P 0 55P ns 3 twCLKOUTSL Pulse duration CLKOUT3 low 0 45P 0 55P ns 4 tycLKouT3 Transition time CLKOUT3 0 05P ns 5 tamxi2H Delay time CLKIN MXI high to CLKOUT3 high 1 8 ns CLKOUT3H e owes Delay time
110. L 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 16 Reserved 17 ASP AlwaysOn ON SyncRst 18 12C AlwaysOn ON SyncRst 19 UARTO AlwaysOn ON BTSEL 1 0 00 Enable NAND BTSEL 1 0 01 Enable OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 20 UART1 AlwaysOn ON SyncRst 21 UART2 AlwaysOn ON SyncRst 22 SPIO AlwaysOn ON SyncRst 23 PWMO AlwaysOn ON SyncRst 24 PWM1 AlwaysOn ON SyncRst 25 PWM2 AlwaysOn ON SyncRst 26 GPIO AlwaysOn ON SyncRst 27 TIMERO AlwaysOn ON BTSEL 1 0 00 Enable NAND BTSEL 1 0 01 Enable OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 28 TIMER1 AlwaysOn ON SyncRst 29 TIMER2 AlwaysOn ON Enable 30 System Module AlwaysOn ON Enable 82 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 16 Module Configuration continued Default States 31 ARM AlwaysOn ON Enable 32 BUS AlwaysOn ON Enable 33 BUS AlwaysOn ON Enable 34 BUS AlwaysOn ON Enable 35 BUS AlwaysOn ON Enable 36 BUS AlwaysOn ON Enable 37 BUS AlwaysOn ON Enable 38 BUS AlwaysOn ON Enable 39 Reserved Reserved Reserved Reserved 40 VPSS DAC Always On ON SyncRst
111. M modules support the following features e 32 bit period counter e 32 bit first phase duration counter e 8 bit repeat count for one shot operation One shot operation will produce N 1 periods of the waveform where N is the repeat counter value e Configurable to operate in either one shot or continuous mode e Buffered period and first phase duration registers e One shot operation triggerable by hardware events with programmable edge transitions low to high or high to low e One shot operation triggerable by the CCD VSYNC output of the video processing subsystem VPSS which allows any of the PWM instantiations to be used as a CCD timer This allows the DM355 module to support the functions provided by the DM320 CCD timer feature generating strobe and shutter signals e One shot operation generates N 1 periods of waveform N being the repeat count register value e Configurable PWM output pin inactive state e Interrupt and EDMA synchronization events 5 16 1 PWMO0 1 2 3 Electrical Timing Data Table 5 46 Switching Characteristics Over Recommended Operating Conditions for PWM0 1 2 3 Outputs see Figure 5 47 and Figure 5 48 DM355 NO PARAMETER UNIT MIN MAX 1 tw PWMh Pulse duration PWMx high P ns 2 tw PWML Pulse duration PWMx low P ns 3 pw Transition time PWMx 05P ns 4 td CCDC PWMV Delay time CCDC VD trigger event to PWMx valid 10 ns 1 P MXI1 CLKIN cycle time in ns For example whe
112. MHz The following figure provides a legend for reading the complete device name for any TMS320DM355 DMSoC platform member TMX 320 DM355 ZCE 216 pela SPEED GRADE TMX Experimental device ifi i 216 MHz TMS Qualified device 570 MHz DEVICE FAMILY PACKAGE TYPE 4 320 TMS320 DSP family ZCE 337 pin plastic BGA with Pb free soldered balls DEVICE DM355 SILICON REVISION Blank Initial Silicon1 1 A BGA Ball Grid Array B For actual device part numbers P Ns and ordering information contact your nearest TI Sales Representative Figure 2 5 Device Nomenclature 2 6 3 Device Documentation 2 6 3 1 Related Documentation From Texas Instruments The following documents describe the TMS320DM355 Digital Media System on Chip DMSoC Copies of these documents are available on the internet at www ti com Contact your TI representative for Extranet 56 access SPRS463 SPRZ264 SPRUFB3 SPRUED1 SPRUED2 SPRUED3 TMS320DM355 Digital Media System on Chip DMSoC Data Manual This document describes the overall TMS320DM355 system including device architecture and features memory map pin descriptions timing characteristics and requirements device mechanicals etc TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functional specifications for the TMS320DM355 DMSoC TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM Subsystem in the TMS320DM
113. MIF MMC SDO UARTO and Time For example UARTO is enabled after reset when the device configuration pins BTSEL 1 0 11 Enable UART select UART boot mode For more information on module configuration refer to the ARM Subsystem User s Guide Submit Documentation Feedback Detailed Device Description 81 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 16 Module Configuration Default States Module Module Name Power Domain Power Domain State Module State Number 0 VPSS Master AlwaysOn ON SyncRst 1 VPSS Slave AlwaysOn ON SyncRst 2 EDMA CC AlwaysOn ON BTSEL 1 0 00 Enable NAND BTSEL 1 0 01 Enable OneNAND 3 EDMA TCO AlwaysOn ON BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 4 EDMA TC1 AlwaysOn ON SyncRst 5 Timer3 AlwaysOn ON SyncRst 6 SPI1 AlwaysOn ON SyncRst 7 MMC SD1 AlwaysOn ON SyncRst 8 ASP1 AlwaysOn ON SyncRst 9 USB AlwaysOn ON SyncRst 10 PWM3 AlwaysOn ON SyncRst 11 SPI2 AlwaysOn ON SyncRst 12 RTO AlwaysOn ON SyncRst 13 DDR EMIF AlwaysOn ON SyncRst 14 AEMIF AlwaysOn ON BTSEL 1 0 00 Enable NAND BTSEL 1 0 Enable OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 15 MMC SDO AlwaysOn ON BTSEL 1 0 00 Enable NAND BTSEL 1 0 Enable OneNAND BTSE
114. NTS Digital Media System on Chip DMSoC S SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 9 1 3 Hardware 3A H3A The H3A module is designed to support the control loops for Auto Focus Auto White Balance and Auto Exposure by collecting metrics about the imaging video data The metrics are to adjust the various parameters for processing the imaging video data There are 2 main blocks in the H3A module e Auto Focus AF engine e Auto Exposure AE Auto White Balance AWB engine The AF engine extracts and filters the red green and blue data from the input image video data and provides either the accumulation or peaks of the data in a specified region The specified region is a two dimensional block of data and is referred to as a paxel for the case of AF The AE AWB Engine accumulates the values and checks for saturated values in a sub sampling of the video data In the case of the AE AWB the two dimensional block of data is referred to as a window Thus other than referring them by different names a paxel and a window are essentially the same thing However the number dimensions and starting position of the AF paxels and the AE AWB windows are separately programmable The following features are supported by the AF engine e Support for input from DDR2 mDDR SDRAM in addition to the CCDC port e Support for a Peak Mode in a Paxel a Paxel is defined as a two dimensional block of pixels e Accumulate the maximum Focus Value o
115. O Gate UNIT MIN MAX 1 to TIN Cycle time TIM_IN 4P ns 2 wW TINPH Pulse duration TIM_IN high 0 45C 0 55C ns 3 twTINPL Pulse duration TIM_IN low 0 45C 0 55C ns 4 tytiny Transition time TIM_IN 0 05C ns 1 GPIO000 GPIO001 GPIO002 and GPIO003 can be used as external clock inputs for Timer 3 See the TMS320DM355 DMSoC 64 bit Timer User s Guide for more information SPRUEES 2 P MXI1 CLKIN cycle time in ns For example when MXI1 CLKIN frequency is 24 MHz use P 41 6 ns 3 C TIM_IN cycle time in ns For example when TIM_IN frequency is 24 MHz use C 41 6 ns k 1 f k 2 gt a S Der eme EE mmm E Figure 5 46 Timer Input Timing 144 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 16 Pulse Width Modulator PWM The DM355 contains 4 separate Pulse Width Modulator PWM modules The pulse width modulator PWM feature is very common in embedded systems It provides a way to generate a pulse periodic waveform for motor control or can act as a digital to analog converter with some external components This PWM peripheral is basically a timer with a period counter and a first phase duration comparator where bit width of the period and first phase duration are both programmable The Pulse Width Modulator PW
116. O102 GIO DI GIO GIO 102 50 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID UI Supply PD State SPIO_SDO B11 VO SPIO Vop in SPIO Data Out ASP1_DX C18 VO ASP5 Von in ASP1 Transmit Data 121 ASP1_CLKX D19 VO ASP5 Vpp in ASP1 Transmit Clock 121 ASP1_FSX E16 VO ASP5 Von in ASP1 Transmit Frame Sync 121 ASP1_DR C19 VO ASP5 Vpp in ASP1 Receive Data 121 ASP1_CLKR D18 VO ASP5 Vpp in ASP1 Receive Clock 121 ASP1_FSR E17 VO ASP5 Von in ASP1 Receive Frame Synch 121 ASP1_CLKS D17 ASP5 Von in ASP1 Master Clock 121 RESET D11 Vpp PU in Global Chip Reset active low MXI1 A9 Clocks Vpp in Crystal input for system oscillator 24 MHz MXO1 B9 O Clocks Vop out Output for system oscillator 24 MHz MXI2 R1 Clocks Vpp in Crystal input for video oscillator 27 MHz This crystal is not required VoD MXO2 Ti O Clocks Vop out Output for video oscillator 27 MHz This crystal is not required Von TCK E10 EMUL Vpp PU in JTAG test clock input ATIO N TDI D9 EMUL Vpp PU in JTAG test data input ATIO N TDO E9 O EMUL Vop out L JTAG test data output ATIO
117. PBE VPSS and peripherals PLL2 generates the clock required by the DDR PHY A block diagram of DM355 s clocking architecture is shown in Figure 5 1 The PLLs are described further in Section 3 6 Submit Documentation Feedback Detailed Device Description 65 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 SYSCLKBP CLKOUT2 BPDIV 3 Reference clock MXI MXO AUXCLK 1 24 MHz or 36 Mhz AUXCLK UARTO 1 SYSCLK1 PLLDIV1 2 ARM subsystem MPEG JPEG Coprocessor 12C PWMs x4 Timers x4 RTO 3 CLKOUT1 Reference lock SYSCLK2 S PLLDIV2 4 USB Phy ea zor SYSCLK3 36 MHz PLLDIV3 n PLLDIV4 4 or 2 SYSCLK4 EMIF NAND PLL controller 1 MMC SD x2 VPFE PCLK e vere SPI x3 T vw VPBE ASP x2 EXTCLK e GPIO ARM INTC UART2 EDMA SYSCLK1 PLLDIV1 1 DDR PHY ei gt O Bus logic SYSCLKBP Sys logic BPDIV 8 PLL controller 2 CLKOUT3 PSC IcePick Sequencer Figure 3 2 Device Clocking Block Diagram 66 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 5 2 Supported Clocking Configurations for DM355 216
118. PIO1 GPIO TINT4 Timer 2 TINT12 SYS ARM_INTMUX 14 UARTINT2 or UART2 or 46 GPIO2 GPIO TINT5 Timer 2 TINT34 15 TINT6 Timer 3 TINT12 47 GPIO3 GPIO 16 CCINTO EDMA CC Region 0 48 GPIO4 GPIO 17 SPINT1 0 or SPI1 or 49 GPIO5 GPIO CCERRINT EDMA CC Error 18 SPINT1 1 or SPI1 or 50 GPIO6 GPIO TCERRINTO EDMA TCO Error 19 SPINT2 0 or SPI2 or 51 GPIO7 GPIO TCERRINT1 EDMA TC1 Error 20 PSCINT PSC ALLINT 52 GPIO8 GPIO 21 SPINT2 1 SPI2 53 GPIO9 GPIO 22 TINT7 Timer3 TINT34 54 GPIOBNKO GPIO 23 SDIOINTO MMC SDO 55 GPIOBNK1 GPIO 24 MBXINTO or ASPO or 56 GPIOBNK2 GPIO MBXINT1 ASP1 25 MBRINTO or ASPO or 57 GPIOBNK3 GPIO MBRINT1 ASP1 26 MMCINTO MMC SDO 58 GPIOBNK4 GPIO 27 MMCINT1 MMC SC1 59 GPIOBNK5 GPIO 28 PWMINT3 PWM3 60 GPIOBNK6 GPIO 29 DDRINT DDR EMIF 61 COMMTX ARMSS 30 AEMIFINT Async EMIF 62 COMMRX ARMSS 31 SDIOINT1 SDIO1 63 EMUINT E2ICE 64 Detailed Device Description Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 5 Device Clocking 3 5 1 Overview The DM355 requires one primary reference clock The reference clock frequency may be generated either by crystal input or by external oscillator The reference clock is the clock at the pins named MXI1 MXOI The reference clock drives two separate PLL controllers PLLC1 and PLLC2 PLLC1 generates the clocks required by the ARM MPEG and JPEG co processor V
119. PRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 e Embedded Trace Module and Embedded Trace Buffer ETM ETB For more complete details on the ARMQ refer to the ARM926EU S Technical Reference Manual available at http www arm com CP15 The ARM926EU S system control coprocessor CP15 is used to configure and control instruction and data caches Tightly Coupled Memories TCMs Memory Management Unit MMU and other ARM subsystem functions The CP15 registers are programmed using the MRC and MCR ARM instructions when the ARM in a privileged mode such as supervisor or system mode 3 2 2 MMU The ARM926EJ S MMU provides virtual memory features required by operating systems such as Linux WindowCE ultron ThreadX etc A single set of two level page tables stored in main memory is used to control the address translation permission checks and memory region attributes for both data and instruction accesses The MMU uses a single unified Translation Lookaside Buffer TLB to cache the information held in the page tables The MMU features are e Standard ARM architecture v4 and v5 MMU mapping sizes domains and access protection scheme e Mapping sizes are 1MB sections 64KB large pages 4KB small pages 1KB tiny pages e Access permissions for large pages and small pages can be specified separately for each quarter of the page subpage permissions e Hardware page table walks e Invalidate entire TLB using CP15 register
120. R TMS320DM35x USB Board Design and Layout Guidelines Application Note This provides board design recommendations and guidelines for high speed USB Device Overview Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 Detailed Device Description This section provides a detailed overview of the DM355 device 3 1 ARM Subsystem Overview The ARM Subsystem contains components required to provide the ARM926EUJ S ARM master control of the overall DM355 system including the components of the ARM Subsystem the peripherals and the external memories The ARM is responsible for handling system functions such as system level initialization configuration user interface user command execution connectivity functions interface and control of the subsystem etc The ARM is master and performs these functions because it has a large program memory space and fast context switching capability and is thus suitable for complex multi tasking and general purpose control tasks 3 1 1 Components of the ARM Subsystem The ARM Subsystem in DM355 consists of the following components e ARM926EJ S RISC processor including coprocessor 15 CP15 MMU 16KB Instruction cache 8KB Data cache Write Buffer Java accelerator e ARM Internal Memories 32KB Internal RAM 82 bit wide access 8KB Internal ROM ARM boot
121. RM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF 4M ae ee Reconved 0x0200 0000 Ox09FF FFFF 128M ASYNC EMIF Data ASYNC EMIF Data 0x0A00 0000 0x11EF FFFF 127M 16K 0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved 0x11F2 0000 0x1 FFF FFFF 141M 64K 0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control Regs Regs 0x2000 8000 0x41 FF FFFF 544M 32K Reserved 0x4200 0000 Ox49FF FFFF 128M Reserved AEMIF shadow 0x4A00 0000 Ox7FFF FFFF 864M Reserved 0x8000 0000 Ox8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF 0x9000 0000 OxFFFF FFFF 1792M Reserved Reserved Reserved Reserved Table 2 3 DM355 ARM Configuration Bus Access to Peripherals Address Accessibility Region Start End Size ARM EDMA EDMA CC 0x01C0 0000 0x01C0 FFFF 64K V V EDMA TCO 0x01C1 0000 0x01C1 03FF 1K V V EDMA TC1 0x01C1 0400 0x01C1 07FF 1K V V Reserved 0x01C1 8800 0x01C1 9FFF 6K V V Reserved 0x01C1 A000 0x01C1 FFFF 24K V V UARTO 0x01C2 0000 0x01C2 03FF 1K V V Submit Documentation Feedback Device Overview PRODUCT PREVIEW MalAddd LONAOYd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com Table 2 3 DM355 ARM Configuration Bus Access to Peripherals continued
122. Reference HY Connect directly to ground and to USB_R1 via 10K Q 1 resistor placed as close to the device as possible VDDA33 USB J8 PWR USBP Von Analog 3 3 V power USB PHY Transceiver 7 HY Vss_usB B7 GND USBP Von Analog 3 3 V ground for USB PHY HY Transceiver VDDA33 USB PLL B6 PWR USBP Von Common mode 3 3 V power for USB PHY ane HY PLL Vss_usB D6 GND USBP Von Common mode 3 3 V ground for USB PHY HY PLL VDDA13 USB H7 PWR USBP Von Analog 1 3 V power for USB PHY S HY Vss_usB E6 GND USBP Von Analog 1 3 V ground for USB PHY HY Vppp13 USB C6 PWR USBP Vpp Digital 1 3V power for USB PHY p HY MMCSDO_CLK A15 VO MMC Vpp out L MMCSDO Clock PINMUX4 2 MMCS SDO DO_MS MMCSDO_CMD C14 VO MMC Vpp in MMCSDO Command PINMUX4 2 MMCS SDO DO_MS MMCSDO_DAT A14 VO MMC Vpp in MMCSDO DATA3 PINMUX4 2 MMCS A3 SDO DO_MS MMCSDO_DAT B13 VO MMC Vpp in MMCSDO DATA2 PINMUX4 2 MMCS A2 SDO DO MS MMCSDO_DAT D14 VO MMC Vpp in MMCSD0O DATA1 PINMUX4 2 MMCS Al SDO DO MS MMCSDO_DAT B14 VO MMC Vpp in MMCSDO DATAO PINMUX4 2 MMCS AO SDO DO MS UARTO_RXD U18 UART Vpp in UARTO Receive Data 0 Used for UART boot mode UARTO_TXD T18 O UART Vpp out H UARTO Transmit Data 0 Used for UART boot mode SPIO_SDENA O B12 VO SPIO Vpp in SPIO Enable Chip Select 0 PINMUX4 0 SPIO_S GlO103 GIO DENA GIO GIO 103 SPIO_SCLK C12 VO SPIO Vpp in SPIO Clock SPIO_SDI A12 VO SPIO Vpp in SPIO Data In PINMUX4 1 SPIO_S GI
123. SED SEPTEMBER 2007 5 5 Oscillators and Clocks 5 5 1 has two oscillator input output pairs MXI1 MXO1 and MXI2 MXO2 usable with external crystals or ceramic resonators to provide clock inputs The optimal frequencies for the crystals are 24 MHz MXI1 MXO1 and 27 MHz MXI2 MXO2 Optionally the oscillator inputs are configurable for use with external clock oscillators If external clock oscillators are used to minimize the clock jitter a single clean power supply should power both the and the external oscillator circuit and the minimum CLKIN rise and fall times must be observed The electrical requirements and characteristics are described in this section The timing parameters for CLKOUT 3 1 are also described in this section The has three output clock pins CLKOUT 3 1 See Section 3 5 and Section 3 6 for more information on CLKOUT 3 1 MXI1 24 MHz Oscillator The MXI1 typically 24 MHz can also be 36 MHz oscillator provides the primary reference clock for the device The on chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins along with two load capacitors as shown in Figure 5 5 The external crystal load capacitors must be connected only to the oscillator ground pin Vss mx1 Do not connect to board ground Vss Also the PLL power pin ops su Should be connected to the power supply through a ferrite bead L1 in the example circuit shown in Figure 5 5 MXI1 CLKIN MXO1 Vas Mai VpDA_PLL1 V
124. Standard CCD Analog Front End AFE SPI2_SDENA 0 GIO raw 13 SPI2 YCC 16 bit time multiplexed between chroma CB CR 05 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 05 SPI SPI2 Chip Select GIO GIO 99 PINMUXO 5 4 CIN_ 5 CIN4 GIO098 L4 VO CCDC VDD VIN PD in Standard CCD Analog Front End AFE SPI2_SDI GIO raw 1 2 SPI2_SDENA 1 SPI2 SPI2 YCC 16 bit time multiplexed between chroma CB CR 04 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 04 SPI SPI2 Data In GIO GIO 098 PINMUXO 7 6 CIN_ 4 Input O Output Z High impedance S Supply voltage GND Ground A Analog signal Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used annann BRON Serer aH To reduce EMI and reflections depending on the trace length approximately 22 Q to 50 Q damping resistors are recommend on the following outputs placed near the DM355 YOUT 0 7 COUT 0 7 HSYNC VSYNC LCD_OE FIELD EXTCLK VCLK The trace lengths should be minimized 36 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti
125. Sync PINMUX1 16 HVSY GIO073 GIO 7 NC GIO GIO 073 4 VSYNC G5 VO NENG Vpp vout PD in Video Encoder Vertical Sync PINMUX1 16 HVSY GlO072 GIO NC GIO GIO 072 LCD_OE H5 UO VENC Vpp vout in Video Encoder LCD Output Enable or PINMUX1 17 DLCD GIO071 GIO BRIGHT signal GIO GIO 071 40 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State FIELD GIO070 H4 VO VENC Vpp vout in Video Encoder Field identifier for interlaced PINMUX1 19 18 Fl R2 PWM3C GIO display formats ELD VENC PWM3 GIO GIO 070 Digital Video Out R2 PWM3C EXTCLK G3 UO VENC Vpp vout PD in Video Encoder External clock input used if PINMUX1 21 20 EX GIO069 B2 GIO clock rates gt 27 MHz are needed e g 74 25 TCLK PWM3D VENC MHz for HDTV digital output PWM3 GIO GIO 069 Digital Video Out B2 Pwm3D 4 VCLK GIO068 H3 VO NENG Vpp vout out L Video Encoder Video Output Clock PINMUX1 22 VCLK GIO 7 GIO GIO 068 VREF J7 A I O Video Video DAC Reference voltage output DAC 0 45V 0 1uF to GND IOUT E1 AI O Video Video DAC Pre vi
126. TAG Output Timing 150 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS463 device specific data sheet to make it an SPRS463A revision Scope Updated DM355 Pin Descriptions table etc ADDS CHANGES DELETES Section 1 1 Features e Video Processing Subsystem feature 14 Bit Parallel AFE Analog Front End Interface Changed speed from 75 MHz to 67 5 MHz Table 2 1 Characteristics of the Processor e Corrected the Product Status Updated Table 2 3 DM355 ARM Configuration Bus Access to Peripherals Updated Figure 2 1 Pin Map Quadrant A Updated Figure 2 2 Pin Map Quadrant B Updated Figure 2 3 Pin Map Quadrant C Updated Figure 2 4 Pin Map Quadrant D Table 2 7 Digital Video Terminal Functions e Changed Terminal No of YOUT7 R7 from C2 to C3 Table 2 9 Asynchronous EMIF NAND OneNAND Terminal Functions e Changed Terminal No of EM_BA0 GIO054 EM_A14 from T19 to N19 e H16 Changed Terminal Name from EM_AVD GIO032 to EM_ADV GIO032 Table 2 10 DDR Terminal Functions e R11 Changed Terminal Name from DDR_VSSDLL to Vssa pit e R10 Changed Terminal Name from DDR_VDDDLL to Vppa33_ppRDLL Updated Table 2 11 GPIO Terminal Functions Section 2
127. TEMBER 2007 REVISED SEPTEMBER 2007 2 4 7 Universal Serial Bus USB Interface The Universal Serial Bus USB interface supports the USB2 0 High Speed protocol and includes dual role Host Slave support However no charge pump is included Table 2 13 USB Terminal Functions TERMINAL TYPE OTHER DESCRIPTION NAME NO USB D differential signal pair USB DP A7 AVO Z Vopas3 Uep When USB is not used this signal should be connected to Vos uss USB D differential signal pair USB_DM A6 AVO Z Vopass_UsB When USB is not used this signal should be connected to Vss_usB USB reference current output Connect to VSS_USB_REF via 10K ohm 1 resistor placed as close to the USB R1 Gi A VO Z device as possible When USB is not used this signal should be connected to Vss usp USB operating mode identification pin For Device mode operation only pull up this pin to VDD with a 1 5K ohm resistor For Host mode operation only pull down this pin to ground VSS with a 1 5K USB ID D5 A VO Z Vppa33_USB ohm resistor If using an OTG or mini USB connector this pin will be set properly via the cable connector configuration When USB is not used this signal should be connected to Vss usp For host or device mode operation tie the VBUS USB power signal to the USB connector USB_VBUS E5 A VO Z Vop When used in OTG mode operation tie VBUS to the external charge pump and to the VBUS signal
128. The following are the primary features that are supported by the OSD 120 Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously VIDWINO VIDWIN1 and OSDWINO OSDWIN1 Video windows supports YCbCr data in 422 format from external memory with the ability to interchange the order of the CbCr component in the 32 bit word OSD bitmap windows support 1 2 4 8 bit width index data of color palette In addition one OSD bitmap window at a time can be configured to one of the following YUV422 same as video data RGB format data in 16 bit mode R 5bit G 6bit B 5bit 24 bit mode each R G B 8bit with pixel level blending with video windows Programmable color palette with the ability to select between a RAM ROM table with support for 256 colors Support for 2 ROM tables one of which can be selected at a given time Separate enable disable control for each window Programmable width height and base starting coordinates for each window External memory address and offset registers for each window Support for x2 and x4 zoom in both the horizontal and vertical direction Pixel level blending transparency blinking attributes can be defined for OSDWINO when OSDWIN1 is configured as an attribute window for OSDWINO Support for blinking intervals to the attribute window Ability to select either field frame mode for the windows interlaced progressive An eight step blending process between the b
129. Thermal Resistance Characteristics PBGA Package ZCE NO uC W AIR FLOW m s 1 ROJc Junction to case TBD TBD 2 De Junction to board TBD TBD 3 ROJA Junction to free air TBD TBD 4 Psigt Junction to package top TBD TBD 5 Psijg Junction to board TBD TBD 1 m s meters per second 7 1 1 Packaging Information The following packaging information and reflect the most current data available for the designated device This data is subject to change without notice and without revision of this document Note that micro vias are not required for this package Submit Documentation Feedback Mechanical Data 153 PRODUCT PREVIEW MECHANICAL DATA ZCE S PBGA N337 PLASTIC BALL GRID ARRAY PACKAGE A1 Corner F OQQ0000 O O0O 00 OO OOO DOOOOOOOO0O 9111 13 15 17 19 10 12 14 16 18 Bottom View 1 30 MAX 084 ae cating Plone D KEE AQ 0 08 C 0 33 0 46 0 15 MIC AIB 0 23 0 36 0 05 D 4208769 B 08 07 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C This is a lead free solder ball design d TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its produ
130. Timer 3 GIO002 F15 VO Z Vop GIO GIO 002 Can be used as external clock input for Timer 3 GIO003 G15 VO Z Vop GIO GIO 003 Can be used as external clock input for Timer 3 GIO004 B17 V O Z Von GIO GIO 004 GIO005 D15 1 O Z Von GIO GIO 005 GIO006 B18 1 O Z Von GIO GIO 006 GIO007 GIO GIO 007 o oe date Von SPIO Chip Select 1 1 a E12 VO Z Vbo SPI1 Data Out Glo008 GIO GIO 008 SPI1_SDI GIO009 A SPI1_SDE A13 VO Z Vpp SPI1 Data In OR SPI1 Chip Select 1 GIO GIO 009 NA 1 Se SPI1 Clock GIO K C13 V O Z Von GIO 010 GIO010 SPI1_SDE F T SPI1 Chip Select 0 NAIO E13 VO Z Von f GIO011 GIO GIO 011 E R17 VOlz Voo UART1 Transmit Data Gioo12 GIO GIO 012 cee ee ae Voo UART1 Receive Data Gl0013 GIO GIO 013 I2C_SCL 12C Serial Clock GIO GIO014 oe va Vos GIO 014 I2C_SDA 12C Serial Data GIO015 Rs UNE Von GIO GIO 015 CLKOUT3 CLKOUT Output Clock 3 aooe Pi ue Vos GIO GIO 016 CLKOUT2 CLKOUT Output Clock 2 GIO017 Al date Von GIO GIO 017 CLKOUT1 CLKOUT Output Clock 1 GlO018 ule VOZ Vos GIO GIO 018 MMCSD1 _DATAO MMCSD1 DATAO GIO019 A18 V O Z Von GIO GIO 019 UART2_T UART2 Transmit Data XD 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ re
131. V CLKH falling Ge LDI in put Se output Clock Polarity 1 5P 3 ns E Jett ed SPI_DI input valid after SPI_CLK output rising Clock Polarity 0 5P 43 hs 16 et SE SPI_DI input valid after SPI_CLK output falling Clock Polarity 1 5P 3 e Table 5 32 Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode Clock Phase 1 see Figure 5 38 DM355 NO PARAMETER UNIT MIN MAX Delay time SPI_CLK output falling edge to GP DO aa 17 tacLKL Dov output transition Clock Polarity 0 4 5 ns Delay time SPI_CLK output rising edge to SPI_DO ree 18 tacLKH Dov output transition Clock Polarity 1 4 5 ns Delay time SPI_EN 1 0 output falling edge to first SPI_CLK output rising or fallin 2P 5C i9 ege g tt Ge EN 1 0 output falling edg CLK output rising g RoG Du hs 20 tacLkuH DoHz Delay time SPI_CLK output falling or rising edge to GP DO output high impedance p 3 me 1 The delay time can be adjusted using the SPI module register C2TDELAY See the TMS320DM355 DMSoC Serial Peripheral Interface SPI User s Guide SPRUED4 2 The delay time can be adjusted using the SPI module register T2CDELAY See the TMS320DM355 DMSoC Serial Peripheral Interface SPI User s Guide SPRUED4 SPI_EN MV d SPLCLK d d d Clock Polarity 0 k 19 gt SPI_CLK Clock Polarity 1 13 i 14 JN GE lt RE
132. V1 1 PLLM programmable BPDIV 8 SYSCLK1 DDR PHY SYSCLKBP CLKOUT3 Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 7 Power and Sleep Controller PSC In the DM355 system the Power and Sleep Controller PSC is responsible for managing transitions of system power on off clock on off and reset A block diagram of the PSC is shown in Figure 3 5 Many of the operations of the PSC are transparent to software such as power on reset operations However the PSC provides you with an interface to control several important clock and reset operations The PSC includes the following features e Manages chip power on off clock on off and resets e Provides a software interface to Control module clock ON OFF Control module resets e Supports IcePick emulation features power clock and reset For more information on the PSC see the ARM Subsystem User s Guide DMSoC ARM arm_clock arm_mreset arm_power Emulation RESETN module clock MODx module_mreset VDD module_power domain Figure 3 5 DM355 Power and Sleep Controller PSC 3 8 System Control Module The DM355 s system control module is a system level module containing status and top level control logic required by the device The system control module consists of a miscellaneo
133. X UNIT 4 tw URXDB Pulse duration receive data bit RXDn o 99U 1 05U ns 5 wW URXSB Pulse duration receive start bit 0 990 1 05U ns 1 U UART baud time 1 programmed baud rate Table 5 27 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit see Figure 5 35 DM355 NO PARAMETER UNIT MIN MAX UARTO 1 Maximum programmable baud rate 1 5 1 f baud MHz UART2 Maximum programmable baud rate 5 2 tw UTXDB Pulse duration transmit data bit TXDn U 20 U 2 ns 3 tw UTXsB Pulse duration transmit start bit U 2 U 2 ns 1 U UART baud time 1 programmed baud rate Submit Documentation Feedback Peripheral Information and Electrical Specifications 129 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 VE lt gt 2 Start UART_TXDn Bit Data Bits BE on 4 Start UART_RXDn Bit Data Bits Figure 5 35 UART Transmit Receive Timing 130 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 12 Serial Port Interface SPI The contains 3 separate SPI modules These modules provide a programmable length shift register which
134. a System on Chip DMSoC TMS320DM35x DMSoC DDR2 Mobile DDR DDR2 mDDR Memory Controller Reference Guide This document describes the DDR2 mobile DDR memory controller in the TMS320DM35x Digital Media System on Chip DMSoC The DDR2 mDDR memory controller is used to interface with JESD79D 2A standard compliant DDR2 SDRAM and mobile DDR devices TMS320DM35x DMSoC Video Processing Front End VPFE Users Guide This document describes the Video Processing Front End VPFE in the TMS320DM35x Digital Media System on Chip DMSoC TMS320DM35x DMSoC Video Processing Back End VPBE Users Guide This document describes the Video Processing Back End VPBE in the TMS320DM35x Digital Media System on Chip DMSoC TMS320DM35x DMSoC Real Time Out RTO Controller Reference Guide This document describes the Real Time Out RTO controller in the TMS320DM35x Digital Media System on Chip DMSoC TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM355 Digital Media System on Chip DMSoC The following documents describe TMS320DM35x Digital Media System on Chip DMSoC that are not available by literature number Copies of these documents are available by title only on the internet at www ti com Contact your TI representative for Extranet access TMS320DM35x DDR2 mDDR Board Design Application Note This provides board design recommendations and guidelines for DDR2 and mobile DD
135. a PINMUX3 22 GIO1 Gloo12 1 2 GIO GIO GIO 012 SPI1_SDENA 0 E13 VO SPH Vpp in SPI1 Chip Select 0 PINMUX3 23 GIO1 GIO011 GIO 1 GIO GIO 011 48 Device Overview Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State SPI1_SCLK C13 VO SPI1 Vpp in SPI1 Clock PINMUX3 24 GIO1 GIO010 GIO 0 GIO GIO 010 SPI1_SDI A13 VO SPI1 Vpp in SPI1 Data In OR SPI1 Chip Select 1 PINMUX3 26 25 GI GIO009 GIO o9 SPI1_SDENA 1 SPI1 GIO GIO 009 SPI1_SDO E12 VO SPI1 Vpp in SPI1 Data Out PINMUX3 27 GIO8 GIO008 GIO GIO GIO 008 GIO007 C17 VO GIO Vor in GIO GIO 007 PINMUX3 28 GIO7 SPIO_SDENA 1 debou nce SPIO SPIO Chip Select 1 GIO006 B18 VO GIO Von in GIO GIO 006 debou nce GIO005 D15 VO GIO Von in GIO GIO 005 debou nce GIO004 B17 VO GIO Von in GIO GIO 004 debou nce GIO003 G15 VO GIO Von in GIO GIO 003 debou nce GIO002 F15 O GIO Von in GIO GIO 002 debou nce GIO001 E14 I O GIO Von in GIO GIO 001 debou nce GIO000 C16 I O GIO Von in GIO GIO 000 debou nce USB_DP A7 A 1O USBP Vppa33 usB USB D differential signal p
136. able Horizontal Sampling Points in a window e Programmable Vertical Sampling Points in a window Submit Documentation Feedback Peripheral Information and Electrical Specifications 117 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 9 1 4 VPFE Electrical Data Timing Table 5 17 Timing Requirements for VPFE PCLK Master Slave Mode see Figure 5 23 DM355 216 DM355 270 NO UNIT MIN MAX MIN MAX 1 toPCLk Cycle time PCLK 18 52 100 14 81 100 ns 2 tw PCLKH Pulse duration PCLK high 5 7 5 7 ns 3 tw PCLKL Pulse duration PCLK low 5 7 5 7 ns 4 tyPcLk Transition time PCLK 3 3 ns 1 The PCLK frequency must be less than or equal to half the VPSS clock frequency i e PCLK lt SYSCLK4 2 lt gt 1 By dag lea Figure 5 23 VPFE PCLK Timing Table 5 18 Timing Requirements for VPFE CCD Slave Mode see Figure 5 24 er DM355 UNIT MIN MAX 5 tsu CCDV PCLK Setup time CCD valid before PCLK edge 3 ns 6 th PCLK CCDV Hold time CCD valid after PCLK edge 2 ns 7 tsu HDV PCLK Setup time HD valid before PCLK edge 3 ns 8 th PCLK HDV Hold time HD valid after PCLK edge 2 ns 9 tsu VDV PCLK Setup time VD valid before PCLK edge 3 ns 10 th PCLK VDV Hold time VD valid after PCLK edge 2 ns 11
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138. air HY USB_DM Ap A lO USBP Vppa33 usB USB D differential signal pair HY USB_R1 C7 A O USBP USB Reference current output HY Connect to Vss usg rer Via 10K Q 1 resistor placed as close to the device as possible USB_ID D5 A 1O USBP Vppas3_usB USB operating mode identification pin HY For Device mode operation only pull up this pin to VDD with a 1 5K ohm resistor For Host mode operation only pull down this pin to ground VSS with a 1 5K ohm resistor If using an OTG or mini USB connector this pin will be set properly via the cable connector configuration Submit Documentation Feedback Device Overview 49 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State USB_VBUS E5 A I O USBP For host or device mode operation tie the HY VBUS USB power signal to the USB connector When used in OTG mode operation tie VBUS to the external charge pump and to the VBUS signal on the USB connector When the USB is not used tie VBUS to Ves uep USB_DRVVBU CR O USBP Von Digital output to control external 5 V supply S HY VSS_USB_REF C8 GND USBP Von USB Ground
139. al 2 Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback Device Overview 35 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Sp 2 5 Pin List Table 2 23 provides a complete pin description list in pin number order Table 2 23 DM355 Pin Descriptions Mux Control Name BGA Type Group Power PU Reset Description 1 Supply PD State CIN7 GIO101 N3 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE SPI2_SCLK GIO NOT USED SPl2 YCC 16 bit time multiplexed between chroma CB CR 07 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 07 SPI SPI2 Clock GIO GIO 101 PINMUXO 1 0 CIN_ 7 CIN6 GIO100 K5 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE SPI2_SDO GIO NOT USED oe YCC 16 bit time multiplexed between chroma CB CR 06 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 06 SPI SPI2 Data Out GIO GIO 100 PINMUXO0 3 2 CIN_ 6 CIN5 GIO099 M3 VO CCDC Vop vm PD in
140. al Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State MMCSD1_DAT B16 VO MMC Vpp in MMCSD1 DATA3 PINMUX3 9 8 GIO2 A3 GIO022 SD 2 UART2_RTS GIO UART 2 GIO GIO 022 UART2 RTS MMCSD1_DAT A16 VO MMC Vpp in MMCSD1 DATA2 PINMUX3 11 10 GI A2 GIO021 SD 021 UART2_CTS GIO UART 2 GIO GIO 021 UART2 CTS MMCSD1_DAT B15 VO MMC Vpp in MMCSD1 DATA1 PINMUX3 13 12 GI A1 GIO020 SD 020 UART2_RXD GIO UART 2 GIO GIO 020 UART2 Receive Data MMCSD1_DAT A18 VO MMC Vpp in MMCSD1 DATAO PINMUX3 15 14 GI AO GIO019 SD 019 UART2_TXD GIO UART 2 GIO GIO 019 UART2 Transmit Data CLKOUT1 D12 I O Clocks Vpp in CLKOUT Output Clock 1 PINMUX3 16 GIO1 GlO018 GIO 8 GIO GIO 018 CLKOUT2 A11 I O Clocks Vpp in CLKOUT Output Clock 2 PINMUX3 17 GIO1 GlO017 GIO 7 GIO GIO 017 CLKOUTS3 C11 UO Clocks Vop in CLKOUT Output Clock 3 PINMUX3 18 GIO1 GIO016 GIO 6 GIO GIO 016 l2C_SDA R13 VO l2Cc Vpp in 12C Serial Data PINMUX3 19 GIO1 Gloo15 GIO 5 GIO GIO 015 I2C_SCL R14 VO 1l2C Vpp in 12C Serial Clock PINMUX3 20 GIO1 Gloo14 GIO 4 GIO GIO 014 UART1_RXD R15 VO UART Vpp in UART1 Receive Data PINMUX3 21 GIO1 GlO013 1 3 GIO GIO GIO 013 UART1_TXD R17 VO UART Vpp in UART1 Transmit Dat
141. allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 05 PINMUXO 10 YIN_7 0 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 04 GIO GIO 091 YIN4 GIO090 P3 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE PINMUX0 10 YIN_7 GIO raw 04 0 YCC 16 bit time multiplexed between luma Y 04 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 03 GIO GIO 090 YIN3 GIO089 R3 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE PINMUX0 10 YIN_7 GIO raw 03 0 YCC 16 bit time multiplexed between luma Y 03 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 02 GIO GIO 089 YIN2 GIO088 P4 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE PINMUXO 10 YIN_7 GIO raw 02 0 YCC 16 bit time multiplexed between luma Y 02 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 01 GIO GIO 088 YIN1 GIO087 P2 VO CCDC Vpp vin PD in Standard CCD Analog Front End AFE PINMUXO 10 YIN_7 GIO raw 01 0 YCC 16 bit time multiplexed between luma loi YCC 08
142. ammable polarity for both frame synchronization and data clocks e Highly programmable internal clock and frame generation For more detailed information on the ASP peripheral see the Documentation Support section for the Audio Serial Port ASP Reference Guide Submit Documentation Feedback Peripheral Information and Electrical Specifications 137 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 14 1 ASP Electrical Data Timing 5 14 1 1 Audio Serial Port ASP Timing Table 5 35 Timing Requirements for ASP see Figure 5 41 DM355 ger UNIT MIN MAX 15 tc CLkK Cycle time CLK CLK ext 38 5 or 2P 2 3 ns 16 OTG CLKS Pulse duration CLKR X high or CLKR X low CLKS ext 19 25 or P 2 8 4 ns CLKR int 21 5 tsu FRH CKPL Setup time external FSR high before CLKR low ns CLKR ext l CLKR int 0 6 th CKRL FRH Hold time external FSR high after CLKR low CLKR ext 6 ns l CLKR int 21 7 tsu DRV CKRL Setup time DR valid before CLKR low CLKR ext ns CLKR int 8 th CKRL DRV Hold time DR valid after CLKR low CLKR ext 6 dia CLKX int 21 10 tsu FXH CKXL Setup time external FSX high before CLKX low Aree 6 ns l CLKX int 0 11 th CKXL FXH Hold time external FSX high after CLKX low CLKX ext 10 ns 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any
143. arate UART modules 1 with hardware flow control These modules performs serial to parallel conversion on data received from a peripheral device or modem and parallel to serial conversion on data received from the CPU Each UART also includes a programmable baud rate generator capable of dividing the 24MHz reference clock by divisors from 1 to 65 535 to produce a 16 x clock driving the internal logic The UART modules support the following features e Frequency pre scale values from 1 to 65 535 to generate appropriate baud rates e 16 byte storage space for both the transmitter and receiver FIFOs e Unique interrupts one for each UART e Unique EDMA events both received and transmitted data for each UART e 1 4 8 or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA e Programmable auto rts and auto cts for autoflow control supported on UART2 e Programmable serial data formats 5 6 7 or 8 bit characters Even odd or no parity bit generation and detection 1 1 5 or 2 stop bit generation e False start bit detection e Line break generation and detection e Internal diagnostic capabilities Loopback controls for communications link fault isolation Break parity overrun and framing error simulation e Modem control functions CTS RTS supported on UART2 5 11 1 UART Electrical Data Timing Table 5 26 Timing Requirements for UARTx Receive see Figure 5 35 DM355 NO ain TA
144. as a Video Processing Subsystem VPSS with two configurable video imaging peripherals e A Video Processing Front End VPFE e A Video Processing Back End VPBE The VPFE port provides an interface for CCD CMOS imager modules and video decoders The VPBE provides hardware On Screen Display OSD support and composite NTSC PAL and digital LCD output The DM355 peripheral set includes e An inter integrated circuit 12C Bus interface e Two audio serial ports ASP e Three 64 bit general purpose timers each configurable as two independent 32 bit timers e A 64 bit watchdog timer e Up to 104 pins of general purpose input output GPIO with programmable interrupt event generation modes multiplexed with other peripherals e Three UARTs with hardware handshaking support on one UART e Three serial port Interfaces SPI e Four pulse width modulator PWM peripherals e Four real time out RTO outputs e Two Multi Media Card Secure Digital MMC SD interfaces e A USB 2 0 full and high speed device and host interface e Two external memory interfaces An asynchronous external memory interface AEMIF for slower memories peripherals such as NAND and OneNAND A high speed synchronous memory interface for DDR2 mDDR For software development support the has a complete set of ARM development tools which include C compilers assembly optimizers to simplify programming and scheduling and a Windows debugger interface for visibility int
145. asen PU 0 1 F 1 4 EE Crystal C1 24MHzor C2 1 E 36 MHz e Io Figure 5 5 MXI1 24 MHz Oscillator The load capacitors C1 and C2 should be chosen such that the equation is satisfied typical values are C1 C2 10 pF CL in the equation is the load specified by the crystal manufacturer All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins MXI1 and MXO1 and to the Vos ve pin Ce C 6 Submit Documentation Feedback Peripheral Information and Electrical Specifications 99 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 3 Switching Characteristics Over Recommended Operating Conditions for 24 MHz System Oscillator PARAMETER MIN TYP MAX UNIT Start up time from power up until oscillating at stable frequency 4 ms Oscillation frequency 24 or 36 MHz ESR 60 Q Frequency stability 50 ppm 5 5 2 MXI2 27 MHz Oscillator optional oscillator The MXI2 27 MHz oscillator provides an optional reference clock for the s VPSS module The on chip oscillator requires an external 27 MHz crystal connected across the MXI2 and MSC pins along with two load capacitors as shown in Figure 5 6 The external crystal load capacitors must be connected only to the 27 MHz osc
146. bell application and other low cost portable digital video applications Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality the DM355 combines high performance high quality low power consumption at a very low price point The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation The interface is flexible enough to support various types of CCD and CMOS sensors signal conditioning circuits power management DDR mDDR memory SRAM NAND shutter Iris and auto focus motor controls etc The processor core is an ARM926EU S RISC processor The ARM926EU S is a 32 bit processor core that performs 32 bit and 16 bit instructions and processes 32 bit 16 bit and 8 bit data The core uses pipelining so that all parts of the processor and memory system can operate continuously The ARM core incorporates e A coprocessor 15 CP15 and protection module e Data and program Memory Management Units MMUs with table look aside buffers e Separate 16K byte instruction and 8K byte data caches Both are four way associative with virtual index virtual tag VIVT DM355 performance is enhanced by its MPEG JPEG co processor The MPEG JPEG co processor performs the computational operations required for image processing JPEG compression and MPEG1 2 4 video and imaging standards The device h
147. between luma and chroma of the upper channel Y CB CR 07 SPI SPI2 Clock GIO GIO 101 Standard CCD Analog Front End AFE NOT USED CING e YCC 16 bit Time multiplexed between chroma CB SR 06 GIO100 K5 V O Z PD e YCC 8 bit which allows for two simultaneous decoder inputs it is time SPI2 SDO Von vn multiplexed between luma and chroma of the upper channel Y CB CR 06 8 SPI SPI2 Data Out GIO GIO 100 Standard CCD Analog Front End AFE Raw 13 CIN5 e YCC 16 bit Time multiplexed between chroma CB SR 05 GIO099 M3 VO Z PD e YCC 8 bit which allows for two simultaneous decoder inputs it is time SPI2_SDEN Von vn multiplexed between luma and chroma of the upper channel Y CB CR 05 A 0 SPI SPI2 Chip Select GIO GIO 099 Standard CCD Analog Front End AFE Raw 12 CIN4 e YCC 16 bit Time multiplexed between chroma CB SR 04 GI0098 L4 VOZ PD e YCC 8 bit which allows for two simultaneous decoder inputs it is time SPl2_SDEN Von vn multiplexed between luma and chroma of the upper channel Y CB CR 04 Alt SPI SPI2 Data In GIO GIO 098 Standard CCD Analog Front End AFE Raw 11 e YCC 16 bit Time multiplexed between chroma CB SR 03 CIN3 PD i aahi Gl0097 J4 O Z TER e YCC 8 bit which allows for two simultaneous decoder inputs it is time R multiplexed between luma and chroma of the upper channel Y CB CR 03 GIO GIO 097 Standard CCD Analog Front End AFE Raw 10 e YCC 16 bit Time multiplexed between chroma CB SR 0
148. ble 2 12 MMC SD Terminal Functions da TEXAS INSTRUMENTS www ti com TERMINAL TYPE OTHER 3 DESCRIPTION NAME NO de e Ni Volz ae MMCSDO Clock o p Volz Wis MMCSDO Command MMCSDO_ DATAO B14 VO Z Von MMCSDO DATAO MMCSDO_ DATA D14 VO Z Von MMCSDO DATA MMCSDO_ DATAZ B13 VO Z Von MMCSDO DATA2 MMCSDO_ DATAS A14 VO Z Von MMCSDO DATA3 MMCSD1 MMCSD1 Clock CLK C15 VO Z Von Gloo24 GIO GIO 024 MMCSD1 MMCSD1 Command CMD A17 VO Z Von GlO023 GIO GIO 023 MMCSD1_ DATAO MMCSD1 DATAO GI0019 A18 VO Z Von GIO GIO 019 UART2_T UART2 Transmit data XD MMCSD1_ DATA1 MMCSD1 DATA1 GI0020 B15 VO Z Von GIO GIO 020 UART2_R UART2 Receive data XD MMCSD1_ DATA2 MMCSD1 DATA2 Glo021 A16 VO Z Von GIO GIO 021 UART2_C UART2 CTS TS MMCSD1_ DATA3 MMCSD1 DATA3 GI0022 B16 VO Z Von GIO GIO 022 UART2_R UART2 RTS TS 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 28 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEP
149. com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA ID Type Group Power Supply PU PD Reset State Description Mux Control CIN3 GIO097 J4 UO CCDC GIO Vop vn PD in Standard CCD Analog Front End AFE raw 1 1 YCC 16 bit time multiplexed between chroma CB CR 03 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 03 GIO GIO 097 PINMUXO 8 CIN_32 CIN2 GIO096 J5 UO CCDC GIO Vop vn PD Standard CCD Analog Front End AFE raw 10 YCC 16 bit time multiplexed between chroma CB CR 02 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 02 GIO GIO 096 PINMUXO 8 CIN_32 CIN1 GIO095 L3 UO CCDC GIO Vop vn PD Standard CCD Analog Front End AFE raw 09 YCC 16 bit time multiplexed between chroma CB CR 01 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 01 GIO GIO 095 PINMUXO 9 CIN_10 CINO GIO094 J3 UO CCDC GIO Vop vn PD Standard CCD Analog Front End AFE raw 08 YCC 16 bit time multiplex
150. cts and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement the
151. d TEXAS INSTRUMENTS www ti com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 1 TMS320DM355 Digital Media System on Chip DMSoC 1 1 Features High Performance Digital Media System on Chip 216 and 270 MHz ARM926EJ S Clock Rate Fully Software Compatible With ARM9 ARM926EJ S Core Support for 32 Bit and 16 Bit Thumb Mode Instruction Sets DSP Instruction Extensions and Single Cycle MAC e ARM Jazelle Technology EmbeddedICE RT Logic for Real Time Debug ARM9 Memory Architecture e 16K Byte Instruction Cache 8K Byte Data Cache e 32K Byte RAM 8K Byte ROM Little Endian Video Processing Subsystem Front End Provides A Hardware IPIPE for Real Time Image Processing e CCD and CMOS Imager Interface 14 Bit Parallel AFE Analog Front End Interface Up to 67 5 MHz Glueless Interface to Common Video Decoders BT 601 BT 656 Digital YCbCr 4 2 2 8 16 Bit Interface Histogram Module Resize Engine Resize Images From 1 16x to 8x Separate Horizontal Vertical Control Two Simultaneous Output Paths e Back End Provides ei e Hardware On Screen Display OSD e Composite NTSC PAL video encoder output 7 8 16 bit YCC and Up to 18 Bit RGB666 Digital Output BT 601 BT 656 Digital YCbCr 4 2 2 8 16 Bit Interface Supports digital HDTV 720p 1080i output for connection to external y encoder External Memory Interfaces EMIFs
152. d use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document I C bus is a trademark of Texas Instruments Windows is a trademark of Microsoft All other trademarks are the property of their respective owners PRODUCT PREVIEW information concerns products in the formative or design phase of development Characteristic data and other specifications are design goals Texas Instruments reserves the right to change or discontinue these products without notice Copyright 2007 2007 Texas Instruments Incorporated PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 d Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 IEEE 1149 1 JTAG e 337 Pin Ball Grid Array BGA Package Boundary Scan Compatible ZCE Suffix 0 65 mm Ball Pitch ETB Embedded Trace Buffer with e 90nm Process Technology 4K Bytes Trace Buffer memory e 3 3 V and 1 8 V I O 1 3 V Internal Device Revision ID Readable by ARM 2 TMS320DM355 Digital Media System on Chip DMSoC Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 1 2 Description The DM355 is a highly integrated programmable platform for digital still camera digital photo frames IP security cameras 4 channel digital video recorders video door
153. deo buffer DAC output DAC 1000 ohm to VFB IBIAS F2 AI O Video Video DAC External resistor 2550 Ohms to DAC GND connection for current bias configuration VFB G1 AI O Video Video DAC Pre video buffer DAC output DAC 1000 ohm to IOUT 1070 ohm to TVOUT TVOUT F1 A VO Video Vppais_pac Video DAC Analog Composite NTSC PAL DAC output SeeFigure 5 31 andFigure 5 32 for circuit connection VDDA18V DAC L7 PWR Video Video DAC Analog 1 8V power 2 DAC Vssa DAC L8 GND Video Video DAC Analog 1 8V ground 7 DAC DDR_CLK wa VO DDR Von pop out L DDR Data Clock DDR_CLK W8 VO DDR VDD_DDR out H DDR Complementary Data Clock DDR_RAS T6 UO DDR VDD_DDR out H DDR Row Address Strobe DDR_CAS v9 UO DDR VDD_DDR out H DDR Column Address Strobe DDR WE W10 I O DDR VDD_DDR out H DDR Write Enable active low DDR_CS T8 VO DDR VDD_DDR out H DDR Chip Select active low DDR_CKE V10 I O DDR VDD_DDR out L DDR Clock Enable DDR_DQM 1 U15 VO DDR VDD_DDR out L Data mask outputs DQMO For DDR_DQ 7 0 DDR_DQM 0 T12 UO DDR VDD_DDR out L Data mask outputs DQM1 For DDR_DQ 15 8 DDR_DQS 1 V15 VO DDR VDD DDR in Data strobe input outputs for each byte of the 16 bit data bus used to synchronize the data transfers Output to DDR when writing and inputs when reading DQS1 For DDR_DQ 15 8 Submit Documentation Feedback Device Overview 41 PRODUCT PREVIEW MalAddd LONGOUd TMS
154. dia System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 14 Audio Serial Port ASP DM355 includes two separate ASP controllers The primary use for the audio serial port ASP is for audio interface purposes The primary audio modes that are supported by the ASP are the AC97 and IIS modes In addition to the primary audio modes the ASP supports general serial port receive and transmit operation but is not intended to be used as a high speed interface The ASP is backward compatible with other TI ASPs The ASP supports the following features e Full duplex communication e Double buffered data registers which allow a continuous data stream e Independent framing and clocking for receive and transmit e External shift clock generation or an internal programmable frequency shift clock e Double buffered data registers which allow a continuous data stream e Independent framing and clocking for receive and transmit e Direct interface to industry standard codecs analog interface chips AlCs and other serially connected analog to digital A D and digital to analog D A devices e Direct interface to AC97 compliant devices the necessary multiphase frame synchronization capability is provided e Direct interface to IIS compliant devices e Awide selection of data sizes including 8 12 16 20 24 and 32 bits e Law and A Law commanding e 8 bit data transfers with the option of LSB or MSB first e Progr
155. e 6 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 2 Memory Map Summary TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 3 shows the memory map address ranges of the device Table 2 3 depicts the expanded map of the Configuration Space 0x01C0 0000 through 0x01FF FFFF The device has multiple on chip memories associated with its processor and various subsystems To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters The bus masters are the ARM EDMA USB and VPSS Table 2 2 DM355 Memory Map Start Address End Address Size Bytes ARM EDMA USB VPSS Mem Map Mem Map Mem Map Mem Map 0x0000 0000 0x0000 3FFF 16K ARM RAMO Instruction 0x0000 4000 0x0000 7FFF 16K ARM RAMI Reserved Reserved Instruction 0x0000 8000 0x0000 FFFF 32K ARM ROM Instruction only 8K used 0x0001 0000 0x0001 3FFF 16K ARM RAMO Data ARM RAMO ARM RAMO 0x0001 4000 0x0001 7FFF 16K ARM RAM1 Data ARM RAM1 ARM RAM1 0x0001 8000 0x0001 FFFF 32K ARM ROM Data ARM ROM ARM ROM only 8K used 0x0002 0000 0x000F FFFF 896K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC OFFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K A
156. e ACCUP_EN 0 no A C coupling DINV 1 invert See the TMS320DM355 ARM Subsystem Reference Guide and the TMS320DM355 DMSoC Video Processing Back End VPBE User s Guide for more information on the VDAC_CONFIG register and Video Buffer C For proper TVOUT voltage you must connect the pin TVOUT directly to the TV No A C coupling capacitor or termination resistor is necessary on your DM355 board Also it is assumed that the TV has no internal A C coupling capacitor but does have an internal termination resistor as shown in this diagram TVOUT voltage will range from VoLviDBUF t0 VoxvipBurF See Section 4 3 for the voltage specifications Figure 5 32 DAC With Buffer Circuit 126 Peripheral Information and Electrical Specifications Submit Documentation Feedback 49 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC Sep SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 10 USB 2 0 DM355 includes a USB Controller Module that is built around the Mentor USB Multi Point High Speed Dual Role Controller endpoint memory CPPI DMA controller and UTMI PHY The controller conforms to USB 2 0 Specification The USB2 0 peripheral supports the following features e USB 2 0 peripheral at speeds high speed HS 480 Mb s and full speed FS 12 Mb s e USB 2 0 host at speeds HS FS and low speed LS 1 5 Mb s e All transfer modes control bulk interrupt and isochronous e Four Transmit TX and four Receive RX endpoints in add
157. e AFE TG to indicate the which of two frames is input to the CCDC module for sensors with interlaced output CCDC handles 1 or 2 field sensors in hardware GIO GIO 083 CCDC MODE 7 CC DMD amp CCDC MODE 5 SW EN PCLK GIO082 T3 VO CCDC Vop vw PD in Pixel clock input strobe for lines CI7 through PINMUX0 14 PCLK GIO YI0 GIO GIO 082 YOUT7 R7 C3 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT6 R6 A4 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT5 R5 B4 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT4 R4 B3 UO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT3 R3 B2 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT2 G7 A3 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUT1 G6 A2 VO VENC Vpp vout in Digital Video Out VENC settings determine function YOUTO0 G5 B1 UO VENC Men vout in Digital Video Out VENC settings determine function COUT7 G4 C2 UO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 1 0 COU GIO081 PWMO GIO function T7 PWMO GIO GIO 081 PWMO COUT6 G3 D2 VO VENC Vpp vout in Digital Video Out VENC settings determine PINMUX1 3 2 COU GIO080 PWM1 GIO function T6 PWM1 GIO GIO 080 PWM1 4 Submit Documentation Feedback Device Overview 39
158. e VPSS clock frequency i e PCLK lt SYSCLK4 2 VCLKIN CO mw FY AA Ly S k 22 6 Ly 18 VCLK Positive Edge A M S e Clocking VCLK Negative Edge Clocking k 23 24 20 A e gt j 20 vro XK KX gt 2 nit 26 Kee SS GEN Ce ER A VCLKIN PCLK or EXTCLK B VCTL HSYNC VSYNC FIELD and LCD_OE C VDATA COUT 7 0 YOUTI7 0 R 7 3 G 7 2 and B 7 3 Figure 5 30 VPBE Control and Data Output Timing With Respect to VCLK 5 9 2 4 DAC and Video Buffer Electrical Data Timing The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer configuration In the DAC only configuration the internal video buffer is not used and an external video buffer is attached to the DAC In the DAC and video buffer configuration the DAC and internal video buffer are both used and a TV cable may be attached directly to the output of the video buffer See Figure 5 31 and Figure 5 32 for recommenced circuits for each configuration 124 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Vdeo DAC Buffer V VN VREF XX IBIAS IOUT D XXI TVOUT Cpa Reias RLOAD 0 1 pF 25500 4990 Vv Vv DAC Digital Input DAC Output Current DIN lt 9 0 gt lout mA A A MSB a 1 4 mA
159. e the AC97 and IIS modes In addition to the primary audio modes the ASP supports general serial port receive and transmit operation but is not intended to be used as a high speed interface TMS320DM35x DMSoC Serial Peripheral Interface SPI Reference Guide This document describes the serial peripheral interface SPI in the TMS320DM35x Digital Media System on Chip DMSoC The SPI is a high speed synchronous serial input output port that allows a serial bit stream of programmed length 1 to 16 bits to be shifted into and out of the device at a programmed bit transfer rate The SPI is normally used for communication between the DMSoC and external peripherals Typical applications include an interface to external I O or peripheral expansion via devices such as shift registers display drivers SPI EPROMs and analog to digital converters TMS320DM35x DMSoC Universal Asynchronous Receiver Transmitter UART Reference Guide This document describes the universal asynchronous receiver transmitter UART peripheral in the TMS320DM35x Digital Media System on Chip DMSoC The UART peripheral performs serial to parallel conversion on data received from a peripheral device and parallel to serial conversion on data received from the CPU TMS320DM35x DMSoC Inter Integrated Circuit I2C Peripheral Reference Guide This document describes the inter integrated circuit SC peripheral in the TMS320DM35x Digital Media System on Chip DMSoC The DC peripheral p
160. ection Matrix Slave Module DMA Master ARM Internal MPEG JPEG Config Bus Registers and DDR EMIF Memory Memory Co processor Memory Memory ARM V V V V VPSS V DMA Master Peripherals USB V V EDMA3TCO V V V EDMA3TC1 V V V 3 14 2 EDMA Controller Submit Documentation Feedback The EDMA controller handles all data transfers between memories and the device slave peripherals on the DM355 device These are summarized as follows e Transfer to from on chip memories ARM program data RAM MPEG JPEG Co processor memory e Transfer to from external storage DDR2 mDDR SDRAM Asynchronous EMIF OneNAND flash NAND flash Smart Media SD MMC xD media storage e Transfer to from peripherals ASP SPI 12C PWM RTO GPIO Timer WDT UART MMC SD Detailed Device Description 87 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 88 www ti com The EDMA Controller consists of two major blocks the Transfer Controller TC and the Channel Controller CC The CC is a highly flexible Channel Controller that serves as the user interface and event interface for the EDMA system The CC supports 64 event channels and 8 QDMA channels The CC consists of a scalable Parameter RAM PaRAM that supports flexible ping pong circular buffe
161. ed between chroma CB CR 00 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 00 GIO GIO 094 PINMUXO 9 CIN_10 YIN7 GIO093 L5 UO CCDC GIO Vop vn PD Standard CCD Analog Front End AFE raw 07 YCC 16 bit time multiplexed between luma Y 07 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 07 GIO GIO 093 PINMUX0O 10 YIN_7 0 YIN6 GIO092 M4 UO CCDC GIO Vop vn PD Standard CCD Analog Front End AFE raw 06 YCC 16 bit time multiplexed between luma Y 06 YCC 08 bit which allows for 2 simultaneous decoder inputs it is time multiplexed between luma and chroma of the lower channel Y CB CR 06 GIO GIO 092 PINMUX0O 10 YIN_7 0 Submit Documentation Feedback Device Overview 37 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 os Table 2 23 DM355 Pin Descriptions continued Mux Control Name BGA Type Group Power PU Reset Description ID Supply PD State YIN5 GIO091 M5 VO CCDC Vop vw PD in Standard CCD Analog Front End AFE GIO raw 05 YCC 16 bit time multiplexed between luma Y 05 YCC 08 bit which
162. ers An overview of the pin multiplexing is shown in Table 3 12 Table 3 12 Peripheral Pin Mux Overview Peripheral Muxed With Primary Function Secondary Function Tertiary Function VPFE video in GPIO and SPI2 VPFE video in SPI2 GPIO VPBE video out GPIO PWM and RTO VPBE video out PWM and RTO GPIO AEMIF GPIO AEMIF GPIO none ASPO GPIO ASPO GPIO none MMC SD1 GPIO and UART2 MMC SD1 GPIO UART2 CLKOUT GPIO CLKOUT GPIO none 12C GPIO 12C GPIO none UART1 GPIO UART1 GPIO none SPI GPIO SPI GPIO none SPIO GPIO SPIO GPIO none 3 9 1 Hardware Controlled Pin Multiplexing 78 Use the Asynchronous EMIF configuration pins AECFG 3 0 for hardware pin mux control AECFG 3 0 control the partitioning of the AEMIF addresses and GPIOs at reset which allows you to properly configure the number of AEMIF address pins required by the boot device while unused addresses pins are available as GPIOs These settings may be changed by software after reset by programming the PinMux2 register The PinMux2 register is in the System Control Module As shown in Table 3 13 the number of address bits enabled on the AEMIF is selectable from O to 16 Pins that are not assigned to another peripheral and not enabled as address signals become GPIOs except EM_A 2 1 The enabled address signals are always contiguous from EM DATT upwards bits cannot be skipped The exception to this are EM_A 2 1 These signals can be
163. etermine function GIO GIO 076 GIO076 E4 VO Von vom PWM2D PWM2D RTO3 RTO3 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 2 4 14 Pulse Width Modulator PWM Interface The provides Pulse Width Modulator PWM interface Table 2 20 PWM Terminal Functions TERMINAL 4 GT TYPE OTHER 3 DESCRIPTION NAME NO COUT7 G4 Digital Video Out VENC settings determine function GIO GIO 081 GIO081 C2 VOZ Voo vout PWMO PWMO COUT6 G3 Digital Video Out VENC settings determine function GIO GIO 080 GIO080 be ue Von vom pw PWM1 COUT5 G2 Digital Video Out VENC settings determine function GIO GIO 079 GI0079 C1 VO Von vom PWM2A PWM2A RTOO RTOO COUT4 B7 Digital Video Out VENC settings determine function GIO GIO 078 GI0078 D3 VO Von vom PWM2B PWM2B RTO1 RTO1 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used
164. etermine function GIO GIO 077 PWM2C PWM2C RTO2 COUT4 B7 Peer A GI0078 D3 VOIZ GE SC Video Out VENC settings determine function GIO GIO 078 PWM2B PWM2B RTO1 Submit Documentation Feedback Device Overview 25 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 11 GPIO Terminal Functions continued TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO COUT5 G2 a v i i GI0079 C1 VO Z Ne dee GE Video Out VENC settings determine function GIO GIO 079 PWM2A PWM2A RTOO COUT6 G3 Digital Video Out VENC settings determine function GIO GIO 080 G10080 be ZER Vop_vouT PWM1 PWM1 COUT7 G4 Digital Video Out VENC settings determine function GIO GIO 081 GIO081 c2 SS Von vout PWMo PWMO POLK T3 O Z Po Pixel clock input strobe for lines CI7 through YO GIO GIO 082 GlO082 Vop vm Write enable input signal is used by external device AFE TG to gate the DDR CAM_WE PD output of the CCDC module Alternately the field identification input signal is N_FIELD R5 VO Z V used by external device AFE TG to indicate the which of two frames is input to GlO083 DD VIN the CCDC module for sensors with interlaced output CCDC handles 1 or 2 field sensors in hardware GIO GIO 083 CAM VD PD Vertical synchronization signal t
165. evices and then begin a SPI transfer at the rising edge of the master clock CLKX CLKX f H H ZX j M34 gt e was Al p M42 FSX st M37 le M38 k k M36 DX Bn L Bit n 1 LI m i X m X n4 X M39 e a i M40 Figure 5 43 ASP as SPI CLKSTP 11b CLKXP 0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 141 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 41 ASP as SPI Timing Requirements CLKSTP 10b CLKXP 1 see Figure 5 44 MASTER NO UNIT MIN MAX M49 tsu DRV CKXH Setup time DR valid before CLKX high 11 ns M50 thckxH DRV Hold time DR valid after CLKX high 0 ns Table 5 42 ASP as SPI Switching Characteristics CLKSTP 10b CLKXP 1 see Figure 5 44 MASTER NO PARAMETER UNIT MIN MAX M52 te CKX Cycle time CLKX Bae ns M43 tackxH EXH Delay time CLKX high to FSX high T 1 T 3 ns M44 taexL ckxL Delay time FSX low to CLKX low D 2 D 2 ns MAD ta ckxL DXV Delay time CLKX low to DX valid 2 6 ns Disable time DX high impedance following last data bit from MAD tdis CKXH DXHZ CLKX high g imp 9 D 3 D 3 ns 1 P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 2 T CLKX period 1 CLKGDV x P C
166. f each line in a Paxel e Support for an Accumulation Sum Mode instead of Peak mode e Accumulate Focus Value in a Paxel e Support for up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction The number of horizontal paxels is limited by the memory size and cost while the vertical number of paxels is not Therefore the number of paxels in horizontal direction is smaller than the number of paxels in vertical direction e Programmable width and height for the Paxel All paxels in the frame will be of same size e Programmable red green and blue position within a 2x2 matrix e Separate horizontal start for paxel and filtering e Programmable vertical line increments within a paxel e Parallel IIR filters configured in a dual biquad configuration with individual coefficients 2 filters with 11 coefficients each The filters are intended to compute the sharpness peaks in the frame to focus on The following features are supported by the AE AWB engine e Support for input from DDR2 mDDR SDRAM in addition to the CCDC port e Accumulate clipped pixels along with all non saturated pixels e Support for up to 36 horizontal windows e Support for up to 128 vertical windows e Programmable width and height for the windows All windows in the frame will be of same size e Separate vertical start co ordinate and height for a black row of paxels that is different than the remaining color paxels e Programm
167. f refresh and power down The DDR mDDR device can be put into self refresh and power down states 86 Detailed Device Description Submit Documentation Feedback INSTRUMENTS Digital Media System on Chip DMSoC S SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 14 64 Bit Crossbar Architecture The DM355 uses a 64 bit crossbar architecture to control access between device processors subsystems and peripherals It includes an EDMA Controller consisting of a DMA Transfer Controller TC and a DMA Channel Controller CC The TC provides two DMA channels for transfer between slave peripherals The CC provides a user and event interface to the EDMA system It includes up to 64 event channels to which all system synchronization events can be mapped and 8 auto submit quick channels QDMA In most ways these channels are identical A channel refers to a specific event that can cause a transfer to be submitted to the TC as a Transfer Request 3 14 1 Crossbar Connections There are five transfer masters TCs have separate read and write connections connected to the crossbar ARM the Video Processing Sub system VPSS the master peripherals USB and two EDMA transfer controllers These can be connected to four separate slave ports ARM the DDR EMIF and CFG bus peripherals Not all masters may connect to all slaves Connection paths are indicated by V at intersection points shown in Table 3 18 Table 3 18 Crossbar Conn
168. following features e Two transfer controllers e 64 bit wide read and write ports per channel e Up to four in flight transfer requests TR e Programmable priority level e Supports two dimensional transfers with independent indexes on source and destination EDMA3CC manages the 3rd dimension e Support for increment and constant addressing modes e Interrupt and error support Parameter RAM Each EDMA is specified by an eight word 32 byte parameter table contained in Parameter RAM PaRAM within the CC DM355 provides 128 PaRAM entries one for each of the 64 DMA channels and for 64 QDMA Linked DMA entries Detailed Device Description Submit Documentation Feedback R3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC 3 14 2 1 SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 DMA Channels Can be triggered by External events for example ASP TX Evt and RX Evt Software writing a 1 to the given bit location or channel of the Event Set register or Chaining to other DMAs QDMA The Quick DMA QDMA function is contained within the CC DM355 implements 8 QDMA channels Each QDMA channel has a selectable PaRAM entry used to specify the transfer A QDMA transfer is submitted immediately upon writing of the trigger parameter as opposed to the occurrence of an event as with EDMA The QDMA parameter RAM may be written by any Config bus master through the Config Bus and by DMAs through the Config Bus bridge
169. gital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 ADDS CHANGES DELETES Updated Section 5 9 1 Video Processing Front End VPFE Updated Section 5 9 1 1 CCD Controller CCDC Updated Section 5 9 1 2 IPIPE Image Pipe Removed CFALD CFA Multiply Mask Lens Distortion Module section Removed Auto Exposure AE and Auto White Balance AWB Engine section Updated Table 5 17 Timing Requirements for VPFE PCLK Master Slave Mode Table 5 21 Timing Requirements for VPBE CLK Inputs e Added footnote Table 5 24 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK e Updated VCLKIN PCLK or EXTCLK footnote Updated Section 5 10 USB 2 0 Section 5 18 IEEE 1149 1 JTAG e Removed Scan Chain subsection 152 Revision History Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 7 Mechanical Data The following table s show the thermal resistance characteristics for the PBGA ZCE mechanical package Note that micro vias are not required Contact your TI representative for routing recommendations 7 1 Thermal Data for ZCE The following table shows the thermal resistance characteristics for the PBGA ZCE mechanical package Table 7 1
170. grade device e Support for REC656 CCIR 656 standard YCbCr 422 format either 8 or 16 bit e Support for YCbCr 422 format either 8 or 16 bit with discrete H and VSYNC signals e Support for up to 14 bit input e Support for color space conversion e Generates optical black clamping signals e Support for shutter signal control e Support for digital clamping and black level compensation e Fault pixel correction based on a lookup table that contains row and column position of the pixel to be corrected Submit Documentation Feedback Peripheral Information and Electrical Specifications 115 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 9 1 2 116 www ti com Support for program lens shading correction Support for 10 bit to 8 bit A law compression Support for a low pass filter prior to writing to SDRAM If this filter is enabled 2 pixels each in the left and right edges of each line are cropped from the output Support for generating output to range from 16 bits to 8 bits wide 8 bits wide allows for 50 saving in storage area Support for down sampling via programmable culling patterns Ability to control output to the DDR2 via an external write enable signal Support for up to 32K pixels image size in both the horizontal and vertical direction IPIPE Image Pipe The hardware Image Pipe IPIPE is a
171. gt 17 coe Ga MSB OUT DATA LSB OUT Figure 5 38 SPI Master Mode External Timing Clock Phase 1 Submit Documentation Feedback Peripheral Information and Electrical Specifications 133 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 13 Inter Integrated Circuit 12C The inter integrated circuit I2C module provides an interface between and other devices compliant with Philips Semiconductors Inter IC bus I C bus specification version 2 1 and connected by way of an DC bus External components attached to this 2 wire serial bus can transmit receive up to 8 bit data to from the DM355 through the DC module The 12C port supports e Compatible with Philips DC Specification Revision 2 1 January 2000 e Fast Mode up to 400 Kbps no fail safe I O buffers e Noise Filter to Remove Noise 50 ns or less e Seven and Ten Bit Device Addressing Modes e Master Transmit Receive and Slave Transmit Receive Functionality e Events DMA Interrupt or Polling e Slew Rate Limited Open Drain Output Buffers For more detailed information on the DC peripheral see the Documentation Support section for the Inter Integrated Circuit GC Module Reference Guide 134 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 13 1 DC Electrical Data Timing
172. gt 27 MHz are needed e g GlO069 PD 74 25 MHz for HDTV digital output SCH G3 V O Z V GIO GIO 069 PWM3D DD VOUT Digital Video Out B2 PWM3D VCLK Video Encoder Video Output Clock GIO068 He oe Von vom GIO GIO 068 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 4 To reduce EMI and reflections depending on the trace length approximately 22 Q to 50 Q damping resistors are recommend on the following outputs placed near the DM355 YOUT 0 7 COUT 0 7 HSYNC VSYNC LCD_OE FIELD EXTCLK VCLK The trace lengths should be minimized Submit Documentation Feedback Device Overview 17 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 da TEXAS Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 www ti com Table 2 8 Analog Video Terminal Functions TERMINAL 1 2 TYPE OTHER DESCRIPTION NAME NO Video DAC Reference voltage output 0 45V 0 1uF to GND When the DAC is not VREF at AMO used the VREF signal should be connected to Vss IOUT E1 AVOIZ Video DAC Pre video buffer DAC output 1000 ohm to VFB When the DAC is not used the IOUT signal sh
173. hat can be either an input slave mode or an Glo084 R4 VO Z V output master mode Tells the CCDC when a new frame starts DDENIN GIO GIO 084 CAM HD PD Horizontal synchronization signal that can be either an input slave mode or an GIO085 N5 VO Z V output master mode Tells the CCDC when a new line starts RSR GIO GIO 085 Standard CCD Analog Front End AFE raw 00 YCC 16 bit time multiplexed YINO PD between luma Y 00 YCC 08 bit which allows for 2 simultaneous decoder GIO086 P5 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel BCC Y CB CR 00 GIO GIO 086 Standard CCD Analog Front End AFE raw 01 YCC 16 bit time multiplexed YINI PD between luma Y 01 YCC 08 bit which allows for 2 simultaneous decoder GI0O087 P2 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel DD_VIN Y CB CR 01 GIO GIO 087 Standard CCD Analog Front End AFE raw 02 YCC 16 bit time multiplexed YIN2 PD between luma Y 02 YCC 08 bit which allows for 2 simultaneous decoder GIO088 P4 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel DD VIN Y CB CR 02 GIO GIO 088 Standard CCD Analog Front End AFE raw 03 YCC 16 bit time multiplexed YIN3 PD between luma Y 03 YCC 08 bit which allows for 2 simultaneous decoder GIO089 R3 VO Z V inputs it is time multiplexed between luma and chroma of the lower channel ER Y CB CR 03 GIO GIO 089 Standard
174. he includes three UART ports These ports are multiplexed with GIO and other signals Table 2 15 UART Terminal Functions TERMINAL Di 2 3 NAME NO TYPE OTHER DESCRIPTION UARTO_RXD U18 Vnp UARTO Receive data Used for UART boot mode UARTO_TXD T18 O Vnp UARTO Transmit data Used for UART boot mode UART1_RXD UART1 Receive data GIO013 ae ue Yoo GIO GIO013 UART1_TXD UART1 Transmit data GIO012 Riz SE Von GIO GIO012 UA MMCSD1 DATA2 Glo021 A16 VO Z Von GIO Gloo21 UART2 CTS UART2 CTS E MMCSD1 DATA3 Glo022 B16 VO Z Von GIO GIO022 UART2 RTS UART2 RTS oe MMCSD1 DATA Gl0020 B15 VO Z Von GIO GIO020 UART2 RXD UART2 RXD SBS 30 Device Overview l Input O Output Z High impedance S Supply voltage GND Ground A Analog signal Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 15 UART Terminal Functions continued TERMINAL za TAME ge TYPE OTHER 3 DESCRIPTION ce MMCSD1 DATAO GIO019 A18 VO Z Vpop GIO GIO019 UART2 TXD UART2 TXD 2 4 10 FC Interface The includes
175. ignal should be left as a No Connect Output for video oscillator 27 MHz Optional use only if 27MHz derived from MXO2 TH o v MXI1 and PLL does not provide sufficient performance for Video DAC When the De MXOz2 is not used and powered down the MXO2 signal should be left as a No Connect 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 32 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 4 13 Real Time Output RTO Interface The provides Real Time Output RTO interface Table 2 19 RTO Terminal Functions TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO COUT5 G2 Digital Video Out VENC settings determine function GIO GIO 079 GI0079 C1 VO Von vom PWM2A PWM2A RTOO RTOO COUT4 B7 Digital Video Out VENC settings determine function GIO GIO 078 GlO078 D3 VO VDD vout PWM2B PWM2B RTO1 RTO1 COUT3 B6 Digital Video Out VENC settings determine function GIO GIO 077 GIO077 E3 1 O Z Vop vouT PWM2C PWM2C p RTO2 RTO2 COUT2 B5 Digital Video Out VENC settings d
176. illator ground pin Vss_mx2 Do not connect to board ground Vss Also the PLL power pin Vppa ua Should be connected to the power supply through a ferrite bead L1 in the example circuit shown in Figure 5 6 Vos was VpDA_PLL2 Vssa_PLL2 Crystal 27 MHz 0 1 F C1 Ge C2 1F e Figure 5 6 MXI2 27 MHz System Oscillator The load capacitors C1 and C2 should be chosen such that the equation is satisfied typical values are C1 C2 10 pF CL in the equation is the load specified by the crystal manufacturer All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins MXI and MXO and to the Vgg ve pin CC C 2 E C C3 Table 5 4 Switching Characteristics Over Recommended Operating Conditions for 27 MHz System Oscillator PARAMETER MIN TYP MAX UNIT Start up time from power up until oscillating at stable frequency 4 ms Oscillation frequency 27 MHz ESR 60 Q Frequency stability 50 ppm 100 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 5 3 Clock PLL Electrical Data Timing Input and Output Clocks Table 5 5 Timing Requirements for MXI1 CLKIN1 see Figure 5 7
177. input signal is used FIELD R5 V O Z PD by external device AFE TG to indicate which of two frames is input to the CCDC VDD viN module for sensors with interlaced output CCDC handles 1 or 2 field sensors in GIO083 a hardware GIO GIO 083 PCLK T3 Volz PD Pixel clock input strobe for lines C17 through Y10 GIO082 Vop vw GIO GIO 0082 2 4 2 Image Data Output Video Processing Back End VPBE The Video Encoder Digital LCD interface module in the video processing back end has an external signal interface for digital image data output as described in Table 2 7 and Table 2 8 The digital image data output signals support multiple functions interfaces depending on the display mode selected The following table describes these modes Parallel RGB mode with more than RGB565 signals requires enabling pin multiplexing to support e for RGB666 mode Submit Documentation Feedback Device Overview 15 PRODUCT PREVIEW MalAddd LONAOYd Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 6 Signals for VPBE Display Modes PIN NAME YCC16 YCC8 PRGB SRGB REC656 HSYNC HSYNC HSYNC HSYNC HSYNC GIO073 VSYNC VSYNC VSYNC VSYNG VSYNC GlO072 LCD_OE As needed As needed As needed As needed GIOO071 FIELD As needed As needed As needed As needed GIO070 R2 PWM3C EXTCLK As needed As needed As needed As needed
178. ion Driver jitter next transition 25 2 ns 6 tir sourcejpr Source Host Driver jitter paired transition 1 1 ns ti FUNC PT Function Driver jitter paired transition 10 1 ns 7 twEoPT Pulse duration EOP transmitter 1250 1500 160 175 ns 8 twEoPR Pulse duration EOP receiver 670 82 ns 9 tDRATE Data Rate 1 5 12 480 Mb s 10 Zprv Driver Output Resistance 28 49 5 40 5 49 5 Q 1 For more detailed specification information see the Universal Serial Bus Specification Revision 2 0 Chapter 7 Electrical 2 Low Speed C 200 pF Full Speed C 50 pF High Speed C 50 pF 3 tirim t t x 100 Excluding the first transaction from the Idle state 4 br tox 1 toxio Submit Documentation Feedback Peripheral Information and Electrical Specifications 127 MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 USB_DM aerch gt S L 90 Von pede 10 VoL A USB_DP ip a gt let t Figure 5 33 USB2 0 Integrated Transceiver Interface Timing Vss_USB_REF 10KQ241 Figure 5 34 USB Reference Resistor Routing 128 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 11 Universal Asynchronous Receiver Transmitter UART The contains 3 sep
179. ip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 39 ASP as SPI Timing Requirements CLKSTP 11b CLKXP 0 MASTER NO UNIT MIN MAX M39 tsu oRV CKXH Setup time DR valid before CLKX high 11 ns M40 thickxH DRV Hold time DR valid after CLKX high 1 ns Table 5 40 ASP as SPI Switching Characteristics CLKSTP 11b CLKXP 0 see Figure 5 43 MASTER NO PARAMETER UNIT MIN MAX M42 tc CKX Cycle time CLKX Be E ns M34 tackxL ExH Delay time CLKX low to FSX high C 2 C 3 ns M35 taexL ckxH Delay time FSX low to CLKX high T 2 T 2 ns M36 ta cKXL DXV Delay time CLKX low to DX valid 2 6 ns Disable time DX high impedance following last data bit from M37 tdis CKXL DXHZ CLKX low ae g 3 3 ns M38 taFxL pxv Delay time FSX low to DX valid D 2 D 10 ns 1 P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 2 T CLKX period 1 CLKGDV x P C CLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 x P when CLKGDV is even D CLKX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 x P when CLKGDV is even Use which ever value is greater 4 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output CLKXM FSXM 1 CLKRM FSRM 0 for master ASP 5 FSX should be low before the rising edge of clock to enable slave d
180. ite supply rail a 1 KQ resistor should be used Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 21 System Boot Terminal Functions continued TERMINAL TYPE OTHER DESCRIPTION NAME NO Async EMIF Address bus bit 08 EM A08 GIO GIO 062 GlO062 T19 O Z PD System AECFG 0 sets default for AECFG 0 VoD e PinMux2 EM_A0_BA1 AEMIF address width OneNAND or NAND e PinMux2 EM_A13_3 AEMIF address width OneNAND or NAND 2 4 16 Emulation The emulation interface allow software and hardware debugging Table 2 22 Emulation Terminal Functions TERMINAL i 5 TYPE OTHER 9 DESCRIPTION NAME NO TCK E10 Vpp JTAG test clock input TDI D9 l JTAG test data input DD TDO E9 O Vop JTAG test data output TMS D8 l u JTAG test mode select DD TRST c9 l SC JTAG test logic reset active low RTCK E11 O Vop JTAG test clock output PU JTAG emulation 0 UO EMUO E8 VO Z v EMU 1 0 00 Force Debug Scan chain ARM and ARM ETB TAPs connected DD EMU 1 0 11 Normal Scan chain ICEpick only PU JTAG emulation 1 UO EMU1 E7 VO Z V EMU 1 0 00 Force Debug Scan chain ARM and ARM ETB TAPs connected BD EMU 1 0 11 Normal Scan chain ICEpick only 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog sign
181. ition to endpoint 0 e FIFO RAM 4K endpoint Programmable FIFO size e Connects to a standard UTMI PHY with a 60 MHz 8 bit interface PRODUCT PREVIEW e Includes a DMA sub module that supports four TX and four RX channels of CPPI 3 0 DMAs e RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB e USB OTG extensions i e session request protocol SRP and host negotiation protocol HNP The USB2 0 peripheral does not support the following features e On chip charge pump e High bandwidth ISO mode is not supported triple buffering e 16 bit 30 MHz UTMI interface is not supported e RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes e Endpoint max USB packet sizes that do not conform to the USB 2 0 spec for FS LS 8 16 32 64 and 1023 are defined for HS 64 128 512 and 1024 are defined 5 10 1 USB2 0 Electrical Data Timing Table 5 25 Switching Characteristics Over Recommended Operating Conditions for USB2 0 see Figure 5 33 DM355 NO PARAMETER ae ae mera De UNIT MIN MAX MIN MAX MIN MAX 1 ty Rise time USB_DP and USB_DM signals 75 300 4 20 0 5 ns 3 tio Fall time USB_DP and USB_DM signals 75 300 4 20 0 5 ns 3 tem Rise Fall time matching 80 125 90 111 11 4 Vors Output signal cross over voltage 2 1 3 2 1 3 2 V D tr sourcenr Source Host Driver jitter next transition 2 2 ns tjr FUNC NT Funct
182. itmap and video windows Transparency support for the bitmap and video data when a bitmap pixel is zero there will be no Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 blending for that corresponding video pixel Ability to resize from VGA to NTSC PAL 640x480 to 720x576 for both the OSD and video windows Horizontal rescaling x1 5 is supported Support for a rectangular cursor window and a programmable background color selection The width height and color of the cursor is selectable The display priority is Rectangular Cursor gt OSDWIN1 gt OSDWINO gt VIDWIN1 gt VIDWINO gt background color Support for attenuation of the YCbCr values for the REC601 standard The following restrictions exist in the OSD module If the vertical resize filter is enabled for either of the video windows the maximum horizontal window dimension cannot be greater than 720 currently This is due to the limitation in the size of the line memory It is not possible to use both of the CLUT ROMs at the same time However a window can use RAM while another uses ROM 5 9 2 2 Video Encoder Digital LCD Controller VENC DLCD The VENC DLCD consists of three major blocks a the video encoder that generates analog video output b the digital LCD controller that generates digital R
183. loader for non AEMIF boot options e Embedded Trace Module and Embedded Trace Buffer ETM ETB e System Control Peripherals ARM Interrupt Controller PLL Controller Power and Sleep Controller System Control Module The ARM also manages controls all the device peripherals e DDR2 mDDR EMIF Controller e AEMIF Controller including the OneNAND and NAND flash interface e Enhanced DMA EDMA e UART e Timers e RealTime Out RTO e Pulse Width Modulator PWM e Inter IC Communication 12C e Multi Media Card Secure Digital MMC SD e Audio Serial Port ASP e Universal Serial Bus Controller USB e Serial Port Interface SPI e Video Processing Front End VPFE CCD Controller CCDC Submit Documentation Feedback Detailed Device Description 59 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 www ti com Image Pipe IPIPE H3A Engine Hardware engine for computing Auto focus Auto white balance and Auto exposure e Video Processing Back End VPBE On Screen Display OSD Video Encoder Engine VENC Figure 3 1 shows the functional block diagram of the DM355 ARM Subsystem yD oN yo Master IF Master IF ARM interrupt controller AINTC System control Power sleep controller PSC Peripherals DMA bus CFG bus Ka Ka Figure 3 1 DM355
184. me EM BA OI valid to R 6 tsu EMBAV EMOEL EM OE Ge BAIT RS E ns Output hold time EM_OE high to 7 th EMOEH EMBAIV EM_BATT0 invalid RH E ns Output setup time EM_A 13 0 valid to e 8 tsu EMBAV EMOEL EM OE gr Sale RS E ns Output hold time EM_OE high to 9 thEMOEH EMAIV EMATT3 0 invalid ane ps io hi EM OE active low width EW 0 RST E ns WEMOEL EM OE active low width EW 1 RST EWC 16 E ns 11 ta EMWAITH Delay time from EM_WAIT deasserted to 4E ns EMOEH EM_OE high READS OneNAND Synchronous Burst Read 32 fo EM_cLk Frequency EM_CLK 1 66 MH 33 te EM_cLk Cycle time EM_CLK 15 1000 ns 34 tsu EM_ADW Output setup time EM_ADV valid before 5 ER EM_CLKH EM_CLK high th EM_CLKH Output hold time EM_CLK high to EM_ADV 35 e 6 ns EM_ADVIV invalid 36 tsu EM_AV Output setup time EM_A 13 0 EM_BA 1 5 Ke EM_CLKH valid before EM_CLK high 37 th EM_CLKH Output hold time EM_CLK high to 6 ns EM_AIV EM_A 13 0 EM_BA 1 invalid 38 tw EM_CLKH Pulse duration EM_CLK high to Em_cLky 3 ns 39 tw EM_CLKL Pulse duration EM_CLK low to Em_cLky 3 ns WRITES EMIF write cycle time EW 0 WS WST WH E ns 15 t Kee EMIF write cycle time EW 1 eet EW ns C 16 E Output setup time EM_CE 1 0 low to sch EM_WE low SS 0 ONSTE ns a a Output setup time EM CEIT OT low to 0 fg EM_WE low SS 1 Output hold time EM_WE high to vl EM CE 10 high SS 0 BER DS n EMWEF EMCEH Output hold time EM_WE high
185. mma MHz programmable MHz fixed fixed ble bypass bypass bypass bypass 2 18 4 9 10 3 6 4 9 8 96 1 432 2 216 4 108 16 27 4 108 8 180 2 405 2 202 5 4 101 25 15 27 4 101 25 8 168 2 378 2 189 4 94 5 14 27 4 94 5 8 156 2 351 2 175 5 4 87 75 13 27 4 87 75 8 144 2 324 2 162 4 81 12 27 4 81 8 132 2 297 2 148 5 4 74 25 11 27 4 74 25 8 120 2 270 2 135 4 67 5 10 27 2 135 8 108 2 243 2 121 5 4 60 75 9 27 2 121 5 8 96 2 216 2 108 4 54 8 27 2 108 3 5 2 2 2 DM355 216 PLL2 36 MHz reference All supported clocking configurations for DM355 216 PLL2 with 36 MHz reference clock are shown in Table 3 5 Table 3 5 PLL2 Supported Clocking Configurations for DM355 216 36 MHz reference PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock n programmable m 1 fixed MHz PLLDIV1 SYSCLK1 DDR_CLK programmable 1 fixed MHz MHz bypass bypass bypass bypass 1 36 18 12 114 1 342 1 342 171 12 108 1 324 1 324 162 12 102 1 306 1 306 153 12 96 1 288 1 288 144 18 133 1 266 1 266 133 27 150 1 200 1 200 100 27 120 1 160 1 160 80 68 Detailed Device Description Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 3 5 3 Supported Clocking Configurations for DM355 270 This section describes the only supported device clocking configurations for DM355 2
186. n MXI1 CLKIN frequency is 24 MHz use P 41 6 ns Wes bw 2 PWMO 1 2 3 ZA A NO ed Figure 5 47 PWM Output Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 145 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 da TEXAS INSTRUMENTS www ti com VD CCDC L NN le 4 gt rue WEN VALID 4 A gt rou INVALID cc gt in j 4 gt VALID PWM2 INVALID 4 4 gt pws ma X VALID Figure 5 48 PWM Output Delay Timing 146 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 17 Real Time Out RTO The Real Time Out RTO peripheral supports the following features e Four separate outputs e Trigger on Timer3 event 5 17 1 RTO Electrical Timing Data Table 5 47 Switching Characteristics Over Recommended Operating Conditions for RTO Outputs see Figure 5 49 and Figure 5 50 DM355 NO PARAMETER UNIT MIN MAX 1 tw RTOH Pulse duration RTOx high P ns 2 tw RTOL Pulse duration RTOx low P ns 3 tyrTo Transition time RTOx AP ns 4 ta TIMER3 RTOV Delay time Timer 3 TINT12 or TINT34 trigger event to RTOx valid 10 ns ts k 2
187. nalog Front End AFE raw 13 YCC 16 bit time multiplexed GIO099 PD between chroma CB CR 05 YCC 08 bit which allows for 2 simultaneous SPI2 SDE M3 VO Z V decoder inputs it is time multiplexed between luma and chroma of the upper NALOT DD VIN channel Y CB CR 05 SPI SP12 Chip Select GIO GIO 99 CING Standard CCD Analog Front End AFE NOT USED YCC 16 bit time GIO100 PD multiplexed between chroma CB CR 06 YCC 08 bit which allows for 2 SPI2 SD K5 VO Z V simultaneous decoder inputs it is time multiplexed between luma and chroma of o EN the upper channel Y CB CR 06 SPI SPI2 Data Out GIO GIO 100 CIN7 Standard CCD Analog Front End AFE NOT USED YCC 16 bit time GIO101 PD multiplexed between chroma CB CR 07 YCC 08 bit which allows for 2 SPI2 SCL N3 VO Z V simultaneous decoder inputs it is time multiplexed between luma and chroma of kK SCH the upper channel Y CB CR 07 SPI SPI2 Clock GIO GIO 101 SPIO_SDI SPIO Data In GIO102 oe VO Z Von GIO GIO 102 SPIO_SDE A Ke SPIO Chip Select 0 EK B12 VO Z Von GIO GIO 103 Submit Documentation Feedback Device Overview 27 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 2 4 6 Multi Media Card Secure Digital MMC SD Interfaces The DM355 includes two Multi Media Card Secure Digital card interfaces that are compatible with the MMC SD and SDIO protocol Ta
188. ne function YOUT1 G6 A2 VO Z Vop vour Digital Video Out VENC settings determine function YOUT0 G5 B1 VO Z Vop vour Digital Video Out VENC settings determine function COUT7 G4 GIO081 C2 VO Z Vop vour Digital Video Out VENC settings determine function GIO GIO 081 PWMO PWMO COUT6 G3 GIO080 D2 VO Z Vpp_vout Digital Video Out VENC settings determine function GIO GIO 080 PWM1 PWM1 COUT5 G2 Ge c1 Volz Von vour Digital Video Out VENC settings determine function GIO GIO 079 PWM2A RTOO RTOO COUT4 B7 Ge D3 Volz Von vour Digital Video Out VENC settings determine function GIO GIO 078 PWM2B RTO1 RTO1 COUTS3 B6 So i E3 Volz Von vour Digital Video Out VENC settings determine function GIO GIO 077 PWM2C RTO2 RTO2 COUT2 B5 Ge E4 VO Z Von vour Digital Video Out VENC settings determine function GIO GIO 076 PWM2D RTO3 RTO3 COUT1 B4 Digital Video Out VENC settings determine function GIO075 F3 V O Z Vpp_vouT GIO GIO 075 PWM3A PWM3A COUTO B3 Digital Video Out VENC settings determine function Gl0074 F4 VO Z Vpp_vout GIO GIO 074 PWM3B PWM3B HSYNC F5 VOZ PD Video Encoder Horizontal Sync GI0073 Vop vour GIO GIO 073 VSYNC G5 Volz PD Video Encoder Vertical Sync GIlO072 Vpp_vouT GIO GIO 072 FIELD Video Encoder Field identifier for interlaced display formats GIO070 GIO GIO 070 R2 H4 ae Von vout Digital Video Out R2 PWM3C PWM3C EXTCLK Video Encoder External clock input used if clock rates
189. nput O Output Z High impedance S Supply voltage GND Ground A Analog signal Specifies the operating UO supply voltage for each signal See Section 5 3 Power Supplies for more detail PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 9 Asynchronous EMIF NAND OneNAND Terminal Functions continued TERMINAL TYPE OTHER 9 DESCRIPTION NAME NO EM_A06 Async EMIF Address bus bit 06 GIO060 nae ue Vos GIO GIO 60 EM_A05 Async EMIF Address bus bit 05 GIO059 Rig dee Vos GIO GIO 59 EM_A04 Async EMIF Address bus bit 04 GIO058 E ee Vos GIO GIO 58 EM_A03 Async EMIF Address bus bit 03 GIO057 N18 Oe Vos GIO GIO 57 Async EMIF Address bus bit 02 RES N15 1 O Z Von NAND SM xD CLE Command latch enable output Async EMIF Address bus bit 01 EM_A01 Nig WO Von NAND SM xD ALE Address latch enable output EM_A00 Async EMIF Address bus bit 00 GIO056 MiG ue Vos GIO GIO 56 Async EMIF Bank address 1 signal 16 bit address EM_BA1 e In 16 bit mode lowest address bit P19 VO Z V i GIO055 oR e In 8 bit mode second lowest address bit GIO GIO 055 Async EMIF Bank address 0 signal
190. nt 14 14 ta FXH DXV ONLY applies when in data ns delay 0 XDATDLY 00b mode FSX ext SS 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted 2 Minimum delay times also represent minimum output hold times 3 P 1 SYSCLK2 where SYSCLK2 is an output clock of PLLC1 see Section 3 5 4 Use which ever value is greater 5 Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 4P D2 8P 1 1 i aa CLKS a wm GE mem 7 _ ae 2 17 wa 3 3 CLKR me D e EE 9 e mm e A l 7 F Anuk FSR int EE 5 Taes FSR ext j 7 ele eg 8 DR Bit n 1 A m A m Xs E 2 17 ea E CLKX m CE een I a a Oe e E adk FSX int y 17 11 10 FSX ext NT FSX f DATDLY x 00b be gt le 44134 E eH Gd EC EIER GC GC A UNUS A Parameter No 13 applies to the first data bibnly when XDATDLY 0 Figure 5 41 ASP Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 139 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 37 ASP as SPI Timing Requirements CLKSTP 10b CLKXP 0 see Figure 5 42
191. o source code execution Submit Documentation Feedback TMS320DM355 Digital Media System on Chip DMSoC 3 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 1 3 Functional Block Diagram Figure 1 1 shows the functional block diagram of the DM355 device CCD CMOS Module CCDC IPIPE Buffer Logic Enhanced DMA 64 channels DDR2 MDDR 16 Composte video Digital RGB YUV USB2 0 PHY MPEG JPEG Coprocessor Speaker microphone Timer WDT x4 64 PWM x4 d J CLOCK ctrl PZ 64bit DMA Data Bus Peripherals 32bit Configuration Bus ee Figure 1 1 Functional Block Diagram 4 TMS320DM355 Digital Media System on Chip DMSoC Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS www ti com Contents TMS320DM355 Digital Media System on Chip DMSOC WE 1 TI Fee n ee EE NENNEN ENNEN RN ENEE REN NEEN EN e 1 1 3 Description nne EE ENEE EEN 3 1 3 Functional Block Diagram EE 4 Device Overview c2ccccceeeeeeeeeeseeeeeeeees 6 2 1 Device CharacteristicS 0sscseeeeeeeeeeeeeeeneeees 6 2 2 Memory Map SGummanm EE Z 23 Pin ASSIQNMENTS EE 9 2 4 Pin FUNCtIONS EE i3 Sege 36 2 6 Device Support EEN 55 Detailed Device Description 59 3 1 ARM Subsystem Overnlew EN 59 3 2 ARM926EJ S RISC CRU a
192. oint of view As with the selection of any component verification of capacitor availability over the product s production lifetime should be considered See also Section 5 5 1 and Section 5 5 2 for additional recommendations on power supplies for the oscillator PLL supplies Submit Documentation Feedback Peripheral Information and Electrical Specifications 97 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 d Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 SE 5 4 Reset 5 4 1 Reset Electrical Data Timing Table 5 2 Timing Requirements for Reset Il see Figure 5 4 DM355 NO UNIT MIN MAX tw RESET Active low width of the RESET pulse 12C ns tsu BOOT Setup time boot configuration pins valid before RESET rising edge 12C ns 3 thiBooT Hold time boot configuration pins valid after RESET rising edge 12C ns 1 BTSEL 1 0 and AECFG 4 0 are the boot configuration pins during device reset a 2 C MXI CLKIN cycle time in ns For example when MXI CLKIN frequency is 24 MHz use C 41 6 ns lt 4 1 gt i l l l l RESET o o l l 4 2 3 Boot Configuration Pins BTSEL 1 0 AECFG 3 0 Figure 5 4 Reset Timing 98 Peripheral Information and Electrical Specifications Submit Documentation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVI
193. on the USB connector When the USB is not used tie VBUS to Vss_USB Digital output to control external 5 V supply USB_DRVVBUS cS o z Von When USB is not used this signal should be left as a No Connect USB Ground Reference Vss_USB_REF C8 GND Von Connect directly to ground and to USB_R1 via 10K ohm 1 resistor placed as 7 close to the device as possible Analog 3 3 V power USBPHY VDDA33_USB ne GA Von When USB is not used this signal should be connected to Vsg_usp V B6 PWR Vv Common mode 3 3 V power for USB PHY PLL DDAS3_USB_PLL DD When USB is not used this signal should be connected to Vsg_usp Analog 1 3 V power for USB PHY VDDA13_USB g PAE Von When USB is not used this signal should be connected to Vsg_usp Digital 1 3 V power for USB PHY VDDD13_USB c6 PWR Von When USB is not used this signal should be connected to Vsg_usp 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 3 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 2 4 8 Audio Interfaces The DM355 includes two Audio Serial Ports ASP ports which are backward compatible with other TI ASP serial ports and provide DG audio interface One interface is multiplexed with GIO signals Table 2 14 ASP Terminal Functions TERMINAL a NAME NO TYPE
194. onous reads with continuous linear burst mode Does not support synchronous reads with wrap burst modes e Programmable cycle timings for each chip select in asynchronous mode Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 7 1 3 AEMIF Electrical Data Timing TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 13 Timing Requirements for Asynchronous Memory Cycles for AEMIF Module see Figure 5 14 and Figure 5 15 DM355 NO UNIT MIN Nom MAX READS and WRITES Pulse duration EM_WAIT assertion and 2 tw EM_WAIT deassertion 2E ns READS 12 tsu EMDV EMOEH Setup time EM_D 15 0 valid before EM_OE high ns 13 th EMOEH EMDIV Hold time EM DI 5 0 valid after EM_OE high ns 14 tsu EMOEL Delay time from EM_OE low to EM_WAIT 4E ag EMWAIT asserted READS OneNAND Synchronous Burst Read Setup time EM_D 15 0 valid before EM_CLK 30 tsu EMDV EMCLKH high H Dn 4 ns 31 th EMCLKH EMDIV Hold time EM DI 5 0 valid after EM_CLK high 4 ns WRITES 28 tsu EMWEL Delay time from EM_WE low to EM_WAIT Ap ns EMWAIT asserted 1 2 E PLLC1 SYSCLK2 period in ns SYSCLK2 is the EMIF peripheral clock SYSCLK2 is one fourth the PLLC output clock For example when PLLC output clock 432 MHz E 9 259 ns See Section 3 5 for more informa
195. ons shown as MIN MAX or NOM use the appropriate value specified in the recommended operating conditions table 2 These I O specifications apply to regular 3 3 V I Os and do not apply to DDR2 mDDR USB I Os DDR2 mDDR I Os are 1 8 V I Os and adhere to JESD79 2A standard USB I Os adhere to USB2 0 spec Submit Documentation Feedback Device Operating Conditions This specification applies only to pins with an internal pullup PU or pulldown PD See Section 2 4 or Section 2 5 for pin descriptions 4 To pull up a signal to the opposite supply rail a 1 KQ resistor is recommended 100 color bars are not supported 100 color bars require 1 2 V peak to peak The video buffer only provides 1 0 V peak to peak 93 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 Peripheral Information and Electrical Specifications 5 1 Parameter Information Device Specific Information Tester Pin Electronics Data Sheet Timing Reference Point 420 3 5 nH Output p28 Cem Oder Test Z0 500 E see note Device Pin Tx 4 0pF e 1 85 pF see note A The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect
196. ose to the device as possible Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 4 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Vou High level output voltage VDD MIN IOH MAX 2 4 V Output VoL Low level output voltage VDD MIN IOL MAX 0 6 Input current for I O without V VSS to VDD 4 A l internal pull up pull down We Input current for I O with internal huet pull up 3 V VSS to VDD 40 190 Current Input current for I O with internal Input Outp houso Lekt ease n V VSS to VDD 190 40 pA ut lou High level output current 100 lot Low level output current 4000 loz UO off state output current ores a or VSS internal pull 10 Capacitan Ci Input capacitance 4 oF ce Co Output capacitance 4 Resolution Resolution 10 Bits INL Integral non linearity best fit aa 499 ee VIQEO bufer 1 LSB DAC 8 DNL Differential non linearity E 492 9r Neo Durrer 0 5 LSB Compliance Output compliance range IFS 1 4 mA RLOAD 499 Q 0 0 700 V Output high voltage top of 75 Video VoH VIDBUF NTSC or PAL colorbar Je y Buffer Outpupt low voltage bottom of VoL vIDBUF Ge tip ge 0 470 1 For test conditi
197. ositive Edge Clocking Ke Jf Y ff NL vu P 13 g 16 EE CCD 13 0 r ha 24 ZE Figure 5 25 VPFE CCD Master Mode Input Data Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 119 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 www ti com Table 5 20 Switching Characteristics Over Recommended Operating Conditions for VPFE CCD Master Mode see Figure 5 26 DM355 NO PARAMETER UNIT MIN MAX 18 ta PCLKL HDIV Delay time PCLK edge to HD invalid 3 11 ns 20 ta PCLKL VDIV Delay time PCLK edge to VD invalid 3 11 ns PCLK Negative Edge coking ef N Z Nn fY Wwe Positive Edge Clocking _ _ 184 e OX gt 7 gt gt k 20 y DD C a EE EE Figure 5 26 VPFE CCD Master Mode Control Output Data Timing 5 9 2 Video Processing Back End VPBE The Video Processing Back End of VPBE module is comprised of the On Screen Display OSD module and the Video Encoder Digital LCD Controller VENC DLCD 5 9 2 1 On Screen Display OSD The primary function of the OSD module is to gather and blend video data and display bitmap data and then pass it to the Video Encoder VENC in YCbCr format The video and display data is read from external DDR2 mDDR memory The OSD is programmed via control and parameter registers
198. ould be connected to Vss Video DAC External resistor 2550 Ohms to GND connection for current bias IBIAS F2 A WOLZ configuration When the DAC is not used the IBIAS signal should be connected to Vss VFB G1 AVolz Video DAC Pre video buffer DAC output 1000 Ohms to IOUT 1070 Ohms to TVOUT When the DAC is not used the VFB signal should be connected to Vss Video DAC Analog Composite NTSC PAL output SeeFigure 5 31 andFigure 5 32 for TVOUT F1 A VO Z V circuit connection When the DAC is not used the TVOUT signal should be left as a No Connect or connected to Vss Video DAC Analog 1 8V power When the DAC is not used the Vppa1s_pac signal Vopaus Dag S PWR should be connected to Vss Video DAC Analog 1 8V ground When the DAC is not used the Vssa_pac signal Vssa_pac L8 GND should be connected to Vss 1 I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 2 PD pull down PU pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 2 4 3 Asynchronous External Memory Interface AEMIF The Asynchronous External Memory Interface AEMIF signals support AEMIF NAND and OneNAND Table 2 9 Asynchronous EMIF NAND OneNAND Terminal Functions TERMINAL 9 ous TYPE OTHER DESCRIPTION NAME NO EM A13 Async EMIF Add
199. our software programmable timers Timer 0 Timer 1 and Timer 3 general purpose timers can be programmed in 64 bit mode dual 32 bit unchained mode or dual 32 bit chained mode Timer 3 supports additional features over the other timers external clock event input period reload output event tied to Real Time Out RTO module external event capture and timer counter register read reset Timer 2 is used only as a watchdog timer Timer 2 is tied to device reset 64 bit count up counter Timer modes 64 bit general purpose timer mode Timer 0 1 3 Dual 32 bit general purpose timer mode Timer 0 1 3 Watchdog timer mode Timer 2 Two possible clock sources Internal clock External clock event input via timer input pins Timer 3 Three possible operation modes One time operation timer runs for one period then stops Continuous operation timer automatically resets after each period Continuous operation with period reload Timer 3 Generates interrupts to the ARM CPU Generates sync event to EDMA Generates output event to device reset Timer 2 Generates output event to Real Timer Out RTO module Timer 3 External event capture via timer input pins Timer 3 For more detailed information see the TMS320DM355 DMSoC 64 bit Timer User s Guide for more information SPRUEES5 5 15 1 Timer Electrical Data Timing Table 5 45 Timing Requirements for Timer Input see Figure 5 46 N
200. out L DDR Address Bus bit 04 DDR_A03 W3 VO DDR Vop opp out L DDR Address Bus bit 03 DDR_A02 W2 UO DDR VDD_DDR out L DDR Address Bus bit 02 DDR_A01 V3 VO DDR Vop opp out L DDR Address Bus bit 01 DDR AO0 V2 VO DDR Vpp_ppR out L DDR Address Bus bit 00 DDR_DQ15 W17 I O DDR VDD_DDR in DDR Data Bus bit 15 DDR_DQ14 V16 UO DDR VDD_DDR in DDR Data Bus bit 14 DDR_DQ13 W16 I O DDR VDD_DDR in DDR Data Bus bit 13 DDR_DQ12 U16 UO DDR VDD_DDR in DDR Data Bus bit 12 DDR_DQ11 W15 I O DDR VDD_DDR in DDR Data Bus bit 11 DDR_DQ10 W14 I O DDR VDD_DDR in DDR Data Bus bit 10 DDR_DQ09 V14 UO DDR VDD_DDR in DDR Data Bus bit 09 DDR_DQ08 U13 UO DDR VDD_DDR in DDR Data Bus bit 08 DDR_DQ07 W13 I O DDR VDD_DDR in DDR Data Bus bit 07 DDR_DQ06 V13 UO DDR VDD_DDR in DDR Data Bus bit 06 DDR_DQ05 W12 I O DDR VDD_DDR in DDR Data Bus bit 05 DDR_DQ04 U12 UO DDR VDD_DDR in DDR Data Bus bit 04 DDR_DQ03 T11 UO DDR VDD_DDR in DDR Data Bus bit 03 DDR_DQ02 U11 UO DDR VDD_DDR in DDR Data Bus bit 02 DDR_DQ01 W11 UO DDR VDD_DDR in DDR Data Bus bit 01 DDR_DQ00 V11 UO DDR VDD_DDR in DDR Data Bus bit 00 DDR_GATEO W18 I O DDR VDD_DDR DDR Loopback signal for external DQS gating Route to DDR and back to DDR_STRBEN_DEL with same constraints as used for DDR clock and data DDR_GATE1 V17 UO DDR VDD_DDR DDR Loopback signal for external DQS gating Route to DDR and back to DDR_STRBEN with same constraints as used for
201. owered A Fast mode C bus device can be used in a Standard mode C bus system but the requirement tsu SDA SCLH 2 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tp max tsuspa scLH 1000 250 1250 ns according to the Standard mode I C Bus Specification before the SCL line is released A device must internally provide a hold time of at least 300 ns for the SDA signal referred to the ViHmin of the SCL signal to bridge the undefined region of the falling edge of SCL Submit Documentation Feedback Ak u oH _ Za le KH 8 Weg 6 gt Ke 14 4 10 gt gt es 4 ge so TITY ONL RO Hy ie EE A es Ss gt d 1 gt ba k 12 Ily e 3 b 3 e Stop Start Repeated Start The maximum buspa sc has only to be met if the device does not stretch the low period twsgcL of the SCL signal Cp total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed SE bk k Figure 5 39 DC Receive Timings Peripheral Information and Electrical Specifications ege Stop 135 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEM
202. pedance S Supply voltage GND Ground A Analog signal 2 PD internal pull down PU internal pull up To pull up a signal to the opposite supply rail a 1 KQ resistor should be used 3 Specifies the operating I O supply voltage for each signal See Section 5 3 Power Supplies for more detail 14 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 5 CCD Conitroller Video Input Terminal Functions continued TERMINAL 1 as NANE NO TYPE OTHER DESCRIPTION Standard CCD Analog Front End AFE Raw 05 YIN5 PD e YCC 16 bit Time multiplexed between chroma Y 05 Glo091 Ms WO Von VIN e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 05 GIO GIO 091 Standard CCD Analog Front End AFE Raw 04 YIN4 PD e YCC 16 bit Time multiplexed between chroma Y 04 GIO090 P3 VO Z Von YIN e YCC 8 bit which allows for two simultaneous decoder inputs it is time gt multiplexed between luma and chroma of the upper channel Y CB CR 04 GIO GIO 090 Standard CCD Analog Front End AFE Raw 03 YIN3 PD e YCC 16 bit Time multiplexed between chroma Y 03 Gloos9 R3 VOlZ Von vum e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiple
203. pts e Configurable interrupt priority 2 levels of FIQ and 6 levels of IRQ e Configurable interrupt entry table FIQ and IRQ priority table entry to reduce interrupt processing time The ARM core supports two interrupt types FIQ and IRQ See the ARM926EU S Technical Reference Manual for detailed information about the ARM s FIQ and IRQ interrupts Each interrupt channel is mappable to an FIQ or to an IRQ type of interrupt and each channel can be enabled or disabled The INTC supports user configurable interrupt priority and interrupt entry addresses Entry addresses minimize the time spent jumping to interrupt service routines ISRs When an interrupt occurs the corresponding highest priority ISR s address is stored in the INTC s ENTRY register The IRQ or FIQ interrupt routine can read the ENTRY register and jump to the corresponding ISR directly Thus the ARM does not require a software dispatcher to determine the asserted interrupt 3 4 1 Interrupt Mapping The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the ARM Each interrupt is also assigned one of 8 priority levels 2 for FIQ 6 for IRQ For interrupts with the same priority level the priority is determined by the hardware interrupt number the lowest number has the highest priority Table 3 1 shows the connection of device interrupts to the ARM Table 3 1 AINTC Interrupt Connections Interrupt
204. r 1 3 V CVpp K12 PWR Core power 1 3 V CVpp L11 PWR Core power 1 3 V CVpp L12 PWR Core power 1 3 V CVpp N6 PWR Core power 1 3 V CVpp R7 PWR Core power 1 3 V 52 Device Overview Submit Documentation Feedback d TEXAS TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 23 DM355 Pin Descriptions continued Name BGA Type Group Power PU Reset Description Mux Control ID 1 Supply PD State CVpp R8 PWR Core power 1 3 V CVpp T17 PWR Core power 1 3 V CVpp W19 PWR Core power 1 3 V Von F9 PWR Power for Digital IO 3 3 V Von F10 PWR Power for Digital IO 3 3 V Von F11 PWR Power for Digital IO 3 3 V Von Fi2 PWR Power for Digital IO 3 3 V Von Fi3 PWR Power for Digital IO 3 3 V Von F14 PWR Power for Digital IO 3 3 V Von G8 PWP Power for Digital IO 3 3 V Von G14 PWR Power for Digital IO 3 3 V Von K8 PWR Power for Digital IO 3 3 V Von K15 PWR Power for Digital IO 3 3 V Von L6 PWP Power for Digital IO 3 3 V Von L13 PWR Power for Digital IO 3 3 V Von M10 PWR Power for Digital IO 3 3 V Von M11 PWR Power for Digital IO 3 3 V Von M12 PWR Power for Digital IO
205. ram control is given to UBL GIO61 is driven high e g LED on DM355 Timer0 shall be used to accurately toggle GIO61 at 4Hz and 2Hz ARM ROM Boot NAND Mode No support for a full firmware boot Instead copies a second stage user boot loader UBL from NAND flash to ARM internal RAM AIM and transfers control to the user defined UBL Support for NAND with page sizes up to 2048 bytes Support for magic number error detection and retry up to 24 times when loading UBL Support for up to 30KB UBL 32KB IRAM 2KB for RBL stack Optional user selectable support for use of DMA and I cache during RBL execution i e while loading UBL Supports booting from 8 bit NAND devices 16 bit NAND devices are not supported Supports 4 bit ECC 1 bit ECC is not supported Supports NAND flash that requires chip select to stay low during the tR read time Supports Fast Boot option which allows you to quickly boot and recover from a low power mode ARM ROM Boot MMC SD Mode No support for a full firmware boot Instead copies a second stage Uwer Boot Loader UBL from MMC SD to ARm Internal RAM AIM and transfers control to the user software Support for MMC SD Native protocol MMC SD SPI protocol is not supported Support for descriptor error detection and retry up to 24 times when loading UBL Support for up to 30KB UBL 32KB 2KB for RBL stack 84 Detailed Device Description Submit Documen
206. ransmit Event or Timer 2 interrupt TINT4 Event 9 ASPI peo ee ASP1 Receive Event or Timer 2 interrupt TINT5 Event 10 SPI2 SPI2XEVT SPI2 Transmit Event 11 SPI2 SPIZREVT SPI2 Receive Event 12 Reserved 13 Reserved 14 SPI1 SPI1XEVT SPI1 Transmit Event 15 SPI1 SPI1REVT SPI1 Receive Event 16 SPIO SPIOXEVT SPOI Transmit Event 17 SPIO SPIOREVT SPIO Receive Event 18 UARTO URXEVTO UART 0 Receive Event 19 UARTO UTXEVTO UART 0 Transmit Event 20 UART1 URXEVT1 UART 1 Receive Event 1 In addition to the events shown in this table each of the 64 channels can also be synchronized with the transfer completion or intermediate transfer completion events For more detailed information on EDMA event transfer chaining see the Document Support section for the Enhanced Direct Memory Access EDMA Controller Reference Guide 2 The total number of EDMA events in DM355 exceeds 64 which is the maximum value of the EDMA module Therefore several events are multiplexed and you must use the register EDMA_EVTMU2xX in the System Control Module to select the event source for multiplexed events Refer to the ARM Subsystem Guide for more information on the System Control Module register EDMA_EVTMUX Submit Documentation Feedback Detailed Device Description 89 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table
207. re USB Digital 0 0 0 V Vssa PU Supply ground PLL1 0 0 0 V Vssa_PLL2 Supply ground PLL2 0 0 0 V Vss usB Supply ground USB 0 0 0 V Supply Ground Vssa_DLL Supply ground DLL 0 0 0 V Vssa_DAC Supply ground DAC Analog 0 0 0 V Ve vi MXI1 osc ground 0 0 ol v Vss_mx2 MXI2 osc ground 0 0 ol v Voltage Input High Vin High level input voltage 2 V Voltage Input Low Vu Low level input voltage 0 8 v VREF DAC reference voltage 450 mV DACH Reias DAC full scale current adjust resistor 2550 Q Doan Output resistor 499 Q Cgc Bypass capacitor 0 1 uF Beate GC co ROUT between TVOUT and 1070 S Video Buffer Rep Feedback resistor between VFB and IOUT pins 1000 Reias DAC full scale current adjust resistor 2550 Q Cgc Bypass capacitor 0 1 yA USB USB_VBUS USB external charge pump input 4 85 5 5 25 V R1 USB reference resistor 9 9 10 10 1 kQ Temperature Te Operating case temperature rage 0 85 C 1 Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground see Section 5 5 1 2 These I O specifications apply to regular 3 3 V I Os and do not apply to DDR2 mDDR USB I Os DDR2 mDDR I Os are 1 8 V I Os and adhere to JESD79 2A standard USB I Os adhere to USB2 0 spec 92 Device Operating Conditions See Section 5 9 2 4 Also resistors should be E 96 spec line 3 digits with 1 accuracy 4 Connect USB_R1 to Vos usp rer via 10K ohm 1 resistor placed as cl
208. reof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and s
209. ress bus bit 13 GIO067 v19 Oz PD GIO GIO 67 DD on BTSEL 1 V System BTSEL 1 0 sampled at power on reset to determine boot method Used to drive boot status LED signal active low in ROM boot modes EM_A12 PD Async EMIF Address bus bit 12 GIO066 U19 V O Z V GIO GIO 66 BTSEL 0 DD System BTSEL 1 0 sampled at power on reset to determine boot method EM A11 Async EMIF Address bus bit 11 GO SIP Ger ge E led AECFG configuration AECFG 3 AECFG 3 DD 3 sample at power on reset to configuration AE 3 sets default for PinMux2_EM_D15_8 AEMIF default bus width 16 or 8 bits Async EMIF Address bus bit 10 EM_A10 PU GIO GIO 64 GlO064 R18 VO Z V AECFG 3 0 sampled at power on reset to AECFG configuration AECFG 2 1 AECFG 2 DO sets default for PinMux2_EM_BAO AEMIF EM BAO definition EM_BAO EM_A14 GIO 054 rsvd Async EMIF Address bus bit 09 EM_A09 PD GIO GIO 63 GIO063 P17 VO Z V AECFG 3 0 sampled at power on reset to AECFG configuration AECFG 2 1 AECFG 1 DD sets default for PinMux2_EM_BAO AEMIF EM_BAO definition EM_BAO EM_A14 GIO 054 rsvd Async EMIF Address bus bit 08 EM A08 GIO GIO 62 GlO062 T19 VO Z PD AECFG 0 sets default for AECFG 0 Von e PinMux2_EM_A0O_BA1 AEMIF address width OQneNAND or NAND e PinMux2_EM_A13_3 AEMIF address width OneNAND or NAND EM_A07 Async EMIF Address bus bit 07 GIO061 Pig Vog VoD GIO GIO 61 UN 18 Device Overview l I
210. ring channel chaining auto reloading and memory protection The EDMA Channel Controller has the following features e Fully orthogonal transfer description Three transfer dimensions A synchronized transfers one dimension serviced per event AB synchronized transfers two dimensions serviced per event Independent indexes on source and destination Chaining feature allows 3 D transfer based on single event e Flexible transfer definition Increment and constant addressing modes Linking mechanism allows automatic PaRAM set update Chaining allows multiple transfers to execute with one event e Interrupt generation for DMA completion Error conditions e Debug visibility Queue watermarking threshold Error and status recording to facilitate debug e 64 DMA channels Event synchronization Manual synchronization CPU s write to event set register Chain synchronization completion of one transfer chains to next e 8 QDMA channels QDMA channels are triggered automatically upon writing to a PaRAM set entry Support for programmable QDMA channel to PARAM mapping e 128 PaRAM sets Each PaRAM set can be used for a DMA channel QDMA channel or link set remaining e Two transfer controllers event queues The system level priority of these queues is user programmable e 16 event entries per event queue e External events for example ASP TX Evt and RX Evt The EDMA Transfer Controller has the
211. rovides an interface between the DMSoC and other devices compliant with the DC bus specification and connected by way of an 2C bus External components attached to this 2 wire serial bus can transmit and receive up to 8 bit wide data to and from the DMSoC through the DC peripheral This document assumes the reader is familiar with the DC bus specification TMS320DM35x DMSoC Multimedia Card MMC Secure Digital SD Card Controller Reference Guide This document describes the multimedia card MMC secure digital SD card controller in the TMS320DM35x Digital Media System on Chip DMSoC The MMC SD card is used in a number of applications to provide removable data storage The MMC SD controller provides an interface to external MMC and SD cards The communication between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol TMS320DM35x DMSoC Enhanced Direct Memory Access EDMA Controller Reference Guide This document describes the operation of the enhanced direct memory access EDMA3 controller in the TMS320DM35x Digital Media System on Chip DMSoC The EDMA controller s primary purpose is to service user programmed data transfers between two memory mapped slave endpoints on the DMSoC TMS320DM35x DMSoC 64 bit Timer Reference Guide This document describes the operation of the software programmable 64 bit timers in the TMS320DM35x Digital Media System on Chip DMSoC Timer 0 Timer 1 and Timer 3 are used as general purpose
212. s OneNAND Flash Read Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 111 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 7 2 DDR2 Memory Controller The DDR2 mDDR Memory Controller is a dedicated interface to DDR2 mDDR SDRAM It supports JESD79D 2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices DDR2 mDDR SDRAM plays a key role in a DM355 based system Such a system is expected to require a significant amount of high speed external memory for all of the following functions www ti com Buffering of input image data from sensors or video sources Intermediate buffering for processing resizing of image data in the VPFE Numerous OSD display buffers Intermediate buffering for large raw Bayer data image files while performing image processing functions Buffering for intermediate data while performing video encode and decode functions Storage of executable code for the ARM The DDR2 mDDR Memory Controller supports the following features JESD79D 2A standard compliant DDR2 SDRAM Mobile DDR SDRAM 256 MByte memory space Data bus width 16 bits CAS latencies DDR2 2 3 4 and5 mDDR 2 and3 Internal banks DDR2 1 2 4 and 8 mDDR 1 2 and 4 Burst length 8 Burst type sequential 1 CS signal Page sizes 256 512 1024 and
213. sistor should be used 22 Device Overview Submit Documentation Feedback d Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 2 11 GPIO Terminal Functions continued TERMINAL i om NANE N TYPE OTHER DESCRIPTION MMCSD1 _DATA1 MMCSD1 DATA1 GIO020 B15 VO Z Von GIO GIO 020 UART2_R UART2 Receive Data XD MMCSD1 _DATA2 MMCSD1 DATA2 Gloo21 A16 V O Z Von GIO GIO 021 UART2_C UART2 CTS TS MMCSD1 _DATAS3 MMCSD1 DATA3 GIO022 B16 VO Z Von GIO GIO 022 UART2_R UART2 RTS TS Ze fe God J MMCSD1 Command Glo023 DD GIO GIO 023 MMCSD1 f _CLK C15 O Z Man GE Clock GIO024 SR E F16 VO Z V ASPO Receive Frame Synch Glo025 po GIO GIO 025 CR F17 VO Z V ASPO Receive Clock Glo026 pe GIO GIO 026 ASPO_DR ASPO Receive Data GIO027 E18 vOIZ Von GIO GIO 027 EC G17 Vu v ASPO Transmit Frame Synch Gl0028 DD GIO GIO 028 E F18 VO Z V ASPO Transmit Clock G10029 pe GIO GIO 029 ASPO_DX ASPO Transmit Data GIO030 S dee Vos GIO GIO 030 EM_CLK P P G10031 E19 VO Z Von OneNAND Clock signal for OneNAND flash interface GIO GIO 031 EM_ADV H16 VO Z PD OneNAND Address Valid Detect for OneNAND interface GIO032 Von GIO GIO 032 EM_WAIT G18 VOlz PU Async EMIF Async WAIT NAND SM xD RDY _BSY input GIO033 Von GIO GIO 033 EM OE Async EMIF Output Enable
214. ss VCLK FIELD LCD_OE Vss VpDA13_USB NC VDDA _PLL2 G VFB Vss EXTCLK VSYNC CVpp Vop Vss F TVOUT IBIAS COUT1 COUTO HSYNC Vpp_vouT VDD_VOUT VDD_vouT Von E IOUT Vss COUT3 COUT2 USB_VBUS Vss_USB EMU1 EMUO TDO D Vss COUT6 COUT4 USB_ID Vss_USB TMS TDI C COUT5 COUT7 YOUT7 CVpp mee VDDD13_USB USB_R1 Vss_USB_REF TRST B YOUTO YOUT3 YOUT4 YOUT5 Vss Krees Vss_USB Vss MXO1 A CVpp YOUT1 YOUT2 YOUT6 Vss USB_DM USB_DP Vss MXI1 4 2 3 4 5 6 S 8 9 Figure 2 1 Pin Map Quadrant A Submit Documentation Feedback Device Overview 9 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 da TEXAS Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 1 2 3 4 5 6 ri 8 9 W Vss DDR_A02 DDR_A03 DDR AO DDR AO DDR_A09 DDR_A11 DDR_CLK DDR_CLK v Vss DDR_A00 DDR_A01 DDR_A04 DDR_A07 DDR_A10 DDR_A12 DDR_BA 2 DDR CAS U Vss Vss Vss Vss DDR_A06 DDR_A13 DDR_BA 1 DDR_BA 0 Vss T MXO2 Vss PCLK Vss DDR RAS DDR CS DDR_ZN R MXI2 Vss YIN3 CAM_VD CAM_WEN_ Vss CVpp CVpp Von opp FIELD P Vss_mx2 YIN1 YIN4 YIN2 YINO VDD_VIN VDD _VIN VDD_VIN VDD_DDR N Vss RSV05 CIN7 CAM_HD CVpp Vss Vss M RSV04 RSV06 CIN5 YING YINS Vss Vss Vss VDD_DDR L RSV03 Vss CIN1 CIN4 YIN7 Vop VpDA18V_DAC Vss_DAC Vss K RSV02 RSV07 Vss CIN6 CVpp Von Vss 10 Device Overview Figure 2 2 Pin Map Quadrant B Submit Documentation Feedback d TEXAS TMS320DM355
215. t Gamma is implemented using a piece wise linear interpolation approach with a 512 entry look up table for each color The RGB2YCbCr conversion module applies 3x3 matrix transformation to the RGB data to convert it to YCbCr data This module also implements offset The 4 2 2 conversion module applies the chroma low pass filter and down samples Cb and Cr so that IPIPE output data is in YCbCr 4 2 2 format The 2D edge enhancer module improves image clarity with luminance non linear filter This module also has contrast and brightness adjustment functions The chroma suppression module reduces faulty color using luminance Y value or high pass filtering Y value The H resizer and V resizer modules resize horizontal and vertical image sizes respectively The output interface module transfers data from IPIPE to SDRAM in the form of YCbCr 422 or RGB 32bit 1 6bit The histogram function can record histograms of up to 4 distinct areas into up to 256 bins IPIPE has three different processing paths Case 1 The CCD raw data directly leads to IPIPE and stores the YCbCr or RGB data to SDRAM Case 2 IPIPE reads CCD raw data and stores the Bayer pattern data after white balance to SDRAM Case 3 IPIPE reads YCbCr 422 data and apply edge enhance chroma suppression and Resize to output YCbCr or RGB data to SDRAM Peripheral Information and Electrical Specifications Submit Documentation Feedback R3 Texas TMS320DM355 INSTRUME
216. tal ground Vss L2 GND Digital ground Vss L9 GND Digital ground Vss L10 GND Digital ground Vss L14 GND Digital ground Vss M6 GND Digital ground Vss M7 GND Digital ground Vss M8 GND Digital ground Vss M14 GND Digital ground Vss M17 GND Digital ground Vss N1 GND Digital ground Vss N8 GND Digital ground Vss N9 GND Digital ground Vss N14 GND Digital ground Vss R2 GND Digital ground Vss R6 GND Digital ground Vss T2 GND Digital ground Vss T5 GND Digital ground Vss T15 GND Digital ground Vss U1 GND Digital ground Vss US GND Digital ground Vss U3 GND Digital ground Vss U4 GND Digital ground Vss u9 GND Digital ground Vss U14 GND Digital ground Vss U17 GND Digital ground Vss Vi GND Digital ground Vss V18 GND Digital ground Vss WI GND Digital ground 54 Device Overview Submit Documentation Feedback 43 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 2 6 Device Support 2 6 1 Development Tools TI offers an extensive line of development tools for DM355 systems including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE The
217. tation Feedback 3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 e ARM ROM Boot UART mode No support for a full firmware boot Instead loads a second stage user boot loader UBL via UART to ARM internal RAM AIM and transfers control to the user software Support for up to 30KB UBL 32KB 2KB for RBL stack The general boot sequence is shown in Figure 3 6 For more information refer to the ARM Subsystem User s Guide Internal ROM lt I Boot from Boot from NAND flash UART Boot from Yes Yes MMC SD N Boot OK Yes Invoke Invoke loaded OneNAND Program Figure 3 6 Boot Mode Functional Block Diagram 3 13 Power Management The is designed for minimal power consumption There are two components to power consumption active power and leakage power Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required timeline or to run at a clock setting until the work is complete and then drastically cut the clocks e g to PLL Bypass mode until additional work must be performed Leakage power is due Submit Documentation Feedback Detailed Device Description 85 PRODUCT
218. the GPIO register through the internal bus k ng i EXT_INTx f Figure 5 13 GPIO External Interrupt Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 105 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 7 External Memory Interface EMIF 5 7 1 www ti com supports several memory and external device interfaces including e Asynchronous EMIF AEMIF for interfacing to SRAM e OneNAND flash memories e NAND flash memories Asynchronous EMIF AEMIF The EMIF supports the following features e SRAM etc on up to 2 asynchronous chip selects addressable up to 64KB each e Supports 8 bit or 16 bit data bus widths e Programmable asynchronous cycle timings e Supports extended wait mode e Supports Select Strobe mode 5 7 1 1 NAND NAND SmartMedia xD The NAND features of the EMIF are as follows e NAND flash on up to 2 asynchronous chip selects e 8 and 16 bit data bus widths e Programmable cycle timings e Performs 1 bit and 4 bit ECC calculation e NAND Mode also supports SmartMedia SSFDC Solid State Floppy Disk Controller and xD memory cards 5 7 1 2 OneNAND 106 The OneNAND features supported are as follows e NAND flash on up to 2 asynchronous chip selects e Only 16 bit data bus widths e Supports asynchronous writes and reads e Supports synchr
219. the pin mux registers 3 10 Device Reset There are five types of reset in DM355 The types of reset differ by how they are initiated and or by their effect on the chip Each type is briefly described in Table 3 14 and further described in the ARM Subsystem Guide Table 3 14 Reset Types Type Initiator Effect POR Power On Reset RESET pin low and TRST low Total reset of the chip cold reset Resets all modules including memory and emulation Warm Reset RESET pin low and TRST high initiated by ARM Resets all modules including memory except ARM emulator emulation Max Reset ARM emulator or Watchdog Timer WDT Same effect as warm reset System Reset ARM emulator Resets all modules except memory and ARM emulation It is a soft reset that maintains memory contents and does not affect or reset clocks or power states Submit Documentation Feedback Detailed Device Description 79 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 14 Reset Types continued Type Initiator Effect Module Reset ARM software Resets a specific module Allows the ARM to independently reset any module Module reset is intended as a debug tool not as a tool to use in production 3 11 Default Device Configurations After POR warm reset and max reset
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221. tings As a good board design practice such delays must always be taken into account Timing values may be adjusted by increasing decreasing such delays TI recommends utilizing the available I O buffer information specification IBIS models to analyze the timing characteristics correctly To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 If needed external logic hardware such as buffers may be used to compensate any timing differences Submit Documentation Feedback Peripheral Information and Electrical Specifications 95 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 Digital Media System on Chip DMSoC SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 5 2 Recommended Clock and Control Signal Transition Behavior da TEXAS INSTRUMENTS www ti com All clocks and control signals should transition between Vu and Mu or between Vu and Mul in a monotonic manner 5 3 Power Supplies The power supplies of DM355 are summarized in Table 5 1 Table 5 1 Power Supplies Customer Tolerance Package Chip Plane Description Comments Board Plane Name Supply 1 3 V 5 1 3 V CVpp Core Vpp Vopa PLL PLL1 Vppa Vppa_PLL2 PLL2 Vppa Vppp13_USB USB 1 3 V supply Vppa13_USB USB 1 3 V supply 3 3 V
222. tion Setup before end of STROBE phase if no extended wait states are inserted by which EM_WAIT must be asserted to add extended wait states Figure 5 16 and Figure 5 17 describe EMIF transactions that include extended wait states inserted during the STROBE phase However cycles inserted as part of this extended wait period should not be counted the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles Table 5 14 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module see Figure 5 14 and Figure 5 15 DM355 UNI NO PARAMETER MIN Nom MAX T READS and WRITES 1 tatuRNAROUND Turn around time TA E ns READS EMIF read cycle time EW 0 RS RST RH E ns 3 jt i EMEC YLE EMIF read cycle time EW 1 SERTE E ns Output setup time EM_CE T 0 low to RS E m gc EM_OE low SS 0 SUEMCEL EMOEL Output setup time EM_CE 1 0 low to 0 EM_OE low SS 1 Output hold time EM_OE high to e mae EM CRT OT high SS 0 ee de N EMOEFPEMCEH Output hold time EM_OE high to 0 Ge EM_CE T 0 high SS 1 1 TA Turn around RS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold MEWC Maximum external wait cycles These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers
223. ts for JTAG Test Port see Figure 5 51 NO DM355 UNIT MIN MAX 1 Lack Cycle time TCK 20 ns 2 tw TCKH Pulse duration TCK high 8 ns 3 tw TCKL Pulse duration TCK low 8 ns 4 tsu TDIV RTCKH Setup time TDI valid before RTCK high 10 ns 5 th RTCKH TDIIV Hold time TDI valid after RTCK high 9 ns 6 tsu TMSV RTCKH Setup time TMS valid before RTCK high 2 ns 7 th RTCKH TMSIV Hold time TMS valid after RTCK high 5 ns R 1 e le 2 me 3 TCK N oK RTK S N AE A moD S O S YO wn BN 4 gt toil FX gt H 7 eg ts D Figure 5 51 JTAG Input Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 149 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 K Texas Digital Media System on Chip DMSoC INSTRUMENTS www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 5 49 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port see Figure 5 51 NO PARAMETER ee UNIT MIN MAX 8 teRTCK Cycle time RTCK 20 ns 9 tw RTCKH Pulse duration RTCK high 10 10 tw RTCKL Pulse duration RTCK low 10 11 tal JTAG outputs Rise time all JTAG outputs 1 3 ns 12 tall JTAG outputs Fall time all JTAG outputs 1 3 ns 13 tyrtcKt toow Delay time TCK low to TDO valid 0 aa ns 3 je 9 We 10 Ve ege Too LF Figure 5 52 J
224. us set of status and control registers accessible by the ARM and supporting all of the following system features and operations e Device identification e Device configuration Pin multiplexing control Device boot configuration status e ARM interrupt and EDMA event multiplexing control e Special peripheral status and control Timer64 USB PHY control VPSS clock and video DAC control and status DDR VTP control Clockout circuitry GIO de bounce control Submit Documentation Feedback Detailed Device Description 77 PRODUCT PREVIEW MalAddd LONGOUd TMS320DM355 43 Texas Digital Media System on Chip DMSoC INST MENTS SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 e Power management Deep sleep and fast NAND boot control e Bandwidth Management Bus master DMA priority control For more information on the System Control Module refer to the ARM Subsystem User s Guide 3 9 Pin Multiplexing The DM355 makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package In order to accomplish this pin multiplexing is controlled using a combination of hardware configuration at device reset and software control No attempt is made by the DM355 hardware to ensure that the proper pin muxing has been selected for the peripherals or interface mode being used thus proper pin muxing configuration is the responsibility of the board and software design
225. used to represent the ALE and CLE signals for the NAND Flash mode of the AEMIF and are always enabled Note that EM_A 0 does not represent the lowest AEMIF address bit DM355 supports only 16 bit and 8 bit data widths for the AEMIF In 16 bit mode EM_BA 1 represents the LS address bit the half word address and EM_BAJ 0 represents the MS address bit A 14 In 8 bit mode EM_BA 1 0 represent the 2 LS address bits Note that additional selections are available by programming the PinMux2 register in software after boot Note that AECFG selection of 0010 selects OneNAND interface The AEMIF needs to operate in the half rate mode full_rate 0 to meet frequency requirements Software should not change the PINMUX2 register setting to affect the AEMIF rate operation A soft reset of the AEMIF should be performed any time a rate change is made Detailed Device Description Submit Documentation Feedback R3 Texas TMS320DM355 INSTRUMENTS Digital Media System on Chip DMSoC www ti com SPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Table 3 13 AECFG Async EMIF Configuration Pin Mux Coding 1101 NAND 1100 1010 OneNAND 1000 8 bit SRAM 0010 16 bit SRAM 0000 GPIO 54 GPIO 54 EM_A 14 EM BA EM_A 14 EM Bai GPIO 55 EM_BA 1 EM BAD EM BAD EM BAD EM BAD GPIO 56 EM_A 0 EM_A 0 EM_A 0 EM Ai EM Ai EM An EM An EM An EM An EM An EM An EM AIS EM AIS EM AIS EM
226. xed between luma and chroma of the upper channel Y CB CR 03 GIO GIO 089 Standard CCD Analog Front End AFE Raw 02 YIN2 PD e YCC 16 bit Time multiplexed between chroma Y 02 GIO088 P4 O Z Von vum e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 02 GIO GIO 088 Standard CCD Analog Front End AFE Raw 01 YIN1 PD e YCC 16 bit Time multiplexed between chroma Y 01 GlO087 P2 O Z VOO vm e YCC 8 bit which allows for two simultaneous decoder inputs it is time multiplexed between luma and chroma of the upper channel Y CB CR 01 GIO GIO 087 Standard CCD Analog Front End AFE Raw 00 YINO PD e YCC 16 bit Time multiplexed between chroma Y 00 GIO086 P5 VO Z Von vum e YCC 8 bit which allows for two simultaneous decoder inputs it is time S multiplexed between luma and chroma of the upper channel Y CB CR 00 GIO GIO 086 CAM HD PD Horizontal synchronization signal that can be either an input slave mode or an GIO085 N5 VO Z V output master mode Tells the CCDC when a new line starts DONIN GIO GIO 085 CAM VD PD Vertical synchronization signal that can be either an input slave mode or an output Glo084 R4 VO Z V master mode Tells the CCDC when a new frame starts EEN GIO GIO 084 Write enable input signal is used by external device AFE TG to gate the DDR CAM WEN output of the CCDC module Alternately the field identification

Texas Instruments TMS320DM355 User's Manual

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