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Texas Instruments TMS320C6722 User's Manual

1. gt CA dep ed 1 6 8 10 12 14 16 Bottom View 2 02 0 67 0 55 Ted Seating Plone AA A 0 70 0 40 4205478 4 11 07 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA 5 256 PLASTIC BALL GRID ARRAY gt TYP gt gt 00 4 S PE a 0 50 4 J H 14 1
2. Al Corn Sy B PO AONO cem D S 5 5 7 9 1 3 5 2 o 1C 12 14 JJ e gt 5 D PI ane R EE A CFE NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package D This is a lead free solder ball design 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all
3. BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4100 0000 PLLPID PLL controller peripheral identification register 0x4100 0100 PLLCSR PLL control status register 0x4100 0110 PLLM PLL multiplier control register 0x4100 0114 PLLDIVO PLL controller divider register 0 0x4100 0118 PLLDIV1 PLL controller divider register 1 0x4100 011C PLLDIV2 PLL controller divider register 2 0x4100 0120 PLLDIV3 PLL controller divider register 3 0x4100 0138 PLLCMD PLL controller command register 0x4100 013C PLLSTAT PLL controller status register 0x4100 0140 ALNCTL PLL controller clock align control register 0x4100 0148 CKEN Clock enable control register 0x4100 014C CKSTAT Clock status register 0x4100 0150 SYSTAT SYSCLK status register 104 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 5 Application Example Figure 5 1 illustrates a high level block diagram of the device and other devices to which it may typically connect See Section 1 2 for an overview of each major block DSP Audio Zone 1 CODEC DIR ADC DAC DSD SPI or 2 Network Control optional 2 0 Audio Zone 2 Audio Zone 3 CODEC DIR ADC DAC DSD Network McASP1 12C1 Crossbar Switch Digital Out Memory Controller
4. 17 50 Gage Plane 20 20 S 19 80 E 22 20 2180 50 Pin 1 Index Area Seating Plane Ls 0 08 4152725 B 04 05 A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion N This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature SLMAO02 for information regarding recommended board layout This document is available at www ti com http www ti com E Falls within JEDEC 5 026 PowerPAD is a trademark of Texas Instruments 3 TEXAS INSTRUMENTS www ti com 1 TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 4 May 2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TMX320C6722RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6726RFP OBSOLETE HTQFP RFP 144 TBD Call TI Call TI TMX320C6727GDH OBSOLETE BGA GDH 256 TBD Call TI Call TI TMX320C6727ZDH OBSOLETE BGA ZDH 256 TBD Call TI Call TI The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period
5. PULL GPIO DESCRIPTION Universal Host Port Interface UHPI Data and Control UHPI HD O0 E K13 IO IPD Y UHPI HD 1 K14 IO IPD Y UHPI HD 2 M14 IO IPD Y UHPI_HD 3 L13 IO IPD Y UHPI HD 4 3 L14 IO IPD Y UHPI HD 5 N13 IO IPD Y UHPI HD 6 N14 IO IPD Y UHPI HD 7 14 IO IPD Y UHPI Data Bus Lower 16 Bits UHPI HD 8 14 IO IPD Y UHPI HD 9 F14 IO IPD Y UHPI HD 10 F13 IO IPD Y UHPI_HD 11 G14 IO IPD Y UHPI HD 12 5 G13 IO IPD Y UHPI_HD 13 14 IO IPD Y UHPI HD 14 H13 IO IPD Y UHPI HD 15 J13 IO IPD Y UHPI HD 16 HHWIL E H1 IPD Y UHPI HD 17 G3 IO IPD Y UHPI HD 18 G4 IO IPD Y UHPI_HD 19 IO IPD Y UHPI_HD 20 F4 IO IPD Y Data Bus Upper 16 Bits 1O in the following UHPI_HD 21 E3 IO IPD Y modes UHPI HD 22 D3 lo IPD Y e Fullword Multiplexed Address and Data e Fullword Non Multiplexed UHPI_HD 23 C3 IO IPD Y UHPI_HD 25 2 lO IPD Y e Half word Multiplexed Address and Data UHPI HD 26 N3 lO IPD Y In this mode UHPI_HHWIL indicates whether the high or UHPI HD 27 M3 IO IPD Y low half word is being addressed UHPI_HD 28 L3 IO IPD Y UHPI_HD 29 14 IO IPD Y UHPI HD 30 L2 IO IPD Y UHPI_HD 31 H4 IO IPD Y Universal Host Port Interface UHPI Control UHPI HBET O C6 IPD Y Byte Enable for UHPI HD 7 0 HBE 1 C5 IPD Y UHPI Byte Enable for UHPI HD 15
6. 107 7 1 Package Thermal Resistance Characteristics 107 7 2 Supplementary Information About the 144 Pin RFP PowerPAD 108 7 3 Packaging Information 109 Submit Documentation Feedback TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 ki TEXAS INSTRUMENTS www ti com 2 Device Overview 2 1 Device Characteristics Table 2 1 provides an overview of the C672x DSPs The table shows significant features of each device including the capacity of on chip memory the peripherals the execution time and the package type with pin count Table 2 1 Characteristics of the C672x Processors HARDWARE FEATURES C6727 C6726 C6722 dMAX 1 Peripherals EMIF 1 32 bit 1 16 bit 1 16 bit 1 0 0 ot all peripheral pins are available at the same time McASP 3 McASP2 DIT only 2 For more details see the SPI 2 Device Configurations section 2C 2 RTI 1 32KB Program Cache 32KB Program Cache 32KB Program Cache On Chip Memory Size KB 256KB RAM 256KB RAM 128KB RAM 384KB ROM 384KB ROM 384KB ROM Control Status Register CPU ID CPU Rev ID CSR 81 16 0x0300 Frequency MHz 300 250 250 225 250 225 200 3 3 ns C6727 300 4 ns C6722 250 Cycle Time ns 4 ns C6727A 2
7. Peripheral Interrupt and DMA Events A UHPI is available only on the C6727 McASP2 is not available on the C6722 Figure 1 1 C672x DSP Block Diagram Submit Documentation Feedback TMS320C6727 TMS320C6726 TMS320C6722 DSPs 5 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 1 TMS320C6727 TMS320C6726 TMS320C6722 1 1 FOQtUuireS en 1 0 ihn mites emen 1 2 1 Device Compatibility 1 3 Functional Block Diagram 2 Device 2 1 Device 2 2 Enhanced C67x 2 3 CPU Interrupt Assignments eese 2 4 Internal Program Data ROM and RAM 2 5 Program 2 6 High Performance Crossbar Switch 2 7 Memory Map Summary 2 8 29 Pin Assignments 19 2 10 3 Device 3 1 Device Configuration Registers 3 2 Peripheral Pin Multiplexing Options 3 3 Peripher
8. 30 Device Configurations Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 3 3 lists the options for configuring the SPI1 McASPO and McASP1 pins Note that there are additional finer grain options when selecting which McASP controls the particular AXR serial data pins but these options are not listed here and can be made on a pin by pin basis Table 3 3 Options for Configuring 5 1 McASPO and McASP1 Data Pins CONFIGURATION OPTION 1 OPTION 2 OPTION 3 OPTION 4 OPTION 5 PERIPHERAL 5 pin mode 4 pin mode 4 pin mode 3 pin mode disabled McASPO 11 12 12 13 16 max data pins McASP1 4 4 4 4 6 max data pins PINS AXRO 5 SPI1_SCS SPH SCS AXRO 5 AXRO 5 AXRO 5 SPH SCS AXRO 6 SPI1 ENA AXRO 6 SPI1 ENA AXRO 6 AXRO 6 SPH ENA AXRO 7 SPI1_CLK SPH SPH AXRO 7 SPH AXRO S AXR1 5 SPI1_SOMI SPI1_SOMI SPI1_SOMI SPI1_SOMI AXRO 8 or AXR1 5 SPI1_SOMI AXRO S AXR1 4 SPI1_SIMO SPI1_SIMO SPI1_SIMO SPI1_SIMO AXRO 9 or AXR1 4 SPI1_SIMO Table 3 4 lists the options for configuring the shared EMIF and UHPI pins Table 3 4 Options for Configuring EMIF and UHPI C6727 Only CONFIGURATION OPTION 1 OPTION 2 PERIPHERAL UHPI Multiplexed Address Dat
9. Transfer Entry 0 Transfer Entry Transfer Entry k Control Transfer Entry 7 R W Low Priority PARAM Event Entry 0 Event Entry Event Entry k Table LoMAX TA E E 31 RW x vent Entry Reserved Transfer Entry 0 Transfer Entry k Transfer Entry 7 dMAX HiMAX MAXO High Priority REQ Low Priority REQ Figure 4 4 dMAX Controller Block Diagram 40 Peripheral and Electrical Specifications TEXAS INSTRUMENTS www ti com HiMAX Master Crossbar Switch Port Interrupt Lines to the CPU Events LoMAX Master gt Crossbar Switch Port Submit Documentation Feedback X9 Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 The dMAX controller comprises e Event and interrupt processing registers e Event encoder e High priority event Parameter RAM PaRAM e Low priority event Parameter RAM PaRAM e Address generation hardware for High Priority Events MAXO HiMAX e Address generation hardware for Low Priority Events MAX1 LoMAX The TMS320C672x Peripheral Bus Structure can be described logically as a Crossbar Switch with five master ports and five slave ports When accessing the slave ports the module is always given the highest priority followed by the MAX1 LoMAX module In other words in case several mast
10. UHPI HDS 2 UHPI HDS 1 UHPI HCS UHPI HRDY AMUTE2 HINT A External Host MCU RDY INTERRUPT Byte Enables active during reads and writes Some processors support a byte enable mode on their write enable A be used as EM_D 31 16 B Optional for hosts supporting multiplexed address and data Pull up if not used Low when address is on the bus C Two host address lines or host GPIO if address lines are not available D pins E Only required if needed for strobe timing Not required if CS meets strobe timing requirements Figure 4 16 UHPI Multiplexed Host Address Data Fullword Mode Submit Documentation Feedback Peripheral and Electrical Specifications 57 TMS320C6727 TMS320C6726 TMS320C6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 ui Figure 4 17 illustrates the Non Multiplexed Host Address Data Fullword mode of the UHPI In this mode the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI HRDY signal This mode allows the host to randomly access a 64K byte page in the C672x address space The upper 32 bits of the C672x address are set by the DSP only through the CFGHPIAMSB and CFGHPIAUNB registers see Table 4 13 and Table 4 14 DSP External Host MCU EM D 31 16 UHPI HA 15 0 lt UHPI HCNTI 1 0 UHPI HD 15 0 lt UHPI_HD 16 HHWIL lt UHPI
11. The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 but may be started individually and may have different prescaler settings The counters provide the timebase against which four output comparators operate These comparators may be programmed to generate periodic interrupts The comparators include an adder which automatically updates the compare value after each periodic interrupt This means that the DSP only needs to initialize the comparator once with the interrupt period The two input captures be triggered from any of the McASP1 or McASP2 DMA events device configuration register which selects the McASP events to measure is defined in Table 4 37 Measuring the time difference between these events provides an accurate measure of the sample rates at which the McASPs are transmitting and receiving This measurement can be useful as a hardware assist for a software asynchronous sample rate converter algorithm Submit Documentation Feedback Peripheral and Electrical Specifications 97 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 www ti com The digital watchdog is disabled by default Once enabled a sequence of two 16 bit key values OxE51A followed by OxA35C in two separate writes must be continually written to the key register before the watchdog counter counts
12. Pin Direction Register Pin Data In Register I2CPDIR I2CPDIN Figure 4 37 I2C Module Block Diagram Submit Documentation Feedback I2CPDSET I2CPDCLR Register Pin Data Set Register Pin Data Clear Register Peripheral and Electrical Specifications 93 TMS320C6727 TMS320C6726 5320 6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 15 2 12 Peripheral Registers Description s Table 4 33 is a list of the I2C registers TEXAS INSTRUMENTS www ti com Table 4 33 I2Cx Configuration Registers Len REGISTER DESCRIPTION 0x4900 0000 0x4A00 0000 I2COAR Own Address Register 0x4900 0004 0x4A00 0004 I2CIER Interrupt Enable Register 0x4900 0008 0x4A00 0008 I2CSTR Interrupt Status Register 0x4900 000C 0x4A00 000C I2CCLKL Clock Low Time Divider Register 0x4900 0010 0x4A00 0010 I2CCLKH Clock High Time Divider Register 0x4900 0014 0x4A00 0014 I2CCNT Data Count Register 0x4900 0018 0 4 00 0018 I2CDRR Data Receive Register 0x4900 001C 0x4A00 001C I2CSAR Slave Address Register 0x4900 0020 0x4A00 0020 I2CDXR Data Transmit Register 0x4900 0024 0x4A00 0024 I2CMDR Mode Register 0x4900 0028 0x4A00 0028 I2CISR Interrupt Source Register 0x4900 002C 0x4A00 002C 12 Extended Mode Register 0x4900 0030 0x4A00 0030 I2CPSC Prescale Register 0x490
13. Read data Band C ead data 17 gt Hot Write k 4 4 7 34 UHPI HRDY A Depending on the type of write or read operation HPID or HPIC transitions on UHPI HRDY may or may not occur Figure 4 21 Non Multiplexed Read Write Timings 64 Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 UHPI HCS UHPI HAS lt gt 12 eo OX C LX OC 49 12 4 12 e gt 11 vein M O 4 12 e gt 12 e 11 verw EN NCC 4 5 10 4 4 10 gt 9 4 9 37 l 13 4 13 397 5 3 14 gt 5 NL X 7 1 9 3 lt gt 2 2 gt 4 0 36 le 6 OT 38 UHPI HRDY A See Figure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on may or not occur Figure 4 22 Multiplexed Read Timings Using UHPI HAS Submit Documentation Feedback Peripheral and Electrical Specifications 65 TMS320C6727 TMS320C6726 TMS320C6722 49 Texas Floating Point Digital Sign
14. osc TDM Port 6 Independent Audio Zones 3 TX 3 RX 16 Serial Data Pins FLASH High Speed Parallel Data DSP Control SPI or 2 Host 100 MHz SDRAM Microprocessor A only available on the C6727 McASP2 is not available on the C6722 Figure 5 1 TMS320C672x Audio DSP System Diagram Submit Documentation Feedback Application Example 105 TMS320C6727 TMS320C6726 5320 6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS268D device specific data sheet to make it an SPRS268E revision Scope Corrected addresses of the XGBLCTL register in Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus ADDS CHANGES DELETES Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus e Corrected addresses of XGBLCTL Transmitter Global Control Register 106 Revision History Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 7 Mechanical Data 7 1 Package Thermal Resistance Characteristics Table 7 1 and Table 7 2 provide the thermal characteristics for the recommended package types used on the TMS320C672x DSP Table
15. 5 119 UHPI_HCS UHPI_HRDY AMUTE2 HINT A INTERRUPT be used as D 31 16 Optional for hosts supporting multiplexed address and data Pull up if not used Low when address is on the bus DSP byte enables UHPI HBE 3 2 are not required in this mode Two host address lines or host GPIO if address lines are not available A 1 assuming this address increments from 0 to 1 between two successive 16 bit accesses Byte Enables active during reads and writes Some processors support a byte enable mode on their write enable pins G Only required if needed for strobe timing Not required if CS meets strobe timing requirements Tie UHPI HDS 2 and HDS 1 opposite For more information see Figure 4 14 Figure 4 15 UHPI Multiplexed Host Address Data Half Word Mode Peripheral and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 16 illustrates the Multiplexed Host Address Data Fullword Mode hookup between the C672x DSP and an external host microcontroller In this mode all 32 bits of UHPI HD 31 0 are used and the host can access HPIA HPID and HPIC in a single bus cycle DSP EM D 31 16 UHPI HA 15 0 UHPI_HCNTL 1 0 UHPI_HD 15 0 UHPI_HD 16 HHWIL UHPI_HD 31 17 UHPI UHPI HBE 3 0
16. Figure 4 6 C6727 DSP 32 Bit EMIF Example Submit Documentation Feedback Peripheral and Electrical Specifications 47 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 TEXAS INSTRUMENTS www ti com 4 11 2 EMIF Peripheral Registers Description s Table 4 4 is a list of the EMIF registers For more information about these registers see the TMS320C672x DSP External Memory Interface EMIF User s Guide literature number SPRU711 Table 4 4 EMIF Registers BYTE ADDRESS REGISTER NAME DESCRIPTION 0 000 0004 AWCCR Asynchronous Wait Cycle Configuration Register 0 000 0008 SDCR SDRAM Configuration Register OxF000 000C SDRCR SDRAM Refresh Control Register 0 000 0010 A1CR Asynchronous 1 Configuration Register OxF000 0020 SDTIMR SDRAM Timing Register OxF000 003C SDSRETR SDRAM Self Refresh Exit Timing Register OxF000 0040 EIRR EMIF Interrupt Raw Register OxF000 0044 EIMR EMIF Interrupt Mask Register 0 000 0048 EIMSR EMIF Interrupt Mask Set Register OxF000 004C EIMCR EMIF Interrupt Mask Clear Register OxF000 0060 NANDFCR NAND Flash Control Register OxF000 0064 NANDFSR NAND Flash Status Register OxF000 0070 NANDF1ECC NAND Flash 1 ECC Register 48 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Poin
17. www ti com 4 14 1 SPI Device Specific Information 80 Figure 4 31 is a block diagram of the SPI module which is a simple shift register and buffer plus control logic Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission The SPI can operate either as a master in which case it initiates a transfer and drives the SPIx CLK pin or as a slave Four clock phase and polarity options are supported as well as many data formatting options SPIx SIMO SPix_SOMI Peripheral Configuration Bus 16 Bit Shift Register SPIx ENA Interrupt and 4 16 Bit Buffer DMA Requests 3 16 Bit Emulation Buffer C672x SPI Module Figure 4 31 Block Diagram of SPI Module The SPI supports 3 4 and 5 pin operation with three basic pins SPIx SPIx_SIMO and SPIx SOMI and two optional pins 5 SCS SPIx The optional SPIx SCS Slave Chip Select pin is most useful to enable in slave mode when there are other slave devices on the same SPI port The C672x will only shift data and drive the SPIx_SOMI pin when SPIx SCS is held low In slave mode SPIx ENA is an optional output and can be driven in either a push pull or open drain manner The SPIx ENA output provides the status of the internal transmit buffer SPIDATO 1 registers In four pin mode with the enable option SPIx ENA is asserted only when the transmit buffer is full indicating that the
18. 1 Phase 0 5 5 50 6 from SPIx_CLK rising 0 515 Polarity 1 Phase 1 0 from SPIx CLK rising Max delay for slave SPI to drive SPIx ENA valid 21 tuscsL_ENAL M after master asserts SPIx_SCS to delay the 0 5 ns master from beginning the next transfer Polarity 0 Phase 0 to SPIx rising Er 2 2 Polarity 0 Phase 1 Delay from SPIX_SCS CLK rising O Stcspc u 2P 10 22 t active to first ns SPIx CLK 7 8 Q Polarity 1 Phase 0 2P 10 to SPIx falling Polarity 1 Phase 1 _ to SPlx falling 0 5tespoym 2 10 Polarity 0 Phase 0 to SPIx CLK rising M Polarity 0 Phase 1 Delay from assertion of to CLK rising 0 5tspcym 15 23 la ENA SPC M SPIx ENA low to first JG ns SPIx_CLK edge 1 Polarity 1 Phase 0 15 e to SPIx falling Polarity 1 Phase 1 to falling O Stcspcju 15 1 These parameters are in addition to the general timings for SPI master modes Table 4 25 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four master clocking modes 4 In the case where the master SPI is ready with new data before SPIx deassertion b Except for modes when SPIDAT1 CSHOLD is enabled and there is additional data to transmit In this case SPIx SCS will remain asserted 6 This delay can be increased under software cont
19. Copyright 2005 2007 Texas Instruments Incorporated 5320 6727 TMS320C6726 TMS320C6722 R3 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 uk 1 2 Description The TMS320C672x is the next generation of Texas Instruments C67x generation of high performance 32 64 bit floating point digital signal processors The TMS320C672x includes the TMS320C6727 TMS320C6726 and TMS320C6722 devices Enhanced C67x4 CPU The C67x4 CPU is an enhanced version of the C67x CPU used on the C671x DSPs It is compatible with the C67x CPU but offers significant improvements in speed code density and floating point performance per clock cycle At 300 MHz the CPU is capable of a maximum performance of 2400 MIPS 1800 MFLOPS by executing up to eight instructions six of which are floating point instructions in parallel each cycle The CPU natively supports 32 bit fixed point 32 bit single precision floating point and 64 bit double precision floating point arithmetic Efficient Memory System The memory controller maps the large on chip 256K byte RAM and 384K byte ROM as unified program data memory Development is simplified since there is no fixed division between program and data memory size as on some other devices The memory controller supports single cycle data accesses from the C67x CPU to the RAM and ROM Up to three parallel accesses to the internal RAM and ROM from three of the following f
20. MAY 2005 REVISED JANUARY 2007 4 17 1 Clock Electrical Data Timing Table 4 39 assumes testing over recommended operating conditions Table 4 39 CLKIN Timing Requirements NO MIN MAX UNIT 1 Tega Oscillator frequency range OSCIN OSCOUT 12 25 MHz 2 c CLKIN Cycle time external clock driven on CLKIN 20 ns 3 tw CLKINH Pulse width CLKIN high O 4tc CLKIN ns 4 tw CLKINL Pulse width CLKIN low 0 4 ns 5 tyCLKIN Transition time CLKIN 5 ns 6 fei Frequency range of PLL input 12 50 MHz Submit Documentation Feedback Peripheral and Electrical Specifications 101 TMS320C6727 TMS320C6726 5320 6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 www ti com 4 18 Phase Locked Loop PLL 4 18 1 PLL Device Specific Information 102 The C672x DSP generates the high frequency internal clocks it requires through an on chip PLL The input to the PLL is either from the on chip oscillator OSCIN pin or from an external clock on the CLKIN pin The PLL outputs four clocks that have programmable divider options Figure 4 43 illustrates the PLL Topology The PLL is disabled by default after a device reset It must be configured by software according to the allowable operating conditions listed in Table 4 40 before enabling the DSP to run from the PLL by setting PLLEN 1 PLLEN PLL CSR O Clock Divid Input
21. REVISED JANUARY 2007 Table 4 11 UHPI Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION Device Level Configuration Registers Controlling UHPI 0x4000 0008 CFGHPI UHPI Configuration Register 0x4000 000C CFGHPIAMSB Most Significant Byte of UHPI Address 0x4000 0010 CFGHPIAUMB Upper Middle Byte of UHPI Address UHPI Internal Registers 0x4300 0000 PID Peripheral ID Register 0x4300 0004 PWREMU Power and Emulation Management Register 0x4300 0008 GPIOINT General Purpose I O Interrupt Control Register 0x4300 000C GPIOEN General Purpose I O Enable Register 0x4300 0010 GPIODIR1 General Purpose I O Direction Register 1 0x4300 0014 GPIODAT1 General Purpose I O Data Register 1 0x4300 0018 GPIODIR2 General Purpose I O Direction Register 2 0x4300 001C GPIODAT2 General Purpose I O Data Register 2 0x4300 0020 GPIODIR3 General Purpose Direction Register 0x4300 0024 GPIODAT3 General Purpose I O Data Register 3 0x4300 0028 Reserved Reserved 0x4300 002C Reserved Reserved 0x4300 0030 HPIC Control Register 0x4300 0034 HPIAW Write Address Register 0x4300 0038 HPIAR Read Address Register 0x4300 003C Reserved Reserved 0x4300 0040 Reserved Reserved Submit Documentation Feedback Peripheral and Electrical Specifications 59 5320 6727 TMS320C6726 TMS320C6722 R3 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY
22. SPRS268E MAY 2005 REVISED JANUARY 2007 Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used 1 device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example GDH the temperature range for example A is the extended temperature range and the device speed range in megahertz for example 300 is 300 MHz Figure 2 10 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member The ZDH package like the GDH package is a 256 ball plastic BGA but Green For device part numbers and further ordering information for TMS320C672x in the GDH ZDH and RFP package types see the Texas Instruments website at http Awww ti com or contact your TI sales representative TMS 320 C6727 GDH A 250 PREFIX DEVICE SPEED RANGE TMX Experimental device 300 300 MHz CPU Prototype device 250 250 MHz CPU TMS Qualified device 225 225 MHz CPU 200 200 MHz CPU TEMPERATURE RANGE DEFAULT 0 C TO 90 C t Blank 0 C to 90 C commercial temperature A 40 C to 105 C extended temperature DEVICE FAMILY 320 TMS320 DSP family PACKAGE TYPE S GD
23. 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 10 g 1609116 10 AHCLKR X Falling Edge Polarity UUU UUU UUU UUU UUU AHCLKR X Rising Edge Polarity le 12 lesa 4 AFSR X Bit Width 0 Bit Delay N i N AFSR X Bit Width 1 Bit Delay AFSR X Bit Width 2 Bit Delay t E _ AFSR X Slot Width 0 Bit Delay M AFSR X Slot Width 1 Bit Delay AFSR X Slot Width 2 Bit Delay 14 gt I AXR n Data Out Transmit XX AO 1 A30 A31 BO B1 B30 B31 C1 C2 C31 A For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in B For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in Figure 4 30 McASP Output Timings Submit Documentation Feedback Peripheral and Electrical Specifications 79 TMS320C6727 TMS320C6726 TMS320C6722 R3 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 4 14 Serial Peripheral Interface Ports SPIO SPI1
24. 4 6 INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 9 2 dMAX Peripheral Registers Description s Table 4 3 is a list of the dMAX registers Table 4 3 dMAX Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION 0x6000 0008 DEPR Event Polarity Register 0x6000 000C DEER Event Enable Register 0x6000 0010 DEDR Event Disable Register 0x6000 0014 DEHPR Event High priority Register 0x6000 0018 DELPR Event Low priority Register 0x6000 001C DEFR Event Flag Register 0x6000 0034 DERO Event Register 0 0x6000 0054 DER1 Event Register 1 0x6000 0074 DER2 Event Register 2 0x6000 0094 DER3 Event Register 3 0x6000 0040 DFSRO FIFO Status Register 0 0x6000 0060 DFSR1 FIFO Status Register 1 0x6000 0080 DTCRO Transfer Complete Register 0 0x6000 00A0 DTCR1 Transfer Complete Register 1 N A DETR Event Trigger Register Located in C67x DSP Register File N A DESR Event Status Register Located in C67x DSP Register File Submit Documentation Feedback Peripheral and Electrical Specifications 43 TMS320C6727 TMS320C6726 TMS320C6722 R3 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 www ti com 4 10 External Interrupts 44 The C672x DSP has no dedicated general purpose interrupt
25. 6722 4 Peripheral and Electrical Specifications 4 1 Electrical Specifications Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320C672x DSP All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified 4 2 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted UNIT Supply voltage range CVpp OSCVpp 9 0 3 to 1 8 V Supply voltage range DVpp PLLHV 0 3 to 4 V Input Voltage Range All pins except OSCIN 0 3 to DVpp 0 5 V OSCIN pin 0 3 to CVpp 0 5 Output Voltage Range All pins except OSCOUT 0 3 to DVpp 0 5 V OSCOUT pin 0 3 to CVpp 0 5 Clamp Current 20 mA Operating case temperature range Tc Default 0 to 90 A version 40 to 105 Storage temperature range 65 to 150 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 externally All voltage values are
26. MAY 2005 REVISED JANUARY 2007 4 9 Dual Data Movement Accelerator dMAX 4 9 1 dMAX Device Specific Information The dMAX is a module designed to perform Data Movement Acceleration The dMAX controller handles user programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSP The dMAX allows movement of data to from any addressable memory space including internal memory peripherals and external memory The dMAX controller in the C672x DSP has a different architecture from the previous EDMA controller in the C621x C671x devices The dMAX controller includes features such as capability to perform three dimensional data transfers for advanced data sorting capability to manage a section of the memory as a circular buffer FIFO with delay tap based reading and writing data The dMAX controller is capable of concurrently processing two transfer requests provided that they are to from different source destinations Figure 4 4 shows a block diagram of the dMAX controller Submit Documentation Feedback Peripheral and Electrical Specifications 39 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 To From Crossbar Switch High Priority PARAM Event Entry 0 Event Event Entry k Entry Table HiMAX RAM RW Event Entry 31 Reserved
27. Read returns Pin data input register PDSET writes Writes affect Pin data set register alternate write address PDOUT 0x4400 0020 0x4500 0020 0x4600 0020 PDCLR Pin data clear register alternate write address PDOUT 0x4400 0044 0x4500 0044 0x4600 0044 GBLCTL Global control register 0x4400 0048 0x4500 0048 0x4600 0048 AMUTE Audio mute control register 0x4400 004C 0x4500 004C 0 4600 004 DLBCTL Digital loopback control register 0x4400 0050 0x4500 0050 0 4600 0050 DITCTL DIT mode control register 0x4400 0060 0x4500 0060 0x4600 0060 RGBLCTL Receiver global control register Alias of GBLCTL only receive bits are affected allows receiver to be reset independently from transmitter 0x4400 0064 0x4500 0064 0x4600 0064 RMASK Receive format unit bit mask register 0x4400 0068 0x4500 0068 0x4600 0068 RFMT Receive bit stream format register 0x4400 006C 0x4500 006C 0x4600 006C AFSRCTL Receive frame sync control register 0x4400 0070 0x4500 0070 0x4600 0070 ACLKRCTL Receive clock control register 0x4400 0074 0x4500 0074 0 4600 0074 AHCLKRCTL Receive high frequency clock control register 0x4400 0078 0x4500 0078 0x4600 0078 RTDM Receive TDM time slot 0 31 register 0x4400 007C 0x4500 007C 0x4600 007 RINTCTL Receiver interrupt control register 0 4400 0080 0x4500 0080 0x4600 0080 RSTAT Receiver status register 0x4400 0084 0x4500 00
28. from falling 1 P SYSCLK2 period 2 First bit may be MSB or LSB depending upon SPI configuration MO 0 refers to first bit and MO n refers to last bit output on SPIx SIMO MI 0 refers to the first bit input and Ml n refers to the last bit input on SPIx SOMI 3 The final data bit will be held on the SPIx SIMO pin until the SPIDATO or SPIDAT1 register is written with new data Submit Documentation Feedback Peripheral and Electrical Specifications 83 5320 6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 26 General Timing Requirements for SPIx Slave Modes NO MIN MAX UNIT B Cycle Time SPIx_CLK All Slave Modes 256P ns 10 twsPcH s Pulse Width High 5 All Slave Modes greater of 15 ae 11 Pulse Width Low SPlx CLK All Slave Modes greater of pa Polarity 0 Phase 0 2P to SPIx_CLK rising Setup time transmit data Polarity 0 Phase 1 written to SPI and output to SPIx_CLK rising 2P 12 tsu SOMI_SPC S onto SPlx SOMI pin before i NIU initial clock edge from Polarity 1 Phase 0 2P master 2 3 to SPIx falling Polarity 1 Phase 1 to SPIx_CLK falling Polarity 0 Phase 0 from SPIx_CLK rising 2P 15 Polarity 0 Phase 1 2P 4 15 Delay subsequent bi
29. 1 ACLKR internal ACLKRCTL CLKRM 1 PDIR ACLKR 1 ACLKR external input ACLKRCTL CLKRM 0 PDIR ACLKR 0 ACLKR external output ACLKRCTL CLKRM 0 PDIR ACLKR 1 2 SYSCLK2 period ns OD OO 76 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 23 McASP Switching Characteristics NO PARAMETER MIN MAX UNIT Cycle time AHCLKR internal AHCLKR output 20 9 Cycle time AHCLKR external AHCLKR output 20 ME Cycle time AHCLKX internal AHCLKX output 20 Cycle time AHCLKX external AHCLKX output 20 Pulse duration AHCLKR internal AHCLKR output AHR 2 2 5 DAGEN Pulse duration AHCLKR external AHCLKR output AHR 2 2 5 Pulse duration AHCLKX internal AHCLKX output AHX 2 2 58 Pulse duration AHCLKX external AHCLKX output AHX 2 2 53 Cycle time ACLKR internal ACLKR output greater of 2P or 20 ns 4 Cycle time ACLKR external ACLKR output greater of 2P or 20 ns Cycle time ACLKX internal ACLKX output greater of 2P or 20 ns Cycle time ACLKX external ACLKX output greater of 2P or 20 ns Pulse duration ACLKR internal ACLKR outp
30. 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA GDH 5 256 PLASTIC BALL GRID ARRAY 15 00 TYP UDH 1 Corner E
31. 2007 The UHPI has several device level configuration registers which affect its behavior Figure 4 18 Figure 4 19 and Figure 4 20 show the bit layout of these registers Table 4 12 Table 4 13 and Table 4 14 contain a description of the bits in these registers 31 8 Reserved 7 5 4 3 2 1 0 Reserved BYTEAD FULL NMUX PAGEM ENA R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 18 CFGHPI Register Bit Layout 0x4000 0008 Table 4 12 CFGHPI Register Bit Field Description 0x4000 0008 RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 5 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 4 BYTEAD 0 R W UHPI Host Address Type 0 Host Address is a word address 1 Host Address is a byte address 3 FULL 0 R W UHPI Multiplexing Mode when NMUX 0 0 Half Word 16 bit data Multiplexed Address and Data Mode 1 Fullword 32 bit data Multiplexed Address and Data Mode 2 NMUX 0 R W UHPI Non Multiplexed Mode Enable 0 Multiplexed Address and Data Mode 1 Non Multiplexed Address and Data Mode utilizes optional UHPI HA 15 0 pins Host data bus is 32 bits in Non Multiplexed mode Setting this bit prevents the EMIF from driving data out or parking the shared EM D 31 16 UHPI HA 15 0 pins 1 PAGEM 0 R W UHPI Page Mode Enable Only for Multiplexed Address and Data Mode 0 Full 32 bit DSP address
32. 7 1 Thermal Characteristics for GDH ZDH Package NO C W Two Signal Two Plane 101 5 x 114 5 x 1 6 2 02 Cu EIA JESD51 9 PCB 1 RO Thermal Resistance Junction to Ambient 25 0 2 Thermal Resistance Junction to Board 14 5 0 3 ROjc Thermal Resistance Junction to Top of Case 10 0 4 Thermal Metric Junction to Board 14 0 5 Thermal Metric Junction to Top of Case 0 39 0 Table 7 2 Thermal Characteristics for RFP Package THERMAL PAD CONFIGURATION AIR BOTTOM ARRAY pend Two Signal Two Plane 76 2 x 76 2 mm PCB 2 3 1 Rej Thermal Resistance Junction to Ambient 10 6 x 10 6 mm 10 6 x 10 6 mm 6x6 20 0 7 5 x 7 5 mm 7 5 x 7 5 mm 5x5 22 0 2 Wp Thermal Metric Junction to Power Pad 10 6 x 10 6 mm 10 6 x 10 6 mm 6x6 0 39 0 Double Sided 76 2 x 76 2 mm PCB 2 4 3 R ja Thermal Resistance Junction to Ambient 10 6 x 10 6 mm 10 6 x 10 6 mm 6x6 49 0 10 6 x 10 6 mm 38 1 x 38 1 mm 6x6 27 0 10 6 x 10 6 mm 57 2 x 57 mm 6x6 22 0 10 6 x 10 6 mm 76 2 x 76 2 mm 6x6 20 0 4 Wp Thermal Metric Junction to Power Pad 10 6 x 10 6 mm 10 6 x 10 6 mm 6x6 0 39 0 1 PCB modeled with 2 oz ft Top and Bottom Cu 2 Package thermal pad must be properly soldered to top layer PCB thermal pad for both thermal and electrical performance Thermal pad is Vas Submit Documentation Feedback Top layer thermal pad is c
33. 8 C4 IPD Y UHPI Byte Enable for UHPI HD 23 16 HBE 3 E B2 IPD Y UHPI Byte Enable for UHPI HD 31 24 UHPI_HCNTL 0 D9 IPD Y UHPI Control Inputs Select Access Mode UHPI_HCNTL 1 C10 IPD Y UHPI HAS _ C9 IPD Y reel Strobe for Hosts with Multiplexed UHPI HRW D8 IPD Y UHPI Read not Write Input UHPI HDSTI D7 IPU Y UHPI Select Signals which create the internal HSTROBE _ 7 IPU active when 5 C8 IPU Y UHPI_HCS 0 amp UHPI HDS 1 UHPI HDS 2 UHPI_HRDY D6 IPD Y UHPI Ready Output Submit Documentation Feedback Device Overview 23 TMS320C6727 TMS320C6726 5320 6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 TEXAS INSTRUMENTS www ti com Table 2 12 Terminal Functions continued SIGNAL NAME SD PULL GPIO DESCRIPTION McASPO McASP1 McASP2 and SPI1 Serial Ports AHCLKRO AHCLKR1 143 B3 IO Y and McASP1 Receive Master Clock ACLKRO 139 A5 IO Y McASPO Receive Bit Clock AFSRO 141 B4 IO Y McASPO Receive Frame Sync L R Clock AHCLKX0 AHCLKX2 2 C2 IO Y and McASP2 Transmit Master Clock 4 ACLKXO 142 A4 IO 2 Y McASPO Transmit Bit Clock 5 0 144 IO Y McASPO Transmit Frame Sync L
34. C672x DSP As the figures illustrate the C672x DSP includes a limited number of EMIF address lines These are sufficient to connect to SDRAM seamlessly Asynchronous memory such as FLASH typically will need to use additional GPIO pins to act as upper address lines during device boot up when the FLASH contents are copied into SDRAM Normally code is executed from SDRAM since SDRAM has faster access times Any pins listed with a Y in the GPIO column of Table 2 12 may be used for this purpose as long as it can be assured that they be pulled low at and after reset and held low until configured as outputs by the DSP Note that EM BA 1 0 are used as low order address lines for the asynchronous interface For example in Figure 4 5 and Figure 4 6 the flash memory is not byte addressable and its A 0 input selects a 16 bit value The corresponding DSP address comes from EM BA 1 The remaining address lines from the DSP EM A 12 0 drive a word address into the flash inputs A 13 1 For a more detailed explanation of the C672x EMIF operation please refer to the document TMS320C672x External Memory Interface User s Guide literature number SPRUT1 1 Submit Documentation Feedback Peripheral and Electrical Specifications 45 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 46 C6726 C6722 DSP EMIF EM 5 0 EM CAS EM RAS EM WE
35. De PLL from 1 to 32 x4 to x25 Divider CLKIN or D1 CPU and Memory OSCIN 1 to 32 Divider D2 Peripherals and dMAX 1 to 32 Divider D3 EMIF 1 to 32 AUXCLK gt McASPO 1 2 Figure 4 43 PLL Topology Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 40 Allowed PLL Operating Conditions ALLOWED SETTING OR RANGE PARAMETER DEFAULT VALUE MIN MAX 1 PLLRST 1 assertion time during initialization N A 125 ns 2 Lock time before setting PLLEN 1 After changing DO PLLM or N A 187 5 us input clock 3 PLL input frequency PLLREF after DO 12 MHz 50 MHz 4 PLL multiplier values PLLM x13 x4 x25 5 PLL output frequency PLLOUT before dividers D1 D2 D3 2 N A 140 MHz 600 MHz 6 SYSCLK1 frequency set by and dividers DO D1 PLLOUT 1 Device Frequency Specification 7 SYSCLK2 frequency set by PLLM and dividers DO D2 PLLOUT 2 2 or 4 of SYSCLK1 8 SYSCLK3 frequency set by PLLM and dividers DO D3 PLLOUT 3 EMIF Frequency Specification 1 Some values for the DO divider produce results outside of this range and should not be selected 2 In general selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter
36. Dvo UHPI_ Z 21 UHPL UHPL AMUTEO Aue bp REN Aes AFSR2 ACLKR2 AHCLKR2 EM AXRo 7 UHPI AXRO 15 AXRO 13 AxRort2 AXRO 10 nad SPIO_ AFSRO IAXR2 0 1 0 1 1 C er SIMO DVpp AXRO S AXRO 14 AXRO t1 AXR1j4 Vss acLkxo ACLKRO ee SP DVpp SIMO 1 2 15 16 3 4 5 12 14 EM UHP Hopa 0 oc D D Vss UHPI_ HDS 1 UHPI UHPI m Vss Vss Vss Vss Vss Vss AMUTE HINT 02 EM 0 18 EM 046 EM 20 EM 0 29 EM 0 27 0 25 uer NT Dvoo hoer Vss Vss CVpp CVpp CVpp CVpp Vss Vss mi Vss Vss Vss Vss Vss Vss HRDY co co co n n n n n n n n Figure 2 8 256 Terminal Ball Grid Array GDH ZDH Suffix Bottom View Submit Documentation Feedback Device Overview 19 TMS320C6727 TMS320C6726 5320 6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 lt oo aM or 88 S 20 lt a oo alg oy Pas c ZN oo
37. EM CLK EM CKE EM BA 1 0 EM A 11 0 EM WE 0 EM WE DOM 1 EM D 15 0 EM CS 2 EM RW EM OE GPIO RESET 6 Pins EM BA 1 Any GPIO capable pins which can be pulled down at reset can be used to control A 18 13 for FLASH BOOTLOAD Examples AHCLKRO SPIO SCS SCL1 TEXAS INSTRUMENTS www ti com SDRAM 2M x 16 x 4 Bank BA 1 0 A 11 0 LDQM UDQM DQ 15 0 FLASH 512K x 16 Figure 4 5 C6726 C6722 DSP 16 Bit EMIF Example Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 C6727 SDRAM DSP EMIF 4M x 16 x 4 Bank EM 5 0 EM_CAS e EM RAS EM WE o EM CLK EM BA 1 0 EM A 12 0 EM WE DQM 0 EM WE DQN 1 gt EM D 15 0 EM WE DQM 2 EM WE DQN 3 SDRAM EM D 31 16 UHPI HA 15 0 4M x 16 x 4 Bank EM CS 2 EM RW EM OE EM WAIT GPIO 5 Pins Y ww NY VN Y FLASH EM vvv Y YN Any GPIO capable pins which can be pulled down at reset can be used to control A 18 14 for FLASH BOOTLOAD Examples AHCLKRO SPIO_SCS SCL1
38. Fast Mode 0 6 1 2 must be configured correctly to meet the timings in Table 4 35 Submit Documentation Feedback Peripheral and Electrical Specifications 95 TMS320C6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 35 I2C Switching Characteristics continued NO PARAMETER MIN UNIT 19 t Pulse duration I2Cx SCL Standard Mode adi ulse duration X Ow S w SCLL Fast Mode 13 20 t Pulse duration 2 SCL high 1 ulse duration Xx 5 w SCLH N Fast Mode 0 6 5 by Setup time I2Cx SDA valid before I2Cx SCL Standard Mode 250 6 TES high Fast Mode 100 22 t Hold time I2Cx SDA valid after 12Cx_SCL I as 9 E Ime X valia atter X ow S NSGEESDAV E Fast Mode 0 oo 23 1 Pulse duration I2Cx SDA high Standard Mode sell ulse duration Xx S w SDAH E Fast Mode 13 BS k Setup time 2 SCL high before I2Cx SDA Standard Mode 4 Sue aren high Fast Mode 0 6 Capacitive load on each bus line from this Standard Mode 10 29 G pF device Fast Mode 10 k 11 9 4 Z 5227 41 y 8 6 je 14 lad k 10 06 gt de _ ee a Stop Start Repeat
39. HCNTL 1 0 DESCRIPTION MULTIPLEXED HALF WORD FULLWORD FULLWORD 00 HPI Control Register HPIC Access Y Y 01 HPI Data Access HPID with autoincrementing address Y Y N 10 HPI Address Register HPIA Access Y Y N 11 HPI Data Access HPID without autoincrementing Y Y Y address CAUTION When performing a set of HPID with autoincrementing address accesses UHPI_HCNTL 1 0 01 the set must begin and end at a word aligned address In addition all four of the UHPI_HBE 3 0 must be enabled on every access in the set CAUTION The encoding of UHPI_CNTL 1 0 on the C672x DSP is different from HCNTL 1 0 on the C671x DSP Modes 01 and 10 are swapped Submit Documentation Feedback Peripheral and Electrical Specifications 55 TMS320C6727 TMS320C6726 5320 6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 56 mmootusp www ti com Figure 4 15 illustrates the Multiplexed Host Address Data Half Word Mode hookup between the C672x DSP and an external host microcontroller In this mode each 32 bit HPI access is broken up into two halves The UHPI HD 16 HHWIL pin functions as UHPI_HHWIL which must be 0 during the first half of access 1 during the second half CAUTION Unless configured as general purpose in the module HD 31 17 and UHPI HD 16 HHWIL will be driven as outputs along with UHPI HD 15 0 when the HPI is read eve
40. Layout 0x4000 0014 Table 4 37 CFGRTI Register Bit Field Description 0x4000 0014 RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 7 3 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 6 4 CAPSEL1 0 R W CAPSELO selects the input to the RTI Input Capture 0 function 2 0 CAPSELO 0 R W CAPSEL1 selects the input to the RTI Input Capture 1 function The encoding is the same for both fields 000 Select McASPO Transmit DMA Event 001 Select McASPO Receive DMA Event 010 Select McASP1 Transmit DMA Event 011 Select McASP1 Receive DMA Event 100 Select McASP2 Transmit DMA Event 101 Select McASP2 Receive DMA Event Other values are reserved and their effect is not determined Submit Documentation Feedback Peripheral and Electrical Specifications 99 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 4 17 External Clock Input From Oscillator or CLKIN Pin www ti com The C672x device includes two choices to provide an external clock input which is fed to the on chip PLL to generate high frequency system clocks These options are illustrated in Figure 4 42 e Figure 4 42 a illustrates the option that uses an on chip 1 2 V oscillator with external crystal circuit e Figure 4 42 b illustrates the option that uses an external 3 3 V LVCMOS compatible clock input w
41. R Clock AMUTEO 3 C1 McASPO MUTE Output AXRO 0 113 14 IO Y McASPO Serial Data 0 AXRO 1 115 B13 IO s Y McASPO Serial Data 1 AXRO 2 116 A13 IO Y McASPO Serial Data 2 AXRO 3 117 B12 IO Y McASPO Serial Data AXRO 4 119 A12 IO Y McASPO Serial Data 4 AXRO BJSPH 5 5 120 B11 IO Y McASPO Serial Data 5 or SPI1 Slave Chip Select AXRO 6 SPH 121 A11 IO Y McASPO Serial Data 6 or SPI1 Enable Ready AXRO 7 SPI1_CLK 122 B10 IO Y McASPO Serial Data 7 or SPI Serial Clock AXRO 8 AXR1 5 126 B9 _ Y McASPO Serial Data 8 or McASP1 Serial Data 5 or SPI SPH SOMI Data Pin Slave Out Master In AXRO 9 AXR1 4 127 A9 _ Y McASPO Serial Data 9 or McASP1 Serial Data 4 or SPI1 SPI1_SIMO Data Pin Slave In Master Out AXRO 10y AXR1 3 130 B8 IO Y McASPO Serial Data 10 or McASP1 Serial Data AXRO 11 AXR1 2 131 A8 IO Y McASPO Serial Data 11 or McASP1 Serial Data 2 AXRO 12 AXR1 1 134 B7 IO Y McASPO Serial Data 12 or McASP1 Serial Data 1 AXRO 13 AXR1 0 135 B6 IO Y McASPO Serial Data 13 or McASP1 Serial Data 0 AXRO 14J AXR2 1 137 A6 IO Y Serial Data 14 or McASP2 Serial Data 1 4 AXRO 15 AXR2 0 138 B5 IO Y McASPO Serial Data 15 or McASP2 Serial Data 0 ACLKR1 9 E1 IO 2 Y McASP1 Receive Bit Clock AFSR1 12 F1 IO Y McASP1 Receive Frame Sync L R Clock AHCLKX1 5 D1 IO Y McASP1 Transmit Master Clock ACLKX1 7 E2 IO Y McASP1 Transmit Bit Clock AFSX1 11 F2 IO Y McASP1 Transmit Frame Sync L R Cloc
42. is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0
43. level to the master This option is useful when tying several SPI slave devices to a single master 88 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 i MASTER MODE 422 3 4 POLARITY 0 PHASE 0 SPIx CLK T UH GEI MM uec _ ham l ES i e so EE Xy ET ee SPI soul MASTER MODE 4 POLARITY 0 PHASE 1 A t cc ME 4 5 1 6 puse SPL SOM wii a MASTER MODE POLARITY 1 PHASE 0 SPk CLK 1 A 4773 5 SPI_SIMO MOT SPI_SOMI MI 1 MASTER MODE POLARITY 1 PHASE 1 SPIX CLK SSCS 3 PERS 504 5 e SPI SPI_SOMI Figure 4 33 SPI Timings Master Mode Submit Documentation Feedback Peripheral and Electrical Specifications 89 TMS320C6727 TMS320C6726 5320 6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 ME MERE SLAVE MODE POLARITY 0 PHASE 0 SPIx CLK Liesl es SPI_SIMO 5 0 E 13 14 SPI SOMI 50 SO 50 17 Xy Som 12 SLAVE MODE POLARITY 0 PHASE 1 SPIx CLK jo c y
44. ns 17 tsu HD DSH Setup time HD valid before DS rising edge 5 ns 18 th DSH HD Hold time HD valid after DS rising edge 0 ns 37 tsu HCSL DSL Setup time UHPI_HCS low before DS falling edge 0 ns 38 th HRDYH DSL Hold time DS low after UHPI HRDY rising edge 1 ns 1 SYSCLK2 period 2 DS refers to HSTROBE HD refers to UHPI HD 31 0 HDS refers to UHPI HDS 1 or UHPI HDS 2 HAD refers to UHPI HONTL OJ UHPI HONTL 1 HHWIL and UHPI HRW 62 Peripheral and Electrical Specifications Submit Documentation Feedback 4 TEXAS TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 16 Read and Write Switching Characteristics NO PARAMETER MIN MAX UNIT Case 1 HPIC or HPIA read 1 15 Case 2 HPID read with no 7 3 auto increment Case 3 HPID read with 1 taosL HDv Delay time DS low to HD valid auto increment and read FIFO 9 2H 200 ns initially empty Case 4 HPID read with auto increment and data previously 1 15 prefetched into the read FIFO 2 is DSH HDV Disable time HD high impedance from DS high 4 ns 3 ten DSL HDD Enable time HD driven from DS low 3 15 ns 4 taDsL HRDYH Delay time DS low to high 12 ns 5 apsH HRDYH Delay time DS high to UHPI_HRDY high 12 ns Case 1 HPID read with no 3 ________ auto inc
45. safe I O buffers Noise Filter to Remove Noise 50 ns or less e Seven and Ten Bit Device Addressing Modes e Master Transmit Receive and Slave Transmit Receive Functionality e Events DMA Interrupt or Polling e General Purpose I O Capability if not used as 2 CAUTION The C672x 2 pins use a standard 8 mA LVCMOS buffer not the slow I O buffer defined in the I2C specification Series resistors may be necessary to reduce noise at the system level C672x I2C Module Control I2CCOARx Clock Prescaler I2CPSCx Own Address Register Prescaler Register I2CSARx Slave Address Bit Clock Generator Register I2Cx SCL Clock Divide I2CCLKHx High Register I2CCMDRx Mode Register Clock Divide I2CEMDRx Extended Mode ROCLKLX Low Register Register Data Count Peripheral Register Configuration Transmit Bus Transmit Shift Peripheral ID I2CPID1 I2CXSRx Register Register 1 lt gt Peripheral ID I2CPID2 I2CDXRx Transmit Buffer Register 2 I2Cx SDA Noise Interrupt DMA Filter 2 Interrupt Enable Register Receive Interrupt DMA Requests I2CDRRx Receive Buffer AN I2CSTRx Receive Shift I2CRSRx I2CSRCx Interrupt Status Register Interrupt Source Register Register Control Pin Function Pin Data Out I2CPDOUT I2CPFUNC Register
46. shows only Polarity 0 Phase 0 as an example Table gives parameters for all four master clocking modes In the case where the master SPI is ready with new data before SPIx SCS assertion This delay can be increased under software control by the register bit field SPIDELAY C2TDELAY 4 0 Except for modes when SPIDAT1 CSHOLD is enabled and there is additional data to transmit In this case SPIx SCS will remain asserted This delay can be increased under software control by the register bit field SPIDELAY T2CDELAY 4 0 Peripheral and Electrical Specifications 85 TMS320C6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 29 Additional SPI Master Timings 5 Pin Option NO MIN MAX UNIT Polarity 0 Phase 0 0 5t from SPIx CLK falling Ue SPOM Max delay for slave to deassert SPIx ENA after Polarity 0 Phase 1 0 48 final SPlIx CLK edge to from SPIx falling d SPC_ENA M ensure master does not Polarity 1 Phase 0 begin the next from SPIx_CLK rising 0 5te spoym transfer 4 Polarity 1 Phase 1 0 from SPIx CLK rising Polarity 0 Phase 0 0 5t from SPIx_CLK falling Ue SPOM Delay from final Polarity 0 Phase 1 0 20 SPIx edge to from SPIx CLK falling d SPC SCS M master deasserting Polarity i y
47. signal processor DSP TMS320C672x DSP External Memory Interface EMIF User s Guide This document describes the operation of the external memory interface in the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform TMS320C672x DSP Serial Peripheral Interface SPI Reference Guide This reference guide provides the specifications for a 16 bit configurable synchronous serial peripheral interface The SPI is a programmable length shift register used for high speed communication between external peripherals or other DSPs TMS320C672x DSP Universal Host Port Interface UHPI Reference Guide This document provides an overview and describes the common operation of the universal host port interface UHPI TMS320C672x DSP Multichannel Audio Serial Port McASP Reference Guide This document describes the multichannel audio serial port McASP in the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform TMS320C672x DSP Software Programmable Phase Locked Loop PLL Controller Reference Guide This document describes the operation of the software programmable phase locked loop PLL controller in the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform TMS320C67x C67x DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C67x and TMS320C67x digital signal processors DSPs of the TMS32
48. slave is ready to begin another transfer In five pin mode the SPIx_ENA is additionally qualified by SPIx SCS being asserted This allows a single handshake line to be shared by multiple slaves on the same SPI bus In master mode the SPIx ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx The addition of this handshake signal simplifies SPI communications and on average increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst case latency of the slave device Instead each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Optional Slave Chip Select SPIx SCS SPIx SCS Optional Enable Ready SPIx ENA SPIx ENA SPIx CLK SPIx CLK SPIx SOMI SPIx SOMI SPIx SIMO SPIx SIMO MASTER SPI SLAVE SPI Figure 4 32 Illustration of SPI Master to SPI Slave Connection Submit Documentation Feedback Peripheral and Electrical Specifications 81 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED
49. specified through host port 1 Only lower 16 bits of DSP address are specified through host port Upper 16 bits are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers 0 ENA 0 R W UHPI Enable 0 UHPI is disabled 1 UHPI is enabled Set this bit to 1 only after configuring the other bits in this register 60 Peripheral and Electrical Specifications Submit Documentation Feedback 4 TEXAS TMS320C6727 TMS320C6726 5320 6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 31 Reserved 7 HPIAMSB R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 19 CFGHPIAMSB Register Bit Layout 0x4000 000C Table 4 13 CFGHPIAMSB Register Bit Field Description 0x4000 000C BIT NO NAME RESET READ in Multiplexed Address and Data mode when PAGEM 1 Sets bits 31 24 of the DSP internal address as accessed through UHPI VALUE WRITE DESCRIPTION 31 8 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 7 0 HPIAMSB 0 R W UHPI most significant byte of DSP address to access in Non Multiplexed mode and 31 Reserved 7 HPIAUMB R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 20 CFGHPIAUMB Register Bit Layout 0x4000 0010 Table 4 14 CFGHPIAUMB Register Bit Field Description 0x40
50. submission of transfer requests to occur automatically based on system events without any intervention by the CPU The dMAX also includes support for CPU initiated transfers for added control and robustness and they can be used to start memory to memory transfers To generate an event to the dMAX controller the CPU must create a transition on one of the bits from the dMAX Event Trigger DETR Register which are mapped to the DER register Submit Documentation Feedback Peripheral and Electrical Specifications 41 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 TEXAS INSTRUMENTS www ti com Table 4 2 lists how the synchronization events are associated with event numbers in the dMAX controller Table 4 2 dMAX Peripheral Event Input Assignments EVENT NUMBER EVENT ACRONYM EVENT DESCRIPTION 0 DETR O0 The CPU triggers the event by creating appropriate transition edge on bitO in DETR register 1 DETR 16 The CPU triggers the event by creating appropriate transition edge on bit16 in DETR register 2 RTIREQO RTI DMA REQ O 3 RTIREQ1 RTI DMA REQ 1 4 MCASPOTX McASPO DMA REQ 5 MCASPORX McASPO RX DMA REQ 6 MCASP1TX McASP1 TX DMA REQ 7 MCASP1RX McASP1 RX DMA REQ 8 MCASP2TX McASP2 TX DMA REQ 9 MCASP2RX McASP2 RX DMA REQ 10 DETR 1 The CPU trigg
51. that can be 8 16 or 32 bits wide Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general purpose I O pins for upper address lines The asynchronous memory interface can also be configured to support 8 or 16 bit wide NAND flash It includes a hardware ECC calculation for single bit errors that can operate on blocks of data up to 512 bytes Universal Host Port Interface for High Speed Parallel I O The Universal Host Port Interface UHPI is a parallel interface through which an external host CPU can access memories on the DSP Three modes are supported by the C672x UHPI Multiplexed Address Data Half Word 16 bit wide Mode similar to C6713 Multiplexed Address Data Full Word 32 bit wide Mode e Non Multiplexed Mode 16 bit Address and 32 bit Data Bus The UHPI can also be restricted to accessing a single page 64K bytes of memory anywhere in the address space of the C672x this page can be changed but only by the C672x CPU This feature allows the UHPI to be used for high speed data transfers even in systems where security is an important requirement The UHPI is only available on the C6727 Multichannel Audio Serial Ports McASPO McASP1 and McASP2 Up to 16 Stereo Channels 125 The multichannel audio serial port McASP seamlessly interfaces to CODECs DACs ADCs and other devices It supports the ubiquitous IIS format as well as many v
52. user data register 5 0 4600 0148 DITUDRBO Right channel user data register 0 0 4600 014C DITUDRB1 Right channel user data register 1 0 4600 0150 DITUDRB2 Right channel user data register 2 0 4600 0154 DITUDRB3 Right channel user data register 3 0 4600 0158 DITUDRB4 Right channel user data register 4 0 4600 015 DITUDRB5 Right channel user data register 5 0x4400 0180 0x4500 0180 0 4600 0180 SRCTLO Serializer control register 0 0x4400 0184 0x4500 0184 0 4600 0184 SRCTL1 Serializer control register 1 0x4400 0188 0x4500 0188 SRCTL2 Serializer control register 2 0x4400 018C 0x4500 018C SRCTL3 Serializer control register 3 0x4400 0190 0x4500 0190 SRCTL4 Serializer control register 4 0x4400 0194 0x4500 0194 SRCTL5 Serializer control register 5 0x4400 0198 SRCTL6 Serializer control register 6 0x4400 019C SRCTL7 Serializer control register 7 0x4400 01A0 SRCTL8 Serializer control register 8 0x4400 01A4 SRCTL9 Serializer control register 9 0x4400 01A8 SRCTL10 Serializer control register 10 0x4400 01AC SRCTL11 Serializer control register 11 0x4400 01 0 SRCTL12 Serializer control register 12 0x4400 01B4 SRCTL13 Serializer control register 13 0x4400 01B8 SRCTL14 Serializer control register 14 0x4400 01BC SRCTL15 Serializer control register 15 0x4400 0200 0x4500 0200 0x4600 0200 XBUFO Transmit buffer register for serializer 0 0x4400 0204 0x4500 0204 0x4600 0204 XBUF
53. with referenced to Vss unless otherwise specified 3 If OSCVpp and OSCVss pins are used as filter pins for reduced oscillator jitter they should not be connected to CVpp and Vss 4 3 Recommended Operating Conditions MIN NOM MAX UNIT CVpp Core Supply Voltage 1 14 1 2 1 32 V DVpp Supply Voltage 3 13 3 3 3 47 V Tc Operating Case Temperature Range Default 0 90 A version 40 105 1 All voltage values are with referenced to Vss unless otherwise specified Submit Documentation Feedback Peripheral and Electrical Specifications 33 TMS320C6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 4 4 Electrical Characteristics Over Operating Case Temperature Range Unless Otherwise Noted PARAMETER TEST CONDITIONS TYP MAX UNIT Vou High Level Output Voltage 100 VoL Low Level Output Voltage 100 pA 0 2 V lou High Level Output Current Vo 0 8 DVpp 8 mA lo Low Level Output Current Vo 0 22 DVpp 8 mA Vin High Level Input Voltage DVpp V Low Level Input Voltage 0 8 V Vuys Input Hysterisis 0 13 DVpp V loz Input Current and Off State Output Pins without pullup or pulldown 10 Current Pins with internal pullup 170 Pins with internal pulldown 170 ttr Input Transition Time 25 ns Input Capacitance pF Co Output Capacitanc
54. 0 begin the next transfer 5 from lt rising O StcsPC M Polarity 1 Phase 1 0 from SPIx CLK rising 1 These parameters are in addition to the general timings for SPI master modes Table 4 25 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four master clocking modes 4 In the case where the master SPI is ready with new data before SPIx_ENA assertion 5 the case where the master SPI is ready with new data before SPIx_ENA deassertion Table 4 28 Additional SPI Master Timings 4 Chip Select Option 3 NO MIN MAX UNIT Polarity 0 Phase 0 _ to SPIx_CLK rising ao Polarity 0 Phase 1 ia 0 5t 2P 10 49 i Delay from SPIx_SCS active to 10 SPIx_CLK rising d SCS SPC M first SPIx CLK 0 Polarity 1 Phase 0 m to SPIx falling Polarity 1 Phase 1 to SPlx falling 0 51 2P 10 Polarity 0 Phase 0 0 51 from SPIx_CLK falling e SPCM Polarity 0 Phase 1 Delay from final SPIx_CLK edge from falling 0 20 tywspc_scs m to master deasserting ns SPIx SCS 97 Polarity 1 Phase 0 0 51 x from SPIx CLK rising Ue SPCM Polarity 1 Phase 1 0 from SPIx CLK rising S99 9N Submit Documentation Feedback These parameters are in addition to the general timings for SPI master modes Table 4 25 P SYSCLK2 period Figure
55. 0 0034 0x4A00 0034 I2CPID1 Peripheral Identification Register 1 0x4900 0038 0x4A00 0038 I2CPID2 Peripheral Identification Register 2 0x4900 0048 0x4A00 0048 I2CPFUNC Pin Function Register 0x4900 004C 0x4A00 004C I2CPDIR Pin Direction Register 0x4900 0050 0x4A00 0050 I2CPDIN Pin Data Input Register 0x4900 0054 0x4A00 0054 I2CPDOUT Pin Data Output Register 0x4900 0058 0x4A00 0058 I2CPDSET Pin Data Set Register 0x4900 005C 0x4A00 005C I2CPDCLR Pin Data Clear Register 94 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 15 3 2 Electrical Data Timing 4 15 3 1 Inter Integrated Circuit I2C Timing Table 4 34 and Table 4 35 assume testing over recommended operating conditions see Figure 4 38 and Figure 4 39 Table 4 34 2 Input Timing Requirements NO MIN MAX UNIT i t Bude ee Ser Standard Mode 10 cle time I2Cx S E Fast Mode 25 a gt Nh Setup time 2 SCL high before I2Cx SDA Standard Mode 4 7 us Su SCLH SDAL low Fast Mode 0 6 3 t Hold ti 2 SCLI 2 SDA a old time I2Cx ow after 2 OW S h SCLL SDAL Fast Mode 06 i palse duratione scii Standard Mode 4 7 ulse dura
56. 00 0010 RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 8 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 7 0 HPIAUMB 0 R W UHPI upper middle byte of DSP address to access in Non Multiplexed mode and in Multiplexed Address and Data mode when PAGEM 1 Sets bits 23 16 of the DSP internal address as accessed through UHPI Submit Documentation Feedback Peripheral and Electrical Specifications 61 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 4 12 3 UHPI Electrical Data Timing 4 12 3 1 Universal Host Port Interface UHPI Read and Write Timing Table 4 15 and Table 4 16 assume testing over recommended operating conditions see Figure 4 21 through Figure 4 24 Table 4 15 UHPI Read and Write Timing Requirements NO MIN MAX UNIT 9 tsu HASL DSL Setup time low before DS falling edge 5 ns 10 th DSL HASL Hold time UHPT HAS low after DS falling edge 2 ns 11 tsu HAD HASL Setup time HAD valid before UHPI_HAS falling edge 5 ns 12 th HASL HAD Hold time HAD valid after UHPI_HAS falling edge 5 ns 13 tw DSL Pulse duration DS low 15 n 14 tw DSH Pulse duration DS high 2P n8 15 tsu HAD DSL Setup time HAD valid before DS falling edge 5 ns 16 th DSL HAD Hold time HAD valid after DS falling edge 5
57. 00 0048 0x4800 0048 SPIDELAY Delay Register 0x4700 004C 0x4800 004C SPIDEF Default Chip Select Register 0x4700 0050 0x4800 0050 SPIFMTO Format Register 0 0x4700 0054 0x4800 0054 SPIFMT1 Format Register 1 0x4700 0058 0x4800 0058 SPIFMT2 Format Register 2 0x4700 005C 0x4800 005C SPIFMT3 Format Register 3 0x4700 0060 0x4800 0060 TGINTVECTO Interrupt Vector for SPI INTO 0x4700 0064 0x4800 0064 TGINTVECT1 Interrupt Vector for SPI INT1 82 Peripheral and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 4 14 3 SPI Electrical Data Timing 4 14 3 1 Serial Peripheral Interface SPI Timing TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 25 through Table 4 32 assume testing over recommended operating conditions see Figure 4 33 through Figure 4 36 Table 4 25 General Timing Requirements for SPIx Master Modes NO MIN MAX UNIT Cycle Time SPlx All Master Modes 256P ns 2 w SPCHM Pulse Width High SPIx CLK All Master Modes greater of 4P or 45 ns ns tw SPCL M Pulse Width Low SPIx_CLK All Master Modes greater of 4P or 45 ns ns Polarity 0 Phase 0 to SPIx_CLK rising Polarity 0 Phase 1 Delay initial data bit valid to EHI CLK rising O Stcspc u 4P 4 t on SPIx SIMO to initial n
58. 0C6000 DSP platform The C67x C67x DSP generation comprises floating point devices in the C6000 DSP platform The C67x DSP is an enhancement of the C67x DSP with added functionality and an expanded instruction set 28 Device Overview Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SPRAA69 SPRU301 SPRU198 SPRU186 SPRU187 SPRA839 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Using the TMS320C672x Bootloader Application Report This document describes the design details about the TMS320C672x bootloader This document also addresses parallel flash and HPI boot to the extent relevant TMS320C6000 Code Composer Studio Tutorial This tutorial introduces you to some of the key features of Code Composer Studio Code Composer Studio extends the capabilities of the Code Composer Integrated Development Environment IDE to include full awareness of the DSP target by the host and real time analysis tools This tutorial assumes that you have Code Composer Studio which includes the TMS320C6000 code generation tools along with the APIs and plug ins for both DSP BIOS and RTDX This manual also assumes that you have installed a target board in your PC containing the DSP device TMS320C6000 Programmer s Guide Reference for programming the TMS320C6000 digital signal processors DSPs Before you use this manual you should install your code gen
59. 1 Transmit buffer register for serializer 1 0x4400 0208 0x4500 0208 2 1 Transmit buffer register for serializer 2 1 Writes to XRBUF originate from peripheral configuration bus only when XBUSEL 1 in XFMT Submit Documentation Feedback Peripheral and Electrical Specifications 71 TMS320C6727 TMS320C6726 5320 6722 Floating Point Digital Signal Processors TEXAS INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus continued BYTE BYTE BYTE ET DESCRIPTION ADDRESS ADDRESS ADDRESS 0x4400 020C 0x4500 020C XBUFS3 Transmit buffer register for serializer 3 0x4400 0210 0x4500 0210 XBUF4 1 Transmit buffer register for serializer 4 0x4400 0214 0x4500 0214 XBUF5 Transmit buffer register for serializer 5 0x4400 0218 XBUF6 Transmit buffer register for serializer 6 0x4400 021C XBUF7 Transmit buffer register for serializer 7 0x4400 0220 8 1 Transmit buffer register for serializer 8 0x4400 0224 XBUF9 Transmit buffer register for serializer 9 0x4400 0228 XBUF10 Transmit buffer register for serializer 10 0x4400 022C XBUF 11 1 Transmit buffer register for serializer 11 0x4400 0230 XBUF12 Transmit buffer register for serializer 12 0x4400 0234 XBUF13 1 Tr
60. 1 15 16 gt 15 9716 SPI SIMO SK0 LK Sl n 1 ad 56 13 SPI SOMI 0 0 SO 1 SO n 1 SO n 12 SLAVE MODE POLARITY 1 PHASE 0 SPX CLK 5 6 gt 13 1 SPL som PES 2 SLAVE MODE POLARITY 1 PHASE 1 SPIx_CLK 4 7M l 15 4 16 amp 1 1 SPI Figure 4 34 SPI Timings Slave Mode 90 Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 MODE 4 PIN WITH ENABLE SPIx CLK og 3 oo SPI_SIMO Ret MO 1 MO n 1 DART MET M SPI SOMI fiM XL 4 MASTER MODE 4 PIN WITH CHIP SELECT Mali SPIx CLK 4 3 SPI SIMO MO n 1 p 2 4 MASTER MODE 5 PIN pos MO 1 le 23 84 x CLK mm MEN SPI SIMO MO 0 sow CD gt 4 21 MI 0 MI 1 1 SPIx ENA DESELUJ DESEL A SPIx_SCS A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP Figure 4 35 SPI Timings Master Mode 4 Pin and 5 Pin Submit Documentation Feedback Peripheral and Electrical Specifications 91 5320 6727 TMS320C6726 TMS320C6722 49 Texas Floating Point Digital Si
61. 4200 0074 Reserved Reserved bit 0x4200 0080 RTISETINT Set Interrupt Enable Sets interrupt enable bits int RTIINTCTRL without having to do a read modify write operation 0x4200 0084 RTICLEARINT Clear Interrupt Enable Clears interrupt enable bits int RTIINTCTRL without having to do a read modify write operation 98 Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 36 RTI Registers continued BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4200 0088 RTIINTFLAG Interrupt Flags Interrupt pending bits 0x4200 0090 RTIDWDCTRL Digital Watchdog Control Enables the Digital Watchdog 0x4200 0094 RTIDWDPRLD Digital Watchdog Preload Sets the experation time of the Digital Watchdog 0x4200 0098 RTIWDSTATUS Watchdog Status Reflects the status of Analog and Digital Watchdog 0x4200 009C RTIWDKEY Watchdog Key Correct written key values discharge the external capacitor 0x4200 00A0 RTIDWDCNTR Digital Watchdog Down Counter Figure 4 41 shows the bit layout of the CFGRTI register and Table 4 37 contains a description of the bits 31 8 Reserved 7 6 4 3 2 0 Reserved CAPSEL1 Reserved CAPSELO R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 41 CFGRTI Register Bit
62. 50 and 44 ie 4 4 ns C6722A 225 C6727 250 5 6722 200 Core V 1 2V Voltage V 3 3V Prescaler I1 12 8 132 Clock Generator Options Multiplier X4 x5 x6 x25 Postscaler 2 8 132 256 Terminal PBGA GDH _ _ Tum 256 Terminal Green Packages see Section 7 PBGA ZDH 20 x 20 mm _ 144 Pin PowerPAD 144 Pin PowerPAD Green TQFP RFP Green TQFP RFP Process Technology um 0 13 um Product Preview PP Product Status 1 Advance Information Al or PD Production Data PD 1 Advance Information concerns new products in the sampling or preproduction phase of development Characteristic data and other specifications are subject to change without notice Submit Documentation Feedback Device Overview TMS320C6727 TMS320C6726 TMS320C6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 2 2 Enhanced C67x CPU 2 www ti com The TMS320C672x floating point digital signal processors are based on the new C67x CPU This core is code compatible with the C67x CPU core used on the TMS320C671x DSPs but with significant enhancements including an increase in core operating frequency from 225 MHz to 300 MHz while operating at 1 2 V The CPU fetches 256 bit wide advanced very long instruction word VLIW fetch packets that are composed of variable length execute packets The execute packets can supply from one to eigh
63. 6727 TMS320C6726 5320 6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 2 12 the Terminal Functions table identifies the external signal names the associated pin ball numbers along with the mechanical package designator the pin type I IO OZ PWR whether the pin ball has any internal pullup pulldown resistors whether the pin ball is configurable as an IO in GPIO mode and a functional pin description Table 2 12 Terminal Functions SIGNAL NAME SD PULL GPIO DESCRIPTION External Memory Interface EMIF Address and Control EM A 0 91 J16 EM A 1 89 J15 _ 2 88 15 EM_A 3 86 L16 O N EM A 4 84 L15 EM A 5 83 M16 _ 6 80 M15 EMIF Address Bus EM 79 N16 EM A 8 76 N15 _ 9 75 P16 _ 10 93 H15 _ 11 74 15 _ 12 12 IPD N EM BA 0 96 G15 SDRAM Bank Address Asynchronous Memory _ 1 94 H16 Low Order Address EM CS 0 97 F15 SDRAM Chip Select EM CS 2 100 E15 Asynchronous Memory Chip Select EM_CAS 37 R3 SDRAM Column Address Strobe EM_RAS 98 F16 SDRAM Row Address Strobe EM_WE 38 T3 SDRAM Asynchronous Write Enable EM_CKE 71 T14 SDRAM Cloc
64. 8 tena EM_CLKH EM_DLz S Output hold time EM CLK rising to EM_D 31 0 driving 1 15 ns 21 1 CLKH EM CS2V A Delay time from EM_CLK rising edge to EM_CS 2 valid 0 8 ns 22 CLKH EM WE DOMV A Delay time EM CLK rising to EM WE DQN 3 0 valid 0 8 ns 23 laEM CLKH EM AVJA Delay time CLK rising to A 12 0 and EM BA 1 0 valid 0 8 ns 24 taEM_CLKH EM_DV A Delay time EM_CLK rising to EM_D 31 0 valid 0 8 ns 25 td EM_CLKH EM_OEV A Delay time EM_CLK rising to EM_OE valid 0 8 ns 26 CLKH EM RW A Delay time EM CLK rising to EM RW valid 0 8 ns 27 ldis EM CLKH EM DDISJA Delay time EM CLK rising to EM D 31 0 3 stated 0 8 ns 32 1 CLKH EM Delay time EM CLK rising to EM WE valid 0 8 ns 1 These parameters apply to memories selected by EM CS 2 in both normal NAND modes 50 Peripheral and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com BASIC SDRAM WRITE OPERATION TMS320C6727 5320 6726 5320 6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 pee mk A VS SP ONCE NC ONU ONCE M ka wea yp Em WE DOMIS 0 M OO 8 EM BAL M 8 EM AN EEEEEEEEEEEEEEEEEENR 9 gt 120 EMCRS _ _15_ gt 16 Figure 4 7 Basic SDRAM Write Operat
65. 84 0 4600 0084 RSLOT Current receive TDM time slot register 0x4400 0088 0x4500 0088 0x4600 0088 RCLKCHK Receive clock check control register 0x4400 008C 0x4500 008C 0x4600 008C REVTCTL Receiver DMA event control register 0x4400 00A0 0x4500 00A0 0 4600 00 0 XGBLCTL Transmitter global control register Alias of only transmit bits are affected allows transmitter to be reset independently from receiver 0x4400 00A4 0x4500 00A4 0x4600 00A4 XMASK Transmit format unit bit mask register 0x4400 00A8 0x4500 00A8 0 4600 00 8 XFMT Transmit bit stream format register 0x4400 00AC 0x4500 00AC 0x4600 00AC AFSXCTL Transmit frame sync control register 0x4400 00 0 0 4500 00 0 0 4600 0080 ACLKXCTL Transmit clock control register 0x4400 00B4 0x4500 00B4 0x4600 0084 Transmit high frequency clock control register 0x4400 00B8 0x4500 00B8 0x4600 00B8 XTDM Transmit TDM time slot 0 31 register 0x4400 00BC 0x4500 00BC 0x4600 00BC XINTCTL Transmitter interrupt control register 0x4400 00C0 0 4500 00 0 0 4600 0060 Transmitter status register 0x4400 0004 0x4500 00C4 0 4600 0064 XSLOT Current transmit TDM time slot register 70 Peripheral and Electrical Specifications Submit Documentation Feedback TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 ki TEXAS INSTRUMENTS www ti com Table 4 18 McASP Registers
66. 8E MAY 2005 REVISED JANUARY 2007 The C672x DSP executes code directly from a large on chip 32K byte program cache The program cache has these key features Wide 256 bit path to internal ROM RAM Single cycle access on cache hits 2 cycle miss penalty to internal ROM RAM Caches external memory as well as ROM RAM Direct mapped Modes Enable Freeze Bypass Software invalidate to support code overlay The program cache line size is 256 bits wide and is matched with a 256 bit wide path between cache and internal memory This allows the program cache to fill an entire line corresponding to eight C67x CPU instructions with only a single miss penalty of 2 cycles The program cache control registers are listed in Table 2 4 Table 2 4 Program Cache Control Registers REGISTER NAME BYTE ADDRESS DESCRIPTION L1PISAR 0x2000 0000 L1P Invalidate Start Address L1PICR 0x2000 0004 L1P Invalidate Control Register CAUTION Any application which modifies the contents of program RAM for example a program overlay must invalidate the addresses from program cache to maintain coherency by explicitly writing to the L1PISAR and L1PICR registers The Cache Mode Enable Freeze Bypass is configured through a CPU internal register CSR bits 7 5 These options are listed in Table 2 5 Typically only the Cache Enable Mode is used But advanced users may utilize Freeze and Bypass modes to tune performance Table 2 5 Cache Mo
67. Accessed Through Peripheral Configuration Bus continued BYTE BYTE BYTE ER DESCRIPTION ADDRESS ADDRESS ADDRESS 0x4400 00C8 0x4500 00C8 0 4600 00C8 XCLKCHK Transmit clock check control register 0x4400 00CC 0x4500 00CC 0 4600 00CC XEVTCTL Transmitter DMA event control register 0 4600 0100 DITCSRAO Left channel status register 0 0 4600 0104 DITCSRA1 Left channel status register 1 0 4600 0108 DITCSRA2 Left channel status register 2 0 4600 010C DITCSRA3 Left channel status register 3 0 4600 0110 DITCSRA4 Left channel status register 4 0 4600 0114 DITCSRA5 Left channel status register 5 0 4600 0118 DITCSRBO Right channel status register 0 0 4600 011 DITCSRB1 Right channel status register 1 0 4600 0120 DITCSRB2 Right channel status register 2 0 4600 0124 DITCSRB3 Right channel status register 3 0 4600 0128 DITCSRB4 Right channel status register 4 0 4600 012C DITCSRB5 Right channel status register 5 0 4600 0130 DITUDRAO Left channel user data register 0 0x4600 0134 DITUDRA1 Left channel user data register 1 0 4600 0138 DITUDRA2 Left channel user data register 2 0 4600 013 DITUDRA3 Left channel user data register 3 0 4600 0140 DITUDRA4 Left channel user data register 4 0x4600 0144 DITUDRA5 Left channel
68. CAUTION SYSCLK1 SYSCLK2 SYSCLK3 must be configured as aligned by setting ALNCTL 2 0 to 1 and the PLLCMD GOSET bit must be written every time the dividers D1 D2 and D3 are changed in order to make sure the change takes effect and preserves alignment CAUTION When changing the PLL parameters which affect the SYSCLK1 SYSCLK2 SYSCLK3 dividers the bridge BR2 in Figure 2 4 must be reset by the CFGBRIDGE register See Table 2 7 The PLL is an analog circuit and is sensitive to power supply noise Therefore it has a dedicated 3 3 V power pin PLLHV that should be connected to DV at the board level through an external filter as illustrated in Figure 4 44 BOARD DVpp 3 3 V PLLHV Place Filter and Capacitors as Close to DSP as Possible EMI Filter EMI Filter TDK 451832 333 223 153 or 103 Panasonic EXCCET103U or Equivalent Figure 4 44 PLL Power Supply Filter Submit Documentation Feedback Peripheral and Electrical Specifications 103 TMS320C6727 TMS320C6726 5320 6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 18 2 PLL Registers Description s TEXAS INSTRUMENTS www ti com Table 4 41 is a list of the PLL registers For more information about these registers see the TMS320C672x DSP Software Programmable Phase Locked Loop PLL Controller Reference Guide literature number SPRU879 Table 4 41 PLL Controller Registers
69. CLKRM 0 PDIR ACLKR 1 AHR Cycle time AHCLKR AHX Cycle time AHCLKX P SYSCLK2 period AR ACLKR period AX ACLKX period STESS Submit Documentation Feedback Peripheral and Electrical Specifications 77 5320 6727 TMS320C6726 TMS320C6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 2 1 le lle AHCLKR X Falling Edge Polarity UU UU UT UU AHCLKR X Rising Edge Polarity ALLL fmm ACLKR X CLKRP CLKXP 1 8 SDDS SAAT AFSR X Bit Width 0 Bit Delay AFSR X Bit Width 1 Bit Delay MNZ NEN AFSR X Bit Width 2 Bit Delay AFSR X Slot Width 0 Bit Delay AFSR X Slot Width 1 Bit Delay ae 222 AFSR X Slot Width 2 Bit Delay SW 7 AXR n Data In Receive FAX AX AKANE KANE XANAX AIX A0 1 A30 A31 BO B1 B30B31 CO C1 C2 C3 C31 A For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in B For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in Figure 4 29 McASP Input Timings 78 Peripheral and Electrical Specifications Submit Documentation Feedback
70. CPU S Unit DP DP gt DP 1 SP means IEEE Single Precision 32 bit operations and DP means IEEE Double Precision 64 bit operations Finally two new registers which are dedicated to communication with the dMAX unit have been added to the C67x4 CPU These registers are the dMAX Event Trigger Register DETR and the dMAX Event Status Register DESR They allow the CPU and dMAX to communicate without requiring any accesses to the memory system 2 3 CPU Interrupt Assignments Table 2 3 lists the interrupt channel assignments on the C672x device If more than one source is listed the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled peripherals on that channel The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status INT7 and transfer completion INT8 In addition the dMAX can generate interrupts to the CPU on lines INT9 13 and INT15 in response to peripheral events To enable this functionality the associated Event Entry within the dMAX can be programmed so that a CPU interrupt is generated when the peripheral event is received Table 2 3 CPU Interrupt Assignments CPU INTERRUPT INTERRUPT SOURCE INTO RESET INT1 NMI From dMAX or EMIF Interrupt INT2 Reserved INT3 Reserved INT4 RTI Interrupt 0 INT5 RTI Interrupts 1 2 3 and RTI Overflow Interrupts 0 and 1 INT6 UHPI CPU Interrupt fro
71. Chip Select Option 8 NO MIN MAX UNIT 25 t Required delay from SPIx SCS asserted at slave to first P B d SCSL SPO S SPIx CLK edge at slave Polarity 0 Phase 0 from SPIx_CLK falling 10 Polarity 0 Phase 1 Pat Required delay from final from SPIx falling 10 26 H edge before ns SPIx SCS is deasserted Polarity 1 Phase 0 from SPIx_CLK rising 0 5 P 10 Polarity 1 Phase 1 from SPIx_CLK rising Delay from master asserting SPIx SCS to slave drivin 27 tena Sesl_ soM S SOMI valid id d Pie ns Delay from master deasserting SPIx SCS to slave 3 stating 15 ns 28 lgs scsH SOM S SOMI 1 These parameters are in addition to the general timings for SPI slave modes Table 4 26 2 SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four slave clocking modes Submit Documentation Feedback Peripheral and Electrical Specifications 87 TMS320C6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 32 Additional SPI Slave Timings 5 Pin Option NO MIN MAX UNIT Required delay from SPIx SCS asserted at slave to first 25 lascsL edge at slave 3 ns
72. FGMCASP 1 register and Table 4 20 contains a description of the bits 31 8 Reserved 7 3 2 0 Reserved AMUTEIN1 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 27 CFGMCASP1 Register Bit Layout 0x4000 001C Table 4 20 CFGMCASP Register Bit Field Description 0x4000 001C RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 3 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 2 0 AMUTEIN1 0 R W AMUTEIN1 Selects the source of the input to the McASP1 mute input 000 Select the input to be a constant 0 001 Select the input from AXRO 7 SPI1_CLK 010 Select the input from AXRO 8 AXR1 5 SPI1_SOMI 011 Select the input from AXRO SJ AXR1 4 SPI1 SIMO 100 Select the input from AHCLKR2 101 Select the input from SPIO_SIMO 110 Select the input from SPIO SCS I2C1 SCL 111 Select the input from SPIO_ENA I2C1_SDA 74 Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 28 shows the bit layout of the CFGMCASP2 register and Table 4 21 contains a description of the bits 31 8 Reserved 7 3 2 0 Reserved AMUTEIN2 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 28 CFGMCASP2 Re
73. H 256 terminal plastic BGA ZDH 256 terminal Green plastic BGA RFP 144 pin PowerPAD Green TQFP DEVICE C672x DSP 6727 6726 6722 t The extended temperature A version devices may have different operating conditions than the commercial temperature devices For more details see the recommended operating conditions portion of this data sheet tBGA Ball Grid Array TQFP Thin Quad Flatpack The ZDH mechanical package designator represents the Green version of the GDH package For more detailed information see the Mechanical Data section of this document For actual device part numbers P Ns and ordering information see the TI website www ti com Figure 2 10 TMS320C672x DSP Device Nomenclature Submit Documentation Feedback Device Overview 27 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 www ti com 2 10 2 2 Documentation Support Extensive documentation supports the TMS320 DSP family of devices from product announcement through applications development The types of documentation available include data manuals such as this document with design specifications complete user s reference guides for all devices and tools technical briefs development support tools on line help and hardware and software applications The following is a brief descriptive list of support documentation specific to the C672x DSP dev
74. IO EM_D 1 51 R8 IO 5 EM_D 2 49 R7 IO N EM D 3 48 T6 IO 5 N EM Df 4 46 R6 IO EM D 5 45 T5 IO N EM D 6 43 R5 IO N EM_D 7 41 T4 IO N EMIF Data Bus Lower 16 Bits EM_D 8 66 R13 IO N EM DI 9 64 T12 IO N EM D 10 63 R12 IO N EM_D 11 61 T11 IO N EM D 12 59 R11 IO gt EM_D 13 58 R10 IO EM_D 14 56 T9 IO N EM_D 15 55 R9 IO EM D 16 UHPI HA 0 N7 IPD N EM D 17 UHPI HA 1 P6 IPD N EM D 18 UHPI HA 2 N6 IPD N EM_D 19 UHPI_HA 3 5 IPD N EM D 20 UHPI HA 4 P4 IPD N EM_D 21 UHPI_HA 5 P3 IPD N EM D 22 UHPI HA 6 N4 IPD N EM D 23 UHPI HA 7 R2 Ion IPD N EMIF Data Bus Upper 16 Bits IO or EM D 24 UHPI HA 8 P11 IPD N UHPI Address Input 1 EM D 25 UHPI HA 9 N11 IPD N EM_D 26 UHPI_HA 10 P10 IPD N EM_D 27 UHPI_HA 11 N10 IPD N EM_D 28 UHPI_HA 12 Pg IPD N EM_D 29 UHPI_HA 13 N9 IPD N EM D 30 UHPI HA 14 N8 IPD N EM D 31 UHPI HA 15 E P7 IPD N 22 Device Overview Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 2 12 Terminal Functions continued SIGNAL NAME
75. JANUARY 2007 4 14 2 SPI Peripheral Registers Description s Table 4 24 is a list of the SPI registers TEXAS INSTRUMENTS www ti com Table 4 24 SPIx Configuration Registers Hye PRESS ENS nese REGISTER NAME DESCRIPTION 0x4700 0000 0x4800 0000 SPIGCRO Global Control Register 0 0x4700 0004 0x4800 0004 SPIGCR1 Global Control Register 1 0x4700 0008 0x4800 0008 SPIINTO Interrupt Register 0x4700 000C 0x4800 000C SPILVL Interrupt Level Register 0x4700 0010 0x4800 0010 SPIFLG Flag Register 0x4700 0014 0x4800 0014 SPIPCO Pin Control Register 0 Pin Function 0x4700 0018 0x4800 0018 SPIPC1 Pin Control Register 1 Pin Direction 0x4700 001C 0x4800 001C SPIPC2 Pin Control Register 2 Pin Data In 0x4700 0020 0x4800 0020 SPIPC3 Pin Control Register 3 Pin Data Out 0x4700 0024 0x4800 0024 SPIPC4 Pin Control Register 4 Pin Data Set 0x4700 0028 0x4800 0028 SPIPC5 Pin Control Register 5 Pin Data Clear 0x4700 002C 0x4800 002C Reserved Reserved Do not write to this register 0x4700 0030 0x4800 0030 Reserved Reserved Do not write to this register 0x4700 0034 0x4800 0034 Reserved Reserved Do not write to this register 0x4700 0038 0x4800 0038 SPIDATO Shift Register 0 without format select 0x4700 003C 0x4800 003C SPIDAT1 Shift Register 1 with format select 0x4700 0040 0x4800 0040 SPIBUF Buffer Register 0x4700 0044 0x4800 0044 SPIEMU Emulation Register 0x47
76. LKIN 17 H2 Alternate clock input 3 3 V LVCMOS Input PLLHV 27 K2 PWR N PLL 3 3 V Supply Input requires external filter Device Reset RESET 14 G2 N Device reset pin Emulation JTAG Port TCK 35 1 IPU N Test Clock TMS 19 K3 IPU N Test Mode Select TDI 28 L1 IPU N Test Data In TDO 29 M2 OZ IPU N Test Data Out TRST 21 K4 IPD N Test Reset 32 1 IO IPU N Emulation Pin 0 34 1 IO IPU N Emulation Pin 1 Power Pins 256 Terminal GDH ZDH Package Core Supply CVpp E6 E7 E8 E9 E10 E11 G5 G12 H5 H12 J5 J12 K5 K12 M6 M7 M8 M9 M10 M11 IO Supply DVpp A2 A15 B1 B16 D4 D5 D12 D13 E4 E13 J14 M4 M13 N5 N12 P8 R1 R16 T2 T15 Ground Vss A1 A7 A10 A16 E5 E12 F5 F6 F7 F8 F9 F10 F11 F12 G1 G6 G7 G8 G9 G10 G11 G16 H3 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 J10 J11 K1 K6 K7 K8 K9 K10 K11 K16 L5 L6 L7 L8 L9 L10 L11 L12 M5 M12 T1 T7 T10 T16 Power Pins 144 Pin RFP Package Core Supply CVpp 8 16 20 33 44 53 57 65 77 85 90 101 123 128 132 IO Supply DVpp 10 31 42 50 60 68 73 81 92 103 112 125 136 Ground Vgs 1 6 13 15 18 26 30 36 40 47 54 62 69 72 78 82 87 95 99 106 109 114 118 124 129 133 140 Submit Documentation Feedback Device Overview 25 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digit
77. PH 565 pin state captured on rising edge of RESET 6 PINCAP14 AXRO 6 SPI1_ENA pin state captured on rising edge of RESET pin 5 PINCAP13 UHPI_HCS pin state captured on rising edge of RESET pin 4 PINCAP12 UHPI HDJ 0 pin state captured on rising edge of RESET pin 3 PINCAP11 EM D 16 UHPI HA 0 pin state captured on rising edge of RESET pin 2 PINCAP10 AFSXO pin state captured on rising edge of RESET pin 1 PINCAP9 AFSRO pin state captured on rising edge of RESET pin 0 PINCAP8 AXRO 0 pin state captured on rising edge of RESET pin 18 Device Overview Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 2 9 Pin Assignments 2 9 1 Pin Maps Figure 2 8 and Figure 2 9 show the pin assignments on the 256 terminal GDH ZDH package and the 144 pin RFP package respectively ids E m EM WE WE EM Df21 EM 0120 EM D 19 EM D 17 Vss lt o m m IUHPI HA 1 EM A 7 EM UHPI_ UHPL HD 28 29 Vss PLLHV TRST Vss UHPI EM AH ENLAGI HDD EM A 2 Vss HDDS ar EM 0 oscin oscouT OSCVpp CLKIN M HHWIL PU UHPL UHPL UHPI UHPI_ 0 CVpp CVpp CVpp
78. Polarity 0 Phase 0 from falling 0 51 10 Polarity 0 Phase 1 P41 Required delay from final from SPIx_CLK falling 10 26 gsPc scsH s 1 Polarity Phase 20 ns SPIx_SCS is deasserted 1 0 from SPIx_CLK rising 0 5 10 Polarity 1 Phase 1 from SPIx_CLK rising Delay from master asserting SPIx_SCS to slave drivin 27 tena SCSL_SoM s Spix SOMI valid 10 ns Delay from master deasserting SPIx SCS to slave 3 statin 28 tdis SCSH_SOMI S rend SOMI gx 9 10 ns Delay from master deasserting SPIx SCS to slave drivin 29 tena SosL ENAS ENA valid 5 15 me Polarity 0 Phase 0 from SPlx falling eae Delay from final clock receive Polarity 0 Phase 1 2P 15 30 lt edge on SPIx_CLK to slave from SPIx_CLK rising dis SPC_ENA S 3 stating or driving high Polarity 1 Phase 0 m SPIx_ENA 4 from SPIx_CLK rising ii Polarity 1 Phase 1 from SPIx_CLK falling 1 These parameters in addition to the general timings for SPI slave modes Table 4 26 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four slave clocking modes 4 SPIx is driven low after the transmission completes if the SPIINTO ENABLE HIGHZ bit is programmed to 0 Otherwise it is 3 stated If 3 stated an external pullup resistor should be used to provide a valid
79. RY 2007 4 12 Universal Host Port Interface UHPI C6727 Only 4 12 1 UHPI Device Specific Information The C672x DSP includes a flexible universal host port interface UHPI with more options than the host port interface on the C671x DSP The UHPI on the C672x DSP supports three major operating modes listed in Table 4 9 Table 4 9 UHPI Major Modes on C672x UHPI MAJOR MODE EXAMPLE FIGURE Multiplexed Host Address Data Half Word 16 Bit Mode Figure 4 15 Multiplexed Host Address Data Fullword 32 Bit Mode Figure 4 16 Non Multiplexed Host Address Data Fullword 32 Bit Mode Figure 4 17 In all modes the UHPI uses three select inputs UHPI HCS UHPI HDS 2 1 which are combined internally to produce the internal strobe signal HSTROBE The HSTROBE strobe signal is used in the UHPI to capture incoming address and control signals on its falling edge and write data on its rising edge The UHPI HCS signal also gates the deassertion of the UHPI HRDY signal externally UHPI HDS 2 UHPI HDS 1 Internal HSTROBE UHPI HCS UHPI HRDY Internal HRDY Figure 4 14 UHPI Strobe and Ready Interaction The two HPI control pins UHPI HCNTL 1 0 determine the type of access that the host will perform Note that only two of the four access types are supported in Non Multiplexed Host Address Data Fullword Mode Table 4 10 Access Types Selected by UHPI_HCNTL 1 0 MULTIPLEXED MULTIPLEXED UHPI
80. TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowl
81. U Table 2 9 describes the required boot pin settings at device reset for each bootmode Table 2 9 Required Boot Pin Settings at Device Reset BOOT MODE UHPI H SPIO SOMI SPIO SIMO SPIO CLK UHPI 0 BYTEAD FULL NMUX Parallel Flash 1 0 1 0 SPIO Master 1 0 0 1 SPIO Slave 1 0 1 1 I2C1 Master 1 1 0 1 I2C1 Slave 1 1 1 1 1 When UHPI HCS is 0 the state of the SPIO_SOMI SPIO SIMO and pins is copied into the specified bits in the CFGHPI register described in Table 4 12 16 Refer to the C9230C100 TMS320C672x Floating Point Digital Signal Processor ROM Data Manual literature number SPRS277 for details on supported bootmodes and their implementation Device Overview Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 2 6 shows the bit layout of the CFGPINO register and Table 2 10 contains a description of the bits 31 8 Reserved 7 6 5 4 3 2 1 0 PINCAP7 PINCAP6 PINCAP5 PINCAP4 PINCAP3 PINCAP2 PINCAP1 PINCAPO LEGEND R W Read Write R Read only n value after reset Figure 2 6 CFGPINO Register Bit Layout 0x4000 0000 Table 2 10 CFGPINO Register Bit Field Description 0x4000 0000 BIT NO NAME DESCRIPTION 31 8 Reserved Reads are indeterminate Only 05 shoul
82. _HD 31 17 UHPI UHPI HBE 3 0 UHPI HRW UHPI HDS 2 UHPI HDS 1 UHPI HCS UHPI HRDY AMUTE2 HINT A RDY INTERRUPT A Two host address lines or host GPIO if address lines are not available w Not used in this mode C Byte Enables active during reads and writes Some processors support a byte enable mode on their write enable pins D Only required if needed for strobe timing Not required if CS meets strobe timing requirements Figure 4 17 UHPI Non Multiplexed Host Address Data Fullword Mode CAUTION The EMIF data bus and UHPI HA inputs share the EM D 31 16 UHPI HA 15 0 pins When using Non Multiplexed mode make sure the EMIF does not drive EM D 31 16 otherwise a drive conflict with the external host MCU may result Normally the EMIF will begin to drive the EM D 31 16 lines immediately after it completes the SDRAM initialization sequence which occurs automatically after RESET is released To avoid drive conflict then the boot software must set CFGHPI NMUX to 11 before the EMIF drives EM D 31 16 Setting CFGHPI NMUX to 1 forces these pins to be input pins 58 Peripheral and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 4 12 2 UHPI Peripheral Registers Description s Table 4 11 is a list of the UHPI registers TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005
83. a Mode Fullword Non Multiplexed Address Data Mode Half Word Fullword EMIF 32 bit EMIF Data 16 bit EMIF Data PINS EM D 31 16 EM D 31 16 UHPI HA 15 0 UHPI HA 15 0 3 3 Peripheral Pin Multiplexing Control While Section 3 2 describes at a high level the most common pin multiplexing options the control of pin multiplexing is largely determined on an individual pin by pin basis Typically each peripheral that shares a particular pin has internal control registers to determine the pin function and whether it is an input or an output The C672x device determines whether a particular pin is an input or output based upon the following rules e The pin will be configured as an output if it is configured as an output in any of the peripherals sharing the pin e It is recommended that only one peripheral configure a given pin as an output If more than one peripheral does configure a particular pin as an output then the output value is controlled by the peripheral with highest priority for that pin The priorities for each pin are given in Table 3 5 e The value input on the pin is passed to all peripherals sharing the pin for input simultaneously Submit Documentation Feedback Device Configurations 31 5320 6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 TEXAS INSTRUMENTS www ti com Table 3 5 Priority of Control of Data Output on Mu
84. al Pin Multiplexing Control 4 Peripheral and Electrical Specifications 4 1 Electrical Specifications 4 2 Absolute Maximum 05 33 6 Contents Contents o Wy TEXAS INSTRUMENTS www ti com 4 8 Recommended Operating Conditions 33 4 4 Electrical Characteristics 34 4 5 Parameter Information 35 4 6 Timing Parameter Symbology 36 47 Power 37 4 87 38 4 9 Dual Data Movement Accelerator 29 4 10 External 44 4 11 External Memory Interface EMIF 45 4 12 Universal Host Port Interface UHPI C6727 Only 55 4 13 Multichannel Audio Serial Ports McASPO McASP1 and 8 2 68 4 14 Serial Peripheral Interface Ports SPIO SPI1 80 4 15 Inter Integrated Circuit Serial Ports 2 0 12C1 93 4 16 Real Time Interrupt RTI Timer With Digital 97 4 17 External Clock Input From Oscillator or CLKIN Pin 100 4 18 Phase Locked Loop PLL 102 Application Example 105 Revision History 106 Mechanical
85. al Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 HCS HAS 4 13 gt 16 4 Phi 16 gt 15 gt 15 37 gt is 4 37 4 14 gt 5 V L 4 3 3 1 9 2 1 5 2 38 em EN 4 6 gt UHPI HRDY X A SeeFigure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on may or not occur Figure 4 23 Multiplexed Read Timings With UHPI HAS Held High 66 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 UHPI_HCS UHPI HAS X X UHPI HRW um a A EX LK 4 16 gt 16 13 gt 15 gt 15 37 gt 24 13 4 55 37 lt 14 gt HSTROBE V lt gt 18 H gt 18 17 gt 17 UHPI 29 M 34 4 lt gt gt 5 M 34 id 5 UHPI HRDY A See Figure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incre
86. al Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 www ti com 2 10 Development 2 10 1 Development Support offers an extensive line of development tools for the TMS320C6000 DSP platform including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The following products support development of C6000 DSP based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Scalable Real Time Foundation Software DSP BIOS which provides the basic run time target software needed to support any DSP application Hardware Development Tools Extended Development System XDS Emulator supports C6000 DSP multiprocessor system debug EVM Evaluation Module For a complete listing of development support tools for the TMS320C6000 DSP platform visit the Texas Instruments web site on the Worldwide Web at http www ti com uniform resource locator URL For information on pricing and availability contact the nearest TI field sales office or authorized distributor 2 10 2 Device Support 2 10 2 1 Device and Development Support Tool Nomenclature 26 To designate the stages in the product development cycle assigns prefixes to the part numbers
87. anical Data Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 7 2 2 PowerPAD PCB Footprint Texas Instruments PowerPAD Thermally Enhanced Package Technical Brief literature number SLMAO002 should be consulted when creating PCB footprint for this device In general for proper thermal performance the thermal pad under the package body should be as large as possible However the soldermask opening for the PowerPAD should be sized to match the pad size on the 144 pin RFP package as illustrated in Figure 7 2 10000000000000000000000 000000000000000000000000 m Thermal Pad Copper Soldermask opening should be smaller and match should be as large as Possible the size of the thermal pad on the DSP Figure 7 2 Soldermask Opening Should Match Size of DSP Thermal Pad 7 3 Packaging Information The following packaging information reflects the most current released data available for the designated device s This data is subject to change without notice and without revision of this document On the 144 pin RFP package the actual size of the Thermal Pad is 5 4 mm x 5 4 mm Submit Documentation Feedback Mechanical Data 109 MECHANICAL DATA RFP S PQFP G144 PLASTIC QUAD FLATPACK Thermal Pad 27 17
88. ansfer table may contain up to eight transfer entries A transfer entry specifies details required by the dMAX controller to perform the transfer In case an event entry associates the event to an interrupt the event entry specifies which interrupt should be generated to the CPU in case the event arrives Prior to enabling events and triggering a transfer the event entry and transfer entry must be configured The event entry must specify type of transfer transfer details type of synchronization reload element size etc and should include a pointer to the transfer entry The transfer entry must specify source destination counts and indexes If an event is sorted in the high priority event group the event entry and transfer entry must be specified in the high priority Parameter RAM If an event is sorted in the low priority event group the event entry and transfer entry must be specified in the low priority parameter RAM The dMAX Event Flag Register DEFR captures up to 31 separate events therefore it is possible for events to occur simultaneously on the dMAX event inputs In such cases the event encoder resolves the order of processing This mechanism sorts simultaneous events and sets the priority of the events The dMAX controller can simultaneously process one event from each priority group Therefore the two highest priority events one from each group can be processed at the same time An event triggered dMAX transfer allows the
89. ansmit buffer register for serializer 13 0x4400 0238 XBUF14 1 Transmit buffer register for serializer 14 0x4400 023C XBUF15 1 Transmit buffer register for serializer 15 0x4400 0280 0x4500 0280 0x4600 0280 2 Receive buffer register for serializer 0 0x4400 0284 0x4500 0284 0x4600 0284 RBUF1 02 Receive buffer register for serializer 1 0x4400 0288 0x4500 0288 RBUF2 2 Receive buffer register for serializer 2 0x4400 028C 0x4500 028C RBUF3 2 Receive buffer register for serializer 3 0x4400 0290 0x4500 0290 RBUF4 02 Receive buffer register for serializer 4 0x4400 0294 0x4500 0294 RBUF5 Receive buffer register for serializer 5 0x4400 0298 RBUF6 2 Receive buffer register for serializer 6 0x4400 029C RBUF7 02 Receive buffer register for serializer 7 0x4400 02A0 RBUF8 2 Receive buffer register for serializer 8 0x4400 02A4 RBUF9 2 Receive buffer register for serializer 9 0x4400 02A8 RBUF10 Receive buffer register for serializer 10 0x4400 02AC 11 Receive buffer register for serializer 11 0x4400 02B0 RBUF12 Receive buffer register for serializer 12 0x4400 02B4 RBUF13 2 Receive buffer register for serializer 13 0x4400 02B8 RBUF14 Receive buffer register for serializer 14 0x4400 02BC RBUF15 Receive buffer register for serializer 15 2 72 Reads from XRBUF originate on peripheral configuration bus only when RBUSEL 1 in RFMT Peripheral and Electrical Specificatio
90. ariations of this format including time division multiplex TDM formats with up to 32 time slots Each McASP includes a transmit and receive section which may operate independently or synchronously furthermore each section includes its own flexible clock generator and extensive error checking logic As data passes through the McASP it can be realigned so that the fixed point representation used by the application code can be independent of the representation used by the external devices without requiring any CPU overhead to make the conversion The McASP is a configurable module and supports between 2 and 16 serial data pins It also has the option of supporting a Digital Interface Transmitter DIT mode with a full 384 bits of channel status and user data memory McASP2 is not available on the C6722 Inter Integrated Circuit Serial Ports I2CO I2C1 The C672x includes two inter integrated circuit I2C serial ports A typical application is to configure one I2C serial port as a slave to an external user interface microcontroller The other 2 serial port may then be used by the C672x DSP to control external peripheral devices such as a CODEC or network controller which are functionally peripherals of the DSP device The two 2 serial ports are pin multiplexed with the SPIO serial port Serial Peripheral Interface Ports SPIO SPI As in the case of the I2C serial ports the C672x DSP also includes two serial peripheral interfac
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92. ated terminology have been abbreviated as follows Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High cycle time period L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time transition time valid time pulse duration width x lt Unknown changing don t care level 36 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 7 Power Supplies For more information regarding Tl s power management products and suggested devices to power DSPs visit www ti com dsppower 4 7 1 Power Supply Sequencing This device does not require specific power up sequencing between the DVpp and CVpp voltage rails however there are some considerations that the system designer should take into account 1 Neither supply should be powered up for an extended period of time gt 1 second while the other supply is powered down 2 The I O buffers powered from the DVpj rail also require the CVpp rail to be powered up in order to be controlled therefore an I O pin that is supposed to be 3 stated by default may actually drive momentarily until the CVpp rail has powered up Systems should be evaluated to determine if there is a possibili
93. ation AHCLKX external AHCLKX input 7 5 Cycle time ACLKR external ACLKR input greater of 2P or 20 ns 3 Cycle time ACLKX external ACLKX input greater of 2P or 20 ns xs Pulse duration ACLKR external ACLKR input 10 4 tw ACKRX ns Pulse duration ACLKX external ACLKX input 10 Setup time AFSR input to ACLKR internal Setup time AFSX input to ACLKX internal Setup time AFSR input to ACLKR external input Setup time AFSX input to ACLKX external input Setup time AFSR input to ACLKR external output Setup time AFSX input to ACLKX external output Hold time AFSR input after ACLKR internal Hold time AFSX input after ACLKX internal Hold time AFSR input after ACLKR external input Hold time AFSX input after ACLKX external input Hold time AFSR input after ACLKR external output Hold time AFSX input after ACLKX external output Setup time AXRn input to ACLKR internal tsu axR ACKRX Setup time AXRn input to ACLKR external input 5 tsu AFRXC ACKRX ns 6 th ACKRX AFRX ns ns Setup time AXRn input to ACLKR external output Hold time AXRn input after ACLKR internal 8 th ACKRX AXR Hold time AXRn input after ACLKR external input Hold time AXRn input after ACLKR external output 1 ACLKX internal ACLKXCTL CLKXM 1 PDIR ACLKX 1 ACLKX external input ACLKXCTL CLKXM 0 PDIR ACLKX 0 ACLKX external output ACLKXCTL CLKXM 0 PDIR ACLKX
94. ay from EM_WAIT sampled deasserted on EM_CLK rising to 3 beginning of HOLD phase ii 34 ta EM WAITD HOLDJA Setup before end of STROBE phase if no extended wait states are 35 WAITA HOLDJA inserted by which EM WAIT must be sampled asserted on 4EQ ns EM CLK rising in order to add extended wait states 4 1 SYSCLKS EM period These parameters apply to memories selected by EM CS 2 in both normal and NAND modes 3 These parameters specify the number of EM CLK cycles of latency between EM WAIT being sampled at the device pin and the EMIF entering the HOLD phase However the asynchronous setup parameter 30 and hold time parameter 31 around each EM CLK edge must also be met in order to ensure the EM WAIT signal is correctly sampled 4 In Figure 4 13 it appears that there more than 4 cycles encompassed by parameter 35 However EM CLK cycles that are part of the extended wait period should not be counted the 4 EM CLK requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles Table 4 8 EMIF Asynchronous Interface Switching Characteristics NO PARAMETER MIN MAX UNIT 1 c EM Cycle time EMIF clock EM CLK 10 ns 2 tw EM_CLK Pulse width high or low EMIF clock EM_CLK 3 ns 17 tgis EM_CLKH EM_DHZ S Delay time EM_CLK rising to EM_D 31 0 3 stated 7 7 ns 1
95. cated AMUTEINx pins Instead they can select one of the pins listed in Table 4 19 Table 4 20 and Table 4 21 to use as a mute input Submit Documentation Feedback Peripheral and Electrical Specifications 69 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 13 1 MCcASP Peripheral Registers Description s TEXAS INSTRUMENTS www ti com Table 4 18 is a list of the McASP registers For more information about these registers see the TMS320C672x DSP Multichannel Audio Serial Port McASP Reference Guide literature number SPRU878 Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus McASPO BYTE ADDRESS McASP1 BYTE ADDRESS McASP2 BYTE ADDRESS REGISTER NAME DESCRIPTION Device Level Configuration Registers Controlling McASP 0x4000 0018 0x4000 001C 0x4000 0020 CFGMCASPx Selects the peripheral pin to be used as AMUTEINx cASP Internal Reg isters 0x4400 0000 0x4500 0000 0x4600 0000 PID Peripheral identification register 0x4400 0004 0x4500 0004 0x4600 0004 PWRDEMU Power down and emulation management register 0x4400 0010 0x4500 0010 0x4600 0010 PFUNC Pin function register 0x4400 0014 0x4500 0014 0x4600 0014 PDIR Pin direction register 0x4400 0018 0x4500 0018 0x4600 0018 PDOUT Pin data output register 0x4400 001C 0x4500 001C 0x4600 001C PDIN reads
96. citly enabled for security purposes CFGRTI 0x4000 0014 Selects the sources for the RTI Input Captures from among the six Table 4 37 McASP DMA events CFGMCASPO 0x4000 0018 Selects the peripheral pin to be used as AMUTEINO Table 4 19 CFGMCASP1 0x4000 001C Selects the peripheral pin to be used as AMUTEIN1 Table 4 20 CFGMCASP2 1 0x4000 0020 Selects the peripheral pin to be used as AMUTEIN2 Table 4 21 CFGBRIDGE 0x4000 0024 Controls reset of the bridge BR2 in Figure 2 4 This bridge must be reset Table 2 7 explicitly after any change to the PLL controller affecting SYSCLK1 and SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port CSP 1 CFGMCASP2 is reserved on the C6722 3 2 Peripheral Pin Multiplexing Options This section describes the options for configuring peripherals which share pins on the C672x DSP Table 3 2 lists the options for configuring the SPIO 2 0 and 2 1 peripheral pins Table 3 2 Options for Configuring SPIO 2 0 and 2 1 CONFIGURATION OPTION 1 OPTION 2 OPTION 3 PERIPHERAL SPIO 3 4 or 5 pin mode 3 pin mode disabled 12 0 disabled disabled enabled 1261 disabled enabled enabled PINS SPIO SOMI 2CO SDA SPIO SPIO_SOMI 2 0 SDA SPIO SIMO SPIO SIMO SPIO SIMO GPIO through SPIO_SIMO pin control SPIO CLK I2CO SCL SPIO CLK SPIO CLK 2 0 SCL SPIO SCS I2C1 SCL SPIO SCS 2 SCL 2 1 SCL 5 0 ENA I2C1 SDA SPIO_ENA 12C1_SDA 2 1 SDA
97. d be written to these bits 7 PINCAP7 5 0 SOMI I2CO SDA pin state captured on rising edge of RESET pin 6 PINCAP6 SPIO_SIMO pin state captured on rising edge of RESET pin 5 PINCAP5 SPIO CLK I2CO SCL pin state captured on rising edge of RESET pin 4 PINCAP4 SPIO SCS I2C1 SCL pin state captured on rising edge of RESET pin 3 PINCAP3 ENA I2C1 SDA pin state captured on rising edge of RESET pin 2 PINCAP2 AXRO 8 AXR1 5 SPI1_SOMI pin state captured on rising edge of RESET 1 PINCAP1 AXRO SJ AXR1 4 SPI 1 SIMO pin state captured on rising edge of RESET 0 PINCAPO AXRO 7 SPI1_CLK pin state captured on rising edge of RESET Submit Documentation Feedback Device Overview 17 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 2 7 shows the bit layout of the CFGPIN1 register and Table 2 11 contains a description of the bits 31 8 Reserved 7 6 5 4 3 2 1 0 PINCAP15 PINCAP14 PINCAP13 PINCAP12 11 10 PINCAP9 PINCAP8 LEGEND R W Read Write R Read only n value after reset Figure 2 7 CFGPIN1 Register Bit Layout 0x4000 0004 Table 2 11 CFGPIN1 Register Bit Field Description 0x4000 0004 BIT NO NAME DESCRIPTION 31 8 Reserved Reads are indeterminate Only 05 should be written to these bits 7 PINCAP15 AXRO B S
98. dback ki TEXAS INSTRUMENTS www ti com EM_CLK EM_CS 2 EM WE DQN 3 0 EM BA 1 0 EM A 12 0 EM D 31 0 m m m EM_RW EM_CLK EM CS 2 EM WE DQN 3 0 EM BA 1 0 EM A 12 0 EM D 31 0 m m m EM_RW TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors ASYNCHRONOUS WRITE WE STROBE MODE STROBE HOLD SPRS268E MAY 20 05 REVISED JANUARY 2007 le 21 22 22 14 22 BYTE WRITE STROBES 423 ADDRESS 4 23 ADDRESS Figure 4 11 Asynchronous Write WE Strobe Mode ASYNCHRONOUS WRITE SELECT STROBE MODE STROBE lt 32 32 Figure 4 12 Asynchronous Write Select Strobe Mode Submit Documentation Feedback Peripheral and Electrical Specifications 53 5320 6727 TMS320C6726 TMS320C6722 Wy TEXAS Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 SETUP STROBE EXTENDED WAIT STATES STROBE HOLD 35 geucik NAM 4 30 31 EM_WAIT 2 ASSERTED DEASSERTED X 1 1 k 33 1 e 33 gt 1 1 Figure 4 13 EM_WAIT Timing Requirements 54 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUA
99. des Set Through PCC Field of CSR CPU Register on C672x CPU CSR 7 5 CACHE MODE 000b Enable Deprecated Means direct mapped RAM on some C6000 devices 010b Enable Cache is enabled cache misses cause a line fill 011b Freeze Cache is enabled but contents are unchanged by misses 100b Bypass Forces cache misses cache contents frozen Other Values Reserved Not Supported CAUTION Although the reset value of CSR 7 5 PCC field is 000b the value may be modified during the boot process by the ROM code Refer to the appropriate ROM data sheet for more details However note that the cache may be disabled when control is actually passed to application code Therefore it may be necessary to write 010b to the PCC field to explicitly enable the cache at the start of application code CAUTION Changing the cache mode through CSR 7 5 does not invalidate any lines already in the cache To invalidate the cache after modifications are made to program space the control registers L1PISAR and L1PICR must be used Submit Documentation Feedback Device Overview 11 TMS320C6727 TMS320C6726 5320 6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 2 6 High Performance Crossbar Switch The C672x DSP includes a high performance crossbar switch that acts as a central hub between bus masters and targets Figure 2 4 illustrates th
100. down to zero otherwise the DSP will be reset This feature can be used to provide an added measure of robustness against a software failure If the application fails and ceases to write to the watchdog key the watchdog will respond by resetting the DSP and thereby restarting the application Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires however Capture 0 is still available for use by the application as well as the remaining RTI resources 4 16 2 HTl Digital Watchdog Registers Description s Table 4 36 is a list of the RTI registers Table 4 36 RTI Registers BYTE ADDRESS REGISTER NAME DESCRIPTION Device Level Configuration Registers Controlling RTI 0x4000 0014 CFGRTI Selects the sources for the RTI input captures from among the six McASP DMA event RTI Internal Registers 0x4200 0000 RTIGCTRL Global Control Register Starts stops the counters 0x4200 0004 Reserved Reserved bit 0x4200 0008 RTICAPCTRL Capture Control Controls the capture source for the counters 0x4200 000C RTICOMPCTRL Compare Control Controls the source for the compare registers 0x4200 0010 RTIFRCO Free Running Counter 0 Current value of free running counter 0 0x4200 0014 RTIUCO Up Counter 0 Current value of prescale counter 0 0x4200 0018 RTICPUCO Compare Up Counter 0 Compare value compared with prescale co
101. e SPI serial ports This allows one SPI port to be configured as a slave to control the DSP while the other SPI serial port is used by the DSP to control external peripherals The SPI ports support a basic 3 pin mode as well as optional 4 and 5 pin modes The optional pins include a slave chip select pin and an enable pin which implements handshaking automatically in hardware for maximum SPI throughput The SPIO port is pin multiplexed with the two 2 serial ports I2CO and I2C1 The SPI serial port is pin multiplexed with five of the serial data pins from McASPO McASP1 Submit Documentation Feedback TMS320C6727 TMS320C6726 TMS320C6722 DSPs 3 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 1 2 1 4 www ti com Real Time Interrupt Timer RTI The real time interrupt timer module includes Two 32 bit counter prescaler pairs e Two input captures tied to McASP direct memory access DMA events for sample rate measurement e Four compares with automatic update capability Digital Watchdog optional for enhanced system robustness Clock Generation PLL and OSC The C672x DSP includes an on chip oscillator that supports crystals in the range of 12 MHz to 25 MHz Alternatively the clock can be provided externally through the CLKIN pin The DSP includes a flexible software programmable phase locked loop PLL clock generat
102. e 7 pF CVpp Supply GDH CVpp 1 2 V 658 CPU clock 300 MHz CVpp 1 2 V 555 CPU clock 250 MHz DVpp Supply GDH DVpp 3 3 V 76 32 bit EMIF speed 100 MHz HA RFP DVpp 3 3 V 58 16 bit EMIF speed 100 MHz 1 Assumes the following conditions 25 C case temperature 60 CPU utilization EMIF at 50 utilization 100 MHz 50 writes 32 bits for GDH 16 bits for RFP 50 bit switching two 10 MHz SPI at 100 utilization 50 bit switching The actual current draw is highly application dependent For more details on core and activity refer to the TMS320C672x Power Consumption Summary Application Report literature number SPRAAA4 34 Peripheral and Electrical Specifications Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268bE MAY 2005 REVISED JANUARY 2007 4 5 Parameter Information 4 5 1 Parameter Information Device Specific Information Tester Pin Electronics Data Sheet Timing Reference Point 420 3 5 nH Output j Se es 20 500 see note Device Pin TT 4 0 pF gt lt 1 85 pF see note A The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transm
103. e connectivity of the crossbar switch Program Cache EMIF gt PLL RTI i2co 12 1 External Memory Controller T2 Memor Data CPU Program SERAN Master Slave Master Peripheral Configuration Bus Port Port Port ig BR4 SYSCLK1 SYSCLK1 SYSCLK3 SYSCLK3 McASP DMA Bus SYSCLK2 SYSCLK2 SYSCLK1 SYSCLK2 ig 6 _ Priority 1 2 3 4 dMAX MAXO Unit Master Port High Priority dMAX 1 Unit Master Port Second Priority Memory Controller DMP Data Read Write by CPU UHPI Master Interface External Host CPU Crossbar External UHPI Contig Host MCU Universal Host Port MAXO MAX1 Config Interface dMAX Figure 2 4 Block Diagram of Crossbar Switch As shown in Figure 2 4 there are five bus masters M1 Memory controller DMP for CPU data accesses to peripherals and EMIF M2 Memory controller PMP for program cache fills from the EMIF M3 dMAX HiMAX master port for high priority DMA accesses M4 dMAX LoMAX master port for lower priority DMA accesses M5 UHPI master port for an external MCU to access on chip and off chip memories 12 Device Overview Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 The five bus masters arbi
104. e on the opposing data path This allows each data path to source one cross path operand per cycle from the opposing register file On the C67x CPU this single cross path operand can be used by two functional units per cycle an improvement over the C67x CPU in which only one functional unit could use the cross path operand In addition the cross path register read s are not counted as part of the limit of four reads of the same register in a single cycle The C67x CPU executes all C67x instructions plus new floating point instructions to improve performance specifically during audio processing These new instructions are listed in Table 2 2 CPU speed is device dependent See Table 2 1 Device Overview Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 2 2 New Floating Point Instructions for C67x CPU FLOATING POINT INSTRUCTION OPERATION IMPROVES MPYSPDP SP x DP 2 DP Faster than MPYDP Improves high Q biquads bass management and FFT MPYSP2DP SP x SP 2 DP Faster than MPYDP Improves Long FIRs EQ ADDSP new to CPU S Unit SP SP gt SP ADDDP new to CPU S Unit DP DP gt DP Now up to four floating point add and subtract operations in parallel SUBSP new to CPU S Unit SP SP gt SP Improves FFT performance and symmetric FIR SUBDP new to
105. ed Stop Start Figure 4 38 I2C Receive Timings 26 24 k ry a EN E gt 23 21 lt 19 28 ke 2 4 6 gt 2 27 L lle 18 9 17 Stop Start Repeated Stop Start 96 Figure 4 39 2 Transmit Timings Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 16 Real Time Interrupt RTI Timer With Digital Watchdog 4 16 1 RTl Digital Watchdog Device Specific Information C672x includes an RTI timer module which is used to generate periodic interrupts This module also includes an optional digital watchdog feature Figure 4 40 contains a block diagram of the RTI module Compare 0 32 Bit Compare 1 32 Bit SYSCLK2 Counter 0 32 Bit 32 Bit Prescale Used by DSP BIOS Capture 0 32 Bit 32 Bit Prescale Compare 2 Counter 1 32 Bit 32 Bit 32 Bit Prescale Compare 3 2 Bi Capture 1 SEE 32 Bit 32 Bit Prescale Digital Watchdog 25 Bit Counter RESET Controlled by Internal Only CFGRTI Register RTI Interrupt 0 RTI Interrupt 1 RTI Interrupt 2 RTI Interrupt 3 1 2 Watchdog Key Register Transmit Receive 16 Bit Key DMA Events 1 2 Transmit Receive DMA Events Figure 4 40 RTI Timer Block Diagram
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107. eration and debugging tools Includes a brief description of the C6000 DSP architecture and code development flow includes C code examples and discusses optimization methods for the C code describes the structure of assembly code and includes examples and discusses optimizations for the assembly code and describes programming considerations for the C64x DSP TMS320C6000 Assembly Language Tools v6 0 Beta User s Guide Describes the assembly language tools assembler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C6000 platform of devices including the C64x and C67x generations NOTE The enhancements to tools release v5 3 to support the C672x devices are documented in the tools v6 0 documentation TMS320C6000 Optimizing Compiler v6 0 Beta User s Guide Describes the TMS320C6000 C compiler and the assembly optimizer This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS320C6000 platform of devices including the C64x and C67x generations The assembly optimizer helps you optimize your assembly code NOTE The enhancements to tools release v5 3 to support the C672x devices are documented in the tools v6 0 documentation Using IBIS Models for Timing Analysis Describes how to properly use IBIS models to attain accurate timing analysis for a given system The tools supp
108. ers including MAXO and MAX1 attempt to access same slave port concurrently the MAXO will be given the highest priority followed by MAX1 Event signals are connected to bits of the dMAX Event Register DER and the bits in the DER reflect the current state of the event signals An event is defined as a transition of the event signal The dMAX Event Flag Register DEFR can be programmed individually for each event signal to capture either low to high or high to low transitions of the bits in the DER event polarity is individually programmable An event is a synchronization signal that can be used 1 to either trigger dMAX to start a transfer or 2 to generate an interrupt to the CPU All the events are sorted into two groups low priority event group and high priority event group The High Priority Data Movement Accelerator MAXO HiMAX module is dedicated to serving requests coming from the high priority event group The Low Priority Data Movement Accelerator MAX1 LoMAX module is dedicated to serving requests coming from the low priority event group Each PaRAM contains two sections the event entry table section and the transfer entry table section An event entry describes an event type and associates the event to either one of transfer types or to an interrupt In case an event entry associates the event to one of the transfer types the event entry will contain a pointer to the specific transfer entry in the transfer entry table The tr
109. ers the event by creating appropriate transition edge on bit1 in DETR register 11 DETR 17 The CPU triggers the event by creating appropriate transition edge on bit17 in DETR register 12 UHPIINT UHPI CPU INT 13 SPIORX SPIO DMA RX REQ 14 SPHRX RX REQ 15 RTIREQ2 RTI DMA REQ 2 16 RTIREQ3 RTI DMA REQ 3 17 DETR 2 The CPU triggers the event by creating appropriate transition edge on bit2 in DETR register 18 DETR 18 The CPU triggers the event by creating appropriate transition edge on bit18 in DETR register 19 I2COXEVT I2C 0 Transmit Event 20 I2COREVT I2C 0 Receive Event 21 I2C1XEVT 2 1 Transmit Event 22 I2C1REVT I2C 1 Receive Event 23 DETR 3 The CPU triggers the event by creating appropriate transition edge on bit3 in DETR register 24 DETR 19 The CPU triggers the event by creating appropriate transition edge on bit19 in DETR register 25 Reserved 26 MCASPOERR AMUTEINO or McASPO TX INT or McASPO RX INT error on McASPO 27 MCASP1ERR AMUTEIN1 or McASP1 TX INT or McASP1 RX INT error on McASP1 28 MCASP2ERR AMUTEIN2 or McASP2 TX INT or McASP2 RX INT error on McASP2 29 OVLREQ 0 1 Error on RTI 30 DETR 20 The CPU triggers the event by creating appropriate transition edge on bit20 in DETR register 31 DETR 21 The CPU triggers the event by creating appropriate transition edge on bit21 in DETR register 42 Peripheral and Electrical Specifications Submit Documentation Feedback
110. eserved N A N A Reads are indeterminate Only Os should be written to these bits 0 CSPRST 1 R W Resets the CSP Bridge BR2 in Figure 2 4 1 Bridge Reset Asserted 0 Bridge Reset Released CAUTION The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1 and SYSCLK2 and must be released before any accesses to the CSP bridge occur from either the dMAX or the UHPI 14 Device Overview Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 2 7 Memory Map Summary TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A high level memory map of the C672x DSP appears in Table 2 8 The base address of each region is listed Any address past the end address must not be read or written The table also lists whether the regions are word addressable or byte and word addressable Table 2 8 C672x Memory Map DESCRIPTION BASE ADDRESS END ADDRESS BYTE OR WORD ADDRESSABLE Internal ROM Page 0 256K Bytes 0x0000 0000 0x0003 FFFF Byte and Word Internal ROM Page 1 128K Bytes 0x0004 0000 0x0005 FFFF Byte and Word Internal RAM Page 0 256K Bytes 0x1000 0000 0x1003 FFFF Byte and Word Memory and Cache Control Registers 0x2000 0000 0x2000 001F Word Only Emulation Control Registers Do Not Access 0x3000 0000 Ox3FFF FFFF Wo
111. g to EM D 31 0 invalid 1 15 ns 11 taEM CLKH EM RASV S Delay time EM CLK rising to EM RAS valid 7 7 ns 12 toh EM CLKH EM RAsIV S Output hold time EM CLK rising to EM RAS invalid 1 15 ns 13 taEM CASV S Delay time EM CLK rising to EM CAS valid 7 7 ns 14 toh EM CLKH EM CASIV s Output hold time EM CLK rising to EM CAS invalid 1 15 ns 15 taEM CLKH EM WEV S Delay time EM CLK rising to EM WE valid 7 7 ns 16 tohEM CLKH EM WEIV S Output hold time EM CLK rising to EM WE invalid 1 15 ns 17 tgis EM_CLKH EM_DHZ S Delay time EM_CLK rising to EM_D 31 0 3 stated 7 7 ns 18 tena EM_CLKH EM_DLZ S Output hold time EM CLK rising to EM_D 31 0 driving 1 15 ns Submit Documentation Feedback Peripheral and Electrical Specifications 49 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 uk Table 4 7 EMIF Asynchronous Interface Timing Requirements NO MIN MAX UNIT 28 lt Input setup time read data valid on EM D 31 0 before EM_CLK 5 su EM DV EM CLKH A rising 29 tniEM CLKH EM Input hold time read data valid D 31 0 after EM CLK rising 2 ns 30 tsuEM CLKH EM WAITV A Setup time EM WAIT valid before EM CLK rising edge 5 ns 31 _ WAITIVJA Hold time EM WAIT valid after EM CLK rising edge 0 ns 33 twEM WAITJA Pulse width of EM WAIT assertion and deassertion 2 5 ns Del
112. gister Bit Layout 0x4000 0020 Table 4 21 CFGMCASP2 Register Bit Field Description 0x4000 0020 RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 3 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 2 0 AMUTEIN2 0 R W AMUTEIN2 Selects the source of the input to the McASP2 mute input 000 Select the input to be a constant 0 001 Select the input from AXRO 7 SPI1 CLK 010 Select the input from AXRO 8 AXR1 5 SPI1_SOMI 011 Select the input from AXRO 9 AXR1 4 SPI1_SIMO 100 Select the input from AHCLKR2 101 Select the input from SPIO_SIMO 110 Select the input from SPIO SCS I2C1 SCL 111 Select the input from SPIO_ENA I2C1_SDA 1 CFGMCASP2 is reserved on the C6722 Submit Documentation Feedback Peripheral and Electrical Specifications 75 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 4 13 2 Electrical Data Timing 4 13 2 1 Multichannel Audio Serial Port McASP Timing Table 4 22 and Table 4 23 assume testing over recommended operating conditions see Figure 4 29 and Figure 4 30 Table 4 22 McASP Timing Requirements NO MIN UNIT Cycle time AHCLKR external AHCLKR input 20 1 c AHCKRX ns Cycle time AHCLKX external AHCLKX input 20 Pulse duration AHCLKR external AHCLKR input 4 5 2 tw AHCKRX ns Pulse dur
113. gnal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 92 www ti com SLAVE MODE 4 PIN WITH ENABLE SPIx CLK SPI SOMI SPI SIMO SLAVE MODE 4 PIN WITH CHIP SELECT 25 26 SPIx CLK FX dA X Km SO n 1 8 SPI SOMI SPI SIMO SPIx SCS um XS Sm SLAVE MODE 5 PIN 4 25 30 SPIx_CLK FX SPN 6 27 SO 1 gt 28 SP SOMI 50 0 1 SO n Ca BC 4 gt 29 5 0 5 1 Sl n 1 Sl n SPIx ENA DESELA J DESELA SPIx_SCS DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP Figure 4 36 SPI Timings Slave Mode 4 Pin and 5 Pin Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 15 Inter Integrated Circuit Serial Ports 2 0 2 1 4 15 1 2 Device Specific Information Having two I2C modules on the C672x simplifies system architecture since one module may be used by the DSP to control local peripherals ICs DACs ADCs etc while the other may be used to communicate with other controllers in a system or to implement a user interface Figure 4 37 is block diagram of the C672x 2 Module Each 2 port supports e Compatible with Philips I2C Specification Revision 2 1 January 2000 Fast Mode up to 400 Kbps no fail
114. he last bit input on SPIx_SIMO Measured from the termination of the write of new data to the SPI module as evidenced by new output data appearing on the SPIx_SOMI pin In analyzing throughput requirements additional internal bus cycles must be accounted for to allow data to be written to the SPI module by either the DSP CPU or the dMAX The final data bit will be held on the SPIx SOMI pin until the SPIDATO or SPIDAT1 register is written with new data Peripheral and Electrical Specifications Submit Documentation Feedback 4 TEXAS TMS320C6727 TMS320C6726 5320 6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 27 Additional SPI Master Timings 4 Pin Enable Option NO MIN MAX UNIT Polarity 0 Phase 0 to SPIx_CLK rising 15 Polarity 0 Phase 1 Delay from slave assertion of to a CLK rising 0 5tspcym 15 17 la ENA SPC M SPIx_ENA active to first ns 7 SPIx_CLK from master Polarity 1 Phase 0 15 to SPIx CLK falling Polarity 1 Phase 1 to SPlx falling 0 5 15 Polarity 0 Phase 0 0 5t from SPIx_CLK falling Ue SPOM Max delay for slave to deassert Polarity 0 Phase 1 0 18 t SPIx after final SPIx_CLK from SPIx falling P d SPC_ENA M edge to ensure master does not Polarity 1 Phase
115. ices SPRS277 SPRZ232 SPRU723 SPRU877 SPRU795 SPRAA78 SPRU711 SPRU718 SPRU719 SPRU878 SPRU879 SPRU733 C9230C100 TMS320C672x Floating Point Digital Signal Processor ROM Data Manual Describes the features of the C9230C100 TMS320C672x digital signal processor ROM TMS320C6727 TMS320C6726 TMS320C6722 Digital Signal Processors Silicon Errata Describes the known exceptions to the functional specifications for the TMS320C6727 TMS320C6726 and TMS320C6722 digital signal processors DSPs TMS320C672x DSP Peripherals Overview Reference Guide This document provides an overview and briefly describes the peripherals available on the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform TMS320C672x DSP Inter Integrated Circuit I2C Module Reference Guide This document describes the inter integrated circuit I2C module in the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform TMS320C672x DSP Dual Data Movement Accelerator dMAX Reference Guide This document provides an overview and describes the common operation of the data movement accelerator dMAX controller in the TMS320C672x digital signal processors DSPs of the TMS320C6000 DSP platform This document also describes operations and registers unique to the dMAX controller TMS320C6713 to TMS320C672x Migration This document describes the issues related to migrating from the TMS320C6713 to TMS320C672x digital
116. ion BASIC SDRAM READ OPERATION EM_CLK EM CS 0 EM WE DQN 3 0 EM BA 1 0 EM A 12 0 le 19 17 lt gt 20 EN lt lt 12 134 144 EM_CAS WAEEN 2 EM CLK Delay T EM D 31 0 EM RAS Figure 4 8 Basic SDRAM Read Operation Submit Documentation Feedback Peripheral and Electrical Specifications 51 TMS320C6727 TMS320C6726 TMS320C6722 K Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268bE MAY 2005 REVISED JANUARY 2007 ASYNCHRONOUS READ WE STROBE MODE SETUP STROBE HOLD TA EM CLK EM CS 2 EM WE DQN 3 0 EM BA 1 0 ADDRESS le 23 23 EM A 12 0 ADDRESS 17 READ DATA 2829 EM_D 31 0 1 25 1 25 18 gt EM RW Figure 4 9 Asynchronous Read WE Strobe Mode ASYNCHRONOUS READ SELECT STROBE MODE SETUP STROBE HOLD TA McK V 21 21 EMCS2 1 T _ 22 le 22 EM WE DQN 3 0 BYTE LANE ENABLES le 23 Le 23 EM BA 1 0 ADDRE EM A 12 0 ADDRESS READ DATA 26 29 EM DI31 0 25 25 4 18 T1 T EM_RW Figure 4 10 Asynchronous Read Select Strobe Mode 52 Peripheral and Electrical Specifications Submit Documentation Fee
117. ission line effect The transmission line is intended as a load only It is not neccessary to add or subtract the transmission line delay 2 ns longer from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of lt 4 Volts per nanosecond 4 V ns at the device pin Figure 4 1 Test Load Circuit for AC Timing Measurements 4 5 1 1 Signal Transition Levels All input and output timing parameters are referenced to 1 5 V for both 0 and 1 logic levels Vref 1 5 V Figure 4 2 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V MAX and Vj MIN for input clocks Vo and Voy MIN for output clocks Vret Vin MIN or MIN Vret MAX or MAX Figure 4 3 Rise and Fall Transition Time Voltage Reference Levels 4 5 1 2 Signal Transition Rates All timings are tested with an input edge rate of 4 Volts per nanosecond 4 V ns Submit Documentation Feedback Peripheral and Electrical Specifications 35 TMS320C6727 TMS320C6726 TMS320C6722 K Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 4 6 Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100 To shorten the symbols some of the pin names and other rel
118. ith the CLKIN pin Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not used must be tied to ground CVpp 1 2 V C5 OSCVpp OSCIN gt D X R lock Clock i Cg Rs Input From e e CLKIN OSCOUT 5 to PLL dr n OSCVss CLKIN gt gt ES On Chip 1 2 V Oscillator External 3 3 V LVCMOS Compatible Clock Source a b Figure 4 42 C672x Clock Input Options If the on chip oscillator is chosen then the recommended component values for Figure 4 42 a are listed in Table 4 38 Table 4 38 Recommended On Chip Oscillator Components FREQUENCY XTAL TYPE X C50 C Cs Rs 22 579 AT 49 KDS 1AF225796A 470 pF 470 pF 8 pF 8 pF 1MQ 02 22 579 SMD 49 KDS 1AS225796AG 470 pF 470 pF 8 pF 8 pF 1 MQ 02 24 576 AT 49 KDS 1AF245766AAA 470 pF 470 pF 8 pF 8 pF 1MQ 00 24 576 SMD 49 KDS 1AS245766AHA 470 pF 470 pF 8 pF 8 pF 1 02 1 Capacitors C5 and Cg are used to reduce oscillator jitter but are optional If Cg are not used then the node connecting capacitors C7 and Cg should be tied to OSCVss and OSCVpp should be tied to CVpp 100 Peripheral and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E
119. k AMUTE1 4 D2 Y McASP1 MUTE Output AHCLKR2 C14 IO IPD Y McASP2 Receive Master Clock ACLKR2 C13 IO IPD Y McASP2 Receive Bit Clock AFSR2 C12 IO IPD Y McASP2 Receive Frame Sync L R Clock ACLKX2 D11 IO IPD Y McASP2 Transmit Bit Clock AFSX2 C11 IO IPD Y McASP2 Transmit Frame Sync L R Clock AMUTE2 HINT D10 IPD Y McASP2 MUTE Output or UHPI Host Interrupt SPIO 2 0 and 12C1 Serial Port Pins SPIO_SOMI I2CO_SDA 111 B14 IO Y SPIO Data Pin Slave Out Master In or 12C0 Serial Data SPIO SIMO 110 B15 IO Y SPIO Data Pin Slave In Master Out SPIO CLK I2CO SCL 108 C16 IO Y SPIO Serial Clock or 2 0 Serial Clock SPIO SCS I2C1 SCL 107 C15 IO Y SPIO Slave Chip Select or I2C1 Serial Clock SPIO ENA I2C1 SDA 105 D16 IO Y SPIO Enable Ready or I2C1 Serial Data 4 2 is not available on the C6722 24 Device Overview Submit Documentation Feedback 4 TEXAS TMS320C6727 TMS320C6726 5320 6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Table 2 12 Terminal Functions continued SIGNAL NAME PULL GPIO DESCRIPTION Clocks OSCIN 23 J2 1 2 V Oscillator Input OSCOUT 24 J3 1 2 V Oscillator Output OSCVpp 25 J4 PWR N Oscillator 1 2 V Vpp tap point for filter only OSCVss 22 J1 PWR Oscillator Vss tap point for filter only C
120. k Enable EM_CLK 70 R14 EMIF Output Clock EM WE DOM 0 39 R4 Write Enable or Byte Enable for EM D 7 0 EM WE DON 1 67 T13 Write Enable or Byte Enable for EM_D 15 8 EM WE DOM 2 P13 IPU N Write Enable or Byte Enable for EM_D 23 16 EM WE DQN 3 R15 IPU N Write Enable or Byte Enable for EM_D 31 24 EM_OE 104 D15 SDRAM Asynchronous Output Enable EM_RW 102 E16 Asynchronous Memory Read not Write EM_WAIT _ 014 IPU N Asynchronous Wait Input Programmable Polarity or Interrupt NAND 1 TYPE column refers to pin direction in functional mode If a pin has more than one function with different directions the functions are separated with a slash 2 PULL column IPD Internal Pulldown resistor IPU Internal Pullup resistor 3 If the GPIO column is Y then in GPIO mode the pin is configurable as an IO unless otherwise marked Submit Documentation Feedback Device Overview 21 TMS320C6727 TMS320C6726 TMS320C6722 49 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 Table 2 12 Terminal Functions continued SIGNAL NAME RFP eat TYPE PULLO GPIO DESCRIPTION External Memory Interface EMIF Data Bus Universal Host Port Interface UHPI Address Bus Option EM D 0 52 T8
121. ki TEXAS INSTRUMENTS www ti com TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 1 TMS320C6727 TMS320C6726 TMS320C6722 DSPs 1 1 Features A C672x 32 64 Bit 300 MHz Floating Point DSPs Upgrades to C67x CPU From C67x DSP Generation 2X CPU Registers 64 General Purpose New Audio Specific Instructions Compatible With the C67x CPU Enhanced Memory System 256K Byte Unified Program Data RAM 384K Byte Unified Program Data ROM Single Cycle Data Access From CPU Large Program Cache 32K Byte Supports RAM ROM and External Memory External Memory Interface EMIF Supports 100 MHz SDRAM 16 or 32 Bit Asynchronous NOR Flash SRAM 8 16 or 32 Bit NAND Flash 8 or 16 Bit Enhanced I O System High Performance Crossbar Switch Dedicated McASP DMA Bus Deterministic Performance dMAX Dual Data Movement Accelerator Supports 16 Independent Channels Concurrent Processing of Two Transfer Requests 1 2 and 3 Dimensional Memory to Memory and Memory to Peripheral Data Transfers Circular Addressing Where the Size of a Circular Buffer FIFO is not Limited to 2 Table Based Multi Tap Delay Read and Write Transfers From To a Circular Buffer Three Multichannel Audio Serial Ports Transmit Receive Clocks up to 50 MHz Six Clock Zones and 16 Serial Data Pins Suppor
122. l registers In fact the default state for this interrupt is disabled Also interrupt generation always occurs on a rising edge of EM WAIT the polarity selection for wait state generation has no effect on the interrupt polarity The EM WAIT pin should remain asserted for at least two SYSCLK3 cycles to ensure that the edge is detected Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 TMS320C6726 5320 6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 11 External Memory Interface EMIF 4 11 1 EMIF Device Specific Information The C672x DSP includes an external memory interface EMIF for optional SDRAM NOR FLASH NAND FLASH or SRAM The key features of this EMIF are e One chip select EM CS 0 dedicated for x16 and x32 SDRAM x8 not supported e chip select EM CS 2 dedicated for x8 x16 or x32 NOR FLASH x8 x16 or x32 Asynchronous SRAM or x8 or x16 NAND FLASH Data bus width is 16 bits on the C6726 and C6722 and 32 bits on the C6727 e SDRAM burst length of 16 bytes e External Wait Input on the C6727 through EM_WAIT programmable active high or active low e External Wait pin functions as an interrupt for NAND Flash support Flash logic calculates ECC on blocks of up to 512 bytes ECC logic suitable for single bit errors Figure 4 5 and Figure 4 6 show typical examples of EMIF to memory hookup on the
123. ltiplexed Pins PIN FIRST PRIORITY SECOND PRIORITY THIRD PRIORITY SPIO_SOMI I2CO_SDA SPIO_SOMI 2 0 SDA SPIO CLK I2CO SCL SPIO 2 0 SCL SPIO_SCS I2C1_SCL SPI0_SCS 12 1_ SPIO_ENA I2C1_SDA SPIO_ENA I2C1 SDA AXRO 5 SPI1_SCS AXRO 5 SPH SCS AXRO 6 SPI1_ENA AXRO 6 SPH ENA AXRO 7 SPI1_CLK AXRO 7 SPI1_CLK AXRO SJAXR1 B SPM SOMI AXRO 8 1 5 SPI1_SOMI AXRO SAXR1 4SPM SIMO AXRO S 1 4 SPI1_SIMO AXRO 10 AXR1 3 AXRO 10 1 3 AXRO 11 AXR1 2 AXRO 11 1 2 AXRO 12 AXR1 1 AXRO 12 AXR1 1 AXRO 13 AXR1 0 AXRO 13 AXR1 0 AXRO 14 AXR2 1 AXRO 14 AXR2 1 AXRO 15 AXR2 0 AXRO 15 AXR2 0 AHCLKRO AHCLKR1 AHCLKRO AHCLKR1 AHCLKXO AHCLKX2 AHCLKXO AHCLKX2 AMUTE2 HINT AMUTE2 HINT HD 16 HHWIL HD 16 HHWIL EM D 81 16 J UHPI 15 0 7 EM DJ 31 16 Disabled if CFGHPI NMUX 1 UHPI_HA 15 0 Input Only 1 When using the UHPI in non multiplexed mode ensure EM D 31 16 are configured as inputs so that these pins may be used as UHPI HA 15 0 To ensure this you must set the CFGHPI NMUX bit to a 1 before the EMIF SDRAM initialization completes otherwise a drive conflict will occur The EMIF bus parking function drives the data bus in between accesses 32 Device Configurations Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6727 TMS320C6726 5320
124. m External Host MCU INT7 FIFO status notification from dMAX INT8 Transfer completion notification from dMAX INT9 dMAX event 0x2 specified in the dMAX interrupt event entry INT10 dMAX event 0x3 specified in the dMAX interrupt event entry INT11 dMAX event 0x4 specified in the dMAX interrupt event entry INT12 dMAX event 0x5 specified in the dMAX interrupt event entry INT13 dMAX event 0x6 specified in the dMAX interrupt event entry INT14 2 0 2 1 SPIO Interrupts INT15 dMAX event 0x7 specified in the dMAX interrupt event entry Submit Documentation Feedback Device Overview 9 TMS320C6727 TMS320C6726 TMS320C6722 49 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 2 4 www ti com Internal Program Data ROM and RAM The organization of program data ROM and RAM on C672x is simple and efficient ROM is organized as two 256 bit wide pages with four 64 bit wide banks RAM is organized as a single 256 bit wide page with eight 32 bit wide banks The internal memory organization is illustrated in Figure 2 2 ROM and Figure 2 3 RAM ROM Page 1 Base Address 0x0004 0000 ROM Page 0 Base Address Bank Bank Bank 0x0000 0000 1 2 3 Byte Figure 2 2 Program Data ROM Organization Byte RAM Page 0 lt Base Address Bank Bank Bank Bank Bank Bank 0x1000 0000 2 3 4 5 6 7 Figure 2 3 Program Data RAM Organization The C672
125. menting and the state of the FIFO transitions on UHPI_HRDY may or not occur Figure 4 24 Multiplexed Write Timings With UHPI HAS Held High Submit Documentation Feedback Peripheral and Electrical Specifications 67 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 TEXAS INSTRUMENTS www ti com 4 13 Multichannel Audio Serial Ports McASPO McASP1 and McASP2 The McASP serial port is specifically designed for multichannel audio applications Its key features are e Flexible clock and frame sync generation logic and on chip dividers e Up to sixteen transmit or receive data pins and serializers e Large number of serial data format options including TDM Frames with 2 to 32 time slots per frame periodic or 1 slot per frame burst Time slots of 8 12 16 20 24 28 and 32 bits First bit delay 0 1 or 2 clocks MSB or LSB first bit order Left or right aligned data words within time slots DIT Mode optional with 384 bit Channel Status and 384 bit User Data registers e Extensive error checking and mute generation logic e All unused pins GPIO capable Peripheral GIO Configuration Control Bus r7 DIT RAM 384 384 U I McASP DMA Bus Dedicated Figure 4 25 McASP Block Diagram 68 Peripheral and Electrical Specifications Receive Logic Clock Frame Generator State Machine Transmi
126. n though only the lower half word is used to transfer data This can be especially problematic for the UHPI HD 16 HHWIL pin which should be used as an input in this mode Therefore be sure to configure the upper half of the UHPI HD bus as general purpose l O pins Furthermore be sure to program the UHPI HD 16 function as a general purpose input to avoid a drive conflict with the external host MCU In this mode as well as the Multiplexed Host Address Data Fullword mode the UHPI can be made more secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB and CFGHPIAUMB registers See Table 4 13 and Table 4 14 The host is responsible for configuring the internal HPIA register whether or not it is being overridden by the device configuration registers CFGHPIAMSB and CFGHPIAUMB After the HPIA register has been set either a single or a group of autoincrementing accesses to HPID may be performed The UHPI HRDY adds wait states to extend the host MCU access until the C672x DSP has completed the desired operation The HINT signal is available for the DSP to interrupt the host MCU The UHPI also includes an interrupt to the DSP core from the host as part of the HPIC register DSP External Host MCU EM D 31 16 UHPI HA 15 0 NC UHPI HCNTI 1 0 UHPI HD 15 0 UHPI HD 16J HHWIL lt UHPI HD 31 17 NC or GPIO UHPI UHPI_HBE 1 0 UHPI_HRW 512 9 UHPI
127. ns Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 26 shows the bit layout of the CFGMCASPO register and Table 4 19 contains a description of the bits 31 8 Reserved 7 3 2 0 Reserved AMUTEINO R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 26 CFGMCASPO Register Bit Layout 0x4000 0018 Table 4 19 CFGMCASPO Register Bit Field Description 0x4000 0018 RESET READ BIT NO NAME VALUE WRITE DESCRIPTION 31 3 Reserved N A N A Reads are indeterminate Only Os should be written to these bits 2 0 AMUTEINO 0 R W AMUTEINO Selects the source of the input to the McASPO mute input 000 Select the input to be a constant 0 001 Select the input from AXRO 7 SPI1 CLK 010 Select the input from AXRO 8J AXR1 B SPI1 SOMI 011 Select the input from AXRO SJ AXR1 4 SPI1 SIMO 100 Select the input from AHCLKR2 101 Select the input from SPIO_SIMO 110 Select the input from SPIO SCS I2C1 SCL 111 Select the input from SPIO_ENA I2C1_SDA Submit Documentation Feedback Peripheral and Electrical Specifications 73 TMS320C6727 TMS320C6726 5320 6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 27 shows the bit layout of the C
128. of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320C6727GDH250 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Device Overview Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors
129. om any addressable memory space including internal memory peripherals and external memory The dMAX controller includes features such as the capability to perform three dimensional data transfers for advanced data sorting and the capability to manage a section of the memory as a circular buffer FIFO with delay tap based reading and writing of data The dMAX controller is capable of concurrently processing two transfer requests provided that they are to from different source destinations External Memory Interface EMIF for Flexibility and Expansion The external memory interface on the C672x supports a single bank of SDRAM and a single bank of asynchronous memory The EMIF data width is 16 bits wide on the C6726 and C6722 and 32 bits wide on the C6727 SDRAM support includes x16 and x32 SDRAM devices with 1 2 or 4 banks The C6726 and C6722 support SDRAM devices up to 128M bits 1 Throughout the remainder of the document TMS320C6727 or C6727 TMS320C6726 or C6726 and or TMS320C6722 or C6722 will be referred to as TMS320C672x or C672x 2 TMS320C6727 TMS320C6726 TMS320C6722 DSPs Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M bit and 512M bit devices Asynchronous memory support is typically used to boot from a parallel non multiplexed NOR flash device
130. onnected through via array to both bottom layer thermal pad and internal Vss plane 4 Top layer thermal pad is connected through via array to bottom layer thermal pad Mechanical Data 107 TMS320C6727 TMS320C6726 TMS320C6722 33 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 uk 7 2 Supplementary Information About the 144 Pin RFP PowerPAD Package 7 2 1 Standoff Height This section highlights a few important details about the 144 pin RFP PowerPAD package Texas Instruments PowerPAD Thermally Enhanced Package Technical Brief literature number SLMAO02 should be consulted before designing a PCB for this device As illustrated in Figure 7 1 the standoff height specification for this device between 0 050 mm and 0 150 mm is measured from the seating plane established by the three lowest package pins to the lowest point on the package body Due to warpage the lowest point on the package body is located in the center of the package at the exposed thermal pad Using this definition of standoff height provides the correct result for determining the correct solder paste thickness According to Tl s PowerPAD Thermally Enhanced Package Technical Brief literature number SLMAO02 the recommended range of solder paste thickness for this package is between 0 152 mm and 0 178 mm Standoff Height Figure 7 1 Standoff Height Measurement on 144 Pin RFP Package 108 Mech
131. or Three different clock domains SYSCLK1 SYSCLK2 and SYSCLK3 are generated by dividing down the PLL output SYSCLK1 is the clock used by the CPU memory controller and memories SYSCLK2 is used by the peripheral subsystem and dMAX SYSCLKS3 is used exclusively for the EMIF Device Compatibility The TMS320C672x floating point digital signal processors are based on the new C67x CPU This core is code compatible with the C67x CPU core used on the TMS320C671x DSPs but with significant enhancements including additional floating point instructions See Section 2 2 TMS320C6727 TMS320C6726 TMS320C6722 DSPs Submit Documentation Feedback Texas TMS320C6727 TMS320C6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors www ti com SPRS268E MAY 2005 REVISED JANUARY 2007 1 3 Functional Block Diagram Figure 1 1 shows the functional block diagram of the C672x device Program Data JTAG EMU RAM 256K Bytes McASPO 32 16 Serializers C67x CPU Program Data 32 D2 Memory ROM 0 res Controller 256K Bytes o 32 5 McASP1 32 6 Serializers Program INT Fetch Program Data a ROM Page1 5 32 McASP2 129K Bytes 5 2 Serializers 32 DIT Programi 32 SPI1 Cache 32K Bytes 32 SPIO 32 12 0 32 12C1 High Performance Crossbar Switch Interrupts MAXO CONTROL MAX1 Events Out In dMAX Peripheral Configuration Bus 32 RTI
132. ort documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE For a complete listing of C6 000 DSP latest documentation visit the Texas Instruments web site the Worldwide Web at http www ti com uniform resource locator URL Submit Documentation Feedback Device Overview 29 TMS320C6727 TMS320C6726 TMS320C6722 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 7 3 Device Configurations 3 1 Device Configuration Registers The C672x DSP includes several device level configuration registers which are listed in Table 3 1 These registers need to be programmed as part of the device initialization procedure See Section 3 2 Table 3 1 Device Level Configuration Registers REGISTER NAME BYTE ADDRESS DESCRIPTION DEFINED CFGPINO 0x4000 0000 Captures values of eight pins on rising edge of RESET pin Table 2 10 CFGPIN1 0x4000 0004 Captures values of eight pins on rising edge of RESET pin Table 2 11 CFGHPI 0x4000 0008 Controls enable of UHPI and selection of its operating mode Table 4 12 CFGHPIAMSB 0x4000 000C Controls upper byte of UHPI address into C672x address space in Table 4 13 Non Multiplexed Mode or if explicitly enabled for security purposes CFGHPIAUMB 0x4000 0010 Controls upper middle byte of UHPI address into C672x address space Table 4 14 in Non Multiplexed Mode or if expli
133. our sources are supported Two 64 bit data accesses from the C67x CPU e One 256 bit program fetch from the core and program cache e One 32 bit data access from the peripheral system either dMAX or UHPI The large 32K byte program cache translates to a high hit rate for most applications This prevents most program data access conflicts to the on chip memory It also enables effective program execution from an off chip memory such as an SDRAM High Performance Crossbar Switch A high performance crossbar switch acts as a central hub between the different bus masters CPU dMAX UHPI and different targets peripherals and memory The crossbar is partially connected some connections are not supported for example UHPI to peripheral connections Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target When a conflict does occur the arbitration is a simple and deterministic fixed priority scheme The dMAX is given highest priority since it is responsible for the most time critical I O transfers followed next by the UHPI and finally by the CPU dMAX Dual Data Movement Accelerator The dMAX is a module designed to perform Data Movement Acceleration The Data Movement Accelerator dMAX controller handles user programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs The dMAX allows movement of data to fr
134. parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of
135. pins but the dMAX can be used in combination with McASP AMUTEIN signal to provide external interrupt capability There is a multiplexer for each McASP controlled by the CFGMCASP0 1 2 registers which allows the AMUTEIN input for that McASP to be sourced from one of seven I O pins on the DSP Once a pin is configured as an AMUTEIN source a very short pulse two SYSCLK2 cycles or more on that pin will generate an event to the dMAX This event can trigger the dMAX to generate a CPU interrupt by programming the assoicated Event Entry There are a few additional points to consider when using the AMUTEIN signal to enable external interrupts as described above The I O pin selected by the CFGMCASP0 1 2 registers must be configured as a general purpose input pin within the associated peripheral Also the AMUTEIN signal should be disabled within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active This can be done by clearing the INEN bit of the AMUTE register inside the McASP Finally AMUTEIN events are logically ORed with the McASP transmit and receive error events within the dMAX therefore the ISR that processes the dMAX interrupt generated by these events must discern the source of the event The EMIF EM WAIT pin has the ability to generate an NMI INT1 based upon a rising edge on the EM WAIT pin Note that while this interrupt is connected to the CPU NMI non maskable interrupt it is actually maskable through the EMIF contro
136. r I IO LaLa lt lt lt amp lt lt lt lt lt mn m 8 l ls on22222o0222022222220222202220 22227 gt gt gt et 8 EE n ED n HR pn t Vss Vss SPIO SIMO EM CKE SPIO_SOMI I2CO_SDA EM_CLK DVpp Vss AXRO 0 DVpp Vss EM WE DOM 1 AXRO 1 EM DI8 AXRO 2 CVpp AXRO 3 EM 0 9 Vss EM D 10 AXRO 4 Vss AXRO S SP SCS EM D 11 AXRO G SPI1 ENA DVpp AXRO 7 SPI EM D 12 CVpp EM D 13 Vss CVpp DVpp EM D 14 AXRO S AXR1 5 SPI1 SOMI EM D 15 AXRO S AXR1 4 SPI1 SIMO Vss CVpp CVpp Vss EM 0 0 AXRO 10J AXR1 3 EM AXRO 11 AXR1 2 DVpp CVpp EM D 2 Ves EM D 3 AXRO 12J AXR1 1 Vss AXRO 13 AXR1 0 EM 0 4 DVpp EM D 5 AXRO 14J AXR2 1 CVpp AXRO 15 AXR2 0 EM D 6 ACLKRO DVpp Vss EM 0 7 AFSRO Vss ACLKXO EM WE DQM 0 AHCLKRO AHCLKR1 EM WE AFSXO EM CAS CVpp TRST r 21 OSCVsg 22 OSCIN 23 OSCOUT r 24 Vss 26 PLLHV 27 TDI TDO 29 AMUTEO OSCVpp 25 AHCLKXO AHCLKX2 2 A Actual size of Thermal Pad is 5 4 mm x 5 4 mm See Section 7 3 Figure 2 9 144 Low Profile Quad Flatpack RFP Suffix Top View 20 Device Overview Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 2 9 2 Terminal Functions TMS320C
137. rd Only Device Configuration Registers 0x4000 0000 0x4000 0083 Word Only PLL Control Registers 0x4100 0000 0x4100 015F Word Only Real time Interrupt RTI Control Registers 0x4200 0000 0x4200 00A3 Word Only Universal Host Port Interface UHPI Registers 0x4300 0000 0x4300 0043 Word Only McASPO Control Registers 0x4400 0000 0x4400 02BF Word Only McASP1 Control Registers 0x4500 0000 0x4500 02BF Word Only McASP2 Control Registers 0x4600 0000 0x4600 02BF Word Only SPIO Control Registers 0x4700 0000 0x4700 007F Word Only SPI1 Control Registers 0x4800 0000 0x4800 007F Word Only 12 0 Control Registers 0x4900 0000 0x4900 007F Word Only I2C1 Control Registers 0x4A00 0000 0x4A00 007F Word Only DMA Port any address in this range 0x5400 0000 Ox54FF FFFF Word Only McASP1 DMA Port any address in this range 0x5500 0000 Ox55FF FFFF Word Only McASP2 DMA Port any address in this range 0x5600 0000 Ox56FF FFFF Word Only dMAX Control Registers 0x6000 0000 0x6000 008F Word Only HiMAX Event Entry Table 0x6100 8000 0x6100 807F Byte and Word Reserved 0x6100 8080 0x6100 809F HiMAX Transfer Entry Table 0x6100 80A0 0x6100 81FF Byte and Word MAX1 LoMAX Event Entry Table 0x6200 8000 0x6200 807F Byte and Word Reserved 0x6200 8080 0x6200 809F MAX1 LoMAX Transfer Entry Table 0x6200 80A0 0x6200 81FF Byte and Word External SDRAM space on EMIF 0x8000 0000 O
138. rement 10 2H 4 20 Delay time DS low to UHPI_HRDY 6 tapsi HRDYL low Case 2 HPID read with ns auto increment and read FIFO 10 2H 2009 initialy empty 7 ta HDv HRDYL Delay time HD valid to HRDY low 0 ns Case 1 HPIA write 5 2H 2009 Delay time DS high to C 2 HPID read with 34 t ey ume ase 2 read wit ns eer HEY UHPI_HRDY low auto increment and read FIFO 5 2H 200 initially empty Delay time DS low to UHPI_HRDY low for HPIA write and FIFO not 35 ta DSL HRDYL nnd 40 2H 20 ns 36 la HASL HRDYH Delay time UHPI HAS low to UHPI high 12 ns 1 0 5 SYSCLK2 period 2 DS refers to HSTROBE HAD refers to UHPI HCNTL 0 UHPI HCNTL 1 HHWIL and UHPI HRW 3 Max delay is a best case assuming no delays due to resource conflicts between UHPI and dMAX or CPU UHPI HRDY should always be used to indicate when an access is complete instead of relying on these parameters Submit Documentation Feedback Peripheral and Electrical Specifications 63 5320 6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 udi Read Write UHPI HCS 37 37 14 gt 13 13 gt UHPI_HDSx A ma K 15 15 qe o k 16 16 UHPI UHPI_HA 15 0 Vaid X X vaia X 4 3 2 UHPI_HD 31 0
139. rol by the register bit field SPIDELAY T2CDELAY 4 0 7 If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx ENA 8 In the case where the master SPI is ready with new data before SPIx SCS assertion 9 This delay can be increased under software control by the register bit SPIDELAY C2TDELAY 4 0 10 If SPIx_ENA was initially deasserted high and SPIx CLK is delayed 86 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Table 4 30 Additional SPI Slave Timings 4 Pin Enable Option NO MIN MAX UNIT Polarity 0 Phase 0 _ from SPIx_CLK falling P 10 3P 15 Polarity 0 Phase 1 Delay from final from CLK falling O 5tyspcym 10 O 5tyspq 3P 15 24 tyspc_enaHys SPIx_CLK edge to slave Bae Er deasserting SPIx olarity 1 Phase 0 _ from SPIx_CLK rising 10 15 Polarity 1 Phase 1 O StcisPc M 10 0 5 5 3P 15 from SPIx_CLK rising 1 These parameters are in addition to the general timings for SPI slave modes Table 4 26 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four slave clocking modes Table 4 31 Additional SPI Slave Timings 4 Pin
140. s WSIMCCSPEUM edge on SPIx Polarity 1 Phase 0 to SPIx_CLK falling Polarity 1 Phase 1 to SPIx_CLK falling O 5tespoym 4P Polarity 0 Phase 0 15 from SPIx CLK rising Polarity 0 Phase 1 15 Delay subsequent bits from SPIx_CLK falling 5 la SPC SIMO M valid on SPIx SIMO after 7 ns transmit edge of SPIx CLK Polarity 1 Phase 0 15 from SPIx CLK falling Polarity 1 Phase 1 15 from SPIx CLK rising Polarity 0 Phase 0 _ from 5 falling 0 10 Output hold time Polarity 0 Phase 1 SP SIMO valid after from SPlx rising OStaspcj 7 10 oh SPC_SIMO M receive edge of SPIXCLK Polarity 1 Phase 0 ns except for final bit from SPlx rising 0 5tespcym 10 Polarity 1 Phase 1 _ from falling 0 5tspqym 10 Polarity 0 Phase 0 to SPlx falling Polarity 0 Phase 1 Input Setup Time to SPI CLK rising earn tS 7 tsusOMI SPCM SPIx SOMI valid before ns E receive edge of Polarity 1 Phase 0 E to SPIx_CLK rising Bins Polarity 1 Phase 1 to SPIx_CLK falling oer de Polarity 0 Phase 0 from falling Polarity 0 Phase 1 Input Hold Time from SPIx_CLK rising 0 5P 5 8 SOMI M SPIx SOMI valid after Polarit 1 Ph 0 ns E receive edge of SPIx olarity 1 Phase 0 from SPIx CLK rising Polarity 1 Phase 1
141. s distributed so that only one bridge crossing is necessary for PMP accesses The effect is that PMP has 5th priority to the EMIF but lower latency A bus bridge is needed between masters and targets which run at different clock rates The bus bridge contains a small FIFO to allow the bridge to accept an incoming burst access at one clock rate and pass it through the bridge to a target running at a different rate Table 2 6 lists the FIFO properties of the four bridges BR1 BR2 BR3 and BR4 in Figure 2 4 Table 2 6 Bus Bridges LABEL BRIDGE DESCRIPTION MASTER CLOCK TARGET CLOCK BR1 DMP Bridge to peripherals MAX EMIF SYSCLK1 SYSCLK2 BR2 dMAX UHPI to ROM RAM CSP SYSCLK2 SYSCLK1 BR3 PMP to EMIF SYSCLK1 SYSCLK3 BR4 CPU UHPI and dMAX to EMIF SYSCLK2 SYSCLK3 Submit Documentation Feedback Device Overview 13 TMS320C6727 TMS320C6726 TMS320C6722 K Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 2 5 shows the bit layout of the device level bridge control register CFGBRIDGE and Table 2 7 contains a description of the bits 31 16 Reserved 15 1 0 Reserved CSPRST R W 1 LEGEND R W Read Write R Read only n value after reset Figure 2 5 CFGBRIDGE Register Bit Layout 0x4000 0024 Table 2 7 CFGBRIDGE Register Bit Field Description 0x4000 0024 BIT NO NAME RESET VALUE READ WRITE DESCRIPTION 31 1 R
142. t 32 bit instructions to the eight functional units during every clock cycle The variable length execute packets are a key memory saving feature distinguishing the C67x CPU from other VLIW architectures Additionally execute packets can now span fetch packets providing a code size improvement over the C67x CPU core The CPU features two data paths shown in Figure 2 1 each composed of four functional units D M S and L and a register file The D unit in each data path is a data addressing unit that is responsible for all data transfers between the register files and the memory The M functional units are dedicated for multiplies and the S and L functional units perform a general set of arithmetic logical and branch functions All instructions operate on registers as opposed to data in memory but results stored in the 32 bit registers can be subsequently moved to memory as bytes half words or words Data Path A Data Path B Figure 2 1 CPU Data Paths The register file in each data path contains 32 32 bit registers for a total of 64 general purpose registers This doubles the number of registers found on the C67x CPU core allowing the optimizing C compiler to pipeline more complex loops by decreasing register pressure significantly The four functional units in each data path of the CPU can freely share the 32 registers belonging to that data path Each data path also features a single cross path connected to the register fil
143. t Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 4 11 3 EMIF Electrical Data Timing Table 4 5 through Table 4 8 assume testing over recommended operating conditions see Figure 4 7 through Figure 4 13 Table 4 5 EMIF SDRAM Interface Timing Requirements NO MIN MAX UNIT 19 tsuEM DV EM CLKH Input setup time read data valid on D 31 0 before EM CLK rising 3 ns 20 th EM_CLKH EM_DIV Input hold time read data valid on D 31 0 after EM CLK rising 1 9 ns Table 4 6 EMIF SDRAM Interface Switching Characteristics NO PARAMETER MIN MAX UNIT 1 Cycle time EMIF clock EM CLK 10 ns 2 tw EM_CLK Pulse width EMIF clock EM_CLK high or low 3 ns 3 CLKH EM CSV S Delay time CLK rising to EM CS O0 valid 7 7 ns 4 toh EM CLKH EM CSIV S Output hold time EM CLK rising to EM CS 0 invalid 1 15 ns 5 taEM CLKH EM WE DQMV S Delay time EM CLK rising to EM WE DQN 3 0 valid 77 ns 6 lonEM CLKH EM WE DOMIV S Output hold time EM CLK rising to EM WE DQNM 3 0 invalid 1 15 ns 7 ta EM_CLKH EM_AV S Delay time EM CLK rising to EM A 12 0 and EM 1 0 valid 77 ns Output hold time EM CLK rising to EM A 12 0 and EM BA 1 0 8 tonEM CLKH EM AIV S invalid 1 15 ns 9 ta EM_CLKH EM_DV S Delay time EM_CLK rising to EM_D 31 0 valid 7 7 ns 10 toh EM_CLKH EM_DIV S Output hold time EM CLK risin
144. t Logic Clock Frame Generator State Machine Formatter Receive Formatter Serializer y McASPx x 0 1 2 Pins AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx 0 AXRx 1 AXRx y Function Receive Master Clock Receive Bit Clock Receive Left Right Clock or Frame Sync The McASPs DO NOT have dedicated AMUTEINx pins Transmit Left Right Clock or Frame Sync Transmit Bit Clock Transmit Master Clock Transmit Receive Serial Data Pin Transmit Receive Serial Data Pin Transmit Receive Serial Data Pin Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 The three McASPs on C672x have different configurations see Table 4 17 NOTE McASP2 is not available on the C6722 Table 4 17 McASP Configurations on C672x DSP McASP DIT CLOCK PINS DATA PINS COMMENTS McASPO No AHCLKXO AHCLKX2 AFSXO Up to 16 AHCLKX0 AHCLKX2 share pin AHCLKRO AHCLKR1 ACLKRO AFSRO AHCLKRO AHCLKR 1 share pin McASP1 No AHCLKX1 ACLKX1 AFSX1 ACLKR1 AFSR1 Up to 6 AHCLKRO AHCLKR 1 share pin McASP2 Yes ACLKX2 AFSX2 AHCLKR2 ACLKR2 AFSR2 Up to 2 Full functionality on C6727 On C6726 Only available on the C6727 functions only as DIT since only AHCLKX0 AHCLKX2 is available Not available on the C6722 NOTE The McASPs do not have dedi
145. tion I2Cx ow s weet 3 Fast Mode 13 j 5 t Pulse duration I2Cx SCL high Standard Mode ulse duration I2Cx i s Fast Mode 0 6 6 1 Setup ti 2 SDA bef 2 SCL high Standard Mode 220 etup time I2Cx efore I2Cx i ns su SDA SCLH p ES 9 Fast Mode 100 7 1 Hold ti I2Cx SDA after 2 SCL I pode J old time 12Cx after 2 ow S E Fast Mode 0 09 i P l s duration PCL SD hidh Standard Mode 4 7 ulse duration I2Cx i S Fast Mode 13 d ae Standard Mode 1000 9 1 50 Rise time 2 SDA ns Fast Mode 20 0 1C 300 mM Standard Mode 1000 10 Rise time 2 SCL ns Fast Mode 20 0 1C 300 Standard Mode 300 11 SDA Fall time 2 SDA ns Fast Mode 20 0 10 300 Standard Mode 300 12 6 Fall time 12Cx_SCL ns Fast Mode 20 0 1C 300 aa Setup time I2Cx_SCL high before 2 _ Standard Mode 4 ae ees high Fast Mode 0 6 44 ike tb d Standard Mode N A ulse duration spike must be suppresse ns uad Fast Mode 0 50 Standard Mode 400 15 Cp Capacitive load for each bus line pF Fast Mode 400 Table 4 35 I2C Switching Characteristics NO PARAMETER MIN MAX UNIT 6 i Gudea lack SCL Standard Mode 10 cle time I2Cx S eet y Fast Mode 25 17 Setup time I2Cx_SCL high before 2 6 Standard Mode 4 7 Su SCLH SDAL low Fast Mode 0 6 5 Standard Mode 4 18 th SDAL SCLL Hold time 2 SCL low after 2 SDA low us
146. trate for five different target groups T1 On chip memories through the CPU Slave Port CSP T2 Memories on the external memory interface EMIF T3 Peripheral registers through the peripheral configuration bus T4 McASP serializers through the dedicated McASP DMA bus 5 dMAX registers The crossbar switch supports parallel accesses from different bus masters to different targets When two or more bus masters contend for the same target beginning at the same cycle then the highest priority master is given ownership of the target while the other master s are stalled However once ownership of the target is given to a bus master it is allowed to complete its access before ownership is arbitrated again Following are two examples Example 1 Simultaneous accesses without conflict dMAX HiMAX accesses McASP Data Port for transfer of audio data e dMAX LoMAX accesses SPI port for control processing e UHPI accesses internal RAM through the CSP e CPU fills program cache from Example 2 Conflict over a shared resource e dMAX accesses RTI port for McASP sample rate measurement dMAX LoMAX accesses SPI port for control processing In Example 2 both masters contend for the same target the peripheral configuration bus The HiMAX access will be given priority over the LoMAX access The master priority is illustrated in Figure 2 4 by the numbers 1 through 4 in the bus arbiter symbols Note that the EMIF arbitration i
147. ts TDM 125 and Similar Formats DIT Capable McASP2 Universal Host Port Interface 32 Bit Wide Data Bus for High Bandwidth Muxed and Non Muxed Address and Data Two 10 MHz SPI Ports With 3 4 and 5 Pin Options Two Inter Integrated Circuit I2C Ports Real Time Interrupt Counter Watchdog Oscillator and Software Controlled PLL Applications Professional Audio e Mixers Effects Boxes Audio Synthesis Instrument Amp Modeling Audio Conferencing Audio Broadcast Audio Encoder Emerging Audio Applications Biometrics Medical Industrial Commercial or Extended Temperature 144 Pin 0 5 mm PowerPAD Thin Quad Flatpack TQFP RFP Suffix 256 Terminal 1 0 mm 16x16 Array Plastic Ball Grid Array PBGA GDH and ZDH Suffixes Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document C67x PowerPAD TMS320C6000 C6000 DSP BIOS XDS TMS320 are trademarks of Texas Instruments Philips is a registered trademark of Koninklijki Philips Electronics N V All trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters
148. ts from SPIx_CLK falling 13 tyspc_soms valid on 5 5 after T transmit edge of SPIx CLK Polarity 1 Phase 0 415 from SPIx CLK falling Polarity 1 Phase 1 from SPIx_CLK rising 2P 15 Polarity 0 Phase 0 _ from SPIx falling 0 5tespc s 10 Output hold time Polarity 0 Phase 1 _ SPI SOMI valid after from SPIx_CLK rising O Stcsecs 10 14 Tonspc_soms receive edge of SPIXCLK Polarity 1 Phase 0 ns except for final bit from 5 rising 0 5te spc s 10 Polarity 1 Phase 1 _ from SPIx_CLK falling O Stesecjs 10 Polarity 0 Phase 0 to SPIx_CLK falling 0 5 15 Polarity 0 Phase 1 Input Setup Time to SRI CLK rising 0 5P 15 15 tsusimo_sPc s SPIx_SIMO valid before ns receive edge of SPIx_CLK Polarity 1 Phase 0 0 5P 15 to SPIx_CLK rising Polarity 1 Phase 1 to SPIx_CLK falling 0 5P 15 Polarity 0 Phase 0 from SPIx_CLK falling 0 5P 5 Polarity 0 Phase 1 Input Hold Time from SPIx_CLK rising 0 5P 5 16 6 SIMO S SPIx_SIMO valid after ns receive edge of SPIx_CLK Polarity 1 Phase 0 05P 5 from SPIx CLK rising 4 Polarity 1 Phase 1 from SPlx CLK falling 0 5 5 84 SYSCLK2 period First bit may be MSB or LSB depending upon SPI configuration SO 0 refers to first bit and SO n refers to last bit output on SPIx_SOMI SI 0 refers to the first bit input and Sl n refers to t
149. ty for contention that needs to be addressed In most systems where both the DVpp and CVpp supplies ramp together as long as CVpp tracks DVpp closely any contention is also mitigated by the fact that the CVpp rail would reach its specified operating range well before the DVpp rail has fully ramped 4 7 2 Power Supply Decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP The core supply caps can be placed in the interior space of the package and the I O supply caps be placed around the exterior space of the package For the BGA package it is recommended that both the core and supply caps be placed on the underside of the PCB For the TQFP package it is recommended that the core supply caps be placed on the underside of the PCB and the I O supply caps be placed on the top side of the PCB Both core and I O decoupling can be accomplished by alternating small 0 1 uF low ESR ceramic bypass caps with medium 0 220 uF low ESR ceramic bypass caps close to the DSP power pins and adding large tantalum or ceramic caps ranging from 10 uF to 100 uF further away Assuming 0603 caps it is recommended that at least 6 small 6 medium and 4 large caps be used for the core supply and 12 small 12 medium and 4 large caps be used for the I O supply Any cap selection needs to be evaluated from an electromagnetic radiation EMI point of view EMI varies from one s
150. unter 0 0x4200 0020 RTICAFRCO Capture Free Running Counter 0 Current value of free running counter 0 on external event 0x4200 0024 RTICAUCO Capture Up Counter 0 Current value of prescale counter 0 on external event 0x4200 0030 RTIFRC1 Free Running Counter 1 Current value of free running counter 1 0x4200 0034 RTIUC1 Up Counter 1 Current value of prescale counter 1 0x4200 0038 RTICPUC1 Compare Up Counter 1 Compare value compared with prescale counter 1 0x4200 0040 RTICAFRC1 Capture Free Running Counter 1 Current value of free running counter 1 on external event 0x4200 0044 RTICAUC1 Capture Up Counter 1 Current value of prescale counter 1 on external event 0x4200 0050 RTICOMPO Compare 0 Compare value to be compared with the counters 0x4200 0054 RTIUDCPO Compare 0 Value to be added to the compare register 0 value on compare match 0x4200 0058 RTICOMP1 Compare 1 Compare value to be compared with the counters 0x4200 005C RTIUDCP1 Update Compare 1 Value to be added to the compare register 1 value on compare match 0x4200 0060 RTICOMP2 Compare 2 Compare value to be compared with the counters 0x4200 0064 RTIUDCP2 Compare 2 Value be added to the compare register 2 value on compare match 0x4200 0068 RTICOMP3 Compare 3 Compare value to be compared with the counters 0x4200 006C RTIUDCP3 Update Compare 3 Value to be added to the compare register 3 value on compare match 0x4200 0070 Reserved Reserved bit 0x
151. ut AR 2 2 5 5 T fen Pulse duration ACLKR external ACLKR output AR 2 2 5 Pulse duration ACLKX internal ACLKX output AX 2 2 56 Pulse duration ACLKX external ACLKX output AX 2 2 56 Delay time ACLKR internal AFSR output 5 Delay time ACLKX internal AFSX output 5 Delay time ACLKR external input AFSR output 10 Delay time ACLKX external input AFSX output 10 Delay time ACLKR external output AFSR output 10 Delay time ACLKX external output AFSX output 10 Delay time ACLKR internal AFSR output 1 Delay time ACLKX internal AFSX output 1 Delay time external input AFSR output 0 Delay time ACLKX external input AFSX output Delay time ACLKR external output AFSR output Delay time ACLKX external output AFSX output Delay time ACLKX internal AXRn output 1 5 14 ta ACLKX AXRV Delay time ACLKX external input AXRn output 10 ns Delay time ACLKX external output AXRn output 10 Disable time ACLKX internal AXRn output 3 10 15 tdis ACKX AXRHZ Disable time ACLKX external input AXRn output 3 10 ns Disable time ACLKX external output AXRn output 3 10 1 ACLKX internal ACLKXCTL CLKXM 1 PDIR ACLKX 1 ACLKX external input ACLKXCTL CLKXM 0 PDIR ACLKX 0 ACLKX external output ACLKXCTL CLKXM 0 PDIR ACLKX 1 ACLKR internal ACLKRCTL CLKRM 1 PDIR ACLKR 1 ACLKR external input ACLKRCTL CLKRM 0 PDIR ACLKR 0 ACLKR external output ACLKRCTL
152. x memory controller supports up to three parallel accesses to the internal RAM and ROM from three of the following four sources as long as there are no bank conflicts e Two 64 bit data accesses from the C67x CPU e One 256 bit wide program fetch from the program cache e One 32 bit data access from the peripheral system either dMAX or A program cache miss is 256 bits wide and conflicts only with data accesses to the same page Multiple data accesses to different pages or to the same page but different banks will occur without conflict The organization of the C672x internal memory system into multiple pages 3 total and a large number of banks 16 total means that it is straightforward to optimize DSP code to avoid data conflicts Several factors including the large program cache and the partitioning of the memory system into multiple pages minimize the number of program versus data conflicts The result is an efficient memory system which allows easy tuning towards the maximum possible CPU performance The C672x ROM consists of a software bootloader plus additional software Please refer to the C9230C100 TMS320C672x Floating Point Digital Signal Processors ROM Data Manual literature number SPRS277 for more details on the ROM contents Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 2 5 Program Cache TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS26
153. x8FFF FFFF Byte and Word External Asynchronous Flash space on EMIF 0x9000 0000 Ox9FFF FFFF Byte and Word EMIF Control Registers OxF000 0000 OxF000 OOBF Word Only 1 The upper byte of the EMIF s SDRAM Configuration Register SDCR 31 24 is byte addressable to support placing the into the Self Refresh State without triggering the SDRAM Initialization Sequence Submit Documentation Feedback Device Overview 15 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS SPRS268E MAY 2005 REVISED JANUARY 2007 2 8 Boot Modes www ti com The C672x DSP supports only one hardware bootmode option this is to boot from the internal ROM starting at address 0x0000 0000 Other bootmode options are implemented by a software bootloader stored in ROM The software bootloader uses the CFGPINO and CFGPIN1 registers which capture the state of various device pins at reset to determine which mode to enter Note that in practice only a few pins are used by the software CAUTION Only an externally applied RESET causes the CFGPINO and CFGPIN1 registers to recapture their associated pin values Neither an emulator reset nor a RTI reset causes these registers to update The ROM bootmodes include e Parallel Flash on EM CS 2 e SPIO or I2C1 master mode from serial EEPROM SPIO or I2C1 slave mode from external MCU e UHPI from an external MC
154. ystem design to another so it is expected that engineers alter the decoupling capacitors to minimize radiation Refer to the High Speed DSP Systems Design Heference Guide literature number SPRU889 for more detailed design information on decoupling techniques Submit Documentation Feedback Peripheral and Electrical Specifications 37 TMS320C6727 TMS320C6726 TMS320C6722 43 Texas Floating Point Digital Signal Processors INSTRUMENTS 4 8 Reset A hardware reset RESET is required to place the DSP into a known good state out of power up The RESET signal can be asserted pulled low prior to ramping the core and I O voltages or after the core and I O voltages have reached their proper operating conditions As best practice RESET should be held low during power up Prior to deasserting RESET low to high transition the core and voltages should be at their proper operating conditions 4 8 1 Heset Electrical Data Timing Table 4 1 assumes testing over recommended operating conditions Table 4 1 Reset Timing Requirements NO MIN MAX UNIT 1 tw RSTL Pulse width RESET low 100 ns 2 tsu BPV RSTH Setup time boot pins valid before RESET high 20 ns 3 th RSTH BPV Hold time boot pins valid after RESET high 20 ns 38 Peripheral and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6727 5320 6726 TMS320C6722 INSTRUMENTS Floating Point Digital Signal Processors SPRS268E

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