Texas Instruments TAS3002 User's Manual
Contents
1. BIT FIELD NAME TYPE DESCRIPTION Fast load 0 Normal operation mode 1 Fast load mode default SCLK frequency 0 SCLK is 32 fs 1 SCLK is 64 fs Serial port mode 00 Left justified 01 Right justified 10 125 11 Reserved Serial port word length 00 16 bit 01 18 bit 10 20 bit 11 24 bit 4 13 Main Control Register 2 43h The TAS3002 device contains two main control registers main control register 1 MCR1 and main control register 2 MCR2 The MCR2 register contains the bits associated with the AllPass function and the download of bass and treble control information and it is accessed via 12 with the address 43h MCR2 43h Table 4 3 Main Control Register 2 Description BIT FIELD NAME TYPE DESCRIPTION Reserved R W 0 Normal operation initial condition after reset 1 Download bass and treble 6 5 Reserved R Reserved Bits 6 and 5 return Os when read 4 2 Reserved Undefined 1 DM 1 0 0 Normal operation initial condition after reset 1 AllPass mode bass and treble are still functional 0 INP R Reserved Bit 0 returns 0 when read 4 7 4 8 5 Filter Processor 5 1 Biquad Block The biquad block consists of seven digital biquad filters per channel organized in a cascade structure as shown in Figure 5 1 Each of these biquad filters has five downloadable 24 bit 4 20 coefficients Each stereo channel has independent coefficients Biqua2. 386n 394n S93n BATn SA2h 5BON NOTE Bytes are in the same order as they appear in the 2 register map The EEPROM address is AOh 8 Electrical Characteristics 8 1 Absolute Maximum Ratings Over Operating Temperature Rangest Supply voltage range AVDD III 0 3 V to 3 6 V DVDD Aa 0 3 V to 3 6 V Analog input voltage range eee 0 3 to AVpp 0 3 V Digital input voltage range 0 3 to DVpp 0 3 V Operating free air temperature TA _ 0 C to 70 C Storage temperature range Teig eee eee nnn 65 C to 150 C Case temperature for 10 seconds 122 C Lead temperature from case for 10 seconds 97 8 Electrostatic discharge see Note 1 2000 V T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 Human body model per Method 3015 2 of MIL STD 833B 8 2 Recommended Operating C
3. won o Left Channel Right Channel Figure 2 2 125 Serial Interface Format 2 3 2 2 3 MSB Left Justified Serial Interface Format The normal output mode for the MSB left justified serial interface format is for 16 18 20 or 24 bits Figure 2 3 shows the following characteristics of this protocol e Left channel is transmitted when LRCLK is high e The SDIN data is justified to the leading edge of the LRCLK e The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK Left Channel Right Channel Figure 2 3 MSB Left Justified Serial Interface Format 2 4 2 3 Switching Characteristics td SDOUT SDOUT valid from SCLK falling edge see Note 1 NOTE 1 Maximum of 50 pF external load on SDOUT tc SCLK a M t ScLK SCLK gt P tf SCLK P t taspouT lt gt td SLR 1 SDOUTI SDOUTO tsu SDIN gt th SDIN SDIN1 SDIN2 Figure 2 4 For Right Left Justified and I2S Serial Protocols 2 5 2 6 3 Analog Input Output The TAS3002 device contains a stereo 24 bit ADC with two single ended inputs per channel Selection of the A or B analog input is accomplished by setting a bit in the analog control register ACR by an 12C command Additionally the TAS3002 device has a stereo 24 bit digital to analog converter DAC 3 1 Analog Input Figure 3 1 shows the techn
4. is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval license warranty or endorsement thereof Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service is an unfair and deceptive business practice and TI is not responsible nor liable for any such use Resale of Tl s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service is an unfair and deceptive business practice and is not responsible nor liable for any such use Also see Standard Terms and Conditions of Sale for Semiconductor Products www ti com sc docs stdterms htm Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2001 Texas Instruments Incorporated 1 Introduction 1 1 Description The TAS3002 device is a system on a chi
5. terminal 11 CLKSEL is tied high and an MCLK rate of 51215 must be supplied If the 25615 MCLK is selected CLKSEL is tied low and an MCLK of 256fg must be supplied In both cases an LRCLK of 64SCLK must be supplied e MCLK SCLK must be synchronous and their edges must be at least 3 ns apart e If the LRCLK phase changes by more than 10 cycles of MCLK the codec automatically resets The TAS3002 device is compatible with 13 different serial interfaces Available interface options are 125 right justified and left justified Table 2 1 indicates how the 13 options are selected using the I2C bus and the main control register MCR 12 address 01h All serial interface options at either 16 18 20 or 24 bits operate with SCLK at 6415 Additionally the 16 bit mode operates at 32fs Table 2 1 Serial Interface Options MODE MCRBIT 6 5 4 MCR BIT 1 0 SDIN2 SDOUT1 SDOUT2 AND SDOUTO 0 0 00 00 16 bit 3215 1 1 00 00 16 bit left justified 6415 2 1 01 00 16 bit right justified 6415 3 1 10 00 16 bit 125 6415 4 1 00 01 18 bit left justified 6415 5 1 01 01 18 bit right justified 64 fg 6 1 10 01 18 bit 125 6415 7 1 00 10 20 bit left justified 6415 8 1 01 10 20 bit right justified 6415 9 1 10 10 20 bit 125 6415 10 1 00 11 24 bit left justified 6415 11 1 01 11 24 bit right justified 6415 12 1 10 11 24 bit 125 6415 Figure 2
6. 1 through Figure 2 3 illustrate the relationship between the SCLK LRCLK and the serial data I O for the different interface protocols 2 2 Digital Output Modes The digital output modes SDOUT1 SDOUT2 SDOUTO are described in Sections 2 2 1 through 2 2 3 2 2 1 MSB First Right Justified Serial Interface Format The normal output mode for the MSB first right justified serial interface format is for 16 18 20 or 24 bits Figure 2 1 shows the following characteristics of this protocol e Left channel is transmitted when LRCLK is high e The SDIN s recorded data is justified to the trailing edge of the LRCLK e The SDOUT s MSB playback data is transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK e fthe LRCLK phase changes by more than 10 cycles of MCLK the codec automatically resets LRCLK fs Ncc so e je Left Channel Right Channel Figure 2 1 MSB First Right Justified Serial Interface Format 2 2 2 125 Serial Interface Format The normal output mode for the 125 serial interface format is for 16 18 20 or 24 bits Figure 2 2 shows the following characteristics of this protocol e Left channel is transmitted when LRCLK is low e SDIN is sampled with the rising edge of SCLK e SDOUT is transmitted on the falling edge of e If the LRCLK phase changes by more than 10 cycles of MCLK the codec automatically resets LRCLK fs om u
7. 2168 2208 15 2201 2388 15 P3sCh 24Ah 15 2481 2598 15 25An 268 15 269h 277h_ 15 28026 15 287h 205h 15 296h 2A4h 15 2A5h 2B3h 15 aB n 2C2h 15 2cah 2Din_ 15 __202 15 2Emeern 15 afon eren 15 2FFh 30Dh 15 30En 31ch 15 31Dh 32Bh 15 32ch33 15 38Bh 349h 15 asanasen_ 15 359h 367h_ 15 ___ 376 15 37zh 385h 15 __ 15 __ 15 Table 7 5 2048 Byte EEPROM Memory Map 2 1 Speakers With Multiple Equalizations Pom i o o o o T o o T 6 eme 200h 20Eh Biquad 0 5B1h 5BFh 40Dh 41Bh 20Fh 21Dh Biquad 1 5COh 5CEh 41Ch 42Ah 21Eh 22Ch Biquad 2 5CFh 5DDh 42Bh 439h Set 1 22Dh 23Bh Biquad 3 43Ah 448h 23Ch 24Ah Biquad 4 449h 457h 24Bh 259h Biquad 5 25Ah 268h Biquad 6 5FCh 60Ah 458h 466h 60Bh 619h 467h 475h Set 3 638h 646h 494h 4A2h 647h 655h 4A3h 4B1h 656h 664h 4B2h 4C0h 6A1h 6AFh 4FDh 50Bh 6BOh 6BEh 50Ch 51Ah 2FFh 30Dh Biquad 3 6BFh 6CDh 51Bh 529h 30Eh 31Ch Biquad 4 31Dh 32Bh Biquad 5 6CEh 6DCh 52Ah 538h 32Ch 33Ah Biquad 6 6DDh 6EBh 539h 547h 33Bh 349h Biquad 0 6ECh 6FAh 548h 556h 34Ah 358h Biquad 1 6FBh 709h 557h 565h Set4 269h 277h Biquad 0 61Ah 628h 476h 484h 278h 286h Biquad 1 629h 637h 485h 493h Set2 SGGh S74h 575h 580h 377h 385 5 4 592
8. 4 3 Dynamic Loudness Contour Block Diagram The loudness contour is activated by sending an activation command via 12C from an external device Optionally a contour gain command can be sent by an external device to provide tracking with the system volume control 4 9 1 Loudness Biquads Loudness biquad filters for the left and right channels are independently programmable via 12C Their subaddresses are 21h and 22h respectively The digital filters are written as five 24 bit 4 20 hex coefficients for each channel 4 9 2 Loudness Gain Loudness gain values for the left and right channels are independently programmable via I2C Their subaddresses are 23h and 24h respectively The gain values are written as one 4 20 hex coefficient for each channel 4 9 3 Loudness Contour Operation When the frequency of the loudness contour is determined a digital filter must be developed Then the gain of the filter is determined These values are placed in the storage area of the system controller microcontroller and sent to the TAS3002 device when it is desired to activate the loudness contour If it is necessary to change the frequency or gain of the contour new gain and filter coefficients are sent by the system controller This function is performed normally when the volume control is changed that is more volume less contour The gain of the loudness contour filter then tracks the volume control The loudness contour biquad filter
9. Sending I2C data while the TAS3002 device is busy causes errors and locks up the device which must then be reset 6 3 Table 6 3 gives typical values of the wait states that be expected with the various functions of the part Table 6 3 12 Wait States Volume Not dependent on size of change Equalization Can occur with each filter 6 4 SMBus Operation The TAS3002 device supports a subset of the SMBus protocol With proper programming techniques it is possible to use the SMBus to set up the TAS3002 device 6 4 1 Block Write Protocol The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block To send a command using this format the most significant bit MSB of the TAS3002 subaddress must be set high and the subaddress also with MSB set high must be programmed into the SMBus command byte This operation signals the TAS3002 device that the next byte is the SMBus byte count byte The next byte after the byte count is then entered into the device as the first byte of data SMBus Command Byte 68h 8rh XX dd dd dd TAS3002 Subaddress Byte Count Data Data Data Address r subaddress Don t Care 6 4 2 Write Byte Protocol The TAS3002 device also supports the SMBus write byte protocol Writing to the main control register MCR bass and treble registers requires using the byte write protocol To send a command using this protoc
10. command that informs the TAS3002 that a byte has been read e 2C Stop is a valid IC Stop command NOTES 1 The TAS3002 will appear to be locked up if a Send Ack is issued after the last byte read It is required to send an 2 after the last byte and a Send Ack 2 The I2C Start and I2C Stop commands are the same for both 12C read and 12C write 6 3 3 12C Wait States The TAS3002 device performs interpolation algorithms for its volume and tone controls If a volume or tone change is sent to the part via 12C the command sent after the volume or tone bass and treble change causes an 12C wait state to occur This wait state lasts from 41 ms to 231 ms depending on the system clock rate the command sent and in the case of bass or treble the amount of the change Secondly if a long series of commands is sent to the TAS3002 device it may occasionally create a short wait state on the order of 150 us to 300 us while it loads and processes the commands When a sample rate of 32 kHz is used longer wait states can occur occasionally up to 15 ms The preferred way to take care of wait states is to use an 12 controller that recognizes wait states During the wait state period it stops sending data over 12C If this function is not available on the system controller fixed delays can be implemented in the system software to ensure that the controller is not trying to send more data while the TAS3002 device is busy
11. conditions These start and stop conditions for the 12 bus are required by standard protocol to be generated by the master The master must also generate the 7 bit slave address and the read write R W bit to open communication with another device and then wait for an acknowledge condition The slave holds SDA low during acknowledge clock period to indicate an acknowledgment When this occurs the master transmits the next byte of the sequence After each 8 bit word an acknowledgment must be transmitted by the receiving device There is no limit on the number of bytes that can be transmitted between start and stop conditions When the last word transfers the master generates a stop condition to release the bus Figure 6 1 shows a generic data transfer sequence 7 Bit R 8 Bit Register Data 8 Bit Register Data 8 Bit Register Data SDA Slave Address W for Address N for Address N 1 for Address N 2 lz 61 lilo 7 161 lilo 7 6 1106 1 a T Start Stop Figure 6 1 Typical 12C Data Transfer Sequence Table 6 1 lists the definitions used by the 2 protocol Table 6 1 12C Protocol Definitions DEFINITION DESCRIPTION Transmitter The device that sends data Receiver The device that receives data Master The device that initiates a transfer generates clock signals and terminates the transfer Slave The device addressed by the master Multimaster More than one master can atte
12. from the external EEPROM If no EEPROM is present the TAS3002 device remains in its default condition If addresses other than 68h 69h are set the TAS3002 device only operates as an 12C slave device If the microcontroller determines the TAS3002 device has an I2C address of 68h 69h and the EEPROM is present the microcontroller downloads coefficients from the EEPROM Once the download is complete it enables the serial audio in the mode defined by an I2C write to the MCR to transfer data into and out of the device Before reading the EEPROM the serial audio port defaults to 125 mode The TAS3002 device allows the user to update volume bass and treble dynamically by an 12 slave command or by a simple GPI input The can select volume up and down bass treble up and down or digital equalizations Up to five different equalizations that is flat jazz rock voice etc can be stored in the external EEPROM Also DRCE MCR1 MCR2 and loudness contour are enabled and disabled by 12C When the TAS3002 device operates in the 12C master mode it echoes changes to all of its functions to other 12C addresses that are defined in its external EEPROM If no addresses are defined it does not echo 7 2 Power Up Power Down Reset 7 2 1 Power Up Sequence An active low on terminal 6 RESET while MCLK is running resets the internal microcontroller and DSPs RESET synchronizes internally and can be asserted asynchronously or with the simple RC cir
13. mmm Stop band Stop band attenuation 28 8 kHz to 3 MHz 7 Amplitude R 20 40 60 80 100 0 fs 2 1 fs 2 fs 3 fs 4 fs 5 fs 1 Frequency Hz Figure 8 5 DAC Filter Overall Frequency Characteristics 0 1 0 05 Amplitude dB 0 0 1 fs 0 2 fs 0 3 fs 0 4 fs 0 5 fs f Frequency Hz Figure 8 6 DAC Digital Filter Pass Band Ripple Characteristics 8 4 8 8 Digital to Analog Converter TA 25 C AVpp 3 3 V DVpp 3 3 V fg 48 kHz input 0 dB fg sine wave at 1 kHz SNR EIAJ gt Signal to noise distortion ratio OdB 1kHz 20 Hzto20kHz 83 dB Idle channel tone rejection Intermodulation distortion 75 Frequency response 0 5 Deviation from linear phase Pt degree DAC crosstalk dB ps Jitter tolerance DC offset 8 9 DAC Output Performance Data 25 C AVpp 3 3 V DVpp 3 3 V The output load resistance is connected through a dc blocking capacitor Output load capacitance VCOM internal resistance see Note 4 VCOM output CLOAD VRFILT internal resistance see Note 5 NOTES 4 VCOM may vary during power down 5 VRFILT must never be used as a voltage reference 8 5 8 10 I2C Serial Port Timing Characteristics ar tsu sta Setup time repeated start 4 20 th dat Data hold time See Note 6 us NOTE 6 A device
14. the 53002 device 1 tne inf sale mw w Rightchannelanalogimputt SSCS 41_ Shift bit clock input output when IFM S is high CN some sooo O spour O Serial data output rom intemal audio pressing spour2 ____24 O Serial data output monaural mix of left and rignt before processing _ beste Digital to analog converter mid rail decouple with parallel combination of 10 uF and 0 1 uF capacitors TT Vase a 1 ADCpus votagereterence OOOO 2 O Vatagerfeenos lo pass er AT CATAN 1 Grystalinput connected between 2 Audio Data Formats 2 1 Serial Interface Formats The TAS3002 device works in master or slave mode In the master mode terminal 21 IFM S is tied high This activates the master clock MCLK circuitry A crystal can be connected across terminals 13 XTALI MCLK and 14 XTALO or an external TTL compatible MCLK can be connected to XTALI MCLK In that case MCLK is outputs on terminal 12 MCLKO with terminals 19 LRCLK O and 20 SCLK O becoming outputs to drive slave devices In the slave mode IFM S is tied low LRCLK O and SCLK O are inputs and the interface operates as a slave device requiring externally supplied MCLK LRCLK left right clock SCLK shift clock inputs There are two options for selecting the clock rates If the 512fg MCLK rate is selected
15. 35 INSTRUMENTS TAS3002 Digital Audio Processor With Codec 2001 Digital Audio Digital Speakers SLAS307B IMPORTANT NOTICE Texas Instruments and its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its products to the specifications applicable at the time of sale in accordance with T s standard warranty Testing and other quality control techniques are utilized to the extent deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied
16. 6 fs 0 8 fs 115 f Frequency Hz Figure 8 2 ADC Digital Filter Stop Band Characteristics 8 2 0 002 Amplitude dB 0 002 0 0 1 fs 0 2 fs 0 3 fs 0 4 fs 0 5 fs f Frequency Hz Figure 8 3 ADC Digital Filter Pass Band Characteristics Amplitude dB 1 A 0 1 fs 2 fs 3 fs 415 f Frequency Hz Figure 8 4 ADC High Pass Filter Characteristics 8 5 Analog to Digital Converter TA 25 C AVpp 3 3 V DVpp 3 3 V fg 48 kHz 20 bit I2S mode All terms characterized by frequency are scaled with the chosen sampling frequency fs PARAMETER SNR Signal to noise distortion ratio Power supply rejection ratio Idle channel tone rejection Intermodulation distortion ADC crosstalk Overall ADC frequency response 20 Hz to 20 kHz Gain error Gain matching NOTE 3 Measured with a 50 mV peak sine curve 8 3 8 6 Input Multiplexer 25 C AVpp 3 3 V DVpp 3 3 V fg 48 kHz 20 bit 125 mode PARAMETER TEST CONDITIONS MAX UNIT Input impedance YP Full scale input voltage range aaz 8 7 DAC Interpolation Filter Ta 25 C AVpp 3 3 V DVpp 3 3 V fg 48 kHz 20 bit 125 mode All terms characterized by frequency are scaled with the normal mode sampling frequency fs See Figure 8 5 and Figure 8 6 for performance curves of the DAC digital filter
17. G Each instruction downloaded must be eight bytes If only one byte is changed all eight bytes must be transmitted The first two bytes remain the same for every instruction however the last six bytes can be programmed using hexadecimal values from the corresponding tables referred to in Section NO TAG With high compression ratios and fast attack times available this function is suited for a commercial killer in a television set application 4 11 AllPass Function This function is enabled by setting terminal 27 ALLPASS on the TAS3002 device to 1 When asserted the internal equalization filters are set into AllPass flat mode When this terminal is reset to 0 the equalization filters are returned to the equalization that was in use before the terminal was asserted In AllPass mode the bass and treble controls are still functional This function is frequently used for headphones When the headphone plug is inserted into its jack a switched contact in the jack enables the AllPass function The AllPass function also can be activated by writing a 1 to bit 2 of the analog control register 4 6 4 12 Main Control Register 1 01h The TAS3002 device contains two main control registers main control register 1 MCR1 and main control register 2 MCR2 The MCR1 register contains the bits associated with load speed SCLK frequency serial port mode and serial port word length It is accessed via 12C with the address 01h 1 01h
18. L is provided by an external master clock MCLK of 256 fg 512fg or a 25615 crystal The TAS3002 device has six internally configurable general purpose input GPI terminals that control volume bass treble and equalization Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal microcontroller 1 2 Features e Programmable seven band parametric equalization e Programmable digital volume control e Programmable digital bass and treble control e Programmable dynamic range compression expansion DRCE e Programmable loudness contour dynamic bass control e Configurable serial port for audio data e Two input data channels that can be mixed with digital data from the analog to digital converter ADC of the codec analog input These channels are controlled by 12C commands e Three output data channels Left and right data go through equalization bass treble DRCE and volume to SDOUT1 SDOUT2 mixes left and right data SDOUT2 operates as a center channel or subwoofer channel The output of the ADC is available for additional processing e Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation e Serial 2C master slave port that allows Downloading of control data to the device externally from the EEPROM an 12C master Controlling other 12C devices Two I2C selectable single ended analog input stereo channels Equalization bypass mo
19. PA 5 32 RESET 6 31 CS1 7 30 GPI2 ls 29 TEST 9 28 GPIO CAP 10 27 ALLPASS CLKSEL 11 26 SDOUT1 MCLKO 12 25 SDOUTO wo SI HE x Qo CN 30725892228 SE A Ale zi 0 D lt x Figure 1 2 TAS3002 Terminal Assignments 1 5 Terminal Functions Table 1 1 lists the terminals in alphanumeric order by signal name along with the terminal number terminal type and a description of the terminal function TERMINAL NAME NO 45 1 4 a NUN Eu Table 1 1 TAS3002 Terminal Functions DESCRIPTION Analog power supply 3 3 V Table 1 1 TAS3002 Terminal Functions Continued TERMINAL lO DESCRIPTION NAME NO ce pu TATI 1 7 AA TT 000 s Switch input terminals Digital audio control a input IE O Lowwhen analog input is selected il Ii MA 7 7 OSS yS INA 1 1 m O 34 Noconneoton Can be used as a printed board routing charnel no 36 Noconneoton be used as a printed cul board routing channe 1 high places the TASGOO2 device in power down RESET 6 1 Tose w resets
20. Stop Stop condition as defined in 2 NOTE Table is for serial data SDA serial clock SCL is not shown but conditions apply as well Whenever writing to a subaddress the correct number of data bytes must follow in order to complete the write cycle For example if the volume control register with subaddress 04h is written to six bytes of data must follow otherwise the cycle is incomplete and errors occur 6 2 6 3 2 TAS3002 I2C Readback Example The TAS3002 saves in a stack or first in first out FIFO buffer the last 7 bytes that were sent to it When an I2C read command is sent to the device LSB high it answers by popping the first byte off the stack The TAS3002 then expects either a Send Ack command an 12C Stop command from the host If a Send Ack command is sent from the host then the TAS3002 pops another byte off the stack If an I2C Stop is sent then the TAS3002 ends this transaction The proper sequence for reading is described as follows 2 Start Send I2C address byte with read bit set to 1 LSB set equal to 1 Receive Byte 0 Send Ack Receive Byte 1 Send Ack Receive Byte 2 Send Ack Receive Byte 3 Send Ack Receive Byte 4 Send Ack Receive Byte 5 Send Ack Receive Byte 6 if an ACK is sent after byte 6 it locks up the TAS3002 I2C Stop 12 Start is a valid 12C Start command e Receive Byte is a valid 122 command which reads a byte from the TAS3002 e Send Ack is a valid 12C
21. When GPI terminal is activated the TAS3002 device echoes its function over I2C to a TAS3001 device mapped to address 6Ah Therefore a system with two audio equalization chips can be implemented without the need for a microcontroller 7 6 2 GPIArchitecture The GPI provides simple but flexible input port to activate the input parameters Each terminal input is an active logic low 7 5 Power Up Restore Volume Initialize Default and MCR Initialize TAS3002 TAS3001 Load Parameters and Coefficients to DSP Volume Bass Treble Up Down Echo to TAS3001 Switch BQ Set Save Volume Mute Save PWR_DN Stop PLL Power Down Prd DRC Figure 7 3 Internal Interface Flow Chart 7 6 7 7 External EEPROM Memory Maps Table 7 2 through Table 7 5 show the 512 byte and 2048 byte EEPROM memory maps Table 7 2 512 Byte EEPROM Memory Map 2 0 Channels meom CT omom 8 mee G Trees _ NOTE Bytes are in the same order as they appear in the 12C register map The EEPROM address is AOh Table 7 3 512 Byte EEPROM Memory Map 2 1 Channels with TAS3001 031h 03Fh Biquad 0 PS igntand let RATA 6 owe s 6 A wwcwm 6 A TT 5 E 1FAh 1FFh NOTE In this mode the TAS3002 and the TAS3001 device
22. cuit in Figure 7 1 On reset SCL and SDA go to a high impedance state If the 12 address is set to 68h approximately 400 us after RESET returns to 1 the device sends one byte query 12C to look for an EEPROM If an EEPROM is found the TAS3002 becomes an I2C master otherwise it becomes an I2C slave When using address 68h in the slave mode an external master must wait until after the EEPROM query or else bus contention and improper operation occur 12C address x6Ah does not query the bus for an EEPROM The address for the EEPROM is AOh 7 2 2 Reset The TAS3002 device has an asynchronous reset terminal RESET This reset is synchronized with various clocks used in this device to generate a synchronous internal reset Upon reset the TAS3002 device goes through the following process e Clears all the RAM memory content e Clears all the registers in the circuits e Purges the codec e Selects analog input A RINA and LINA and sets the input A active indicator INPA low e Initializes the equalization parameters to AllPass filters e Sets the digital audio interface to the 125 18 bit mode e Sets the bass treble to 0 dB e Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog in e Sets the volume to 40 dB e Turns off all enhancement features DRCE etc e Reads the I2C address If the address is 68h the device reads its EEPROM It is possible to load the user defined bass treble data and break points op
23. d 0 Biquad 1 Biquad 6 Figure 5 1 Biquad Cascade Configuration 5 1 1 Filter Coefficients The filter coefficients for the TAS3002 device are downloaded through the I2C port and loaded into the biquad memory space Each biquad filter memory space has an independent address Digital audio data coming into the device is processed by the biquad block and then converted into analog waveforms by the DAC Alternatively filters can be loaded by asserting terminals on the GPI port 5 1 2 Biquad Structure The biquad structure that is used for the parametric equalization filters is as follows bs b z H z 0 1 2 2 NOTE ap is fixed at value 1 and is not downloadable The coefficients for these filters are represented in 4 20 format 4 bits for the integer part and 20 bits for the fractional part In order to transmit them over I2C it is necessary to separate each coefficient into three bytes The upper 4 bits of byte 2 comprise the integer part the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part The filters can be designed using the automatic loudspeaker equalization program ALE or a script running under MatLab named Filtermaker Both of these tools are available from Texas Instruments 5 2 6 I2C Serial Control Interface 6 1 Introduction Control parameters for the TAS3002 device can be loaded from I2C serial EEPROM by using the TAS3002 master interface mode If no EEPROM is fou
24. d signal to noise ratio SNR Since this circuit lowers the noise floor THD N is improved also Analog Output Adjust Capacitors for Desired Er Low Frequency Response 7 C1 TLV2362 Equilvalent 24 Bit VOOM S 6 2 DAC 10 WF N 7T 0 1 uF o AOUTL L Ain 5 Op Amp 2 c5 y Ji C2 1 2 C3 5 TLV2362 or Equilvalent 5 Op Amp 2 Figure 3 3 Analog Output With External Amplifier 3 2 3 Reference Voltage Filter Figure 3 4 shows the TAS3002 reference voltage filter 0 1 uF TAS3002 Figure 3 4 TAS3002 Reference Voltage Filter 3 3 3 4 4 Audio Control Enhancement Functions 4 1 Soft Volume Update The TAS3002 device implements a TI proprietary soft volume update This feature allows a smooth and pleasant sounding change from one volume level to another over the entire range of volume control 18 dB to mute The volume is adjustable by downloading a gain coefficient through the 12C interface in 4 16 format 4 bits for the integer and 16 bits for the fractional part NO TAG lists the 4 16 coefficients converted into dB for the range of 70 dB to 18 dB with 0 5 dB step resolution Right and left channel volumes can be unganged and set to different values This feature implements a balance control Volume is changed by writing the desired value into the volume control registers This is done by asser
25. de Single 3 3 V power supply Power down without reloading the coefficients Sampling rates of 32 kHz 44 1 kHz or 48 kHz Master clock frequency of 256fs 51215 Can have crystal input to replace MCLK Crystal input frequency is 256 fs Six GPI terminals for volume bass treble up down control mute and selection of equalization filters 1 3 Functional Block Diagram Figure 1 1 is a block diagram showing the major functions of the TAS3002 AVSS REF VREFM VREFP gt VRFILT gt AVDD AVss DVpp O DVss AINRP C AINRMC RINA Voltage Analog Digital Reference Supplies Supplies RINB AINLP O gt SDOUTO AINLM LINA LINB C p O VCOM gt O AOUTL O AOUTR 24 Bit Stereo DAC L R L R gt SDOUT2 32 Bit Audio Signal Processor SDOUT1 32 Bit Audio Signal Processor PWR_DN 5 L R RESET 5 TESTO O O z 2 5499 aa X o 2015 a nn x KEES Eg Figure 1 1 TAS3002 Block Diagram 1 4 Terminal Assignments Figure 1 2 shows the terminal locations on the package outline along with the signal name assigned to each terminal PACKAGE TOP VIEW tc Be zZ Ze 072222000 II gt gt lt lt rz lt E lt LINA 36 NC 2 35 AVpp AVss REF 34 NC AVss 4 33 GPI5 IN
26. down resumes normal operation 7 3 7 3 1 Power Down Timing Sequence PWR_DN RESET i J lt Power Down Mode amp Normal Operation lt 1ms gt Figure 7 2 Power Down Timing Sequence In power down mode the TAS3002 device typically consumes less than 1 mA 7 4 Test Mode Terminal 9 TEST is tied low in normal operation This function is reserved for factory test and must not be asserted 7 5 Internal Interface Figure 7 3 shows the flow chart of the interface between the microcontroller and its peripheral blocks 7 6 GPI Terminal Programming During initialization the microcontroller fetches a control byte from its EEPROM or receives a command I2C 7 6 1 GPI Interface The six GPI terminals are programmed to operate as indicated in Table 7 1 7 4 Table 7 1 GPI Terminal Programming Ga G sw s L x J j j T massen mssoy ag T P T mewa L T T NOTE x Logic low Initially after reset the TAS3002 GPI is set to control volume bass and treble Simultaneously setting GPI bits 1 and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization To return to volume bass and treble control simultaneously set GPI terminals 2 and 3 low for 1 second
27. ellite Amplifiers s PCM1744 Analog Out 10 Mechanical Information The TAS3002 device is packaged in a 48 terminal PFB package The following illustration shows the mechanical dimensions for the PFB package PFB S PQFP G48 PLASTIC QUAD FLATPACK 0 13 NOM 1 12 5 50 7 20 680 59 gage Planet 9 20 8 80 sQ 0 05 MIN Seating Plane 0 08 1 20 MAX 4073176 B 10 96 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 10 2
28. in setting when updated dynamically outside of the fast load mode therefore it is desirable to use fast load in conjunction with the soft volume mode SDIN1 SDIN2 and the ADC output can be mixed with a user selectable gain for each channel The gain control registers are represented in 4 20 format Left Channel Mix Coefficients p 12C Register Address 08h PENIS SDIN2 3 24 Bit Left Mix Coefficient SDIN1_L SDIN2_L ADC_L SDOUT1 SDIN1_R SDIN2_R ADC_R gt L R SUM SDOUT2 y 1 2 Right Channel Mix Coefficients SDIN1 SDIN2 ADC I2C Register Address 07h 3 24 Bit Right Mix Coefficient Figure 4 1 TAS3002 Mixer Function 4 4 Mono Mixer Control The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio data from the input mixer in order to derive a monaural channel This mixer has a fixed gain of 6 dB so that full scale inputs on L sum and sum do not produce clipping on the resulting L R_sum The output of this mixer is present on terminal 24 SDOUT2 and is generally used for a digitally mixed subwoofer or center channel application 4 5 Treble Control The treble gain level may be adjusted within the range of 15 dB to 15 dB with 0 5 dB step resolution The level changes are accomplished by downloading treble codes shown in NO TAG into the treble gain register Alternatively a limi
29. ique and components required for analog input to the TAS3002 device The maximum input signal must not exceed 0 7 Vrms Selection of the above component values gives a frequency response from 20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems 1200 pF M _ AINRP 0 47 uF ae O o RINA Voltage Reference RINB 1200 Y AINLP AINLM D D I gt O00 0 O Analog Inputs Use 0 47 uF for 20 Hz Cutoff Input Select Command From Internal Controller O Anti Alias Capacitors for fg 48 kHz 3 Tie unused analog inputs to analog ground through 0 1 uF capacitors Figure 3 1 Analog Input to the TAS3002 Device 3 2 Analog Output 3 2 1 Direct Analog Output The full scale analog output from the TAS3002 device is 0 707 Vrms It is referenced to VCOM which is approximately 1 5 Vdc VCOM must be decoupled with the network shown in Figure 3 2 AOUTR 24 Bit VCOM Analog Output Adjust Capacitors for Desired Low Frequency Response ur DAC AOUTL 0 1 uF AGND Figure 3 2 VCOM Decoupling Network 3 2 2 Analog Output With Gain Because the maximum analog output from the TAS3002 device is 0 707 Vrms the output level can be increased by using an external amplifier The circuit shown in Figure 3 3 boosts the output level 1 Vrms when it has a gain of 1 414 and provides improve
30. mpt to control the bus at the same time without corrupting the message Arbitration Procedure to ensure the message is not corrupted when two masters attempt to control the bus Synchronization Procedure to synchronize the clock signals of two or more devices 6 3 Operation The 7 bit address for the TAS3002 device is 0110 10X R W where X is a programmable address bit set by terminal 7 CS1 Combining CS1 and the RAN bit the TAS3002 device can respond to four different 12C addresses two read and two write These two addresses are licensed I2C addresses that do not conflict with other licensed I2C audio devices In addition to the 7 bit device address subaddresses direct communication to the proper memory location within the device A complete table of subaddresses and control registers is provided in Appendix A For example to change bass to 10 dB gain Section 6 3 1 shows the data that is written to the 12 port Table 6 2 I2C Address Byte Table 12 ADDRESS BYTE A6 A1 CS1 A0 RW 68h 011010 0 0 69h 011010 0 1 6Ah 011010 1 0 6Bh 011010 1 1 6 3 1 Write Cycle Example Start Slave Address RW A Subaddress A Data A Stop FUNCTION DESCRIPTION Start Start condition as defined in I2C Slave address 0110100 CS1 0 RW 0 write A Acknowledgement as defined in 12C slave Subaddress treble control register 0000 0101 Data 0 dB gain 0111 0010
31. must internally provide hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL P S P YN men H lt th dat tsu sta gt tsu sto of Data se SCL Allowed NN Set Line Stable 4 th sta M th sta NOTE t low is measured from the end of tf to the beginning of tr t high is measured from the end of tr to the beginning of tf Figure 8 7 12 Bus Timing 8 6 9 System Diagrams Figure 9 1 and Figure 9 2 show the TAS3002 stereo and 2 1 channel applications respectively 3 3 VDD Analog Out l Analog In 7 SPDIF 3 TAS3002 or 125 USB B T V EQ Switches NOTE Items such as the PLL network and power supplies are omitted for clarity Figure 9 1 Stereo Application Analog In SPDIF or 125 USB Switches on GPIO k Sal 3 3 VDD 2 Analog Out 5 9 TAS3002 o M 125 OUT aster spout B T V EQ Sub Vol Ly L R Mix 12C NOTE Items such as the PLL network and power supplies are omitted for clarity Figure 9 2 TAS3002 Device 2 1 Channels 9 2 Slave TAS3001 Address 6Ah To Sat
32. nd the TAS3002 device becomes a slave device and loads from another 12C master interface Information loaded into the TAS3002 registers is defined in Appendix A The 12C bus uses terminals 16 SDA for data and 15 SCL for clock to communicate between integrated circuits in a system These devices can be addressed by sending a unique 7 bit slave address plus R W bit 1 byte All compatible devices share the same terminals via a bidirectional bus using a wired AND connection An external pullup resistor must be used to set the high level on the bus The TAS3002 device operates in standard mode up to 100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF Furthermore the TAS3002 device supports a subset of the SMBus protocol When it is attached to the SMBus then byte word and block transfers are supported The SMBus NAK function is not supported and care must be taken with the sequence of the instructions sent to the TAS3002 device Additionally the TAS3002 device operates in either master or slave mode therefore at least one device connected to the 12C bus must operate in master mode 6 2 12 Protocol The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions A high to low transition on SDA indicates a start and a low to high transition indicates a stop Normal data bit transitions must occur within the low time of the clock period Figure 6 1 shows these
33. nt Byte SENT Start 69h xxh 07h Stop RECEIVED Start 07h aah ddh ddh ddh ddh ddh ddh Stop Byte Count Where xxh Command byte It is a don t care because the response contains only the subaddress and the last six bytes of data written to the TAS3002 device aah The last subaddress accessed in the device ddh Data bytes from the TAS3002 device NOTE Use read sequence defined in 6 3 2 6 5 6 6 7 Microcontroller Operation The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform housekeeping and interface functions Additionally it handles 22 communication and general purpose input functions 7 1 General Description The microcontroller uses a 256fg system clock and can access up to 8K bytes of memory It interfaces with the digital audio interface 12 master slave for downloading data and coefficients It also interfaces with two internal DSPs for transferring coefficients and other information The TAS3002 coefficients are loaded through 12C in the master or slave mode Standard audio processing functions volume bass and treble can be controlled activated through external switches connected to the six GPI terminals Upon reset the internal microcontroller sets all coefficients and audio parameters to the default values See Section 7 2 2 for default values If the TAS3002 address is 68h ADDR_SEL 0 it becomes the bus master device and attempts to load parameters and coefficients
34. ol the most significant bit MSB of the TAS3002 subaddress must be set high and the subaddress also with MSB set high must be programmed into the SMBus command byte The next byte after the command byte is then entered into the device as the first byte of data SMBus Command Byte 68h 8rh dd TAS3002 Subaddress Data Address r subaddress 6 4 6 4 3 Wait States If separate 12C SMBus commands are sent too frequently the TAS3002 device can generate a bus wait state This happens when the device is busy while performing smoothing operations and changing volume bass and treble The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed according to the SMBus specification worst case 200 ms The following is a possible bus wait state scenario CODE Start 68 84 06 01 00 00 01 00 00 Stop ACTUAL Start 68 84 06 01 Waitt 00 00 01 00 00 Stop T If the master does not recognize bus waiting or if the master times out on a long wait the master must not send consecutive I2C SMBus commands without a time interval of 200 ms between transactions 6 4 4 TAS3002 SMBus Readback The TAS3002 device supports a subset of SMBus readback When an SMBus read command is sent to the device LSB high it answers with the subaddress and the last six bytes written SMBus Byte Command Cou
35. onditions 25 C AVpp 3 3 V DVpp 3 3 V Voltages at analog inputs and outputs and at AVpp are with respect to ground Supply voltage AVpp V Supply voltage DVpp V Operating mA Supply current analog Power down see Note 2 uA Supply current digital 9 Power down see Note 2 uA Operating mW Power dissipation Power down see Note 2 i mW NOTE 2 If the clocks are turned off 8 3 Static Digital Specifications Ta 25 AVpp 3 3 V DVpp 3 3 V PARAMETER TEST CONDITIONS MIN MAX UNIT VIH High level input voltage 2 0 3 6 V VIL Low level input voltage 0 3 0 8 High level output voltage lo 1 VOL Low level output voltage lo 4 mA 0 4 V Input leakage current 10 10 uA Output load capacitance 50 pF 8 1 8 4 ADC Digital Filter Ta 25 C AVpp 3 3 V DVpp 3 3 V fg 48 kHz 20 bit 125 mode All terms characterized by frequency are scaled with the chosen sampling frequency fs See Figure 8 1 through Figure 8 4 for performance curves of the ADC digital filter PARAMETER TEST CONDITIONS TYP MAX UNIT Deviation from linear phase 20 Hz to 20 kHz 50 0 m I o 0 o 100 150 200 0 215 415 6 fs 8 fs 10 fg 12 fs f Frequency Hz Figure 8 1 ADC Digital Filter Characteristics 0 20 m 1 40 60 lt 80 100 0 0 2 fs 0 4 fs 0
36. own An 12C master is required to write the appropriate command into the ACR The ACR subaddress is 40h R W Table 4 1 er Register Description FIELDNAME TYPE DESCRIPTION Reserved Bits 5 and 4 return Os when read 3 2 DM 1 0 R W De emphasis control De emphasis off initial condition after reset 48 kHz sample rate de emphasis selected ne 44 1 kHz sample rate de emphasis selected 11 Reserved 1 R W Analog input select 0 LINA and RINA selected initial condition after reset 1 and RINB selected APD R W Analog power down 0 Normal operation initial condition after reset 1 Power down 4 4 4 9 Dynamic Loudness Contour The necessity for applying loudness compensation to playback systems to compensate for the fact that the ear perceives bass and treble less audibly at low levels than at high ones has been established since the first data was published by Fletcher and Munson in 1933 There are many equal loudness contours in publication like Steven s contours Robinson and Dadson contours Some have even reached the acceptance level of ISO recommendation The TAS3002 device has a simplified loudness contour algorithm that diminishes the effect of weak bass at low listening levels Since contour has volume level dependency the user must define the relation between the gain of the contour circuit and the volume level Figure 4 3 is a block diagram of this circuit Figure
37. p that replaces conventional analog equalization to perform digital parametric equalization dynamic range compression and loudness contour Additionally this device provides high quality soft digital volume bass and treble control All control parameters are uploaded from an outside MCU through the 12C slave port or from an external EEPROM through the 12C master port The TAS3002 device also has an integrated 24 bit stereo codec with two 12C selectable single ended inputs per channel The digital parametric equalization consists of seven cascaded independent biquad filters per channel Each biquad filter has five 24 bit coefficients that can be configured into many different filter functions such as band pass high pass and low pass The internal loudness contour algorithm can be controlled and programmed with an 12C command Dynamic range compression expansion DRCE is programmable through the 12 port The system designer can set the threshold energy estimation time constant compression ratio and attack and decay time constants The TAS3002 device supports 13 serial interface formats 125 left justified right justified with data word lengths of 16 18 20 or 24 bits The sampling frequency fs may be set to 32 kHz 44 1 kHz or 48 kHz The 13 serial interface formats are listed and described in Section 2 1 The TAS3002 device uses a system clock generated by the internal phase locked loop PLL The reference clock for the PL
38. s are provided in addition to the seven equalization biquad filters See Section NO TAG for programming instructions 4 5 4 10 Dynamic Range Compression Expansion DRCE The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system The DRCE receives data and affects scaling after the volume loudness block As shown in Figure 4 4 the DRCE is applied after the volume loudness control block as a DRCE scale factor The DRCE must be adjusted such that the signal does not reach the hard limit value However if the signal does reach the maximum digital value the saturation logic serves as a hard limiter that does not allow the signal to extend beyond the available range Loudness Soft Volume Parametric Equalization Tone Left Channel Mixer DRCE Scaling SDIN1_L LEFT_SUM 7 B nd ass 2 Order Treble IIR Filters Saturation LEFT_OUT SDIN2_L ANALOGIN_L Dynamic Range Control Analog in From ADC ANALOGIN_R SDIN1 R RIGHT SUM 7 2nd Order IIR Filters Soft Saturation RIGHT_OUT Volume Bass Treble SDIN2_R Right Channel Mixer DRCE Scaling Parametric Equalization Loudness Figure 4 4 TAS3002 Digital Signal Processing Block Diagram The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code of NO TA
39. s both use the same equalization coefficients for their right and left channels Bytes are in the same order as they appear in the 12C register map The EEPROM address is 7 8 Table 7 4 2048 Byte EEPROM Memory Map 2 0 Speakers With Multiple Equalizations o j 0021 1EFh w Ar O9Ah 18B5b Bass tree o Basswebetable treble table 20h SCOh SCEh 5OFh SDDA set SDEN SECH 5 20Fh 21Dh 21Eh 22Ch 22Dh 23Bh 5EDh 5EBn SFCT 6OA 5081 6191 23Ch 24Ah Biquad 0 476h 484h 61Ah 628h Biquad 1 485h 493h 629h 637h Biquad 2 494h 4A2h 638h 646h Biquad 3 Set 2 4A3h 4B1h 647h 655h 25Ah 268h 269h 277h 278h 286h 287h 295h 296h 2A4h 2A5h 2B3h 2B4h 2C2h 2C3h 2D1h 2D2h 2E0h 2E1h 2EFh 2FOh 2FEh 2FFh 30Dh 30Eh 31Ch 31Dh 32Bh 32Ch 33Ah 33Bh 349h 34Ah 358h 359h 367h 368h 376h 377h 385h 386h 394h 395h 3A3h 24Bh 259h Biquad 4 4B2h 4C0h 656h 664h Biquad 5 4C1h 4CFh 665h 673h gen 4DOh 4DEh 674h 682h 3 91 692h 6A0H Seta Biquad 4 51Bh 529h 6BFh 6CDh Biquad 5 52Ah 538h 6CEh 6DCh lan 539h 547h 6DDh 6EBh 709 7 718 Set 4 Biquad 4 584h 592h 728h 736h Biquad 5 593h 5A1h 737h 745h Biquad 6 5A2h 5B0h 746h 754h NOTE Bytes are in the same order as they appear in the 2 register The EEPROM address is AOh m 20Fh 21Dh_ 15
40. ssible to update the parametric equalization without any audio processing delay The audio processor pauses while the RAM is updated in this mode Bass and treble cannot download in this mode 1 and Mixer2 registers can download in this mode or normal mode FL bit 0 Once the download is complete the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1 MCR1 This puts the TAS3002 device into normal mode 7 2 5 Codec Reset During initialization the output of the codec is disabled Throughout reset and initialization the output of the DAC is muted to prevent extraneous noise being sent to the system output Data from the ADC and other internal processing is purged so that when reset initialization is complete only valid inputs are sent to the system output 7T 3 Power Down Mode The TAS3002 device has an asynchronous power down mode In the power down mode the internal control registers and equalization programming of the device are stored in the device To enter power down mode 1 Assert the power down control signal 1 2 Setthe serial audio input clocks to 0 The TAS3002 device goes into power down mode To exit the power down mode 1 Assert RESET logic 0 2 Restart the serial audio clocks 3 Wait for a delay of 1 0 ms to allow the PLL to lock 4 Negate the power down control signal logic 0 5 Negate RESET logic 1 The device then returns to the state it was in before power
41. ted range of treble control is available by asserting the treble up or treble down GPI terminal see Section 7 6 1 The treble control has a corner frequency of 6 kHz at a 48 kHz sample rate The gain values for treble control can be found in Section NO TAG 4 6 Bass Control The bass gain level can be adjusted within the range of 15 dB to 15 dB with 0 5 dB step resolution The level changes are accomplished by downloading bass codes shown in NO TAG into the bass frequency control register Alternatively a limited range of bass control is available by asserting the bass up or bass down GPI terminal see Section 7 6 1 Bass control is a shelf filter with a corner frequency of 250 Hz at a 48 kHz sample rate The gain values for bass control can be found in Section NO TAG 4 7 De Emphasis Mode DM De emphasis is implemented in the DAC and is software controlled De emphasis is valid at 44 1 kHz and 48 kHz To enable de emphasis values are written into the analog control register via the 12C command See Section 4 8 for analog control register operation Figure 4 2 illustrates the frequency response of the de emphasis mode De Emphasis Response dB 3 18 10 6 50 us 15 us Frequency kHz Figure 4 2 De Emphasis Mode Frequency Response 4 3 4 8 Analog Control Register 40h The analog control register ACR allows control of de emphasis selection of the analog input channel to the ADC and analog power d
42. ting the volume up or volume down GPI terminal see Section 7 6 1 for a limited range of volume control Alternatively volume control settings can be sent to the TAS3002 device over the 12C bus 4 2 Software Soft Mute Soft mute is implemented by loading all zeros in the volume control register This causes the volume to ramp down over a duration of 2048fg samples to a final output of 0 infinity dB Soft mute can be enabled by either asserting the mute GPI terminal see Section 7 6 1 or sending a mute command over the 12 bus Subsequent assertions of the mute GPI terminal toggle soft mute off and on 4 3 Input Mixer Control The TAS3002 device is capable of mixing and multiplexing three channels SDIN1 SDIN2 and the ADC output of serial audio data The mixing is controlled through three mixer control registers This is accomplished by loading values into the corresponding bytes of the mixer left gain 07h and mixer right gain 08h control registers See Figure 4 1 for a functional block diagram of the input mixer The values loaded into these registers are in 4 20 format 4 bits for the integer and 20 bits for the fractional part NO TAG lists the 4 20 numbers converted into dB for the range of 70 dB to 18 dB although any positive 4 20 number may be used To mute any of the channels Os are loaded into the respective mixer control register Mixer controls are updated instantly and can cause audible artifacts for large changes
43. tional If there is no data the device loads default bass treble delta and break points from ROM e address is 6Ah the device puts the 12C interface in slave mode and waits for input 7 2 3 Reset Circuit Because the TAS3002 device has an internal power on reset POR in many cases additional components are not needed to reset the device It resets internally at approximately 80 of Vpp In the case where the system power supplies are slow in reaching their final voltage or where there is a difference in the time the system power supplies take to become stable the TAS3002 reset can be delayed by a simple RC circuit DVpp 10 TAS3002 0 1 uF DVss Figure 7 1 TAS3002 Reset Circuit The reset delay for the above circuit can be calculated by the simple equation tra 0 8RC 400 us Where The delay before the TAS3002 device comes out of reset Value of the capacitance from RESET pin 6 to DVss Value of the resistance from RESET pin 6 to DVpp The circuit described in Figure 7 1 delays the start up of the TAS3002 device approximately 1 2 ms When it is necessary to control the reset of the TAS3002 device with an external device such as a microcontroller RESET pin 6 can be treated as a logic signal It then brings the device out of reset when the voltage on RESET reaches Vpp 2 7 2 4 Fast Load Mode While in fast load mode FL bit bit 7 of main control register 1 0 is po
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