Texas Instruments CDCM7005 User's Manual
Contents
1. JHBUSSE 5002 9z udy Aepsen HOS NAO 8 1 quinN 1ueunooq ezig ajnpow uogenjeA3 NAO S002ZAWOGO can 52 5002 0490 b z wie soe OTT Dvd 1410 x 227 NO 4 Spano 2 vo ao TS OJS lyd 10 SNLVLS INO dd HE 092 56 1 10 OXOA 5011 SONY pony NO RES 38H 1V1S E i NO zh lt F SKK 8h 146 438 se 39 99 nm gen HUN 89H zn SC 3 7 5 434 21 ou di 10 1393 434 035 a oas KE Wen ony oo 2 T aan ane MESA EE 52 SNILOXOA I OXON dk OXOA OXO ger veo 8LA ofl tt 2 7 LAK Y lvi YOA DOA NMauMd T LMS SUN y DA T zn L 2 t Parts List 6 12 gt Parts List 1890591 S00Z 92 2 HOS N3O 8 1J quinN juewns0q ezig NAO S002WOGO 1 0 42. gt Si gt ver eer zer uo dwy dO EU401X3 M 191115 9Al9V EEr ZEF uo g 9 uid poys 195 1jnejeg 19111 4 5584 6 13 Parts List Board Layout and Schematics Parts List BUSSE 900292 Way epsen V HOS N4O 8 ano ayo Jequiny ezig lnpoW NAO S00ZWOGO aul OL 920 ze 3 SL vH s 27 Z SN 85 2 ayo ren ird 222 DA rama 29 lt ate 1 wyo 0 NN 029 ssed g ayo 2390001 lt yne aq 615 L g v NO vns 819 wy T VIS GNI Z A NI T r z9 or VET ui 49 SZ xx Ov DOA ayo ano vas aue u NI OXOA Z II DG SNI OXON T 00 0 T ayo git T vWS SEA r or n AT 564 D WAS TON
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4. aS D 4 2 Software Installation Follow the steps below in order to install the SPI control software 1 Run program setup exe in the Installer folder 2 Reboot your computer 3 Run the Software from Start gt Programs gt CDCM7005 EVM gt CDCM7005 EVM 4 2 Chapter 5 Application Circuit Diagram This chapter discusses the application circuit diagram Topic Page 5 1 Application Circuit Diagram 5 2 5 1 Application Circuit Diagram 5 1 Application Circuit Diagram The following applications sections the two loop filter configurations are discussed 5 1 1 Passive Loop Filter The passive loop filter is a second order filter two poles one zero The zero is required for the overall loop stability R1 C1 and C2 generate the dominant pole of the system A second pole is introduced by R2 and C3 Figure 5 1 CDCM7005 With a Passive Loop Filter Configuration VC09O Low Pass Filter 491 52 MHz 160 Q PECL_OUT_B M PECL OUT m OU 058 100 nF CDCM7005 PRI REF SEC_REF EH A R1 4 7 KQ CP_OUT so CTRL LE 5 F SPI CTRL_DATA CTRL CLK STATUS REF Vcc Vcc STATUS VC X O v PLL_LOCK os ty 10 nF 1300 5 1300 VC00O_IN 19 nF 4 VC X O IN B R R
5. Parts List Board Layout Schematics 6 7 Parts List Figure 6 4 Bottom Layer View X 6 8 Parts List Figure 6 5 Ground Plane View K NA Parts List Board Layout and Schematics 6 9 Parts List Figure 6 6 Power Layer View 6 3 Schematics The following pages contain the schematics for the CDCM7005 QFN package 6 10 gt Parts List L PEYS St 5002 9z udy Aepsen 8 1 jueuinooq 9214 lnpoW NJO S00ZWOGO not 9001 665 890 95 992 ano 00 ana eae ao 400 OL OL uzz uor gt 7550 t990 290 L99 099 66989999999 F P F F PET E uot _ _ i nez eso zs 150 2090 6r9 4 4 09 4 Mues Poo P 99 2 0 r 4 4 4 4 20 aye 4 fuge P 090 660 8 0 1 212965 WH 91 6 11 Parts List Board Layout and Schematics L 2 Y 5
6. Manual amp REF SEL O Automatic detec ICLK Select gt 2 MHz req gt 2 PRI REF 21 Cae x 3 2 k Reference SEC REF e 3 E Feedback Clock CTRL LE gt SPI LOGIC CTRL DATA T PD Ir lt RESETor Y at HOLD INC PEOD VCXO N re VCC Selected REF Signal AVCC MHz Progr Delay Progr Divider M M 20 Progr Delay Progr Divider N N 22 PECL to LVCMOS FB_MUX 4 STATUS REF PRI_SEC_CLK L5 5 5 REF CP F7 LOCK HOLD Charge PFD Pump Y0_MUX Current Reference Y1_MUX Y2 MUX P Divider Bias Generator VBB gt 1 3 V YA D CMO CMO LN B O OUT YOA Y0B YIA Y1B 2 h Y2B Y3A Y4A Y4B 1 2 GND Chapter 2 Quick Start In order to setup the EVM quickly and to take some measurements at default settings the following actions are required Supply 3 3 V to P1 LED D4 will be on L Apply a single ended reference c
7. Connect the parallel port cable to the PC and EVM parallel port This needs control S W see Chapter 4 3 2 4 LoopFilter J32 J34 The loop filter is one of the key elements determining the loop bandwidth of the PLL The loop filter converts the charge pump current into the control voltage for the voltage controlled oscillator The phase difference between the input clocks of the phase frequency detector determines the width of the charge pump output current pulses These high frequency pulses are transformed into a voltage to control the oscillator Basically three types of loop filters are implemented on the EVM Passive loop filter External active loop filter using an external low noise OPA Filter types can be selected by soldering bridges J32 J34 see Table 3 1 Control voltage of the VC X O can be measured at J9 or TP1 If an external OPA is used it needs to be switched on by connecting J34 For example passive filter operation is provided when pads 1 and 3 of J33 are solder bridged and pads 1 and 3 of J32 are solder bridged Default setting Passive Loop Filter Table 3 1 Filter Configurations Bridge Passive Filter Active With An External OPA J33 1 3 1 2 J34 Open Closed J32 1 3 1 2 3 2 5 High Speed Outputs and Inputs J1 J4 J6 J11 J13 J14 J22 and J23 The 7005 drives five differential outputs All PECL outputs are ac coupled and terminated with 150 Q to GND This is in contrast to
8. 39 0 CIN c 9 ZNINS b 258 HNO NO 00t ayo BLNO 3 24 99 9 OSA1819 A zT ane ON T 5 ADE Sed ayo _ UOOLOLD 99A s WAS WHL A amp T Wis VN T S n ayo ZA T 00i NN b 06H ai 99 001 NN 4 SIND 81H SL S WHO Te wy N ayo TVWS are 09 7 0510 ART s 338 oas u 0 0 VAS UJ 2 90 wy m VNS LA OOF AN CATE T LH 99 ano z u3avaH QN9 29 orn L ayo 001 AN L L KPA uot 0 vr YS Oo E 68 e P z TTE He Usa vns ax SEHR e IH S SWT ayo 49 A gorn FE cu KIA 199 lt uot GOA VAS uu i z WS OX KOA 001 NN Ir 29 6 14 gt Parts List L 1881599 5002 92 HOS N3O 8 1J quinN juewns0q ezig NAO 9002 0942 enu HOd T3T1Vvuvd E D A L aNd 0 698901 Y turus g 95 ver 29A 5 viva ids T vt ZN Viva 9 rm ane d aor 2 129
9. 35 TEXAS INSTRUMENTS CDCM7005 QFN Package Evaluation Module Manual HPA High Speed Communications User s Guide 2005 Clock Drivers SCAU015 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any T
10. 4 2 Software Installation 4 2 Application Level Circuit Diagram 5 1 5 1 Application Circuit Diagram 5 2 5 1 4 Passive Loop Filter senarren spear bre bed yi EE IT ERR bees 5 2 5 1 2 External Active Loop Filter Using OPA341 5 3 Parts List Board Layouts and Schematics 6 1 6 1 yuka puak esas EVE Nine AEN ae Se 6 2 6 2 Board Layout 6 4 6 3 E E E 6 9 Figures mee mE e O OI N N Board VIW occae ped ec RO vate perg Maw Re MID 3 2 Screen VIEW J uu pasya AA EX WS Ie ao eu ae puce EN REC ORC RE S 4 2 CDCM7005 With a Passive Loop Filter Configuration 5 2 CDCM7005 With an External Active Loop Filter Using OPA341 5 3 Component View and Silkscreen Top Side 6 5 Component View and Silkscreen Bottom Side 6 6 Layer VIEW eI dae II 6 7 Bottom Layer VIOW Racer e Ee dera edd 6 8 Ground Plane s ese he tat A LL ad 6 9 Pow
11. C55 C65 C38 C44 C51 smd cap 0402 3 C39 C45 C52 smd_cap_0402 AVX 0402YD333KAT2A EE C59 C61 C67 smd cap 0402 AVX 0402YC223KAT2A C69 C71 smd cap 0402 100 nF 10 pF Part Number Panasonic ECJ 0EB1E103K Panasonic ECJ 0EB1E104K Panasonic ECJ 0EB1E101K Panasonic ECJ 0EB1E102K Panasonic ECJ 1VF1C105Z Panasonic ECJ 0EB1A104K Panasonic ECJ 0EB1E103K NU Rohm MCH155A1R1CK Panasonic ECJ 0EC1H220J NU Rohm MCH155A1R1CK Panasonic ECP U1C104MA5 Murata GRM32ER71A226KE20L Panasonic ECJ 0EB1E104K Panasonic ECJ 0EF1H103Z Panasonic ECS T1CC226R Panasonic ECS T1CC226R Panasonic ECS H1CC106R Yageo 04022F104Z7B20D Panasonic ECD GOE100C Parts List tem QTY Heference P Part Number Designator 22 2 C74 smd cap 1210 10 uF Murata GRM32DR61E106KA12L C77 smd_cap_1210 10 uF Murata GRM32DR61E106KA12L 23 1 C78 smd_cap_0805 NU Panasonic ECP U1C104MA5 24 D1 D3 smd led 1206 Lite On LTST C150AKT 25 1 D4 smd_led_1206 GREEN Lite On LTST C150KGKT 26 RTI 5 385 Toyocom Fifer 27 7 J1 J4 J6 J8 sma alt SMA Johnson Comp 142 0701 841 29 J9 J11 J13 sma alt NU SMA Johnson Comp J14 J16 J18 142 0701 841 J22 J23 30 J12 J25 J26 hdr3 100ctr HDR3 Header 3 pos 0 1 ctr J27 31 2 J17 J15 smd bridge 0402 SMDSP BRIDGE Panasonic ERJ 2GEORO0X 32 HDRZ Header2 1 or 33 2 J21 J20 smd bridge 0402 SMD3P BRIDGE Panasonic ERJ 2GEORO0X 34 J24 J28 J29 HDR2 Heade
12. ERJ 2RKF1003X 60 1 R52 smd res 0402 160 Q Panasonic ERJ 2RKF1002X 61 2 R53 R72 smd res 0402 4 7 Panasonic 62 3 R54 R56 smd res 0402 750 Panasonic 63 1 R58 smd res 0402 NU 12K 1 Panasonic 64 smd cap 0402 1 5 Panasonic 65 smd res 0402 180 Q Panasonic 66 3 R78 R79 R81 smd res 0402 Panasonic 67 SW2 SW1 Switch reset KT11P3JM ms 68 TP1 TP2 testpin 30dia T TPOINTR R Test point 69 U2 mbga pt8mm 64 skt BELLUM Texas Instruments 70 soic14 SN74LV125 Texas Instruments ir ur scar S s Cs OPA341UA T woo woos woos Toyocom VOXO Cu posee e s JJ s 75 SCREW Legs for PCB 6 4 Parts List 6 2 Board Layout Figure 6 1 Component View and Silkscreen Top View 98 ME Sou c R68 2 12 os 228 19 r3 Ser I B LS z gt 3539 899 us qe a B35 3 OD Cr Parts List Board Layout and Schematics 6 5 Parts List Figure 6 2 Component View and Silkscreen Bottom View eps 3 a hd 0000 E y sia Da 00 k gt EP xi N 6 6 Parts List Figure 6 3 Top Layer View ANE J a A d 7 B E Eee 2
13. R R 820 820 1500 1500 Ly L 4 5 2 5 1 2 External Active Loop Filter Using OPA341 Application Circuit Diagram Figure 5 2 CDCM7005 With a External Active Loop Filter Using OPA341 VC090 491 52 MHz PECL OUT B PECL OUT CDCM7005 PRI REF SEC REF Low Pass Filter R3 10 CTRL LE STATUS REF CTRL DATA STATUS VC X O CTRL CLK PLL LOCK VC X O IN VC X O_IN Application Circuit Diagram Chapter 6 Parts List Board Layout and Schematics This chapter contains the parts list board layout and schematics for the CDCM7005 EVM Topic Page 6 61 as A E EE E E A ah 6 2 6 4 6 2 Board ayout m 6 8 6 3 Schematics 6 1 Parts List 10 11 12 13 14 15 16 17 18 19 20 21 6 2 List tem Reference Designator 24 C1 C9 C12 C13 C15 C17 C26 C40 C41 C46 C47 C53 C54 056 058 C66 C72 C10 smd cap 0402 100 nF C11 C32 smd cap 0402 C62 C64 C68 C73 100 pF C20 C22 smd cap 0402 0 1 uF 3 e 10 nF smd_cap_0402 22 pF NU 1 pF 0 1 uF C27 C29 C75 smd_cap_0805 C76 C79 C80 smd cap 0402 C33 C35 smd cap 0402 22 UF 22 nF 10 nF 22 UF C36 C42 C48 smd cap 1210 pol C49 smd cap 1210 pol 22 uF 10 uF 5 C37 C43 C50 smd cap 1210 pol
14. coupling will increase the PLL stabilization time after power up due to transient effects It also increases the switching time between PRI REF and SEC REF in case of automatic reference clock switching Therefore the ac coupling must be removed for optimized system performance C1 and C5 has to be replaced with an 0 resistor and R4 R6 R13 and R15 have to be removed Serial Peripheral Interface SPI Software This chapter discusses the serial peripheral interface software Topic Page 4 1 Functional Description 7 211 n n sl 4 2 4 2 Software 4 2 4 1 Functional Description 4 1 Functional Description Programming software here as described is intended for programming the in ternal control register of the CDCM7005 The software runs under Win dows98 NT 2000 and XP A quick installation is required prior to use See the Software Installation section There are several cases where programming is mandatory As a rule of thumb here are some examples Use of active loop filter Change of divider ratio or disable of certain LVPECL LVCMOS outputs Select between LVPECL or LVCMOS output Change of phase offset Delay M N or selection of 90 or 180 phase shift Change of charge pump output current Widening the lock detect window OOOO O O Figure 4 1 Screen View gt Texas Instruments CDCM 7005 SPI Software DS aM
15. HE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the EVM User s Guide and specifically the EVM Warnings and Restrictions notice in the EVM User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For further safety concerns please contact the TI application engineer Persons handling the product mu
16. I patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter
17. ces can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated Preface Read This First About This Manual This manual explains how to use the CDCM7005 evaluation module EVM and provides guidelines to build the customer s own systems The manual includes schematics layout bill of materials and a software description How to Use This Manual This document contains the following chapters Chapter 1 Introduction Chapter 2 Quick Start Chapter 3 EVM Hardware D D D Li Chapter 4 Serial Peripheral Interface SPI Software Chapter 5 Schematics Board Layout and Parts List Related Documentation From Texas Instruments 1 CDCM7005 Data Sheet SCAS793 Texas Instruments FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case t
18. er Layer VIOW et E a Desc e ae Dese ed pon recie d 6 10 Tables 3 1 vi Filter Configurations 3 3 Chapter 1 Introduction The CDCM7005 is a high performance low phase noise and low skew clock synchronizer that synchronizes an on board voltage controlled crystal oscillator VC X O frequency to an external reference clock The device operates up to 2 2 GHz The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements by selecting the external VC X O loop filter components frequency for PFD and charge pump current Each of the five differential LVPECL and five LVCMOS pair outputs can be programmed by a serial peripheral interface SPI The SPI allows individual control of the frequency and enable disable state of each output As the system requires external components like a loop filter and VC X O this EVM provides an easy method to evaluate and modify the performance and parameters of the clock system in conjunction with the specific customer application Loop bandwidth can be selected as low as 10 Hz or less allowing the device to clean the system s clock jitter In non PLL mode the CDCM7005 can be used as a simple LVPECL or LVCMOS buffer with divider options Topic Page 1 4 CDCM7005 Functional Block Diagram 1 2 CDCM7005 Functional Block Diagram 1 1 CDCM7005 Functional Block Diagram
19. he user at his own expense will be required to take whatever measures may be required to correct this interference If You Need Assistance If you need assitance with this device please email clocks_apps list ti com Contents INTRODUCTIONS uu sus sasa ee eee ae ee 1 1 1 4 CDCM7005 Functional Block Diagram 1 2 Quick Start 2 1 EVM Hardware 3 1 3 1 Board View and Connector Location 3 2 3 2 Hardware Configuration 3 2 2 2217 Power Supply P1 P2 Q uu iita 3 2 3 2 2 Onboard Switches and Indicators SW1 SW2 01 04 3 2 3 2 8 Programming Interfaces J30 J31 3 3 3 2 4 Loop Filter J82 J34 3 3 3 2 5 High Speed Outputs and Inputs J1 J4 J6 J11 J13 J14 J22 and J23 3 3 3 2 VCXO Inputs and Outputs 16 18 3 4 3 27 AC Coupling at PRI REF C1 R4 and SEC REF C5 R13 R15 3 4 Serial Peripheral Interface SPI 4 1 4 1 Functional Description oe ERR REEL E Y 4 2
20. lock to the reference clock input PRI REF pin A1 or SEC REF pin B1 For default setting the reference clock must be 1 8 of the VC X O frequency If REF SEL is set to 1 then PRI REF is selected If REF SEL is set to 0 then SEC REF is selected This selection can be realized via J26 header 1 and 2 is high header 2 and 3 is low Connect YO YOB or Y1 Y1B to oscilloscope in order to check an output signal Ensure the oscilloscope has 50 Q to ground termination After power up D1 is on if there is a valid reference clock and D2 is on if there is a valid VC X O clock for the CDCM7005 If D3 turns on then the reference clock and the VC X O clocks are phase locked 2 1 Chapter 3 EVM Hardware This chapter discusses the EVM hardware Topic Page 3 1 Board View and Connector Location 3 2 3 2 Hardware Configuration 3 2 3 1 Board View and Connector Location 3 1 Board View and Connector Location Figure 3 1 Board View PRI REF V CTRL L N samaq rm s Ux 3 2 Hardware Configuration This section describes the board configuration using on board jumpers and solder bridges 3 2 1 Power Supply P1 P2 Supply 3 3 V 1096 on P1 and P2 using a stabilized external power supply B WARNING Never supply more than 3 6 V on P1 3 2 2 Onboard Switches and Indicators SW1 SW2 D1 D4 Push SW1 to enter the power down
21. mode of the CDCM7005 device Then all current sources are switched off all outputs are switched into 3 state and all dividers M N and P are reset to default Push SW to enter the reset mode of the device The charge pump CP is switched to 3 state and all counters N M P are rest to zero the initial divider settings are maintained in SPI The three status outputs of the CDCM7005 are fed to LED indicators D1 on indicates a valid reference input clock signal D2 is on if the VC X O input clock is valid and D3 turns on if the PLL has been locked J 04 indicates power supply p M Note In case of a low input impedance of the VC X O control voltage input there is a possibility D3 may not turn on to indicate locking 3 2 Hardware Configuration 3 2 3 Programming Interfaces J30 J31 The SPI of the device is used for writing to the control register of the device It consists of three control lines CTRL_CLK CTRL DATA and CTRL LE There are four 30 bit wide RAM registers which can be addressed by the two LSBs of a transferred word Every transmitted word must have 32 bits starting with MSB After supplying power or activating the power down mode the registers are loaded with the device default values internally see the CDCM7005 data sheet SCAS793 However if specific register settings are required for any applications there are two ways to program the device externally
22. r 2 pos 0 1 ctr 35 1 J30 dcon25m PARALLEL SPC Technology PORT DB 25P PCB 36 J31 HDR4 Header 4 pos 0 1 ctr 37 2 J33 J32 JUMPER3 SMD CD HDR 3_cdc7005 Use 0 W to short pins C7005 see assy dwg 38 HORZ Headers pos 39 1 1 smd_cap_0603 75 Q at100 MHz Murata BLM18BA750SN1D 40 1 L2 smd_cap_0603 470 nH Murata LQW18ANR47J00D 41 2 14 13 smd_cap_0603 180 nH Panasonic ELJ FJR18JF2 42 3 L5 L7 smd_cap_0603 75 Q at 100 MHz Murata BLM18BA750SN1D 43 1 L8 smd_cap_0805 2 2 nH J W Miller Magnetics PM0805 2N2M 24 PWR IN SPC Technologies 845R a SPC Technologies 845B 46 18 R1 R2 R7 R9 smd res 0402 NU 100 Q Panasonic R10 R11 R16 ERJ 2RKF1000X R18 R20 R22 R24 R26 R27 R30 R35 R48 R50 47 2 R3 R12 smd res 0402 NU Panasonic Parts L ERJ 2GEJ510X ist Board Layout and Schematics 6 3 Parts List tem QTY Heference P Part Number pega 48 7 R4 R6 R13 R15 smd res 0402 100 Q Panasonic 49 R5 R8 R14 R17 smd res 0402 150 Q Panasonic 50 10 R25 R57 R59 smd_res_0402 10 Panasonic R60 R68 R71 ERJ 2RKF1002X R74 R75 51 R28 R45 smd_res_0402 0Q Panasonic 52 R29 R32 R49 smd res 0402 150 Q Panasonic 53 R38 R31 smd_res_0402 130 Q Panasonic 54 10 R33 R34 R41 smd_res_0402 00 Panasonic 55 2 R43 R36 smd_res_0402 Panasonic 56 smd res 0402 57 2 R39 R40 a 58 2 R47 R46 smd res 0402 NU 100 Panasonic ERJ 2RKF1000X 59 4 R51 R64 R66 smd res 0402 100 Panasonic R67
23. st have electronics training and observe good laboratory practice standards No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V and 3 6 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 45 The EVM is designed to operate properly with certain components above 60 as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devi
24. ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated EVM IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use As such the goods being provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety measures typically found in the end product incorporating the goods As a prototype this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive Should this evaluation kit not meet the specifications indicated in the EVM User s Guide the kit may be returned within 30 days from the date of delivery for a full refund T
25. typical LVPECL termination which requires Vcc 2 V as termination voltage The reason is to simplify the power supply scheme The device output s trace impedance is 50 Q and traces are matched in length All outputs have options for pullup and pulldown resistors EVM Hardware 3 3 Hardware Configuration When the CDCM7005 is powered up it defaults to five LVPECL outputs However this EVM is configured as follows YO Y2 LVPECL Y4 LVCMOS in addition Y4 has an option for a custom filter The reference input clock signal has to be applied to J1 or J6 The reference input clock signal can be sensed on J4 In this case close the bridge J5 the oscilloscope s 50 O may be used to terminate the 50 O trace The reference input clock sense line is matched to the LVPECL outputs line to avoid any additional delay offset The input is ac coupled C4 3 2 6 VC X O Inputs and Outputs J16 J18 The CDCM7005 requires an external VC X O in order to complete the PLL loop The VC X O adjusts the frequency and phase depending on the control voltage level coming from the loop filter and provide the input clock to the LVPECL block Another option would be to use an external source via J16 and J18 3 27 AC Coupling at PRI REF C1 R4 R6 and SEC REF C5 R13 R15 3 4 An ac coupling is provided at PRI REF and SEC REF to ease the use of the CDCM7005 with different signaling levels IVCMOS LVPECL LVDS However the ac
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