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Texas Instruments 3138 155 232931 User's Manual

1. backoff slot boundary as illustrated in transmitted using normal data Figure 24 transmission if desired N Q amp S A x gQ X Ro So af OS Z g ka Beacon network PPDU 12 Acknowledge symbol periods y Lge 12 symbol periods lt tik lt 32 symbol periods Non beacon PPDU Acknowledge network fe Lg tack 12 symbol periods Figure 24 Acknowledge frame timing ag TEXAS INSTRUMENTS SWRS041B Page 42 of 89 E Pisco Products from Texas Instruments 20 Radio control state machine CC2420 has a built in state machine that is used to switch between different operational states modes The change of state is done either by using command strobes or by internal events such as SFD detected in receive mode The radio control state machine states are shown in Figure 25 The numbers in brackets refer to the state number readable in the FSMSTATE status register Reading the FSMSTATE status register is primarily for test debug purposes Before using the radio in either RX or TX mode the voltage regulator and crystal oscillator must be turned on and become stable The voltage regulator and crystal oscillator start up times are given in the Electrical Specifications section on page 9 The crystal oscillator is controlled by accessing the SXOSCON SXOSCOFF command strobes The XOSC16M_STABLE bit in the status register returned during address
2. 8 RF_N FIFOP 29 Lt L81 a Fenn coa E AVDD_SW o c81 a SFD i i i NC DVDD1 8 26 i Sl i gt Dp gt g a i a NC S 5 lt g CDVDD3 3 ie ju is i w 1 is 5 iS lo Q a ne i 1 a a y Q 1 a ee fe ae cs fa 9 i z i z is me z 5 Q N N a a Q ie ou ie a 4 gt Mas R gt i i H H i i i H 9 1 ULISaY geo Figure 4 Typical application circuit with discrete balun for single ended operation ki TEXAS SWRS041B Page 21 of 89 INSTRUMENTS E Chipcon Products CC2420 from Texas Instruments 3 3 V Power E e LA 42 41 ATEST1 47 ATEST2_ 46 AVDD_IF1_44 VREG_IN 43 VREG_0U VREG_EN XOSC16_01 39 XOSC16_02 38 GND CC2420 SCLK Folded Bea RF En di l TXRX_SWITCH H FIFO ac Transceiver 9_ RF_N GND igital Interface NC YL ZIN AAAY ZL DAY aqay 6L auwn5 ana yg HYOD aasa 8L Ody ada saya ansa GL ZAIT daav Oz auwnod LZ ULaSaY Figure 5 Suggested application circuit with differential antenna folded dipole ki TEXAS SWRS041B Page 22 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments CN Single ended output Single ended output transmission line balun discrete balun 5 C391 27 pF 5 NPO 0402 27 pF 5 NPO 0402 27 pF 5 NPO 0402 L61 8 2 nH 5 7 5 nH 5 27 nH 5 Monolithic multilayer Monolithic multilayer 0402 Monolithic multilayer 040
3. PA_CURRENT 2 0 3 R W Current programming of the PA 0 3 current adjustment 2 current adjustment 1 current adjustment Nominal setting 1 current adjustment 2 current adjustment 3 current adjustment 4 current adjustment 4 Pe Output PA level 0 dBm ki TEXAS SWRS041B Page 66 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments RXCTRLO 0x16 Receive control register 0 RXMIXBUF_CUR 1 0 R W RX mixer buffer bias current 0 690uUA 1 980uA nominal 2 1 16mA 3 1 44mA 11 10 HIGH_LNA_GAIN 1 0 Controls current in the LNA gain compensation branch in AGC High gain mode 0 Compensation disabled 1 100 yA compensation current 2 300 pA compensation current Nominal 3 1000 pA compensation current _LNA_GAIN 1 0 Controls current in the LNA gain compensation branch in AGC Med gain mode _LNA_GAIN 1 0 R W Controls current in the LNA gain compensation branch in AGC Low gain mode _LNA_CURRE 1 0 Controls main current in the LNA in AGC Med gain mode _LNA_CURRE 1 0 Controls main current in the LNA in AGC Low gain mode HIGH_LNA_CURRENT 1 0 R W Controls main current in the LNA in AGC High gain mode 0 240 yA LNA current x2 1 480 yA LNA current x2 2 640 yA LNA current x2 3 1280 pA LNA current x2 ki TEXAS SWRS041B Page 67 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments RXCTRL1 0x17
4. first r8 r9 r410 r441 r42 r143 r44 r15 Figure 20 CC2420 Frame Check Sequence FCS hardware implementation 1 kis TEXAS INSTRUMENTS SWRS041B Page 38 of 89 E Pisco Products from Texas Instruments Length byte Data in RXFIFO n MPDU MPDU CC2420 RSSI eS eee r signed CRC Corr Bitnumber 7 6 5 4 3 2 7 01 me Correlation value unsigned Figure 21 Data in RXFIFO when MDMCTRLO AUTOCRC is set 17 RF Data Buffering CC2420 can be configured for different transmit and receive modes as set in the MDMCTRL1 TX_MODE and MDMCTRL1 RX_MODE control bits Buffered mode mode 0 will be used for normal operation of CC2420 while other modes are available for test purposes 17 1 Buffered transmit mode In buffered transmit mode TX_MODE 0 the 128 byte TXFIFO located in CC2420 RAM is used to buffer data before transmission A preamble sequence defined in the Frame Format section below is automatically inserted before the length field during transmission The length field must always be the first byte written to the transmit buffer for all frames Writing one or multiple bytes to the TXFIFO is described in the FIFO access section on page 31 Reading data from the TXFIFO is possible with RAM access but this does not remove the byte from the FIFO Transmission is enabled by issuing a STXON or STXONCCA command strobe
5. 1 requires O dB Wanted signal 82 dBm adjacent modulated channel at 10 MHz PER 1 as specified by 1 1 requires 30 dB Wanted signal 82 dBm adjacent modulated channel at 10 MHz PER 1 as specified by 1 1 requires 30 dB Wanted signal 82 dBm Undesired signal is an IEEE 802 15 4 modulated channel stepped through all channels from 2405 to 2480 MHz Signal level for PER 1 Wanted signal 82 dBm Undesired signal is an IEEE 802 15 4 modulated at the same frequency as the desired signal Signal level for PER 1 Wanted signal 3 dB above the sensitivity level CW jammer PER 1 Complies with EN 300 440 class 2 Conducted measurement in a 50 Q single ended load Measured according to EN 300 328 EN 300 440 class 2 FCC CFR47 Part 15 and ARIB STD T 66 Page 10 of 89 E Passar Products CC2420 from Texas Instruments Parameter Min Typ Max Unit Condition Note Frequency error tolerance 300 300 kHz Difference between centre frequency of the received RF signal and local oscillator frequency 1 requires 200 kHz Symbol rate error tolerance 120 ppm Difference between incoming symbol rate and the internally generated symbol rate 1 requires 80 ppm Data latency 3 us Processing delay in receiver Time from complete transmission of SFD until complete reception of SFD i e from SFD goes active on transmitter until active on receiver 6 4 R
6. CCA_HYST 2 0 CCA Hysteresis in dB values 0 through 7 dB CCA_MODE Reserved CCA 1 when RSSI_VAL lt CCA_THR CCA_HYST CCA 0 when RSSI_VAL 2 CCA_THR CCA 1 when not receiving valid IEEE 802 15 4 data CCA 0 otherwise CCA 1 when RSSI_VAL lt CCA_THR CCA_HYST and not receiving valid IEEE 802 15 4 data CCA 0 when RSSI_VAL 2 CCA_THR or receiving a packet In packet mode a CRC 16 ITU T is calculated and is transmitted after the last data byte in TX In RX CRC is calculated and checked for validity If AUTOACK is set all packets accepted by address recognition with the acknowledge request flag set and a valid CRC are acknowledged 12 symbol periods after being received The number of preamble bytes 2 zero symbols to be sent in TX mode prior to the SYNCWORD encoded in steps of 2 whe reset value of 2 is compliant with IEEE 802 15 4 since the 4 zero byte is included in the SYNCWORD 0 1 leading zero bytes not recommended 1 2 leading zero bytes not recommended 2 3 leading zero bytes IEEE 802 15 4 compliant 3 4 leading zero bytes 15 16 leading zero bytes ki TEXAS SWRS041B Page 64 of 89 INSTRUMENTS E epenn Products CC2420 from Texas Instruments MDMCTRL1 0x12 Modem Control Register 1 10 6 CORR_THR 4 0 Demodulator correlator threshold value required before SFD search Note that on early CC2420 versions the reset value was 0 DEMOD_AVG_MODE Frequency offset
7. SWRS041B CC2420 recognition This may be handled by using the FIFOP pin since this pin does not go active until the frame passes address recognition Figure 14 shows an example of pin activity when reading a packet from the RXFIFO In this example the packet size is 8 bytes IOCFGO FIFOP_THR 3 and MODEMCTRLO AUTOCRC is set The length will be 8 bytes RSSI will contain the average RSSI level during reception of the packet and FCS corr contains information of FCS check result and the correlation levels 14 3 RXFIFO overflow The RXFIFO can only contain a maximum of 128 bytes at a given time This may be divided between multiple frames as long as the total number of bytes is 128 or less If an overflow occurs in the RXFIFO this is signalled to the microcontroller by making the FIFO pin go inactive while the FIFOP pin is active Data already in the RXFIFO will not be affected by the overflow i e frames already received may be read out A SFLUSHRX command strobe is required after an RXFIFO overflow to enable reception of new data Note that the SFLUSHRX command strobe should be issued twice to ensure that the SFD pin goes back to its inactive state For security enabled frames the MAC layer must read the source address of the received frame before it can decide which key to use to decrypt or authenticate This data must therefore not be overwritten even if it has been read out of the RXFIFO by the microcontroll
8. a _ BALUN_CTRL signal controls whether the PA should receive its required external biasing 1 or not 0 by controlling the RX TX output switch R W RXTX signal controls whether the LO buffers 0 or PA buffers 1 should be used E Powerdown of prescaler W Powerdown of PA negative path Powerdown of PA positive path When PA_N_PD 1 and PA_P_PD 1 the up conversion mixers are in powerdown Powerdown of TX DACs XOSC16M_PD RXBPE_CAL PD Powerdown control of complex bandpass receive filter calibration oscillator Powerdown control of charge pump CS DENT Powerdown control of VCO I Q generator LO buffers RXBPE_ZPD O O PD Powerdown control of complex bandpass receive filter control of Powerdown control of complex bandpass receive filter bandpass receive filter LNAMIX_PD i Powerdown control of LNA down conversion mixers and front end bias AGCCTRL 0x23 AGC Control VGALGAIN OE GAIN_OE Use the VcA_GATN value during RX instead of the AGC value the VGA_GAIN value Use the VcA_GATN value during RX instead of the AGC value RX instead of the AGC value Y 4 ES GAIN When written VGA manual gain override value when read the currently used VGA gain setting 13 LNAMIX_GAINMODE LNA Mixer Gain mode override setting 1x0 l 0 Gain mode is set by AGC algorithm 1 Gain mode is always low gain 2 Gain mode is always med gain 3 Gain mode
9. 44 0 1604 66 33 99 Fax 49 0 8161 80 2045 Internet support ti com sc pic euro htm Japan Fax International 81 3 3344 5317 Domestic 0120 81 0036 Internet Email International support ti com sc pic japan htm Domestic www tij co jp pic ki TEXAS SWRS041B Page 88 of 89 INSTRUMENTS E peon Products from Texas Instruments Phone International Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand Fax Email Internet CC2420 886 2 23786800 Toll Free Number 1 800 999 084 800 820 8682 800 96 5941 91 80 51381665 Toll 001 803 8861 1006 080 551 2804 1 800 80 3973 0800 446 934 1 800 765 7404 800 886 1028 0800 006800 001 800 886 0010 886 2 2378 6808 tiasia ti com or ti china ti com support ti com sc pic asia htm 2007 Texas Instruments All rights reserved vy TEXAS INSTRUMENTS SWRS041B Page 89 of 89 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warr
10. Added reset values for several registers Some typographical changes Removed Chipcon specific Disclaimer Trademarks and Life Support Policy sections Ordering part number changed from CC2420 RTB2 and CC2420 RTR2 to CC2420Z RTB1 and CC2420Z RTR1 respectively Important New recommended setting for RXBPF_LOCUR in RXCTRL1 0x17 use 1 instead of reset value 0 Updated address information Added new balun circuit with transmission lines in section Application Circuit Updated electrical specifications with measured data on CC2420 EM with new balun Updated values and figure for suggested application circuit with folded dipole antenna Corrected values for capacitors in Table 2 discrete balun Added data latency figure in receiver specification Updated crystal oscillator start up time Updated PLL loop filter bandwidth Updated adjacent channel rejection figures Updated current consumption for RX mode Typographical errors corrected in text and figures Removed comment about tuning capacitor for crystal oscillator Added statement that RAM access shall not be used for FIFO access Added more details about RSSI Clarified the interpretation of a programmed synchronisation word Updated purchasing information Updated soldering standard Added chapter numbering and split table for electrical specifications for readability Gathered and added information related to pin configurations in section 13 Included TX_UNDERFLOW and RX_
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12. address recognition is disabled or is successful the SFD pin goes inactive again only after the last byte of the MPDU has been received lf the received frame fails address recognition the SFD pin goes inactive immediately This is illustrated in Figure 13 The FIFO pin is active when there are one or more data bytes in the RXFIFO The first byte to be stored in the RXFIFO is the length field of the received frame i e the FIFO pin goes active when the length field is written to the RXFIFO The FIFO pin then remains active until the RXFIFO is empty If a previously received frame is completely or partially inside the RXFIFO the FIFO pin will remain active until the RXFIFO is empty The FIFOP pin is active when the number of unread bytes in the RXFIFO exceeds the threshold programmed into IOCFGO FIFOP_THR When address recognition is enabled the FIFOP pin will remain inactive until the incoming frame passes address recognition even if the number of bytes in the RXFIFO exceeds the programmed threshold The FIFOP pin will also go active when the last byte of a new packet is received even if the threshold is not exceeded If so the FIFOP pin will go inactive once one byte has been read out of the RXFIFO When address recognition is enabled data should not be read out of the RXFIFO before the address is completely received since the frame may be automatically flushed by CC2420 if it fails address kis TEXAS INSTRUMENTS
13. dipole is used the balun can be omitted If the antenna also provides a DC path from the TXRX_SWITCH pin to the RF pins inductors are not needed for DC bias Figure 5 shows a suggested application circuit using a differential antenna The antenna type is a standard folded dipole The dipole has a virtual ground point hence bias is provided without degradation in antenna performance 9 2 Bias resistor The bias resistor R451 is used to set an accurate bias current 9 3 Crystal An external crystal with two loading capacitors C381 and C391 is used for the crystal oscillator See page 53 for details 9 4 Voltage regulator The on chip voltage regulator supplies all 1 8 V power supply inputs C42 is required for stability of the regulator A series resistor may be used to comply with the ESR requirement 9 5 Power supply decoupling and filtering Proper power supply decoupling must be used for optimum performance The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application Texas Instruments provides a compact reference design that should be followed very closely Page 19 of 89 E pon Products CC2420 from Texas Instruments C C391 16MHz crystal load capacitor see page 53 DC bias and match DC bias and match L81 Balun and match Precision resistor for current reference generator 16MHz crystal see page 53
14. equal to OxFFFF in which case the beacon frame shall be accepted regardless of the source PAN identifier e f a destination PAN identifier is included in the frame it shall match macPANld or shall be the broadcast PAN identifier OxXFFFF e f a short destination address is included in the frame it shall match either macShortAddress or the broadcast address OxFFFF Otherwise if an extended destination address is included in the frame it shall match aExtendedAddress e f only source addressing fields are included in a data or MAC command frame the frame shall only be accepted if the device is a PAN coordinator and the source 19 Acknowledge Frames CC2420 includes hardware support for transmitting acknowledge frames as specified in 1 Figure 23 shows the format of the acknowledge frame If MDMCTRLO AUTOACK is enabled an acknowledge frame is transmitted for all incoming frames accepted by the address kis TEXAS INSTRUMENTS SWRS041B CC2420 PAN identifier macPANId matches If any of the above requirements are not satisfied and address recognition is enabled CC2420 will disregard the incoming frame and flush the data from the RXFIFO Only data from the rejected frame is flushed data from previously accepted frames may still be in the RXFIFO The IOCFGO BCN_ACCEPT control bit must be set when the PAN identifier programmed into CC2420 RAM is equal to OxFFFF and cleared otherwise This particula
15. is based on Packet Error Rate PER measurements instead of BER This is a more accurate measurement of the true RF performance since it mirrors the way the actual system operates It is recommended to perform PER measurements instead of BER measurements to evaluate the performance of IEEE 802 15 4 systems To do PER measurements the following may be used as a guideline e A valid preamble SFD and length field must be used for each packet e The PSDU see Figure 17 on page 36 length should be 20 bytes for sensitivity measurements as specified by 1 e The sensitivity limit specified by 1 is the RF level resulting in a 1 PER The packet sample space for a given measurement must then be gt gt 100 to have a sufficiently large sample space E g at least 1000 packets should be used to measure the sensitivity e The data transmitted over air must be spread according to 1 and the description on page 24 Pre generated packets may be used although 1 requires that the PER is averaged over random PSDU data e The CC2420 receive FIFO may be used to buffer data received during PER measurements since it is able to buffer up to 128 bytes e The MDMCTRL1 CORR_THR control register is by default set to 20 as described in the Demodulator Symbol Synchroniser and Data Decision section Page 58 of 89 E a Products from Texas Instruments e The RXCTRL1 RXBPF_LOCUR control bit should be set to 1 The simpl
16. se SCLK A Write to regist ler RKFIFO al oo X AS X aa X AB YA X A X a0 X Gy Do OG E EE De Ea X Du KDB X DB X Dut X Du X Du2 X Out X Du x so 9200 105 1 GP j X T f T im w Write tol TXFIFO A3 A1 al LOCKE X X 292000006 Y AZ AO X Dy DE a 5X Dw4 X Dw NG ao ae Ww X Dw Ke NG 5 Ow AX Dw I xa 1X Dw o x X E X s7 100000 ay S7 ee ss K 82 XS aM S7 Read from register RXFIFO a 9 X 1 Veo CC EP ED X so lt 87 X s6 X S5 X s4 X s3 X s2 X S1 X so XK D15 Xo Da DO Da de oe 9X D8 XK _D 7 a a 5 X Da4 X Dr ya ae ya ONDA 15 Read ar ll one byte tb RAM multiple rpad writes alsp possible si 1 Xm X A5 X44 YAS Ym X At X40 y x 81 X BO X o Yx Y x X x x X X EAE DADA X so STK SKS KS KS KS x Da 29 G9 9 9 Cr A Cx i Read orfe byt from RAM multiple reads alo pogsible SI eB C2 C2 C2 C2 OOO EDEDED ER ES l l x so 300000500 Parameter Symbol SCLK clock Fscik frequency SCLK low pulse duration SCLK high pulse duration y x Dp7 EN LE Dat D3 D2VD 1 DO Figure 9 SPI timing diagram The minimum time CSn must be low before the first positive
17. transmit mode The SFD and CCA pins retain their normal operation also in serial mode CC2420 will remain in serial transmit mode until transmission is turned off manually In serial receive mode MDMCTRL1 RX_MODE 1 byte synchronisation is still performed by CC2420 This means that the FIFOP clock pin will remain inactive until a start of Incoming outgoing RF data Transmit mode FIFOP frame delimiter has been detected Preamble SFD s0 s1 s2 4 us gt e JUL FIFO from uC Receive mode FIFOP bo b1 b2 b3 ba bs be b7 be Y bo b10 b11 bs bo Y b10 b11 FIFO from CC2420 bo ot b2 Y b3 Figure 22 Unbuffered test mode pin activity ag TEXAS INSTRUMENTS SWRS041B Page 40 of 89 bay E Pisco Products from Texas Instruments 18 Address Recognition CC2420 includes hardware support for address recognition as specified in 1 Hardware address recognition may be enabled disabled using the MDMCTRLO ADR_DECODE control bit Address recognition is based on the following requirements listed from section 7 5 6 2 in 1 e The frame type subfield shall not contain an illegal frame type e If the frame type indicates that the frame is a beacon frame the source PAN identifier shall match macPANld unless macPANld is
18. 0x20 FSMTC R W Finite State Machine Time Constants 0x21 MANAND R W Manual signal AND override register 0x22 MANOR R W Manual signal OR override register 0x23 AGCCTRL R W AGC Control Register 0x24 AGCTSTO R W AGC Test Register 0 0x25 AGCTST1 R W AGC Test Register 1 0x26 AGCTST2 R W AGC Test Register 2 0x27 FSTSTO R W Frequency Synthesizer Test Register 0 0x28 FSTST1 R W Frequency Synthesizer Test Register 1 0x29 FSTST2 R W Frequency Synthesizer Test Register 2 0x2A FSTST3 R W Frequency Synthesizer Test Register 3 0x2B RXBPFTST R W Receiver Bandpass Filter Test Register 0x2C FSMSTATE R Finite State Machine State Status Register 0x2D ADCTST R W ADC Test Register 0x2E DACTST R W DAC Test Register 0x2F TOPTST R W Top Level Test Register 0x30 RESERVED R W Reserved for future use control status register 0x31 Not used 0x3D Ox3E TXFIFO W Transmit FIFO Byte Register 0x3F RXFIFO R W Receiver FIFO Byte Register R W Read write control status R Read only W Write only S Command Strobe perform action upon access Table 11 Configuration registers overview ki TEXAS SWRS041B Page 62 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments MAIN 0x10 Main Control Register Active low reset of the entire circuit should be applied before doing anything else Equivalent to using the RESETn reset pin ee Active low reset of the encryption module Test purposes only SETn EMOD_RESETn R W Ac
19. 16 MHz Crystal oscillator pin 2 XOSC16_Q1 Analog I O 16 MHz Crystal oscillator pin 1 or external clock input Pao xe 41 VRE zZ m pu ua Ry Aa H mj O D1 8 Power digital 1 8 V Power supply for digital core Not Connected G_EN Digital input Voltage regulator enable active high held at VREG_IN voltage level when active Note that VREG_EN is relative VREG_IN not DVDD3 3 VREG_OUT VREG_IN AVDD_IF1 R BTAS ATEST2 ATESTI AVDD_CHP Power analog 1 8 V Power supply for phase detector and charge pump NOTES The exposed chip die attach pad must be connected to a solid ground plane as this is the main ground connection for the ki TEXAS SWRS041B Page 16 of 89 INSTRUMENTS E Pisco Products from Texas Instruments 8 Circuit Description CC2420 DIGITAL DEMODULATOR Digital RSSI Serial Gain Control voltage Image Suppression regulator Channel Filtering Demodulation Frame _ _TX RX CONTROL synchronization DIGITAL INTERFACE WITH FIFO BUFFERS CRC AND ENCRYPTION CONTROL LOGIC Serial microcontroller Control DIGITAL MODULATOR Digital and Analog test interface Data spreading Modulation On chip BIAS Figure 2 CC2420 simplified block diagram A simplified block diagram of CC2420 is shown in Figure 2 CC2420 features a low IF receiver The received
20. 4 1 1 2 1 2 Start of Frame Frame Data Frame Check Preamble ne Frame Sequence Delimiter Length Control Field Sequence Sequence SFD FCF Number FCS Synchronisation Header PHY Header MAC Header MHR MAC Footer SHR PHR MFR Figure 23 Acknowledge frame format 1 Two command strobes SACK and SACKPEND are defined to transmit acknowledge frames with the frame pending field cleared or set respectively The acknowledge frame is only transmitted if the CRC is valid For systems using beacons there is an additional timing requirement that the acknowledge frame transmission should be started on the first backoff slot boundary 20 symbol periods at least 12 symbol periods after the last symbol of the incoming frame This timing must be controlled by the microcontroller by issuing the SACK and SACKPEND command strobe 12 symbol periods before the following If a SACK or SACKPEND command strobe is issued while receiving an incoming frame the acknowledge frame is transmitted 12 symbol periods after the last symbol of the incoming frame This should be used to transmit acknowledge frames in non beacon networks This timing is also illustrated in Figure 24 Using SACKPEND will set the pending data flag for automatically transmitted acknowledge frames using AUTOACK The pending flag will then be set also for future acknowledge frames until a SACK command strobe is issued Acknowledge frames may be manually
21. 42 1 Document History 42 2 Product Status Definitions 43 Address Information 44 TI Worldwide Technical Support us TEXAS INSTRUMENTS SWRS041B Page 4 of 89 E Chipcon Products CC2420 from Texas Instruments 1 Abbreviations ADC AES AGC ARIB TEXAS INSTRUMENTS Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Association of Radio Industries and Businesses Bit Error Rate Cipher Block Chaining Message Authentication Code Clear Channel Assessment Counter mode CBC MAC Code of Federal Regulations Carrier Sense Multiple Access with Collision Avoidance Counter mode encryption Continuous Wave Digital to Analog Converter Direct Sequence Spread Spectrum Electro Static Discharge Equivalent Series Resistance Error Vector Magnitude Federal Communications Commission Frame Control Field First In First Out FIFO and Frame Control High Speed Serial Debug Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific and Medical International Telecommunication Union Telecommunication Standardization Sector Input Output In phase Quadrature phase kilo bits per second Low Noise Amplifier Local Oscillator Link Quality Indication Least Significant Bit Byte Medium Access Control MAC Footer MAC Header Message Integrity Code MAC Protocol Data Unit MAC Service Data Unit Not Available Not Connected Offs
22. 6 7 Digital Inputs Outputs 12 6 8 Voltage Regulator 13 6 9 Battery Monitor 13 6 10 Power Supply 13 7 Pin Assignment 15 8 Circuit Description 17 9 Application Circuit 19 9 1 Input output matching 19 9 2 Bias resistor 19 9 3 Crystal 19 9 4 Voltage regulator 19 9 5 Power supply decoupling and filtering 19 10 IEEE 802 15 4 Modulation Format 24 11 Configuration Overview 25 12 Evaluation Software 26 13 4 wire Serial Configuration and Data Interface 27 13 1 Pin configuration 27 13 2 Register access 27 13 3 Status byte 28 13 4 Command strobes 29 13 5 RAM access 29 13 6 FIFO access 31 13 7 Multiple SPI access 31 14 Microcontroller Interface and Pin Description 32 14 1 Configuration interface 32 142 Receive mode 33 143 RXFIFO overflow 33 144 Transmit mode 34 145 General control and status pins 35 15 Demodulator Symbol Synchroniser and Data Decision 35 16 Frame Format 36 16 1 Synchronisation header 36 16 2 Length field 37 16 3 MAC protocol data unit 37 16 4 Frame check sequence 38 ki TEXAS SWRS041B INSTRUMENTS Page 2 of 89 E oe Products from Texas Instruments 17 RF Data Buffering CC2420 17 1 Buffered transmit mode 17 2 Buffered receive mode 17 3 Unbuffered serial mode 18 Address Recognition 19 Acknowledge Frames 20 Radio control state machine 21 MAC Security Operations Encryption and Authentication 21 1 Keys 21 2 Nonce counter 21 3 Stand alone encryption 21 4
23. CC2420 QLP48 package RoHS 43 tube compliant Pb free assembly in tubes with 43 pcs per tube CC2420 RTR1 CC2420RTCR Single chip RF Transceiver CC2420 QLP48 package RoHS 4000 tape and reel compliant Pb free assembly T amp R with 4000 pcs per reel CC2420Z RTB1 CC2420ZRTC Single chip RF Transceiver including royalty for using Tl s 43 tube ZigBee Software Stack Z Stack in an end product CC2420 QLP48 package RoHS compliant Pb free assembly in tubes with 43 pcs per tube CC2420Z RTR1 CC2420ZRTCR Single chip RF Transceiver including royalty for using Tl s 4000 tape and reel ZigBee Software Stack Z Stack in an end product CC2420 QLP48 package RoHS compliant Pb free assembly T amp R with 4000 pcs per reel ki TEXAS SWRS041B Page 85 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments 42 General Information 42 1 Document History SWRS041b 2007 03 19 SWRS041a 2006 12 18 SWRS041 2006 04 06 1 4 l vy TEXAS INSTRUMENTS Slightly changed optimum load impedance on Page 9 and 19 to better describe the Application circuit Updated ordering information Updated address information Typical data latency changed from 2 to 3 us Updates reflecting the programmable polarity of FIFO FIFOP SFD and CCA pins Clarification relating to VREG_EN as digital input BATT_OK changed to BATTMON_OK for consistency MANFIDH VERSION register reset value changed to current version is 3
24. E oa Products from Texas Instruments CC2420 2 4 GHz IEEE 802 15 4 ZigBee ready RF Transceiver Applications 2 4 GHz IEEE 802 15 4 systems ZigBee systems Home building automation Industrial Control Product Description The CC2420 is a true single chip 2 4 GHz IEEE 802 15 4 compliant RF transceiver designed for low power and low voltage wireless applications CC2420 includes a digital direct sequence spread spectrum baseband modem providing a spreading gain of 9 dB and an effective data rate of 250 kbps The CC2420 is a low cost highly integrated solution for robust wireless communication in the 2 4 GHz unlicensed ISM band It complies with worldwide regulations covered by ETSI EN 300 328 and EN 300 440 class 2 Europe FCC CFR47 Part 15 US and ARIB STD T66 Japan The CC2420 provides extensive hardware support for packet handling data buffering burst transmissions data encryption data authentication clear channel assessment link quality indication and packet timing information These Key Features e True single chip 2 4 GHz IEEE 802 15 4 compliant RF transceiver with baseband modem and MAC support e DSSS baseband modem with 2 MChips s and 250 kbps effective data rate e Suitable for both RFD and FFD operation e Low current consumption RX 18 8 mA TX 17 4 mA e Low supply voltage 2 1 3 6 V with integrated voltage regulator e Low supply voltage 1 6 2 0 V with external voltage regula
25. FIFO as will be described in the Microcontroller Interface and Pin Description section on page 32 Note that the FIFO and FIFOP pins only apply to the RXFIFO The TXFIFO has its underflow flag in the status byte The TXFIFO may be flushed by issuing a SFLUSHTX command strobe Similarly a SFLUSHRX Command strobe will flush the receive FIFO 13 7 Multiple SPI access Register access command strobes FIFO access and RAM access may be issued continuously without setting Csn high E g the user may issue a command strobe a register write and writing 3 bytes to the TXFIFO in one operation as illustrated in Figure 11 The only exception is that FIFO and RAM access must be terminated by setting CSn high Page 31 of 89 E Pisco Products from Texas Instruments CC2420 CSn gs ADDR X ADDR X X XA DD Rix eX DATA ope ATA apor JOATA spon so Status X Status X DATAsmss X DATA sg X Status X Status X Status X Status Command Register Strobe Read TXFIFO Write Figure 11 Multiple SPI Access Example 14 Microcontroller Interface and Pin Description When used in a typical system CC2420 will interface to a microcontroller This microcontroller must be able to e Program CC2420 into different modes read and write buffered data and read back status information via the 4 wire SPI bus configuration interface ST SO SCLK and Csn e Interface to the receive and transmit FIFOs using the FIFO and
26. FIFOP status pins e Interface to the cca pin for clear channel assessment e Interface to the SFD pin for timing information particularly for beaconing networks 14 1 Configuration interface A CC2420 to microcontroller interface example is shown in Figure 12 The microcontroller uses 4 I O pins for the SPI CC2420 configuration interface SI SO SCLK and CSn SO should be connected to an input at the microcontroller ST SCLK and CSn must be microcontroller outputs Preferably the microcontroller should have a hardware SPI interface The microcontroller pins connected to SI SO and SCLK can be shared with other SPl interface devices so is a high impedance output as long as CSn is not activated active low csn should have an external pull up resistor or be set to a high level when the voltage regulator is turned off in order to prevent the input from floating SI and SCLK should be set to a defined level to prevent the inputs from floating uC FIFO GIOO FIFOP Interrupt CCA SY GI01 SFD gt Timer Capture CSn K _ GIO2 sl MOSI SO SCLK MISO SCLK Figure 12 Microcontroller interface example kis TEXAS INSTRUMENTS SWRS041B Page 32 of 89 E Pisa Products from Texas Instruments 14 2 Receive mode In receive mode the SFD pin goes active after the start of frame delimiter SFD field has been completely received If
27. Fully equipped development kit e Demonstration board reference design with microcontroller code e Easy to use software for generating the CC2420 configu ration data Small size QLP 48 package 7 x 7 mm Complies with EN 300 328 EN 300 440 class 2 FCC CFR47 part 15 and ARIB STD T66 Page 7 of 89 E Pisa Products CC2420 from Texas Instruments 4 Absolute Maximum Ratings Units Condition Parameter Supply voltage for on chip voltage regulator VREG_IN pin 43 Supply voltage VDDIO for digital l Os DVDD3 3 pin 25 Supply voltage VDD on AVDD_VCO DVDD1 8 etc pin no 1 2 3 4 10 14 15 17 18 20 26 35 37 44 and 48 Voltage on any digital O pin pin no 21 27 34 f VDDIO 0 3 max 3 6 and 41 Voltage on any other pin pin no 6 7 8 11 12 VDD 0 3 max 2 0 13 16 36 38 39 40 45 46 and 47 The absolute maximum ratings given the limiting values may cause permanent above should under no circumstances be damage to the device violated Stress exceeding one or more of Caution ESD sensitive device Precaution should be used when handling the device in order to prevent permanent damage 5 Operating Conditions Parameter sd Min Typ Max Units Condition Supply voltage for on chip voltage regulator 2 1 3 6 V VREG_IN pin 43 Supply voltage VDDIO for digital l Os DVDD3 3 1 6 3 6 V The digital I O voltage DVDD3 3 pin pin 25 must match the external in
28. MHz RF Transceiver e Direct Sequence Spread Spectrum DSSS transceiver e 250 kbps data rate 2 MChip s chip rate e O QPSK with half sine pulse shaping modulation e Very low current consumption RX 18 8 mA TX 17 4 mA e High sensitivity 95 dBm e High adjacent channel rejection 30 45 dB e High alternate channel rejection 53 54 dB e On chip VCO LNA and PA e Low supply voltage 2 1 3 6 V with on chip voltage regulator e Programmable output power e 1 Q low IF soft decision receiver e Q direct up conversion transmitter Separate transmit and receive FIFOs e 128 byte transmit data FIFO e 128 byte receive data FIFO Very few external components e Only reference crystal and a minimised number of passives e No external filters needed Easy configuration interface e 4 wire SPI interface e Serial clock up to 10 MHz SWRS041B CC2420 802 15 4 MAC hardware support e Automatic preamble generator e Synchronisation word insertion detection e CRC 16 computation and checking over the MAC payload Clear Channel Assessment Energy detection digital RSSI Link Quality Indication Full automatic MAC security CTR CBC MAC CCM 802 15 4 MAC hardware security e Automated security operations within the receive and transmit FIFOs e CTR mode encryption decryption e CBC MAC authentication e CCM encryption decryption and authentication e Stand alone AES encryption Development tools available e
29. Receive control register 1 EOS RXBPF_LOCUR R W Controls reference bias current to RX bandpass filters 0 4 uA Reset value Use 1 instead 1 3 uA Note Recommended setting RXBPF_MIDCUR Controls reference bias current to RX bandpass filters 0 4 uA Default 1 3 5uA EXEC E ET CES EN ON EOS cis 1 fv sn ronson oe o ava Rx tien gan nee setgin AGE medum gan mee LNA_CAP_ARRAY 1 0 1 Selects varactor array setting in the LNA 0 OFF 1 0 1pF x2 Nominal 2 0 2pF x2 3 0 3pF x2 RXMIX_VCM 1 0 1 R W Controls VCM level in the mixer feedback loop 0 8 pA mixer current 1 12 pA mixer current Nominal 2 16 pA mixer current 3 20 pA mixer current RXMIX_CURRENT 1 0 2 R W Controls current in the mixer 0 360 pA mixer current x2 1 720 yA mixer current x2 2 900 yA mixer current x2 Nominal 3 1260 pA mixer current x2 5 4 RXMIX_TAIL 1 0 1 R W Control of the receiver mixers output current 0 12 pA 1 16 pA Nominal 2 20 pA 3 24 yA ki TEXAS SWRS041B Page 68 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments FSCTRL 0x18 Frequency Synthesizer Control and Status 15 14 LOCK_THR 1 0 Number of consecutive reference clock periods with successful synchronisation windows required to indicate lock 0 64 1 128 recommended 2 256 3 512 Calibration has been performed since the last time the frequency synthesizer was turned on Calibration status 1
30. See the Radio control state machine section on page 43 for an illustration of how the transmit command strobes affect the state of CC2420 The STXONCCA strobe is ignored if the channel is busy See the Clear Channel Assessment section on page 50 for details on CCA The preamble sequence is started 12 symbol periods after the command strobe After the programmable start of frame delimiter has been transmitted data is fetched from the TXFIFO xi TEXAS INSTRUMENTS SWRS041B A TXFIFO underflow is issued if too few bytes are written to the TXFIFO Transmission is then automatically stopped The underflow is indicated in the TX_UNDERFLOW status bit which is returned during each address byte and each byte written to the TXFIFO The underflow bit is only cleared by issuing a SFLUSHTX command strobe The TXFIFO can only contain one data frame at a given time After complete transmission of a data frame the TXFIFO is automatically refilled with the last transmitted frame Issuing a new STXON or STXONCCA command strobe will then cause CC2420 to retransmit the last frame Writing to the TXFIFO after a frame has been transmitted will cause the TXFIFO to be automatically flushed before the new byte is written The only exception is if a TXFIFO underflow has occurred then a SFLUSHTX command strobe is required 17 2 Buffered receive mode In buffered receive mode RX_MODE 0 the 128 byte RXFIFO located in CC2420 RAM is used
31. Table 1 Overview of external components 3 3V Power supply o C391 C381 C42 R451 Hh XTAL me A Eon co o a SH gt eee E E 4 fy H D t a a a d 2 eo 7 2 4 wl o d a a E 4 8 Eg E 3 u R gt e a a 1 154 E gt o o a VCO_GUARD x x e z AVDD_VCO DVDD_RAM Antenna 3_ AVDD_PRE sn 50 Ohm AVDD_RF1 sI m GND CC2420 SCLK C81 L81 on RF csn VA TXRX_SWITCH FIFO in i Transceiver ar io E ios E iD ia NC f AAA 61 avn anoa Yg maoo ansa z a os o lo Si YL cat ddA ZL OAW ddaw DAY dana SGL Zar Figure 3 Typical application circuit with transmission line balun for single ended operation ki TEXAS SWRS041B Page 20 of 89 INSTRUMENTS E Chipcon Products CC2420 from Texas Instruments 3 3 V Power supply T T gt 0 C391 C381 est lo HIIR C42 XTAL A i ER l colo o NN A NN E co H q y cn bo i A Lal N N fal Z E Z V a N o i T E E f iu H D E a a a a 1 Sy se 6 2 El El a 1 o oO so wo n J 2 5 E 4 a E E k o DR i gt 14 gt a a 1 i 4 E gt o o a VCO_GUARD IN NC 36 A AVDD_VCO DVDD_RAM 34 Antenna AVDD_PRE so o 50 Ohm Say AVDD_RF1 SI oe c61 1 GND CC2420 SCLK O C62 cry 1626 a RF Ese E Ty TXRX_SWITCH Transceiver FIFO 30 o Digital Interface
32. Texas Instruments 27 VCO and PLL Self Calibration 27 1 VCO The VCO is completely integrated and operates at 4800 4966 MHz The VCO frequency is divided by 2 to generate frequencies in the desired band 2400 2483 5 MHz 27 2 PLL self calibration The VCO s characteristics will vary with temperature changes in supply voltages and the desired operating frequency 28 Output Power Programming The RF output power of the device is programmable and is controlled by the TXCTRL PA_LEVEL register Table 9 shows the output power for different CC2420 In order to ensure reliable operation the VCO s bias current and tuning range are automatically calibrated every time the RX mode or TX mode is enabled i e in the RX_CALIBRATE TX_CALIBRATE and TX_ACK_CALIBRATE control states in Figure 25 on page 44 settings including the complete programming of the TXCTRL control register The typical current consumption is also shown PA_LEVEL TXCTRL register Output Power dBm Current Consumption mA 31 OxAOFF 0 17 4 27 OxAOFB 1 16 5 23 OxAOF7 3 15 2 19 OXAOF3 5 13 9 15 OxAOEF 7 125 11 OxAO0EB 10 11 2 7 OxAOE7 15 9 9 3 OxA0E3 25 8 5 Table 9 Output power settings and typical current consumption 2 45 GHz 29 Voltage Regulator CC2420 includes a low drop out voltage regulator This is used to provide a 1 8 V power supply to the CC2420 power supplies The vo
33. and supply the best possible product No Identification Noted Full Production This data sheet contains the final specifications Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Chipcon The data sheet is printed for reference information only ki TEXAS SWRS041B Page 87 of 89 INSTRUMENTS E oa Products from Texas Instruments 43 Address Information Texas Instruments Norway AS Gaustadall en 21 N 0349 Oslo NORWAY Tel 47 22 95 85 44 Fax 47 22 95 85 46 Web site http www ti com lpwrf 44 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page TI Semiconductor KnowledgeBase Home Page Product Information Centers CC2420 support ti com support ti com sc knowledgebase Americas Phone Fax Internet Email 1 972 644 5580 1 972 927 6377 support ti com sc pic americas htm Europe Middle East and Africa Phone Belgium English Finland English France Germany Israel English Italy Netherlands English Russia Spain Sweden English United Kingdom 32 0 27 45 54 32 358 0 9 25173948 33 0 130 70 11 64 49 0 8161 80 33 11 180 949 0107 800 79 11 37 31 0 546 87 95 45 7 0 95 363 4824 34 902 35 40 28 46 0 8587 555 22
34. average filter behaviour 0 Lock frequency offset filter after preamble match 1 Continuously update frequency offset filter MODULATION_MODE Set one of two RF modulation modes for RX TX 0 IEEE 802 15 4 compliant mode 1 Reversed phase non IEEE compliant could be used to set up a system which will not receive 802 15 4 packets Set test modes for TX 0 Buffered mode use TXFIFO normal operation 1 Serial mode use transmit data on serial interface infinite transmission For lab testing only 2 TXFIFO looping ignore underflow in TXFIFO and read cyclic infinite transmission For lab testing only 3 Send random data from CRC infinite transmission For lab testing only Set test mode of RX 0 Buffered mode use RXFIFO normal operation 1 Receive serial mode output received data on pins Infinite RX For lab testing only 2 RXFIFO looping ignore overflow in RXFIFO and write cyclic infinite reception For lab testing only 3 Reserved RSSI 0x13 RSSI and CCA Status and Control Register 15 8 CCA_THR 7 0 32 R W Clear Channel Assessment threshold value signed number on 2 s complement for comparison with the RSSI The unit is 1 dB offset is the same as for RSSI_VAL The CCA signal goes active when the received signal is below this value The CCA signal is available on the CCA pin The reset value is approximately 77 dBm 7 0 RSSI_VAL 7 0 128 R RSSI estimate on a logarithmic sca
35. bit 1 16 AGC_VGA_GAIN 1 VGA gain setting bit 1 17 VGA_RESET_N VGA peak detector reset sign active low 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 CLK_8M 8 MHz clock signal output 24 XOSC16M_STABLE MHz crystal oscillator stabilised same as the status bit in Table 25 FSDIG_FREF Frequency synthesizer 4 MHz reference signal 26 FSDIG_FPLL Frequency synthesizer 4 MHz divided signal 27 FSDIG_LOCK_WINDOW Frequency synthesizer lock window 28 WINDOW_SYNC Frequency synthesizer synchronized lock window 29 CLK_ADC ADC clock signal 1 30 ZERO Low 31 ONE High Table 12 CCA test signal select table ki TEXAS SWRS041B Page 81 of 89 INSTRUMENTS E Pisco Products from Texas Instruments CC2420 SFDMUX Signal output on SFD pin Description 0 SFD Normal operation 1 ADC_1 0 ADC I branch LSB used for random number generation 2 DEMOD_RESYNCH_EARLY High one 16 MHz clock cycle each time the demodulator resynchronises early 3 LOCK_STATUS Lock status same as FSCTRL LOCK_STATUS 4 MOD_CHIP Chip rate data signal during transmission 5 MOD_SERIAL_DATA_OUT Bit rate data signal during transmission 6 FFCTRL_FS_PD Frequency synthesizer power down active high 7 FFCTRL_ADC_PD ADC power down active high 8 FFCTRL_VGA_PD VGA power down active high 9 FFCTRL_RXBPF_PD Receiver bandpass filter power down active high 10 FFCTRL_LNAMIX_PD R
36. by using the SAES command strobe The selected key SECCTRLO SEC_SAKEYSEL is then used to encrypt the plaintext written to the stand alone buffer Upon completion of the encryption operation the ciphertext is written back to the stand alone buffer thereby overwriting the plaintext Note that RAM write operations also output data currently in RAM so that a new plaintext may be written at the same time as reading out the previous ciphertext 21 4 In line security operations CC2420 can do MAC security operations encryption decryption and authentication on frames within the TXFIFO and RXFIFO These operations are called in line security operations As with other MAC hardware support within CC2420 in line security operation relies on the length field in the PHY header A correct length field must therefore be used for all security operations Wi TEXAS INSTRUMENTS SWRS041B The key nonce does not apply to CBC MAC and SECCTRLO and SECCTRL1 control registers must be correctly set before starting any in line security operation The in line security mode is set in SECCTRLO SEC_MODE to one of the following modes Disabled CBC MAC authentication CTR encryption decryption CCM authentication and encryption decryption When enabled TX in line security is started in one of two ways e Issue a STXENC command strobe In line security will be performed within the TXFIF
37. devices Optionally in a star network topology the FFD could be equipped with a more accurate crystal thereby relaxing the requirement on the RFD This can make sense in systems where the RFDs ship in higher volumes than the FFDs 34 4 Communication robustness CC2420 provides very good adjacent alternate and co channel rejection image frequency suppression and blocking properties The CC2420 performance is significantly better than the requirements imposed by 1 These are highly important parameters for reliable operation in the 2 4 GHz band since an increasing number of devices systems are using this license free frequency band 34 5 Communication security The hardware encryption and authentication operations in CC2420 enable secure communication which is required for many applications Security operations require a lot of data processing which is costly in an 8 bit microcontroller system The hardware support within CC2420 enables a high level of security even with a low cost 8 bit controller Page 57 of 89 E Pisco Products from Texas Instruments 34 6 Low cost systems As the CC2420 provides 250 kbps multi channel performance without any external filters a very low cost system can be made A differential antenna will eliminate the need for a balun and the DC biasing can be achieved in the antenna topology 34 7 Battery operated systems In low power applications the CC2420 should be powered down w
38. is below threshold and not receiving valid IEEE 802 15 4 data Clear channel assessment is available on the CCA output pin CCA is active high but the polarity may be changed by setting the IOCFGO CCA_POLARITY control bit Implementing CSMA CA may easiest be done by using the STXONCCA command strobe as described in the Radio control state machine section on page 43 Transmission will then only start if the channel is clear The TX_ACTIVE status bit see Table 5 may be used to detect the result of the CCA 26 Frequency and Channel Programming The operating frequency is set by programming the 10 bit frequency word located in FSCTRL FREQ 9 0 The operating frequency Fc in MHz is given by Fo 2048 FSCTRL FREQ 9 0 MHz The frequency can be programmed with 1 MHz resolution In receive mode the actual LO frequency is Fc 2 MHz since a 2 MHz IF is used Direct conversion is used for transmission so here the LO frequency equals Fc The 2 MHz IF is automatically set by CC2420 so the frequency programming is equal for RX and TX ag TEXAS INSTRUMENTS SWRS041B IEEE 802 15 4 specifies 16 channels within the 2 4 GHz band in 5 MHz steps numbered 11 through 26 The RF frequency of channel k is given by 1 Fo 2405 5 k 11 MHz k 11 12 26 For operation in channel k the FSCTRL FREQ register should therefore be set to FSCTRL FREQ 357 5 k 11 Page 50 of 89 E Pisco Products from
39. is used TX Key select 0 Key 0 is used 1 Key 1 is used RX Key select 0 Key 0 is used 1 Key 1 is used Number of bytes in authentication field for CBC MAC encoded as M 2 2 0 Reserved Security mode 0 In line security is disabled 1 CBC MAC 2 CTR 3 CCM ki TEXAS SWRS041B Page 70 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments SECCTRL1 0x1A Security Control Register R W Multi purpose length byte for TX in line security operations CTR Number of cleartext bytes between length byte and the first byte to be encrypted CBC MAC Number of cleartext bytes between length byte and the first byte to be authenticated CCM l a defining the number of bytes to be authenticated but not encrypted Stand alone SEC_TXL has no effect Multi purpose length byte for RX in line security operations CTR Number of cleartext bytes between length byte and the first byte to be decrypted CBC MAC Number of cleartext bytes between length byte and the first byte to be authenticated CCM l a defining the number of bytes to be authenticated but not decrypted Stand alone SEC_RXL has no effect BATTMON 0x1B Battery Monitor Control register BATTMON_OK Battery monitor comparator output read only BATT_OK is valid 5 us after BATTMON_EN has been asserted and BATTMON_VOLTAGE has been programmed 0 Power supply lt Toggle Volt
40. parasitic capacitance is typically 2 pF 5 pF The crystal oscillator circuit is shown in Figure 30 Typical component values for different values of C are given in Table 10 The crystal oscillator is amplitude regulated This means that a high current is used to start up the oscillations When the amplitude builds up the current is reduced to what is necessary to maintain a stable oscillation This ensures a fast start up and keeps the drive level to a minimum The ESR of the crystal must be within the specification in order to ensure a reliable start up see the Electrical Specifications section Page 53 of 89 E Pisco Products from Texas Instruments XOSC16_Q1 a a XTAL C391 CC2420 XOSC16_Q2 C381 Figure 30 Crystal oscillator circuit Table 10 Crystal oscillator component values 32 Input Output Matching The RF input output is differential RF_N and RF_P In addition there is supply switch output pin TXRX_SWITCH that must have an external DC path to RF_N and RF_P In RX mode the TXRX_SWITCH pin is at ground and will bias the LNA In TX mode the TXRX_SWITCH pin is at supply rail voltage and will properly bias the internal PA The RF output and DC bias can be done using different topologies Some are shown in Figure 4 and Figure 5 33 Transmitter Test Modes CC2420 can be set into different transmit test modes for performance evaluation The test mode descriptions in the followin
41. transfer indicates whether the oscillator is running and stable or not see Table 5 This status register can be polled when waiting for the oscillator to start vy TEXAS INSTRUMENTS SWRS041B CC2420 For test purposes the frequency synthesizer FS can also be manually calibrated and started by using the STXCAL command strobe register This will not start a transmission before a STXON command strobe is issued This is not shown in Figure 25 Enabling transmission is done by issuing a STXON or STXONCCA command strobe Turning off RF can be accomplished by using one of the SRFOFF or SXOSCOFF command strobe registers After reset the CC2420 is in Power Down mode All configuration registers can then be programmed in order to make the chip ready to operate at the correct frequency and mode Due to the very fast start up time CC2420 can remain in Power Down until a transmission session is requested As also described in the 4 wire Serial Configuration and Data Interface section on page 27 the crystal oscillator must be running IDLE in order to have access to the RAM and FIFOs Page 43 of 89 Chipcon Products from Texas Instruments El CC2420 C Voltage Regulator on VREG_EN set low Sin Y VREG_EN set high Wait until voltage regulator has powered up SXOSCOFF a A le command strobe Power Down PD N Chip Reset pin or register Crystal oscillator disabled register
42. 0 kHz RF Att 30 dB Ref Lvl VBW 100 kHz O dBm SWT 5 ms Unit dBm 10 i 20 30 1AVG 1SA 40 50 A 60 U i 70 80 90 100 Center 2 45 GHz 1 MHz Span 10 MHz Date 23 0CT 2003 21 34 19 Figure 32 Modulated spectrum plot ki TEXAS SWRS041B Page 56 of 89 INSTRUMENTS E oa Products from Texas Instruments CC2420 34 System Considerations and Guidelines SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters SRDs Short Range Devices for license free operation are allowed to operate in the 2 4 GHz band worldwide The most important regulations are ETSI EN 300 328 and EN 300 440 Europe FCC CFR 47 part 15 247 and 15 249 USA and ARIB STD T66 Japan 34 1 Frequency hopping and multi channel systems The 2 4 GHz band is shared by many systems both in industrial office and home environments CC2420 uses direct sequence spread spectrum DSSS as defined by 1 to spread the output power thereby making the communication link more robust even in a noisy environment With CC2420 it is also possible to combine both DSSS and FHSS frequency hopping spread spectrum in a proprietary non IEEE 802 15 4 system This is achieved by reprogramming the operating frequency see the Frequency and Channel Programming section on page 50 before enabling RX or TX A fre
43. 0 on MAC frames within the TXFIFO RXFIFO respectively SECCTRL1 SEC_TXL SEC_RXL sets the number of bytes between the length field and the first byte to be encrypted decrypted respectively This controls the number of plaintext bytes in the current frame For IEEE 802 154 MAC encryption only the MAC payload see Figure 17 on page 36 should be encrypted so SEC_TXL SEC_RXL is set to 3 0 to 20 depending on the address information in the current frame When encryption is initiated the plaintext in the TXFIFO is then encrypted as specified by 1 The encryption module will encrypt all the plaintext currently available and wait if not everything is pre buffered The encryption operation may also be started without any data in the TXFIFO at all and data will be encrypted as it is written to the TXFIFO When decryption is initiated with a SRXDEC command strobe the ciphertext Wi TEXAS INSTRUMENTS SWRS041B CC2420 of the RXFIFO is then decrypted as specified by 1 21 6 CBC MAC CBC MAC in line authentication is provided by CC2420 hardware SECCTRLO SEC_M sets the MIC length M encoded as M 2 2 When enabling CBC MAC in line TXFIFO authentication the generated MIC is written to the TXFIFO for transmission The frame length must include the MIC SECCTRL1 SEC_TXL SEC_RXL sets the number of bytes between the length field and the first byte to be authenti
44. 2 0402 L62 Not used 5 6 nH 5 Not used Monolithic multilayer 0402 22 nH 5 Not used 12 nH 5 Monolithic multilayer Monolithic multilayer 0402 0402 L81 1 8 nH 0 3nH 7 5 nH 5 Not used Monolithic multilayer 0402 Monolithic multilayer 0402 43 KQ 1 0402 43kQ 1 0402 43 kQ 1 0402 16 MHz crystal 16 pF load 16 MHz crystal 16 pF load 16 MHz crystal 16 pF load C1 Cu Ci ESR lt 60 Q C ESR lt 60 0 ESR lt 600 Table 2 Bill of materials for the application circuits ki TEXAS SWRS041B Page 23 of 89 INSTRUMENTS E oa Products from Texas Instruments 10 IEEE 802 15 4 Modulation Format This section is meant as an introduction to the 2 4 GHz direct sequence spread spectrum DSSS RF modulation format defined in IEEE 802 15 4 For a complete description please refer to 1 The modulation and spreading functions are illustrated at block level in Figure 6 1 Each byte is divided into two symbols 4 bits each The least significant symbol is transmitted first For multi byte fields the CC2420 least significant byte is transmitted first except for security related fields where the most significant byte it transmitted first Each symbol is mapped to one out of 16 pseudo random sequences 32 chips each The symbol to chip mapping is shown in Table 3 The chip sequence is then transmitted at 2 MChips s with the least significant chip Co transmitted first for each symbol Tran
45. 4 The CC2420 hardware implementation is shown in Figure 20 Please refer to 1 for further details In transmit mode the FCS is appended at the correct position defined by the length field The FCS is not written to the TXFIFO but stored in a separate 16 bit register In receive mode the FCS is verified by hardware The user is normally only interested in the correctness of the FCS not the FCS sequence itself The FCS sequence itself is therefore not written to the RXFIFO during receive Instead when MODEMCTRLO AUTOCRC is set the two FCS bytes are replaced by the RSSI value average correlation value used for LQI and CRC OK not OK This is illustrated in Figure 21 The first FCS byte is replaced by the 8 bit RSSI value This RSSI value is measured over the first 8 symbols following the SFD See the RSSI section on page 48 for details The 7 least significant bits in the last FCS byte are replaced by the average correlation value of the 8 first symbols of the received PHY header length field and PHY Service Data Unit PSDU This correlation value may be used as a basis for calculating the LQI See the Link Quality Indication section on page 49 for details The most significant bit in the last byte of each frame is set high if the CRC of the received frame is correct and low otherwise Data input Y LSB en
46. In line security operations 21 5 CTR mode encryption decryption 21 6 CBC MAC 21 7 CCM 21 8 Timing 22 Linear IF and AGC Settings 23 RSSI Energy Detection 24 Link Quality Indication 25 Clear Channel Assessment 26 Frequency and Channel Programming 27 VCO and PLL Self Calibration 27 1 VCO 27 2 PLL self calibration 28 Output Power Programming 29 Voltage Regulator 30 Battery Monitor 31 Crystal Oscillator 32 Input Output Matching 33 Transmitter Test Modes 33 1 Unmodulated carrier 33 2 Modulated spectrum 34 System Considerations and Guidelines 34 1 Frequency hopping and multi channel systems 34 2 Data burst transmissions 34 3 Crystal accuracy and drift 34 4 Communication robustness 34 5 Communication security 34 6 Low cost systems 34 7 Battery operated systems 34 8 BER PER measurements 35 PCB Layout Recommendations 36 Antenna Considerations 37 Configuration Registers 38 Test Output Signals 39 Package Description QLP 48 40 Recommended layout for package QLP 48 we Twas SWRS041B INSTRUMENTS Page 3 of 89 E econ Products from Texas Instruments 40 1 Package thermal properties CC2420 40 2 Soldering information 40 3 Plastic tube specification 40 4 Carrier tape and reel specification 41 Ordering Information 42 General Information
47. L control bits SECCTRLO kis TEXAS INSTRUMENTS As can be seen from Table 6 on page 31 KEYO is located from address 0x100 and KEY1 from address 0x130 A way of establishing the keys used for encryption and authentication must be decided for each particular application IEEE 802 15 4 does not define how this is done it is left to the higher layer of the protocol ZigBee uses an Elliptic Curve Cryptography ECC based approach to establish keys For PC based solutions more processor intensive solutions such as Diffie Hellman may be chosen Some applications may also use pre programmed keys e g for remote keyless entry where the key and lock are delivered in pairs A push button approach for loading keys may also be selected 21 2 Nonce counter The receive and transmit nonces used for encryption decryption are located in RAM from addresses 0x110 and 0x140 respectively They are both 16 bytes The nonce must be correctly initialized before receive or transmit CTR or CCM operations are started The format of the nonce is shown in Table 7 The block counter must be set to 1 for compliance with 1 The key sequence counter is controlled by a layer above the MAC layer The frame counter must be increased for each new frame by the MAC layer The source address is the 64 bit IEEE address 1 byte 8 bytes 4 bytes 1 byte 2 bytes Flags Source Frame Key Block Address Counte
48. LNA from PA in receive transmit mode TXRX_SWITCH Power analog Common supply connection for integrated RF front end Must be connected to RF_P and RF_N externally through a DC path N RF I O Negative RF input output signal to LNA from PA in receive transmit mode 1 8 V Power supply for receive and transmit mixers 1 8 V Power supply for transmit receive IF chain SWRS041B Page 15 of 89 kis TEXAS INSTRUMENTS E Pisa Products CC2420 from Texas Instruments e re DV DGN DG RES DG DSU q Oo N a un ry a Q Q O H Name Pin type Pin Description p lt q q23 NotComected D_ADC D_ADC D_GUARD ARD ETn B_PADS igital Digital output CCA Clear Channel Assessment digital mux output serial RF clock output in test mode Digital I O Active when data in FIFO Poe era RE datanpat ouputintest mode Digital input SPI Clock input up to 10 MHz Digital input SPI Slave Input Sampled on the positive edge of SCLK Digital output SPI Slave Output Updated on the negative edge of SCLK tristate Tristate when CSn high Digital output SFD Start of Frame Delimiter digital mux output DSUB_CORE Ground digital Substrate connection for digital modules D3 3 Power digital 3 3 V Power supply for digital I Os VDD_RAM Power digital 1 8 V Power supply for digital RAM Not Connected AVDD_XOSC16 Power analog 1 8 V crystal oscillator power supply XOSC16_02 Analog I O
49. L_LONG When 1 this control bit doubles the time allowed for VCO frequency measurements during VCO calibration 0 PLL Calibration time is 37 us 1 PLL Calibration time is 57 us 13 10 PEE CURRE The value of the reference current calibrated against during VCO calibration VCO_CURRENT_K nn 0 VCO current calibration constant Current B override value when FSTST2 VCO_CURRENT_OE 1 R W Controls the source of the VCO VC node in normal operation TOPTST VC_IN_TEST_EN 0 0 Loop filter closed loop PLL 1 VC DAC open loop PLL VC_DAC_VAL 2 0 VC DAC output value FSTST2 0x29 Frequency Synthesizer Test Register 2 VCO_CURCAL_SPEE VCO current calibration speed 0 Normal 1 Double speed 2 Half speed 3 Undefined VCO_CURF O 5 0 EMC VCO current override value current A current override value current A 5 0 VCO_CURE 32 The VCO current result holds the register content of the most recent calibration ki TEXAS SWRS041B Page 77 of 89 INSTRUMENTS E Pisa Products CC2420 from Texas Instruments FSTST3 0x2A Frequency Synthesizer Test Register 3 E eres E ee Disable charge pump during VCO calibration when set CHP_CURRE E R W Charge pump current override enable 0 Charge pump current set by calibration 1 Charge pump current set by START_CHP_CURRENT IA Forces the CHP to output up current when set AAA A Forces t
50. MO 220 ki TEXAS SWRS041B Page 83 of 89 INSTRUMENTS E Pisco Products from Texas Instruments CC2420 40 Recommended layout for package QLP 48 4 69mm a 4mm T 0 54mm LLL 5 4mm A 4 28mm i Note The figure is an illustration only and not to scale There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package See also the CC2420 EM reference design 40 1 Package thermal properties Thermal resistance Air velocity m s Rth j a K W 25 6 40 2 Soldering information Recommended soldering profile is according to IPC JEDEC J STD 020C ki TEXAS SWRS041B INSTRUMENTS Page 84 of 89 E Pisco Products CC2420 from Texas Instruments 40 3 Plastic tube specification QLP 7x7mm antistatic tube Tube Specification Package Tube Width Tube Height Tube Length Units per Tube QLP 48 8 5 0 2 mm 2 2 0 2 0 1 mm 315 1 25 mm 43 40 4 Carrier tape and reel specification Carrier tape and reel is in accordance with ElA Specification 481 Tape and Reel Specification Package Tape Width Component Hole Reel Units per Reel Pitch Pitch Diameter QLP 48 16 mm 12 mm 4 mm 13 inch 4000 41 Ordering Information Chipcon Part TI Part Number Description Minimum Order Number Quantity MOQ CC2420 RTB1 CC2420RTC Single chip RF Transceiver
51. O but a RF transmission will not be started Ciphertext may be read back using RAM read operations e Issue a STXON or STXONCCA command strobe In line security will be performed within the TXFIFO and a RF transmission of the ciphertext is started When enabled RX in line security is started as follows e Issue a SRXDEC command strobe The first frame in the RXFIFO is then decrypted authenticated as set by the current security mode Page 46 of 89 E a Products from Texas Instruments RX in line security operations are always performed on the first frame currently inside the RXFIFO even if parts of this have already been read out over the SPI interface This allows the receiver to first read the source address out to decide which key to use before doing authentication of the complete frame In CTR or CCM mode it is of course important that bytes to be decrypted are not read out before the security operation is started When the SRXDEC command strobe is issued the FIFO and FIFOP pins will go inactive This is to indicate to the microcontroller that no further data may be read out before the next byte to be read has undergone the requested security operation The frame in the RXFIFO may be received over RF or it may be written into the RXFIFO over the SPI interface for debugging or higher layer security operations 21 5 CTR mode decryption encryption CTR mode encryption decryption is performed by CC242
52. RF signal is amplified by the low noise amplifier LNA and down converted in quadrature I and Q to the intermediate frequency IF At IF 2 MHz the complex Q signal is filtered and amplified and then digitized by the ADCs Automatic gain control final channel filtering de spreading symbol correlation and byte synchronisation are performed digitally When the SFD pin goes active this indicates that a start of frame delimiter has been detected CC2420 buffers the received data in a 128 byte receive FIFO The user may read the FIFO through an SPI interface CRC is verified in hardware RSSI and correlation values are appended to the frame CCA is available on a pin in receive mode Serial unbuffered data The CC2420 transmitter is based on direct up conversion The data is buffered in a 128 byte transmit FIFO separate from the receive FIFO The preamble and start of frame delimiter are generated by hardware Each symbol 4 bits is spread using the IEEE 802 15 4 spreading sequence to 32 chips and output to the digital to analog converters DACs An analog low pass filter passes the signal to the quadrature I and Q upconversion mixers The RF signal is amplified in the power amplifier PA and fed to the antenna The internal T R switch circuitry makes the antenna interface and matching easy The RF connection is differential A balun may be used for single ended antennas The biasing of the PA and LNA is done by co
53. S Send acknowledge frame with pending field set 0x0C SRXDEC S Start RXFIFO in line decryption authentication as set by SPI_SEC_MODE Ox0D STXENC S Start TXFIFO in line encryption authentication as set by SPI_SEC_MODE without starting TX i ki TEXAS SWRS041B Page 61 of 89 INSTRUMENTS E Passar Products CC2420 from Texas Instruments Address Register Register type Description Ox0E SAES S AES Stand alone encryption strobe SPI_SEC_MODE is not required to be 0 but the encryption module must be idle If not the strobe is ignored 0x0F Not used 0x10 MAIN R W Main Control Register 0x11 MDMCTRLO R W Modem Control Register 0 0x12 MDMCTRL1 R W Modem Control Register 1 0x13 RSSI R W RSSI and CCA Status and Control register 0x14 SYNCWORD R W Synchronisation word control register 0x15 TXCTRL R W Transmit Control Register 0x16 RXCTRLO R W Receive Control Register 0 0x17 RXCTRL1 R W Receive Control Register 1 0x18 FSCTRL R W Frequency Synthesizer Control and Status Register 0x19 SECCTRLO R W Security Control Register 0 Ox1A SECCTRL1 R W Security Control Register 1 0x1B BATTMON R W Battery Monitor Control and Status Register 0x1C IOCFGO R W Input Output Control Register 0 0x1D IOCFG1 R W Input Output Control Register 1 Ox1E MANFIDL R W Manufacturer ID Low 16 bits Ox1F MANFIDH R W Manufacturer ID High 16 bits
54. SSI Carrier Sense Carrier sense level 77 Programmable in RSSI CCA_THR RSSI dynamic range The range is approximately from 100 dBm to 0 dBm RSSI accuracy See page 48 for details RSSI linearity RSSI average time 8 symbol periods as specified by 1 6 5 IF Section Intermediate frequency IF 6 6 Frequency Synthesizer Section Crystal oscillator frequency See page 53 for details Crystal frequency accuracy 40 40 ppm Including aging and temperature requirement dependency as specified by 1 Crystal operation Parallel C381 and C391 are loading capacitors see page 53 ki TEXAS SWRS041B Page 11 of 89 INSTRUMENTS El Chipcon Products from Texas Instruments CC2420 Parameter Min Typ Max Unit Condition Note Crystal load capacitance 12 16 20 pF 16 pF recommended Crystal ESR 60 Q Crystal oscillator start up time 1 0 ms 16 pF load Phase noise Unmodulated carrier 109 dBc Hz At 1 MHz offset from carrier 117 dBc Hz At 2 MHz offset from carrier 117 dBc Hz At 3 MHz offset from carrier 117 dBc Hz At 5 MHz offset from carrier PLL loop bandwidth 100 kHz PLL lock time 192 us The startup time from the crystal oscillator is running and RX TX turnaround time 6 7 Digital Inputs Outputs General Logic 0 input voltage Logic 1 input voltage Logic 0 output voltage Logic 1 output voltage Logic 0 input current Logi
55. See the Radio control state machine section on page 43 for details ki TEXAS SWRS041B Page 78 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments ADCTST 0x2D ADC Test Register ADC_CLOCK_DISABLE ADC Clock Disable 0 Clock enabled when ADC enabled 1 Clock disabled even if ADC is enabled ADC_I 6 0 po fR Read the current ADC l branch value 6 0 ADC_0 6 0 fo fR Read the current ADC Q branch value DACTST 0x2E DAC Test Register Ta 12 DAC_SRC 2 0 The TX DACs data source is selected by DAC_SRC according to Normal operation from modulator The DAC_I_O and DAC_Q_O override values below From ADC most significant bits 1 Q after digital down mixing and channel filtering Full spectrum White Noise from CRC From ADC least significant bits RSSI Cordic Magnitude Output HSSD module This feature will often require the DACs to be manually turned on in MANOR and TOPTST ATESTMOD_MODE 4 DAC_I_O 5 0 o R l branch DAC override value DAC_Q_0 5 0 o R Q branch DAC override value ki TEXAS SWRS041B Page 79 of 89 INSTRUMENTS E epenn Products CC2420 from Texas Instruments TOPTST 0x2F Top Level Test Register RAM_BIST_RUN Enable BIST of the RAM 0 RAM BIST disabled normal operation 1 RAM BIST Enabled Result output to pin as set in IOCFG1 TEST PATMN EN BATTMON I ESO CA E Enable test output of the battery monitor When ATESTMOD_MODE 7 this cont
56. TC 0x20 Finite state machine time constants TC_RXCHAIN2RX 2 0 3 R W The time in 5 us steps between the time the RX chain is enabled and the demodulator and AGC is enabled The RX chain is started when the bandpass filter has been calibrated after 6 5 symbol periods 121 0 TC_SWITCH2TX 2 0 R W The time in advance the RXTX switch is set high before enabling TX In us TC_PAON2T 10 R W The time in advance the PA is powered up before enabling TX In ps R W The time after the last chip in the packet is sent and the TXRX switch is disabled In us set in power down Also the time at which the modulator is disabled In us C_TXEND2PAOFF 2 0 The time after the last chip in the packet is sent and the PA is ki TEXAS SWRS041B Page 73 of 89 INSTRUMENTS E Pisa Products from Texas Instruments CC2420 MANAND 0x21 Manual signal AND override register e o pee EN pan E CN ES ope ES EXI pee EN e RXBPE_ZPD O F_PD PRXBPF_PD f SAA The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain Global bias powerdown 1 bias Global bias powerdown 1 down The BALUN_CTRL signal controls whether the PA should receive its required external biasing 1 or not 0 by controlling the RX TX output switch R W RXTX signal controls whether the LO buffers 0 or PA buffers 1 should be used Rm Power
57. UNDERFLOW in state diagram Disclaimer updated to include Z stack information Product status changed to Full Production SWRS041B Page 86 of 89 E Spean Products CC2420 from Texas Instruments 1 2 2004 06 09 Output power range 24 dB was 40 dB Deleted option for single ended external PA Adjacent channel rejection corrected to 46 dB for 5MHz was 39 dB 39 dB for 5 MHz was 46 dB 58 dB for 10 MHz was 53 dB and 55 dB for 10 MHz was 57 dB image channel deleted in text for In band spurious reception Revision for reference 1 updated CSMA CA added to abbreviations Schematic view of the IEEE 802 15 4 Frame Format corrected address field 0 to 20 bits Changed blocking specifications to relate to EN 300 440 class 2 Updated addresses for Chipcon offices Added section Operating Conditions Section RAM access A6 0 LSB IOCFGO BCN_ACCEPT bit added and described in section Address recognition and the IOCFGO register The previous IDLE mode has been renamed to power down to be consistent with other Chipcon data sheets Three power modes defined Voltage regulator off OFF Power down PD Voltage regulator enabled IDLE XOSC running and used throughout the document Default TXMIXBUF_CUR 1 0 in table for TXCTRL set to 2 Added information compliance with EN 300 328 og EN 300 440 Class 2 Added more information about FIFOP in section Receive mode Removed text about SO programmable pull up from en
58. XAS SWRS041B INSTRUMENTS Current drawn from VREG_IN through voltage regulator Voltage regulator off Voltage regulator on Including crystal oscillator and voltage regulator Page 13 of 89 E Passar Products CC2420 from Texas Instruments Parameter Min Typ Max Unit Condition Note Current Consumption transmit mode P 25 dBm 8 5 mA The output power is delivered P 15 dBm 9 9 mA differentially to a 50 Q singled 10 dBm 11 mA ended load through a balun see P 5 dBm 14 mA also page 54 P 0 dBm 17 4 mA ki TEXAS SWRS041B Page 14 of 89 INSTRUMENTS E peon Products CC2420 from Texas Instruments 7 Pin Assignment AVDD_XOSC16 ATEST2 R_BIAS AVDD_IF1 VREG_IN VREG_OUT VREG_EN XOSC16_Q1 XOSC16_Q2 NC ti it ist sti it Ise lap VCO_GUARD NC AVDD_VCO DVDD_RAM AVDD_PRE so AVDD_RF1 SI GND SCLK RF_P CSn TXRX_SWITCH FIFO RF_N FIFOP GND CCA AVDD_SW SFD NC DVDD1 8 NC DVDD3 3 z gt uy g D oO p 62222 26 8 amp 6 amp g g s g Z Cc nan Z C C AGND 0 iw iw iw iw gt m iw ive w E gt a ly lo Exposed die a 3 6 5 2 0 gt 0 attach pad N O e gt DO D D o m Figure 1 CC2420 Pinout Top View Ground analog Exposed die attach pad Must be connected to solid ground plane 1 8 V Power supply for VCO 1 8 V Power supply for Prescaler 1 8 V Power supply for RF front end Grounded pin for RF shielding RF I O Positive RF input output signal to
59. a built in test pattern generator that can generate pseudo random sequence using the CRC generator This is enabled by setting MDMCTRL1 TX_MODE to 3 and issues an STXON command strobe The modulated spectrum is then available on the RF pins The low byte of the CRC word is transmitted and the CRC is updated with OxFF for each new byte The length of the transmitted data sequence is 65535 bits The transmitted data sequence is then Synchronisation header 0x00 0x78 Oxb8 0x4b 0x99 Oxc3 Oxe9 Since a synchronisation header preamble and SFD is transmitted in all TX modes this test mode may also be used to transmit a known pseudorandom bit xi TEXAS INSTRUMENTS SWRS041B sequence for bit error testing Please note that CC2420 requires symbol synchronisation not only bit synchronisation for correct reception Packet error rate is therefore a better measurement for the true RF performance Another option to generate a modulated spectrum is to fill the TXFIFO with pseudo random data and set MDMCTRL1 TX_MODE to 2 CC2420 will then transmit data from the FIFO disregarding a TXFIFO underflow The length of the transmitted data sequence is then 1024 bits 128 bytes A plot of the modulated spectrum from CC2420 is shown in Figure 32 Note that to find the output power from the modulated spectrum the RBW must be set to 3 MHz or higher Page 55 of 89 E a Products CC2420 from Texas Instruments RBW 10
60. access enabled FIFO RAM access disabled SXOSCON Y Wait for the specified crystal oscillator start up time or poll the XOSC16M_STABLE status bit Vv a SRFOFF ee All States AF IDLE except Power Down PD a 1 G RX_CALIBRATE 2 and 40 E 12 symbol periods later ees AA SELUSBR RX_SFD_SEARCH B 4 5 and 6 SFD Frame received or found o failed address as AA recognition RX_FRAME 16 and 40 Automatic or manual acknowledge request _ Y TX_ACK_CALIBRATE N 48 MAS 12 sba periods later y PS Coa PAE TX_ACK_PREAMBLE 49 50 and 51 Acknowledge te Ve completed TX_ACK C 52 53 and 54 Figure 25 Radio control states kis TEXAS INSTRUMENTS SWRS041B TX_CALIBRATE 32 8 or 12 symbol periods later TX PREAMBLE Preamble and SFD 34 35 and 36 _ _ is transmitted TX_FRAME N TXFIFO Data _ 87 38 and 39 _ is transmitted K nderflow TX_UNDERFLOW 56 The transition from TX_UNDERFLOW to RX_CALIBRATE is automatic but SFLUSHTX must be used to reset underflow indication Page 44 of 89 E Pisco Products from Texas Instruments CC2420 21 MAC Security Operations Encryption and Authentication CC2420 features hardware IEEE 802 15 4 MAC security operations This includes counter mode CTR encryption decryption CBC MAC authentication and CCM encryption authentication All securit
61. age 1 Power supply gt Toggle Voltage BATTMON_EN Battery monitor enable 0 Battery monitor is disabled 1 Battery monitor is enabled BATTMON_VOLTAGE Battery monitor toggle voltage The toggle voltage is given by 4 0 72 BATTMON_VOLTAGE Wero 1 25V a7 ki TEXAS SWRS041B Page 71 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments IOCFGO 0x1C I O Configuration Register 0 BCN_ACCEPT Accept all beacon frames when address recognition is enabled This bit should be set when the PAN identifier programmed into CC2420 RAM is equal to OxFFFF and cleared otherwise This bit is don t care when MDMCTRLO ADR_DECODE 0 0 Only accept beacons with a source PAN identifier which matches the PAN identifier programmed into CC2420 RAM 1 Accept all beacons regardless of the source PAN identifier 10 FIFO_POLARITY Polarity of the output signal FIFO 0 Polarity is active high 1 Polarity is active low FIFOP_POLARITY Polarity of the output signal FIFOP O Polarity is active high 1 Polarity is active low SFD_POLARITY Polarity of the SFD pin 0 Polarity is active high 1 Polarity is active low CCA_POLARITY Polarity of the CCA pin Polarity is active high Polarity is active low FIFOP_THR 6 0 FIFOP_THR sets the threshold in number of bytes in the RXFIFO for FIFOP to go active IOCFG1 0x1D I O Configuration Register 1 12210 HSSD_SRC The HSSD module is used as foll
62. and dump function in the AGC 0 8 samples 1 16 samples 2 32 samples 3 64 samples o Target value for the AGC control loop given in 2 dB steps Reset value corresponds to approximately 25 of the ADC dynamic range in reception AGCTST2 0x26 AGC Test Register 2 MED2HIGHGAIN MED2HIGHGAIN sets the difference in the receiver LNA MIXER gain from medium gain mode to high gain mode used by the AGC for setting the correct front end gain mode LOW2MEDGAIN 4 0 LOW2MEDGAIN sets the difference in the receiver LNA MIXER gain from low gain mode to medium gain mode used by the AGC for setting the correct front end gain mode ki TEXAS SWRS041B Page 76 of 89 INSTRUMENTS E Pisa Products CC2420 from Texas Instruments FSTSTO 0x27 Frequency Synthesizer Test Register 0 VCO_ARRAY_SE LONG When 1 this control bit doubles the time allowed for VCO settling during VCO calibration VCO_ARRAY_OE VCO array manual override enable VCO_ARRAY_O 4 0 Seem omora e VCO array override value array override value VCO_ARRAY_RES 4 0 16 The VCO array result holds the register content of the most recent calibration FSTST1 0x28 Frequency Synthesizer Test Register 1 15 VCO_TX_NOCAL R W 0 VCO calibration is always performed when going to RX or when going to TX 1 VCO calibration is only performed when going to RX or when using the STXCAL command strobe VCO_ARRAY_CA
63. ants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanie
64. c 1 input current FIFO setup time FIFO hold time Serial interface pins SCLK SI SO and CSn timing specification kis TEXAS INSTRUMENTS SWRS041B Signal levels are referred to the voltage level at pin DVDD3 3 Output current 8 mA 3 3 V supply voltage Output current 8 mA 3 3 V supply voltage Input signal equals GND Input signal equals VDD TX unbuffered mode minimum time FIFO must be ready before the positive edge of FIFOP TX unbuffered mode minimum time FIFO must be held after the positive edge of FIFOP See Table 4 on page 28 Page 12 of 89 E Pisco Products from Texas Instruments 6 8 Voltage Regulator CC2420 H AA 2 1 3 0 3 6 V Input Voltage Output Voltage Quiescent current Start up time 6 9 Battery Monitor Note that the internal voltage regulator can only supply CC2420 and no external circuitry On the VREG_IN pin On the VREG_OUT pin No current drawn from the VREG_OUT pin Min and max numbers include 2 1 through 3 6 V input voltage Current consumption TEA When enabled a a cia A E a Besar eee Absolute accuracy Relative accuracy 50 50 mV Voltage regulator already enabled New toggle voltage programmed May be software calibrated for known reference voltage Current consumption in different modes see Figure 25 page 44 Voltage regulator off OFF Power Down mode PD Idle mode IDLE Current Consumption receive mode ki TE
65. cated normally set to O for MAC authentication SECCTRLO SEC_CBC_HEAD defines if the authentication length is used as the first byte of data to be authenticated or not This bit should be set for compliance with 1 When enabling CBC MAC in line RXFIFO authentication the generated MIC is compared to the MIC in the RXFIFO The last byte of the MIC is replaced in the RXFIFO with e 0x00 if the MIC is correct e OxFF if the MIC is incorrect The other bytes in the MIC are left unchanged in the RXFIFO 21 7 CCM CCM combines CTR mode encryption and CBC MAC authentication in one operation CCM is described in 3 SECCTRL1 SEC_TXL SEC_RXL sets the number of bytes after the length field to be authenticated but not encrypted The MIC is generated and verified very much like with CBC MAC described above The only differences are from the requirements in 1 for CCM Page 47 of 89 E Pisco Products from Texas Instruments 21 8 Timing CC2420 Table 8 shows some examples of the time used by the security module for different operations Mode I a I m I MIC Time us CCM 50 69 8 222 CTR 15 99 CBC 17 98 12 99 Stand 16 14 alone Table 8 Security timing examples 22 Linear IF and AGC Settings CC2420 is based on a linear IF chain where the signal amplification is done in an analog VGA variable gain amplifier The gain of the VGA is dig
66. ccepted The command strobe register is accessed in the same way as for a register write operation but no data is transferred That is only the RAM Register bit set to 0 R W bit set to 0 and the 6 address bits in the range 0x00 through 0Ox0E are xi TEXAS INSTRUMENTS SWRS041B written A command strobe may be followed by any other SPI access without pulling CSn high and is executed on the last falling edge on SCLK 13 5 RAM access The internal 368 byte RAM may be accessed through the SPI interface Single or multiple bytes may be read or written sending the address part 2 bytes only once The address is then automatically incremented by the CC2420 hardware for each new byte Data is read and written one byte at a time unlike register access where 2 bytes are always required after each address byte The crystal oscillator must be running when accessing the RAM The RAM Register bit must be set high to enable RAM access The 9 bit RAM address consists of two parts B1 0 MSB selecting one of the three memory banks and A6 0 LSB selecting the address within the selected bank The RAM is Page 29 of 89 E Pisa Products from Texas Instruments divided into three memory banks TXFIFO bank 0 RXFIFO bank 1 and security bank 2 The FIFO banks are 128 bytes each while the security bank is 112 bytes A6 0 is transmitted directly after the RAM Register bit as shown in Figure 9 For RAM access a se
67. cond byte is also required before the data transfer This byte contains B1 0 in bits 7 and 6 followed by the R W bit 0 for read write 1 for read Bits 4 through O are don t care as shown in Figure 9 For RAM write data to be written must be input on the st pin directly after the second address byte RAM data read is output on the so pin simultaneously but may be ignored by the user if only writing is of interest CC2420 For RAM read the selected byte s are output on the so pin directly after the second address byte See Figure 10 for an illustration on how multiple RAM bytes may be read or written in one operation The RAM memory space is shown in Table 6 The lower 256 bytes are used to store FIFO data Note that RAM access should never be used for FIFO write operations because the FIFO counter will not be updated Use RXFIFO and TXFIFO access instead as described in section FIFO access As with register data data stored in RAM will be retained during power down mode but not when the power supply is turned off e g by disabling the voltage regulator using the VREG_EN pin ADDR X ADDR X ADDR DATA DATA 8LSB ass MA ADDR YX DATA smog ADDR YX DATAgyss X DATA cg CSn 1 Command strobe Multiple command strobes Read or write a whole register 16 bit ADDR DATA suse Read 8 MSB of a register Multiple register read or write ADDR DATA use Read or write n bytes f
68. ctive during transmission of a data frame as shown in Figure 15 The SFD pin goes active when the SFD field has been completely transmitted It goes inactive again when the complete MPDU as defined by the length field has been transmitted or if an underflow is kis TEXAS INSTRUMENTS SWRS041B detected See the RF Data Buffering section on page 39 for more information on TXFIFO underflow As can be seen from comparing Figure 13 and Figure 15 the SFD pin behaves very similarly during reception and transmission of a data frame If the SFD pins of the transmitter and the receiver are compared during the transmission of a data frame a small delay of approximately 2 us can be seen because of bandwidth limitations in both the transmitter and the receiver Page 34 of 89 E Pisa Products from Texas Instruments Y K g o e Ko O Gp CC2420 Data transmitted over RF Preamble Length MAC Protocol Data Unit MPDU SFD Pin lt gt gt lt 12 symbol periods Automatically generated preamble and SFD gt gt CRC generated Data fetched by CC2420 from TXFIFO Figure 15 Pin activity example during transmit 14 5 General control and status pins In receive mode the FIFOP pin can be used to interrupt the microcontroller when a threshold has been exceeded or a complete frame has been received This pin should then be connected to a microcontroller interrupt pi
69. d 0x120 LSB ciphertext output 0x11F MSB Flags RXNONCE RXCTR Receiver nonce for in line authentication or 0x110 LSB receiver counter for in line decryption 0x10F MSB KEYO Encryption key O 0x100 LSB OxOFF MSB RXFIFO 128 bytes receive FIFO 0x080 LSB Ox07F MSB TXFIFO 128 bytes transmit FIFO 0x000 LSB Table 6 CC2420 RAM Memory Space 13 6 FIFO access The TXFIFO and RXFIFO may be accessed through the TXFIFO 0x3E and RXFIFO 0x3F registers The TXFIFO is write only but may be read back using RAM access as described in the previous section Data is read and written one byte at a time as with RAM access The RXFIFO is both writeable and readable Writing to the RXFIFO should however only be done for debugging or for using the RXFIFO for security operations decryption authentication The crystal oscillator must be running when accessing the FIFOs When writing to the TXFIFO the status byte see Table 5 is output for each new data byte on so as shown in Figure 9 This could be used to detect TXFIFO underflow see section RF Data Buffering section on page 39 while writing data to the TXFIFO Multiple FIFO bytes may be accessed in one operation as with the RAM access FIFO access can only be terminated by kis TEXAS INSTRUMENTS SWRS041B setting the CSn pin high once it has been started The FIFO and FIFOP pins also provide additional information on the data in the receive
70. d by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of Tl products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated Tl product or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in
71. down of prescaler Rm Powerdown of PA negative path W R W Powerdown of PA positive path When PA_N_PD 1 and PA_P_PD 1 the up conversion mixers are in powerdown Powerdown of TX DACs R CN oS R W Powerdown control of complex bandpass receive filter calibration oscillator Rm Powerdown control of charge pump R Powerdown control of VCO I Q generator LO buffers pa Powerdown control of the ADCs Powerdown control of the VGA ECM Powerdown control of complex bandpass receive filter UN Powerdown control of LNA down conversion mixers and front end bias 1 For some important signals the value used by analog and digital modules can be overridden manually This is done as follows for the hypothetical important signal S IS_USED IS IS_AND_MASK IS_OR_MASK using boolean notation The AND mask and OR mask for the important signals listed resides in the MANAND and MANOR registers respectively Examples Writing OXFFFE to MANAND and 0x0000 to MANOR will force LNAMIX_PD 0 whereas all other signals will be unaffected Writing OXFFFF to MANAND and 0x0001 to MANOR will force LNAMIX_PD 1 whereas all other signals will be unaffected kis TEXAS INSTRUMENTS SWRS041B Page 74 of 89 E Pisco Products CC2420 from Texas Instruments MANOR 0x22 Manual signal OR override register AA A AA VGA_RE The VGA_RESET_N signal is used to reset the peak detectors in e E VGA in the RX chain
72. e kis TEXAS INSTRUMENTS SWRS041B RAM Register bit set to O for register access followed by the R W bit 0 for write 1 for read The following 6 bits are the address bits A5 0 A5 is the most significant bit of the address and is sent first The 16 data bits are then transferred D15 0 also MSB first See Figure 9 for an illustration The configuration registers can also be read by the microcontroller via the same configuration interface The R W bit must be set high to initiate the data read back CC2420 then returns the data from the addressed register on the 16 clock cycles following the register address The so pin is used as the data output and must be configured as an input by the microcontroller The timing for the programming is also shown in Figure 9 with reference to Table 4 The clocking of the data on SI into the CC2420 is done on the positive edge of SCLK When the last bit DO of the 16 data bits has been written the data word is loaded in the internal configuration register Multiple registers may be written without releasing CSn as described in the Multiple SPI access section on page 31 The register data will be retained during power down mode but not when the power supply is turned off e g by disabling the voltage regulator using the VREG_EN pin The registers can be programmed in any order Page 27 of 89 E oa Products CC2420 from Texas Instruments 7 sp ch t tg
73. e on chip battery monitor enables monitoring the unregulated voltage on the VREG_IN pin It gives status information on the voltage being above or below a BATTMON BATTMON_EN Internal bandgap 1 25V voltage reference programmable threshold A simplified schematic of the battery monitor is shown in Figure 29 VREG_IN Xx BATTMON BATTMON_OK Baron BATTMON_VOLTAGE 4 0 Figure 29 Battery monitor simplified schematic kis TEXAS INSTRUMENTS SWRS041B Page 52 of 89 E Pisco Products from Texas Instruments The battery monitor is controlled through the BATTMON control register The battery monitor is enabled and disabled using the BATTMON BATTMON_EN control bit The voltage regulator must also be enabled when using the battery monitor The battery monitor status bit is available in the BATTMON BATTMON_OK status bit This bit is high when the VREG_IN input voltage is higher than the toggle voltage Vioggle The battery monitor toggle voltage is set in the 5 bit BATTMON BATTMON_VOLTAGE control bits BATTMON_VOLTAGE is an unsigned positive number from 0 to 31 The toggle voltage is given by 72 BATTMON_VOLTAGE V ewe 1 25V 27 31 Crystal Oscillator An external clock signal or the internal crystal oscillator can be used as main frequency reference The reference frequency must be 16 MHz Because the crystal frequency
74. eceiver LNA Mixer power down active high 11 FFCTRL_PA_P_PD Power amplifier power down active high 12 VGA_PEAK_DET 0 VGA Peak detector gain stage 0 13 VGA_PEAK_DET 2 VGA Peak detector gain stage 2 14 VGA_PEAK_DET 4 VGA Peak detector gain stage 4 15 AGC_LNAMIX_GAINMODE 0 RF receiver front end gain mode bit 0 16 AGC_VGA_GAIN 0 VGA gain setting bit 0 17 RXBPF_CAL_CLK Receiver bandpass filter calibration clock 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 PD_F_COMP Frequency synthesizer frequency comparator value 25 FSDIG_FREF Frequency synthesizer 4 MHz reference signal 26 FSDIG_FPLL Frequency synthesizer 4 MHz divided signal 27 FSDIG_LOCK_WINDOW Frequency synthesizer lock window 28 WINDOW_SYNC Frequency synthesizer synchronized lock window 29 CLK_ADC_DIG ADC clock signal 2 30 ZERO Low 31 ONE High Table 13 SFD test signal select table ki TEXAS SWRS041B Page 82 of 89 INSTRUMENTS E Chipcon Products CC2420 from Texas Instruments 39 Package Description QLP 48 Note The figure is an illustration only and not to scale Quad Leadless Package QLP D D1 E El e b L D2 E2 QLP 48 Min 6 9 6 65 6 9 6 65 0 18 0 3 5 05 5 05 7 0 6 75 7 0 6 75 0 5 0 4 5 10 5 10 Max 7 1 6 85 7 1 6 85 0 30 0 5 5 15 5 15 The overall packet height is 0 85 0 05 All dimensions in mm The package is compliant to JEDEC standard
75. edge of SCLK Es minimum time Csn must be held low after the last negative edge of SCLK CSn setup time CSn hold time sI setup time E minimum time data on SI must be ready before the positive edge of SCLK SI hold time The minimum time data must be held at sI after the positive edge of SCLK Rise time time tise A EE ns The maximum rise time for scuk andcsn maximum rise time for The maximum rise time for scuk and csn and CSn EEN time EE The maximum fall time for SCLK and CSn Note The set up and hold times refer to 50 of VDD Table 4 SPI timing specification Issuing a SNOP no operation command 13 3 Status byte strobe may be used to read the status During transfer of the register access byte byte It may also be read during access to command strobes the first RAM address chip functions such as register or FIFO byte and data transfer to the TXFIFO the access CC2420 status byte is returned on the so pin The status byte contains 6 status bits which are described in Table 5 kis TEXAS SWRS041B Page 28 of 89 INSTRUMENTS E Pisa Products from Texas Instruments CC2420 Bit Name Description 7 Reserved ignore value 6 XOSC16M_STABLE Indicates whether the 16 MHz oscillator is running or not 0 The 16 MHz crystal oscillator is not running 1 The 16 MHz crystal oscillator is running 5 TX_UNDERF LOW Indicates whether an FIFO underflow has occ
76. en by L 14250 f kis TEXAS INSTRUMENTS SWRS041B CC2420 signal has the same phase shifts as the O QPSK sequence previously defined For a desired symbol sequence So S4 Sn 1 Of length n symbols the desired chip sequence Co Cy C2 C32n 1 Of length 32n is found using table lookup from Table 3 on page 24 lt can be seen from comparing the phase shifts of the O QPSK signal with the frequency of a MSK signal that the MSK chip sequence is generated as Co xnor c1 C4 xor Co C2 XNor C3 C32n 4 XOF C32 Where C3 may be arbitrarily selected separate vias Supply power filtering is very important The external components should be as small as possible 0402 is recommended and surface mount devices must be used Caution should be used when placing the microcontroller in order to avoid interference with the RF circuitry A Development Kit with a fully assembled Evaluation Module is available It is strongly advised that this reference layout is followed very closely in order to get the best performance The schematic BOM and layout Gerber files for the reference designs are all available from the Texas Instruments website where f is in MHz giving the length in cm An antenna for 2450 MHz should be 5 8 cm Each arm is therefore 2 9 cm Other commonly used antennas for short range communication are monopole helical and loop antennas The single ended monopole and helical would r
77. equire a balun network between the differential output and the antenna Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength Page 59 of 89 E a Products from Texas Instruments A 4 They are very easy to design and can be implemented simply as a piece of wire or even integrated into the PCB The length of the 4 4 monopole antenna is given by L 7125 f where f is in MHz giving the length in cm An antenna for 2450 MHz should be 2 9 cm Non resonant monopole antennas shorter than 1 4 can also be used but at the expense of range In size and cost critical applications such an antenna may very well be integrated into the PCB Enclosing the antenna in high dielectric constant material reduces the overall size vy TEXAS INSTRUMENTS SWRS041B CC2420 of the antenna Many vendors offer such antennas intended for PCB mounting Helical antennas can be thought of as a combination of a monopole and a loop antenna They are a good compromise in size critical applications Helical antennas tend to be more difficult to optimize than the simple monopole Loop antennas are easy to integrate into the PCB but are less effective due to difficult impedance matching because of their very low radiation resistance For low power applications the differential antenna is recommended giving the best range and because of its simplicity The antenna should be con
78. equires max 35 Q Optimum load impedance 95 Differential impedance as seen j187 from the RF port RF_P and RF_N towards the antenna For matching details see the Input Output Matching section on page 54 30 1000 MHz 1 12 75 GHz 1 8 1 9 GHz 5 15 5 3 GHz Error Vector Magnitude EVM ki TEXAS SWRS041B Page 9 of 89 INSTRUMENTS E Chipcon Products from Texas Instruments 6 3 Receive Section CC2420 Receiver Sensitivity Saturation maximum input level Adjacent channel rejection 5 MHz channel spacing Adjacent channel rejection 5 MHz channel spacing Alternate channel rejection 10 MHz channel spacing Alternate channel rejection 10 MHz channel spacing Channel rejection 2 15 MHz lt 15 MHz Co channel rejection Blocking Desensitisation 5 MHz from band edge 20 MHz from band edge 30 MHz from band edge 50 MHz from band edge Spurious emission 30 1000 MHz 1 12 75 GHz kis TEXAS INSTRUMENTS SWRS041B PER 1 as specified by 1 Measured in a 500 single ended load through a balun 1 requires 85 dBm PER 1 as specified by 1 Measured in a 50Q single ended load through a balun 1 requires 20 dBm Wanted signal 82 dBm adjacent modulated channel at 5 MHz PER 1 as specified by 1 1 requires 0 dB Wanted signal 82 dBm adjacent modulated channel at 5 MHz PER 1 as specified by 1
79. er If the SECCTRLO RXFIFO_PROTECTION control bit is set CC2420 also protects the frame header of security enabled frames until decryption has been performed If no MAC security is used or if it is implemented outside the CC2420 this bit may be cleared to achieve optimal use of the RXFIFO Page 33 of 89 E Pisco Products from Texas Instruments CC2420 S gt se e DI Se ES xe Q Ok ws aS Data received over RF Preamble SFD Length MAC Protocol Data Unit MPDU with correct address Address N recognition OK SFD Pin FIFO Pin FIFOP Pin if threshold _ __ higher than frame length FIFOP Pin if threshold lower than frame length Data received over RF Preamble SFD Length MAC Protocol Data Unit MPDU with wrong address Address o recognition fails SFD Pin FIFO Pin FIFOP Pin Figure 13 Pin activity examples during receive XO o lt O RS g RR ES RY BY Ni ss of S BS e CEN oO s S sX SO o A OS Re A MS ES 3 NES SCLK E E 7 x 2 _ of a a E _ 2 a T _ SFD CSn S DDR rie ii 7 so Status X Length X PSDUO X PSDU1 X_PSDU2 X PSDUS X PSDU4 X PSDU5 X RSSI FOSCO FIFOP FIFO Figure 14 Example of pin activity when reading RXFIFO 14 4 Transmit mode During transmit the FIFO and FIFOP pins are still only related to the RXFIFO The SFD pin is however a
80. er read write Note that the crystal oscillator must be running for accessing the RXFIFO ki TEXAS SWRS041B Page 80 of 89 INSTRUMENTS E oa Products from Texas Instruments 38 Test Output Signals The two digital output pins CCA and SFD can be set up to output test signals CC2420 IOCFG1 SFDMUX This is summarized in Table 12 and Table 13 below defined by IOCFG1 CCAMUX and CCAMUX Signal output on CCA pin Description 0 CCA Normal operation 1 ADC_Q 0 ADC Q branch LSB used for random number generation 2 DEMOD_RESYNC_LATE High one 16 MHz clock cycle each time the demodulator resynchronises late 3 LOCK_STATUS Lock status same as FSCTRL LOCK_STATUS 4 MOD_CHIPCLK Chip rate clock signal during transmission 5 MOD_SERIAL_CLK Bit rate clock signal during transmission 6 FFCTRL_FS_PD Frequency synthesizer power down active high 7 FFCTRL_ADC_PD ADC power down active high 8 FFCTRL_VGA_PD VGA power down active high 9 FFCTRL_RXBPF_PD Receiver bandpass filter power down active high 10 FFCTRL_LNAMIX_PD Receiver LNA Mixer power down active high 11 FFCTRL_PA_P_PD Power amplifier power down active high 12 AGC_UPDATE High one 16 MHz clock cycle each time the AGC updates its gain setting 13 VGA_PEAK_DET 1 VGA Peak detector gain stage 1 14 VGA_PEAK_DET 3 VGA Peak detector gain stage 3 15 AGC_LNAMIX_GAINMODE 1 RF receiver front end gain mode
81. est way of making a PER measurement will be to use another CC2420 as the reference transmitter However this makes it difficult to measure the exact receiver performance Using a signal generator this may either be set up as O QPSK with half sine shaping or as MSK If using O QPSK the phases must be selected according to 1 If using MSK the chip sequence must be modified such that the modulated MSK 35 PCB Layout Recommendations Following Texas Instruments s reference design is highly recommended In our reference design the top layer is used for signal routing and the open areas are filed with metallisation connected to ground using several vias Layer 2 has not been used in our CC2420 reference designs Layer 3 is used for power routing and the bottom layer serves as ground plane with a little routing The area under the chip is used for grounding and must be well connected to the ground plane with several vias The ground pins should be connected to ground as close as possible to the package pin using individual vias The de coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by 36 Antenna Considerations CC2420 can be used together with various types of antennas A differential antenna like a dipole would be the easiest to interface not needing a balun balanced to un balanced transformation network The length of the A 2 dipole antenna is giv
82. et Quadrature Phase Shift Keying Power Amplifier Printed Circuit Board Packet Error Rate Physical Layer PHY Header Phase Locked Loop PHY Service Data Unit Quad Leadless Package Random Access Memory Resolution BandWidth Radio Frequency Receive Signal Strength Indicator Receive SWRS041B Page 5 of 89 E Pisco Products CC2420 from Texas Instruments SHR Synchronisation Header SPI Serial Peripheral Interface TBD To Be Decided To Be Defined T R Transmit Receive TX Transmit VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier 2 References 1 IEEE std 802 15 4 2003 Wireless Medium Access Control MAC and Physical Layer PHY specifications for Low Rate Wireless Personal Area Networks LR WPANs http standards ieee org getieee802 download 802 15 4 2003 pdf 2 NIST FIPS Pub 197 Advanced Encryption Standard AES Federal Information Processing Standards Publication 197 US Department of Commerce N S T November 26 2001 Available from the NIST website http csrc nist gov publications fips fips197 fips 197 pdf 3 R Housley D Whiting N Ferguson Counter with CBC MAC CCM submitted to NIST June 3 2002 Available from the NIST website http csrc nist gov CryptoToolkit modes proposedmodes ProposedModesPa ge html we co SWRS041B Page 6 of 89 INSTRUMENTS E Chipcon Products 3 Wy TEXAS INSTRUMENTS from Texas Instruments Features 2400 2483 5
83. g sections requires that the chip is first reset the crystal oscillator is enabled using the SXOSCON command strobe and that the crystal oscillator has stabilised 33 1 Unmodulated carrier An unmodulated carrier may be transmitted by setting MDMCTRL1 TX_MODE to 2 or 3 writing kis TEXAS INSTRUMENTS SWRS041B Component values are given in Table 2 Using a differential antenna no balun is required If a single ended output is required for a single ended connector or a single ended antenna a balun should be used for optimum performance The balun adds the signals from the RF_N and RF_P This is achieved having two paths with equal amplitude response but 180 degrees phase difference 0x1800 to the DACTST register and issue a STXON command strobe The transmitter is then enabled while the transmitter Q DACs are overridden to static values An unmodulated carrier will then be available on the RF output pins A plot of the single carrier output spectrum from CC2420 is shown in Figure 31 below Page 54 of 89 E a Products from Texas Instruments CC2420 RBW 10 kHz RF Att 30 dB Ref Lvl VBW 10 kHz 3 dBm SWT 50 ms Unit dBm 3 i ES 10 20 30 have 1SA 40 50 60 70 80 90 97 Center 2 45 GHz 200 kHz Span 2 MHz Date 23 0CT 2003 21 38 33 Figure 31 Single carrier output 33 2 Modulated spectrum The CC2420 has
84. gure 4 The external components shown are described in Table 1 and typical values are given in Table 2 Note that most decoupling capacitors are not shown on the application circuits For the complete reference design please refer to Texas Instrument s web site http www ti com 9 1 Input output matching The RF input output is high impedance and differential The optimum differential load for the RF port is 95 j187 Q When using an unbalanced antenna such as a monopole a balun should be used in order to optimise performance The balun can be implemented using low cost discrete inductors and capacitors only or in combination with transmission lines Figure 3 shows the balun implemented in a two layer reference design It consists of a half wave transmission line C81 L61 L71 and L81 The circuit will present the optimum RF termination to CC2420 with a 50 Q load on the antenna connection This circuit has improved EVM performance sensitivity and harmonic suppression compared to the design in Figure 4 Please refer to the input output matching section on page 54 for more details The balun in Figure 4 consists of C61 C62 C71 C81 L61 L62 and L81 and will present the optimum RF termination to CC2420 with a 50 Q load on the antenna connection A low pass filter may be added to add margin to the FCC requirement on second harmonic level kis TEXAS INSTRUMENTS SWRS041B CC2420 If a balanced antenna such as a folded
85. he CHP to output down current when set the CHP to output down current when set CHP_DISABLE Set to manually disable charge pump by masking the up and down pulses from the phase detector I Selects short or long reset delay in phase detector 0 Short reset delay 1 Long reset delay gt STEP The charge pump current value step period 0 0 25 us 1 0 5 us 2 1us 3 4us STOP_CH E The charge pump current to stop at after the current is stepped down from START_CHP_CURRENT after VCO calibration is complete The current is stepped down periodically with intervals as defined in CHP_STEP_PERIOD START_CHP_ EN The charge pump current to start with after VCO calibration is complete The current is then stepped down periodically to the value STOP_CHP_CURRENT with intervals as defined in CHP_STEP_PERIOD Also used for overriding the charge pump current when CHP_CURRENT_OE 1 RXBPFTST 0x2B Receiver Bandpass Filters Test Register Ter reana CN aw EST pe reses ero E EI A E E E E o OI RXBPF_CAP_RE RX bandpass filter capacitance calibration result 0 Minimum capacitance in the feedback 1 Second smallest capacitance setting 127 Maximum capacitance in the feedback FSMSTATE 0x2C Finite state machine information FSM_CUR_STATE Provides the current state of the FIFO and Frame Control FFCTRL finite state machine
86. hen not being active Extremely low power consumption may be achieved when disabling also the voltage regulator This will require reprogramming of the register and RAM configuration 34 8 BER PER measurements CC2420 includes test modes where data is received infinitely and output to pins RX_MODE 2 see page 40 This mode may be used for Bit Error Rate BER measurements However the following actions must be taken to do such a measurement e A preamble and SFD sequence must be used even if pseudo random data is transmitted since receiving the DSSS modulated signal requires symbol synchronisation not bit synchronisation like e g in 2FSK systems The SYNCWORD may be set to another value to fit to the measurement setup if necessary e The data transmitted over air must be spread according to 1 and the description on page 24 This means that the transmitter used during measurements must be able to do spreading of the bit data to chip data Remember that the chip sequence transmitted by the test setup is not the same as the bit sequence which is output by CC2420 e When operating at or below the sensitivity limit CC2420 may loose symbol synchronisation in infinite receive mode A new SFD and restart of the receiver may be Wi TEXAS INSTRUMENTS SWRS041B CC2420 required to re gain synchronisation In an IEEE 802 15 4 system all communication is based on packets The sensitivity limit specified by 1
87. ht 0 0 0 7 A In receive mode CC2420 uses the preamble sequence for symbol synchronisation and frequency offset adjustments The SFD is used for byte synchronisation and is not part of the data stored in the receive buffer RXFIFO Preamble SFD IEEE 802 15 4 0 A CC2420 2 PREAMBLE_LENGTH 1 zero symbols SWO SW1 SW2 SW3 Each box corresponds to 4 bits Hence the preamble corresponds to 8 x 4 0 s or 4 bytes with the value 0 SWO SYNCWORD 3 0 if different from F else 0 SW1 SYNCWORD 7 4 if different from F else 0 SW2 SYNCWORD 11 8 if different from F else 0 SW3 SYNCWORD 15 12 if different from F else 0 Figure 18 Transmitted Synchronisation Header 16 2 Length field The frame length field shown in Figure 17 defines the number of bytes in the MPDU Note that the length field does not include the length field itself It does however include the FCS Frame Check Sequence even if this is inserted automatically by CC2420 hardware It also includes the MIC if authentication is used The length field is 7 bits and has a maximum value of 127 The most significant bit in the length field is reserved 1 and should be set to zero CC2420 uses the length field both for transmission and reception so this field xi TEXAS INSTRUMENTS SWRS041B must always be included In transmit mode the length field is used for underflow detection as de
88. is always high gain Ty LNAMIX_GAINMODE Status bit defining the currently selected gain mode selected by 1 0 the AGC or overridden by the LNAMIX_GAINMODE_O setting ki TEXAS SWRS041B Page 75 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments AGCTSTO 0x24 AGC Test Register 0 Loge LNAMIX_HYST 3 0 Hysteresis on the switching between different RF front end gain modes defined in 2 dB steps LNAMIX_THR_H Threshold for switching between medium and high RF front end gain mode defined in 2 dB steps LNAMIX_THR_L 5 Threshold for switching between low and medium RF front end gain mode defined in 2 dB steps AGC_BLANK_MODE Set the VGA blanking mode when switching out a gain stage When VGA_GAIN_OE 0 0 Blanking is performed when the AGC algorithm switches out one or more 14dB gain stages 1 Blanking is never performed When VGA_GAIN_OE 1 Blanking is performed when AGC_BLANK_MODE 1 CUR_BOOST Doubles the bias current in the peak detectors in between the VGA stages when set 12511 AGC_SE _WAIT 1 0 a O Timing Timing for AGC to wait for analog gain to settle AGC to wait for analog gain to settle 10 8 _PEAK_ E Sets the AGC mode for use of the VGA peak detectors it 2 Digital ADC peak detector enable disable it 1 Analog fixed stages peak detector enable disable it 0 Analog variable gain stage peak detector enable disable AGC_WIN_SIZE Window size for the accumulate
89. is calculated and continuously updated for each symbol after RSSI has become valid Page 48 of 89 E Pisco Products from Texas Instruments CC2420 RSSI Register Value RF Level dBm Figure 27 Typical RSSI value vs input power 24 Link Quality Indication The link quality indication LQI measurement is a characterisation of the strength and or quality of a received packet as defined by 1 The RSSI value described in the previous section may be used by the MAC software to produce the LQI value The LQI value is required by 1 to be limited to the range 0 through 255 with at least 8 unique values Software is responsible for generating the appropriate scaling of the LQI value for the given application Using the RSSI value directly to calculate the LQI value has the disadvantage that g a narrowband interferer inside the channel bandwidth will increase the LQI value although it actually reduces the true link quality CC2420 therefore also provides an average correlation value for each incoming packet based on the 8 first symbols following the SFD This unsigned 7 bit value can be looked upon as a measurement of the chip error rate although CC2420 does not do chip decision kis TEXAS INSTRUMENTS SWRS041B As described in the Frame check sequence section on page 38 the average correlation value for the 8 first symbols is appended to each received frame together with the RSSI a
90. is used as reference for the data rate as well as other internal signal processing functions other frequencies cannot be used If an external clock signal is used this should be connected to XOSC16_Q1 while xosc16_02 should be left open The MAIN XOSC16M_BYPASS bit must be set when an external clock signal is used Using the internal crystal oscillator the crystal must be connected between the XOSC16_Q1 and XOSC16_Q2 pins The oscillator is designed for parallel mode operation of the crystal In addition loading capacitors C384 and C391 for the crystal are required The loading capacitor values depend on the total load capacitance C specified for the crystal The total load capacitance seen between the crystal terminals should equal C for the crystal to oscillate at the specified frequency kis TEXAS INSTRUMENTS SWRS041B CC2420 Alternatively for a desired toggle voltage BATTMON_VOLTAGE should be set according to Vere BATTMON_VOLTAGE 72 27 1 25 V The voltage regulator must be enabled for at least 100 pus before the first measurement After being enabled the BATTMON_OK status bit needs 2 us to settle for each new toggle voltage programmed The main performance characteristics of the battery monitor is shown in the Electrical Specifications section on page 9 1 1 C parasitic A 381 Cs The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance The total
91. itally controlled The AGC Automatic Gain Control loop ensures that the ADC operates inside its 23 RSSI Energy Detection CC2420 has a built in RSSI Received Signal Strength Indicator providing a digital value that can be read from the 8 bit signed 2 s complement RSSI RSSI_VAL register The RSSI value is always averaged over 8 symbol periods 128 us in accordance with 1 The RSSI_VALID status bit Table 5 indicates when the RSSI value is valid meaning that the receiver has been enabled for at least 8 symbol periods The RSSI register value RSSI RSSI_VAL can be referred to the power P at the RF pins by using the following equations P RSSI_VAL RSSI_OFFSET dBm where the RSSI_OFFSET is found empirically during system development from the front end gain RSSI_OFFSET is approximately 45 E g if reading a value kis TEXAS INSTRUMENTS SWRS041B dynamic range by using an analog digital feedback loop The AGC characteristics are set through the AGCCTRL AGCTSTO AGCTST1 and AGCTST2 registers The reset values should be used for all AGC control and test registers of 20 from the RSSI register the RF input power is approximately 65 dBm A typical plot of the RSSI_VAL reading as function of input power is shown in Figure 27 lt can be seen from the figure that the RSSI reading from CC2420 is very linear and has a dynamic range of about 100 dB The RSSI register value RSST RSSI_VAL
92. le signed number on 2 s complement Unit is 1 dB offset is described in the RSSI Energy Detection section on page 48 The RSSI_VAL value is averaged over 8 symbol periods The RSSI_VALID status bit may be checked to verify that the receiver has been enabled for at least 8 symbol periods The reset value of 128 also indicates that the RSSI_VAL value is invalid ki TEXAS SWRS041B Page 65 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments SYNCWORD 0x14 Sync Word SYNCWORD 15 0 OxA70F Synchronisation word The SYNCWORD is processed from the least significant nibble F at reset to the most significant nibble A at reset SYNCWORD is used both during modulation where OxF s are replaced with 0x0 s and during demodulation where OxF s are not required for frame synchronisation In reception an implicit zero is required before the first symbol required by SYNCWORD The reset value is compliant with IEEE 802 15 4 TXCTRL 0x15 Transmit Control Register TX mixer buffer bias current 0 690uUA 1 980UA 2 1 16mA nominal 3 1 44mA TX_TURNAROUND Sets the wait time after STXON before transmission is started 0 8 symbol periods 128 us 1 12 symbol periods 192 us 12 11 11 TXMIX_CAP_ARRAY 1 TXMIX_CAP_ARRAY 1 0 EXE EN Selects varactor array settings in the transmit mixers ES 9 TXMIX_CURRENT 1 0 Transmit mixers current 0 1 72 mA 1 1 88 mA 2 2 05 mA 3 2 21 mA
93. ltage regulator should not be used to provide power to other circuits because of limited power sourcing capability and noise considerations The voltage regulator input pin VREG_IN is connected to the unregulated 2 1 to 3 6 V power supply The voltage regulator is enabled disabled using the active high voltage regulator enable pin VREG_EN The regulated 1 8 V voltage output is kis TEXAS INSTRUMENTS SWRS041B available on the VREG_OUT pin A simplified schematic of the voltage regulator is shown in Figure 28 The voltage regulator requires external components as described in the Application Circuit section on page 19 When disabling the voltage regulator note that register and RAM programming will be lost as leakage current reduces the output voltage on the VREG_OUT pin below 1 6 V CC2420 should then be reset before the voltage regulator is disabled Page 51 of 89 E Pisco Products from Texas Instruments In applications where the internal voltage regulator is not used connect VREG_EN and VREG_IN to ground VREG_OUT shall VREG_EN Regulator Enable disable Internal bandgap 1 25 V gt mH voltage reference CC2420 be left open Note that the battery monitor will not work when the voltage regulator is not used VREG_IN x VREG_OUT Figure 28 Voltage regulator simplified schematic 30 Battery Monitor Th
94. mbol De spreading is performed using over sampled symbol correlators Symbol kis TEXAS INSTRUMENTS SWRS041B synchronisation is achieved by a continuous start of frame delimiter SFD search When a SFD is detected data is written to the RXFIFO and may be read out by the microcontroller at a lower bit rate than the 250 kbps generated by the receiver The CC2420 demodulator also handles symbol rate errors in excess of 120 ppm without performance degradation Resynchronisation is performed continuously to adjust for error in the incoming symbol rate The RXCTRL1 RXBPF_LOCUR control bit should be written to 1 The MDMCTRL1 CORR_THR control bits are by default set to 20 defining the threshold for detecting IEEE 802 15 4 start of frame delimiters Page 35 of 89 E Pisco Products from Texas Instruments CC2420 Digital IF Channel Filtering 1 Q Analog IF signal Frequency Offset Compensation RSSI Generator Digital Symbol Data Correlators and Filtering Synchronisation Average Correlation Value may be used for LQI Figure 16 Demodulator Simplified Block Diagram 16 Frame Format CC2420 has hardware support for parts of the IEEE 802 15 4 frame format This section gives a brief summary to the IEEE 802 15 4 frame format and describes how CC2420 is set up to comply with this Figure 17 1 shows a schematic view of the IEEE 802 15 4 frame format Similar figures de
95. military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of Tl products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony
96. n In receive mode the FIFO pin can be used to detect if there is data at all in the receive FIFO The SFD pin can be used to extract the timing information of transmitted and received data frames The SED pin will go active when a start of frame delimiter has been completely detected transmitted The SFD pin should preferably be connected to a timer capture pin on the microcontroller For debug purposes the SFD and CCA pins can be used to monitor several status signals as selected by the IOCFG1 register See Table 12 and Table 13 for available signals The polarity of FIFO FIFOP SFD and CCA can be controlled by the IOCFGO register address 0x1C 15 Demodulator Symbol Synchroniser and Data Decision The block diagram for the CC2420 demodulator is shown in Figure 16 Channel filtering and frequency offset compensation is performed digitally The signal level in the channel is estimated to generate the RSSI level see the RSSI Energy Detection section on page 48 for more information Data filtering is also included for enhanced performance With the 40 ppm frequency accuracy requirement from 1 a compliant receiver must be able to compensate for up to 80 ppm or 200 kHz The CC2420 demodulator tolerates up to 300 kHz offset without significant degradation of the receiver performance Soft decision is used at the chip level i e the demodulator does not make a decision for each chip only for each received sy
97. n transmitting a zero symbol chip sequence Tc 0 5 us 11 Configuration Overview CC2420 can be configured to achieve the best performance for different applications Through the programmable configuration registers the following key parameters can be programmed e Receive transmit mode e RF channel selection e RF output power vy TEXAS INSTRUMENTS SWRS041B Power down power up mode Crystal oscillator power up power down Clear Channel Assessment mode Packet handling hardware support Encryption Authentication modes Page 25 of 89 Ehipcon Products CC2420 from Texas Instruments 12 Evaluation Software Texas Instruments TI provides users of Studio can be downloaded from _ TI s web CC2420 with a software program page http www ti com Figure 8 shows SmartRF Studio Windows interface the user interface of the CC2420 which may be used for radio performance configuration software and functionality evaluation SmartRF Calculation Window CC2420 SmartRF Studio DMCTRL1 0x12 0x0000 SSI 0x13 00000 NCWORD 0x14 0x0000 CTRL 0x15 00000 RXCTRLO 0x16 0x0000 l RXCTRL1 0x17 0x0000 l FSCTAL 018 0x0000 SECCTALO 0x19 0x0000 Es SECCTRL1 011A 0x0000 l BATTMON 0x1B 00000 AGCCTAL 0x23 00000 AGCTSTO 0x24 Ox0000 AGCTST1 0x25 0x0000 AGCTST2 0x26 0x0000 FSTSTO 0x27 0x0000 Modem Control Register 0 Figure 8 SmartRF Studio u
98. nd CRC OK not OK when MDMCTRLO AUTOCRC is set A correlation value of 110 indicates a maximum quality frame while a value of 50 is typically the lowest quality frames detectable by CC2420 Software must convert the correlation value to the range 0 255 defined by 1 e g by calculating LQI CORR a b limited to the range 0 255 where a and b are found empirically based on PER measurements as a function of the correlation value A combination of RSSI and correlation values may also be used to generate the LQI value Page 49 of 89 E oa Products from Texas Instruments 25 Clear Channel Assessment The clear channel assessment signal is based on the measured RSSI value and a programmable threshold The clear channel assessment function is used to implement the CSMA CA functionality specified in 1 CCA is valid when the receiver has been enabled for at least 8 symbol periods Carrier sense threshold level is programmed by RSSI CCA_THR The threshold value can be programmed in steps of 1 dB A CCA hysteresis can also be programmed in the MDMCTRLO CCA_HYST control bits All 3 CCA modes specified by 1 are implemented in CC2420 They are set in MDMCTRLO CCA_MODE as can be seen in the register description The different modes are CC2420 0 Reserved 1 Clear channel when received energy is below threshold 2 Clear channel when not receiving valid IEEE 802 15 4 data 3 Clear channel when energy
99. nected as close as possible to the IC If the antenna is located away from the RF pins the antenna should be matched to the feeding transmission line 50 Q Page 60 of 89 E Pisa Products from Texas Instruments 37 Configuration Registers The configuration of CC2420 is done by programming the 16 bit configuration registers Complete descriptions of the registers are given in the following tables After chip reset from the RESETn pin or programmable through the MAIN RESETn configuration bit all the registers have default values as shown in the tables Note that the MAIN register is only reset by using the pin reset RESETn When writing to this register all bits will get the value written not the default value This also means that the MAIN RESETn bit must be written both low and then high to perform a chip reset through the serial interface 15 registers are Strobe Command Registers listed first in Table 11 below Accessing these registers will initiate the change of an internal state or mode There CC2420 are 33 normal 16 bits registers also listed in Table 11 Many of these registers are for test purposes only and need not be accessed for normal operation of CC2420 The FIFOs are accessed through two 8 bit registers TXFIFO and RXFIFO The TXFIFO register is write only Data may still be read out of the TXFIFO through regular RAM access see section RAM access section
100. nnecting TXRX_SWITCH to RF_P and RF_N through an external DC path modes are also available for test purposes The frequency synthesizer includes a completely on chip LC VCO and a 90 degrees phase splitter for generating the ki TEXAS SWRS041B Page 17 of 89 INSTRUMENTS interface E a Products from Texas Instruments and Q LO signals to the down conversion mixers in receive mode and up conversion mixers in transmit mode The VCO operates in the frequency range 4800 4966 MHz and the frequency is divided by two when split in and Q A crystal must be connected to XOSC16_Q1 and xX0OSC16_Q2 and provides the reference frequency for the synthesizer A digital lock signal is available from the PLL The digital baseband includes support for frame handling address recognition data buffering and MAC security vy TEXAS INSTRUMENTS SWRS041B CC2420 The 4 wire SPI serial interface is used for configuration and data buffering An on chip voltage regulator delivers the regulated 1 8 V supply voltage The voltage regulator may be enabled disabled through a separate pin A battery monitor may optionally be used to monitor the unregulated power supply voltage The battery monitor is configurable through the SPI interface Page 18 of 89 E Pisco Products from Texas Instruments 9 Application Circuit Few external components are required for the operation of CC2420 A typical application circuit is shown in Fi
101. on page 29 but data is then not removed from the FIFO Note that the crystal oscillator must be active for all FIFO and RAM access During address transfer and while data is being written to the TXFIFO a status byte is returned on the serial data output pin So This status byte is described in Table 5 on page 29 All configuration and status registers are described in the tables following Table 11 Address Register Register type Description 0x00 SNOP S No Operation has no other effect than reading out status bits 0x01 SXOSCON S Turn on the crystal oscillator set XOSC16M_PD 0 and BIAS_PD 0 0x02 STXCAL S Enable and calibrate frequency synthesizer for TX Go from RX TX to a wait state where only the synthesizer is running 0x03 SRXON S Enable RX 0x04 STXON S Enable TX after calibration if not already performed Start TX in line encryption if SPI_SEC_MODE 0 0x05 STXONCCA S If CCA indicates a clear channel Enable calibration then TX Start in line encryption if SPI_SEC_MODE 0 else do nothing 0x06 SRFOFF S Disable RX TX and frequency synthesizer 0x07 SXOSCOFF Turn off the crystal oscillator and RF 0x08 SFLUSHRX S Flush the RX FIFO buffer and reset the demodulator Always read at least one byte from the RXFIFO before issuing the SFLUSHRX command strobe 0x09 SFLUSHTX S Flush the TX FIFO buffer Ox0A SACK S Send acknowledge frame with pending field cleared 0x0B SACKPEND
102. ows 0 Off 1 Output AGC status gain setting peak detector status accumulator value Output ADC and Q values Output I Q after digital down mix and channel filtering Reserved Reserved Input ADC and Q values Input DAC and Q values NOOB WP The HSSD module requires that the FS is up and running as it uses CLK_PRE 150 MHZ to produce its 37 5 MHz data clock and serialize its output words 95 SFDMUX 4 0 0 R W Multiplexer setting for the SFD pin 4 0 CCAMUX 4 0 0 R W Multiplexer setting for the CCA pin MANFIDL 0x1E Manufacturer ID Lower 16 Bit ista 12 CE 7 fo The device part number CC2420 has part number 0x002 E 1 50 MANFID 11 0 0x33D Gives the JEDEC manufacturer ID The actual manufacturer ID can be found in MANIFID 7 1 the number of continuation bytes in MANFID 11 8 and MANFID O 1 Chipcon s JEDEC manufacturer ID is Ox7F Ox7F Ox7F Ox9E Ox1E preceded by three continuation bytes ki TEXAS SWRS041B Page 72 of 89 INSTRUMENTS E a Products CC2420 from Texas Instruments MANFIDH 0x1F Manufacturer ID Upper 16 Bit Ce IN 15 12 VERSION 3 0 Version number Current version is 3 Note that previous CC2420 versions will have lower reset values 11 0 earrmwompi5 4J o r The device part number CC2420 has part number 0x002 The device part number CC2420 has part number 0x002 device part number CC2420 has part number 0x002 FSM
103. quency synchronisation scheme must then be implemented within the proprietary MAC layer to make the transmitter and receiver operate on the same RF channel 34 2 Data burst transmissions The data buffering in CC2420 lets the user have a lower data rate link between the microcontroller and the RF device than the RF bit rate of 250 kbps This allows the microcontroller to buffer data at its own speed reducing the workload and timing requirements The relatively high data rate of CC2420 also reduces the average power consumption compared to the 868 915 MHz bands defined by 1 where only 20 40 kbps are available CC2420 may be powered up a smaller portion of the time so that the average power consumption is reduced for a given amount of data to be transferred xi TEXAS INSTRUMENTS SWRS041B 34 3 Crystal accuracy and drift A crystal accuracy of 40 ppm is required for compliance with IEEE 802 15 4 1 This accuracy must also take ageing and temperature drift into consideration A crystal with low temperature drift and low aging could be used without further compensation A trimmer capacitor in the crystal oscillator circuit in parallel with C7 could be used to set the initial frequency accurately For non lIEEE 802 15 4 systems the robust demodulator in CC2420 allows up to 120 ppm total frequency offset between the transmitter and receiver This could e g relax the accuracy requirement to 60 ppm for each of the
104. r Sequence Counter Counter SWRS041B Table 7 IEEE 802 15 4 Nonce 1 The block counter bytes are not updated in RAM only in a local copy that is reloaded for each new in line security operation l e the block counter part of the nonce does not need to be rewritten The CC2420 block counter should be set to 0x0001 for compliance with 1 CC2420 gives the user full flexibility in selecting the flags for both nonces The Page 45 of 89 E Pisco Products from Texas Instruments flag setting is stored in the most significant byte of the nonce The flag byte used for encryption and authentication is then generated as shown in Figure 26 MSB in CC2420 nonce RAM CBC MAC flag byte oo 7 6 5 4 3 2 1 0 CTR Flag CBC Flag bits 7 6 bits 7 6 _ CTR mode flag byte Y 7 6 5 4 3 2 1 0 Res Res 0 0 0 E CC2420 The frame counter part of the nonce must be incremented for each new packet by software SECCTRLO SEC_M T 6 5 4 3 2 Res Adata M L Figure 26 CC2420 Security Flag Byte 21 3 Stand alone encryption Plain AES encryption with 128 bit plaintext and 128 bit keys 2 is available using stand alone encryption The plaintext is stored in stand alone buffer located at RAM location 0x120 as can be seen from Table 6 on page 31 A stand alone encryption operation is initiated
105. rly applies to active and passive scans as defined by 1 which requires all received beacons to be processed by the MAC sublayer Incoming frames with reserved frame types FCF frame type subfield is 4 5 6 or 7 is however accepted if the RESERVED_FRAME_MODE control bit in MDMCTRLO is set In this case no further address recognition is performed on these frames This option is included for future expansions of the IEEE 802 15 4 standard If a frame is rejected CC2420 will only start searching for a new frame after the rejected frame has been completely received as defined by the length field to avoid detecting false SFDs within the frame The MDMCTRLO PAN_COORDINATOR control bit must be correctly set since parts of the address recognition procedure requires knowledge about whether the current device is a PAN coordinator or not recognition with the acknowledge request flag set and a valid CRC AUTOACK therefore does not make sense unless also ADR_DECODE and AUTOCRC are enabled The sequence number is copied from the incoming frame Page 41 of 89 E a Products from Texas Instruments AUTOACK may be used for non beacon systems as long as the frame pending field see Figure 19 is cleared The acknowledge frame is then transmitted 12 CC2420 symbol periods after the last symbol of the incoming frame This is as specified by 1 for non beacon networks Bytes
106. rols whether the ATEST2 in is used to output the VC node voltage 0 or to control the VC node voltage 1 ESTMOD_PD Powerdown of analog test module 0 Power up 1 Power down ESTMOD_MODE 3 When ATESTMOD_PD 0 the function of the analog test module is as follows 0 Outputs I ATEST1 and Q ATEST2 from RxMIX 1 Inputs I ATEST2 and Q ATEST1 to BPF 2 Outputs I ATEST1 and Q ATEST2 from VGA 3 Inputs l ATEST2 and Q ATEST1 to ADC 4 Outputs I ATEST1 and Q ATEST2 from LPF 5 Inputs I ATEST2 and Q ATEST1 to TxMIX 6 Outputs P ATEST1 and N ATEST2 from Prescaler Must be terminated externally 7 Connects TX IF to RX IF and simultaneously the ATEST1 pin to the internal VC node see VC_IN_TEST_EN 8 Connect ATEST1 input to ATEST2 output through single2diff and diff2single buffers used for measurements on the test interface RESERVED 0x30 Reserved register containing spare control and status bits ENE RES 15 0 CEE Reserved for future use TXFIFO 0x3E Transmit FIFO Byte register TEO TXFIFO 7 0 W Transmit FIFO byte register write only Reading the TXFIFO is only possible using RAM read Note that the crystal oscillator must be running for writing to the TXFIFO RXFIFO 0x3F Receive FIFO Byte register 7 0 RXFIFO 7 0 R W Receive FIFO byte regist
107. rom to RF FIFO ADDReico ADATA veo Read or write n bytes from to RAM DATA pte ADDRL gam ADDR Ham DATA apor DATA saps DATA opps ae X DATA moore DATA tes A DATA tes DATA te na ADATA pro no DATA puto net Note FIFO and RAM access must be terminated with setting the CSn pin high Command strobes and register access may be followed by any other access since they are completed on the last negative edge on SCLK They may however also be terminated with setting CSn high if desirable e g for reading only 8 bits from a configuration register Figure 10 Configuration registers write and read operations via SPI kis TEXAS INSTRUMENTS SWRS041B Page 30 of 89 E Passar Products from Texas Instruments CC2420 Address Byte Ordering Name Description Ox16F Not used 0x16C 0x16B MSB SHORTADR 16 bit Short address used for address recognition 0x16A LSB 0x169 MSB PANID 16 bit PAN identifier used for address recognition 0x168 LSB 0x167 MSB IEEEADR 64 bit IEEE address of current node used for address 0x160 LSB recognition Ox15F MSB CBCSTATE Temporary storage for CBC MAC calculations 0x150 LSB 0x14F MSB Flags TXNONCE TXCTR Transmitter nonce for in line authentication and 0x140 LSB transmitter counter for in line encryption 0x13F MSB KEY1 Encryption key 1 0x130 LSB 0x12F MSB SABUF Stand alone encryption buffer for plaintext input an
108. scribed in the FIFO access section on page 31 16 3 MAC protocol data unit The FCF data sequence number and address information follows the length field as shown in Figure 17 Together with the MAC data payload and Frame Check Sequence they form the MAC Protocol Data Unit MPDU The format of the FCF is shown in Figure 19 Please refer to 1 for details Page 37 of 89 E Pisco Products from Texas Instruments There is no hardware support for the data sequence number this field must be inserted and verified by software CC2420 CC2420 includes hardware address recognition as described in the Address Recognition section on page 41 Bits 0 2 3 4 5 6 7 9 10 11 12 13 14 15 Frame Security Frame Acknowledge Intra Reserved Destination Reserved Source Type Enabled Pending request PAN addressing addressing mode mode Figure 19 Format of the Frame Control Field FCF 1 16 4 Frame check sequence A 2 byte frame check sequence FCS follows the last MAC payload byte as shown in Figure 17 The FCS is calculated over the MPDU i e the length field is not part of the FCS This field is automatically generated and verified by hardware when the MODEMCTRLO AUTOCRC control bit is set It is recommended to always have this enabled except possibly for debug purposes If cleared CRC generation and verification must be performed by software The FCS polynomial is 1 xo 4 x24 4
109. scribing specific frame formats data frames beacon frames acknowledgment frames and MAC command frames are included in 1 Data Symbol Output Bytes 2 1 0 to 20 n 2 Frame Data Frame Check MA nes Control Field Sequence Snare Frame payload Sequence FCF Number FCS MAC Header MHR MAC Payload MAC Footer MFR Bytes 4 1 1 5 0 to 20 n PHY Preamble Siart or frame Frame pS Sa Laver Sequence Delimiter ena Data Unit y q SFD g MPDU Synchronisation Header PHY Header PHY Service Data Unit SHR PHR PSDU 11 0 to 20 n PHY Protocol Data Unit PPDU Figure 17 Schematic view of the IEEE 802 15 4 Frame Format 1 16 1 Synchronisation header The synchronisation header SHR consists of the preamble sequence followed by the start of frame delimiter SFD In 1 the preamble sequence is defined to be 4 bytes of 0x00 The SFD is one byte set to 0xA7 In CC2420 the preamble length and SFD is configurable The default values are compliant with 1 Changing these values will make the system non compliant to IEEE 802 15 4 A synchronisation header is always transmitted first in all transmit modes Wi TEXAS INSTRUMENTS SWRS041B The preamble sequence length can be set by MDMCTRLO PREAMBLE_LENGTH while the SFD is programmed in the SYNCWORD register SYNCWORD is 2 bytes long which gives the user some extra flexibility as described below Figure 18 shows how
110. ser interface kis TEXAS SWRS041B Page 26 of 89 INSTRUMENTS E epesi Products from Texas Instruments CC2420 13 4 wire Serial Configuration and Data Interface CC2420 is configured via a simple 4 wire SPl compatible interface pins SI So SCLK and CSn where CC2420is the slave This interface is also used to read and write buffered data see page 39 All address and data transfer on the SPI interface is done most significant bit first 13 1 Pin configuration The digital inputs SCLK SI and CSn are high impedance inputs no internal pull up and should have external pull ups if not driven so is high impedance when CSn is high An external pull up should be used at so to prevent floating input at microcontroller Unused I O pins on the MCU can be set to outputs with a fixed 0 level to avoid leakage currents 13 2 Register access There are 33 16 bit configuration and status registers 15 command strobe registers and two 8 bit registers to access the separate transmit and receive FIFOs Each of the 50 registers is addressed by a 6 bit address The RAM Register bit bit 7 must be cleared for register access The Read Write bit bit 6 selects a read or a write operation and makes up the 8 bit address field together with the 6 bit address In each register read or write cycle 24 bits are sent on the Sl line The CSn pin Chip Select active low must be kept low during this transfer The bit to be sent first is th
111. smitted bit stream gt LSB first Bit to Symbol Symbol to Chip Modulated Signal O QPSK Modulator Figure 6 Modulation and spreading functions 1 Symbol Chip sequence Co C4 Co C31 0 11011001110000110101001000101110 1 11101101100111000011010100100010 2 00101110110110011100001101010010 3 00100010111011011001110000110101 4 01010010001011101101100111000011 5 00110101001000101110110110011100 6 11000011010100100010111011011001 7 10011100001101010010001011101101 8 10001100100101100000011101111011 9 10111000110010010110000001110111 10 01111011100011001001011000000111 11 01110111101110001100100101100000 12 00000111011110111000110010010110 13 01100000011101111011100011001001 14 10010110000001110111101110001100 15 11001001011000000111011110111000 Table 3 IEEE 802 15 4 symbol to chip mapping 1 The modulation format is Offset Quadrature Phase Shift Keying O QPSK with half sine chip shaping This is equivalent to MSK modulation Each chip kis TEXAS INSTRUMENTS SWRS041B is shaped as a half sine transmitted alternately in the and Q channels with one half chip period offset This is illustrated for the zero symbol in Figure 7 Page 24 of 89 E Pisco Products from Texas Instruments Te gt e CC2420 tonaos N BAON N A AA AA SAA AYIYA NY IU O URNA O gt 2 Te Figure 7 I Q Phases whe
112. terfacing circuit e g microcontroller Supply voltage VDD on AVDD_VCO DVDD1 8 i 2 0 V The typical application uses regulated etc pin no 1 2 3 4 10 14 15 17 18 20 26 35 1 8 V supply generated by the on chip 37 44 and 48 voltage regulator Operating ambient temperature range Ta wo 85 C ki TEXAS SWRS041B Page 8 of 89 INSTRUMENTS E Pisa Products CC2420 from Texas Instruments 6 Electrical Specifications Measured on CC2420 EM with transmission line balun Ta 25 C DVDD3 3 and VREG_IN 3 3 V internal voltage regulator used if nothing else stated 6 1 Overall RF Frequency Range 2400 2483 5 MHz Programmable in 1 MHz steps 5 MHz steps for compliance with 1 6 2 Transmit Section _ fae ae call _ Transmit chip rate 2000 mm 2000 kChips s As defined by 1 Nominal output power Delivered to a single ended 50 Q load through a balun 1 requires minimum 3 dBm Programmable output power range The output power is programmable in 8 steps from Harmonics 2 harmonic 3 harmonic approximately 24 to 0 dBm dBm Measured conducted with 1 MHz dBm 44 resolution bandwidth on spectrum 64 analyser At max output power delivered to a single ended 50 Q load through a balun See page 54 Spurious emission Maximum output power dBm Complies with EN 300 328 EN dBm 300 440 FCC CFR47 Part 15 dBm and ARIB STD T 66 dBm Measured as defined by 1 1 r
113. the CC2420 synchronisation header relates to the IEEE 802 15 4 specification H The programmable preamble length only applies to transmission it does not affect receive mode The preamble length should not be set shorter than the default value Note that 2 of the 8 zero symbols in the preamble sequence required by 1 are included in the SYNCWORD register so that the CC2420 preamble sequence is only 6 symbols long for compliance with 1 Two Page 36 of 89 E a Products from Texas Instruments additional zero symbols in SYNCWORD make CC2420 compliant with 1 In reception CC2420 synchronises to received zero symbols and searches for the SFD sequence defined by the SYNCWORD register The least significant symbols in SYNCWORD set to OxF will be ignored while symbols different from OxF will be required for synchronisation The default setting of OxA7OF thereby requires one additional zero symbol for synchronisation This will reduce the number of false frames detected due to noise The following illustrates how the programmed synch word is interpreted during reception by CC2420 If SYNCWORD OxA7FF CC2420 will require the incoming symbol sequence of from left to Synchronisation Header CC2420 right O 7 A If SYNCWORD OXA7OF CC2420 will require the incoming symbol sequence of from left to right O 0 7 A If SYNCWORD OxA700 CC2420 will require the incoming symbol sequence of from left to rig
114. tire document In Voltage regulator section of Electrical Specifications voltage regulator may only supply CC2420 MANF IDH VERSION register changed to current version is 2 Included package height in package drawing Included layout drawing for package Power supply pins defined clearer in Absolute maximum ratings Third harmonic level corrected to 51dBm in Electrical specifications second harmonic to 37dBm Table with Crystal oscillator component values corrected Link to reference 3 corrected Corrected spelling grammar and references to tables and figures Figure showing SmartRF Studio user interface included Added figure to describe pin activity during RXFIFO read out Added description on how to connect pins when not using internal regulator 1 1 2004 03 22 Application circuits Pin 20 and pin 37 connected to 1 8 V from VREG_OUT IOCFGO SO_PULLUP deleted Added document history table 2003 11 17 Initial release 42 2 Product Status Definitions Data Sheet Identification Product Status Advance Information Planned or Under This data sheet contains the design specifications for Development product development Specifications may change in any manner without notice Preliminary Engineering Samples This data sheet contains preliminary data and and First Production supplementary data will be published at a later date Chipcon reserves the right to make changes at any time without notice in order to improve design
115. tive low reset of the demodulator module Test purposes only R W Active low reset of the modulator module Test purposes only Active low reset of the frequency synthesizer module Test purposes only fo f Reserved write as O E XOSC16M_BYPASS Bypasses the crystal oscillator and uses a buffered version of the signal on Q1 directly This can be used to apply an external rail rail clock signal to the Q1 pin oe ki TEXAS SWRS041B Page 63 of 89 INSTRUMENTS E Pisco Products CC2420 from Texas Instruments MDMCTRLO 0x11 Modem Control Register 0 Mode for accepting reserved IEE 802 15 4 frame types when address recognition is enabled MDMCTRLO ADR_DECODE 1 0 Reserved frame types 100 101 110 111 are rejected by address recognition 1 Reserved frame types 100 101 110 111 are always accepted by address recognition No further address decoding is done When address recognition is disabled MDMCTRLO ADR_DECODE 0 all frames are received and RESERVED_FRAME MODE is don t care PAN_COORDINATOR Should be set high when the device is a PAN Coordinator Used for filtering packets with no destination address as specified in section 7 5 6 2 in 802 15 4 D18 Hardware Address decode enable 0 Address decoding is disabled 1 Address decoding is enabled
116. to buffer data received by the demodulator Accessing data in the RXFIFO is described in the FIFO access section on page 31 The FIFO and FIFOP pins are used to assist the microcontroller in supervising the RXFIFO Please note that the FIFO and FIFOP pins are only related to the RXFIFO even if CC2420 is in transmit mode Page 39 of 89 E a Products from Texas Instruments Multiple data frames may be in the RXFIFO simultaneously as long as the total number of bytes does not exceed 128 See the RXFIFO overflow section on page 33 for details on how a RXFIFO overflow is detected and signalled 17 3 Unbuffered serial mode Unbuffered mode should be used for evaluation debugging purposes only Buffered mode is recommended for all applications In unbuffered mode the FIFO and FIFOP pins are reconfigured as data and data clock pins The TXFIFO and RXFIFO buffers are not used in this mode A synchronous data clock is provided by CC2420 at the FIFOP pin and the FIFO pin is used as data input output The FIFOP clock frequency is 250 kHz when active This is illustrated in Figure 22 CC2420 In serial transmit mode MDMCTRL1 TX_MODE 1 a synchronisation sequence is inserted at the start of each frame by hardware as in buffered mode Data is sampled by CC2420 on the positive edge of FIFOP and should be updated by the microcontroller on the negative edge of FIFOP See Figure 22 for an illustration of the timing in serial
117. tor kis TEXAS SWRS041B INSTRUMENTS e Wireless sensor networks e PC peripherals e Consumer Electronics features reduce the load on the host controller and allow CC2420 to interface low cost microcontrollers The configuration interface and transmit receive FIFOs of CC2420 are accessed via an SPI interface In a typical application CC2420 will be used together with a microcontroller and a few external passive components CC2420 is based on Chipcon s SmartRF 03 technology in 0 18 um CMOS Programmable output power No external RF switch filter needed I Q low IF receiver 1 Q direct upconversion transmitter Very few external components 128 RX 128 TX byte data buffering Digital RSSI LQI support Hardware MAC encryption AES 128 Battery monitor QLP 48 package 7x7 mm Complies with ETSI EN 300 328 EN 300 440 class 2 FCC CFR 47 part 15 and ARIB STD T66 e Powerful and flexible development tools available Page 1 of 89 E Pisco Products from Texas Instruments Table of contents CC2420 1 Abbreviations 5 2 References 6 3 Features 7 4 Absolute Maximum Ratings 8 5 Operating Conditions 8 6 Electrical Specifications 9 6 1 Overall 9 6 2 Transmit Section 9 6 3 Receive Section 10 6 4 RSSI Carrier Sense 11 6 5 IF Section 11 6 6 Frequency Synthesizer Section 11
118. urred during transmission Must be cleared manually with a SFLUSHTX command strobe 0 No underflow has occurred 1 An underflow has occurred 4 ENC_BUSY Indicates whether the encryption module is busy 0 Encryption module is idle 1 Encryption module is busy 3 TX_ACTIVE Indicates whether RF transmission is active 0 RF Transmission is idle 1 RF Transmission is active 2 LOCK Indicates whether the frequency synthesizer PLL is in lock or not 0 The PLL is out of lock 1 The PLL is in lock 1 RSSI_VALID Indicates whether the RSSI value is valid or not 0 The RSSI value is not valid 1 The RSSI value is valid always true when reception has been enabled at least 8 symbol periods 128 us 0 Reserved ignore value Table 5 Status byte returned during address transfer and TXFIFO writing 13 4 Command strobes Command strobes may be viewed as single byte instructions to CC2420 By addressing a command strobe register internal sequences will be started These commands must be used to enable the crystal oscillator enable receive mode start decryption etc All 15 command strobes are listed in Table 11 on page 62 When the crystal oscillator is disabled Power Down state in Figure 25 on page 44 only the SXOSCON command strobe may be used All other command strobes will be ignored and will have no effect The crystal oscillator must stabilise see the XOSC16M_STABLE status bit in Table 5 before other command strobes are a
119. when calibration in progress and 0 otherwise Synchronisation window pulse width 0 2 prescaler clock periods recommended 1 4 prescaler clock periods LOCK_STATUS Frequency synthesizer lock status 0 Frequency synthesizer is out of lock 1 Frequency synthesizer is in lock Frequency control word controlling the RF operating frequency Fc In transmit mode the local oscillator LO frequency equals Fc In receive mode the LO frequency is 2 MHz below Fc 2405 _ MEZ Fc 2048 FREQ 9 0 MHz See the Frequency and Channel Programming section on page 50 for further information ki TEXAS SWRS041B Page 69 of 89 INSTRUMENTS E Passar Products CC2420 from Texas Instruments SECCTRLO 0x19 Security Control Register RXFIFO_PROTECTION Protection enable of the RXFIFO see description in the RXFIFO overflow section on page 33 Should be cleared if MAC level security is not used or is implemented outside CC2420 Defines what to use for the first byte in CBC MAC does not apply to CBC MAC part of CCM O Use the first data byte as the first byte into CBC MAC 1 Use the length of the data to be authenticated calculated as the packet length field SEC_TXL 2 for TX or using SEC_RXL for RX as the first byte into CBC MAC before the first data byte This bit should be set high for CBC MAC 802 15 4 inline security Stand Alone Key select 0 Key 0 is used 1 Key 1
120. y operations are based on AES encryption 2 using 128 bit keys Security operations are performed within the transmit and receive FIFOs on a frame basis CC2420 also includes stand alone AES encryption in which one 128 bit plaintext is encrypted to a 128 bit ciphertext The SAES STXENC and SRXDEC command strobes are used to start security operations in CC2420 as will be described in the following sections The ENC_BUSY status bit see Table 5 may be used to monitor when a security operation has been completed Security command strobes issued while the security engine is busy will be ignored and the ongoing operation will be completed Table 6 on page 31 shows the CC2420 RAM memory map including the security related data located from addresses 0x100 through 0x15F RAM access see the RAM access section on page 29 is used to write or read the keys nonces and stand alone buffer All security related data is stored little endian i e the least significant byte is transferred first over the SPI interface during RAM read or write operations For a complete description of IEEE 802 15 4 MAC security operations please refer to 1 21 1 Keys All security operations are based on 128 bit keys The CC2420 RAM space has storage space for two individual keys KEYO and KEY1 Transmit receive and stand alone encryption may select one of these two keys individually in the SEC_TXKEYSEL SEC_RXKEYSEL and SEC_SAKEYSE

Texas Instruments 3138 155 232931 User's Manual

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