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SMSC USB2250 User's Manual

1. 0 25 027 L4 DETAIL A R EVISION HISTORY REVISON DESCRIP TION DATE RELEASED BY SEE SPECF PONT PAGE FORREM SIONHISTORY REMARK WERALL PACKAG STAN DC xy PyP PY EAD FOQT LENG LEAD LENG WI THICKNESS U 40 BS PITCH NOTES JIDER RADIUS OT RADIUS LANARITY 1 ALL DIMENSIONS ARE IN MILLIME TE R 2 TRUE POSITION SPREAD TOLE RANCE OF EACH LEAD IS 0 035mm MAXIMUM 3 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSIONS M AXIMUM ALLOWED PROTRUSION IS 0 25 mm PER SIDE 4 DIMENSION L IS MEASURED AT THE GAUGE PLANE 0 25mm ABOVE THE SEATING PLANE 5 DETAILS ON PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATE D UNLESS OTHERMSESPEQFIED DIMENSIONS ARE INMILLIME TERS AND TOLERANCESARE DECIMAL ANGULAR XX 304 15 XXX 40 05 X XXX 0 025 INTEFPRET DM ANDTO PER ASMEY 145 M 1994 TH FD ANG E PRO ECT ON 80 ARKAY DRIVE ILL HAUPPAUGE NY 11788 USA ANEAFAR KY EKO PACKAGE OUTLINE MATERAL S K ILIEV 128 VTQFP 14x14x1 Omm BODY 0 4mm PITCH 12A7 04 CHECKED S K ILIEV DWG NUMBER FEV 12 17 04 MO 128 V TQFP 14x 14x 1 0 C PANT WTH SCALE TO FIT DO NOT SCALEDRAWNG Figure 9 1 USB2250 50i 51 51i 128 Pin VTQFP 14x14x1 0mm Body APPRO ED S K ILIEV STD COMPLIANCE 12 7 04 JEDEC MS 026 D 2 0mm Pitch
2. 0 C to 70 C 40 C to 85 C 0 C to 70 C 40 C to 85 C SMSC 80 ARKAY DRIVE HAUPPAUGE NY 11788 631 435 6000 FAX 631 273 3123 Copyright 2008 SMSC or its subsidiaries All rights reserved Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications Consequently complete information sufficient for construction purposes is not necessarily given Although the information has been checked and is believed to be accurate no responsibility is assumed for inaccuracies SMSC reserves the right to make changes to specifications and product descriptions at any time without notice Contact your local SMSC sales office to obtain the latest specifications before placing your product order The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC s standard Terms of Sale Agreement dated before the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use i
3. Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Datasheet List of Figures Figure 2 1 USB2250 50i 51 51i Block Diagram 7 Figure 4 1 USB2250 50i 51 51i 128 Pin VTQFP Diagram e 10 Figure 6 1 Pin Reset States soe re 82 60050 qud 256685484544 RIS 21 Figure 6 2 Legend for Pin Reset States Table nen 21 Figure 6 3 USB2250 50i 51 51i Pin Reset States _ 22 Figure 7 1 Supply Rise Time Model rn 29 Figure 8 1 Typical Crystal Circuit RR rn 33 Figure 8 2 Formula to Find Value of C1 and C2 ees 33 Figure 9 1 USB2250 50i 51 51i 128 Pin VTQFP 14x14x1 0mm Body 2 0mm Pitch 34 Revision 1 1 05 29 08 SMSC USB2250 50i 51 51i 4 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller Datasheet List of Tables Table 0 1 USB2250 50i 51 51iComparison of Features 2 Table 3 1 USB2250 50i 51 51i 128 Pin VTOFP Package es 8 Table 5 2 USB2250 50i 51 51i Buffer Type Descriptions llli 20 Table 7 1 Pin Capacitance aaa 32 Table 10 1 USB2250 50i 51 51i GPIO Usage ROM Rev 0x00 35 SMSC USB2250 50i 51 51i 5 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Chapter 1 Acronyms Datasheet CF Compact Flash CFC Compact Flash Controller EEPROM Electrically
4. high while nRESET is asserted Datasheet MISC General Purpose LED1 GPIO1 120 012 GPIO This pin may be used either as input I O edge sensitive interrupt input or output LED In addition as an output the GPIO1 can be used output controlled by the LED1_GPIO1 register General Purpose GPIOS3 121 O12 This pin may be used either as input edge VO VBUS DET sensitive interrupt input or output This pin is not 5V tolerant An external resistor divider must be used when connected to VBUS SMSC USB2250 50i 51 51i 17 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTOFP TYPE DESCRIPTION General Purpose GPIO4 118 O12 GPIO This pin may be used either as input I O SCL xD ID edge sensitive interrupt input or output O12 SCL This is the clock output when used with an external EEPROM VO12 xD ID This is the xD card detection pin only applicable to the USB2250 USB2250i General Purpose GPIO5 5 012 This pin may be used either as input edge I O SDA sensitive interrupt input or output Datasheet SDA This is the data pin when used with an external serial EEPROM General Purpose GPIO8 14 VO12 GPIO This pin may be used either as input I O CRD_PWRO edge sensitive interrupt input or output O200 CRD_PWR Card Power drive of 3 3V either 100mA o
5. 0 4 CF PIO Modes 0 6 Memory Stick Specification 1 43 Memory Stick Pro Format Specification 1 02 Memory Stick Pro HG Duo Format Specification 1 01 Memory Stick MS Duo HS MS MS Pro HG MS Pro xD Picture Card 1 2 Smart Media Specification 1 3 Secure Digital 2 0 HS SD HC SD TransFlash and reduced form factor media MultiMediaCard Specification 4 2 1 4 8 bit MMC SDIO and MMC Streaming Mode support m Extended configuration options xD player mode operation Socket switch polarities etc Media Activity LED 1 xD Picture Card not applicable to USB2251 SMSC USB2250 50i 51 51i DATASHEET Datasheet GPIO configuration and polarity Upto 11 GPIOs based on configuration for special function use LED indicators button inputs power control to memory devices etc The number of actual GPIO s depends on the implementation configuration used Four GPIO s with up to 200 mA drive An additional 16 GPIO s if CF is not used On Board 24MHz Crystal Driver Circuit Optional external 24MHz clock input 4 Independent Internal Card Power FET 200mA each Fold back short circuit current protected m 8051 8 bit microprocessor 60MHz single cycle execution 64KB ROM 14KB RAM m Internal Regulator for 1 8V core operation m Optimized pinout improves signal routing easing implementation and allowing for improved signal integrity OEM Selectable Features VID PID
6. 49 All VDD18 pins must be connected together Power on the circuit board 1 8V Core power If the internal regulator is enabled then this pin must have a 1 0ULF or SEN 20 ESR lt 0 10 capacitor to VSS 3 3V Power 8 VDD33 15 3 3V Power 8 Voltage Regulator Input Voltage Datasheet Regulator Input u Notes 1 Hot insertion capable card connectors are required for all flash media It is required for the SD connector to have a Write Protect switch This allows the chip to detect the MMC card 2 nMCE is normally asserted except when the 8051 is in standby mode 3 Refer to PWR MGMT CTL1 register for controlling pull up down resistors associated with the pins as well as the individual card control registers SMSC USB2250 50i 51 51i 19 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc 5 2 Buffer Type Descriptions Datasheet Table 5 2 USB2250 50i 51 51i Buffer Type Descriptions m a mm O is 77 message 000000 MO Io Input Output buffer with 12mA sink and 12mA source 1110000000 Input Output buffer with 12mA sink and 12mA source 1110000000 with 12mA sink and 12mA source VO200 Input Output buffer 12mA with FET disabled 100 200mA source only when the FET is enabled VO12PD Input Output buffer with 12mA sink and 12mA source with an internal weak pull down resistor ou A OIPU InputOutput buffer with 12mA sink and 12mA source with a pull up resistor
7. 7 0 while data transfer occurs on CF D 15 0 The bi directional data signal has an internal weak pull down resistor VO12 GPIO 31 24 These pins are GPIOs if the CF_INTF_EN bit of the CFC_ATA_MODE CTL is disabled and the EXTENDED_GPIO bit is set in UTIL CONFIG1 is enabled SMSC USB2250 50i 51 51i 11 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION CF Data 7 0 CF D 7 0 O12PD CF_D 7 0 The bi directional data signals CF D CF DO in True IDE mode data transfer In True IDE Mode all of the task file register operations occur on the CF D 7 0 while data transfer occurs on CF D 15 0 Datasheet GPIO GPIO 23 16 The bi directional data signal has an internal weak pull down resistor VO12 GPIO 23 16 These Pins are GPIOs if the CF INTF EN bit of the CFC ATA MODE CTL is disabled and the EXTENDED GPIO bit set in UTIL CONFIG1 is enabled IO Ready CF IORDY This pin is the active high input signal for IORDY This pin has an internal weak pull up resistor that can be controlled by CF INTF EN bit of CFC ATA_MODE CIL CF Card GPIO13 012 This is a GPIO designated as the Compact Detection1 CF nCD Flash card detection pin CF Hardware CF nRESET This pin is an active low hardware reset Reset signal to the CF device CF IO Read CF nlOR 72 O1
8. Erasable Programmable Read Only Memory FET Field Effect Transistor LUN Logical Unit Number MMC MultiMediaCard MS Memory Stick MSC Memory Stick Controller PLL Phase Locked Loop RoHS Restriction of Hazardous Substances Directive SD Secure Digital SDIO Secure Digital Input Output SDC Secure Digital Controllerl SIE Serial Interface Engine SM SmartMedia SMC SmartMedia Controller VTQFP Very Thin Quad Flat Package xD xD Picture Card Note In order to develop make use or sell readers and or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs technical information and licenses under patent and other intellectual property rights from or through various persons or entities including without limitation media standard companies forums and associations and other patent holders may be required These media standard companies forums and associations include without limitation the following Sony Corporation Memory Stick Memory Stick Pro SD3 LLC Secure Digital MultiMedia Card Association MultiMediaCard the SSFDC Forum SmartMedia the Compact Flash Association Compact Flash and Fuji Photo Film Co Ltd Olympus Optical Co Ltd and Toshiba Corporation xD Picture Card SMSC does not make such licenses or technical information available does not promise or represent that any such licenses or technical information will actually
9. I Input Output buffer with 12mA sink and 12mA source with a pull up resistor I with 12mA sink and 12mA source with a pull up resistor m aa Revision 1 1 05 29 08 20 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Datasheet Chapter 6 Pin Reset State Table Hardware Firmware v Initialization Vi Operational Voltage RESET n s Signal v Vpp33 ini a es TE RESET Time Vss Figure 6 1 Pin Reset States hardware enables function hardware disables function hardware disables output driver hardware enables pullup hardware enables pulldown hardware controls function but state is protocol dependent firmware controls function through registers hardware supplies power through pin applicable only to CARD_PWR pins hardware disables pad Figure 6 2 Legend for Pin Reset States Table SMSC USB2250 50i 51 51i 21 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller M lt lt c c lt c lt lt E Datasheet Post Reset State MS Mode PU IN OUT PU IN Post Reset State SD Mode OUT PUT fw fw fw fw fw fw fw fw fw fw fw fw fw L fw f f f GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Post Reset State xD Mode hw Figure 6 3 USB2250 5
10. is permanently enabled SM Command SM CLE 53 O12PD This pin is an active high Command Latch Strobe Enable signal for the SM device This pin has a weak pull down resistor that is permanently enabled 39 SM Data 7 0 SM_D 7 0 O12PD These pins are the bi directional data signals 40 SM_D7 SM_DO 41 42 The bi directional data signal has an internal 43 weak pull down resistor 44 45 46 SM Read Enable SM_nRE 55 O12PU This pin is an active low read strobe signal for the SM device When using the internal FET this pin has an internal weak pull up resistor that is tied to the output of the internal Power FET and is controlled by the SM_PU bit of the SMC CTL register If an external FET is used Internal FET is disabled then the internal pull up is not available external pull ups must be used SM Write Enable SM nWE 48 O12PU This pin is an active low write strobe signal for SM device When using the internal FET this pin has an internal weak pull up resistor that is tied to the output of the internal Power FET and is controlled by the SM PU bit of the SMC CTL register If an external FET is used Internal FET is disabled then the internal pull up is not available external pull ups must be used SM Write Protect SM nWPS 38 IPU A write protect seal is detected when this pin Switch is low This pin has an internal weak pull up resistor that is controlled by the SM INTF EN bit of the SMC MODE CTL2 register Datasheet S
11. 0i 51 51i Pin Reset States 128 Pin Reset States IL a GPIO GPIO C KAK e e a we pis ow ist KERE EREILIE KEN GE nla Kari SEI KAK LIL EIER KIE pm TN EEK CZ AE ER ZE KAERKIG KME Kass ERE E E CF nIOR CF DO GPIO16 CF D1 GPIO17 CF D2 GPIO18 CF D3 GPIO19 CF D4 GPIO20 CF D5 GPIO21 CF D6 GPIO22 CF D7 GPIO23 CF D8 GPIO24 CF D9 GPIO25 CF D10 GPIO26 CF D11 GPIO27 CF D12 GPIO28 CF D13 GPIO29 CF D14 GPIO30 CF D15 GPIO31 OUT PU IN OUT PU IN co O CO LO Revision 1 1 05 SMSC USB2250 50i 51 51i DX S EE 6 1 Post Reset State Post Reset State Post Reset State RESET STATE xD Mode SD Mode MS Mode OUT S IN OUT IN OUT PU IN OUT PU IN LL UOISIASH S IT ON EE EEN IE alas EE mp o EE CF DMACK TXD GPIO7 NI CF DMARQ RXD GPIO2 LAAHSVLVG ec GA B B gt B OI Co O ci NO Co R OI D o N GPIO13 CF_nCD SM Do SM D1 p I SM D3 SM D4 SM_D5 SM_D6 SM_D7 11G 1G 10G 0GCcaSNn ISNS jeoeusejeq 1 O11UuOO EIPSIN USEJJ 10IS MNIN 0 e ASN ISE4 ENN P Post Reset State Post Reset State Post Reset State RESET STATE xD Mode SD Mode MS Mode 2 gt OUT BD IN OUT T IN OUT PU IN OUT PU IN gt gt 92 MS D1 Ox m ON dy C7 UJ N Oi S 12 SD DO SD yes Gi Z o jeoeusejeq 1 O11UuOO EIPSIN USEJJ 10IS MNIN 0 e ASN ISE4 ENN P Post Reset State Post Reset State Post Res
12. 2 This pin is an active low read strobe signal for the CF device CF IO Write CF nlOW 73 O12 This pin is an active low write strobe signal Strobe for the CF device CF DMA request CF DMARO CF DMARO This pin is the DMA RXD GPIO2 from the device to the controller RXD The signal can be used as input to the RXD of UART in the device when the TXD RXD SEL bit in UTIL CONFIG1 register is cleared to 0 bal GPIO This pin may be used either as input ad sensitive interrupt input or output CF DMA CF DMACK CF nDMACK This pin is an active low dma acknowledge TXD GPIO acknowledge signal for the CF device TXD GPIO7 can be used as an output TXD of UART in the device when the GPIO2 TXD bit in UTL CONFIG register is set to 1 VO12 GPIO This pin may be used either as input edge sensitive interrupt input or output SMART MEDIA INTERFACE SM Write Protect SM_nWP 47 O12PD This pin is an active low write protect signal for the SM device This pin has a weak pull down resistor that is permanently enabled Revision 1 1 05 29 08 12 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION SM Address SM ALE 52 O12PD This pin is an active high Address Latch otrobe Enable signal for the SM device This pin has a weak pull down resistor that
13. BOL VTOFP TYPE DESCRIPTION Crystal XTAL1 124 ICLKx 24MHz Crystal or external clock input Input External CLKIN Clock Input XTAL This pin can be connected to one terminal of the crystal or it can be connected to an external 24 48MHz clock when a crystal is not used Note The MA 1 0 pins will be sampled while nRESET is asserted and the value will be latched upon nRESET negation This will determine the clock source and value Crystal Output XTAL2 123 OCLKx 24MHz Crystal This is the other terminal of the crystal or it is left open when an external clock source is used to drive XTAL1 CLKIN It may not be used to drive any external circuitry other than the crystal circuit 1 8V PLL Power VDD18PLL 125 This pin is the 1 8V Power for the PLL If the internal regulator is enabled then this pin must have a 1 0UF or greater 420 ESR lt 0 10 capacitor to VSS 3 3V Analog VDDA33 128 3 3V Analog Power Power Datasheet MEMORY IO INTERFACE Memory Data MD 7 0 Bus VO12 These signals are used to transfer data between the internal CPU and the external program memory Note These pins have internal weak pull up resistors that are controlled by the MD PU DIS bit of the PWR MGMT CTL1 register Memory Address MA16 Bus O12 These signals address memory locations within the external memory MA16 is a bit generated by the ROM Mapper Memory Address MA 15 2 O12 These signals address memory locations Bus within
14. ETER SYMBOL MIN TYP MAX UNITS COMMENTS VO12 VO12PU amp VO12PD Type Buffer Low Output Level V Lou 12mA High Output Level V lou 12mA Vpp33 3 3V Output Leakage HA VIN O to Vpp33 Note 7 5 Pull Down uA Pull Up IO U Note 7 6 I R Note 7 7 1 0200 Integrated Power FET for GPIO8 GPIO9 GPIO10 amp GPIO11 High Output Current Mode 200 mA Vdroprer 0 46V Low Output Current Mode 100 mA Vdroprer 0 23V Note 7 8 On Resistance 2 1 Q Impr 70mA Note 7 8 Output Voltage Rise Time 800 US Ci oAp 10uF Supply Current Active loc 110 140 mA VDD VDDP 1 8V Full Speed VDD33 VDDA 3 3V Supply Current Suspend csBY 350 750 HA VDD VDDP 1 8V Vpp33 VDDA 3 3V Note 7 5 Output leakage is measured with the current pins in high impedance Note 7 6 See The USB 2 0 Specification Chapter 7 for USB DC electrical characteristics Note 7 7 RBIAS is a 3 3V tolerant analog pin Note 7 8 Output current range is controlled by program software software disables FET during short circuit condition SMSC USB2250 50i 51 51i 31 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Note 7 9 The assignment of each Integrated Card Power FET to a designated Card Connector is controlled by both firmware and the specific board implementation Firmware will default to the settings listed in Table 10 1 USB2250 50i 51 51i GPIO Usage ROM Rev 0x00 on p
15. Flash Media Controller Datasheet Table of Contents Chapter AP CURL AA IA AA AA he eee eee ae ee 6 Chapter 2 Block Kn ee us DE AE BORD ANNA NANANA NAAN era 7 Chapter 3 Pin Table rrr NAA AD AA ES SES ec dil T2941 IE Package ti i ke i urs ESA Ba ashuan acoso dr c ke de Rb ern 8 Chapter 4 Pin Configuration 10 Chapter 5 Pin Descriptions sss ss s 9993 s s lt via eee ROSE BAR REK DR RR ER AR 11 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions 11 5 2 Buffer Type Descriptions rn 20 Chapter 6 Pin Reset State Table 21 ol 128 Pin Reset SALES a u u audias de ky ic edo Rt i c iw Me ac a dcc i cc e Wea AA 22 Chapter 7 DE T vod 9 dep a NAG e ocn dd v ov EIER REOR RN 28 7 1 Maximum Guaranteed Ratings 28 7 2 Recommended Operating Conditions 29 7 3 DC Electrical Characteristics ee rn 30 r MEE GE CE Tle nama ansehen naher TIT TT bee oes KABLLUED ABO E 32 Chapter 8 AC Specihcaiong sss s s s s s s een neben 33 o ee ee oe SERE N EO ER EE EE EO TE OE ne N OE OE a 33 Chapter Package Outline sss sss s EE ERROR EIS HOEKE DR n Va rares 34 Chapter TU GPIO Usage seas s s nennen a ER ORDE SO ES ED De id 35 SMSC USB2250 50i 51 51i 3 Revision 1 1 05 29 08 DATASHEET
16. Language ID m 28 character Manufacturer ID and Product string s 12 hex digit max Serial Number string Customizable Vendor specific data by optional use of external serial EEPROM m Bus or Self powered selection LED blink interval or duration Internal power FET configuration Software Features Optimized for low latency interrupt handling Reduced memory footprint Device Firmware Upgrade DFU support of external EEPROM or External Flash Assembly line support End user field upgrade support DFU Package consists of driver firmware sample DFU application and source code DFU driver API m Optional custom firmware with external ROM up to 128k Please see the USB2250 50i 51 51i Software Release Notes for additional Software Features pplications A Flash Media Card Reader Writer m Printers m m m Desktop and Mobile PCs Consumer A V Media Players Viewers Vista ReadyBoost Revision 1 1 05 29 08 Ultra Fast USB 2 0 Multi Slot Flash Media Controller SMSC Datasheet ORDER NUMBER USB2250 50i 51 51i NU XX for 128 pin VTQFP Lead Free RoHS Compliant Package XX in the order number indicates the internal ROM firmware revision level Please contact your SMSC sales representative for more information Table 0 1 USB2250 50i 51 51iComparison of Features CompactFlash amp Memory StickTM Part Number Secure Digital MultiMediaCar TM xD Picture Operational SmartMedia Card temperature
17. MSC USB2250 50i 51 51i 13 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION SM Busy or Data SM_nB R 56 IPU This pin is connected to the BSY RDY pin of Ready the SM device When using the internal FET this pin has an internal weak pull up resistor that is tied to the output of the internal Power FET and is controlled by the SM_PU bit of the SMC CTL register If an external FET is used Internal FET is disabled then the internal pull up is not available external pull ups must be used SM Chip Enable SM nCE O12PU This pin is the active low chip enable signal to the SM device When using the internal FET this pin has an internal weak pull up resistor that is tied to the output of the internal Power FET and is controlled by the SM PU bit of the SMC CTL register If an external FET is used Internal FET is disabled then the internal pull up is not available external pull ups must be used SM Card GPIO14 VO12 This is a GPIO designated as the Smart Detection GPIO SM_nCD Media card detection pin Datasheet MEMORY STICK INTERFACE MS Bus State MS_BS 91 O12 This pin is connected to the BS pin of the MS device It is used to control the Bus States 0 1 2 and 3 BSO BS1 BS2 and BS3 of the MS device MS Card GPIO12 IPU This is a GPIO designated as th
18. R MAP ROM 64KB Clock Generation and Control Program Memory VO Bus 8051 SFR PROCESSOR RAM ROM is not available in USB2259 Figure 2 1 USB2250 50i 51 51i Block Diagram SMSC USB2250 50i 51 51i 7 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Chapter 3 Pin Table Datasheet LA 1 128 Pin Package Table 3 1 USB2250 50i 51 51i 128 Pin VTQFP Package COMPACTFLASH INTERFACE 28 PINS CF DO GPIO16 CF D3 GPIO19 CF D4 GPIO20 CF_D7 GPIO23 CF_D8 GPIO24 CF_D11 GPIO27 CF_D12 GPIO28 CF D15 GPIO31 CF SA GPIO13 CF nCD CF DMARQ RXD GPIO2 SMARTMEDIA INTERFACE 17 PINS MEMORY STICK INTERFACE 11 PINS MS BS MS DO MS SDIO MS SCLK GPIO12 MS INS SD MMC INTERFACE 12 PINS SD CMD SD CLK SD DO SD D1 SD D2 SD D3 GPIO6 SD WP GPIO15 SD nCD SD D4 SD D5 SD D6 SD D7 USB INTERFACE 8 PINS VDDA33 XTAL2 XTAL1 CLKIN REG_EN Revision 1 1 05 29 08 8 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 3 1 USB2250 50i 51 51i 128 Pin VTQFP Package continued Datasheet MEMORY IO INTERFACE 28 PINS MAO CLK SELO MA1 CLK SEL1 MA2 MISC 10 PINS nRESET GPIO3 VBUS DET GPIO4 SCL xD_ ID GPIO5 SDA LED1 GPIO1 GPIO8 CARD PWRO GPIO9 CARD PWR1 GPIO10 CARD PWR2 GPIO11 CARD PWR3 TEST DIGITAL POWER 14 PINS TOTAL 128 SMSC USB2250 50i 51 51i 9 Revision 1 1 05 29 08 DATA
19. SHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Datasheet Chapter 4 Pin Configuration G Sgegr 8 88888 2 522228 ne 52828 gt 66666 509 S ze g S o SABBBEAB8828335 08885 te 5508858 nn LLULLLLULULLLOLLOODLOLLLLLILLILIN 22322320000000002000262600600000 MS_D6 nRESET GPIO12 MS INS 95 CF_D5 GPIO21 MS D3 L 99 CF D12 GPIO28 MS D7 CF D4 GPIO20 MS SCLK CF D11 GPIO27 VSS CF Da GPIO19 TEST GPIO13 CF nCD VDD33 GPIO14 SM nCD GPIO6 SD WP SM nB R MA7 SM nRE MA13 SM nCE MAG SM CLE MA8 SM ALE MA5 51 VSS MA9 50 VDD33 MA4 5 49 VDD18 MA11 48 SM nWE MA3 47 SM nWP nMRD SM DO MA2 SM D1 CF DMARO RXD GPIO2 SM D2 GPIO4 SCL xD ID Top View SM D3 CF DMACK TXD GPIO7 SM D4 LED1 GPIO1 SM D5 GPIO3 VBUS DET SM D6 VSS SM D7 XTAL2 SM nWPS XTAL1 CLKIN MDO VDD18PLL MD1 VSS MD2 RBIAS MD3 VDDA33 MD7 NG ET SFASZSSRELSLBNBIARASTUSER RRA 33339 ABB A AAE 82 gt Dell ll D Sneeze G u DADA gt aogqooo VJ m OT ao n V o d d gei a C O o va O E e r lt lt O O 5 gt o b O v Figure 4 1 USB2250 50i 51 51i 128 Pin VTQFP Diagram Revision 1 1 05 29 08 10 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Datasheet Chapter 5 Pin Descriptions This section provides a detailed description of each signal The signals are arranged in functional groups according to their associated interface T
20. SMSC SUCCESS BY DESIGN USB2250 501 51 511 Ultra Fast USB 2 0 Multi Slot Flash Media Controller PRODUCT FEATURES General Description The SMSC USB2250 50i 51 51i is a USB 2 0 compliant high speed Mass Storage Class Peripheral Controller intended for reading and writing to more than 24 popular flash media formats from the CompactFlash CF SmartMedia M SM xD Picture Card xD Memory StickTM MS Secure Digital SD and MultiMediaCard M MMC families The SMSC USB2250 50i 51 51i is a fully integrated single chip solution capable of ultra high performance operation Average sustained transfer rates exceeding 35MB s are possible if the media and host can support those rates General Features m 128 pin VTQFP 14x14mm lead free RoHS compliant package m Targeted for applications in which single or combo media Sockets are used Supports multiple simultaneous card insertions Flexible assignment of number of LUNs and how card types are associated with the LUNs Hardware controlled data flow architecture for all self mapped media m Pipelined hardware support for access to non self mapped media m Product name with i denotes the version that supports the industrial temperature range of 40 C to 85 C Hardware Features Single Chip Flash Media Controller with non multiplexed interface for independent card sockets Flash Media Specification Revision Compliance Compact Flash Specification 4 1 CF UDMA Modes
21. a Bus Responsible for transfer direction and types of data change depending on the Bus State SD MMC INTERFACE SD Data 7 0 SD D 7 0 SD Clock SD CLK 18 O12 This is an output clock signal to the SD MMC device The clock frequency is software configurable SD Command SD CMD O12PU This is a bi directional signal that connects to the CMD signal of the SD MMC device The bi directional signal should have an internal weak pull up resistor The pull up register can be controlled by SD MM INTF EN bit of SDC MODE CTL SD Write GPIO6 O12 This is a GPIO designated as the Secure Protected GPIO SD_WP Digital card mechanical write detect pin SD Card Detect GPIO15 VO12 This is a GPIO designated as the Secure GPIO SD_nCD Digital card detection pin Datasheet O12PU These are the bi directional data signals SD DO SD D7 The bi directional signals should have weak pull up resistors The register can be controlled by the SD MMC INTF EN bit of SDC MODE CTL USB INTERFACE USB Bus Data USB 7 O U These pins connect to the USB bus data USB 8 signals USB Transceiver RBIAS 127 A 12 0k 1 0 resistor is attached from Bias VSSA to this pin in order to set the transceiver s internal bias currents SMSC USB2250 50i 51 51i 15 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller FP smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYM
22. age 35 Datasheet Note 7 10 The 3 3V supply should be at least at 75 of its operating condition before the 1 8V supply is allowed to ramp up 7 4 Capacitance Ta 25 C fc 1MHz Vpp Vppp 1 8V Table 7 1 Pin Capacitance a mms PARAMETER SYMBOL on UNIT TEST CONDITION Clock Input Capacitance CxTAL All pins except USB pins and pins under test are tied to AC ground Revision 1 1 05 29 08 32 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P SMSE Datasheet Chapter 8 AC Specifications 8 1 Oscillator Clock Crystal Parallel Resonant Fundamental Mode 24 MHz 100ppm External Clock 50 Duty cycle 1096 24 48 MHz 100ppm Jitter 100ps rms XTAL1 Cs lt Cp CxraL C A Crystal CL C XTAL2 Cs Cs CxraL Figure 8 1 Typical Crystal Circuit Note Cp equals total board trace capacitance C Csi X Co Css CL C Csi Co Css Figure 8 2 Formula to Find Value of C4 and C SMSC USB2250 50i 51 51i 33 Revision 1 1 05 29 08 DATASHEET 133HSVIVO ve 80 6Z 50 UL UOISIASH ILG LG IOG OGEEASN OSINS Chapter 9 Package Outline TOP VIEW SEE DETAIL A C A i SIDE VIEW SEAT ING PLANE
23. be obtainable from or through the various persons or entities including the media standard companies forums and associations or with respect to the terms under which they may be made available and is not responsible for the accuracy or sufficiency of or otherwise with respect to any such technical information SMSC s obligations if any under the Terms of Sale Agreement or any other agreement with any customer or otherwise with respect to infringement including without limitation any obligations to defend or settle claims to reimburse for costs or to pay damages shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices or to any combinations involving any of them with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications Solid State Disk Patents By making any purchase of any of the devices made the subject of this document the customer represents warrants and agrees that it has obtained all necessary licenses under then existing Solid State Disk Patents for the manufacture use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of th
24. definitely without damage to the device as long as VDD33 and VDDA33 are less than 3 63V and A is less than 70 C Voltage on any 0 5 Vpp33 0 3 V signal pin Voltage on 0 5 4 0 V XTAL1 Voltage on 0 5 Vopig 0 3 V XTAL2 Note 7 1 Stresses above the specified parameters may cause permanent damage to the device This is a stress rating only and functional operation of the device at any condition above those indicated in the operation sections of this specification is not implied Note 7 2 When powering this device from laboratory or system power supplies it is important that the Absolute Maximum Ratings not be exceeded or device failure can result Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output When this possibility exists it is suggested that a clamp circuit be used Revision 1 1 05 29 08 28 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller Datasheet Voltage ir VDD38 3 3V 100 VSS t10 190 Time Figure 7 1 Supply Rise Time Model Note 7 3 When powering the device the maximum power supply ramp time should be set at a rate faster than 400us This speed is important to ensure that the device resets properly Measure rise time at 10 and 90 7 2 Recommended Operating Conditions PARAMETER SYMBOL MIN max UNITS COMMENTS Operating Tem
25. e Memory Insertion GPIO MS INS Stick card detection pin MS System CLK MS SCLK This pin is an output clock signal to the MS device The clock frequency is software configurable O12PD MS DIZ 0 These pins are the bi directional data signals for the MS device MS D2 and MS D3 have weak pull down resistors MS D1 has a pull down resistor if it is in parallel mode otherwise it is disabled In 4 MS System Data MS D 7 1 In Out or 8 bit parallel mode there is a weak pull down resistor on all MS D7 0 signals The resistors are controlled by MSC SYSTEM 0 MSC MODE CTL and MSC PRO HG registers Revision 1 1 05 29 08 14 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION MS System Data MS D0 94 O12PD MS DO This pin is one of the bi directional In Out MS SDIO data signals for the MS device In serial mode the most significant bit MSB of each byte is transmitted first by either MSC or the MS device on MS D0 MS DO MS D2 and MS D3 which have weak pull down resistors MS D1 has a pull down resistor if it is in parallel mode Otherwise it is disabled In 4 or 8 bit parallel mode all MS D7 0 signals have a weak pull down resistor The resistors are controlled by MSC SYSTEM 0 MSC MODE CTL and MSC PRO HG registers MS SDIO Serial Dat
26. et State RESET STATE xD Mode SD Mode MS Mode 2 gt OUT Fo IN OUT T IN OUT PU IN OUT PU IN gt gt x 32 GPIO15 SD_nCD GPIO yes GPIO a a de dy C7 un UJ N o jeoeusejeq 1 O11UuOO EIPSIN USEJJ 10IS MNIN 0 e ASN ISE4 ENN P Post Reset State Post Reset State Post Reset State RESET STATE xD Mode SD Mode MS Mode 2 gt OUT Fo IN OUT T IN OUT PU IN OUT PU IN 34 MD3 gt 31 MD4 MA U m 2 118 GPIO4 SCL xD ID GPIO GPIO O NG Oi o jeoeusejeq 1 O11UuOO EIPSIN USEJJ 10IS MNIN 0 e ASN ISE4 ENN P Post Reset State Post Reset State Post Reset State RESET STATE xD Mode SD Mode MS Mode o gt OUT Fo IN OUT T IN OUT PU IN OUT PU IN gt gt y 5 GPIO5 SDA GPIO GPIO QN m dy C7 UJ N o jeoeusejeq 1 O11UuOO EIPSIN USEJJ 10IS MNIN 0 e ASN ISE4 ENN Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Chapter 7 DC Parameters Datasheet 7 1 Maximum Guaranteed Ratings PARAMETER SYMBOL Cs UNITS COMMENTS Storage Ta 55 150 C Temperature Lead 325 C Soldering lt 10 seconds Temperature 3 3V supply VDD33 0 5 4 0 V voltage VDDA33 Voltage on 0 5 3 3V supply voltage 2 lt 6 V USB and USB pins Voltage on 0 5 Vpp33 0 3 V When internal power FET GPIO8 9 10 operation of these pins are amp 11 enabled these pins may be simultaneously shorted to ground or any voltage up to 3 63V in
27. he n symbol in the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When n is not present before the signal name the signal is asserted at the high voltage level The terms assertion and negation are used exclusively This is done to avoid confusion when working with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active independent of whether that level is represented by a high or low voltage The term negate or negation indicates that a signal is inactive 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions Table 5 1 USB2250 50i 51 51i 128 Pin VTOFP Pin Descriptions 128 PIN BUFFER SYMBOL VTQFP TYPE DESCRIPTION COMPACT FLASH INTERFACE CF Chip Select 0 CF nCS0 This pin is the active low chip select 0 signal for the task file registers of the CF ATA device in True IDE mode CF Register CF SA 2 0 VO12 These pins are the register select address Address ES bits for the CF ATA device 84 CF Interrupt CF IRQ 74 This is the active high interrupt request signal from the CF device This pin has an internal weak pull down resistor that can be controlled by CF INTF EN bit of CFC ATA MODE CTL EL a 15 8 CF_D 15 8 O12PD CF D 15 8 The bi directional data signals GPIO 31 24 CF_D15 CF D8 in True IDE mode data transfer In True IDE Mode all task file register operations occur on the CF D
28. is document which may be sold to the customer and any sale by SMSC of such units to the customer are valid exercises of the customer s rights and licenses under such Solid State Disk Patents that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture use or sale of such units and that SMSC shall have no obligation for any costs or expenses related to the customer s obtaining or having obtained rights or licenses under any Solid State Disk Patents SMSC MAKES NO WARRANTIES EXPRESS IMPLIED OR STATUTORY IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE No license is granted by SMSC expressly by implication by estoppel or otherwise under any patent trademark copyright mask work right trade secret or other intellectual property right To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect Forms of these Software License Agreements may be obtained by contacting SMSC Revision 1 1 05 29 08 6 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller er SMS Datasheet Chapter 2 Block Diagram SIE BUS i SD MMC CF GPIO 16 USB Host EPO TX EPO RX 1 8V Reg XDATA BRIDGE BUS ARBITER PLL GPIOs ipis RAM 10KB ADD
29. jeeusejeq J9JJOJJUOD EIPSIN USEJ4 10IS MNIN O c ASN ISE4 PAIN Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Datasheet Chapter 10 GPIO Usage Table 10 1 USB2250 50i 51 51i GPIO Usage ROM Rev 0x00 E MN ACTIVE LEVEL SYMBOL DESCRIPTION AND NOTE GPlOT IT LED LED indicator E u P DMARQ RXD CI MEN Flash DMA request Receive Port of Debugger GPIOS H veus DET USB Vbus detect E ELEM xD ID Serial EEPROM clock output xD card detect GPO 1 SDR WP SD Write Protect 11 Write Protect ARE Transmit Port of Debugger GPO t JORDPWRO o PWRO Card Power Control Power Control meme ee SMSC USB2250 50i 51 51i 35 Revision 1 1 05 29 08 DATASHEET
30. n any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval of an Officer of SMSC and further testing and or modification will be fully at the risk of the customer Copies of this document or other SMSC literature as well as the Terms of Sale Agreement may be obtained by visiting SMSC s website at http www smsc com SMSC is a registered trademark of Standard Microsystems Corporation SMSC Product names and company names are the trademarks of their respective holders SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND AGAINST INFRINGEMENT AND THE LIKE AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT INCIDENTAL INDIRECT SPECIAL PUNITIVE OR CONSEQUENTIAL DAMAGES OR FOR LOST DATA PROFITS SAVINGS OR REVENUES OF ANY KIND REGARDLESS OF THE FORM OF ACTION WHETHER BASED ON CONTRACT TORT NEGLIGENCE OF SMSC OR OTHERS STRICT LIABILITY BREACH OF WARRANTY OR OTHERWISE WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES SMSC USB2250 50i 51 51i 2 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot
31. perature Commercial Part Industrial Part 3 3V supply voltage V DD33 3 0 3 6 ku 7 4 VDDA33 3 3V supply rise time ph la ie See Figure 7 1 and Note 7 3 Voltage on 9 9 If any 3 3V supply voltage drops USB and USB pins below 3 0V then the MAX becomes 3 3V supply voltage 0 5 lt 5 5 pin Voltage on XTALT on Voltage on XTALT pf OB 3 an Vows Voltage on XTAL2 Ek Note 7 4 A 3 3V regulator with an output tolerance of 1 must be used if the output of the internal power FET s must support a 5 tolerance SMSC USB2250 50i 51 51i 29 Revision 1 1 05 29 08 DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc 7 3 DC Electrical Characteristics Gw msn mm ms mmm I IPU IPD Type Input Buffer Low Input Level VILI V TTL Levels High Input Level Vu 2 0 V Pull Down PD 72 uA Pull Up PU 58 uA IS Type Input Buffer Low Input Level V TTL Levels High Input Level V Hysteresis 420 mV ICLK Input Buffer Low Input Level 0 5 V High Input Level V Input Leakage 10 uA Vedi Input Leakage Datasheet All and IS buffers Low Input Leakage 10 uA High Input Leakage 10 uA 012 Type Buffer Low Output Level 0 4 V lo 12mA High Output Level V lon 12mA Vpp33 3 3V Output Leakage 10 HA VIN O to Vpp33 Note 7 5 Revision 1 1 05 29 08 30 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller mad gp SMSE PARAM
32. r 200mA General Purpose GPIO9 78 012 GPIO This pin may be used either as input I O CRD_PWRI edge sensitive interrupt input or output O200 CRD_PWR Card Power drive of 3 3V either 100mA or 200mA GPIO10 76 012 GPIO These pins may be used either as CRD PWR2 input edge sensitive interrupt input or output It is a requirement that this is the only FET used to power SM devices Failure to do this will violate SM voltage specification on SM device pins O200 CRD_PWR Card Power drive of 3 3V either 100mA or 200mA GPIO11 16 VO12 GPIO These pins may be used either as CRD_PWR3 input edge sensitive interrupt input or output O200 CRD_PWR Card Power drive of 3 3V either 100mA or 200mA RESET Input nRESET 64 This active low signal is used by the system to reset the chip The active low pulse should be at least 1us wide TEST Input TEST 103 This signal is used for testing the chip User should normally tie this pin low externally if the test function is not used Regulator REG EN IPU This signal is used to enable the internal Enable 1 8V regulator General Purpose VO General Purpose VO Revision 1 1 05 29 08 18 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION DIGITAL POWER and GROUND 1 8V Digital Core VDD18
33. the external memory Revision 1 1 05 29 08 16 SMSC USB2250 50i 51 51i DATASHEET Ultra Fast USB 2 0 Multi Slot Flash Media Controller P smsc Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions continued 128 PIN BUFFER NAME SYMBOL VTQFP TYPE DESCRIPTION Memory Address MA1 1 0 25 ie 0 These signals address memory Bus CLK 27 Mal within the external memorv SEL1 1 0 O12PD CLK SEL 1 0 During nRESET assertion these pins will select the operating frequency of the external clock and the corresponding weak pull down resistors are enabled When nRESET is negated the value on these pins will be internal latched and these pins will revert to MA 1 0 functionality the internal pull downs will be disabled CLK SEL 1 0 00 24MHz CLK SEL 1 0 2 01 RESERVED CLK SEL 1 0 10 RESERVED CLK SEL 1 0 11 48MHz Note If the latched value is 1 then the corresponding MA pin is tri stated when the chip is in the powerdown state If the latched value is 0 then the corresponding MA pin will function identically to the MA 15 3 pins at all times other than during nRESET assertion Memory Write nMWR Program Memory Write active low Strobe Memory Read nMRD Program Memory Read active low Strobe Memory Chip nMCE 26 O12 Program Memory Chip Enable active low Enable This signal is asserted when any external access is being done by the processor This signal is held to the logic

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