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SMSC LAN91C111 User's Manual

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1. 39 40 41 42 43 44 45 46 120 119 118 117 116 115 114 113 LAN91C111 FEAST 128 PIN QFP 47 49 50 112 111 110 109 108 107 106 105 104 103 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nADS ARDY GND nVLBUS AEN LCLK nSRDY VDD D24 GND D23 D22 D21 D20 VDD MNN NNN 228 og D6 nBE3 nBE2 nBE1 nBEO GND A15 A14 A13 A12 A11 A10 A9 A8 A7 A5 A4 A2 A1 VDD D8 D10 D11 GND D12 D13 D14 D15 GND D16 D17 D18 D19 Revision 1 91 08 18 08 Figure 2 2 Pin Configuration LAN91C111 FEAST 128 PIN QFP 10 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSC Chapter 3 Block Diagrams The diagram shown in Figure 3 1 Basic Functional Block Diagram describes the device basic functional blocks
2. OIGNLNI slaavr pansasay 0 0 0 0 L 0 0 0 0 0 0 0 0 0 0 038L OVAL HAIL zw ETA 018 anavo z103 HOSdA8 SIQLWX SIGINT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u E u E E VINSJ OL xad Ob XL xa4 dN L 0 0 0 0 L L L 0 0 0 0 0 0 0 VINSJ OL xad or xad vl dN 0 0 0 0 0 0 9 0 0 0 0 9 L L 9 L SLUVd vzino tano ozino erino 0 t 0 L 0 0 0 0 0 0 0 0 0 0 0 suno zuno suno suno vuno erno LINO orno 6INO sino zino sino vino sino D 0 0 L 0 0 0 0 0 0 0 L L L L 0 u HVY Wa HVY
3. Datasheet LOW ADDRESS 0 BYTE 0 0 0 0 0 0 0 0 HIGH ADDRESS 1 BYTE 0 0 0 0 0 0 0 0 LOW ADDRESS 2 BYTE 0 0 0 0 0 0 0 0 HIGH ADDRESS 3 BYTE 0 0 0 0 0 0 0 0 LOW ADDRESS 4 BYTE 0 0 0 0 0 0 0 0 HIGH ADDRESS 5 BYTE 0 0 0 0 0 0 0 0 8 14 Bank 1 General Purpose Register OFFSET NAME TYPE SYMBOL GENERAL PURPOSE A REGISTER READ WRITE GPR HIGH HIGH DATA BYTE BYTE 0 0 0 0 0 0 0 0 LOW LOW DATA BYTE BYTE 0 0 0 0 0 0 0 0 This register can be used as a way of storing and retrieving non volatile information in the EEPROM to be used by the software driver The storage is word oriented and the EEPROM word address to be read or written is specified using the six lowest bits of the Pointer Register This register can also be used to sequentially program the Individual Address area of the EEPROM that is normally protected from accidental Store operations This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111 Revision 1 91 08 18 08 56 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet 8 15 Bank 1 Control Register OFFSET NAME TYPE SYMBOL C CONTROL REGISTER READ WRITE CTR HIGH Reserved ROV Reserved Reserved AUTO Reserved Reserved Reserved BYTE BA
4. 1 4 4 4 121 Figure 14 15Jam Timing ice sehe ee Ret bee taedio de each c Re nee aces 122 Figure 14 16Link Pulse Timing 1 3 4 4 1 1 124 Figure 14 17FLP Link Pulse Timing 125 Figure 15 1 128 Pin TQFP Package Outline 14 14 1 0 126 Figure 15 2 128 Pin QFP Package Outline 3 9 MM 127 Revision 1 91 08 18 08 6 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet List of Tables Table 4 1 LAN91C111 Pin Requirements 128 Pin QFP and 1 0mm TQFP 14 Table 7 1 4B 5B Symbol 0 27 Table 7 2 Transmit Level 64 41 32 Table 8 1 Internal I O Space 4 46 Table 9 1 Serial Frame 71 Table 9 2 Serial Port Register 2 73 Table 10 1 Typical Flow Of Events For Placing Device In Low Power 84 Table 10 2 Flow Of Events For Restoring Device In Normal Power
5. 105 13 3 Twisted Pair Characteristics 108 13 4 Twisted Pair Characteristics Receive 109 Chapter 14 Timing 110 Revision 1 91 08 18 08 4 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet Chapter 15 Package Outlines o AER GERE A ERR 126 Chapter 16 Revision HIStory 66 5 sso 0 605 ey y EO ET Y PEFRETE REFER EE YT 128 SMSC LAN91C111 REV C 5 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet List of Figures Figure 2 1 Pin Configuration LAN91C111 FEAST 128 9 Figure 2 2 Pin Configuration LAN91C111 FEAST 128 10 Figure 3 1 Basic Functional Block Diagram 11 Figure 3 2 Block Diagram trek ed LER ETE ko RR RR Rr dul 12 Figure 3 3 LAN91C111 Physical Layer to Internal MAC Block 13 Figure 7 1 Serial Port Frame Timing 1 23 Figure 7 2 Frame Format amp MII Nibble 24 F
6. TPI Collision Observed by Physical Layer t t 34 gt 35 gt LEDn MII 10 Mbps M TOK 2 138 Collision Observed by Physical Layer Figure 14 13 Collision Timing Receive Revision 1 91 08 18 08 120 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC Datasheet MII 100 Mbps TPI TPO Collision Observed by Physical Layer t t 34 35 LEDn v E A TPO P 139 Collision Observed by Physical Layer t t i 34 pl 35 gt LEDn 2 Figure 14 14 Collision Timing Transmit SMSC LAN91C111 REV C 121 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet MII 100 Mbpb Tro 52 8 wos KOK Ke 141 Collision Observed by Physical Layer MII 10 Mbps m OXXXAXXXAXXXXAAXAXX AA AA AA AA AA AA AA TPO AM my Figure 14 15 Jam Timing Revision 1 91 08 18 08 122 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Table 14 4 Link Pulse Timing Characteristics LIMIT UNIT COND
7. 85 Table 12 1 VL Local Bus Signal 5 98 Table 12 2 High End ISA or Non Burst EISA Machines Signal 100 Table 12 3 EISA 32 Bit Slave Signal Connections 102 Table 14 1 Transmit Timing Characteristics 118 Table 14 2 Receive Timing 119 Table 14 3 Collision and Jam Timing 119 Table 14 4 Link Pulse Timing 1 123 Table 15 1 128 Pin TQFP Package 126 Table 15 2 128 Pin Package Parameters 127 Table 16 1 Customer Revision History 128 SMSC LAN91C111 REV C 7 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Chapter 1 General Description Datasheet The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications For this third generation of products flexibility and integration dominate the design requirements The LAN91C111 is a mixed
8. OOTIV V lt 1 agiva NOILYOOTIY Pr LNI ALdIW3 XL XL INI XLN 4e cw ANI Ke LON Odl4 fy povu MOVHMU 10 3 XL 8184 pe XL m 0 12 S 9 4 01 2 v S 9 4 DAS XL ps WNAXL Ag s a 1 1 e eeg a ASVINHO Ne 108 810 IL x 7 uo 1012e1eq e6p3 povu 10991 1109171 Yyy 1501 1 58 Figure 8 2 Interrupt Structure 65 Revision 1 91 08 18 08 DATASHEET SMSC LAN91C111 REV EP smsc 10 100 Ethernet Single Chip MAC PHY Datasheet 8 22 Bank 3 Multicast Table Registers OFFSET NAME TYPE SYMBOL 0 THROUG 7 MULTICAST TABLE READ WRITE MT LOW MULTICAST TABLE 0 BYTE 0 0 0 0 0 0 0 0 HIGH MULTICAST TABLE 1 BYTE 0 0 0 0 0 0 0 0 LOW MULTICAST TABLE 2 BYTE 0 0 0 0 0 0 0 0 HIGH MULTICAST TABLE 3 BYTE 0 0 0 0 0 0 0 0 LOW MULTICAST TABLE 4 BYTE 0 0 0 0 0 0 0 0 HIGH MULTICAST TAB
9. 4 100 Figure 12 2 LAN91C111 5 06 102 Figure 12 3 LAN91C111 on 06 104 Figure 14 1 Asynchronous Cycle 0 1 110 Figure 14 2 Asynchronous Cycle Using 111 Figure 14 3 Asynchronous Cycle 0 112 Figure 14 4 Asynchronous 1 112 Figure 14 5 Burst Write Cycles 0 1 113 Figure 14 6 Burst Read Cycles 06 1 114 Figure 14 7 Address Latching for Al 115 Figure 14 8 Synchronous Write Cycle 06 0 115 Figure 14 9 Synchronous Read Cycle 1 06 0 116 Figure 14 OMIT Timing siento ee EUR Eier 117 Figure 14 11 Transmit Timing esent meh ei REDE DR LIE Ei tdg 118 Figure 14 12Receive Timing End of Packet 10 119 Figure 14 13Collision Timing Receive 120 Figure 14 14Collision Timing
10. 53uxa ave NIT dvo FS ETEN MOV HANS dvo HL dvo 3I dvo HXL 3XL dvo vL 0 0 0 0 0 0 0 0 0 0 010 0 9 L 0 0 OSMA osm pansesay 181109 su Sid iW Na daads isu ox x ex x gx 9 Lx 6 orx EL X 119 p m s y indino snes 2 uoneinByuoS I uopeanyuog Aiqedeg AHd Ht dl AHd smeis 1014U09 02 6 8L 74 9r Table 9 2 MII Serial Port Register MAP 73 Revision 1 91 08 18 08 DATASHEET SMSC LAN91C111 REV C EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet 9 1 Register 0 Control Register RST LPBK SPEED ANEG EN PDN MII DIS ANEG RST DPLX RW SC RW RW RW RW RW RW SC RW 0 0 1 1 0 1 0 0 COLST Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 RST Reset A 1 written to this bit will initiate reset of the PHY The bit is self clearing and the PHY will return a 1 on reads to this bit until the reset is completed Write transactio
11. Ethernet Single Chip PHY 9 6 Register 16 Configuration 1 Structure and Bit Definition LNKDIS XMTDIS XMTPDN Reserved Reserved BYPSCR UNSCDS EQLZR RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 CABLE RLVLO TLVL3 TLVL2 TLVL1 TLVLO TRF1 TRFO RW RW RW RW RW RW RW RW 0 0 1 0 0 0 1 0 LNKDIS Link Disable 1 Receive Link Detect Function Disabled Force Link Pass 0 Normal XMTDIS TP Transmit 1 TP Transmitter Disabled 0 Normal XMTPDN TP Transmit 1 TP Transmitter Powered Down Powerdown 0 Normal RESERVED RESERVED Reserved Must be 0 for Proper Operation BYPSCR Bypass 1 Bypass Scrambler Descram bler Scrambler Descr 0 No Bypass ambler Select UNSCDS Unscrambled Idle 1 Disable AutoNegotiation with devices that transmit unscrambled Reception Disable idle on powerup and various instances 0 Enables AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances EQLZR Receive Equalizer 1 Receive Revision 1 91 08 18 08 78 DATASHEET Equalizer Disabled Set To 0 Length SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Select 0 Receive Equalizer On For 100MB Mode Only CABLE Cable Type Select 1 STP 150 Ohm 0 UTP 100 Ohm RLVLO Receiv
12. 19 6 1 Buffer Types nose unten dike vilt her Elle fer Sac Seb got hiner ee ten bit ermer A 19 Chapter 7 Functional Description 20 A Clock Generator Block eed re ey C do ionene o RC I an 20 17 2 CSMAICD BIlOCk 45 aser rase dicic dox HETT AT bed 20 7 2 1 2 etie tr sak nee vid er sd rad ea qu 20 7 2 2 Arbiter Block i ise KORR E enit Ro x Da lend RR es 20 7 3 MMU Bloke iR deer REI seede s a Rupe 20 74 oio e borsa ne a a kle ded aa 21 7 5 Interface usa erede ri e m eiie de beret a 21 7 5 1 Management Data Software Implementation 21 7 5 2 Management Data 0 14 0 22 7 5 3 MI Serial Port Frame Structure 22 7 5 4 MII Packet Data Communication with External 24 7 6 Serial EEPROM Interface 4 25 7 7 Internal Physical Layer 2225 25 22 lt lt rem E 25 7 7 1 MII Bisable iue oa cc i Ro Roa loe RALIS Rh
13. EMPTY TX DONE PACKET NUMBER CPU ADDRESS CSMA ADDRESS Y tf CSMA CD yv LOGICAL PACKET ADDRESS MMU M S BIT ONLY PACK OUT PHYSICAL ADDRESS y RAM Figure 10 6 Interrupt Generation for Transmit Receive MMU Revision 1 91 08 18 08 94 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSC Chapter 11 Board Setup Information The following parameters are obtained from the EEPROM as board setup information ETHERNET INDIVIDUAL ADDRESS I O BASE ADDRESS INTERFACE All the above mentioned values are read from the EEPROM upon hardware reset Except for the INDIVIDUAL ADDRESS the value of the IOS switches determines the offset within the EEPROM for these parameters in such a way that many identical boards can be plugged into the same system by just changing the IOS jumpers In order to support a software utility based installation even if the EEPROM was never programmed the EEPROM can be written using the LAN91C111 One of the IOS combination is associated with a fixed default value for the key parameters I O BASE that can always be used regardless of the EEPROM based value being programmed This value will be used if all IOS pins are left open or pulled high The EEPROM is arranged as a 64 x 16 array The specific target device is the 9346 1024 bit Serial EEPROM All EEPROM accesses done in words All EEPROM addresses in t
14. Revision 1 91 08 18 08 86 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet S W DRIVER MAC SIDE 7 The generates TXEMPTY interrupt upon completion of sequence of enqueued packets If a TX failure occurs on any packets TX INT is generated and TXENA is cleared transmission sequence stops The packet number of the failure packet is presented at the TX FIFO PORTS Register 8 SERVICE INTERRUPT Read Interrupt Status Register exit the interrupt service routine Option 1 Release the packet Option 2 Check the transmit status in the EPH STATUS Register write the packet number of the current packet to the Packet Number Register re enable TXENA then go to step 4 to start the TX sequence again 10 4 Typical Flow of Event For Receive S W DRIVER MAC SIDE 1 ENABLE RECEPTION By setting the RXEN bit 2 A packet is received with matching address Memory is requested from MMU packet number is assigned to it Additional memory is requested if more pages are needed 3 The internal DMA logic generates sequential addresses and writes the receive words into memory The MMU does the sequential to physical address translation If overrun packet is dropped and memory is released 4 When the end of packet is detected the status word is placed at the beginning of the receive packet in memory Byte count is placed at
15. amp Copy Data amp Source Address ra m Enqueue Packet lt EPH INTR io gt 1 Yes Ed Set Ready for Packet Flag CallEPHINTR nn L Return Buffers to Upper Layer EM ETT Disable Allocation Interrupt lt lt MDINT Mask Yes 2 di Restore Address Pointer amp Bank Select Registers Call MDINT __ Unmask SMC91C111 Interrupts Exit ISR Figure 10 1 Interrupt Service Routine Revision 1 91 08 18 08 88 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY e m S Datasheet RXINTR Y Write Ad Ptr Reg amp Read Word 0 from RAM y Yes Destination Mulicast Read Words 2 3 4 from RAM for Address Filtering Y Address Filtering Pass Yes No Status Word Yes OK 7 Do Receive Lookahead 7 Get Specs from Upper Layer Y La No Vers o Copy Copy Data Per Upper Layer Specs Y Issue Remove and Release Command y __ ReturntolSR 1 Figure 10 2 RX INTR 89 Revision 1 91 08 18 08 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet TX Interrupt With AUTO RELEASE FALSE Save the Packet Number Register Saved PNR Read Byte Bank 2 Offset 2 Read the EPH Status Registe
16. 43 8 2 Receive Frame Status 44 83 VO 5 i c aay pes Le KSS de RUS Xe AERE ERR We b p eda E ded 45 SMSC LAN91C111 REV C 3 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP Datasheet 8 4 Bank Select Register 46 8 5 Bank 0 Transmit Control Register 47 8 6 Bank 0 EPH Status Register 48 8 7 Bank 0 Receive Control 49 8 8 Bank 0 Counter Register 50 8 9 Bank 0 Memory Information 51 8 10 Bank 0 Receive Phy Control Register 51 8 11 Bank 1 Configuration 2 2 54 8 12 Bank 1 Base Address 55 8 13 Bank 1 Individual Address 55 8 14 Bank 1 General Purpose Register 56 8 15 Bank 1 Control 1 57 8 16 Bank
17. 76 9 5 Register 5 Auto Negotiation Remote End Capability Register 77 9 6 Register 16 Configuration 1 Structure and Bit Definition 78 9 7 Register 17 Configuration 2 Structure and Bit 79 9 8 Register 18 Status Output Structure and Bit 80 9 9 Register 19 Mask Structure and Bit 81 9 10 Register 20 Reserved Structure and Bit 82 Chapter 10 Software Driver and Hardware Sequence 84 10 1 Software Driver and Hardware Sequence Flow for Power 84 10 2 Typical Flow of Events for Transmit Auto Release 0 85 10 3 Typical Flow of Events for Transmit Auto Release 1 86 10 4 Typical Flow of Event For 87 Chapter 11 Board Setup Information 95 Chapter 12 Application 98 Chapter 13 Operational Description 105 13 1 Maximum Guaranteed 05 105 13 2 DC Electrical Characteristics
18. By default the last byte in the receive frame format is followed by the CRC and the Control byte follows the CRC bit15 bito RAM OFFSET 2nd Byte 1st Byte een TT TTT TTT 0 STATUS WORD 2 RESERVED BYTE COUNT always even 4 DATA AREA CRC 4 BYTES 2046 Max CONTROL BYTE LAST DATA BYTE if odd Last Byte Figure 8 1 Data Frame Format TRANSMIT PACKET RECEIVE PACKET STATUS WORD Written by CSMA upon transmit completion see Status Register Written by CSMA upon receive completion see RX Frame Status Word BYTE COUNT Written by CPU Written by CSMA DATA AREA Written modified by CPU Written by CSMA CONTROL BYTE Written by CPU to control odd even data bytes Written by CSMA also has odd even bit BYTE COUNT Divided by two it defines the total number of words including the STATUS WORD the BYTE COUNT WORD the DATA AREA the CRC and the CONTROL BYTE The CRC is not included if the STRIP_CRC bit is set The maximum number of bytes in a RAM page is 2048 bytes SMSC LAN91C111 REV 43 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet The receive byte count always appears as even the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant The transmit byte count least significant bit will be assumed 0
19. However status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is initiated NO WAIT When set does not request additional wait states An exception to this are accesses to the Data Register if not ready for a transfer When clear negates ARDY for two to three clocks on any cycle to the LAN91C111 GPCNTRL This bit is a general purpose output port Its inverse value drives pin nCNTRL and it is typically connected to a SELECT pin of the external PHY device such as a power enable It can be used to select the signaling mode for the external PHY or as a general purpose non volatile configuration pin Defaults low EXT PHY External PHY Enabled This bit when set 1 a Enables the external MII b The Internal PHY is disabled and is disconnected Tri stated from the internal MII along with any sideband signals such as MDINT going to the MAC Core When this bit is cleared 0 Default a The internal PHY is enabled b The external MII pins including the MII Management interface pins are tri stated Reserved Reserved bits SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet 8 12 Bank 1 Base Address Register OFFSET NAME TYPE SYMBOL BASE ADDRESS REGISTER READ WRITE This register holds the address decode option chosen for the LAN91C111 It is part of the EEPROM saved setup and is not us
20. The inputs and outputs of the host Interface are 5V tolerant and will directly interface to other 5V devices Revision 1 91 08 18 08 8 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Chapter 2 Pin Configurations Pin Configuration ioo 8 N kkEEXCErccortorcrtrocscoanaBnoa8sBab2t SRSRRSESREPPLTPPEPPLTPESSSSSSSSESS5 VDD 1 96 nBE2 nCSOUT 2 95 O 1 1050 3 94 nBEO 1051 4 93 H GND 1052 0 5 92 15 ENEEP 6 91 2 A14 EEDO 7 90 A13 EEDI 8 89 1 A12 9 88 At EECS 10 87 0 A10 AVDD O 11 86 A9 RBIAS I 12 85 D AGND 13 84 7 T
21. The SMSC LAN91C111 is single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10 100 Ethernet connectivity solutions The optional Serial EEPROM is used to store information relating to default IO offset parameters as well as which of the Interrupt line are used by the host Host System I Processot ISA Embedded LAN91C111 Ethernet Internal IEEE 802 3 MII Media P HY X MAC Independent Interface Co re II TX RX Buffer 8K Minimal LAN91C111 Configuration Figure 3 1 Basic Functional Block Diagram SMSC LAN91C111 REV 11 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet EEPROM INTERFACE Control Contra Control Control Control Arbiter lt Contro 8 32 bit Bus Ethernet Interface Protocol 10 100 Address Unit Control MMU PHY me bo DMA Handler Pointer EPH WR TX Data TXD 0 3 A FIFO A 3K byte 32 bit Data Dynamically Data Allocated RD SHAM 32 bit Daa RX Data RXD 0 3 FIFO NJ PC Figure 3 2 Block Diagram The diagram shown in Figure 3 2 describes the supported Host interfaces which include ISA or Generic Embed
22. and strips off the ESD delimiter T R symbols and replaces it with two 4B Data 0 nibbles a k a per IEEE 802 3 specifications and shown in Figure 7 3 Table 7 1 4B 5B Symbol Mapping SYMBOL NAME DESCRIPTION 5B CODE 4B CODE 0 Data 0 11110 0000 1 Data 1 01001 0001 2 Data 2 10100 0010 SMSC LAN91C111 REV C 27 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Table 7 1 4B 5B Symbol Mapping continued SYMBOL NAME DESCRIPTION 5B CODE 4B CODE 3 Data 3 10101 0011 4 Data 4 01010 0100 5 Data 5 01011 0101 6 Data 6 01110 0110 7 Data 7 01111 0111 8 Data 8 10010 1000 9 Data 9 10011 1001 A Data 10110 1010 B Data B 10111 1011 C Data 11010 1100 D Data D 11011 1101 E Data E 11100 1110 F Data F 11101 1111 Idle 11111 0000 J SSD 1 11000 0101 K SSD 2 10001 0101 T ESD 1 01101 0000 R ESD 2 00111 0000 H Halt 00100 Undefined a Invalid codes All others 0000 These 5B codes are not used For decoder these 5B codes are decoded to 4B 0000 For encoder 4B 0000 is encoded to 5B 11110 as shown in symbol Data 0 The 4B5B decoder detects SSD ESD and codeword errors in the incoming data stream as specified in IEEE 802 3 These errors are indicated by asserting RX ER output while the errors are being transmitted across RXD 3 0
23. 10 100 Ethernet Single Chip MAC PHY Datasheet DAN JO 53909 9NISIH NO V LVQ LNO 930010 AHd 40 S393 ONISIH NO V VQ NI 9019 AHd sua mE SLIM T o silviva fo 0 40 10 90 0 16 1 1 1 Tr f og sa 9a 1 eia SIG 0 7 0H ecd vH Od Id td L L DA 0 0 QT BT BT BR RE wf ef ef Ve e Ve VE EE Need ef I eI vf I If ef ef S NI VI V ST NI VE SI ST V om 31949 avau OON 40 3003 ONISIK NO VIVA NI S9079 SLIM 1 lo stlviva low 0 rlavoau lo rlavAHd 0 40 0 16 nn I ea 5 9d ea eua vid sta 0 L 0H Lu eu H vH Od Id 2 td L 0 L 0 Ji V H NA V M 0 EVENES VTS EE 370A0 Revision 1 91 08 18 08 iagram D iming 23 DATASHEET Figure 7 1 MI Serial Port Frame SMSC LAN91C111 REV C EP 10 100 Ethernet Single Chip MAC PHY Datasheet 7 5 4 MII Packet Data Communication with External PHY The is a nibble wide packet data interface defined in IEEE 802 3 The LAN91C111 meets all the MII requirements outlined in IEEE 802 3 and shown in Figure 7 2 P TX EN 1 BENET 3 START TX EN 0 IDLE
24. 16 collisions the MULTIPLE COLLISION COUNT field is incremented by one If a packet experiences deferral the NUMBER OF DEFERRED TX field is incremented by one even if the packet experienced multiple deferrals during its collision retries The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts are generated on successful transmissions Reading the register in the transmit service routine will be enough to maintain statistics SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet 8 9 Bank 0 Memory Information Register OFFSET NAME TYPE SYMBOL MEMORY INFORMATION 8 REGISTER READ ONLY MIR HIGH FREE MEMORY AVAILABLE IN BYTES 2K M BYTE 0 0 0 0 0 1 0 0 LOW MEMORY SIZE IN BYTES 2K M BYTE 0 0 0 0 0 1 0 0 FREE MEMORY AVAILABLE This register can be read at any time to determine the amount of free memory The register defaults to the MEMORY SIZE upon POR Power On Reset or upon the RESET MMU command MEMORY SIZE This register can be read to determine the total memory size All memory related information is represented in 2K M byte units where the multiplier M is 1 for LAN91C111 8 10 Bank 0 Receive Phy Control Register OFFSET NAME TYPE SYMBOL RECEIVE PHY CONTROL A REGISTER READ WRITE RPCR HIGH Reserved Reserved SPEED DPLX ANEG Reserved Reserved Reserved
25. 18 08 52 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet DUPLEX MODE CONTROL WHAT DO YOU AUTO NEGOTIATION SPEED AND DUPLEX MODE CONTROL FOR THE WANT TO DO CONTROL BITS FOR THE PHY MAC 10 Full Duplex 0 0 0 1 X X 1 0 1 0 1 X X 1 1 0 X X 0 1 1 10 Half Duplex 0 0 0 0 X X 0 0 1 0 0 X X 0 1 0 X X 0 0 0 LS2A LS1A LSOA LED select Signal Enable These bits define what LED control signals are routed to the LEDA output pin on the LAN91C111 Ethernet Controller The default is 10 100 Link detected LS2A LS1A LSOA LED SELECT SIGNAL LEDA 0 0 0 nPLED3 nPLEDO Logical OR of 100Mbps Link detected 10Mbps Link detected default 0 0 1 Reserved 0 1 0 nPLEDO 10Mbps Link detected 0 1 1 nPLED1 Full Duplex Mode enabled 1 0 0 nPLED2 Transmit or Receive packet occurred 1 0 1 nPLEDS 100Mbps Link detected 1 1 0 nPLED4 Receive packet occurred 1 1 1 nPLED5 Transmit packet occurred LS2B LS1B LSOB LED select Signal Enable These bits define what LED control signals are routed to the LEDB output pin on the LAN91C111 Ethernet Controller The default is 10 100 Link detected LS2B LS1B LSOB LED SELECT SIGNAL LEDB 0 0 0 nPLED3 nPLEDO Logical OR of 100Mbps Link detected 10Mbps Link detected default 0 0 1 Reserved 0 1 0 nPLEDO 10Mbps Link dete
26. 2 MMU Command 58 8 17 Bank 2 Packet Number Register 59 8 18 Bank 2 FIFO Ports 1 60 8 19 Bank 2 Pointer 2 61 8 20 Bank 2 Data Register suse cu da Bee ed ed be RR ORO d ce ee 62 8 21 Bank 2 Interrupt Status 62 8 22 Bank Multicast Table 66 8 23 Bank 3 Management 67 8 24 Bank Revision 67 8 25 Bank3 RCV Register 0 0 0 hrs 68 8 26 Bank 7 External Registers 0 68 Chapter 9 PHY MII Registers 70 9 1 Register 0 Control 41 74 9 2 Register 1 Status 2 75 9 3 Register 2 amp 3 PHY Identifier Register 76 9 4 Register 4 Auto Negotiation Advertisement Register
27. BUS LAN91C111 SIGNAL SIGNAL NOTES A2 A15 A2 A15 Address bus used for I O space and register decoding latched by nADS rising edge and transparent on nADS low time M nIO AEN Qualifies valid I O decoding enabled access when low This signal is latched by nADS rising edge and transparent on nADS low time W nR W nR Direction of access Sampled by the LAN91C111 on first rising clock that has nCYCLE active High on writes low on reads nRDYRTN nRDYRTN Ready return Direct connection to VL bus nLRDY nSRDY and some nSRDY has the appropriate functionality and timing to create the VL logic nLRDY except that nLRDY behaves like an open drain output most of the time LCLK LCLK Local Bus Clock Rising edges used for synchronous bus interface transactions nRESET RESET Connected via inverter to the LAN91C111 nBEO nBE1 nBEO nBE1 nBE2 Byte enables Latched transparently by nADS rising edge nBE2 nBE3 nBES3 nADS nADS nCYCLE Address Strobe is connected directly to the VL bus nCYCLE is created typically by using nADS delayed by one LCLK IRQn INTRO Typically uses the interrupt lines on the ISA edge connector of VL bus Revision 1 91 08 18 08 98 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE DATASHEET Datasheet Table 12 1 VL Local Bus Signal Connections continued VL BUS LAN91C111 SIGNAL SIGNAL NOTES D
28. BYTE 0 0 0 0 0 0 0 0 LOW LS2A LS1A 150 LS2B LS1B 150 Reserved Reserved BYTE SPEED Speed select Input This bit is valid and selects 10 100 PHY operation only when the ANEG Bit 0 this bit overrides the SPEED bit in the PHY Register 0 Control Register and determine the speed mode When this bit is set 1 the Internal PHY will operate at 100Mbps When this bit is cleared 0 the Internal PHY will operate at 10Mbps When the ANEG bit 1 this bit is ignored and 10 100 operation is determined by the outcome of the Auto negotiation or this bit is overridden by the SPEED bit in the PHY Register 0 Control Register when the ANEG EN bit in the PHY Register 0 Control Register is clear DPLX Duplex Select This bit selects Full Half Duplex operation This bit is valid and selects duplex operation only when the ANEG Bit 0 this bit overrides the DPLX bit in the PHY Register 0 Control SMSC LAN91C111 REV C 51 Revision 1 91 08 18 08 DATASHEET EP smsc Register and determine the duplex mode When this bit is set 1 the Internal PHY will operate at full duplex mode When this bit is cleared 0 the Internal PHY will operate at half Duplex mode When the ANEG bit 1 this bit is ignored and duplex mode is determined by the outcome of the Auto negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 Control Register when the ANEG EN bit in the PHY Register 0 Cont
29. CONTROL BYTE should be ignored 8 2 Receive Frame Status This word is written at the beginning of each receive frame in memory It is not available as a register HIGH ALGN BROD BAD ODD TOOLNG TOO BYTE ERR CAST CRC FRM SHORT LOW HASH VALUE MULT BYTE CAST Reserved 5 4 3 2 1 ALGNERR Frame had alignment error Revision 1 91 08 18 08 44 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE BROADCAST Receive frame was broadcast When broadcast packet is received the MULTCAST bit may be also set on the status word in addition to the BRODCAST bit The software implement may just ignore the MULTCAST bit if for BRODCAST packet BADCRC Frame had CRC error or RX ER was asserted during reception ODDFRM This bit when set indicates that the received frame had an odd number of bytes TOOLNG Frame length was longer than 802 3 maximum size 1518 bytes on the cable TOOSHORT Frame length was shorter than 802 3 minimum size 64 bytes on the cable HASH VALUE Provides the hash value used to index the Multicast Registers Can be used by receive routines to speed up the group address search The hash value consists of the six most significant bits of the CRC calculated on the Destination Address and maps into the 64 bit multicast table Bits 5 4 3 of the hash value select a byte of the multicast table while bits 2 1 0 determine the bit within the byte selected Examples of the a
30. LAN91C111 after both bits are low A worst case RELOAD operation initiated by RESET or by software takes less than 750 us 57 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet 8 16 Bank 2 MMU Command Register OFFSET NAME TYPE SYMBOL WRITE ONLY MMU COMMAND BUSY BIT 0 REGISTER READABLE MMUCR This register is used by the CPU to control the memory allocation de allocation TX FIFO and RX FIFO control The three command bits determine the command issued as described below HIGH BYTE LOW COMMAND Reserved Reserved Reserved Reserved BUSY BYTE Operation Code 0 COMMAND SET OPERATION DECIMAL CODE VALUE COMMAND 000 0 NO OPERATION 001 1 ALLOCATE MEMORY FOR TX 010 2 RESET MMU TO INITIAL STATE Frees all memory allocations clears relevant interrupts resets packet FIFO pointers 011 3 REMOVE FRAME FROM TOP OF RX FIFO be issued after CPU has completed processing of present receive frame This command removes the receive packet number from the RX FIFO and brings the next receive frame if any to the RX area output of RX FIFO 100 4 REMOVE AND RELEASE OF RX FIFO Like 3 but also releases all memory used by the packet presently at the RX FIFO output The MMU busy time after issuing REMOVE and RELEASE command depends on the time when the busy bit is
31. Maximum Fixed commercial temp range to state O C to 07 17 08 Guaranteed Ratings on 70 C for LAN91C111 page 105 Rev 1 9 Cover Added bullet Commercial Temperature Range 07 17 08 from 09 to 70 LAN91C111 Rev 1 9 Section 8 24 Bank 3 Changed REV default from 0001 to 0010 07 17 08 Revision Register on page 67 Rev 1 9 Table 14 3 Asynchronous Changed T1A time in table under figure from 10nS 07 17 08 Cycle nADS 0 on min to 2nS min page 112 Rev 1 9 Section 10 4 Typical Flow In step 4 changed last sentence from If CRC is 07 17 08 of Event For Receive on incorrect the packet memory is released and no page 87 interrupt will occur to RCV BAD bit of the Bank 1 Control Register controls whether or not to generate interrupts when bad CRC packets are received Rev 1 9 Section 7 7 14 Receive Added note at end of 10 Mbps subsection stating 07 17 08 Polarity Correction on The first 3 received packets must be discarded page 40 after the correction of a reverse polarity condition Revision 1 91 08 18 08 128 SMSC LAN91C111 REV C DATASHEET
32. NO TRANSITIONS PREAMBLE 1 0 10 1 62 BITS LONG SFD 1 1 BEFORE AFTER _ MANCHESTER DA SA LN LLC DATA FCS DATA ENCODING SOI 1 1 WITH NO MID BIT TRANSITION 2 Figure 7 3 10 Frame Format On the transmit side for 100Mbps TX operation data is received on the controller and then sent to the 4B5B encoder for formatting The encoded data is then sent to the scrambler The scrambled and encoded data is then sent to the TP transmitter The TP transmitter converts the encoded and scrambled data into MLT 3 ternary format reshapes the output and drives the twisted pair cable On the receive side for 100Mbps TX operation the twisted pair receiver receives incoming encoded and scrambled MLT 3 data from the twisted pair cable remove any high frequency noise equalizes the input signal to compensate for the effects of the cable qualifies the data with squelch algorithm and converts the data from MLT 3 coded twisted pair levels to internal digital levels The output of the twisted pair receiver then goes to clock and data recovery block which recovers clock from the incoming data uses the clock to latch in valid data into the device and converts the data back to NRZ format The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler respectively and outputted to the Ethernet controller Revision 1 91 08 18 08 26 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Singl
33. Revision 1 91 08 18 08 82 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 1 0 1 0 0 0 0 0 Reserved Reserved for Factory Use SMSC LAN91C111 REV C 83 DATASHEET Revision 1 91 08 18 08 EP SMSC Chapter 10 Software Driver and Hardware Sequence 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Flow 10 1 Software Driver and Hardware Sequence Flow for Power Management This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller to perform power management The Ethernet controller has the ability to reduce its power consumption when the Device is not required to receive or transmit Ethernet Packets Power Management is obtained by disabling the EPH clocks including the Clocks derived from the Internal PHY block to reduce internal switching this reducing current consumption The Host interface however will still be accessible As discussed in Table 10 1 and Table 10 2 the tables describe the interaction between the EPH and Host driver allowing the Device to transition from low power state to normal functionality and vice versa Table 10 1 Typical Flow Of Events For Placing Device In Low Power Mode S W DRIVER CONTROLLER FUNCTION
34. and the rest of the LAN91C111 operates normally Twisted Pair Receiver Receiver 100 Mbps The TX receiver detects input signals from the twisted pair input and converts it to a digital data bit stream ready for dock and data recovery The receiver can reliably detect data from a 100BASE TX transmitter that has been passed through 0 100 meters of 100 Ohm category 5 or 150 Ohm STP The TX receiver consists of an adaptive equalizer baseline wander correction circuit comparators and MLT 3 decoder The TP inputs first go to an adaptive equalizer The adaptive equalizer compensates for the low pass characteristic of the cable and it has the ability to adapt and compensate for 0 100 meters of category 5 100 Ohm UTP or 150 Ohm STP twisted pair cable The baseline wander correction circuit restores the DC component of the input waveform that was removed by external transformers The comparators convert the equalized signal back to digital levels and are used to qualify the data with the squelch circuit The MLT 3 decoder takes the three level MLT 3 digital data from the comparators and converts it to back to normal digital data to be used for dock and data recovery Receiver 10 Mbps The 10 Mbps receiver is able to detect input signals from the twisted pair cable that are within the template shown in Figure 7 5 The inputs are biased by internal resistors The TP inputs pass through a low pass filter designed to eliminate any high frequency
35. at internal MII is asserted as described in the Controller Interface section Refer to the TP squelch section for 10 Mbps mode for the algorithm for valid data detection 7 7 11 End of Packet 100 Mbps End of packet for 100 Mbps mode is indicated by the End of Stream Delimiter referred to as ESD The ESD pattern consists of the two T R 4B5B symbols inserted after the end of the packet as defined in IEEE 802 3 Clause 24 The transmit ESD is generated by the 4B5B encoder and the T R symbols are inserted by the 4B5B encoder after the end of the transmit data packet The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits two 5B words from the descrambler during valid packet reception to determine if there is an ESD If the 10 consecutive code bits from the receiver during valid packet reception consist of the T R symbols the end of packet is detected data reception is terminated the MAC is notified of valid data received and symbols are substituted in place of the T R symbols If 10 consecutive code bits from the receiver during valid packet reception do not consist of T R symbols but consist of symbols instead then the packet is considered to have been terminated prematurely and abnormally When this premature end of packet condition is detected the MAC is notified of invalid data received for the nibble associated with the first symbol Premature end of packet
36. by the controller regardless of the value written in memory DATA AREA The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS followed by variable length number of bytes On transmit all bytes are provided by the CPU including the source address The LAN91C111 does not insert its own source address On receive all bytes are provided by the CSMA side The 802 3 Frame Length word Frame Type in Ethernet is not interpreted by the LAN91C111 It is treated transparently as data both for transmit and receive operations CONTROL BYTE For transmit packets the CONTROL BYTE is written by the CPU as X X ODD CRC 0 0 0 0 ODD If set indicates an odd number of bytes with the last byte being right before the CONTROL BYTE If clear the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted CRC When set CRC will be appended to the frame This bit has meaning only if the NOCRC bit in the TCR is set For receive packets the CONTROL BYTE is written by the controller as 0 1 ODD 0 0 0 0 0 ODD If set indicates an odd number of bytes with the last byte being right before the CONTROL BYTE If clear the number of data bytes is even and the byte before the
37. condition is also indicated by setting the bad ESD bit in the PHY MI serial port Status Output register 10 Mbps The end of packet for 10 Mbps mode is indicated with the SOI Start of Idle pulse The SOI pulse is a positive pulse containing a Manchester code violation inserted at the end of every packet The transmit SOI pulse is generated by the TP transmitter and inserted at the end of the data packet after TXEN is deasserted The transmitted SOI output pulse at the TP output is shaped by the transmit waveshaper to meet the pulse template requirements specified in IEEE 802 3 Clause 14 and shown in Figure 7 6 The receive SOI pulse is detected by the TP receiver by sensing missing data transitions Once the SOI pulse is detected data reception is ended and the MAC is notified of no data invalid data received Revision 1 91 08 18 08 36 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet 4 5 31Vv 0 25BT 2 25 BT 585 mV 585 mV sin 2 t 1BT 0 lt t lt 0 25 BT and 2 25 lt t lt 2 5 BT 3 1 V N 2 5 BT 4 5 BT Figure 7 6 SOI Output Voltage Template 10MBPS 7 7 12 Link Integrity amp AutoNegotiation General The LAN91C111 can be configured to implement either the standard link integrity algorithms or the AutoNegotiation algorithm The standard link integrity algorithms are used solely to esta
38. indicates completion This signal is synchronous to the bus clock LCLK 46 48 nReady Return nRDYRTN Input This input is used to complete synchronous read cycles In EISA burst mode it is sampled on falling LCLK edges and synchronous cycles are delayed until it is sampled high 29 31 Interrupt INTRO 024 Interrupt Output Active High it s used to interrupt the Host on a status event Note The selection bits used to determined by the value of INT SEL 1 0 bits in the Configuration Register are no longer required and have been set to reserved in this revision of the FEAST family of devices 45 47 nLocal Device nLDEV 016 Output This active low output is asserted when AEN is low and A4 A15 decode to the LAN91C111 address programmed into the high byte of the Base Address Register nLDEV is a combinatorial decode of unlatched address and AEN signals 31 33 nRead Strobe nRD IS Input Used in asynchronous bus interfaces 32 34 nWrite Strobe nWR IS Input Used in asynchronous bus interfaces 34 Revision 1 91 08 18 08 36 nData Path Chip Select nDATACS 16 with pullup DATASHEET Input When nDATACS is low the Data Path can be accessed regardless of the values of AEN A1 A15 and the content of the BANK SELECT Register nDATACS provides an interface for bursting to and from the LAN91C111 32 b
39. interfaces the CSMA CD Transmit and Receive FIFOs on one side and the Arbiter block on the other To increase the bandwidth into memory a 50 MHz clock is used by the DMA block and the data path is 32 bits wide For example during active reception at 100 Mbps the CSMA CD block will write a word into the Receive FIFO every 160ns The DMA will read the FIFO and accumulate two words on the output port to request a memory cycle from the Arbiter every 320ns The DMA machine is able to support full duplex operation Independent receive and transmit counters are used Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed Arbiter Block The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks BIU requests represent pipelined CPU accesses to the Data Register while DMA requests represent CSMA CD data movement Internal SRAM read accesses are always 32 bit wide and the Arbiter steers the appropriate byte s to the appropriate lanes as a function of the address The CPU Data Path consists of two uni directional FIFOs mapped at the Data Register location These FIFOs can be accessed in any combination of bytes word or doublewords The Arbiter will indicate Not Ready whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO MMU Block The Hardware Memory Management Unit allocates memory and transmit and receive packet queues It
40. noise on the input The output of the receive filter goes to two different types of comparators squelch and zero crossing The squelch comparator determines whether the signal is valid and the zero crossing comparator is used to sense the actual data transitions once the signal is determined to be valid The output of the squelch comparator goes to the squelch circuit and is also used for link pulse detection SOI detection and reverse polarity detection the output of the zero crossing comparator is used for clock and data recovery in the Manchester decoder SMSC LAN91C111 REV C 33 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE a Short Bit b Long Bit cese Slope 0 5 V ns 585 585 mV sin 2 UPW 585 mV sin 2 tr t PW 2 PW 0 PW 4 3PW 4 PW Figure 7 5 TP Input Voltage Template 10MBPS TP Squelch 100 Mbps The squelch block determines if the TP input contains valid data The 100 Mbps TP squelch is one of the criteria used to determine link integrity The squelch comparators compare the TP inputs against fixed positive and negative thresholds called squelch levels The output from the squelch comparator goes to a digital squelch circuit which determines if the receive input data on that channel is valid If the data is invalid the receiver is in the squelched state If the input voltage exceed
41. of the turnaround D 15 0 Data These 16 bits contain data to from one of the eleven registers Any selected by register address bits REGAD 4 0 Revision 1 91 08 18 08 72 SMSC LAN91C111 REV C DATASHEET EP SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet 0 0 0 0 0 L 0 L 0 0 paniosoH 0 0 0 0 0 0 L L L L L L L L L L pamasay 1 1 Svr asaw assw NASSSOTW UVANNIN ANIW 0 0 0 0 0 0 0 L 0 0 0 0 0 0 0 0 u u u 178 va 178 u 1 ave asa ass ONASSSOT UVANT 0 0 0 0 0 0 0 0 L L L L L L L L
42. or Full Duplex capability from a remote device and automatically place itself in the correct mode The device can be forced into the Full or Half Duplex modes by either setting the duplex bit in the MI serial port Control register The device can automatically configure itself for Full or Half Duplex modes by using the AutoNegotiation algorithm to advertise and detect Full and Half Duplex capabilities to and from a remote terminal All of this is described in detail in the Link Integrity and AutoNegotiation section 10 Mbps Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode 100 10 Mbps SELECTION General The device can be forced into either the 100 or 10 Mbps mode or the device also can detect 100 or 10 Mbps capability from a remote device and automatically place itself in the correct mode The device can be forced into either the 100 or 10 Mbps mode by setting the speed select bit in the PHY MI serial port Control register assuming AutoNegotiation is not enabled The device can automatically configure itself for 100 or 10 Mbps mode by using the AutoNegotiation algorithm to advertise and detect 100 and 10 Mbps capabilities to and from a remote terminal All of this is described in detail in the Link Integrity amp AutoNegotiation section 7 7 16 Loopback Diagnostic Loopback A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control register When diagnostic loopback is enable
43. pins 24 39 52 26 41 54 Ground GND Ground pins 57 67 72 59 69 74 93 103 95 105 108 117 110 119 13 19 15 21 Analog Ground AGND Analog Ground pins 21 23 Loopback LBK 04 Output Active when LOOP bit is set TCR bit 1 20 22 nLink Status nLNK with Input General purpose input port used to pullup convey LINK status EPHSR bit 14 28 30 nCNTRL nCNTRL O12 General Purpose Control Pin 47 49 X25out X250ut 012 25Mhz Output to external PHY 111 113 Transmit Enable TXEN100 O12 Output to MII PHY Envelope to 100 100 Mbps Mbps transmission 119 121 Carrier Sense CRS100 I with Input from MII PHY Envelope of packet 100 Mbps pulldown reception used for deferral and backoff purposes SMSC LAN91C111 REV 17 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet PIN NO NAME SYMBOL BUFFER DESCRIPTION TQFP QFP 125 127 Receive Data RX DV I with Input from MII PHY Envelope of data Valid pulldown valid reception Used for receive data framing 112 114 Collision Detect COL100 I with Input from MII PHY Collision detection 100 Mbps pulldown input 113 116 115 118 Transmit Data TXD3 012 Outputs Transmit Data nibble to MII TXDO PHY 109 111 Transmit Clock 25 I with Input Transmit clock input from MII pullup Nibble rate clock 25MHz for 100Mbps amp 2 5MHz for 10Mbps 118 120 Re
44. pins are able to accept 5V signals DC levels and conditions defined in the DC Electrical Characteristics section SMSC LAN91C111 REV 19 Revision 1 91 08 18 08 DATASHEET EP SMSC 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Chapter 7 Functional Description 7 1 7 2 7 2 1 7 2 2 7 3 Clock Generator Block 1 The XTAL1 and XTAL2 pins are to be connected to 25 MHz crystal 2 TX25 is an input clock It will be the nibble rate of the particular PHY connected to the MII 2 5 MHz for 10 Mbps PHY and 25 MHz for 100 Mbps PHY 3 RX25 This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive state machine 2 5 MHz for 10 Mbps PHY and 25 MHz for 100 Mbps PHY 4 LCLK Bus clock Used by the BIU for synchronous accesses Maximum frequency is 50 MHz for VL BUS mode and 8 33 MHz for EISA slave CSMA CD Block This is 16 bit oriented block with fully independent Transmit and Receive logic The data path in and out of the block consists of two 16 bit wide uni directional FIFOs interfacing the DMA block The DMA port of the FIFO stores 32 bits to exploit the 32 bit data path into memory but the FIFOs themselves are 16 bit wide The Control Path consists of a set of registers interfaced to the CPU via the BIU DMA Block This block accesses packet memory on the CSMA CD s behalf fetching transmit data and storing received data It
45. ports of the Receive FIFO and the Transmit completion FIFO The packet numbers to be processed by the interrupt service routines are read from this register HIGH REMPTY Reserved RX FIFO PACKET NUMBER BYTE 1 0 0 0 0 0 0 0 LOW TEMPTY Reserved TX FIFO PACKET NUMBER BYTE 1 0 0 0 0 0 0 0 REMPTY No receive packets queued in the RX FIFO For polling purposes uses the ROV INT bit in the Interrupt Status Register TOP OF RX FIFO PACKET NUMBER Packet number presently at the output of the RX FIFO Only valid if REMPTY is clear The packet is removed from the RX FIFO using MMU Commands 3 or 4 Revision 1 91 08 18 08 60 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE TEMPTY No transmit packets in completion queue For polling purposes uses the TX INT bit in the Interrupt Status Register TX FIFO PACKET NUMBER Packet number presently at the output of the TX FIFO Only valid if TEMPTY is clear The packet is removed when TX INT acknowledge is issued Note For software compatibility with future versions the value read from each FIFO register is intended to be written into the PNR as is without masking higher bits provided TEMPTY and REMPTY 0 respectively 8 19 Bank 2 Pointer Register OFFSET NAME TYPE SYMBOL READ WRITE NOT EMPTY IS A READ ON
46. squelch criteria 2 data being passed to the MAC are forced to all 0 s 3 MAC is notified of the collision when the SQE test is performed 4 MAC is notified of the collision when the jabber condition has been detected Collision Test The MAC and PHY collision indication can be tested by setting the collision test register bit in the PHY MI serial port Control register When this bit is set internal TXEN from the MAC is looped back onto COL and the TP outputs are disabled Start of Packet 100 Mbps Start of packet for 100 Mbps mode is indicated by a unique Start of Stream Delimiter referred to as SSD The SSD pattern consists of the two J K 5B symbols inserted at the beginning of the packet in place of the first two preamble symbols as defined in IEEE 802 3 Clause 24 The transmit SSD is generated by the 4B5B encoder and the J K symbols are inserted by the 4B5B encoder at the beginning of the transmit data packet in place of the first two 5B symbols of the preamble The receive pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits two 5B words from the descrambler Between packets the receiver will be detecting the idle pattern which is 5B symbols While in the idle state the MAC is notified that no data invalid data is received If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the J K symbols the start of packet is detected data recepti
47. the second word If the CRC checks correctly the packet number is written into the RX FIFO The RX FIFO being not empty causes RCV INT interrupt to be set The BAD bit of the Bank 1 Control Register controls whether or not to generate interrupts when bad CRC packets are received 5 SERVICE INTERRUPT Read the Interrupt Status Register and determine if RCV INT is set The next receive packet is at receive area Its packet number can be read from the FIFO Ports Register The software driver can process the packet by accessing the RX area and can move it out to system memory if desired When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number SMSC LAN91C111 REV C 87 Revision 1 91 08 18 08 DATASHEET SMSC 10 100 Ethernet Single Chip MAC PHY Datasheet ISR Save Bank Select amp Address Ptr Registers Y Mask SMC91C111 Interrupts Y Read Interrupt Register A No lt Yes lt lt RX INTR Yes Bit Call TX INTR or TXEMPTY o TX INTR gt secs Call RXINTR Get Next TX p Packet Y ALLOC INTR gt lt lt Availablefor gt No 7 Yes Y Yes Transmission Write Allocated Pkt into Packet Number Reg Y Call ALLOCATE Write Ad Pir Reg
48. 0 D31 D0 D31 32 bit data bus The bus byte s used to access the device are a function of nBEO nBE3 Double word access Low word access High word access Byte 0 access Byte 1 access Byte 2 access Byte 3 access Not used tri state on reads ignored on writes Note that nBE2 and override the value of A1 which is tied low in this application nLDEV nLDEV nLDEV is a totem pole output nLDEV is active on valid decodes of A15 A4 and AEN O UNUSED PINS VCC nRD nWR GND A1 nVLBUS OPEN nDATCS SMSC LAN91C111 REV 99 Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet VLBUS W nR W nR A2 A15 A2 A15 LCLK M nlO LCLK AEN nRESET LAN91C111 IRQn 031 INTRO DO D31 nRDYRTN nRDYRTN nBEO nBE3 nBEO nBES3 nADS Delay 1 LCLK simulated OG nADS nCYCLE Figure 12 1 LAN91C111 on VL BUS HIGH END ISA OR NON BURST EISA MACHINES On ISA machines the LAN91C111 is accessed as a 16 bit peripheral The signal connections are listed in the following table Table 12 2 High End ISA or Non Burst EISA Machines Signal Connectors SABUS mores A1 A15 A1 A15 Address bus used for I O space and register decoding AEN AEN Qualifies valid 1 decoding enabled access when low nlORD nRD I O Read strobe asynchronous read accesses Address i
49. 0100 1 08 0101 1 06 0110 1 04 0111 1 02 1000 1 00 1001 0 98 1010 0 96 1011 0 94 1100 0 92 1101 0 90 1110 0 88 1111 0 86 Transmit Rise and Fall Time Adjust The transmit output rise and fall time can be adjusted with the two transmit rise fall time adjust bits in the PHY MI serial port Configuration 1 The adjustment range is 0 25ns to 0 5ns in 0 25ns steps Revision 1 91 08 18 08 32 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet 7 7 8 EP smsc STP 150 Ohm Cable Mode The transmitter can be configured to drive 150 Ohm shielded twisted pair cable The STP mode can be selected by appropriately setting the cable type select bit in the PHY MI serial port Configuration 1 register When STP mode is enabled the output current is automatically adjusted to comply with IEEE 802 3 levels Transmit Disable The TP transmitter can be disabled by setting the transmit disable bit in the PHY MI serial port Configuration 1 register When the transmit disable bit is set the TP transmitter is forced into the idle state no data is transmitted no link pulses are transmitted and internal loopback is disabled Transmit Powerdown The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY MI serial port Configuration 1 register When the transmit powerdown bit is set the TP transmitter is powered down the TP transmit outputs are high impedance
50. 1 Disable Transmitter Clear the TXENA bit of the Ethernet MAC finishes packet currently being Transmit Control Register transmitted 2 Remove and release all TX completion packet numbers on the TX completion FIFO 3 Disable Receiver Clear the RXEN bit of the The receiver completes receiving the current frame if Receive Control Register any and then goes idle Ethernet MAC will no longer receive any packets 4 Process all Received packets and Issue a Remove RX and TX completion FIFO s are now Empty and and Release command for each respective RX all MMU packet numbers are now free packet buffer 5 Disable Interrupt sources Clear the Interrupt Status Register Save Device Context Save all Specific Register Values set by the driver 6 Set PDN bit in PHY MI Register O to 1 7 The internal PHY entered in powerdown mode the TP outputs are in high impedance state 8 Write to the EPH Power EN Bit located in the configuration register Bank 1 Offset 0 9 Ethernet MAC gates the RX Clock TX clock derived from the Internal PHY The EPH Clock is also disabled 10 The Ethernet MAC is now in low power mode The Host may access all Runtime IO mapped registers All IO registers are still accessible However the Host should not read or write to the registers with the exception of Configuration Register Control Register Bank Register Revision 1 91 08 18 08 84 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Si
51. 27 7 7 2 ze x 27 7 7 8 Decoder uic Xa adi E ce SE ee Aetio sk NR e FR een RR wees 27 7 7 4 Clock and Data Recovery 29 7 7 5 SGratmbDlet desse ad E Des 29 7 7 6 gt 52 we 29 7 7 7 Twisted Pair 30 7 7 8 Twisted Pair 1 33 7 7 9 eni EL 35 43540 Stato s esie sek here sv eger teen dose 35 LGV ENdofP cket uet Et c sce Rut Rar tee UU Bo Re ee hoe 36 7 7 12 Link Integrity amp AutoNegotiation 37 LANS Jabber nie ecu deen eh EE AR ee aa ee ER aS Ee See Rane 40 7 7 14 Receive Polarity 1 40 7 7 15 Full Duplex Mode isc ere ea bee ae oa 41 LANG LoopDack ione 41 PHY PowerdoWn ue is veg ge a Ro keiser CRT RC 41 77 18 PHY Intertupt eee mde tma D teo ep wae enne eas 41 18 Reset M 42 Chapter 8 MAC Data Structures and 43 8 1 Frame Format In Buffer Memory
52. 80 1 2 VDD 3 3V Adjustable with RBIAS Adjustment Range relative to TOIA with RBIAS 11K 0 86 1 16 VDD 3 3V Adjustable with LVL 3 0 Relative to Value at TLVL 3 0 1000 TORA TP Output Current 50 Relative to Ideal Values in Table 3 TLVL Step Accuracy Table 3 Values Relative to Output with TLVL 3 0 1000 TOR TP Output 10K Ohm Resistance TOC TP Output 15 pF Capacitance 13 4 Twisted Pair Characteristics Receive Unless otherwise noted all test conditions are as follows a Vcc 3 3V 5 a RBIAS 11K 1 no load 62 5 10 Mhz Square Wave on TP inputs 100 10 Mbps LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX RST TP Input Squelch 166 500 mV pk 100 Mbps RLVL 0 Threshold 310 540 mV 10 Mbps RLVL 0 60 200 mV pk 100 Mbps RLVL 1 186 324 mV pk 10 Mbps RLVL 1 RUT TP Input Unsquelch 100 300 mV pk 100 Mbps RLVL 0 Threshold 186 324 mV pk 10 Mbps RLVL 0 20 90 mV pk 100 Mbps RLVL 1 112 194 mV pk 10 Mbps RLVL 1 TP Input Open Circuit VDD 2 4 Volt Voltage on Either TPI or TPI with Voltage 0 2 Respect to GND RCMR Input Common ROCV Volt Voltage on TPI with Respect to Mode Voltage Range 0 25 GND RDR TP Input Differential VDD Volt Voltage Range RIR TP Input Resistance 5K Ohm RIC TP Input Capacitance 10 pF SMSC LAN91C111 REV C 109 Revision 1 91 08 18 08 DATASHEET 10 100 E
53. 91C111 REV C 105 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS Input Leakage All I and IS buffers except pins with pullups pulldowns lu 10 10 Vin 0 Low Input Leakage 10 10 Vin Voc High Input Leakage IP Type Buffers Input Current liL 110 45 Vn 0 ID Type Buffers Input Current li 45 110 Vin Vcc O4 Type Buffer Low Ouiput Level Vor 0 4 lg 6 mA High Output Level Vor 2 4 V 4 mA Output Leakage 10 10 Vin 0 to Voc 1 04 Type Buffer Low Output Level VoL 0 4 V lo 6 mA High Output Level 2 4 V 4 mA Output Leakage 10 10 Vin 0 to Voc 012 Type Buffer Low Output Level VoL 0 4 V loy 20 mA High Output Level 2 4 V 10 mA Output Leakage 10 10 Vin 0 to Veg 016 Type Buffer Low Output Level VoL 0 4 V 35 mA High Output Level Vou 2 4 V 15 mA Output Leakage 10 10 Vin 010 Voc 024 Type Buffer Low Output Level VoL 0 4 V 35 mA High Output Level 2 4 V 15 mA Output Leakage 10 10 Vin 0 to Voc Revision 1 91 08 18 08 106 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC EP SMSE D
54. 91C111 REV C 47 SWFDUP Enables Switched Full Duplex mode In this mode transmit state machine is inhibited from recognizing carrier sense so deferrals will not occur Also inhibits collision count therefore the collision related status bits in the EPHSR are not valid ROL LATCOL SQET 16COL MUL COL and SNGL COL Uses COL100 as flow control limiting backoff and jam to 1 clock each before inter frame gap then retry will occur after IFG If COL100 is active during preamble full preamble will be output before jam When SWFDUP is high the values of FDUPLX and MON CSN have no effect EPH LOOP Internal loopback at the EPH block Serial data is internally looped back when set Defaults low When EPH LOOP is high the following transmit outputs are forced inactive TXDO TXD3 Oh TXEN100 0 The following and external inputs are blocked CRS100 0 COL100 0 RX DV RX ER 0 STP SQET STP SQET Stop transmission on SQET error If this bit is set LAN91C111 will stop and disable the transmitter on SQE test error If the external SQET generator on the network generates the SQET pulse during the IPG Inter Frame Gap this bit will not be set and subsequent transmits will occur as the case of implementing Auto Release for multiple transmit packets If this bit is cleared then the SQET bit in the EPH Status register will be cleared Defaults low FDUPLX When set the LAN91C111 will cause frames to be received if they pass the ad
55. ASE packet number command to free up the memory used by this packet Remove packet number from completion FIFO by writing TX INT Acknowledge Register Option 1 Release the packet Option 2 Check the transmit status in the EPH STATUS Register write the packet number of the current packet to the Packet Number Register re enable TXENA then go to step 4 to start the TX sequence again 10 3 Typical Flow of Events for Transmit Auto Release 1 S W DRIVER MAC SIDE 1 ISSUE ALLOCATE MEMORY FOR TX N BYTES the MMU attempts to allocate N bytes of RAM 2 WAIT FOR SUCCESSFUL COMPLETION CODE Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt The TX packet number is now at the Allocation Result Register 3 LOAD TRANSMIT DATA Copy the TX packet number into the Packet Number Register Write the Pointer Register then use a block move operation from the upper layer transmit queue into the Data Register 4 ISSUE ENQUEUE PACKET NUMBER TO TX FIFO This command writes the number present in the Packet Number Register into the TX FIFO The transmission is now enqueued No further CPU intervention is needed until a transmit interrupt is generated 5 The enqueued packet will be transferred to the MAC block as a function of TXENA nTCR bit and of the deferral process 1 2 duplex mode only state 6 Transmit pages are released by transmit completion
56. C LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet 7 7 9 7 7 10 SMSC Equalizer Disable The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY MI serial port Configuration 1 register When disabled the equalizer is forced into the response it would normally have if zero cable length was detected Receive Level Adjust The receiver squelch and unsquelch levels can be lowered by 4 5 dB by setting the receive level adjust bit in the PHY MI serial port Configuration 1 register By setting this bit the device may be able to support longer cable lengths Collision 100 Mbps Collision occurs whenever transmit and receive occur simultaneously while the device is in Half Duplex Collision is sensed whenever there is simultaneous transmission packet transmission on TPO and reception non idle symbols detected on TP input When collision is detected the MAC is notified Once collision starts the receive and transmit packets that caused the collision are terminated by their respective MACs until the responsible MACs terminate the transmission the PHY continues to pass the data on The collision function is disabled if the device is in the Full Duplex mode is in the Link Fail State or if the device is in the diagnostic loopback mode 10 Mbps Collision in 10Mbps mode is identical to the 100Mbps mode except 1 reception is determined by the 10Mbps
57. D RELEASE 0 0 0 1 0 0 1 0 LOW BYTE LE CR TE Reserved Reserved EEPROM RELOAD STORE ENABLE ENABLE ENABLE SELECT 0 0 0 1 0 0 0 0 SMSC LAN91C111 REV C RCV BAD When set bad CRC packets are received When clear bad CRC packets do not generate interrupts and their memory is released AUTO RELEASE When set transmit pages are released by transmit completion if the transmission was successful when TX SUC is set In that case there is no status word associated with its packet number and successful packet numbers are not even written into the TX COMPLETION FIFO A sequence of transmit packets will generate an interrupt only when the sequence is completely transmitted TX EMPTY INT will be set or when a packet in the sequence experiences a fatal error TX INT will be set Upon a fatal error TXENA is cleared and the transmission sequence stops The packet number that failed is present in the FIFO PORTS register and its pages are not released allowing the CPU to restart the sequence after corrective action is taken LE ENABLE Link Error Enable When set it enables the LINK OK bit transition as one of the interrupts merged into the EPH INT bit Clearing the LE ENABLE bit after an EPH INT interrupt caused by a LINK OK transition will acknowledge the interrupt LE ENABLE defaults low disabled CR ENABLE Counter Roll over Enable When set it enables the CTR ROL bit as one of the interrupts merged in
58. DC of the MII Management serial interface Datasheet MDIO Management Data input output Bi directional between and PHY that carries management data All control and status information sent over this pin is driven and sampled synchronously to the rising edge of signal MDC Management Data Clock Sourced by the as a timing reference for transfer of information on the MDIO signal MDC is a periodic signal with no maximum high or low times The minimum high and low times should be 160ns each and the minimum period of the signal should be 400ns These values are regardless of the nominal period of the TX and RX clocks 7 5 2 Management Data Timing A timing diagram for a MI serial port frame is shown in Figure 7 1 The MI serial port is idle when at least 32 continuous 1 s are detected on MDIO and remains idle as long as continuous 1 s are detected During idle MDIO is in the high impedance state When the MI serial port is in the idle state a 01 pattern on the MDIO initiates a serial shift cycle Data on MDIO is then shifted in on the next 14 rising edges of MDC MDIO is high impedance If the register access mode is not enabled on the next 16 rising edges of MDC data is either shifted in or out on MDIO depending on whether a write or read cycle was selected with the bits READ and WRITE After the 32 MDC cycles have been completed one complete register has been read written the serial shift process is halted data is latched
59. Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by the PLL The data is then converted from a single bit stream into nibble wide data word according to the format shown in Figure 7 2 Clock Recovery 10 Mbps The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except 1 the recovered clock frequency is 2 5 MHz nibble clock 2 the PLL is switched from TX25 to the TP input when the squelch indicates valid data 3 The PLL takes up to 12 transitions bit times to lock onto the preamble so some of the preamble data symbols are lost but the dock recovery block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the receive controller interface as shown in Figure 7 2 Data Recovery 10 Mbps The data recovery process for 10Mbps mode is identical to the 100Mbps mode As mentioned in the Manchester Decoder section the data recovery process inherently performs decoding of Manchester encoded data from the TP inputs 7 7 5 Scrambler 100 Mbps 100BASE TX requires scrambling to reduce the radiated emissions on the twisted pair The LAN91C111 scrambler takes the encoded data from the 4B5B encoder scrambles it per the IEEE 802 3 specifications and sends it to the TP transmitter 10 Mbps A scrambler is not used in 10Mbps mode Scrambler Bypass The scrambler can be bypassed by setting the bypass scrambler descrambler bit in the PHY MI serial port Configuratio
60. E RCR HIGH SOFT FILT ABORT E Reserved Reserved Reserved STRIP RXEN BYTE RST CAR NB CRC 0 0 0 0 0 0 0 0 LOW Reserved Reserved Reserved Reserved Reserved ALMUL PRMS RX BYTE ABORT 0 0 0 0 0 0 0 0 SOFT RST Software Activated Reset Active high Initiated by writing this bit high terminated by writing the bit low The LAN91C111 s configuration is not preserved except for Configuration Base and 0 5 Registers EEPROM is not reloaded after software reset FILT CAR Filter Carrier When set filters leading edge of carrier sense for 12 bit times 3 nibble times Otherwise recognizes a receive frame as soon as carrier sense is active Does NOT filter RX DV on MII SMSC LAN91C111 REV C 49 Revision 1 91 08 18 08 DATASHEET SMSE 8 8 10 100 Ethernet Single Chip MAC PHY Datasheet ABORT ENB Enables abort of receive when collision occurs Defaults low When set the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated This bit has no effect if the SWFDUP bit in the TCR is set STRIP CRC When set it strips the CRC on received frames As a result both the Byte Count and the frame format do not contain the CRC When clear the CRC is stored in memory following the packet Defaults low RXEN Enables the receiver when set If cleared completes receiving current frame and then goes idle Defaults low on reset ALMUL When set accep
61. EN nBE 3 0 Setup to nADS Rising 8 ns t9 A1 A15 AEN nBE 3 0 Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns 111 nCYCLE Hold Rising Non Burst Mode 3 ns t16 W nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising Read 4 ns t21 nSRDY Delay from LCLK Rising 7 ns t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold after LCLK Rising 3 ns 127 TXDO TXD3 EN 127 gt TXEN100 RXDO RXD3 FEE RX25 RX DV RX ER Figure 14 10 MII Timing PARAMETER MIN TYP MAX UNITS 127 TXDO TXD3 100 Delay from TX25 Rising 0 15 ns 128 RXDO RXD3 RX DV RX ER Setup to RX25 Rising 10 ns t29 RXDO RXD3 RX DV RX ER Hold After RX25 Rising 10 ns SMSC LAN91C111 REV C 117 Revision 1 91 08 18 08 DATASHEET SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet AG TEST TIMING CONDITIONS Unless otherwise noted all test conditions are as follows 1 VoD 3 3V 5 2 RBIAS 11K 1 no load 3 Measurement Points 4 TPl 0 0 V During Data 0 3V at start end of packet 5 All other inputs and outputs 1 4 Volts Table 14 1 Transmit Timing Characteristics LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX 130 Transmit Propagation Delay 60 140 nS 100Mbps 600 nS 10Mbps t31 Transmit Output Jitter 0 7 nS pk pk 100Mbps 5 5 NS pk pk 10Mbps t32 Transmit SOI Pulse Width to 250 nS 10Mbps 0 3V t33 Transmit
62. FINITION R W IDLE Idle Pattern These bits are an idle pattern Device will not initiate an MI cycle until W it detects at least 32 1 s Start Bits When ST 1 0 01 MI Serial Port access cycle starts W READ Read Select 1 Read Cycle W WRITE Write Select 1 Write Cycle W PHYAD 4 0 Physical PHYSICAL ADDRESS R Device Address SMSC LAN91C111 REV 71 DATASHEET Revision 1 91 08 18 08 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet SYMBOL NAME DEFINITION R W REGAD 4 0 Register If REGAD 4 0 00000 11110 these bits determine the specific W Address register from which D 15 0 is read written If multiple register access is enabled and REGAD 4 0 11111 all registers are read written in a single cycle TA1 Turnaround These bits provide some turnaround time for MDIO R W TAO Time When READ 1 TA 1 0 70 When WRITE 1 TA 1 0 10 The turnaround time is a 2 bit time spacing between the Register Address field and the Data field of a management frame to avoid contention during a read transaction For a read transaction both the STA and the PHY shall remain high impedance state for the first bit time of the turnaround The PHY shall drive zero bit during the second bit time of the turnaround of read transaction During write transaction the STA shall drive one bit for the first bit time of the turnaround and zero bit for the second bit time
63. ITIONS SYM PARAMETER MIN TYP MAX t42 NLP Transmit Link Pulse Width See Figure 7 8 nS t43 NLP Transmit Link Pulse Period 8 24 mS 144 NLP Receive Link Pulse Width Required 50 nS For Detection t45 NLP Receive Link Pulse Minimum Period 6 7 mS link test min Required For Detection t46 NLP Receive Link Pulse Maximum 50 150 mS link test max Period Required For Detection 147 Receive Link Pulse Required To 3 3 3 Link max Exit Link Fail State Pulses 148 FLP Transmit Link Pulse Width 100 150 nS t49 FLP Transmit Clock Pulse to Data Pulse 55 5 62 5 69 5 uS interval_timer Period t50 FLP Transmit Clock Pulse to Clock Pulse 111 125 139 uS Period t51 FLP Transmit Link Pulse Burst Period 8 22 mS transmit link burst time r t52 FLP Receive Link Pulse Width Required 50 nS For Detection 153 FLP Receive Link Pulse Minimum Period 5 25 us flp_test_min_timer Required For Clock Pulse Detection 154 FLP Receive Link Pulse Maximum 165 185 us flp_test_max_timer Period Required For Clock Pulse Detection 155 FLP Receive Link Pulse Minimum Period 15 47 uS data detect min timer Required For Data Pulse Detection 156 FLP Receive Link Pulse Maximum 78 100 us data_detect_max_timer Period Required For Data Pulse Detection 157 FLP Receive Link Pulse Burst Minimum 5 7 mS nlp test min timer Period Required For Detection 158 Receive Link Pulse Burst Maximum 50 150 mS test max timer Period Required For Detection 159 FLP Receive Link Pul
64. K bit should only be set after the following steps A packet is enqueued for transmission The previous empty condition is cleared acknowledged TX INT Set when at least one packet transmission was completed or any of the below transmit fatal errors occurs SQET SQE Error LOST CARR Lost Carrier LATCOL Late Collision 16COL 16 collisions The first packet number to be serviced can be read from the FIFO PORTS register The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS register After servicing a packet number its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit set RCV INT Set when a receive interrupt is generated The first packet number to be serviced can be read from the FIFO PORTS register The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register Receive Interrupt is cleared when RX FIFO is empty Revision 1 91 08 18 08 64 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY EP sSmsc Datasheet SLdNYYILNI NIVIN E 8 610 0 6 sna viva Jaysibay YSEIN 1dnueju 30 JeisiBeu SNIS J NUAJU Om 151 INI LNI OLNI G3943N SLdNYYILNI HSHd3 if ANI NHAO sk
65. L MAX REMARKS A 3 4 Overall Package Height Al 0 05 0 5 Standoff A2 2 55 3 05 Body Thickness D 23 70 23 90 24 10 X Span D 2 11 85 11 95 12 05 2 X Span Measured from Centerline D1 19 90 20 0 20 10 X body Size E 17 70 17 90 18 10 Y Span E 2 8 85 8 95 9 05 Y Span Measured from Centerline 1 13 90 14 00 14 10 Y body Size H Lead Frame Thickness L 0 73 0 88 1 03 Lead Foot Length L1 x 1 95 Lead Length e 0 5 Basic Lead Pitch q 0 79 Lead Foot Angle W 0 10 0 30 Lead Width R1 0 13 Lead Shoulder Radius R2 0 13 0 30 Lead Foot Radius x 0 0762 Coplanarity Assemblers 0 08 Coplanarity Test House SMSC LAN91C111 REV C Notes 1 Controlling Unit millimeter 2 Tolerance on the position of the leads is 0 04 mm maximum 3 Package body dimensions D1 and E1 do not include the mold protrusion Maximum mold protrusion is 0 25 mm 4 Dimension for foot length L measured at the gauge plane 0 25 mm above the seating plane 5 Details of pin 1 identifier are optional but must be located within the zone indicated 127 Revision 1 91 08 18 08 DATASHEET lt Chapter 16 Revision History 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Table 16 1 Customer Revision History REVISION LEVEL amp DATE SECTION FIGURE ENTRY CORRECTION Rev 1 9 All Updated document references to Rev C 07 17 08 Rev 1 9 Section 13 1
66. LE 5 BYTE 0 0 0 0 0 0 0 0 LOW MULTICAST TABLE 6 BYTE 0 0 0 0 0 0 0 0 HIGH MULTICAST TABLE 7 BYTE 0 0 0 0 0 0 0 0 The 64 bit multicast table is used for group address filtering The hash value is defined as the six most significant bits of the CRC of the destination addresses The three msb s determine the register to be used MTO MT7 while the other three determine the bit within the register If the appropriate bit in the table is set the packet is received If the ALMUL bit in the RCR register is set all multicast addresses are received regardless of the multicast table values Hashing is only a partial group addressing filtering scheme but being the hash value available as part of the receive status word the receive routine can reduce the search time significantly With the proper memory structure the search is limited to comparing only the multicast addresses that have the actual hash value in question Revision 1 91 08 18 08 66 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE 8 23 Bank 3 Management Interface OFFSET NAME TYPE SYMBOL MANAGEMENT 8 INTERFACE READ WRITE MGMT HIGH Reserved MSK_ Reserved Reserved Reserved Reserved Reserved Reserved BYTE CRS100 0 0 1 1 0 0 1 1 LOW Reserved MDOE MCLK MDI MDO BYTE 0 0 1 1 0 0 MDI Pin 0 MSK CRS100 Disables CRS100 detection during transmit in half duplex mode SWFD
67. LT R LT R LT R LT R LT R LT R LT 0 0 0 0 0 0 0 0 SPDDET DPLXDET Reserved Reserved Reserved Reserved Reserved Reserved R LT R LT R R R R R R 1 0 0 0 0 0 0 0 Interrupt Detect 1 Interrupt Bit s Have Changed Since Last Read Operation 0 No Change LNKFAIL Link Fail Detect 1 Link Not Detected 0 Normal LOSSSYNC Descrambler Loss of 1 Descrambler Has Lost Synchronization Synchronization 0 Normal Detect CWHRD Codeword Error 1 Invalid 4B5B Revision 1 91 08 18 08 80 DATASHEET Code Detected On Receive Data 0 Normal SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet SSD Start Of Stream Error 1 No Start Of Stream Delimiter Detected on Receive Data 0 Normal ESD End Of Stream Error 1 No End Of Stream Delimiter Detected on Receive Data 0 Normal RPOL Reverse Polarity 1 Reverse Polarity Detect Detected JAB Jabber Detect 1 Jabber Detected 0 Normal SPDDET 100 10 Speed Detect 1 Device in 100Mbps Mode 100BASE TX 0 Device in 10Mbps Mode 10BASE T DPLXDET Duplex Detect 1 Device In Full Duplex 0 Device In Half Duplex Reserved Reserved Reserved for Factory Use 9 9 Register 19 Mask Structure and Bit Definition MINT MLNKFAIL MLOSSSYN MCWRD MSSD MESD MRPOL MJAB RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 MSPDDT MDPLDT Reserved Reserved Reserved Reserved
68. LY 6 POINTER REGISTER BIT PTR HIGH RCV AUTO READ Reserved NOT POINTER HIGH BYTE INGR EMPTY 0 0 0 0 0 0 0 LOW POINTER LOW BYTE 0 0 0 0 0 0 0 0 POINTER REGISTER The value of this register determines the address to be accessed within the transmit or receive areas It will auto increment on accesses to the data register when AUTO INCR is set The increment is by one for every byte access by two for every word access and by four for every double word access When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register READ Determines the type of access to follow If the READ bit is high the operation intended is read If the READ bit is low the operation is write Loading new pointer value with the READ bit high generates a pre fetch into the Data Register for read purposes Readback of the pointer will indicate the value of the address last accessed by the CPU rather than the last pre fetched This allows any interrupt routine that uses the pointer to save it and restore it without affecting the process being interrupted The Pointer Register should not be loaded until the Data Register FIFO is empty The NOT EMPTY bit of this register can be read to determine if the FIFO is empty On reads if ARDY is not connected to the host the Data Register should not be read before 370n
69. MSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet gt ZZ gt 0 4 U 0 6 AN V 0 8 1 0 0 10 20 30 40 50 60 70 80 90 100 10 TIME ns Figure 7 4 TP Output Voltage Template 10 MBPS REFERENCE TIME NS INTERNAL MAU VOLTAGE V 0 0 15 1 0 15 0 4 D 25 0 55 E 32 0 45 F 39 0 G 57 1 0 H 48 0 7 67 0 6 J 89 0 K 74 0 55 L 73 0 55 M 61 0 N 85 1 0 100 0 4 110 0 75 SMSC LAN91C111 REV C 31 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet REFERENCE TIME NS INTERNAL MAU VOLTAGE V Q 111 0 15 R 111 0 5 111 0 15 110 1 0 0 100 0 3 V 110 0 7 90 0 7 Transmit Level Adjust The transmit output current level is derived from an internal reference voltage and the external resistor on RBIAS pin The transmit level can be adjusted with either 1 the external resistor on the RBIAS pin or 2 the four transmit level adjust bits in the PHY MI serial port Configuration 1 register as shown in Table 7 2 The adjustment range is approximately 14 to 16 in 2 steps Table 7 2 Transmit Level Adjust TLVL 3 0 GAIN 0000 1 16 0001 1 14 0010 1 12 0011 1 10
70. Negotiation Outcome Indication The outcome or result of the AutoNegotiation process is stored in the speed detect and duplex detect bits in the PHY MI serial port Status Output register AutoNegotiation Status The status of the AutoNegotiation process can be monitored by reading the AutoNegotiation acknowledgement bit in the MI serial port Status register The MI serial port Status register contains a single AutoNegotiation acknowledgement bit which indicates when an AutoNegotiation has been initiated and successfully completed AutoNegotiation Enable The AutoNegotiation algorithm can be enabled by setting both the ANEG bit in the MAC Receive PHY Control Register and the ANEG bit in the MI PHY Register 0 Control register Clearing either of these two bits will turn off AutoNegotiation mode When the AutoNegotiation algorithm is enabled the SMSC LAN91C111 REV C 39 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet device halts all transmissions including link pulses for 1200 1500 ms enters the Link Fail State and restarts the negotiation process When AutoNegotiation mode is turned on or reset software driver should wait for at least 1500ms to read the ANEG bit in the MI PHY Status Register to determine whether the AutoNegotiation process has been completed When the ANEG bit in the Receive PHY Control Register is cleared AutoNegotiation algorithm is disabled the sel
71. O Read strobe asynchronous read accesses Address is valid combined with before its leading edge Must not be active during DMA bursts if nCMD DMA is supported Latched W R nWR I O Write strobe asynchronous write access Address is valid combined with before leading edge Data latched on trailing edge Must not be nCMD active during DMA bursts if DMA is supported nSTART nADS Address strobe is connected to EISA nSTART RESDRV RESET nBEO nBE1 nBE2 1 nBE2 Byte enables Latched on nADS rising edge nBE3 nBE3 IRQn INTRO Interrupts used as active high edge triggered 031 031 32 bit data bus bus byte s used to access the device function of nBEO nBE3 Double word access Low word access High word access Byte 0 access Byte 1 access Byte 2 access Byte 3 access Not used tri state on reads ignored on writes Note that nBE2 and nBE3 override the value of A1 which is tied low in this application Other combinations of nBE are not supported by the LAN91C111 Software drivers are not anticipated to generate them nEX32 nLDEV nLDEV is a totem pole output nLDEV is active on valid decodes of nNOWS LAN91C111 pins A15 A4 and 0 nNOWS is similar to nLDEV optional additional except that it should go inactive on nSTART rising nNOWS can be logic used to request compressed cycles 1 5 BCLK long nRD nWR will be 1 2 BCLK wide
72. Ohm Load 2 694 3 062 3 429 Vpk 10 Mbps STP Mode 150 Ohm Load Tovs TP Differential Output 98 102 96 100 Mbps Ratio of Positive And Voltage Symmetry Negative Amplitude Peaks on TORF TP Differential Output 3 0 5 0 nS 100 Mbps Rise And Fall Time TRFADJ 1 0 10 TORFS TP Differential Output 0 5 nS 100 Mbps Difference Between Rise Rise And Fall Time and Fall Times on Symmetry ToDC TP Differential Output nS 100 Mbps Output Data 0101 NRZ Duty Cycle Distortion 0 25 Pattern Unscrambled Measure At 50 Points ToJ TP Differential Output 1 4 nS 100 Mbps Output Data scrambled H Jitter Too TP Differential Output 5 0 96 100 Mbps Overshoot TOVT TP Differential Output See Figure 7 4 10 Mbps Voltage Template TSOI TP Differential Output See Figure 7 6 10 Mbps SOI Voltage Template TLPT TP Differential Output See Figure 7 7 10 Mbps NLP and FLP Link Pulse Voltage Template TOIV TP Differential Output 50 mV 10 Mbps Idle Voltage TOIA TP Output Current 38 40 42 mA pk 100 Mbps UTP with TLVL 3 0 1000 31 06 32 66 34 26 100 Mbps STP with TLVL 3 0 1000 88 100 112 mA pk 10 Mbps UTP with TLVL 3 0 1000 71 86 81 64 91 44 mA pk 10 Mbps STP with TLVL 3 0 1000 Revision 1 91 08 18 08 108 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX TOIR TP Output Current 0
73. PO 14 LAN91C111 83 A6 TPO 15 TM 82 AS AVDD 16 81 TPl 17 FEAST 80 TP 18 79 2 AGND 19 128 PIN TOFP 78 nLNK 20 77 VDD LBK 21 76 D nLEDA 22 75 1 9 nLEDB 23 74 010 GND 24 73 DM MDI 25 72 GND MDO 26 D12 MCLK 27 70 D D13 nCNTRL 28 69 5 014 INTRO 29 68 O 015 RESET 30 67 GND nRD O 31 66 O 016 nWR 32 65 O D17 5588588 993995 998580958985808685096 gt gt gt gt CEEFEEEEEEFEEHEEEEEEEEEEEEEEEFEE 50755 gt 2 228 a 2 1 Pin Configuration SMSC LAN91C111 REV C 9 DATASHEET LAN91C111 FEAST 128 PIN TQFP Revision 1 91 08 18 08 EP SMSC 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet XTAL1 XTAL2 VDD nCSOUT 1050 1051 1052 EEDO EEDI EESK EECS AVDD RBIAS AGND TPO TPO AVDD AGND nLNK LBK nLEDA nLEDB GND MDI MDO MCLK nCNTRL INTRO RESET nRD nWR VDD nDATACS nCYCLE W nR RX ER RX DV RXDO RXD1 RXD2 RXD3 VDD CRS100 RX25 Pin Configuration TXEN100 GND TXDO TXD1 TXD2 TXD3 COL100 VDD TX25 GND DO D1 D2 D3 GND D4 D5 128 127 126 125 124 123 122 121
74. PREAMBLE FRAME DATA NIBBLES IDLE DELIM i PRMBLE SFD DATA1 DATA2 _ DATANH DATAN 546 4 62 2BT PREAMBLE 1 0 1 0 62 BITS LONG SFD 1 1 DATAn BETWEEN 64 1518 DATA BYTES IDLE TX EN 0 FIRST BIT MAC s SERIAL BIT STREAM Y LSB Do Di D2 D5 De D7 MSB FIRST SECOND NIBBLE PETE GE NIBBLE RXDO 4 4 MII ASA N BBIE TXD1 RXD1 STREAM TXD2 RXD2 TXD3 RXD3 i Figure 7 2 MII Frame Format amp MII Nibble Order The MII consists of the following signals four transmit data bits TXD 3 0 transmit clock TX25 transmit enable TXEN100 four receive data bits RXD 3 0 receive clock RX25 carrier sense CRS100 receive data valid RX DV receive data error RX ER and collision COL100 Transmit data is clocked out using the TX25 clock input while receive data is clocked in using RX25 The transmit and receive clocks operate at 25 MHz in 100Mbps mode and 2 5 MHz in 10Mbps In 100 Mbps mode the LAN91C111 provides the following interface signals to the PHY For transmission TXEN100 TXDO 3 TX25 For reception RX DV RX ER RXDO 3 RX25 For CSMA CD state machines CRS100 COL100 A transmission begins by TXEN100 going active high and TXDO TXD3 having the first valid preamble nibble TXDO carries the least significant bit of the nibble that is the one that would
75. Pin QFP and 1 0 TQFP package FUNCTION PIN SYMBOLS NUMBER OF PINS System Address Bus 1 15 0 20 System Data Bus DO D31 32 System Control Bus RESET nADS LCLK ARDY 14 nRDYRTN nSRDY INTRO nRD nWR nDATACS nCYCLE W nR nVLBUS Serial EEPROM EEDI EEDO EECS EESK ENEEP 8 IOS0 IOS2 LEDs nLEDA nLEDB 2 PHY TPO TPO TPI nLNK LBK 8 nCNTRL RBIAS Crystal Oscillator XTAL1 XTAL2 2 Power VDD AVDD 10 Ground GND AGND 12 Physical Interface MII TXEN100 CRS100 COL100 RX_DV 18 RX ER TXDO TXD3 RXD0 RXD3 MDI MDO MCLK RX25 TX25 MISC nCSOUT X250UT 2 TOTAL 128 Revision 1 91 08 18 08 14 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSC Chapter 5 Description of Pin Functions PIN NO TQFP QFP NAME SYMBOL BUFFER TYPE DESCRIPTION 81 92 83 94 Address A4 A15 Input Decoded by LAN91C111 to determine access to its registers 78 80 80 82 Address A1 A3 Input Used by LAN91C111 for internal register selection 41 43 Address Enable AEN Input Used as an address qualifier Address decoding is only enabled when AEN is low 94 97 96 99 nByte Enable nBEO nBE3 Input Used during LAN91C111 register accesses to determine the width of the access and the regis
76. ROL 7 JAB 8 SPDDET 9 DPLXDET These bits automatically latch upon changing state and stay latched until they are read When they are read the bits that caused the interrupt to happen are updated to their current value The MDINT bit will be cleared by writing the acknowledge register with MDINT bit set Reserved Must be 0 EPH INT Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions This bit merges exception type of interrupt sources whose service time is not critical to the execution speed of the low level drivers The exact nature of the interrupt can be obtained from the EPH Status Register EPHSR and enabling of these sources can be done via the Control Register The possible sources are LINK Link Test transition CTR ROL Statistics counter roll over TXENA cleared A fatal transmit error occurred forcing TXENA to be cleared TX SUC will be low and the specific reason will be reflected by the bits SQET SQE Error LOST CARR Lost Carrier SMSC LAN91C111 REV C 63 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE LATCOL Late Collision 16COL 16 collisions Datasheet Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register 1 1 LE ENABLE Link Error Enable 2 CR ENABLE Counter Roll Over 3 TE ENABLE Transmit Error Enable EPH INT will only be cleared by t
77. Reserved Reserved RW RW RW RW RW RW RW RW 1 1 0 0 0 0 0 0 Interrupt Mask 1 Mask Interrupt SMSC LAN91C111 REV C Interrupt Detect 0 No Mask 81 DATASHEET For INT In Register 18 Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet MLNKFAIL Interrupt Mask Link 1 Mask Interrupt Fail Detect For LNKFAIL In Register 18 0 No Mask MLOSSSYN Interrupt Mask 1 Mask Interrupt Descrambler Loss For LOSSSYNC In Register 18 of Synchronization 0 No Mask Detect MCWRD Interrupt Mask 1 Mask Interrupt Codeword Error For CWRD In Register 18 0 No Mask MSSD Interrupt Mask Start 1 Mask Interrupt Of Stream Error For SSD In Register 18 0 No Mask MESD Interrupt Mask End Of 1 Mask Interrupt Stream Error For ESD In Register 18 0 No Mask MRPOL Interrupt Mask 1 Mask Interrupt Reverse Polarity For RPOL In Detect Register 18 0 No Mask MJAB Interrupt Mask Jabber 1 Mask Interrupt Detect For JAB In Register 18 0 No Mask MSPDDT Interrupt Mask 100 10 1 Mask Interrupt Speed Detect For SPDDET In Register 18 0 No Mask MDPLDT Interrupt Mask Duplex 1 Mask Interrupt Detect For DPLXDET In Register 18 0 No Mask Reserved Reserved Reserved for Factory Use 9 10 Register 20 Reserved Structure and Bit Definition Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0
78. SE REG 011 Ch CONFIGURATION REG Dh BASE REG 100 10h CONFIGURATION REG 11h BASE REG 101 14h CONFIGURATION REG 15h BASE REG 110 18h CONFIGURATION REG 19h BASE REG XXX 20h IAO 1 21h 1 2 3 22h 1 4 5 11 1 64 16 Serial SMSC LAN91C111 REV C 97 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet Chapter 12 Application Considerations The LAN91C111 is envisioned to fit a few different bus types This section describes the basic guidelines system level implications and sample configurations for the most relevant bus types All applications are based on buffered architectures with private SRAM bus FAST ETHERNET SLAVE ADAPTER Slave non intelligent board implementing 100 Mbps and 10 Mbps speeds Adapter requires 1 LAN91C111 chip 2 Serial EEPROM 93046 3 Some bus specific glue logic Target systems 1 VL Local Bus 32 bit systems 2 High end ISA or non burst EISA machines 3 EISA 32 bit slave VL Local Bus 32 Bit Systems VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as 32 bit peripheral in terms of the bus interface All registers except the DATA REGISTER will be accessed using byte or word instructions Accesses to the DATA REGISTER could use byte word or dword instructions Table 12 1 VL Local Bus Signal Connections VL
79. SMSC SUCCESS BY DESIGN PRODUCT FEATURES LAN91C111 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Single Chip Ethernet Controller Dual Speed 10 100 Mbps Fully Supports Full Duplex Switched Ethernet a Supports Burst Data Transfer 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM Interface Supports 8 16 and 32 Bit CPU Accesses Internal 32 Bit Wide Data Path Into Packet Buffer Memory Built in Transparent Arbitration for Slave Sequential Access Architecture Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues 3 3V Operation with 5V Tolerant Buffers See Pin List Description for Additional Details Single 25 MHz Reference Clock for Both PHY and External 25Mhz output for an external PHY supporting PHYs physical media Low Power CMOS Design Supports Multiple Embedded Processor Host Interfaces ARM SH Power PC Coldfire 680X0 683XX MIPS R3000 3 3V MII Media Independent Interface MAC PHY Interface Running at Nibble Rate Management Serial Interface 128 Pin QFP package lead free RoHS compliant package also available 128 Pin TQFP package 1 0 mm height lead free RoHS compliant package also available Commercial Temperature Range from 0 C to 70 C LAN91C111 Industrial Temperature Range f
80. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice Contact your local SMSC sales office to obtain the latest specifications before placing your product order The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC s standard Terms of Sale Agreement dated before the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval of an Officer of SMSC and further testing and or modification will be fully at the risk of the customer Copies of this document or other SMSC literature as well as the Terms of Sale Agreement may be obtained by visiting SMSC s website at http www smsc com SMSC is a registered trademark of Standard Microsystems Corporation SMSC Product names and company names are the trad
81. SOI Pulse Width to 4500 nS 10Mbps 40mV t34 LEDn Delay Time 25 mS t35 LEDn Pulse Width 80 105 mS 100Mbps LEDn TXEN Bit is Set Revision 1 91 08 18 08 Figure 14 11 Transmit Timing 118 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC EP SMSE Datasheet Table 14 2 Receive Timing Characteristics LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX 136 Receive Input Jitter 3 0 nS 100Mbps 13 5 NS pk pk 10Mbps 137 SOI Pulse Minimum Width 125 200 nS 10Mbps Required for Idle Detection Measure TPI from last zero cross to 0 3V point 136 137 Figure 14 12 Receive Timing End of Packet 10 MBPS Table 14 3 Collision and Jam Timing Characteristics LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX 138 Rcv Packet Start to COL 200 nS 100Mbps Assert Time 700 nS 10Mbps 300 nS 10Mbps t39 Xmt Packet Start to COL 200 nS 100Mbps Assert Time 700 nS 10Mbps t40 Start of Packet to Transmit 500 nS 100Mbps JAM Packet Start During JAM 1500 nS 10Mbps t41 Xmt Packet Start to COL 200 nS 100Mbps Assert Time 700 nS 10Mbps SMSC LAN91C111 REV C 119 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet MII 100 Mbps 0 2 2
82. STER On EEPROM write operations after setting the STORE bit the value of the GENERAL PURPOSE REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits RELOAD and STORE are set by the user to initiate read and write operations respectively Polling the value until read low is used to determine completion When an EEPROM access is in progress the SMSC LAN91C111 REV C 95 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP smsc Datasheet STORE and RELOAD bits of CTR will readback as both bits high No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear This mechanism is also valid for reset initiated reloads Note If no EEPROM is connected to the LAN91C111 for example for some embedded applications the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted Configuration Base and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value Revision 1 91 08 18 08 96 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC EP SMSE Datasheet 16 BITS 10S2 0 WORD ADDRESS 000 Oh CONFIGURATION REG th BASE REG 001 4h CONFIGURATION REG 5h BASE REG 010 8h CONFIGURATION REG 9h BA
83. THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE C BURST CYCLES BCLK LCLK EISA Bus Clock Data transfer clock for DMA bursts nDAK n nDATACS DMA Acknowledge Active during Slave DMA cycles Used by the LAN91C111 as nDATACS direct access to data path nlORC W nR Indicates the direction and timing of the DMA cycles High during LAN91C111 writes low during LAN91C111 reads nlOWC nCYCLE Indicates slave DMA writes nEXRDY nRDYRTN EISA bus signal indicating whether a slave DMA cycle will take place on the next BCLK rising edge or should be postponed nRDYRTN is used as an input in the slave DMA mode to bring in EXRDY UNUSED PINS VOC nVLBUS SMSC LAN91C111 REV C 103 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Table 12 3 EISA 32 Bit Slave Signal Connections continued EISA BUS LAN91C111 SIGNAL SIGNAL NOTES GND A1 EISA BUS LA2 LA15 A2 A15 RESET RESET AEN JAN M nlO DO D31 D0 D31 IRQn INTRO LAN91C111 nBE 0 3 nBE 0 3 nCMD LATCH nRD nWR gates nWR nSTART nADS nLDEV nEX32 oc Figure 12 3 LAN91C111 on EISA BUS Revision 1 91 08 18 08 104 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE Chapter 13 Operational Description 13 1 Maximum Guaranteed Ratings Operating Temperature Range Storage Temperature R
84. UP 0 MDO MII Management output The value of this bit drives the MDO pin MDI MII Management input The value of the MDI pin is readable using this bit MDCLK MII Management clock The value of this bit drives the MDCLK pin MDOE MII Management output enable When high pin MDO is driven when low pin MDO is tri stated The purpose of this interface along with the corresponding pins is to implement MII PHY management in software 8 24 Bank 3 Revision Register OFFSET NAME TYPE SYMBOL A REVISION REGISTER READ ONLY REV HIGH BYTE 0 0 1 1 0 0 1 1 LOW CHIP REV BYTE 1 0 0 1 0 0 1 0 CHIP Chip ID Can be used by software drivers to identify the device used REV Revision ID Incremented for each revision of a given device SMSC LAN91C111 REV C 67 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet 8 25 Bank 3 RCV Register OFFSET NAME TYPE SYMBOL C RCV REGISTER READ WRITE RCV HIGH Reserved BYTE 0 0 0 0 0 0 0 0 LOW RCV Reserved Reserved MBO MBO MBO MBO MBO BYTE DISCRD 0 0 0 1 1 1 1 1 RCV DISCRD Set to discard a packet being received Will discard packets only in the process of being received When set prior to the end of receive packet bit 4 RKOVRN of the interrupt status register will be s
85. also determines the value of the transmit and receive interrupts as a function of the queues The page size is 2048 bytes with a maximum memory size of 8kbytes MIR values are interpreted in 2048 byte units Revision 1 91 08 18 08 20 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet 7 4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses different signals are used for each one Transparent latches are added on the address path using rising nADS for latching When working with an asynchronous bus like ISA the read and write operations are controlled by the edges of nRD and nWR ARDY is used for notifying the system that it should extend the access cycle The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C111 clock and therefore asynchronous to the bus In the synchronous VL Bus type mode nCYCLE and LCLK are used to for read and write operations Completion of the cycle may be determined by using nSRDY nSRDY is controlled by LCLK and synchronous to the bus Direct 32 bit access to the Data Path is supported by using the nDATACS input By asserting nDATACS external DMA type of devices will bypass the BIU address decoders and can sequentially access memory with no CPU intervention nDATACS accesses can be used in the EISA DMA burst mode nVLBUS 1 or in async
86. and they are also indicated in the serial port by setting SSD ESD and codeword error bits in the PHY MI serial port Status Output register Manchester Decoder 10 Mbps In Manchester coded data the first half of the data bit contains the complement of the data and the second half of the data bit contains the true data The Manchester decoder in the LAN91C111 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI pulse Since the clock and data recovery block has already separated the clock and data from the TP receiver the Manchester decoding process to NRZ data is inherently performed by that block Revision 1 91 08 18 08 28 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet 7 7 4 Clock and Data Recovery Clock Recovery 100 Mbps Clock recovery is done with PLL If there is no valid data present on the TP inputs the PLL is locked to the 25 MHz TX25 When valid data is detected on the TP inputs with the squelch circuit and when the adaptive equalizer has settled the PLL input is switched to the incoming data on the TP input The PLL then recovers a clock by locking onto the transitions of the incoming signal from the twisted pair wire The recovered dock frequency is a 25 MHz nibble dock and that clock is outputted on the controller interface signal RX25 Data Recovery 100 Mbps
87. ange Lead Temperature Range soldering 10 seconds Positive Voltage on any pin with respect to Ground Negative Voltage on any pin with respect to Ground Maximum 09 to 70 C for LAN91C111 40 C to 85 C for LAN91C1111 55C to 4 150 C 325 4 0 3V 0 3V 45V Stresses above those listed above could cause permanent damage to the device This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied Note When powering this device from laboratory or system power supplies it is important that the Absolute Maximum Ratings not be exceeded or device failure can result Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used 13 2 DC Electrical Characteristics Vcc 3 3 0 V 10 PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS Type Input Buffer Low Input Level 0 8 V TTL Levels High Input Level 2 0 V IS Type Input Buffer Low Input Level Vius 0 8 V Schmitt Trigger High Input Level VIHIS 2 2 V Schmitt Trigger Schmitt Trigger Hysteresis Vuys 250 mV Input Buffer Low Input Level Vil ck 0 8 V High Input Level 2 2 V SMSC LAN
88. atasheet PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS 1 024 Type Buffer Low Output Level VoL 0 4 V lo 35 mA High Output Level Vou 2 4 V 15 mA Output Leakage 10 10 Vin 0 to Veg l OD Type Buffer Low Output Level VoL 0 4 V lol 4 mA High Output Level Vou 24 V na Output Leakage 10 10 Vin 0 to Voc Supply Current Active Dynamic Current loc 100 140 mA Assuming internal PHY is used Powerdown Supply Current IPDN 15 38 mA Internal PHY in Powerdown mode 14 36 mA Internal MAC PHY in Powerdown mode CAPACITANCE Ta 25 C 1MHz Vcc 3 3V LIMITS PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION Clock Input Capacitance Cin 20 pF All pins except pin under test tied to AC ground Input Capacitance 10 Output Capacitance Cour 20 pF CAPACITIVE LOAD ON OUTPUTS ARDY D0 D31 non VLBUS 45 pF D0 D31 in VLBUS 45 pF All other outputs 45 pF SMSC LAN91C111 REV C 107 Revision 1 91 08 18 08 DATASHEET EP SMSE 13 3 Twisted Pair Characteristics Transmit VDD 3 3v 5 RBIAS 11K 1 no load 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet LIMIT SYM PARAMETER UNIT CONDITIONS MIN TYP MAX Tov TP Differential Output 0 950 1 000 1 050 Vpk 100 Mbps UTP Mode Voltage 100 Ohm Load 1 165 1 225 1 285 Vpk 100 Mbps STP Mode 150 Ohm Load 2 2 2 5 2 8 Vpk 10 Mbps UTP Mode 100
89. blish an active link to and from a remote device There are different standard link integrity algorithms for 10 and 100 Mbps modes The AutoNegotiation algorithm is used for two purposes 1 To automatically configure the device for either 10 100 Mbps Half Full Duplex modes and 2 to establish an active link to and from a remote device The standard link integrity and AutoNegotiation algorithms are described below AutoNegotiation is only specified for 100BASE TX and 10BASE T operation 10BASE T Link Integrity Algorithm 10Mbps The LAN91C111 uses the same 10BASE T link integrity algorithm that is defined in IEEE 802 3 Clause 14 This algorithm uses normal link pulses referred to as NLP s and transmitted during idle periods to determine if a device has successfully established a link with a remote device called Link Pass State The transmit link pulse meets the template defined in IEEE 802 3 Clause 14 and shown in Figure 7 7 Refer to IEEE 802 3 Clause 14 for more details if needed SMSC LAN91C111 REV C 37 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet 0 85 20 BT BT Figure 7 7 Link Pulse Output Voltage Template NLP FLP 100BASE TX Link Integrity Algorithm 100Mbps Since 100BASE TX is defined to have an active idle signal then there is no need to have separate link pulses like those defined for 10BASE T The LAN91C111 uses the squelch criteria and d
90. can be bypassed by setting the bypass scrambler descrambler bit in the PHY MI serial port Configuration 1 register When this bit is set the data bypasses the descrambler and goes directly from the TP receiver to the 4B5B decoder 7 7 7 Twisted Pair Transmitter Transmitter 100 Mbps The TX transmitter consists of MLT 3 encoder waveform generator and line driver The MLT 3 encoder converts the NRZ data from the scrambler into a three level MLT 3 code required by IEEE 802 3 MLT 3 coding uses three levels and converts 1 s to transitions between the three levels and converts 0 s to no transitions or changes in level The purpose of the waveform generator is to shape the transmit output pulse The waveform generator takes the MLT 3 three level encoded waveform and uses an array of switched current sources to control the rise fall time and level of the signal at the Output The output of the switched current sources then goes through a low pass filter in order to smooth the current output and remove any high frequency components In this way the waveform generator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE 802 3 The waveform generator eliminates the need for any external filters on the TP transmit output The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category 5 unshielded twisted pair cable or 150 Ohm sh
91. ce routine to process many receive packets without exiting or one at a time if the ISR just returns after processing and removing one There are two types of transmit interrupt strategies 1 One interrupt per packet 2 One interrupt per sequence of packets The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used TX INT bit Set whenever the TX completion FIFO is not empty TX EMPTY INT bit Set whenever the TX FIFO is empty AUTO RELEASE When set successful transmit packets are not written into completion FIFO and their memory is released automatically 1 One interrupt per packet enable TX INT set AUTO RELEASE 0 The software driver can find the completion result in memory and process the interrupt one packet at a time Depending on the completion code the driver will take different actions Note that the transmit process is working in parallel and other transmissions might be taking place The LAN91C111 is virtually queuing the packet numbers and their status words In this case the transmit interrupt service routine can find the next packet number to be serviced by reading the TX FIFO PACKET NUMBER at the FIFO PORTS register This eliminates the need for the driver to keep a list of packet numbers being transmitted The numbers are queued by the LAN91C111 and provided back to the CPU as their transmission completes 2 One interrupt per sequence of packets Enable TX EMPTY INT and TX INT s
92. ceive Clock RX25 with Input Receive clock input from MII PHY pullup Nibble rate clock 25MHz for 100Mbps amp 2 5MHz for 10Mbps 121 124 123 126 Receive Data RXD3 I with Inputs Received Data nibble from MII RXDO pullup PHY 25 27 Management MDI I with MII management data input Data Input pulldown 26 28 Management MDO 04 MII management data output Data Output 27 29 Management MCLK 04 MII management clock Clock 126 128 Receive Error RX ER I with Input Indicates code error detected by pulldown PHY Used by the LAN91C111 to discard the packet being received The error indication reported for this event is the same as a bad CRC Receive Status Word bit 13 2 4 nChip Select nCSOUT O4 Output Chip Select provided for Output mapping of PHY functions into LAN91C111 decoded space Active on accesses to LAN91C111 s eight lower addresses when the BANK SELECTED is 7 12 14 RBIAS NA Transmit Current Set An external Resistor resistor connected between this pin and GND will set the output current for the TP transmit outputs 14 16 TPO Twisted Pair Transmit Output Positive 15 17 TPO Twisted Pair Transmit Output Negative 17 19 TPl Twisted Pair Receive Input Positive 18 20 TPI Twisted Receive Input Negative 22 24 nLEDA OD24 PHY LED Output 23 25 nLEDB OD24 PHY LED Output Note 5 1 If the EEPROM is enabled Revision 1 91 08 18 08 18 SMSC LAN91C111 REV C DATASHEET 10 100 E
93. cleared The time from issuing REMOVE and RELEASE command on the last receive packet to the time when receive FIFO is empty depends on RX INT bit turning low An alternate approach can be checking the read RX FIFO register 101 5 RELEASE SPECIFIC PACKET Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER Should not be used for frames pending transmission Typically used to remove transmitted frames after reading their completion status Can be used following 3 to release receive packet memory in a more flexible way than 4 Revision 1 91 08 18 08 58 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet OPERATION DECIMAL CODE VALUE COMMAND 110 6 ENQUEUE PACKET NUMBER INTO TX FIFO This is the normal method of transmitting a packet just loaded into RAM The packet number to be enqueued is taken from the PACKET NUMBER REGISTER 111 7 RESET TX FIFOs This command will reset both TX FIFOs The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO This command provides a mechanism for canceling packet transmissions and reordering or bypassing the transmit queue The RESET TX FIFOs command should only be used when the transmitter is disabled Unlike the RESET MMU command the RESET TX FIFOs does not release any memory Note When using the RESET TX FIFOS command the CPU is responsible for releasing th
94. cted 0 1 1 nPLED1 Full Duplex Mode enabled 1 0 0 nPLED2 Transmit or Receive packet occurred 1 0 1 nPLED3 100Mbps Link detected 1 1 0 nPLED4 Receive packet occurred nPLED5 Transmit packet occurred SMSC LAN91C111 REV 53 Revision 1 91 08 18 08 DATASHEET EP SMSE Reserved Must be 0 8 11 10 100 Non PCI Ethernet Single Chip MAC PHY Bank 1 Configuration Register OFFSET NAME CONFIGURATION REGISTER TYPE SYMBOL READ WRITE CR Datasheet The Configuration Register holds bits that define the adapter configuration and are not expected to change during run time This register is part of the EEPROM saved setup HIGH BYTE EPH Power EN Reserved Reserved NO WAIT Reserved GPCNTRL EXT PHY Reserved 1 0 0 0 0 0 LOW BYTE Reserved Reserved Reserved Reserved Reserved Reserved Revision 1 91 08 18 08 54 EPH Power EN Used to selectively power transition the EPH to low power mode When this bit is cleared 0 the Host will place the EPH into low power mode The Ethernet MAC will gate the 25Mhz TX and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets The Host interface however will still be active allowing the Host access to the device through Standard IO access All LAN91C111 registers will still be accessible
95. d transmit data at internal MII is looped back onto receive data output at internal MII transmit enable signal is looped back onto carrier sense output at internal the TP receive and transmit paths are disabled the transmit link pulses are halted and the Half Full Duplex modes do not change 7 7 17 PHY Powerdown The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY MI serial port Control register In powerdown mode the TP outputs are in high impedance state all functions are disabled except the PHY MI serial port and the power consumption is reduced to a minimum To restore PHY to normal power mode set the bit in PHY MI Register 0 to 0 The PHY is then in isolation mode MII DIS bit is set This MII DIS bit is needed to be cleared The device is guaranteed to be ready for normal operation 500mS after powerdown is de asserted 7 7 18 PHY Interrupt The LAN91C111 PHY has interrupt capability The interrupt is triggered by certain output status bits also referred to as interrupt bits in the serial port R LT bits are read bits that latch on transition SMSC LAN91C111 REV C 41 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE R LT bits are also interrupt bits if they are not masked out with the Mask register bits Interrupt bits automatically latch themselves into their register locations and assert the interrupt indication when they change
96. ddress mapping ADDRESS HASH VALUE 5 0 MULTICAST TABLE BIT ED 00 00 00 00 00 000 000 MT 0 bit 0 OD 00 00 00 00 00 010 000 MT 2 bit 0 01 00 00 00 00 00 100 111 MT 4 bit 7 2F 00 00 00 00 00 111 111 MT 7 bit 7 MULTCAST Receive frame was multicast If hash value corresponds to a multicast table bit that is set and the address was a multicast the packet will pass address filtering regardless of other filtering criteria 8 3 Space The base I O space is determined by the IOSO IOS2 inputs and the EEPROM contents To limit the space requirements to 16 locations the registers are assigned to different banks The last word of the area is shared by all banks and can be used to change the bank in use Registers are described using the following convention OFFSET NAME TYPE SYMBOL HIGH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 BYTE X X X X X X X X LOW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BYTE X X X X X X X X FFSET Defines the address offset within the IOBASE where the register can be accessed at provided the bank select has the appropriate value The offset specifies the address of the even byte bits 0 7 or the address of the complete word The odd byte can be accessed using address offset 1 Some registers like the Interrupt Ack or like Interrupt Mask are functionally described as two eight bit registers in that case the offset of each o
97. ded The Host interface is an 8 16 or 32 bit wide address data bus with extensions for 32 16 and 8 bit embedded RISC and ARM processors The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10 100 Ethernet Physical layer framer to the internal MAC Revision 1 91 08 18 08 12 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet MII External Signals RBIAS EEPROM CONTROL 100BASE TX TRANSMITTER SWITCHED TPO 4B5B MLT3 1 LP gt T TX ER TXEN100 TX25 2 10BASE T TRANSMITTER o T E i hannes x MANCHESTER ui z a o 3 ae 011009 OLLISION ae ona 25225 52 o o Rxpisd HEX ER RX DV pif ees 100BASE TX RECEIVER CLOCK amp ADAPTIVE TPl DATA QUALIZER M TPI RECOVERY 0 10BASE T RECEIVER Recovery Manchester 0 LED Power PHY AUTONEG On CONTROLS Logic Reset LED D U CED Control Lases Figure 3 3 LAN91C111 Physical Layer to Internal MAC Block Diagram SMSC LAN91C111 REV C 13 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Chapter 4 Signal Descriptions Datasheet Table 4 1 LAN91C111 Pin Requirements 128
98. dress filter regardless of the source for the frame When clear the node will not receive a frame sourced by itself This bit does not control the duplex mode operation the duplex mode operation is controlled by the SWFDUP bit MON CSN When set the LAN91C111 monitors carrier while transmitting It must see its own carrier by the end of the preamble If it is not seen or if carrier is lost during transmission the transmitter aborts the frame without CRC and turns itself off and sets the LOST CARR bit in the EPHSR When this bit is clear the transmitter ignores its own carrier Defaults low Should be 0 for MII operation NOCRC Does not append CRC to transmitted frames when set Allows software to insert the desired CRC Defaults to zero namely CRC inserted PAD EN When set the LAN91C111 will pad transmit frames shorter than 64 bytes with 00 For TX CPU should write the actual BYTE COUNT before padded by the LAN91C111 to the buffer RAM excludes the padded 00 When this bit is cleared the LAN91C111 does not pad frames Revision 1 91 08 18 08 DATASHEET SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet FORCOL When set the FORCOL bit will force collision by not deferring deliberately This bit is set and cleared only by the CPU When TXENA is enabled with no packets in the queue and while the FORCOL bit is set the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the lin
99. e If a packet is queued a preamble and SFD will be transmitted This bit defaults low to normal operation NOTE The LATCOL bit in the EPHSR setting up as a result of FORCOL will reset TXENA to 0 In order to force another collision TXENA must be set to 1 again LOOP Loopback General purpose output port used to control the LBK pin Typically used to put the PHY chip in loopback mode TXENA Transmit enabled when set Transmit is disabled if clear When the bit is cleared the LAN91C111 will complete the current transmission before stopping When stopping due to an error this bit is automatically cleared 8 6 Bank 0 EPH Status Register OFFSET NAME TYPE SYMBOL 2 EPH STATUS REGISTER READ ONLY EPHSR This register stores the status of the last transmitted frame This register value upon individual transmit packet completion is stored as the first word in the memory area allocated to the packet Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions The register can be used for real time values like TXENA and LINK OK If TXENA is cleared the register holds the last packet completion status HIGH Reserved LINK Reserved CTR EXC LOST LATCOL Reserved BYTE OK ROL DEF CARR 0 nLNK pin 0 0 0 0 0 0 LOW TX LTX SQET 16COL LTX MUL SNGL TX SUC BYTE DEFR BRD MULT COL COL 0 0 0 0 0 0 0 0 LINK OK General purpose input port dr
100. e Chip MAC PHY Datasheet 7 7 1 7 7 2 7 7 3 EP sSmsc 10Mbps operation is similar to the 100Mbps TX operation except 1 there is no scrambler descrambler 2 the encoder decoder is Manchester instead of 4B5B 3 the data rate is 10Mbps instead of 100Mbps and 4 the twisted pair symbol data is two level Manchester instead of ternary MLT 3 The Management Interface hereafter referred to as the MI serial port is a two pin bi directional link through which configuration inputs can be set and status outputs can be read Each block plus the operating modes are described in more detail in the following sections MII Disable The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control register When the MII is disabled the MII inputs are ignored the MII outputs are placed in high impedance state and the TP output is high impedance Encoder 4B5B Encoder 100 Mbps 100BASE TX requires that the data be 4B5B encoded 4B5B coding converts the 4 Bit data nibbles into 5 Bit date code words The mapping of the 4B nibbles to the 5B code words is specified in IEEE 802 3 The 4B5B encoder on the LAN91C111 takes 4B nibbles from the controller interface converts them into 5B words and sends the 5B words to the scrambler The 4B5B encoder also substitutes the first 8 bits of the preamble with the SSD delimiters a k a J K symbols and adds an ESD delimiter MR symbols to the
101. e IEEE 802 3 Physical Layer PHY and Media Access Control MAC into the same silicon The data path connection between the MAC and the internal PHY is provided by the internal The LAN91C111 also supports the EXT PHY mode for the use of an external PHY such as HPNA This mode isolates the internal PHY to allow interface with an external PHY through the MII pins To enter this mode set EXT PHY bit to 1 in the Configuration Register 7 5 1 Management Data Software Implementation The MII interface contains of a pair of signals that physically transport the management information across the a frame format and a protocol specification for exchanging management frames and a register set that can be read and written using these frames MII management refers to the ability of a management entity to communicate with PHY via the MII serial management interface MI for the purpose of displaying selecting and or controlling different PHY options The host manipulates the MAC to drive the MII management serial interface By manipulating the MAC s registers MII management frames are generated on the management interface for reading or writing information from the PHY registers Timing and framing for each management command is to be generated by the CPU host SMSC LAN91C111 REV C 21 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE and external PHY communicate via MDIO and M
102. e Input 1 Receive Squelch Levels Reduced By 4 5 dB R W Level Adjust 0 Normal TLVLO 3 Transmit Output See Table 7 2 Level Adjust TRFO 1 Transmitter 11 0 25nS Rise Fall Time 10 0 0nS Adjust 01 0 25nS 00 0 50nS 9 7 Register 17 Configuration 2 Structure and Bit Definition Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R R R R R R R R 1 1 1 1 1 1 1 1 Reserved Reserved APOLDIS JABDIS MREG INTMDIO Reserved Reserved R R RW RW RW RW RW RW 0 0 0 0 0 0 0 0 APOLDIS Auto Polarity 1 Auto 1 Auto Disable Polarity Polarity Correction Correction Function Function Disabled Disabled 0 Normal 0 Normal JABDIS Jabber Disable 1 Jabber 1 Jabber Select Disabled RW Disabled 0 Enabled 0 Enabled MREG Multiple Register 1 Multiple Access Enable Register Access Enabled 5 5 LAN91C111 REV C 79 Revision 1 91 08 18 08 DATASHEET EP SMSE INTMDIO Reserved 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet 0 No Multiple 0 Register Access Multiple Register Access Interrupt 1 Interrupt 1 Interrupt Scheme Select Signaled With Signaled MDIO Pulse With MDIO During Idle Pulse During Idle 0 Interrupt 0 Interrupt Not Signaled Not Signaled On MDIO On MDIO Reserved for Factory Use 9 8 Register 18 Status Output Structure and Bit Definition INT LNKFAIL LOSSSYNC CWRD SSD ESD RPOL JAB R R
103. e memory associated with outstanding packets or re enqueuing them Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command a MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it COMMAND SEQUENCING second allocate command command 1 should not be issued until the present one has completed Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt A second release command commands 4 5 should not be issued if the previous one is still being processed The BUSY bit indicates that a release command is in progress After issuing command 5 the contents of the PNR should not be changed until BUSY goes low After issuing command 4 command 3 should not be issued until BUSY goes low BUSY Readable at bit 0 of the MMU command register address When set indicates that MMU is still processing a release command When clear MMU has already completed last release command BUSY and FAILED bits are set upon the trailing edge of command 8 17 Bank 2 Packet Number Register OFFSET NAME TYPE SYMBOL PACKET NUMBER 2 REGISTER READ WRITE PNR Reserved Reserved PACKET NUMBER AT TX AREA 0 0 0 0 0 0 0 0 PACKET NUMBER AT TX AREA The value written into this register determines which packet number is accessible through t
104. earing the EXT PHY bit in the Configuration Register ANEG RST Auto Negotiation Reset This bit will return 0 if the PHY does not support ANEG or if ANEG is disabled through the ANEG EN bit If neither of the previous is true setting this bit to 1 resets the ANEG process This bit is self clearing and the PHY will return a 1 until ANEG is initiated writing a 0 does not affect the ANEG process Revision 1 91 08 18 08 74 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet DPLX Duplex mode When Auto Negotiation is disabled this bit can be used to manually select the link duplex state Writing 1 to this bit selects full duplex while a 0 selects half duplex When Auto Negotiation is enabled reading or writing this bit has no effect COLTST Collision test Setting a 1 allows for testing of the MII COL signal 0 allows normal operation Reserved Reserved Must be 0 for Proper Operation 9 2 Register 1 Status Register CAP 4 CAP TXF CAP TXH CAP TF CAP TH Reserved Reserved Reserved R R R R R R R R 0 1 1 1 1 0 0 0 Reserved CAP SUPR ANEG ACK REM FLT CAP ANEG LINK JAB EXREG R R R R LH R R LL R LH R 0 0 0 0 1 0 0 1 4 100BASE T4 Capable 1 Indicates 100Base T4 capable PHY 0 not capable CAP TXF 100BASE TX Full Duplex Capable 1 Indicates 100Ba
105. ection of 10 100 Mbps mode and duplex mode is determined by the SPEED bit and the DPLX bit in the MAC Receive PHY Control register When the ANEG bit in the Receive PHY Control Register is set and the ANEG EN bit in the MI PHY Register 0 Control Register is cleared AutoNegotiation algorithm is disabled the selection of 10 100 Mbps mode and duplex mode is determined by the SPEED bit and the DPLX bit in the MI PHY Register 0 Control Register AutoNegotiation Reset The AutoNegotiation algorithm can be initiated at any time by setting the AutoNegotiation reset bit in the PHY MI serial port Control register Link Disable The link integrity function can be disabled by setting the link disable bit in the PHY MI serial port Configuration 1 register When the link integrity function is disabled the device is forced into the Link Pass state configures itself for Half Full Duplex based on the value of the duplex bit in the PHY MI serial port Control register configures itself for 100 10 Mbps operation based on the values of the speed bit in the MI serial port Control register and continues to transmit NLP S or TX idle patterns depending on whether the device is in 10 or 100 Mbps mode 7 7 13 Jabber 100 Mbps Jabber function is disabled in the 100 Mbps mode 10 Mbps Jabber condition occurs when the transmit packet exceeds a predetermined length When jabber is detected the TP transmit outputs are forced to the idle state collision is asserted a
106. egister Write the Pointer Register then use a block move operation from the upper layer transmit queue into the Data Register ISSUE ENQUEUE PACKET NUMBER TO TX FIFO This command writes the number present in the Packet Number Register into the TX FIFO The transmission is now enqueued No further CPU intervention is needed until a transmit interrupt is generated The enqueued packet will be transferred to the MAC block as a function of TXENA nTCR bit and of the deferral process 1 2 duplex mode only state SMSC LAN91C111 REV C 85 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet S W DRIVER MAC SIDE 6 Upon transmit completion the first word in memory is written with the status word The packet number is moved from the TX FIFO into the TX completion FIFO Interrupt is generated by the TX completion FIFO being not empty If a TX failure occurs on any packets TX INT is generated and TXENA is cleared transmission sequence stops The packet number of the failure packet is presented at the TX FIFO PORTS Register 7 SERVICE INTERRUPT Read Interrupt Status Register If it is a transmit interrupt read the TX FIFO Packet Number from the FIFO Ports Register Write the packet number into the Packet Number Register The corresponding status word is now readable from memory If status word shows successful transmission issue RELE
107. eiver and MI serial port The LAN91C111 can operate as a 100BASE TX device hereafter referred to as 100Mbps mode or as a 10BASE T device hereafter referred to as 10Mbps mode The difference between the 100Mbps mode and the 10Mbps mode is data rate signaling protocol and allowed wiring The 100Mbps TX mode uses two pairs of category 5 or better UTP or STP twisted pair cable with 4B5B encoded scrambled and MLT 3 coded 62 5 MHz ternary data to achieve a throughput of 100Mbps The 10Mbps mode uses two pairs of category 3 or better UTP or STP twisted pair cable with Manchester encoded 10MHz binary data to achieve a 10Mbps throughput The data symbol format on the twisted pair cable for the 100 and 10Mbps modes are defined in IEEE 802 3 specifications and shown in Figure 7 3 SMSC LAN91C111 REV C 25 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip PHY SMSC Deaton INTERFRAME FRAME INTERFRAME GAP ETHERNET MAC PREAMBLE SFD DA SA LN LLC DATA FCS GAP 100 BASE TX DATA SYMBOLS IDLE SSD PREAMBLE SFD DA SA LLGDATA FOS ESD IDLE IDLE IDLE 1111 SSD 110001000 1 BEFORE AFTER PREAMBLE 1 0 1 0 62 BITS LONG 4B5B ENCODING SFD 1 1 SCRAMBLING DA SA LN LLC DATA FCS DATA AND MLT3 Esp 0110100111 CODING I 10 BASE T DATA SYMBOLS PREAMBLE stb DA s LN uc DATA FCS sol IDLE IDLE 2
108. emarks of their respective holders SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND AGAINST INFRINGEMENT AND THE LIKE AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT INCIDENTAL INDIRECT SPECIAL PUNITIVE OR CONSEQUENTIAL DAMAGES OR FOR LOST DATA PROFITS SAVINGS OR REVENUES OF ANY KIND REGARDLESS OF THE FORM OF ACTION WHETHER BASED ON CONTRACT TORT NEGLIGENCE OF SMSC OR OTHERS STRICT LIABILITY BREACH OF WARRANTY OR OTHERWISE WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Revision 1 91 08 18 08 2 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip PHY Datasheet Table of Contents Chapter 1 General 8 Chapter 2 Pin 9 Chapter 3 Block 5 5 555 11 Chapter 4 Signal Descriptions 14 Chapter 5 Description of Pin 15 Chapter 6 Signal Description
109. en transmit and receive resources The MMU allocates and de allocates memory upon different events An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation Memory is always requested by the side that needs to write into it that is the CPU for transmit or the MAC for receive The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand Furthermore the receive process requests will be dependent on network traffic in particular on the arrival of broadcast and Revision 1 91 08 18 08 92 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE multicast packets that might not be for the node and that are not subject to upper layer software flow control INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller For that purpose there is no register reading necessary before the next element in the queue namely transmit or receive packet can be handled by the controller The transmit and receive results are placed in memory The receive interrupt will be generated when the receive queue FIFO of packets is not empty and receive interrupts are enabled This allows the interrupt servi
110. end of every packet as defined in IEEE 802 3 The 4B5B encoder also fills the period between packets called the idle period with the continuous stream of idle symbols Manchester Encoder 10 Mbps The Manchester encoding process combines clock and NRZ data such that the first half of the data bit contains the complement of the data and the second half of the data bit contains the true data as specified in IEEE 802 3 This guarantees that a transition always occurs in the middle of the bit call The Manchester encoder on the LAN91C111 converts the 10Mbps NRZ data from the controller interface into a Manchester Encoded data stream for the TP transmitter and adds a start of idle pulse SOI at the end of the packet as specified in IEEE 802 3 The Manchester encoding process is only done on actual packet data and the idle period between packets is not Manchester encoded and filled with link pulses Decoder 4B5B Decoder 100 Mbps Since the TP input data is 4B5B encoded on the transmit side it must also be decoded by the 4B5B decoder on the receive side The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802 3 The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler converts them into 4B nibbles per Table 2 and sends the 4B nibbles to the controller interface The 4B5B decoder also strips off the SSD delimiter a k a J K symbols and replaces them with two 4B Data 5 nibbles 5 symbol
111. er can be accessed as a doubleword at offset OXOCh as a word at offset OxOEh or as a byte at offset OxOEh A doubleword write to offset OxXOCh will write the BANK SELECT REGISTER but will not write the registers OxXOCh and OxODh but will only write to register OXOEh BANK 7 has no internal registers other than the BANK SELECT REGISTER itself On valid cycles where BANK7 is selected BSO BS1 BS2 1 and A320 nCSOUT is activated to facilitate implementation of external registers Note BANK7 does not exist in LAN91C9x devices For backward S W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C111 Revision 1 91 08 18 08 DATASHEET 46 SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY Datasheet 8 5 Bank 0 Transmit Control Register OFFSET NAME TRANSMIT CONTROL REGISTER TYPE READ WRITE EP SMSC Bank 7 is new register Bank to the SMSC LAN91C111 device This bank has extended registers that allow the extended feature set of the SMSC LAN91C111 SYMBOL TCR This register holds bits programmed by the CPU to control some of the protocol transmit options HIGH BYTE SWFDUP Reserved EPH LOOP STP SQET FDUPLX MON CSN Reserved NOCRC LOW BYTE PAD EN 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 FORCOL LOOP TXENA SMSC LAN
112. escrambler synchronization algorithm on the input data to determine if the device has successfully established a link with a remote device called Link Pass State Refer to IEEE 802 3 for both of these algorithms for more details AutoNegotiation Algorithm As stated previously the AutoNegotiation algorithm is used for two purposes 1 To automatically configure the device for either 10 100 Mbps and Half Full Duplex modes and 2 to establish an active link to and from a remote device The AutoNegotiation algorithm is the same algorithm that is defined in IEEE 802 3 Clause 28 AutoNegotiation uses a burst of link pulses called fast link pulses and referred to as FLP S to pass up to 16 bits of signaling data back and forth between the LAN91C111 and a remote device The transmit FLP pulses meet the templated specified in IEEE 802 3 and shown in Figure 7 7 A timing diagram contrasting NLP s and FLP s is shown in Figure 7 8 Revision 1 91 08 18 08 38 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet a Normal Link Pulse NLP ser 4 4 4 b Fast Link Pulse FLP 4 D1 D2 D3 D14 D15 RJ He ax Data Data Data Data Data Data Figure 7 8 NLP VS FLP Link Pulse The AutoNegotiation algorithm is initiated by any of these events 1 AutoNegotiat
113. et AUTO RELEASE 1 TX EMPTY INT is generated only after transmitting the last packet in the FIFO TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore the FIFO will not be emptied This mode has the advantage of a smaller CPU overhead and faster memory de allocation Note that when AUTO RELEASE 1 the CPU is not provided with the packet numbers that completed successfully Note The pointer register is shared by any process accessing the LAN91C111 memory In order to allow processes to be interruptible the interrupting process is responsible for reading the pointer value before modifying it saving it and restoring it before returning from the interrupt Typically there would be three processes using the pointer 1 Transmit loading sometimes interrupt driven 2 Receive unloading interrupt driven 3 Transmit Status reading interrupt driven 1 and 3 also share the usage of the Packet Number Register Therefore saving and restoring the PNR is also required from interrupt service routines SMSC LAN91C111 REV C 93 Revision 1 91 08 18 08 DATASHEET EP SMSC 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet INTERRUPT EMPTY STATUS REGISTER NUMBER RX FIFO INT REGISTER PACKET NUMBER e TX EMPTY Y TWO OPTIONS ET Ix RX INT FIFO FIFO ALLOC 4 INT EMPTY TX COMPLETION RX PACKET FIFO NUMBER
114. et to indicate that the packet was discarded Otherwise the packet will be received normally and bit 0 set RCVINT in the interrupt status register RCV DISCRD is self clearing MBO Must be 1 8 26 Bank 7 External Registers OFFSET NAME TYPE SYMBOL 0 THROUG H7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs HIGH EXTERNAL R W REGISTER BYTE LOW EXTERNAL R W REGISTER BYTE Revision 1 91 08 18 08 68 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet CYCLE NCSOUT LAN91C111 DATA BUS AEN 0 Driven low Transparently latched on nADS Ignored on writes A320 rising edge Tri stated on reads A4 15 matches I O BASE BANK SELECT 7 BANK SELECT 4 5 6 High Ignore cycle Otherwise High Normal LAN91C111 cycle SMSC LAN91C111 REV 69 DATASHEET Revision 1 91 08 18 08 10 100 Ethernet Single Chip MAC PHY SMSC Chapter 9 PHY MII Registers Datasheet Multiple Register Access Multiple registers can be accessed on a single PHY MI serial port access cycle with the multiple register access features The multiple register access features can be enabled by setting the multiple register access enables bit in the PHY MI serial port Configuration 2 register When multiple register access is enabled multiple registers can be accessed on a single PHY MI
115. ey make a transition or change value and they stay latched until they are read After R LT bits are read they are updated to their current value R LT bits can also be programmed to assert the interrupt function Bit Type Definition R Read Only R WSC Read Write Self Clearing W Write Only R LH Read Latch high RW Read Write R LL Read Latch low R LT Read Latch on Transition REGISTER ADDRESS REGISTER NAME 0 Control 1 Status 2 3 PHY ID 4 Auto Negotiation Advertisement 5 Auto Negotiation Remote End Capability 6 15 Reserved 16 Configuration 1 Revision 1 91 08 18 08 70 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip PHY EP SMSE Datasheet REGISTER ADDRESS REGISTER NAME 17 Configuration 2 18 Status Output 19 Mask 20 Reserved PHY Register Description Table 9 1 MII Serial Frame Structure lt Idle gt Star Read Write PHY Addr gt lt REG Addr gt lt Turnaround gt lt Data gt IDLE ST 1 0 READ WRITE PHYAD 4 0 REGAD 4 0 TA 1 0 D 15 0 D 15 0 4 Register 0 Control Register 1 Status Register 2 PHY ID 1 Register 3 PHY ID 2 Register 4 AutoNegotiation Advertisement Register 5 AutoNegotiation Remote End Capability Register 16 Configuration 1 Register 17 Configuration 2 Register 18 Status Output Register 19 Mask Register 20 Reserved SYMBOL NAME DE
116. go first out of the EPH at 100 Mbps while TXD3 carries the most significant bit of the nibble TXEN100 and TXDO TXD3 clocked by the LAN91C111 using TX25 rising edges TXEN100 goes inactive at the end of the packet on the last nibble of the CRC During a transmission COL100 might become active to indicate a collision COL100 is asynchronous to the LAN91C111 s clocks and will be synchronized internally to TX25 Reception begins when RX DV receive data valid is asserted A preamble pattern or flag octet will be present at RXDO RXD3 when RX DV is activated The LAN91C111 requires no training sequence beyond a full flag octet for reception RX DV as well as RXDO RXD3 are sampled on RX25 rising Revision 1 91 08 18 08 24 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC edges RXDO carries the least significant bit and RXD3 the most significant bit of the nibble RX DV goes inactive when the last valid nibble of the packet CRC is presented at RXDO RXD3 Datasheet RX ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is invalid The LAN91C111 will discard the packet by treating it as a CRC error RXDO RXD3 should always be aligned to packet nibbles therefore opening flag detection does not consider misaligned cases Opening flag detection expects the 5Dh pattern and will not reject the packet on non preamble patterns CRS100 is used a
117. he TX area Some MMU commands use the number stored in this register as the packet number parameter This register is cleared by a RESET or a RESET MMU Command SMSC LAN91C111 REV C 59 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet OFFSET NAME TYPE SYMBOL ALLOCATION RESULT 3 REGISTER READ ONLY ARR This register is updated upon an ALLOCATE MEMORY MMU command FAILED Reserved ALLOCATED PACKET NUMBER 1 0 0 0 0 0 0 0 FAILED A zero indicates a successful allocation completion If the allocation fails the bit is set and only cleared when the pending allocation is satisfied Defaults high upon reset and reset MMU command For polling purposes the ALLOC INT in the Interrupt Status Register should be used because it is synchronized to the read operation Sequence 1 Allocate Command 2 Poll ALLOC INT bit until set 3 Read Allocation Result Register ALLOCATED PACKET NUMBER Packet number associated with the last memory allocation request The value is only valid if the FAILED bit is clear Note For software compatibility with future versions the value read from the ARR after an allocation request is intended to be written into the PNR as is without masking higher bits provided FAILED 0 8 18 Bank 2 FIFO Ports Register OFFSET NAME TYPE SYMBOL 4 FIFO PORTS REGISTER READ ONLY FIFO This register provides access to the read
118. he following methods Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK OK transition Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above 3 1 to 3 5 RX_OVRN INT Set when 1 the receiver aborts due to an overrun due to a failed memory allocation 2 the receiver aborts due to a packet length of greater than 2K bytes or 3 the receiver aborts due to the RCV DISCRD bit in the RCV register set The RX_OVRN INT bit latches the condition for the purpose of being polled or generating an interrupt and will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set ALLOC INT Set when an MMU request for TX ram pages is successful This bit is the complement of the FAILED bit in the ALLOCATION RESULT register The ALLOC INT bit is cleared by the MMU when the next allocation request is processed or allocation fails TX EMPTY INT Set if the TX FIFO goes empty can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission This bit latches the empty condition and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set If a real time reading of the FIFO empty is desired the bit should be first cleared and then read The TX_EMPTY MAS
119. he spec specified as word addresses REGISTER EEPROM WORD ADDRESS Configuration Register IOS Value 4 Base Register IOS Value 4 1 INDIVIDUAL ADDRESS 20 22 hex If IOS2 IOSO 7 only the INDIVIDUAL ADDRESS is read from the EEPROM Currently assigned values are assumed for the other registers These values are default if the EEPROM read operation follows hardware reset The EEPROM SELECT bit is used to determine the type of EEPROM operation a normal or b general purpose register 1 NORMAL EEPROM OPERATION EEPROM SELECT bit 0 On EEPROM read operations after reset or after setting RELOAD high the CONFIGURATION REGISTER and BASE REGISTER are updated with the EEPROM values at locations defined by the 052 0 pins The INDIVIDUAL ADDRESS registers are updated with the values stored in the INDIVIDUAL ADDRESS area of the EEPROM On EEPROM write operations after setting the STORE bit the values of the CONFIGURATION REGISTER and BASE REGISTER are written in the EEPROM locations defined by the IOS2 IOSO pins The three least significant bits of the CONTROL REGISTER EEPROM SELECT RELOAD and STORE are used to control the EEPROM Their values are not stored nor loaded from the EEPROM 2 GENERAL PURPOSE REGISTER EEPROM SELECT bit 1 On EEPROM read operations after setting RELOAD high the EEPROM word address defined by the POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGI
120. hronous cycles These cycles MUST be 32 bit cycles Please refer to the corresponding timing diagrams for details on these cycles The BIU is implemented using the following principles a Address decoding is based on the values of A15 A4 and AEN b Address latching is performed by using transparent latches that are transparent when nADS 0 and nRD 1 nWR 1 and latch on nADS rising edge c Byte word and doubleword accesses to all registers and Data Path are supported except a doubleword write to offset Ch will only write the BANK SELECT REGISTER offset OxOFh No bus byte swapping is implemented no eight bit mode e Word swapping as a function of A1 is implemented for 16 bit bus support f The asynchronous interface uses nRD and nWR strobes If necessary ARDY is negated on the leading edge of the strobe The ARDY trailing edge is controlled by CLK g The VLBUS synchronous interface uses LCLK nADS and W nR as defined in the VESA specification as well as nCYCLE to control read and write operations and generate nSRDY h EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave Mode C specification when nDATACS is driven by nDAK i Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously j Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the nDATACS pin 7 5 MAC PHY Interface The LAN91C111 integrates th
121. ice has successfully received its Link Partner s Link code Word RF Remote Fault When set an advertisement frame will be sent with the corresponding bit set This in turn will cause the PHY receiving it to set the Remote Fault bit in its Status register T4 100BASE T4 A 1 indicates the PHY is capable of 100BASE T4 TX FDX 100BASE TX Full Duplex Capable 1 indicates the PHY is capable of 100BASE TX Full Duplex TX HDX 100BASE TX Half Duplex Capable A 1 indicates the PHY is capable of 100BASE TX Half Duplex 10 FDX 10BASE T Full Duplex Capable indicates the PHY is capable of 10BASE T Full Duplex 10 HDX 10BASE T Half Duplex Capable indicates the PHY is capable of 10BASE T Half Duplex The management entity sets the value of this field prior to AutoNegotiation 1 in these bit indicates that the mode of operation that corresponds to these will be acceptable to be auto negotiated to Only modes supported by the PHY can be set CSMA indicates the PHY is capable of 802 3 CSMA Operation 9 5 Register 5 Auto Negotiation Remote End Capability Register NP ACK RF Reserved Reserved Reserved T4 TX FDX R R R R R R R R 0 0 0 0 0 0 0 0 TX HDX 10 FDX 10 HDX Reserved Reserved Reserved Reserved CSMA R R R R R R R R 0 0 0 0 0 0 0 0 The bit definitions are analogous to the Auto Negotiation Advertisement Register SMSC LAN91C111 REV C 77 DATASHEET Revision 1 91 08 18 08 SMSE 10 100
122. ielded twisted pair cable Transmitter 10 Mbps The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter Even so the transmitter still consists of a waveform generator and line driver The purpose of the waveform generator is to shape the output transmit pulse The waveform generator consists of a ROM DAC dock generator and filter The DAC generates a stair stepped representation of the desired output waveform The stairstepped DAC output then goes through a low pass filter in order to smooth the DAC output and remove any high frequency components The DAC values are determined from the ROM outputs the ROM contents are chosen to shape the pulse to the desired template and are clocked into the DAC at high speed by the clock generator In this way the waveform generator preshapes the output waveform to be transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE 802 3 Clause 14 and also shown in Figure 7 4 The waveshaper replaces and eliminates external filters on the TP transmit output The line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category 3 4 5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins without any external filters During the idle period no output signal is transmitted on the TP outputs except link pulse Revision 1 91 08 18 08 30 S
123. igure 7 3 TX 10BT Frame 26 Figure 7 4 Output Voltage Template 10 31 Figure 7 5 Input Voltage Template 10MBPS 34 Figure 7 6 SOI Output Voltage Template 10 5 37 Figure 7 7 Link Pulse Output Voltage Template 38 Figure 7 8 NLP VS FLP Link Pulse 1 39 Figure 8 1 Data Frame Format i c eda ke ER VIR eR EXER ex Pia a A 43 Figure 8 2 Interrupt Structure 65 Figure 10 1 Interrupt Service 88 Figure 10 2 RA INTR 4 epum eee eee ee pee eee eed eee ee ee 89 Figure 10 3 DOINTB tc ee ade EE eee aha ata PR ee 90 Figure 10 4 TXEMPTY INTR Assumes Auto Release Option 91 Figure 10 5 Drive Send and Allocate 92 Figure 10 6 Interrupt Generation for Transmit 94 Figure 11 1 64 X 16 Serial EEPROM Map 1 97 Figure 12 1 LAN91C111 on
124. into the device and MDIO goes into high impedance state Another serial shift cycle cannot be initiated until the idle condition at least 32 continuous 1 s is detected 7 5 3 Serial Port Frame Structure The structure of the PHY serial port frame is shown in Table 9 1 and timing diagram of frame is shown in Figure 7 1 Each serial port access cycle consists of 32 bits or 192 bits if multiple register access is enabled REGAD 4 0 11111 exclusive of idle The first 16 bits of the serial port cycle are always write bits and are used for addressing The last 16 176 bits are from one all of the 11 data registers The first 2 bit in Table 9 1and Figure 7 1 are start bits and need to be written as a 01 for the serial port cycle to continue The next 2 bits are a read and write bit which determine if the accessed data register bits will be read or write The next 5 bits are device addresses The next 5 bits are register address select bits which select one of the five data registers for access The next 1 bit is a turnaround bit which is not an actual register bit but extra time to switch MDIO from write to read if necessary as shown in Figure 7 1 The final 16 bits of the PHY MI serial port cycle or 176 bits if multiple register access is enabled and REGAD 4 0 11111 come from the specific data register designated by the register address bits REGAD 4 0 Revision 1 91 08 18 08 22 SMSC LAN91C111 REV C DATASHEET EP SMSE
125. ion enabled 2 device enters the Link Fail State 3 AutoNegotiation Reset Once a negotiation has been initiated the LAN91C111 first determines if the remote device has AutoNegotiation capability If the remote device is not AutoNegotiation capable and is just transmitting either a 10BASE T or 100BASE TX signal the LAN91C111 will sense that and place itself in the correct mode If the LAN91C111 detects FLP s from the remote device then the remote device is determined to have AutoNegotiation capability and the device then uses the contents of the MI serial port AutoNegotiation Advertisement register and FLP s to advertise its capabilities to a remote device The remote device does the same and the capabilities read back from the remote device are stored in the PHY MI serial port AutoNegotiation Remote End Capability register The LAN91C111 negotiation algorithm then matches it s capabilities to the remote device s capabilities and determines what mode the device should be configured to according to the priority resolution algorithm defined in IEEE 802 3 Clause 28 Once the negotiation process is completed the LAN91C111 then configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes depending on the outcome of the negotiation process and it switches to either the 100BASETX or 10BASE T link integrity algorithms depending on which mode was enabled by AutoNegotiation Refer to IEEE 802 3 Clause 28 for more details Auto
126. its at a time SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet PIN NO NAME SYMBOL BUFFER DESCRIPTION TQFP QFP 9 11 EEPROM Clock EESK 04 Output 4 usec clock used to shift data in and out of the serial EEPROM 10 12 EEPROM EECS O4 Output Serial EEPROM chip select Select Used for selection and command framing of the serial EEPROM 7 9 EEPROM Data EEDO O4 Output Connected to the DI input of the Out serial EEPROM 8 10 EEPROM Data EEDI with Input Connected to the DO output of the In pulldown serial EEPROM 3 5 5 7 I O Base IOSO IOS2 with Input External switches can be pullup connected to these lines to select between predefined EEPROM configurations 6 8 Enable ENEEP with Input Enables when high or open EEPROM pullup LAN91C111 accesses to the serial EEPROM Must be grounded if no EEPROM is connected to the LAN91C111 127 128 1 2 Crystal 1 XTAL1 Iclk An external 25 MHz crystal is connected Crystal 2 XTAL2 across these pins If a TTL clock is supplied instead it should be connected to XTAL1 and XTAL2 should be left open XTAL1 is the 5V tolerant input of the internal amplifier and XTAL2 is the output of the internal amplifier 1 33 44 3 35 46 Power VDD 3 3V Power supply pins 62 77 98 64 79 110 120 100 112 122 11 16 13 18 Analog Power AVDD 3 3V Analog power supply
127. iven by nLNK pin inverted Typically used for Link Test A transition on the value of this bit generates an interrupt ROL Counter Roll Over When set or more 4 bit counters have reached maximum count 15 Cleared by reading the ECR register EXC DEF Excessive Deferral When set last current transmit was deferred for more than 1518 2 byte times Cleared at the end of every packet sent LOST CARR Lost Carrier Sense When set indicates that Carrier Sense was not present at end of preamble Valid only if MON is enabled This condition causes TXENA bit in TCR to be reset Cleared by setting TXENA bit in TCR LATCOL Late collision detected on last transmit frame If set a late collision was detected later than 64 byte times into the frame When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR Cleared by setting TXENA in TCR TX DEFR Transmit Deferred When set carrier was detected during the first 6 4 us of the inter frame gap Cleared at the end of every packet sent LTX BRD Last transmit frame was a broadcast Set if frame was broadcast Cleared at the start of every transmit frame Revision 1 91 08 18 08 48 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet SQET Signal Quality Error Test This bit is set under the following conditions 1 LAN91C111 is set to operate in Half Duple
128. l port Control register this reset bit is a self clearing bit and the PHY will return a 1 on reads to this bit until the reset is completed 3 the RESET pin is asserted high 4 the SOFT RST bit is set high and then cleared When reset is initiated by 1 or 2 an internal power on reset pulse is generated which resets all internal circuits forces the PHY MI serial port bits to their default values and latches in new values for the MI address After the power on reset pulse has finished the reset bit in the PHY MI serial port Control registers cleared and the device is ready for normal operation When reset is initiated by 3 the same procedure occurs except the device stays in the reset state as long as the RESET pin is held high The internal PHY is guaranteed to be ready for normal operation 50 mS after the reset pin was de asserted or the reset bit is set Software driver requires to wait for 50 5 after setting the RST bit to high to access the internal PHY again Revision 1 91 08 18 08 42 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet 5 15 Chapter 8 Data Structures Registers 8 1 Frame Format In Buffer Memory The frame format in memory is similar for the Transmit and Receive areas The first word is reserved for the status word The next word is used to specify the total number of bytes and it is followed by the data area The data area holds the frame itself
129. low 40 42 SMSC LAN91C111 REV C nVL Bus Access nVLBUS with pullup 15 DATASHEET Input When low the LAN91C111 synchronous bus interface is configured for VL Bus accesses Otherwise the LAN91C111 is configured for EISA DMA burst accesses Does not affect the asynchronous bus interface Revision 1 91 08 18 08 EP SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet PIN NO TQFP QFP NAME SYMBOL BUFFER TYPE DESCRIPTION 42 44 Local Bus Clock LCLK Input Used to interface synchronous buses Maximum frequency is 50 MHz Limited to 8 33 MHz for EISA DMA burst mode This pin should be tied high if it is in asynchronous mode 38 40 Asynchronous Ready ARDY OD16 Open drain output ARDY may be used when interfacing asynchronous buses to extend accesses lts rising access completion edge is controlled by the XTAL1 clock and therefore asynchronous to the host CPU or bus clock ARDY is negated during Asynchronous cycle when one of the following conditions occurs No Wait Bit in the Configuration Register is cleared Read FIFO contains less than 4 bytes when read Write FIFO is full when write 43 45 nSynchronous Ready nSRDY O16 Output This output is used when interfacing synchronous buses and nVLBUS 0 to extend accesses This signal remains normally inactive and its falling edge
130. n 1 register When this bit is set the 5B data bypasses the scrambler and goes directly from the 4B5B encoder to the twisted pair transmitter 7 7 6 Descrambler 100 Mbps The LAN91C111 descrambler takes the scrambled data from the data recovery block descrambles it per the IEEE 802 3 specifications aligns the data on the correct 5B word boundaries and sends it to the 4B5B decoder The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE 802 3 specification Once the descrambler is synchronized it will maintain synchronization as long as enough descrambled idle pattern 1 s are defected within given interval To stay in synchronization the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1 s in 1ms interval SMSC LAN91C111 REV C 29 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY P smsc Datasheet If 25 consecutive descrambled idle pattern 1 s are not detected within the 1ms interval the descrambler goes out of synchronization and restarts the synchronization process If the descrambler is in the unsynchronized state the descrambler loss of synchronization detect bit is set in the MI serial port Status Output register to indicate this condition Once this bit is set it will stay set until the descrambler achieves synchronization 10 Mbps A descrambler is not used in 10 Mbps mode Descrambler Bypass The descrambler
131. nBE1 nLDEV nlOCS16 lt 4 Figure 12 2 LAN91C111 on ISA BUS EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed as a 32 bit I O slave along with a Slave DMA type C data path option As an I O slave the LAN91C111 uses asynchronous accesses In creating nRD and nWR inputs the timing information is externally derived from nCMD edges Given that the access will be at least 1 5 to 2 clocks more than 180ns at least there is no need to negate EXRDY simplifying the EISA interface implementation As a DMA Slave the LAN91C111 accepts burst transfers and is able to sustain the peak rate of one doubleword every BCLK Doubleword alignment is assumed for DMA transfers The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits wait states Table 12 3 EISA 32 Bit Slave Signal Connections EISA BUS LAN91C111 SIGNAL SIGNAL NOTES LA2 LA15 A2 A15 Address bus used for I O space and register decoding latched by nADS nSTART trailing edge M nlO AEN Qualifies valid I O decoding enabled access when low These AEN signals are externally ORed Internally the AEN pin is latched by nADS rising edge and transparent while nADS is low Revision 1 91 08 18 08 102 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Table 12 3 EISA 32 Bit Slave Signal Connections continued EISA BUS LAN91C111 SIGNAL SIGNAL NOTES Latched W R nRD I
132. nd register bits in the PHY MI serial port Status and Status Output registers are set Jabber Disable The jabber function can be disabled by setting the jabber disable bit in the PHY MI serial port Configuration 2 register 7 7 14 Receive Polarity Correction 100 Mbps No polarity detection or correction is needed in 100Mbps mode 10 Mbps The polarity of the signal on the TP receive input is continuously monitored If either 3 consecutive link pulses or one SOI pulse indicates incorrect polarity on the TP receive input the polarity is internally determined to be incorrect and a reverse polarity bit is set in the PHY MI serial port Status Output register The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled Note The first 3 received packets must be discarded after the correction of a reverse polarity condition Revision 1 91 08 18 08 40 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY e m S r Datasheet Autopolarity Disable The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2 register 7 7 15 Full Duplex Mode 100 Mbps Full Duplex mode allows transmission and reception to occur simultaneously When Full Duplex mode is enabled collision is disabled The device can be either forced into Half or Full Duplex mode or the device can detect either Half
133. ne is independently specified SMSC LAN91C111 REV C 45 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Regardless of the functional description all registers can be accessed as doublewords words or bytes The default bit values upon hard reset are highlighted below each register Table 8 1 Internal I O Space Mapping 1 2 0 CONFIG MMU COMMAND MTO 1 2 EPH STATUS BASE PNR MT2 3 4 RCR 1 5 4 5 6 COUNTER 2 3 POINTER MT6 7 8 MIR 4 5 MGMT RPCR GENERAL PURPOSE DATA REVISION C RESERVED CONTROL INTERRUPT RCV E BANK BANK BANK BANK A special BANK BANK7 exists to support the addition of external registers 8 4 Bank Select Register OFFSET NAME TYPE SYMBOL E BANK SELECT REGISTER READ WRITE BSR HIGH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE 0 0 1 1 0 0 1 1 LOW BS2 BS1 BSO BYTE X X X X X 0 0 0 BS2 BS1 BSO Determine the bank presently in use This register is always accessible and is used to select the register bank in use The upper byte always reads as 33h and can be used to help determine the location of the LAN91C111 The BANK SELECT REGISTER is always accessible regardless of the value of BS0 2 Note The bank select regist
134. ngle Chip MAC PHY Datasheet EP SMSE Table 10 2 Flow Of Events For Restoring Device In Normal Power Mode S W DRIVER the configuration register Bank 1 Offset 0 CONTROLLER FUNCTION Write and set 1 the EPH Power Bit located Ethernet MAC Enables the RX Clock TX clock derived from the Internal PHY The EPH Clock is also enabled Write the PDN bit in PHY MI Register O to 0 The PHY is then set in isolation mode MII DIS bit is set Need to clear this MII DIS bit and need to wait for 500 ms for the PHY to restore normal Internal PHY entered normal operation mode Issue MMU Reset Command Restore Device Register Level Context Enable Transmitter Set the TXENA bit of the Transmit Control Register Ethernet MAC can now transmit Ethernet Packets Enable Receiver Set 1 the RXEN bit of the Receive Control Register Ethernet MAC is now able to receive Packets Ethernet MAC is now restored for normal operation 10 2 Typical Flow of Events for Transmit Auto Release 0 S W DRIVER MAC SIDE ISSUE ALLOCATE MEMORY FOR TX N BYTES the MMU attempts to allocate N bytes of RAM WAIT FOR SUCCESSFUL COMPLETION CODE Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt The TX packet number is now at the Allocation Result Register LOAD TRANSMIT DATA Copy the TX packet number into the Packet Number R
135. ns to this register may be ignored while the PHY is processing the reset All PHY registers will be driven to their default states after reset The internal PHY is guaranteed to be ready for normal operation 50 mS after the RST bit is set Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again LPBK Loopback Writing a 1 will put the PHY into loopback mode Speed Speed Selection When Auto Negotiation is disabled this bit can be used to manually select the link speed Writing a 1 to this bit selects 100 Mbps a 0 selects 10 Mbps When Auto Negotiation is enabled reading or writing this bit has no meaning effect ANEN EN Auto Negotiation Enable Auto negotiation is on when this bit is 1 In that case the contents of bits Speed and Duplex are ignored and the ANEG process determines the link configuration PDN Power down Setting this bit to 1 will put the PHY in PowerDown mode In this state the PHY will respond to management transactions MII DIS MII DISABLE Setting this bit will set the PHY to an isolated mode in which it will respond to MII management frames over the MII management interface but will ignore data on the MII data interface internal PHY is placed in isolation mode at power up and reset It can be removed from isolation mode by clearing the MII DIS bit in the PHY Control Register If necessary the internal PHY can be enabled by cl
136. nsmit receive pair interfacing to 10 100Base T utilizing the internal physical layer block The second interface follows the MII Media Independent Interface specification standard consisting of 4 bit wide data transfers at the nibble rate This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks Three of the LAN91C111 s pins are used to interface to the two line MII serial management protocol The SMSC LAN91C111 integrates IEEE 802 3 Physical Layer for twisted pair Ethernet applications The PHY can be configured for either 100 Mbps 100Base TX or 10 Mbps 10Base T Ethernet operation The Analog PHY block consists of a 4B5B Manchester encoder decoder scrambler de scrambler transmitter with wave shaping and output driver twisted pair receiver with on chip equalizer and baseline wander correction clock and data recovery Auto Negotiation controller interface MII and serial port MI Internal output wave shaping circuitry and on chip filters eliminate the need for external filters normally required in 100Base TX and 10Base T applications The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on chip Auto Negotiation algorithm The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base TX 10Base T adapter cards motherboards repeaters switching hubs The LAN91C111 operates from a single 3 3V supply
137. nt through 1 1 1 1 1 successfully Y Read Pkt 4 Register amp Save Y Write Address Pointer Register Y Read Status Word from RAM Y Update Statistics Y Y Issue Release Command Update Variables Acknowledge TXINTR Y Re Enable TXENA Y Restore Packet Number Return to ISR Figure 10 4 TXEMPTY INTR Assumes Auto Release Option Selected SMSC LAN91C111 REV C 91 DATASHEET Revision 1 91 08 18 08 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet DRIVER SEND ALLOCATE Ch Bank Select SES 2 gies Issue Allocate Memory egister Command to MMU Y Call ALLOCATE Read Interrupt Status Register Exit Driver Send Yes Allocation No Passed Read Allocation Result Register Write Allocated Packet into Store Data Buffer Pointer Packet Register Write Address Pointer Register Clear Ready for Packet Flag Copy Part of TX Data Packet into RAM Enable Allocation Interrupt Y Write Source Address into Proper Location y Copy Remaining TX Data Packet into RAM Enqueue Packet Y Set Ready for Packet Flag Y Return Buffers to Upper Layer Y Return Figure 10 5 Drive Send and Allocate Routines MEMORY PARTITIONING Unlike other controllers the LAN91C111 does not require a fixed memory partitioning betwe
138. nterline D1 13 80 14 00 14 20 X body Size E 15 80 16 00 16 20 Y Span E 2 7 90 8 00 8 10 175 Y Span Measure from Centerline E1 13 80 14 00 14 20 Y body Size H 0 09 0 20 Lead Frame Thickness L 0 45 0 60 0 75 Lead Foot Length from Centerline L1 1 00 Lead Length e 0 40 Basic Lead Pitch q 0 79 Lead Foot Angle W 0 13 0 18 0 23 Lead Width R1 0 08 Lead Shoulder Radius R2 0 08 0 20 Lead Foot Radius 0 0762 Coplanarity Assemblers 0 08 Coplanarity Test House Notes 1 Controlling Unit millimeter 2 Tolerance on the position of the leads is 0 035 mm maximum 3 Package body dimensions D1 and E1 do not include the mold protrusion Maximum mold protrusion is 0 25 mm 4 Dimension for foot length L measured at the gauge plane 0 25 mm above the seating plane is 0 78 1 08 mm 5 Details of pin 1 identifier are optional but must be located within the zone indicated 6 Shoulder widths must conform to JEDEC MS 026 dimension S of a minimum of 0 20mm Revision 1 91 08 18 08 126 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC Datasheet Z 1 EH EAI FT c5 e i m Figure 15 2 128 Pin Package Outline 3 9 Footprint Table 15 2 128 Pin QFP Package Parameters MIN NOMINA
139. o facilitate double word move operations regardless of the actual bus width 16 or 32 bits The DATA register is accessible at any address in the 8 through Bh range while the number of bytes being transferred is determined by A1 and nBEO nBE3 The FIFOs are 12 bytes each Bank 2 Interrupt Status Registers OFFSET NAME TYPE SYMBOL INTERRUPT STATUS REGISTER READ ONLY IST MDINT Reserved INT RX OVRN INT ALLOC INT TX EMPTY INT TX INT RCV INT 0 1 Revision 1 91 08 18 08 6 2 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet OFFSET NAME TYPE SYMBOL INTERRUPT ACKNOWLEDGE C REGISTER WRITE ONLY IST MDINT Reserved RX OVRN TX EMPTY TX INT INT INT OFFSET NAME TYPE SYMBOL INTERRUPT MASK D REGISTER READ WRITE MSK MDINT Reserved EPH INT RX OVRN ALLOC INT TX EMPTY TX INT RCV INT MASK MASK INT MASK INT MASK MASK MASK MASK 0 0 0 0 0 0 0 0 This register be read and written as word or as two individual bytes The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low MASK bit being set will cause hardware interrupt MDINT Set when the following bits in the PHY MI Register 18 Serial Port Status Output Register change state 1 LNKFAIL 2 LOSSSYNG 3 CWRD 4 SSD 5 ESD 6 P
140. on is begun the MAC is notified that valid data is received and 5 5 symbols are substituted in place of the J K symbols If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither nor J K symbols but contains at least 2 non contiguous 0 s then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication also referred to as bad SMSC LAN91C111 REV C 35 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE SSD is signaled to the controller interface When False Carrier is detected the MAG is notified of false carrier and invalid received and the bad SSD bit is set in the PHY MI serial port Status Output register Once a False Carrier Event is detected the idle pattern two symbols must be detected before any new SSD s can be sensed Datasheet If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither nor J K symbols but does not contain at least 2 non contiguous O s the data is ignored and the receiver stays in the idle state 10 Mbps Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP inputs then the start of packet for 10 Mbps mode is detected when valid data is detected by the TP squelch circuit When start of packet is detected carrier sense signal
141. r Temp Read Bank 0 Offset 2 Acknowledge TX Interrupt Write Byte 0x02 Bank 2 Offset C Check for Status of Transmission If Temp AND 0x0001 Successful Transmission Step 4 1 1 Issue MMU Release Release Specific Packet Write 0 00 0 Bank2 Offset 0 Step 4 1 2 Return from the routine l Transmission has FAILED Now we can either release or re enqueue the packet Step 4 2 1 Get the packet to release re enqueue stored in FIFO Temp Read Bank 2 Offset 4 Temp Temp 4 0x003F Step 4 2 2 Write to the PNR Write Temp Bank2 Offset 2 Step 4 2 3 Option 1 Release the packet Write 0x00A0 Bank2 Offset 0 Option 2 Re Enqueue the packet Write 0 00 0 Bank2 Offset 0 Step 4 2 4 Re Enable Transmission Temp Read BankO0 Offset 0 Temp Temp2 OR 0 0001 Write Temp2 Bank 0 Offset 0 Step 4 2 5 Return from the routine 5 Restore the Packet Number Register Write Byte Saved PNR Bank 2 Offset 2 Figure 10 3 TX INTR Revision 1 91 08 18 08 90 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC Datasheet SMSC TXEMPTY INTR Y Write Acknowledge Reg with TXEMPTY Bit Set y Read TXEMPTY amp TX INTR T TXEMPTY 0 TXEMPTY X amp amp TXINT 0 TXINT 1 Waiting for Completion Transmission Failed TXEMPTY 1 amp TXINT 0 Everything we
142. rol Register is clear 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet ANEG Auto Negotiation mode select The PHY is placed in Auto Negotiation mode when the ANEG bit and the ANEG EN bit in PHY Register 0 Control Register both are set When either of these bits is cleared 0 the PHY is placed in manual mode DUPLEX MODE AUTO CONTROL WHAT DO YOU NEGOTIATION AUTO NEGOTIATION ADVERTISEMENT FOR THE WANT TO DO CONTROL BITS REGISTER MAC Try to Auto Negotiate ANEG ANEG E TX FDX TX HDX 10 FDX 10 HDX SWFDUP to Bit N Bit Bit Bit Bit Bit Bit RPCR Register O Register Register Register Register Transmit MAC PHY 4 4 4 4 Control PHY PHY PHY PHY Register MAC 100 Full Duplex 1 1 1 1 1 1 1 100 Half Duplex 1 1 0 1 1 1 0 10 Full Duplex 1 1 0 0 1 1 1 10 Half Duplex 1 1 0 0 0 1 0 DUPLEX MODE CONTROL WHAT DO YOU AUTO NEGOTIATION SPEED AND DUPLEX MODE CONTROL FOR THE WANT TO DO CONTROL BITS FOR THE PHY MAC Try to Manually Set to ANEG ANEG E SPEED DPLX SPEED DPLX SWFDUP Bit N Bit Bit Bit Bit Bit Bit RPCR Register 0 RPCR RPCR Register Register Transmit MAC PHY MAC MAC 0 0 Control Bank 0 Bank 0 Bank 0 PHY PHY Register Offset A Offset A Offset A MAC 100 Full Duplex 0 0 1 1 X X 1 0 1 1 1 X X 1 1 0 X X 1 1 1 100 Half Duplex 0 0 1 0 X X 0 0 1 1 0 X X 0 1 0 X X 1 0 0 Revision 1 91 08
143. rom 40 C to 85 C LAN91C111i Network Interface Fully Integrated IEEE 802 3 802 3u 100Base TX 10Base T Physical Layer Auto Negotiation 10 100 Full Half Duplex On Chip Wave Shaping No External Filters Required Adaptive Equalizer Baseline Wander Correction LED Outputs User selectable Up to 2 LED functions at one time Link Activity Full Duplex 10 100 Transmit Receive SMSC LAN91C111 REV DATASHEET Revision 1 91 08 18 08 10 100 Ethernet Single Chip MAC PHY Datasheet ORDER NUMBERS LAN91C111 NC LAN91C111i NC INDUSTRIAL TEMPERATURE FOR 128 PIN QFP PACKAGES LAN91C111 NS LAN91C111i NS INDUSTRIAL TEMPERATURE FOR 128 LEAD FREE ROHS COMPLIANT PACKAGES LAN91C111 NE 1 0MM HEIGHT LAN91C111i NE INDUSTRIAL TEMPERATURE FOR 128 PIN TQFP PACKAGES LAN91C111 NU 1 0MM HEIGHT LAN91C111i NU INDUSTRIAL TEMPERATURE FOR 128 PIN LEAD FREE ROHS COMPLIANT PACKAGES SMSC 80 ARKAY DRIVE HAUPPAUGE NY 11788 631 435 6000 FAX 631 273 3123 Copyright 2008 SMSC or its subsidiaries All rights reserved Circuit diagrams and other information relating to SMSC products are included as means of illustrating typical applications Consequently complete information sufficient for construction purposes is not necessarily given Although the information has been checked and is believed to be accurate no responsibility is assumed for inaccuracies
144. s t12A nDATACS Hold After Rising 0 ns t14 nRDYRTN Setup to LCLK Falling 10 ns t15 nRDYRTN Hold after LCLK Falling 10 ns t7 W nR Setup to LCLK Falling 15 ns t17A W nR Hold After Falling 3 ns t18 Data Setup to LCLK Rising Write 15 ns t20 Data Hold from LCLK Rising Write 4 ns t22 nCYCLE Setup to LCLK Rising 5 ns t22A nCYCLE Hold After LCLK Rising 10 ns SMSC LAN91C111 REV C 113 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet t17 gt lat12 114 nDATACS t17A W nR nCYCLE 119 119 5 Read Data 2 115 nRDYRTN Figure 14 6 Burst Read Cycles nVLBUS 1 PARAMETER MIN TYP MAX UNITS t12 nDATACS Setup to LCLK Rising 20 ns t12A nDATACS Hold after Rising 0 ns t14 nRDYRTN Setup to LCLK Falling 10 ns t15 nRDYRTN Hold after LCLK Falling 10 ns t7 W nR Setup to LCLK Falling 15 ns t17A W nR Hold After Falling 3 ns t19 Data Delay from LCLK Rising Read 5 15 ns Revision 1 91 08 18 08 114 DATASHEET SMSC LAN91C111 REV C 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet 18 nADS Address 3 0 5 nLDEV Figure 14 7 Address Latching for All Modes PARAMETER MIN TYP MAX UNITS t8 A1 A15 AEN nBE 3 0 Set
145. s a frame envelope signal for the CSMA CD MAC state machines deferral and backoff functions but it is not used for receive framing functions CRS100 is an asynchronous signal and it will be active whenever there is activity on the cable including LAN91C111 transmissions and collisions 7 6 Serial EEPROM Interface This block is responsible for reading the serial EEPROM upon hardware reset or equivalent command and defining defaults for some key registers write operation is also implemented by this block that under CPU command will program specific locations in the EEPROM This block is an autonomous state machine and controls the internal Data Bus of the LAN91C111 during active operation 7 7 Internal Physical Layer The LAN91C111 integrates the IEEE 802 3 physical layer PHY internally The EXT PHY bit in the Configuration Register is 0 as the default configuration to set the internal PHY enabled The internal PHY address is 00000 the driver must use this address to talk to the internal PHY The internal PHY is placed in isolation mode at power up and reset It can be removed from isolation mode by clearing the MII DIS bit in the PHY Control Register If necessary the internal PHY can be enabled by clearing the EXT PHY bit in the Configuration Register The internal PHY of LAN91C111 has nine main sections controller interface encoder decoder scrambler descrambler clock and data recovery twisted pair transmitter twisted pair rec
146. s after the pointer was loaded to allow the Data Register FIFO to fill If the pointer is loaded using 8 bit writes the low byte should be loaded first and the high byte last Reserved Must be 0 NOT EMPTY When set indicates that the Write Data FIFO is not empty yet The CPU can verify that the FIFO is empty before loading a new pointer value This is a read only bit Note If AUTO INCR is not set the pointer must be loaded with a dword aligned value SMSC LAN91C111 REV C 61 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Ethernet Single Chip MAC PHY Datasheet 8 20 Bank 2 Data Register OFFSET NAME TYPE SYMBOL 8 THROUGH BH DATA REGISTER READ WRITE DATA DATA HIGH X X X X X X X DATA LOW 8 21 DATA REGISTER Used to read or write the data buffer byte word presently addressed by the pointer register This register is mapped into two uni directional FIFOs that allow moving words to and from the LAN91C111 regardless of whether the pointer address is even odd or dword aligned Data goes through the write FIFO into memory and is pre fetched from memory into the read FIFO If byte accesses are used the appropriate next byte can be accessed through the Data Low or Data High registers The order to and from the FIFO is preserved Byte word and dword accesses can be mixed on the fly in any order This register is mapped into two consecutive word locations t
147. s the squelch levels at least 4 times with alternating polarity within 10 uS interval the data is considered to be valid by the squelch circuit and the receiver now enters into the unsquelch state In the unsquelch state the receive threshold level is reduced by approximately 3096 for noise immunity reasons and is called the unsquelch level When the receiver is in the unsquelch state then the input signal is deemed to be valid The device stays in the unsquelch state until loss of data is detected Loss of data is detected if no alternating polarity unsquelch transitions are detected during any 10 uS interval When the loss of data is detected the receive squelch is turned on again TP Squelch 10 Mbps The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps mode except 1 the 10 Mbps TP squelch algorithm is not used for link integrity but to sense the beginning of a packet 2 the receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50 250 nS interval 3 the receiver goes into the squelch state when idle is detected 4 unsquelch detection has no affect on link integrity link pulses are used for that in 10 Mbps mode 5 start of packet is determined when the receiver goes into the unsquelch state an a CRS100 is asserted and 6 the receiver meets the squelch requirements defined in IEEE 802 3 Clause 14 Revision 1 91 08 18 08 34 SMS
148. s valid before leading edge Revision 1 91 08 18 08 100 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Table 12 2 High End ISA or Non Burst EISA Machines Signal Connectors continued ores nlOWR nWR I O Write strobe asynchronous write access Address is valid before leading edge Data is latched on trailing edge IOCHRDY ARDY This signal is negated on leading nRD nWR if necessary It is then asserted on CLK rising edge after the access condition is satisfied RESET RESET 0 nBEO nSBHE nBE1 IRQn INTRO DO D15 015 16 bit data bus bus byte s used to access the device function of nBEO and 1 Lower Upper Lower Not used Not used Upper Not used tri state on reads ignored on writes nlOCS16 nLDEV buffered nLDEV is a totem pole output Must be buffered using an open collector driver is active on valid decodes of A15 A4 and AEN 0 UNUSED PINS GND nADS VCC nBE2 nBE3 No upper word access nCYCLE W nR nRDYRTN LCLK SMSC LAN91C111 REV 101 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY SMSC patos ISA BUS 1 15 4 M A15 AEN RESET RESET VCC nBE2 D0 D15 00 015 INTRO LAN91C111 nlORD nRD nlOWR nWR 0 nBEO nSBHE
149. se X full duplex capable PHY 0 not capable CAP TXH 100BASE TX Half Duplex Capable 1 Indicates 100Base X alf duplex capable PHY 0 not capable CAP TF 10BASE T Full Duplex Capable 1 Indicates 10Mbps full duplex capable PHY 0 not capable CAP TH 10BASE T Half Duplex Capable 1 Indicates 10Mbps half duplex capable PHY 0 not capable Reserved Reserved Must be 0 for Proper Operation CAP SUPR MI Preamble Suppression Capable 1 indicates the PHY is able to receive management frames even if not preceded by a preamble 0 when it is not able ANEG ACK Auto Negotiation Acknowledgment When read as 1 indicate ANEG has been completed and that contents in registers 4 5 6 and 7 are valid 0 means ANEG has not completed and contents in registers 4 5 6 and 7 are meaningless The PHY returns zero if ANEG is disabled SMSC LAN91C111 REV C 75 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet REM FLT Remote Fault Detect indicates a Remote Fault Latches the 1 condition and is cleared by reading this register or resetting the PHY CAP ANEG AutoNegotiation Capable Indicates the ability 1 to perform ANEG or not 0 LINK Link Status A 1 indicates a valid Link and a 0 and invalid Link The 0 condition is latched until this register is read JAB Jabber De
150. serial port access cycle by setting the register address to 11111 during the first 16 MDC clock cycles There is no actual register residing in register address location 11111 so when the register address is then set to 11111 all eleven registers are accessed on the 176 rising edges of MDC that occur after the first 16 MDC clock cycles of the PHY MI serial port access cycle The registers are accessed in numerical order from 0 to 20 After all 192 MDC clocks have been completed all the registers have been read written and the serial shift process is halted data is latched into the device and MDIO goes into high impedance state Another serial shift cycle cannot be initiated until the idle condition at least 32 continuous 1 s is detected Bit Types Since the serial port is bi directional there are many types of bits Write bits W are inputs during a write cycle and are high impedance during a read cycle Read bits R are outputs during a read cycle and high impedance during a write cycle Read Write bits RW are actually write bits which can be read out during a read cycle R WSC bits are R W bits that are self clearing after a set period of time or after a specific event has completed R LL bits are read bits that latch themselves when they go low and they stay latched low until read After they are read they are reset high R LH bits are the same as R LL bits except that they latch high R LT are read bits that latch themselves whenever th
151. ses Bursts 3 3 3 Link Required To Detect AutoNegotiation Pulses Capability SMSC LAN91C111 REV 123 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY Datasheet EP SMSE eq a Transmit NLP me L s 144 gt PENAL E LEDn b Receive NLP Figure 14 16 Link Pulse Timing Revision 1 91 08 18 08 124 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet CLK DATA CLK DATA CLK CLK DATA gl yy NE Transmit FLP and FLP Burst 151 CLK DATA CLK DATA TPI t 52 3 4 31 25 62 5 93 75 125 156 25 t56 b Receive FLP t58 LEDn c Receive FLP Burst Figure 14 17 FLP Link Pulse Timing SMSC LAN91C111 REV C 125 Revision 1 91 08 18 08 DATASHEET EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet Chapter 15 Package Outlines HHE HAHAHAHAA HE HHHHHHHHE H 1 DA t Figure 15 1 128 Pin TQFP Package Outline 14X14X1 0 Body Table 15 1 128 Pin TQFP Package Parameters MIN NOMINAL MAX REMARK A 1 20 Overall Package Height Al 0 05 0 15 Standoff A2 095 1100 105 BodyThickness D 11580 1600 1620 XSpan D 2 7 90 8 00 8 10 175 X Span Measure from Ce
152. signal Analog Digital device that implements the MAC and PHY portion of the CSMA CD protocol at 10 and 100 Mbps The design will also minimize data throughput constraints utilizing a 32 bit 16 bit or 8 bit bus Host interface in embedded applications The total internal memory FIFO buffer size is 8 Kbytes which is the total chip storage for transmit and receive operations The SMSC LAN91C111 is software compatible with the LAN9000 family of products Memory management is handled using a patented optimized MMU Memory Management Unit architecture and a 32 bit wide internal data path This mapped architecture can sustain back to back frame transmission and reception for superior data throughput and optimal performance It also dynamically allocates buffer memory in an efficient buffer utilization scheme reducing software tasks and relieving the host CPU from performing these housekeeping functions The SMSC LAN91C111 provides a flexible slave interface for easy connectivity with industry standard buses The Bus Interface Unit BIU can handle synchronous as well as asynchronous transfers with different signals being used for each one Asynchronous bus support for ISA is supported even though ISA cannot sustain 100 Mbps traffic Fast Ethernet data rates are attainable for ISA based nodes on the basis of the aggregate traffic benefits Two different interfaces are supported on the network side The first Interface is a standard Magnetics tra
153. state Interrupt bits stay latched until they are read When interrupt bits are read the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to their current value Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by setting the appropriate mask register bits in the Mask register Datasheet Interrupt indication is done in two ways 1 MDINT bit in Interrupt Status Register 2 INT bit in the PHY MI Serial Port Status Output register The INT bit is an active high interrupt register bit that resides in the PHY MI Serial Port Status Output register 7 8 Reset The chip MAC amp PHY performs an internal system reset when either 1 the RESET pin is asserted high for at least 100ns 2 writing 1 to the SOFT RST bit in the Receive Control Register this reset bit is not a self clearing bit reset can be terminated by writing the bit low It programs all registers to their default value When reset is initiated by 1 and the EEPROM is presented and enabled the controller will load the EEPROM to obtain the following configurations 1 Configuration Register 2 BASE Register or and 3 MAC Address The internal MAC is not a power on reset device thus reset is required after power up to ensure all register bits are in default state The internal PHY is reset when either 1 VDD is applied to the device 2 the RST bit is set in the PHY MI seria
154. tect Jabber condition detected when 1 for 10Mbps 1 latched until this register is read or the PHY is reset Always 0 for 100Mbps EXREG Extended Capability register 1 Indicates extended registers are implemented 9 3 Register 2 amp 3 PHY Identifier Register These two registers offsets 2 and 3 provide a 32 bit value unique to the PHY REG BITS NAME DEFAULT VALUE R W SOFT RESET 2 15 0 Company ID 0000000000010110 R Retains Original Value 3 15 10 Company ID 111110 R Retains Original Value 3 9 4 Manufacturer s ID 000100 R Retains Original Value 3 3 0 Manufacturer s Revision Retains Original Value 9 4 Register 4 Auto Negotiation Advertisement Register NP Reserved Reserved Reserved T4 TX FDX RW R RW RW RW RW RW RW 0 0 0 0 0 0 0 1 TX HDX 10 FDX 10 HDX Reserved Reserved Reserved Reserved CSMA RW RW RW RW RW RW RW RW 1 1 1 0 0 0 0 1 This register control the values transmitted by the PHY to the remote partner when advertising its abilities Revision 1 91 08 18 08 76 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet NP Next Page A 1 indicates the PHY wishes to exchange Next Page information ACK Acknowledge It is used by the Auto negotiation function to indicate that a dev
155. ter s being accessed nBEO nBE3 are ignored when nDATACS is low burst accesses because 32 bit transfers are assumed 107 104 102 99 76 73 71 68 66 63 61 58 56 53 51 48 109 106 104 101 78 75 73 70 68 65 63 60 58 55 53 50 Data Bus 031 l O24 Bidirectional 32 bit data bus used to access the LAN91C111 s internal registers Data bus has weak internal pullups Supports direct connection to the system bus without external buffering For 16 bit systems only 00 015 are used 30 32 Reset RESET IS Input When this pin is asserted high the controller performs an internal system MAC amp PHY reset It programs all the registers to their default value the controller will read the EEPROM device through the EEPROM interface Note 5 1 This input is not considered active unless it is active for at least 100ns to filter narrow glitches 37 39 nAddress Strobe nADS IS Input For systems that require address latching the rising edge of nADS indicates the latching moment for A1 A15 and AEN All LAN91C111 internal functions of A1 A15 AEN are latched except for nLDEV decoding 35 37 nCYCLE Input This active low signal is used to control LAN91C111 EISA burst mode synchronous bus cycles 36 38 Write nRead W nR IS Input Defines the direction of synchronous cycles Write cycles when high read cycles when
156. thernet Single Chip MAC PHY Datasheet EP SMSC Chapter 6 Signal Description Parameters This section provides detailed description of each SMSC LAN91C111 signal The signals arranged in functional groups according to their associated function The n symbol at the beginning of a signal name indicates that it is an active low signal When n is not present before the signal name it indicates an active high signal The term assert or assertion indicates that a signal is active independent of whether that level is represented by a high or low voltage The term negates or negation indicates that a signal is inactive The term High Z means tri stated The term Undefined means the signal could be high low tri stated or in some in between level 6 1 Buffer Types O4 Output buffer with 2mA source and 4mA sink O12 Output buffer with 6mA source and 12mA sink O16 Output buffer with 8mA source and 16mA sink O24 Output buffer with 12mA source and 24mA sink OD16 Open drain buffer with 16mA sink 0D24 Open drain buffer with 24mA sink 4 Bidirectional buffer with 2 source 4 sink 1 024 Bidirectional buffer with 12mA source and 24mA sink VOD Bidirectional Open drain buffer with 4mA sink Input buffer IS Input buffer with Schmitt Trigger Hysteresis Clock input buffer I O Differential Input Differential Output tolerant Input
157. thernet Single Chip MAC PHY EP SMSC Chapter 14 Timing Diagrams Datasheet Address AEN nBE 3 0 nADS Read Data nRD nWR Lisa Write Data Figure 14 1 Asynchronous Cycle nADS 0 PARAMETER MIN TYP MAX UNITS 11 1 15 AEN nBE 3 0 Valid to NAD nWR Active 2 ns t2 A1 A15 AEN nBE 3 0 Hold After nRD nWR Inactive Assuming 5 ns nADS Tied Low t3 nRD Low to Valid Data 15 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inactive 10 ns t5A Data Hold After nWR Inactive 5 ns t6 nRD Strobe Width 15 ns Revision 1 91 08 18 08 110 SMSC LAN91C111 REV DATASHEET 10 100 Ethernet Single Chip MAC EP SMSE Datasheet Asynchronous Cycle Using nADS pt Addr AEN nBE 1 0 valid 18 nADS 13 gt Read Data valid 16 gt gt ti t5 gt nRD nWR t5A Write Data valid cum Figure 14 2 Asynchronous Cycle Using nADS PARAMETER MIN TYP UNITS 11 1 15 nBE 3 0 Valid to nRD nWR Active 2 ns t3 nRD Low to Valid Data 15 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inactive 10 ns t5A Data Hold After nWR Inactive 5 ns t6 nRD Strobe Width 15 ns t8 A1 A15 AEN nBE 3 0 Setup to nADS Rising 8 ns t9 A1 A15 AEN nBE 3 0 Hold after nADS Rising 5 ns SMSC LAN91C111 REV C 111 Re
158. to the EPH INT bit Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover will acknowledge the interrupt CR ENABLE defaults low disabled TE ENABLE Transmit Error Enable When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit An EPH INT interrupt caused by a transmitter error is acknowledged by setting TXENA bit in the TCR register to 1 or by clearing the TE ENABLE bit TE ENABLE defaults low disabled Transmit Error is any condition that clears TXENA with TX SUC staying low as described in the EPHSR register EEPROM SELECT This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE refers to When high the General Purpose Register is the only register read or written When low RELOAD reads Configuration Base and Individual Address and STORE writes the Configuration and Base registers RELOAD When set it will read the EEPROM and update relevant registers with its contents Clears upon completing the operation STORE When set stores the contents of all relevant registers in the serial EEPROM Clears upon completing the operation Note When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high The remaining 14 bits of this register will be invalid During this time attempted read write operations other than polling the EEPROM status will NOT have any effect on the internal registers The CPU can resume accesses to the
159. ts all multicast frames frames in which the first bit of DA is 1 When clear accepts only the multicast frames that match the multicast table setting Defaults low PRMS Promiscuous mode When set receives all frames Does not receive its own transmission unless it is in Full Duplex RX ABORT This bit is set if a receive frame was aborted due to length longer than 2K bytes frame will not be received The bit is cleared by RESET or by the CPU writing it low Reserved Must be 0 Bank 0 Counter Register OFFSET NAME TYPE SYMBOL 6 COUNTER REGISTER READ ONLY ECR Counts four parameters for MAC statistics When any counter reaches 15 an interrupt is issued All counters are cleared when reading the register and do not wrap around beyond 15 HIGH BYTE NUMBER OF EXC DEFFERED TX NUMBER OF DEFFERED TX 0 0 0 0 0 0 0 0 LOW BYTE MULTIPLE COLLISION COUNT SINGLE COLLISION COUNT Revision 1 91 08 18 08 50 Each four bit counter is incremented every time the corresponding event as defined in the EPH STATUS REGISTER bit description occurs Note that the counters can only increment once per enqueued transmit packet never faster limiting the rate of interrupts that can be generated by the counters For example if a packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented by one If a packet experiences between 2 to
160. ually modified during run time HIGH A15 A14 A13 9 8 A7 A6 A5 BYTE 0 0 0 1 1 0 0 0 LOW Reserved Reserved BYTE 0 0 0 0 0 0 0 1 A15 A13 AQ A5 These bits are compared against the I O address on the bus to determine the IOBASE for the LAN91C111 s registers The 64k I O space is fully decoded by the LAN91C111 down to a 16 location space therefore the unspecified address lines A4 A10 A11 and A12 must be all zeros All bits in this register are loaded from the serial EEPROM The base decode defaults to 300h namely the high byte defaults to 18h Reserved Reserved bits Below chart shows the decoding of I O Base Address 300h 8 13 Bank 1 Individual Address Registers OFFSET NAME TYPE SYMBOL 4 THROUG INDIVIDUAL ADDRESS H9 REGISTERS READ WRITE IAR These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload The registers can be modified by the software driver but a STORE operation will not modify the EEPROM Individual Address contents Bit O of Individual Address 0 register corresponds to the first bit of the address on the cable SMSC LAN91C111 REV C 55 DATASHEET Revision 1 91 08 18 08 EP SMSE 10 100 Non PCI Ethernet Single Chip MAC PHY
161. up to nADS Rising 8 ns t9 A1 A15 AEN nBE 3 0 Hold After nADS Rising 5 ns t25 A4 A15 AEN to nLDEV Delay 30 ns 11 110 120 t9 Address AEN nBE 3 0 Le do nADS 116 17 u NI nCYCLE Write Data t21 t21 nSRDY Figure 14 8 Synchronous Write Cycle nVLBUS 0 SMSC LAN91C111 REV C 115 Revision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet PARAMETER MIN TYP MAX UNITS 8 1 15 3 0 Setup to nADS Rising 8 ns t9 A1 A15 AEN nBE 3 0 Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns 111 nCYCLE Hold after LCLK Rising Non Burst Mode 3 ns t16 W nR Setup to nCYCLE Active 0 ns t17A W nR Hold after Rising with nSRDY Active 3 ns 118 Data Setup to Rising Write 15 ns t20 Data Hold from LCLK Rising Write 4 ns t21 nSRDY Delay from LCLK Rising 7 ns t23 t20 t24 l t10 Clock Address AEN nBE 3 0 e nADS gt 116 W nR 111 nCYCLE EE Read Data t21 nSRDY nRDYRTN Figure 14 9 Synchronous Read Cycle nVLBUS 0 Revision 1 91 08 18 08 116 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet PARAMETER MIN TYP MAX UNITS t8 A1 A15 A
162. vision 1 91 08 18 08 DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSE Datasheet Asynchronous Cycle nADS 0 r2 nDATACS mw gt t4 Read Data valid 16A tt A p 15 nRD nWR 15A vrite Data im co Figure 14 3 Asynchronous Cycle nADS 0 PARAMETER MIN TYP MAX UNITS nDATACS Setup to nRD nWR Active 2 ns t2 nDATACS Hold After nRD nWR Inactive Assuming nADS Tied 5 ns Low t3A nRD Low to Valid Data 30 ns t4 nRD High to Data Invalid 2 15 ns 15 Data Setup to nWR Inactive 10 ns 15 Data Hold After nWR Inactive 5 ns t6A nRD Strobe Width 30 ns Address AEN nBE 3 0 nRD nWR t2 t26A t13 ARDY Data CL Val ata Figure 14 4 Asynchronous Ready Revision 1 91 08 18 08 112 SMSC LAN91C111 REV C DATASHEET 10 100 Ethernet Single Chip MAC PHY EP SMSC Datasheet PARAMETER MIN TYP MAX UNITS 126 ARDY Low Pulse Width 100 150 ns t26A Control Active to ARDY Low 10 ns 113 Valid Data to ARDY High 10 ns 15 18 4 21114 Clock t12A nDATACS _ Mime W nR t22A nCYCLE i Write Data C nRDYRTN t15 Figure 14 5 Burst Write Cycles nVLBUS 1 PARAMETER MIN TYP MAX UNITS t12 nDATACS Setup to LCLK Rising 20 n
163. x mode SWFDUP 0 2 When STP SQET 1 SWFDUP 0 SQET bit will be set upon completion of a transmit operation and no SQET Pulse has occurred during the IPG Inter Frame Gap If a pulse has occurred during the IPG SQET bit will not get set 3 Once SQET bit is set setting the TXENA bit in TCR register or via hardware software reset can clear this bit 16COL 16 collisions reached Set when 16 collisions are detected for transmit frame TXENA bit in TCR is reset Cleared when TXENA is set high LTX MULT Last transmit frame was a multicast Set if frame was a multicast Cleared at the start of every transmit frame MULCOL Multiple collision detected for the last transmit frame Set when more than one collision was experienced Cleared when TX SUC is high at the end of the packet being sent SNGLCOL Single collision detected for the last transmit frame Set when a collision is detected Cleared when TX SUC is high at the end of the packet being sent TX SUC Last transmit was successful Set if transmit completes without a fatal error This bit is cleared by the start of a new frame transmission or when TXENA is set high Fatal errors are 16 collisions 1 2 duplex mode only a SQET fail and STP SQET 1 1 2 duplex mode only Carrier lost and MON 1 1 2 duplex mode only Late collision 1 2 duplex mode only 8 7 Bank 0 Receive Control Register OFFSET NAME TYPE SYMBOL RECEIVE CONTROL 4 REGISTER READ WRIT

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