Home

SMC Networks SMC91C95 User's Manual

1. 139 Odl4 XH 93151999 YAEWNN 15X V ALda E ALda LON 1NI XL XL 1NI 1NI SNOILdO 1NI 32151999 5 15 1 993 1MI FIGURE 11 INTERRUPT GENERATION FOR TRANSMIT RECEIVE MMU 74 RX INTR Write Ad Ptr amp Read Word 0 from RAM Destination Multicast y Read Words 2 3 4 from RAM for Address Filtering Address iltering Pass Status Word OK Do Receive Lookahead y Get Copy Specs from Upper Copy Data Per Upper Layer Specs Y Issue Remove and Release Command Y Return to ISR FIGURE 12 RX INTR 75 Save Pkt Number Register Y Read TXDONE Pkt from FIFO Ports Reg Y Write Into Packet Number Register rite Address Pointer Register Y Read Status Word from RAM Y Update Statistics Re Enable Y Immediately Issue Release Command y Update Variables Y Acknowledge TXINTR y Read TX INT Again TX INT 0 Yes Restore Packet Number Y Return to ISR FIGURE 13 TX INTR Assumes Auto Release Option Selected 76 TXEMPTY INTR ip cc y Write Acknowledge Reg with TXEMPTY Bit
2. Memory ADDRESS 0 7 35 PCMCIA REGISTERS ADDRESS 8000 80 35 INTERNAL VS ATTRIBUTE MEMORY 36 THEORY OF 69 PACKET E APA ur 70 INTERNAL VS EXTERNAL ATTRIBUTE MEMORY 80 PCMCIA CONFIGURATION REGISTERS 82 FUNCTIONAL DESCRIPTION OF THE 91 BOARD SETUP 0 000 0 nnne nnne nnn nnn nnns 100 OPERATIONAL 104 TIMING DIAGRAMS iin dien Core 108 Related Documentation 1 POMCIA 2 1 Standard for PCMCIA timing and functionality 2 spec for multi function extensions 3 AT amp T HSM288xCF Modem Chip Set Data Sheet July 5 1994 4 Rockwell RC224ATF and C39 Modem Chip Sets Designer s Guide Network Interface e Four Direct Driven LEDs for Status Diagnostics e Integrates 10BASE T Transceiver Functions Software Drivers Driver and Receiver Link Integrity Test e
3. The Modem controller No No Register function and Modem SRESET Bit PCMCIA Configuration Registers except for the bit itself 33 POWERDOWN LOGIC pins and bits involved in powerdown are PWRDWN TXCLK Input pin valid when Pwrdwn bits in ECSR and MCSR registers Enable Function bits in ECOR and MCOR registers One bit for each function PWRDN Ethernet powerdown bit in Control WAKUP EN Magic packet receive enable The 1 XENDEC is not zero 0 2 One bit for each function 3 4 Register 5 bit in the Control Register 6 nWAKEUP Pin for Magic Packet receive Ethernet function powerdown 91 95 Powerdown States A The SMC91C95 is Off and no Clock is running B1 The SMC91C95 of Off with clock running No Active LAN or Host Data Transfer TBD Current Reduction with No Link Pulses for LAN access B2 The SMC91C95 of Off with clock running No C Active LAN or Host Data Transfer TBD Current Reduction with Link active The SMC91C95 is completely powered up With Active LAN or Host Data transfer Max 40MA typ PWRDWN TXCLK Pin B1 ECOR and ECSR Powerdown Bits B2 Power State MCOR and MCSR Bits B2 Power State WAKUP EN Control Register Table 6 Powerdown Functions POWERDOWN ENTERED When pin is high and reset is inactive Pwrdwn bit in ECSR is high or Enable Function bit in ECOR is low Pwrdwn bit in MCSR is high or En
4. nCE1 nCE2 nREG nWE 0 9 A15 nlORD nIOWR SPKROUT nMRESET MINT STSCHG RESET nIREQ nMCS 00015 SMC91C95 MRDY nlOIS16 nINPACK nWAIT MPWDN MRINGIN MRINGOB nFWE SPKRIN nOE 10BASE T AUI INTERFACE nRESET INT PHONE LINE ncs a RDY MODEM PWDN CHIPSET RINGIN RINGOUTB SPKR nWE nOE 00 07 0 EXTENDED ATTRIBUTE EPROM 2816 Optional CS SK DI DO SERIAL EPROM ISA Hy9346 PCMCIA Hy93c66 Figure 2 SMC91C95 System Block Diagram for Dual Function PCMCIA Card 19 BUS ADDRESS BUS CONTROL MODEM BUS INTERFACE INTERFACE MANAGEMENT ARBITER CSMA CD ENDEC r M TWISTED PAIR TRANSCEIVER Figure 3 SMC91C95 Internal Block Diagram 20 10BASE T FUNCTIONAL DESCRIPTION The SMC91C95 consists of an integrated Ethernet controller mapped entirely in I O space as well as support for an external Modem controller also mapped in I O space In addition PCMCIA attribute memory space is decoded to interface an external CIS ROM with configuration registers as per PCMCIA 3 X extensions implemented on chip in attribute space above the CIS ROM decode area The PCMCIA Configuration Registers are accessible also in I O spa
5. DESCRIPTION nExternal nXENDEC with pullup When tied low the SMC91C95 is configured ENDEC for external ENDEC When tied high or left open the SMC91C95 will use its internal encoder decoder E 1 117 Analog AVDD 5V analog power supply pins 120 Power 8 119 Analog AVSS Analog ground pins 127 Ground BUFFER TYPES O4 Output buffer with 2mA source and 4mA sink O162 Output buffer with 2mA source and 16mA sink O24 Output buffer with 12mA source and 24mA sink OD16 Open drain buffer with 16mA sink OD24 Open drain buffer with 24mA sink 1 024 Bidirectional buffer with 12mA source 24mA sink I Input buffer with TTL levels IS Input buffer with Schmitt Trigger Hysteresis Iclk Clock input buffer 17 10BASET CABLE SIDE SS3uaav d3ddng 1 1 1 1 NXLAdL 1 9159014 860160115 544 5033 35M9 9IN3U cSOI 1501 0501 003935 1033 C IVLX 6L 0V HMOIU 195539 3IV L IVLX 5031 I150M 9VI0 7 WIYAS tls 5 N31SAS Figure 1 SMC91C95 System Block Diagram for ISA Bus with Boot PROM 18
6. 9346 is typically the serial EEPROM used FIGURE 36 EEPROM READ 127 EESK Falling to EEDO EECS Changing 9346 is typically the serial EEPROM used FIGURE 37 EEPROM WRITE 128 REGISTER ADDRESS IOCHRDY nWAIT Z Parameter Pointer Register Reloaded to a Word of Data Prefetched into Data Register Note If t44 is not met IOCHRDY will be negated for the required time This parameter can be ignored if IOCHRDY is connected to the system FIGURE 38 MEMORY READ TIMING DATA POINTER ADDRESS REGISTER REGISTER Parameter Last Access to Data Register to Pointer Reloaded FIGURE 39 MEMORY WRITE TIMING 129 122 TXD nTXEN Delay from TXCLK Falling Parameter nCRS RXD Setup to RXCLK Falling nCRS RXD Hold after RXCLK Falling FIGURE 41 EXTERNAL ENDEC INTERFACE RECEIVE DATA RXD SAMPLED BY FALLING RXCLK 130 TWISTED PAIR DRIVERS AUI DRIVERS Parameter TPETXP to TPETXN Skew TPETXP N to TPETXDP N Delay TPE
7. LNI Hou 315I93 ASYN 0 c 315I593 Snivis 1 993LMI v ANI OLNI G3OH3IN SLdNYYALNI HSHd3 Eg M3SVIW3L MSVINHO 10 1 X5VII3 H3 ANT MC OLOALAG 3503 Ou 4 5 5 03IIV NHAO X Aldana 0315 e ALdlN3 LON NOIL314WOO XL NOIIVOOTIV 4 Oga XL FIGURE 9 INTERRUPT STRUCTURE 64 SPACE BANK OFFSET NAME TYPE SYMBOL 0 THROUGH 7 MULTICAST TABLE READ WRITE MT LOW BYTE MULTICAST TABLE 0 0 0 0 0 0 0 0 0 HIGH BYTE MULTICAST TABLE 1 0 0 0 0 0 0 0 0 LOW BYTE MULTICAST TABLE 2 0 0 0 0 0 0 0 0 HIGH BYTE MULTICAST TABLE 3 0 0 0 0 0 0 0 0 LOW BYTE MULTICAST TABLE 4 0 0 0 0 0 0 0 0 HIGH BYTE MULTICAST TABLE 5 0 0 0 0 0 0 0 0 LOW BYTE MULTICAST TABLE 6 0 0 0 0 0 0 0 0 HIGH BYTE MULTICAST TABLE 7 0 0 0 0 0 0 0 0 The 64 bit multicast table is used for group address set multicast addresses received filtering The hash value is defined as the six most significant bits of the CRC the destination addresses The three msb s determine the register to be used MTO MT7 while the other three determine the bit within the
8. Note Assuming NO WAIT ST 0 in configuration register and cycle time observed Note The cycle time is defined only for accesses to the Data Register as follows For Data Register Read From nIORD falling to next falling For Data Register Write From nlOWR rising to next nlOWR rising FIGURE 29 ISA CONSECUTIVE READ AND WRITE CYCLES 121 A0 15 ISA VALID ADDRESS AEN nSBHE nlOCS16 IOCHRDY 4 118 ig 4 to VALID DATA OUT Parameter Control Active to Low IOCHRDY Width when Data is Unavailable at Data Register Valid Data to IOCHRDY Inactive IOCHRDY is used instead of meeting 120 and 143 No Wait St bit is 1 IOCHRDY only negated if needed and only for Data Register access FIGURE 30 DATA REGISTER SPECIAL READ ACCESS 122 A0 15 ISA VALID ADDRESS AEN nSBHE nlOCS16 9 gt IOCHRDY VALID DATA IN Parameter min typ max Control Active to IOCHRDY Low 15 IOCHRDY Width when Data Register is Full 425 IOCHRDY is used instead of meeting t20 and t44 Wait St bit is 1 IOCHRDY only negated if needed and only for Data Register access FIGURE 31 DATA REGISTER SPECIAL WRITE ACCESS 123 A0 15 ISA VALID ADDRESS VALID ADDRESS AEN nlOWR nlORD
9. 1h BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG FIGURE 17 64 X 16 SERIAL EEPROM MAP FOR ISA MODE 103 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature 0 C to 70 C Storage Temperature Range 55 C to 150 C Lead Temperature Range soldering 10 seconds 325 C Positive Voltage on any pin with respect to Ground 2 0 3V Negative Voltage on any pin with respect to Ground 0 3V MAXIMUM cane hed HN Stresses above those listed above could cause permanent damage to the device This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied Note When powering this device from laboratory or system power supplies it is important that the Absolute Maximum Ratings not be exceeded or device failure can result Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output
10. The mapping and queuing functions of the MMU rely on the uniqueness of the packet number assigned to the requester For that purpose the packet number assignment is centralized at the MMU and a number will not be reused until the memory associated with it is released is clear that a packet number should not be released while the number is in the TX or RX packet queue The TX and ROV FIFOs are deep enough to handle the total number of packets the MMU 91 can allocate therefore there is no need for the programmer or the hardware to check FIFO full conditions ARBITER The function of the arbiter is to sequence packet RAM accesses as well as MMU requests in such a way that the on chip single ported RAM and a single MMU can be shared by two parties One party is the host CPU and the other party is the CSMA CD block The arbiter is address transparent namely any address can be accessed at any time In order to exploit the sequential nature of the access and minimize the access time on the system side the CPU cycle is buffered by the Data Register rather than go directly to and from memory Whenever a write cycle is performed the data is written into the Data Register and will be written into memory as a result of that operation allowing the CPU cycle to complete before the arbitration and memory cycle are complete Whenever a read cycle is performed the data is provided immediately from the Data Register without having
11. nlORD D0 15 nINPAC Parameter nlORD Delay to nREG Low to Control nCE1 nCE2 Setup to Control Cycle Time No Wait nREG Hold after Control nCE1 nCE2 Hold after Control Address Setup to Control Address Hold after Control nlORD Active to Data FIGURE 23 PCMCIA CONSECUTIVE READ CYCLES 115 A0 9 A15 nCE1 nCE2 Parameter nREG Low Setup to Control Active nCE1 nCE2 Setup to Control Active nREG Hold after Control Inactive nCE1 nCE2 Hold after Control Inactive Address Setup to Control Active Address Hold after Control Inactive Cycle Time No Wait States Write Data Setup to nIOWR Rising Write Data Hold after nIOWR Rising FIGURE 24 CONSECUTIVE PCMCIA WRITE CYCLES 116 A0 9 A15 By valid valid nREG nCE1 Parameter nWE to nFWE Delay Address nREG nCE1 Delay to nFCS FIGURE 25 PCMCIA ATTRIBUTE MEMORY READ WRITE A15z0 117 nMPWDN MRINGOUTB MEME EU t1 MRINGOUTB Pulse Exiting Powerdown ti MRINGOUTB Pulse Entering Powerdown FIGURE 26 RINGOUT FOR L39 C39 ROCKWELL MODEMS ENTERING EXITING POWERDOWN 118 0 15 AEN nSBHE VALID ADDRESS VALID ADDRESS gt 115 gt nlOCS16 57 120 6 z t6 VALID
12. 01 5 IV GALSIML Haddnag 553900V 2 x E 80 i HOVAYALNI VI0C9 33 FIGURE 7 SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH 28 PACKET FORMAT IN BUFFER MEMORY word is used to specify the total number of bytes and that in turn is followed by the data The packet format in memory is similar for the area The data area holds the packet itself and TRANSMIT and RECEIVE areas The first its length is determined by the byte count The word is reserved for the status word the next packet memory format is word oriented RAM OFFSET DECIMAL 0 STATUS WORD RESERVED BYTE COUNT always even DATA AREA LN SF CONTROL BYTE LAST DATA BYTE if odd FIGURE 8 DATA PACKET FORMAT TRANSMIT PACKET RECEIVE PACKET Written by CSMA upon transmit Written by CSMA upon receive completion see Status completion see RX Frame Register Status Word CONTROL BYTE Written by CPU to control Written by CSMA Also has ODD EVEN data bytes ODD EVEN bit 29 BYTE COUNT Divided by two it defines the total number of words including the STATUS WORD the BYTE COUNT WORD the D
13. LOW DATA BYTE EEPROM that is normally protected from accidental Store operations This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set This allows generic EEPROM read and write routines that do not affect the basic setup of the SMC91C95 SPACE BANK1 OFFSET CONTROL REGISTER HIGH BYTE LOW BYTE BAD When set bad CRC packets are received When clear bad CRC packets do not generate interrupts and their memory is released PWRDN Active high bit used to put the Ethernet function in powerdown mode Cleared by 1 A write to any register in the SMC91C95 I O Space 2 Hardware reset 3 Magic Packet was received This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down WAKUP EN Active high bit used to enable the controller in any of the powerdown modes to power up if a Magic Packet is detected and set the WAKEUP bit in the EPHSR to generate an EPH interrupt if not masked When clear 0 no Magic Packet scanning is done on receive packets NOTE If Magic Packet is enabled using this bit only the notification is done on the WAKEUP bit in the EPHSR only TYPE READ WRITE SYMBOL CTR PWRDWN WAKEU AUTO 1 BAD P EN RELEASE 0 0 0 0 0 X X 1 LE CR TE EEPROM RELOAD STORE ENABLE ENABLE ENABLE SELECT 0 0 0 X X 0
14. VALID DATA OUT Wean VALID DATA IN Parameter min typ units Address nSBHE AEN Setup to Control Active nlORD Low to Valid Data Data Setup to nlOWR Rising Data Hold after nlOWR Rising 25 30 9 ns ns ns ns FIGURE 32 8 MODE REGISTER CYCLES Age ADDRESS VALID nMEMRD ele Parameter Address Setup to Control Active Address Hold after Control Inactive 116 nMEMRD Low to nROM Low 117 nMEMRD High to nROM High BALE tied high FIGURE 33 EXTERNAL ROM READ ACCESS 124 0 15 nSBHE VALID t2 5 BALE nlOCS16 uw EXE Parameter Address nSBHE Setup to BALE Falling Address nSBHE Hold after BALE Falling Address nSBHE AEN Setup to Control Active AEN Hold after Control Inactive A4 A15 AEN Low BALE High to nlOCS16 Low not needed nlOCS16 not relevant in 8 bit mode FIGURE 34 ISA REGISTER ACCESS WHEN USING BALE 125 Address Setup BALE Falling Address Hold after BALE Falling Address Setup to Control Active nMEMRD Low to nROM Low nMEMRD High to nROM High FIGURE 35 EXTERNAL ROM READ ACCESS USING BALE 126 EESK Falling to EEDO EECS Changing
15. Bal e E 0 08 0 003 Ex EX 0 ITT 3 GAGE PLANE 0 25 MILLIMETER INCH SYMBOL MIN NOM MIN NOM MAX A1 0 05 0 10 0 15 0 002 0 004 0 006 A2 0 95 1 00 1 05 0 037 0 039 0 041 0 13 0 18 0 23 0 005 0 007 0 009 0 09 0 20 0 004 0 008 13 90 14 00 14 10 0 547 0 551 0 555 13 90 14 00 14 10 0 547 0 551 0 555 0 40 0 016 Hd 15 90 16 00 16 10 0 626 0 630 0 634 He 15 90 16 00 16 10 0 626 0 630 0 634 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Y 0 08 0 003 8 0 7 0 7 FIGURE 47 VTOFP PACKAGE OUTLINE 136 Circuit diagrams utilizing SMC products are included as a means illustrating typical applications consequently complete information sufficient for construction purposes is not necessarily given The information has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies Furthermore such information does not convey to the purchaser of the semiconductor devices 300 Kennedy Drive described any licenses under the patent rights of SMC or others SMC reserves the right Hauppauge NY 11788 to make changes at any time in order to improve design and supply the best product possible 516 435 6000 SMC91C95 Rev 08 08 96 FAX 516 231 6004
16. Receive Drivers Differential signals received off the twisted pair network or AUI cable are directed to the internal clock recovery circuit prior to being decoded for the MAC Manchester Decoder and Clock Recovery The PHY performs timing recovery and Manchester decoding of incoming differential signals in 10BASE T or AUI modes with its built in phase lock loop PLL The decoded NRZ data RXD and the recovered clock RXCLK becomes available to the MAC typically within 9 bit times 5 for AUI after the assertion of nCRS The receive clock RXCLK is phase locked to the transmit clock in the absence of a received signal idle Squelch Function The integrated smart squelch circuit employs a combination of amplitude timing measurements to determine the validity of data received off the network It prevents noise at the differential inputs from falsely triggering the decoder in the absence of valid data or link test pulses Signal levels below 300mV 180mV for AUI or pulse widths less than 15ns at the differential inputs are rejected Signals above 585mV 300mV for AUI and pulse widths greater than 30 will be accepted When using the extended cable mode with 10BASE T media which extends beyond the standard limit of 100 meters the squelch level can optionally be set to reject signals below 180mV and accept signals above 300mV If the input signal exceeds the squelch requirements the carrier sense output nCRS is ass
17. The PHY encodes the transmit data received from the MAC The encoded data is directed internally to the selected output driver for transmission over the twisted pair network or the AUI cable Data transmission and encoding is initiated by the Transmit Enable input TXE going low Transmit Drivers The encoded transmit data passes through to the transmit driver pair TPETXP N and its complement TPETXDP N Each output of the transmit driver pair has a source resistance of 10 ohms maximum and a current rating of 25 mA maximum The degree of predistortion is determined by the termination resistors the equivalent resistance should be 100 ohms Jabber Function This integrated function prevents the DTE from locking into a continuous transmit state In 10BASE T mode if transmission continues beyond the specified time limit the jabber function inhibits further transmission asserts the collision indicator nCOLL The limits for jabber transmission are 20 to 15 ms in 10BASE T mode In the AUI mode the jabber function performed external transceiver SQE Function In the 10BASE T mode the PHY supports the signal quality error SQE function At the end of a transmission the PHY asserts the nCOLL signal for 10 5 bit times beginning 0 6 to 1 6ms after the last positive transition of a transmitted frame In the AUI mode the SQE 98 function is the external transceiver performed by Receive Functions
18. Transmit Deferred When set carrier was detected during the first 6 4 usec of the inter frame gap Cleared at the end of every packet sent LTX_BRD Last transmit frame was a broadcast Set if frame was broadcast Cleared at the start of every transmit frame SQET Signal Quality Error Test The transmitter opens a 1 6 usec window 0 8 usec after transmission is completed and the receiver returns inactive During this window the transmitter expects to see the SQET signal from the transceiver The absence of this signal is a Signal Quality Error and is reported in this status bit Transmission stops and EPH INT is set if STP SQET is in the TCR is also set when SQET is set This bit is cleared by setting TXENA high 16COL 16 collisions reached Set when 16 collisions are detected for a transmit frame 43 TXENA bit in TCR is reset Cleared when TXENA is set high LTX MULT Last transmit frame was a multicast Set if frame was a multicast Cleared at the start of every transmit frame MULCOL Multiple collision detected for the last transmit frame Set when more than one collision was experienced Cleared when TX SUC is high at the end of the packet being sent SNGLCOL Single collision detected for the last transmit frame Set when a collision is detected Cleared when TX SUC is high at the end of the packet being sent TX SUC Last transmit was successful Set if transmit completes without a fatal error This bit
19. lo 16 mA High Output Level lou 2 mA Output Leakage Vin 0 to Voc OD24 Type Buffer Low Output Level Output Leakage lo Supply Current Active loc All pins except pin under test tied to AC ground Clock Input Capacitance ET gt Input Capacitance Output Capacitance PARAMETER SAMBO FATE SB 106 PARAMETER MIN MAX UNITS 10BASE T Receiver Threshold Voltage 12 100 Receiver Common Mode Range 0 Vo Transmitter Output Voltage 22 22 5 23 Source Resistance 10 ohms Transmitter Output DC Offset 1 55 w Transmitter Backswing Voltage to Idle PERENNE Differential Input Voltage 0585 Receiver Threshold Voltage Receiver Range 0 Transmitter Backswing Voltage to Input Differential Voltage 303 Output Short Circuit to Voc GND Current Differential Idle Voltage measured 8 0 us after last positive transition of data frame CAPACITIVE LOAD ON OUTPUTS nlOCS16 IOCHRDY 240 pF INTRO INTR3 120 pF All other outputs 45 pF 107 TIMING DIAGRAMS H 4 12 gt 0 min t3 y 15 mmo i Adress Access Time 300 ns 0 nREGAcessTme ns _ gt gt gt gt gt 4 Access T
20. AND ALLOCATE ROUTINES 78 Unlike other controllers the SMC91C95 does not require a fixed memory partitioning between transmit and receive resources The MMU allocates and de allocates memory upon different events An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation Memory is always requested by the side that needs to write into it that is the CPU for transmit or the CSMA CD for receive The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand Furthermore the receive process requests will be dependent on network traffic in particular on the arrival of broadcast and multicast packets that might not be for the node and that are not subject to upper layer software flow control In order to prevent unwanted traffic from using too much memory the CPU can program a memory reserved for transmit parameter II the free memory falls below the memory reserved for transmit value MMU requests from the CSMA CD block will fail and the packets will overrun and ignored Whenever enough memory is released packets can be received again II the reserved value is too large the node might lose data which is an abnormal condition If the value is kept at zero memory allocation is handled on first come first served basis for the entire
21. Configuration Registers Address 8000 803Eh The PCMCIA Configuration Registers are stored inside the SMC91C95 above the external Attribute Memory address space These registers are used to configure and control the PCMCIA related functionality of the Ethernet and Modem functions These registers are eight bits wide and reside on even locations The SMC91C95 ignores odd accesses to this area ignore writes do not drive the bus on reads This address offset has been changed from prior SMC9000 PCMCIA designs to allow a larger address range for other attribute memory data This data could be a larger card information structure or a XIP data image Internal VS External Attribute Memory The Internal VS External EPROM attribute memory decodes are shown below This allows the designer to not require an external EPROM device if the single or multi function PCMCIA card needs less than 512 bytes of configuration information As can be seen in the map if 512 bytes of CIS or less is required the nFCS and SMC91C95 need be used if serial EEPROM is being used Internal to the SMC91C95 the memory addressing logic will allow byte or word on odd byte address access 0 1 the SMC91C95 will generate an arbitrary value of zero 0 since the PCMCIA specification states that the high byte of a word access in attribute memory is a don t care This allows backward compatibility to 8 bit hosts nFWE output pins of the Table 7 Attri
22. If this possibility exists it is suggested that a clamp circuit be used DC ELECTRICAL CHARACTERISTICS 0 C 70 C Vcc 5 0 10 PARAMETER UNITS COMMENTS I Type Input Buffer Low Input Level Viu TTL Levels High Input Level Input Buffer Low Input Level V IS Type Input Buffer Low Input Level V Schmitt Trigger High Input Level Schmitt Trigger Schmitt Trigger Hysteresis mV V High Input Level 104 90180 UNITS COMMENTS Input Leakage and IS buffers except pins with pullups pulldowns Low Input Leakage High Input Leakage IP Type Buffers Input Current 150 Vin ID Type Buffers Input Current 1 04 Type Buffer Vin Low Output Level lo 4 mA High Output Level lou 2 mA Vin 010 Voc VoL V 2 4 V Output Leakage lot 10 1 024 Low Output Level VoL V lo 24 mA High Output Level VoH 2 4 V 12 mA Output Leakage lon 10 Vin 0 to Vcc 024 Type Buffer VoL V 2 4 V lo 10 Low Output Level lo 24 mA High Output Level 12 mA Output Leakage Vin 0 to Vcc 04 Type Buffer Low Output Level lo 4 mA High Output Level lou 2 mA Output Leakage Vin 0 to Vcc 105 ii dd OD16 Type Buffer Low Output Level lo 16 mA Output Leakage Vin 0 to Vcc OD162 Type Buffer Low Output Level
23. ODI or NDIS drivers is supported by copying a small part of the received packet and letting the upper layer provide a pointer for the rest of the data If the upper layer indicates it does not want a specific part of the packet a block move operation starting at any particular offset can be done Out of order receive processing is also supported if memory for one packet is not yet available receive packet processing can continue Efficiency Lacking any level of indirection or linked lists of pointers virtually all the memory is used for data There are not descriptors forward links and pointers at all This simplicity and memory efficiency is accomplished without giving up the benefits of linked lists which is unlimited back to back transmission reception without CPU intervention for as long as memory is available FULL DUPLEX ETHERNET SUPPORT Full Duplex Ethernet operation refers to the ability of the network or parts of it to simultaneously transmit and receive packets The CSMA CD protocol used by Ethernet for accessing a shared medium is inherently half duplex and so is the 10BASE T physical layer where simultaneous transmit and receive activity is interpreted as a collision The SMC91C95 supports two types of Full Duplex operation 1 Full Duplex mode for diagnostic purposes only where the received packet is the transmit packet being looped back This mode is enabled using the FDUPLX bit in the TCR In this
24. be written into memory later The memory arbitration request is generated as a function of that FIFO being not empty The nature of the cycle requested byte word is determined by the Isb of the pointer and the number of bytes in the FIFO When read operations occur words are pre fetched upon pointer loading in order to have at least a word ready in the FIFO to be read New pre fetch cycles are requested as a function of the number of bytes in the FIFO For example if an odd pointer value is loaded first a byte is pre fetched into the FIFO and immediately a ful word is pre fetched completing three bytes into the FIFO If the CPU reads a word one byte will be left again a new word is pre fetched In the case of write if an odd pointer value is loaded and a full word is written the FIFO holds two bytes the first of which is immediately written into an odd memory location If by that time another byte or 102 word was written there will be two or three bytes in the FIFO and a full word can be written into the now even memory address When CSMA CD cycle begins the arbiter will route the CSMA CD DMA addresses to the MMU as well as the packet number associated with the operation in progress full duplex mode receive and transmit requests are alternated in such a way that the CPU arbitration cycle time is not affected 16 BITS WORD ADDRESS um ULT cre 295027092 Oh CONFIGURATION REG
25. facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts are generated on successful transmissions Reading the register in the transmit service routine will be enough to maintain statistics SPACE BANKO OFFSET NAME 8 MEMORY INFORMATION REGISTER HIGH BYTE 0 0 0 LOW BYTE 0 0 0 FREE MEMORY AVAILABLE This register can be read at any time to determine the amount of free memory The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command SMC91C90 SMC91C90 SMC91C92 4 SMC91C95 SMC91C100 1 1 REGISTER 46 TYPE READ ONLY SYMBOL MIR FREE MEMORY AVAILABLE IN BYTES 256 M 1 0 0 0 MEMORY SIZE BYTES 4256 1 0 0 0 MEMORY SIZE This register can be read to determine the total memory size and will always read 18H 6144 bytes for the SMC91C95 1 64 kbytes ACTUAL MEMORY 16 kbytes 4608 bytes 6144 bytes 128 kbytes SPACE BANKO OFFSET NAME A MEMORY CONFIGURATION REGISTER HIGH BYTE 0 LOW BYTE 0 0 0 MEMORY RESERVED FOR TRANSMIT Programming this value allows the host CPU to reserve memory to be used later for transmit limiting the amount of memory that receive packets can use up When programmed for zero the memory allocation between transmit and receive is completely dynamic When programmed for a non zero value the allocation is dynamic if the free
26. is cleared by the start of a new frame transmission or when TXENA is set high Fatal errors are 16 collisions SQET fail and STP SQET 1 FIFO Underrun Carrier lost and MON CSN 1 Late collision SPACE BANKO OFFSET NAME 4 RECEIVE CONTROL REGISTER HIGH BYTE LOW BYTE SOFT RST Software activated Reset Active high Initiated by writing this bit high terminated by writing the bit low The SMC91C95 configuration is not preserved except for Configuration Base and IAO IA5 Registers The EEPROM in both ISA and PCMCIA mode is not reloaded after software reset CAR Filter Carrier When set filters leading edge of carrier sense for 12 bit times Otherwise recognizes a receive frame as soon as carrier sense is active STRIP CRC When set it strips the CRC on received frames When clear the CRC is stored in memory following the packet Defaults low TYPE READ WRITE SYMBOL RCR SOFT _ FILT_ STRIP RXxEN RST CAR CRC 0 0 0 0 0 0 0 0 ALMUL PRMS RX_ ABORT 0 0 0 0 0 0 0 0 RXEN Enables the receiver when set If cleared completes receiving current frame and then goes idle Defaults low on reset ALMUL When set accepts all multicast frames frames in which the first bit of DA is 17 When clear accepts only the multicast frames that match the multicast table setting Defaults low PRMS Promiscuous mode When set receives all frames Does not receive its own transmission unless i
27. memory capacity Note that with the memory management built into the SMC91C95 the CPU can dynamically program this parameter For instance when the driver does not need to enqueue transmissions it can allow more memory to be allocated for receive by reducing the value of the reserved memory Whenever the driver 79 needs to burst transmissions it can reduce the receive memory allocation The driver program the parameter as a function of the following variables 1 Free memory read only register 2 Memory size read only register The reserved memory value can be changed on the fly If the MEMORY RESERVED FOR TX value is increased above the FREE MEMORY receive packets in progress are still received but no new packets are accepted until the FREE MEMORY increases above the MEMORY RESERVED value INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller For that purpose there is no register reading necessary before the next element in the queue namely transmit or receive packet can be handled by the controller The transmit and receive results are placed in memory The receive interrupt will be generated when the receive queue FIFO of packets is not empty and receive interrupts are enabled This allows the interrupt service routine to process many re
28. memory exceeds the programmed value while receive allocation requests are denied if the free memory is less or equal to the programmed value This register defaults to zero upon reset It is not affected by the RESET MMU command DEVICE 0 SYMBOL Lower Byte MCR READ WRITE Upper Byte READ ONLY 0 1 1 0 0 1 1 MEMORY RESERVED FOR TRANSMIT BYTES 256 0 0 0 0 The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE If the memory allocated for transmit plus the reserved space for transmit is required to be constant rather than grow with transmit allocations the CPU should update the value of this register after allocating or releasing memory The contents of MIR as well as the low byte of MCR are specified in 256 M bytes The multiplier M is determined by bits 11 10 and 9 as follows Bits 11 10 and 9 are read only bits used by the software driver to transparently run on different controllers of the SMC9000 family M MAX MEMORY SIZE FEAST o 1 2 5 91 90 1 1 2862561 6k future 1 1 4 Future 1 SA rum s t 47 SPACE BANK1 OFFSET NAME TYPE SYMBOL 0 CONFIGURATION REGISTER READ WRITE CR The Configuration Register holds bits that define the device configurati
29. packet numbers the packet being transmitted If the packet numbers match and the logical address of the packet being transmitted exceeds the address being loaded the packet transmission is aborted and Underrun is reported in the transmit status word NOTE If AUTO INCR is not set and 16 bits are used the pointer must be loaded with an even value If AUTO INCR is not set and 8 bit allows even and odd values writes are used consecutive writes to the data register for the same pointer same memory address value is not allowed even and odd pointer values are always allowed SPACE BANK2 OFFSET 8 THROUGH Ah NAME DATA REGISTER TYPE READ WRITE SYMBOL DATA DATA HIGH DATA LOW DATA REGISTER Used to read or write the data buffer byte word presently addressed by the pointer register This register is mapped into two uni directional FIFOs that allow moving words to and from the SMC91C95 regardless of whether the pointer address is even or odd Data goes through the write FIFO into memory and is pre fetched from memory into the read FIFO If byte accesses are used the appropriate next byte can be accessed through the Data Low or Data High registers The order to and from the FIFO is preserved Byte and word accesses can be mixed on the fly in any order This register is mapped into two consecutive word locations to facilitate the usage of double word move instructions The DATA register is accessible
30. path transmit and receive interfaces Statistical counters are kept by the CSMA CD block and are readable through the appropriate register The counters are four bits each and can generate an interrupt when reaching their maximum values Software can use that interrupt to update statistics in memory or it can keep the counter interrupt disabled while relying on the transmit interrupt routine reading the counters Given that the counters can increment only once per transmit this technique is a good complement for the single interrupt per sequence strategy The interface between the CSMA CD block and memory is word oriented Two bi directional FIFOs make the data path interface Whenever a normal collision occurs less than 16 retries half duplex mode the CSMA CD will trigger the backoff logic and will indicate the DMA logic of the collision The DMA is responsible for restarting the data transfer into the CSMA CD block regardless of whether the collision happened on the preamble or not Only when 16 retries are reached the CSMA CD block will clear the TXENA bit and CPU intervention is required The DMA will not automatically restart data transfer in this case nor will it transmit the next enqueued packet until TXENA is set by the CPU The DMA will move the packet number in question from the TX FIFO into the TX completion FIFO NETWORK INTERFACE The SMC91C95 includes both an AUI interface for thick and thin coax applicat
31. purpose register NORMAL EEPROM OPERATION EEPROM SELECT bit 0 a On EEPROM read operations after reset or after setting RELOAD high the CONFIGURATION REGISTER and BASE REGISTER are updated with the EEPROM values at locations defined by the 52 0 pins The INDIVIDUAL ADDRESS registers are updated with the values stored the INDIVIDUAL ADDRESS area of the EEPROM On EEPROM write operations after setting the STORE bit the values of the CONFIGURATION REGISTER and BASE REGISTER written the locations defined by the 1052 0 pins The three least significant bits of the CONTROL REGISTER EEPROM SELECT RELOAD and STORE are used to control the EEPROM Their values are not stored nor loaded from the EEPROM b GENERAL PURPOSE REGISTER EEPROM SELECT bit 1 On EEPROM read operations after setting RELOAD high the EEPROM word address defined by the POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER On EEPROM write operations after setting the STORE bit the value of the GENERAL PURPOSE REGISTER is written the EEPROM word address defined by the POINTER REGISTER 6 least significant bits RELOAD and STORE are set by the user to initiate read and write operations respectively Polling the value until read low is used to determine completion When EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high No ot
32. receiver switches back to the transmitter within 9 bit times Following transmission the transmitter performs a SQE test This test exercises the collision detection circuitry within the 10BASE T interface In full duplex mode carrier sense is asserted during receive activity only The receiver monitors the media at all times It recovers the clock and data and passes it along to the controller In the absence of any receive activity the transmitter is looped back to the receiver In addition the receiver performs automatic polarity correction The 10BASE T interface performs link integrity tests per section 14 2 1 7 of 802 3 using the following values Link loss timer 64 ms Link test min timer 4 ms Link count 2 Link test max timer 64 ms AUN The state of the link is reflected in the EPHSR AUI The SMC91C95 also provides a standard 6 wire AUI interface to a coax transceiver PHYSICAL INTERFACE The internal physical interface PHY consists of an encoder decoder ENDEC and an internal 10BASE T transceiver The ENDEC also provides a standard 6 pin AUI interface to an external coax transceiver for 10BASE T and 10BASE 5 applications The signals between MAC and the PHY can be routed to pins by asserting the nXENDEC pin low This feature allows the interface to an external ENDEC and transceiver The PHY functions can be divided into transmit and receive functions Transmit Functions Manchester Encoding
33. register the appropriate bit in the table is set the packet is received If the ALMUL bit in the RCR register is regardless of the multicast table values Hashing is only a partial group addressing filtering scheme but being the hash value available as part of the receive status word the receive routine can reduce the search time significantly With the proper memory structure the search is limited to comparing only the multicast addresses that have the actual hash value in question SPACE BANK3 OFFSET NAME TYPE SYMBOL 8 MANAGEMENT INTERFACE READ WRITE MGMT HIGH nXNDE 1052 1051 1050 0 0 1 1 LOW MDOE MCLK MDI MDO BYTE 0 0 1 1 0 0 0 0 nXNDEC Read only bit reflecting the status of MDI Reads the value of the EEDI pin the nXENDEC pin MDCLK The value of this bit drives the EESK pin IOS0 IOS2 Read only bits reflecting the status of when MDOE 1 the 1050 1052 pins MDOE When this bit is high pins EEDO EECS MDO The value of this bit drives the EEDO pin and EESK will be used for transceiver when MDOE 1 management functions otherwise the pins assume the EEPROM values EEDO Serial EEPROM Data Out Bit MDO EESK Serial EEPROM Clock Bit MCLK EECS Serial EEPROM Chip Select 66 SPACE BANK3 OFFSET NAME TYPE SYMBOL A REVISION REGISTER READ ONLY REV HIGH BYTE 0 0 1 1 0 0 1 1 LOW CHIP REV BYTE 0 1 0 0 0 0 0 0 CHIP Chip ID Can be used by software drivers REV Revision ID I
34. serial EEPROM and internal SMC91C95 SRAM the data to memory mapping is shown in Table 10 Table 10 PCMCIA to SRAM Memory HOST ADDRESS HEX DATA IN WORDS IN BYTES Data byte 0 Word 1 Low Byte Byte 0 Don t Care Data byte 1 Word 1 High Byte Byte1 Don t Care Data byte 2 Word 2 Low Byte Byte2 Don t Care Data byte 3 Word 2 High Byte Byte3 Data byte 1FC Word FE Low Byte Byte FC Don t Care Data byte 1FD Word FE High Byte Byte1FD Don t Care Data byte 1FE Word FF Low Byte Byte1FE Don t Care Data byte 1FF Word FF High Byte Byte1FF Don t Care NOTE This memory map assumes a 4096 bit Serial EEPROM in PCMCIA mode 55 SPACE 2 OFFSET NAME TYPE SYMBOL 0 MMU COMMAND REGISTER WRITE ONLY MMUCR BUSY Bit Readable This register is used by the CPU to control the memory allocation de allocation TX FIFO and RX FIFO control The three command bits determine the command issued as described below HIGH BYTE LOW Dee id COMMAND SET xyz 000 0 NOOP NO OPERATION 001 1 ALLOCATE MEMORY FOR TX N2 N1 NO defines the amount of memory requested as value 1 256 bytes Namely N2 N1 NO 1 will request 2 256 512 bytes Valid range for N2 N1 NO is 0 through 5 shift based divide by 256 of the packet length yields the appropriate value to be used as N2 N1 NO Immediately generates a completion code at the ALLOCATION RESULT REGISTER Can optional generate an interrup
35. signal is the inverse of the MRINGIN input When the PWRDWN bit is set or the function is disabled this output is low This signal is activated about 12 msec after removing Powerdown 4 Modem Ring MRINGOB O Ring output signal When the modem is not in Output B Powerdown mode PWRDWN bit is zero and the function is enabled this output follows the value of the MRINGIN input When entering Powerdown mode a rising edge is generated on the pin A rising edge is also generated when exiting Powerdown mode also Refer to Figure 2 14 Speaker SPKRIN with pullup Speaker Input This is a digitized single level Input audio input from the modem controller 15 Speaker SPKROUT tri stable Speaker Output This pin reflects the SPKRIN with pullup pin when enabled by the AUDIO bit Modem CSR bit 3 When disabled this pin is tri stated nMPDOUT Schmitt Used to control Powerdown mode Tie to a 180K pull up and a 0 1uF cap to ground Tie high when not used This signal is used in the RC time constant MFBK1 Tie to nMPDOUT through a 5 1M resistor This signal is used in the RC time constant in conjuction with the nMPDOUT pin MEE ELE EM SYMBOL DESCRIPTION n16 Bit nMIS16 I with pullup Input When low it indicates a 16 bit modem Modem otherwise the modem is 8 bit wide Used to determine if nlOIS16 PCMCIA and nlOCS16 ISA need to be asserted for modem cycles The value of this p
36. the memory used by this packet Remove packet number from completion FIFO by writing TX INT Acknowledge Register 71 CSMA CD SIDE The enqueued packet will be transferred to the CSMA CD block as a function of TXENA n TCR bit and of the deferral process in half duplex mode state Upon transmit completion the first word in memory is written with the status word The packet number is moved from the TX FIFO into the TX completion FIFO Interrupt is generated by the TX completion FIFO being not empty 1 TYPICAL FLOW OF EVENTS FOR RECEIVE S W DRIVER ENABLE RECEPTION By setting the RXEN bit SERVICE INTERRUPT Read the Interrupt Status Register and determine if RCV INT is set The next receive packet is at receive area Its packet number can be read from the FIFO Ports Register The software driver can process the packet by accessing the RX area and can move it out to system memory if desired When processing is complete the CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number 72 CSMA CD SIDE A packet is received with matching address Memory is requested from MMU packet number is assigned to it Additional memory is requested if more pages are needed The internal DMA logic generates sequential addresses and writes the receive words into memory The MMU does the sequential to physical address translation If overrun packet is dropped and
37. to arbitrate and complete a memory cycle The present cycle results in an arbitration request for the next data location Loading the pointer causes a similar pre fetch request This type of read ahead and write behind arbitration allows the controller to have a very fast access time and would work without wait states for as long as the cycle time spec is satisfied The values are 40 ns access time and 185ns cycle time By the same token CSMA CD cycles might be postponed The worst case CSMA CD latency for arbiter service is one memory cycle The arbiter uses the pointer register as the CPU provided address and the internal DMA address from the CSMA CD side as the addresses to be provided to the MMU The data path routed by the arbiter goes between memory the data path does not go through the MMU on one side and either the CPU side bus or the data path of the CSMA CD core The data path between memory and the Data Register is in fact buffered by a small FIFO in each direction The FIFOs beneath the Data Register can be read and written as bytes or words in any sequential combination The presence of these FIFOs makes sure that word transfers are possible on the system bus even if the address loaded into the pointer is odd BUS INTERFACE The bus interface handles the data address and control interfaces as a superset of the ISA and PCMCIA specifications and allows 8 or 16 bit adapters to be designed with the SMC91C95
38. two eight bit registers in that case the offset of each one is independently specified Regardless of the functional description when the SMC91C95 is in 16 bit mode all registers be accessed as words or bytes The default bit values upon hard reset are highlighted below each register Table 9 Internal I O a E Mapping CONFIG MCOR COMMAND low byte low byte ECSR MCSR high byte high byte EPH BASE PNR ARR MT2 STATUS low byte IAO IA1 FIFO PORTS MT4 EBASEO IOEIR high byte low byte MBASEO high byte COUNTER 2 MT6 MT7 EBASE1 MBASE1 low byte low byte IA4 IA5 DATA MGMT Msize high byte GENERAL DATA REVISION PURPOSE RESERVED CONTROL INTERRUPT 0 SELECT SELECT SELECT SELECT 38 BANK SELECT REGISTER OFFSET NAME E BANK SELECT REGISTER HIGH BYTE LOW BYTE 52 851 850 Determine the bank presently in use The BANK SELECT REGISTER is always accessible except in PCMCIA powerdown mode and is used to select the register bank in use The upper byte always reads as 33h and can be used to help determine the location of the SMC91C95 TYPE READ WRITE SYMBOL BSR 0 0 1 1 0 0 1 1 X X X X X 0 0 0 The BANK SELECT REGISTER is always accessible regardless of the value of BS0 BS2 The SMC91C95 implements o
39. with Input Active low write strobe used to access pullup the SMC91C95 IO space nMEMR IS with ISA Active low signal used by the host pullup processor to read from the external ROM nOutput PCMCIA Output Enable input used to read Enable from the COR CSR and attribute memory nModem nMRESET O4 Reset output to Modem Asserted whenever Reset RESET pin is high internal POR is active or SRESET bit is high MCOR bit 7 Modem MINT with pull Interrupt input from Modem Reflected in Interrupt down INTR CSR bit 1 and asserts the appropriate interrupt pin if enabled nModem nMCS O4 Chip select output to modem Chip Select MRDY I with pullup Modem ready input Low indicates the modem is not ready either after reset or exiting from stop or sleep modes nModem nMPWDN O4 Powerdown output to modem controller This Powerdown pin is active low when either the PWRDWN bit CSR bit 2 is set or the modem is disabled not configured 12 DESCRIPTION OF PIN FUNCTIONS NAME DESCRIPTION Modem Ring MRINGIN Input Powerdown output to modem controller This pin is active high when either the PWRDWN bit CSR bit 2 is set or the modem is disabled not configured Ring input from the modem controller Toggles when ringing low when not ringing nMRINGOA O4 Ring output signal When there is no ringing Ring Output on the MRINGIN pin and the modem is not in A Powerdown mode this output is high During ringing this
40. written by the controller as ODD If set indicates odd number of bytes with the last byte being right before the CONTROL BYTE II clear the number of data bytes is even and the byte before the CONTROL BYTE should be ignored RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory It is not available as a register ALGN BROD BAD ODD TOOLN TOO ERR CAST CRC FRM G SHORT HASH VALUE HIGH BYTE LOW BYTE ALGNERR Frame had alignment error BRODCAST Receive frame was broadcast BADCRC Frame had CRC error ODDFRM This bit when set indicates that the received frame had an odd number of bytes TOOLNG The received frame is longer than 802 3 maximum size 1518 bytes on the cable TOOSHORT The received frame is shorter than 802 3 minimum size 64 bytes on the cable MULT CAST HASH VALUE Provides the hash value used to index the Multicast Registers Can be used by receive routines to speed up the group address search The hash value consists of the six most significant bits of the CRC calculated on the Destination Address and maps into the 64 bit multicast table Bits 5 4 3 of the hash value select a byte of the multicast table while bits 2 1 0 determine the bit within the byte selected Examples of the address mapping ADDRESS HASH VALUE 5 0 MULTICAST TABLE BIT ED 00 00 00 00 00 OD 00 00 00 00 00 01 0
41. 0 0 AUTO RELEASE When set transmit pages are released by transmit completion if the transmission was successful when TX SUC is set In that case there is no status word associated with its packet number and successful packet numbers are not even written into the TX COMPLETION FIFO A sequence of transmit packets will only generate an interrupt when the sequence is completely transmitted TX EMPTY INT will be set or when a packet in the sequence experiences a fatal error TX INT will be set Upon a fatal error TXENA is cleared and the transmission sequence stops The packet number that failed is the present in the FIFO PORTS register and its pages are not released allowing the CPU to restart the sequence after corrective action is taken LE ENABLE Link Error Enable When set it enables the LINK OK bit transition as one of the interrupts merged into the EPH INT bit Defaults low disabled Writing this bit also serves as the acknowledge by clearing previous LINK interrupt conditions CR ENABLE Counter Roll over Enable When set it enables the CTR ROL bit as one of the interrupts merged into the EPH INT bit Defaults low disabled TE ENABLE Transmit Error Enable When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit Defaults low disabled Transmit Error is any condition that clears TXENA with TX SUC staying low as described in the EPHSR register EEPROM SELECT This bit allows
42. 0 00 00 00 00 2F 00 00 00 00 00 000 000 010 000 100 111 111 111 MT 0 bit 0 MT 2 bit 0 MT 4 bit 7 7 bit 7 MULTCAST Receive frame was multicast If hash value corresponds to a multicast table bit that is set and the address was a multicast the 31 packet will pass address filtering regardless of other filtering criteria INTERRUPT STRUCTURE The SMC91C95 merges two main interrupt sources into a single interrupt line One source is the Ethernet interrupt and the other is the modem interrupt The Ethernet interrupt is conceptually equivalent to the 91 92 interrupt line it is the OR function of all enabled interrupts within the Ethernet core The modem interrupt is an input pin MINT The enabling reporting and clearing of these two sources is controlled by the ECOR ECSR MCOR and MCSR registers The interrupt structure is similar for ISA and PCMCIA modes with the following exceptions a PCMCIA uses a single interrupt pin nIREQ while ISA can use any of four INTRO INTR3 pins b PCMCIA defaults to Ethernet interrupts disabled Enable IREQ 0 in while ISA defaults to Ethernet interrupts enabled The following table summarizes the interrupt merging Table 4 SMC91C95 Interrupt Merging Interrupt Output nIREQ when either function is INTRO INTR3 enabled When both functions are disabled the nIREQ is used to report the latched value of MRDY Ethernet Interrupt Source OR fun
43. 0BASE T or AUI INTERFACE INTERRUPT LINE SELECTION All the above mentioned values are read from the EEPROM upon hardware reset Except for the INDIVIDUAL ADDRESS the value of the IOS switches determines the offset within the EEPROM for these parameters in such a way that many identical boards can be plugged into the same system by just changing the IOS jumpers In order to support a software utility based installation even if the EEPROM was never programmed the EEPROM be written using the SMC91C95 One of the IOS combination is associated with a fixed default value for the key parameters I O BASE ROM BASE INTERRUPT that can always be used regardless of the EEPROM based value being programmed This value will be used if all IOS pins are left open or pulled high The EEPROM is arranged as a 64 x 16 array The specific target device is the 9346 1024 bit Serial EEPROM All EEPROM accesses are done in words All EEPROM addresses shown are specified as word addresses 100 EEPROM WORD REGISTER ADDRESS Configuration IOS Value 4 Register Base Register IOS Value 4 1 INDIVIDUAL ADDRESS 20 22 hex If IOS2 IOSO 7 only the INDIVIDUAL ADDRESS is read from the Currently assigned values are assumed for the other registers These values are default if the EEPROM read operation follows hardware reset The EEPROM SELECT bit is used to determine the type of EEPROM operation a normal or b general
44. 1 2 3 Bit 0 IntrACK This bit controls the clearing of the Intr bit When this bit is cleared Intr reflects the function s interrupt status When this bit is set the Intr bit must be cleared by the host writing a O into it If the function requires additional service indicated by leaving MINT active the Intr bit will remain asserted when the host writes the 0 8024h Pin Replacement Register PRR Cready Bsy This bit is set to a one when the bit Rready Bsy bit changes state from zero 0 to one 1 or one 1 to zero 0 with the source of the change of state is a change in the modem ready MRDY signal The Cready Bsy bit can be written by the CPU also The CPU attempt to write to this bit is masked by the value for Rready Bsy bit A CPU write to this bit is successful only if the Rready Bsy bit is being written as one 1 Note that the h w represented value of the Rready Bsy bit itself is not affected by the write attempt as shown in the following illustration CURRENT VALUE VALUE WRITTEN NEW VALUE Cready Bsy Rready Bsy Cready Bsy Rready Bsy Cready Bsy Rready Bsy In the unlikely event that the MRDY changes state at the same time that the nWE signal changes from low to high ie writing the register the value written by the host will have priority over the new state of the MRDY input pin When read this bit represents Rready Bsy the current state of the modem Ready Busy MRDY signa
45. 1VOIOO1 ualsioau LINSAY SSduaav VWSO 1 XY Odld Xd YAEWNN 15X V 0313 XH ualsioad YAEWNN 15X V gt NOIVOOTIV 9151999 uadooad GNYWWOO NWN Ssauaav ndo L330vd INOQ XL p Odl4 M0I131 V I0 1 1 FIGURE 16 MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS 95 BLOCK The CSMA CD block is first interfaced via its control registers order to define its operational configuration From then on the DMA interface between the CSMA CD block and memory is used to transfer data to and from its data path interface For transmit the CSMA CD block will be asked to transmit frames as soon as they are in memory It will continue transmissions until any of the following transmit error occurs a 16 collisions on same frame half duplex mode b Late collision half duplex mode C Lost Carrier sense and MON CSN set d Transmit Under run SQET error and STP SQET set In that case TXENA will be cleared and the CPU should restart the transmission by setting it again If a transmission is successful TXENA stays set and the CSMA CD is provided by the block with the next packet to be transmitted For receive the CPU sets RXEN as a way of starting the CSMA CD block receive pro
46. 91C95 91 92 etc I O space To limit the I O space requirements to 16 locations the registers are split into six banks The last word of the I O area is shared by all banks and can be used to change the bank in use Banks 0 through 3 functionally correspond to the SMC91C95 banks while Banks 4 and 5 allow access to the multifunction registers in ISA mode FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on chip RAM on one side and the arbiter on the other for address and data flow purposes For allocation and de allocation it interfaces the arbiter only The MMU deals with a single ported memory and is not aware of the fact that there are two entities requesting allocation and actually accessing memory The mapping function done by the MMU is only a function of the packet number accessed and of the offset within that packet being accessed is not a function of who is requesting the access or the direction of the access To accomplish that memory accesses as well as MMU allocation and de allocation requests are arbitrated by the arbiter block before reaching the MMU Memory allocation could take some time but the ALLOC INT bit in Interrupt Status Register is negated immediately upon allocation request allowing the system to poll that register at any time Memory de allocation command completion indication is provided via the BUSY bit readable through the MMU command register
47. ATA AREA and the CONTROL BYTE The receive byte count always appears as even the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory DATA AREA The data area starts at offset 4 of the packet structure and can extend up to 1536 bytes The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS followed by a variable length number of bytes On transmit all bytes are provided by the CPU including the source address The SMC91C95 does not insert its own source address On receive all bytes are provided by the CSMA side The 802 3 Frame Length word Frame Type in Ethernet is not interpreted by the SMC91C95 It is treated transparently as data both for transmit and receive operations CONTROL BYTE The CONTROL BYTE always resides on the high byte of the last word For transmit packets the CONTROL BYTE is written by the CPU as x x oo o ODD If set indicates odd number of bytes with the last byte being right before the CONTROL BYTE If clear the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted CRC When set CRC will be appended to the frame This bit has only meaning if the NOCRC bit in the TCR is set For receive packets the CONTROL BYTE is
48. BIT 5 Not defined BIT 4 Not defined BIT 3 Not defined BIT 2 Enable IREQ Routing This bit enables 1 or disables 0 the Modem function from asserting nIREQ 85 Enable Base and Limit Enable Function BIT 1 Enable Base and Limit This bit enables the on board modem I O base decoder If set the on board decoder is used to select the function If cleared the decoder is disabled and it is assumed that the host provides for the decoding When the decode is disabled the function is enabled and is configured for 16 bits and not in power down mode the signal 101516 is always asserted For multifunction PCMCIA functionality this bit must be set BIT 0 Enable Function This bit enables 1 or disables 0 the Modem function While the Modem is disabled the SMC91C95 inhibits nMCS IREQ is not generated for the Modem function and nINPACK is not returned for accesses to the Modem registers 8022h Modem Configuration and Status Register MCSR Address 8022h Bit 7 Changed This bit is the logical OR of the CREADY Bsy and RINGEVENT bit logically anded with RINGENABLE states Bit 6 SigChg If this bit is a one the function is enabled configured the Changed bit controls the nSTSCHG f this bit is low the function is disabled the nSTSCHG pin is set to a high Bit 5 10158 This bit when set indicates that the Host can only do 8 bit cycles 07 00 In the
49. CIS to be stored in the parallel EEPROM and on power up to be read directly by the host The remaining parallel EEPROM be used for XIP applications if needed The SMC91C95 integrates most of the 802 3 functionality incorporating the MAC layer protocol the physical layer encoding and decoding functions with the ability to handle the AUI interface twisted pair networks the 91 95 integrates the twisted pair transceiver as well as the link integrity test functions The SMC91C95 is a true 10BASE T single chip able to interface a system or a local bus Directly driven LEDs for installation and run time diagnostics are provided as well as 802 3 statistics gathering to facilitate network management The 91 95 offers High integration Single chip adapter including Packet RAM ISA bus interface PCMCIA interface EEPROM interface Encoder decoder with AUI interface Full duplex magic packet 10BASE T transceiver Lucent Technologies and Rockwell International modem interface High performance Chained back to back packet handling with no CPU intervention Queues transmit packets Queues receive packets Full duplex operation for higher network throughput Stores results in memory along with packet Queues Ethernet and modem interrupts Optional single interrupt upon completion of transmit chain Fast block move operation for load unload CPU sees packet bytes as if stored contiguously Han
50. DATA ALID DAT OUT OUT Parameter 13 Address nSBHE AEN Setup to Control Active t4 Address nSBHE AEN Hold after Control Inactive t5 nlORD Low to Valid Data t6 nIORD High to Data Floating t15 A4 A15 AEN Low BALE High to nlOCS16 Low t20 Cycle time BALE Tied High IOCHRDY not used 120 has to be met Note The cycle time is defined only for consecutive accesses to the Data Register These values assume that IOCHRDY is not used FIGURE 27 ISA CONSECUTIVE READ CYCLES 119 A0 15 AEN nSBHE VALID ADDRESS RUE VALID ADDRESS 15 m t4 516 3 18 VALID DATA IN VALID DATA Parameter Address nSBHE AEN Setup to Control Active Address nSBHE AEN Hold after Control Inactive Data Setup to nlOWR Rising Data Hold after nlOWR Rising 4 15 AEN Low BALE High to nlOCS16 Low Cycle time BALE Tied High IOCHRDY not used t20 has to be met Note The cycle time is defined only for consecutive accesses to the Data Register These values assume that IOCHRDY is not used FIGURE 28 ISA CONSECUTIVE WRITE CYCLES 120 VALID ADDRESS VALID ADDRESS nlOCS16 o IOCHRDY VALID DATA VALID DATA 2 typ max Control Active to IOCHRDY Low 15 IOCHRDY Low Pulse Width 150 Cycle time
51. IA mode is used for the CIS Card Information Structure If no serial EEPROM is used the parallel EEPROM must be used Internal CIS RAM address space is replaced by part of the external parallel EEPROM in this case In ISA mode the serial EEPROM is used for configuration and IEEE Node address making it software compatible to the SMC9000 family of Ethernet LAN Controllers In ISA mode the EEPROM is optional requiring a minimum size of 64 X 16 bit word addresses In PCMCIA mode the minimum serial EEPROM if used size can be 64 X 16 up to 256 X 16 This combination of internal and external attribute memory allows the designer to reduce costs by using a serial EEPROM device when using up to 512 bytes of Card Information and if additional memory is needed an external EEPROM may be used When the SMC91C95 goes into powerdown Write access to space or 35 configuration Registers access Link Logic Ethernet Function Modem function Attribute Memory and PCMCIA Configuration Registers access mode the internal CIS data buffer RAM is re initialized The SMC91C95 generates the appropriate control lines 5 nFWE to read and write the Attribute memory and it tri states the data bus during external Attribute Memory accesses Note that the parallel EEPROM is selected for the first 512 byte CIS information also in the absence of the serial EEPROM in PCMCIA mode Only even locations are used PCMCIA
52. ISA Input address line 17 nFlash PCMCIA Output Flash Memory Chip Select Memory used to access attribute memory Goes active Chip Select low when nREG 0 nCE1 0 and A15 0 Address 18 Input address line 18 Address 19 A19 with pullup ISA Input address line 19 Card Enable nCE1 PCMCIA Card Enable 1 input Used to 1 select card on even byte accesses Address I with pullup ISA Address enable input Used as an Enable address qualifier Address decoding is only enabled when AEN is low nREG PCMCIA Attribute memory and IO select input Asserted when the card attribute space or IO space is being accessed DESCRIPTION OF PIN FUNCTIONS NAME SYMBOL TYPE DESCRIPTION nByte High nSBHE I with pullup ISA Byte High Enable input Asserted low Enable by the system to indicate a data transfer on the upper data byte nCard nCE2 PCMCIA Card Enable 2 input Used to Enable 2 select card on odd byte accesses 83 Ready IOCHRDY OD24 with ISA Output Optionally used by the pullup SMC91C95 to extend host cycles nWait nWAIT PCMCIA Output Optionally used by the SMC91C95 to extend host cycles Data Bus 00 015 1 024 Bidirectional 16 bit data bus used to access the SMC91C95 internal registers The data bus has weak internal pullups Supports direct connection to the system bus without external buffering Reset RESET IS with Input Active high Reset This input is not pullup consider
53. LED output 0162 External ENDEC Transmit Data output ENEEP I with pullup Input This active high input enables the EEPROM to be read or written by the SMC91C95 Internally pulled up Must be connected to ground if no serial EEPROM is used In PCMCIA mode a parallel EEPROM is required if no serial EEPROM is used 2227 16 nEN16 with pullup Input When low the SMC91C95 is configured for 16 bit bus operation If left open the SMC91C95 works in 8 bit bus mode 16 bit configuration can also be programmed via serial EEPROM In ISA Mode only or via software initialization of the CONFIGURATION REGISTER Crystal 1 XTAL1 An external parallel resonance 20 MHz crystal Crystal 2 XTAL2 should be connected across these pins If an external clock source is used it should be connected to XTAL1 and XTAL2 should be left open AUI Receive RECP Diff Input AUI receive differential inputs RECN TXP nCOLL Internal ENDEC nXENDEC pin open In 3 Tanai TXN nCRS this mode and the AUI transmit differential outputs They must be externally pulled up using 150 ohm resistors External ENDEC nXENDEC pin tied low In this mode the pins are inputs used for collision and carrier sense functions DESCRIPTION OF PIN FUNCTIONS SYMBOL TYPE DESCRIPTION 125 AUI Collision COLP Diff Input AUI collision differential inputs A collision is 126 COLN indicated by a 10 MHz signal at this in
54. MU for that packet The first receive packet number in the FIFO can be read via the Fifo Ports Register and the data associated with it can be accessed through the receive area The packet number be removed from the FIFO with or without an automatic release of its associated memory The FIFO is read out upon CPU command remove packet from top of RX FIFO or remove and release command after processing the receive packet in the receive area The width of each FIFO is 5 bits per packet number The depth of each FIFO equals the number of packets the SMC91C95 can handle 18 The guideline is software transparency the software driver should not be aware of different devices or FIFO depths If the MMU memory allocation succeeded there will be room in the transmit FIFO for enqueuing the packet Conversely if there is free memory for receive there should be room the receive FIFO for storing the packet number Note that the CPU can enqueue a transmit command with a packet number that does not follow the sequence in which the MMU assigned packet numbers For example when a transmission failed and it is retried in software or when a receive packet is modified and sent back to the network q9 VNSO gt _ __ gt 35V313 pr 31V9OTIV ino V9I5M 3svaiau 31voOTIV 53900V l1J40OVd
55. N upon detecting a FIFO full condition RXEN will stay active to allow reception of subsequent packets if memory becomes available The CSMA CD block will flush the FIFO upon the new frame arrival PACKET NUMBER FIFOS The transmit packet FIFO stores the packet numbers awaiting transmission in the order they were enqueued The FIFO is advanced written when the CPU issues the enqueue packet number command the packet number to be written is provided by the CPU via the Packet Number Register The number was previously obtained by requesting memory allocation from the MMU The FIFO is read by the DMA block when the CSMA CD block is ready to proceed on to the next transmission By reading the TX EMPTY INT bit the CPU can determine if this FIFO is empty The transmit completion FIFO stores the packet numbers that were already transmitted but not yet acknowledged by the CPU The CPU can read the next packet number in this FIFO from 94 the Fifo Ports Register The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge The CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register The receive packet FIFO stores the packet numbers already received into memory in the order they were received The FIFO is advanced written by the DMA block upon reception of a complete valid packet into memory The number is determined the moment the DMA block first requests memory from the M
56. NGOA MRINGOB MRINGOB SPKRIN SPKRIN SPKROUT SPKROUT nMPDOUT nMPDOUT MFBK1 MFBK1 nMIS16 nMIS16 SERIAL EEPROM NUMBER OF PINS FUNCTION NUMBER OF PINS CRYSTAL OSC XTAL1 XTAL1 2 XTAL2 XTAL2 POWER VDD VDD 12 AVDD AVDD GROUND GND GND 12 AGND AGND 10BASE T INTERFACE TPERXP TPERXP TPERXN TPERXN TPETXP TPETXP TPETXN TPETXN TPETXDP TPETXDP TPETXDN TPETXDN RECN COLP COLN TXP nCOLL TXN nGRS AUI INTERFACE RECP RECN COLP COLN TXP nCOLL TXN nCRS MISC nLNKLED TXD nRXLED RXCLK nBSELED RXD nTXLED nTXEN RBIAS WAKEUP nWAKEUPEN PWRDWN TXCLK nXENDEC nEN16 ROM nPCMCIA nLNKLED TXD nRXLED RXCLK nBSELED RXD nTXLED nTXEN WAKEUP nWAKEUPEN PWRDWN TXCLK nXENDEC nEN16 DESCRIPTION OF PIN FUNCTIONS SYMBOL DESCRIPTION 113 nROM 1 04 with This pin is sampled at the end of RESET nPCMCIA pullup When this pin is sampled low the SMC91C95 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode For ISA operation this pin is left open and is used as a ROM chip select output that goes active when nMEMR is low and the address bus contains a valid ROM address 0 A0 A15 Input address lines 0 through 15 Address 16 ISA Input address line 16 PCMCIA Output Flash Memory Write Enable used for programming the attribute memory Goes active low when nWE 0 and WRATTRIB 1 in ECOR bit 3 Address 17
57. SMC SMC91C95 PRELIMINARY STANDARD MICROSYSTEMS CORPORATION ISA PCMCIA Full Duplex Single Chip Ethernet and Modem Controller with RAM FEATURES e Single Chip Ethernet Controller e Optional External Flash Capability for XIP With Modem Support Execute in Place e Kbytes Built In RAM e Automatic Technology to Detect TX RX e Supports IEEE 802 3 ANSI 8802 3 Ethernet 10BASE T Tranceiver Pair Miswiring Standards e Low Power CMOS Design e Full Duplex Support Supports Magic Packet Wakeup e Hardware Memory Management Unit e 128 Pin VTQFP Package e Built In AUI and 10BASE T Network Interfaces Bus Interface Simultasking Early Transmit and Early Receive Functions e Direct Interface to ISA and PCMCIA with e Advanced Power Management No Wait States Features Including Magic Packet Frame Interface Control Software Compatible with SMC91C92 5 SMC91C94 in ISA Mode Pipelined Data Path e Configuration Registers Implement Cardbus e Handles Block Word Transfers for Any Multi Function Specification V3 0 with Alignment Backward Compatibility to V2 1 e High Performance Chained Back to e Interfaces Directly to Lucent Technologies and Back Transmit and Receive Rockwell International Modem Chipsets e Flat Memory Structure for Low CPU On Chip Attribute Memory CIS of up to 512 Overhead Bytes On Even Addresses For Card e Dynamic Memory Allocation Between Transmit and Receive Confi
58. Set Y Read TXEMPTY amp TX INTR Y TXEMPTY 0 TXEMPTY X EXEMPT amp amp amp TXINT 0 TXINT 1 0 Waiting for Completion Transmission Failed Everything went through successfully Y Read Pkt Register amp Save y Write Address Pointer Register Y Read Status Word from RAM Y Update Statistics Y Issue Release Command Update Variables Y Acknowledge TXINTR Y Re Enable TXENA Y Restore Packet Number y Return to ISR FIGURE 14 TXEMPTY INTR 77 DRIVER SEND ALLOCATE Choose Bank Select E Register Issue Allocate Memory egister Command to MMU Y Y Call ALLOCATE Read Interrupt Status Register Y Exit Driver Send Yes Allocation Passed Read Allocation Result Register Y Write Allocated Packet into Store Data Buffer Pointer Packet Register Y Y Write Address Pointer Register Clear Ready for Packet Flag Y Copy Part At T Data Packet Enable Allocation Interrupt Write Source Address into Proper Location Y Copy Remaining TX Data Packet into RAM Y Enqueue Packet Set Ready for Packet Flag Y Return Buffers to Upper Layer FIGURE 15 DRIVER SEND
59. Set when at least one packet transmission was completed The first packet number to be serviced can be read from the FIFO PORTS register The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS register After servicing a packet number its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit set RCV INT Set when a receive interrupt is generated The first packet number to be serviced can be read from the FIFO PORTS register The RCV INT bit is always the logic complement of the bit in the FIFO PORTS register INT Early receive interrupt Set whenever a receive packet is being received and the number of bytes received into memory exceeds the value programmed as ERCV THRESHOLD Bank 3 Offset Ch ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set NOTE If the driver uses AUTO RELEASE mode it should enable TX EMPTY INT as well as TX INT TX EMPTY INT will be set when the complete sequence of packets is transmitted TX INT will be set if the sequence stops due to a fatal error on any of the packets in the sequence NOTE For edge triggered systems the Interrupt Service Routine should clear the Interrupt Mask Register and only enable the appropriate interrupts after the interrupt source is serviced acknowledged SLdNYYALNI NIV anan LNI
60. T NUMBER REGISTER 0 0 0 0 PACKET NUMBER AT TX AREA The value written into this register determines which packet number is accessible through the TX area Some MMU commands use the number stored in this OFFSET NAME 3 ALLOCATION RESULT REGISTER TYPE SYMBOL READ WRITE PNR 0 0 0 0 register as the packet number parameter This register is cleared by a RESET or a RESET MMU Command TYPE SYMBOL READ ONLY ARR This register is updated upon an ALLOCATE MEMORY MMU command FAILED ALLOCATED PACKET NUMBER 1 0 0 0 FAILED A zero indicates a successful allocation completion If the allocation fails the bit is set and only cleared when the pending allocation is satisfied Defaults high upon reset and reset MMU command For polling purposes the ALLOC INT in the Interrupt Status Register should be used because it is synchronized to the read operation Sequence 1 Allocate Command 2 Poll ALLOC INT bit until set 3 Read Allocation Result Register 0 0 0 0 ALLOCATED PACKET NUMBER Packet number associated with the last memory allocation request The value is only valid if the FAILED bit is clear NOTE For software compatibility with future versions the value read from the ARR after an allocation request is intended to be written into the PNR is without masking higher bits provided FAILED 0 SPACE BANK2 OFFSET NAME 4 FIFO PORTS REGISTER TYPE READ ONLY SYMBOL FIFO This
61. TXDN to TPETXDP Skew TXP to TXN Skew FIGURE 42 DIFFERENTIAL OUTPUT SIGNAL TIMING 10BASE T AND AUI 131 first bit decoded nCRS internal TPERXP N first bit decoded nCRS internal Parameter Noise Pulse Width Reject AUI Carrier Sense Turn On Delay AUI Noise Sense Pulse Width Reject 10BASE T Carrier Sense Turn On Delay 10BASE T FIGURE 43 RECEIVE TIMING START OF FRAME AUI AND 10BASE T 132 last bit TPERXP TPERXN 78 jd nCRS internal Parameter Receiver Turn Off Delay FIGURE 44 RECEIVE TIMING END OF FRAME AUI AND 10BASE T 133 TPETXN last bit 1 0 Parameter Transmit Output High to Idle in Half Step Mode Transmit Output High before Idle in Half Step Mode FIGURE 45 TRANSMIT TIMING END OF FRAME AUI AND 10BASE T 134 COL internal Parameter Collision Turn On Delay Collision Turn Off Delay FIGURE 46 COLLISION TIMING AUI 135 T Y j E E Hd D E Uo L 1 Y
62. Uses Certified SMC9000 Drivers Which Receive Polarity Detection and Operate with Every Major Network Correction Operating System e Integrates AUI Interface e Software Driver Compatible with e Implements 10 Mbps Manchester SMC91C92 SMC91C94 and SMC91C100 Encoding Decoding and Clock Recovery 100 Mbps Controllers in ISA Mode Automatic Retransmission Bad Packet e Software Driver Utilizes Full Capability of Rejection and Transmit Padding 32 Bit Microprocessor e External and Internal Loopback Modes PIN CONFIGURATION L EEDO SDOUT TXP nCOLL IL I TXN nCRS TPETXP TEPTXDP INTR2 nSTSCHG TPETXN INTR1 nINPACK TPETXDN INTRO nIREQ AVSS VDD nTXLED nTXEN nlORD nRXLED RXCLK nlOWR nLINKLED TXD nMEMR nOE nBSELED RXD 85 nlOSC16 nlOIS16 VDD VSS SPKRIN IOCHRDY nWAIT SPKROUT BALE nWE nMIS16 nSBHE nCE2 MRDY VDD 5 amp 8 128 Pin VIQFP 8 nMRINGOA 76 D12 MRINGOB VSS nMCS D11 nMRESET D10 VDD D9 MIDLEN1 VDD nMPWDN D8 nMPDOUT D7 MFBK1 D6 VSS VSS NC D5 ND D4 GENERAL DESCRIPTION The SMC91C95 is a VLSI Ethernet Controller that combines ISA and PCMCIA interfaces as well as an interface to a companion modem chip set in one chip The SMC91C95 integrates all the MAC physical layer functions as well as the packet RAM needed to implement a high performance 10BASE T twisted pair node For 10BASES thick coax 10BASE2 thin coax and 10BASE F fiber implementations the SMC91C95 interfaces to exte
63. Y 64 locations only 8 bits Configuration even bytes are Registers usable Modem I O nlORD nlOWR Y Y N 8 locations Space Ethernet nlORD nlOWR 16 locations 8 or 16 bits Space 1 1 This space also allows access to the PCMCIA Configuration Register through Banks 4 and 5 2 Except for the bus interface the functional In the system memory space up to 64 kbytes are behavior of the SMC91C95 after initial decoded by the SMC91C95 as expansion ROM configuration is identical for ISA and PCMCIA The ROM expansion area is 8 bits wide modes Device configuration is done using a serial The SMC91C95 includes an arbitrated shared EEPROM with support for modifications to the memory of 6 kbytes accessed by the CPU The EEPROM at installation time Flash ROM is MMU unit allocates RAM memory to be used for supported for PCMCIA attribute memory transmit and receive packets using 256 byte pages The CSMA CD core implements the 802 3 MAC layer protocol It has two independent interfaces The arbitration is transparent to the CPU in every the data path and the control path Both interfaces sense There is no speed penalty for ISA type of are 16 bits wide machines due to arbitration There are restrictions on what locations can be accessed at The control path provides a set of registers used to any time RAM accesses as well as MMU configure and control the block These registers requests are arbitrated are accessible by the CPU thro
64. able Function bit in MCOR is low Pwrdwn bit in ECSR is high or Enable Function bit in ECOR is low or PWRDN bit in Control Register is high POWERDOWN EXITED When pin goes low Otherwise or when function is reset in ISA mode Otherwise or Ringing from modem chipset Magic Packet received WAKUP in EPH status 34 POWERS DOWN Ethernet Function including Link circuitry Modem Function Ethernet Function plus any analog logic including link logic Ethernet MAC logic Link is enabled DOES NOT POWER DOWN Modem function Attribute Memory and PCMCIA Configuration Registers access Ethernet function Attribute Memory and PCMCIA Configuration Registers access Modem Function Attribute memory and PCMCIA configuration Registers access Link Logic B2 Power State nWAKEUP Pin Table 6 Powerdown Functions POWERDOWN ENTERED When pin is low and reset is inactive POWERDOWN EXITED When pin goes high POWERS DOWN Ethernet Function Link logic enabled DOES NOT POWER DOWN Modem Function Attribute memory and PCMCIA B2 Power State PWRDN bit in Control Register When bit is set reset PCMCIA Attribute Memory Address 0 7FFEh The Attribute Memory is implemented using a combination of interrnal SRAM external parallel EEPROM ROM or Flash ROM The internal SRAM is initialized during power up using the serial EEPROM This serial EEPROM in PCMC
65. ad cycles for an enabled function O24 ISA Output Active high interrupt signal The interrupt line selection is determined by the value of INT SEL1 0 bits in the Configuration Register This interrupt is tri stated when not selected PCMCIA Status changed bit Depending on the setting of the RingEn bit Modem CCSR this pin either reflects the ringing status mode or the state of the Modem Changed bit The ringing status is obtained by stretching the MRINGIN to convert a 20Hz toggle rate to a constant level ISA Output Active high interrupt signal The interrupt line selection is determined by the value of INT SEL1 0 bits in the Configuration Register This interrupt is tri stated when not selected nl O 16 nlOCS16 ISA Active low output asserted in 16 bit mode when AEN is low and A4 A15 decode to the SMC91C95 address programmed into the high byte of the Base Address Register PIN NO 92 Interrupt 2 INTR2 nStatus nSTSCHG Changed IARE 7777 4 NAME SYMBOL DESCRIPTION nlOIS16 PCMCIA Active low output asserted whenever the SMC91C95 is in 16 bit mode and Enable Function bit in the ECOR register is high nREG is low and A4 A15 decode to the LAN address specified in Base Registers 0 and 1 in PCMCIA attribute Space nl O Read IS with Input Active low read strobe used to access pullup the SMC91C95 IO space nl O Write IS
66. at any address in the 8 through Ah range while the number of bytes being transferred are determined by AO and nSBHE in ISA mode and by AO nCE1 and nCE2 in PCMCIA mode SPACE 2 OFFSET NAME TYPE SYMBOL INTERRUPT STATUS REGISTER READ ONLY IST ERCV EPHINT RX OVR ALLOC TX TX INT RCV INT INT N INT INT EMPTY INT X 0 0 0 0 1 0 0 OFFSET NAME TYPE SYMBOL INTERRUPT ACKNOWLEDGE WRITE ONLY ACK REGISTER OFFSET NAME TYPE SYMBOL D INTERRUPT MASK REGISTER READ WRITE MSK ERCV EPHINT ALLOC TX TXINT RCVINT INT N INT INT EMPTY INT X 0 0 0 0 0 0 0 This register can be read and written as a word or and enabling of these sources can be done via the as two individual bytes Control Register The possible sources are The Interrupt Mask Register bits enable the LINK OK transition appropriate bits when high and disable them when CTR ROL Statistics counter roll over low An enabled bit being set wil cause a TXENA cleared A fatal transmit error occurred hardware interrupt forcing TXENA to be cleared TX SUC will be low and the specific reason will be reflected by the bits EPH INT Set when the Ethernet Protocol Handler section indicates one out of various possible TXUNRN Transmit underrun special conditions This bit merges exception type SQET SQE Error of interrupt sources whose service time is not LOST CARR Lost Carrier critical to the execution speed of the low level LATCOL Late Coll
67. bute Memory Address Using Serial EEPROM ATTRIBUTE EXTERNAL EPROM INTERNAL SRAM CONFIGURATION MEMORYADDRESS STORE STORE 512 BYTES REGISTERS Table 8 Attribute Memory Address without Serial EEPROM ATTRIBUTE EXTERNAL EPROM INTERNAL SRAM CONFIGURATION MEMORYADDRESS STORE STORE DT BYTES 36 SPACE ISA PCMCIA Mode In ISA mode the base space is determined by the 1050 1052 inputs and the EEPROM contents A4 A15 are compared against the base I O address for I O space accesses In PCMCIA mode nREG along with nlORD or nlOWR defines an I O access regardless of the A4 A15 value OFFSET NAME HIGH BYTE LOW BYTE OFFSET Defines the address offset within the IOBASE where the register can be accessed at provided the bank select has the appropriate value The offset specifies the address of the even byte bits 0 7 or the address of the complete word The odd byte can be accessed using address offset 1 37 To limit the O space requirements to 16 locations the registers are assigned to different banks The last word of the I O area is shared by all banks and can be used to change the bank in use Registers are described using convention the following TYPE SYMBOL oe oe oe Ter Te Ter D e X X X X X X X X Der we X X X X X X X X Some registers like the Interrupt Ack or like Interrupt Mask are functionally described as
68. case of the 10158 bit being cleared 0 during Reset and Power up for example the PIN MIS16 will override the 10158 default setting the bit 1 Bit 4 ResurvedBit 3 Audio This bit controls the audio pass through of the digital audio When cleared the SPKROUT is three stated When set the SPKRIN pin is passed to the SPKROUT pin Bit 2 PwrDwn When set 1 this bit puts the modem into powerdown mode The modem is also put into powerdown mode when the Enable Function bit is cleared When in powerdown the MRINGIN signal is blocked from going to the ringing output signal When taken out of powerdown when PwrDwn is cleared 1 and Enable Function in the MCOR bit 0 is set 1 the modem is awakened by a 86 0 0 0 0 pulse on the output ringing signals as appropriate The pulse duration is determined by the input signal MRINGIN MRINGIN is then passed to the outputs Bit 1 Intr This bit is read set to a one when this function is requesting interrupt service It is cleared depending upon the setting of IntrACK When this bit and Enable IREQ Routing are set IREQOut is asserted The Intr bit can be reset the following ways and priority ranging from 1 highest to 3 lowest A hardware reset power up The function ie interrupt source can only reset this field to zero 0 if the IntrACK field is reset to zero 0 The host system can only reset this field to a zero 0 only if the IntrACK bit is set to a one
69. ce to allow non PCMCIA dual function designs The Ethernet controller function includes a built in 6kbyte RAM for packet storage This RAM buffer is accessed by the CPU through two sequential access regions of 3 kbytes each The RAM access is internally arbitrated by the SMC91C95 and dynamically allocated between transmit and receive packets using 256 byte pages The Ethernet controller functionality is identical to the SMC91C94 except where indicated otherwise Table 1 Bus Transactions in ISA Mode 8 BIT MODE nEN16 1 16 BIT 0 16 BIT MODE otherwise 21 00 07 08 015 odd byte invalid cycle Table 2 Bus Transactions in PCMCIA Mode 8 BIT MODE even byte IOis8 1 NEN16 1 16BIT 0 4 EXE eee alo lol kem 16BIT CONFIGURATION REGISTER bit 7 lOis8 ECSR register bit 5 nEN16 pin nEN16 For the modem function the transactions are similarxcept that the modem is assumed to be 8 bit wide unless ICI58 0 and nMIS16 0 NOTE The lOis8 value should be identical in MCSR and ECSR if both functions are enabled 8 Bit mode IOis8 1 nMIS16 1 22 Table 3 SMC91C95 Address Spaces SIGNALS PCMCI ON CHIP DEPTH WIDTH USED A PCMCIA nOE nWE N Y N Up to 32k 8 bits on even Attribute external locations only addresses Memory ROM even bytes are usable PCMCIA nOE nWE N Y
70. ceive packets without exiting or one at a time if the ISR just returns after processing and removing one There are two types of transmit interrupt strategies 1 Oneinterrupt per packet 2 Oneinterrupt per sequence of packets The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used TX INT bit Set whenever the TX completion FIFO is not empty TX EMPTY INT bit Set whenever the TX FIFO is empty AUTO RELEASE When set successful transmit packets are written into completion FIFO and their memory is released automatically 1 One interrupt per packet enable TX INT set AUTO RELEASE O The software driver can find the completion result in memory and process the interrupt one packet at a time Depending on the completion code the driver will take different actions Note that the transmit process is working in parallel and other transmissions might be taking place The SMC91C95 is virtually queuing the packet numbers and their status words In this case the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register This eliminates the need for the driver to keep a list of packet numbers being transmitted The numbers are queued by the SMC91C95 and provided back to the their transmission completes 2 One interrupt per sequence of packets Enable TX EMPTY INT and TX INT s
71. cess The CSMA CD block will send data after address filtering through the data path to the DMA block Data is transferred into memory as it is received and the final check on data acceptance is the CRC checking done by the CSMA CD block In any case the DMA takes care of requesting releasing memory for receive packets as well as generating the byte count The receive status word is provided by the CSMA CD block and written in the first location of the receive structure by the DMA block II configured for storing CRC in memory the CSMA CD unit will transfer the CRC bytes through the DMA interface and then will be treated like regular data bytes 96 Note that the receive status word of any packet is available only through memory and is not readable through any other register In order to let the CPU know about receive overruns the RX_OVRN bit is latched into the Interrupt Status Register which is readable by the CPU at any time The address filtering is done inside the CSMA CD block A packet will be received if the destination address is broadcast or if it is addressed to the individual address of the SMC91C95 or if it is a multicast address and ALMUL bit is set or if it is a multicast address matching one of the multicast table entries II the PRMS bit is set all packets are received The CSMA CD block is a full duplex machine and when working in full duplex mode the CSMA CD block will be simultaneously using its data
72. cification Refer to the PCMCIA v3 0 card specification on the Metaformat HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE TYPE READ WRITE SYMBOL IAR The SMC91C95 in PCMCIA mode knows nothing about the location or structure of the IEEE Ethernet Address stored in the EEPROM Once this data is stored in the CIS SRAM data buffer in the 91 95 it is parsed by the host to extract the IEEE Address information and stored manualy by the LAN Driver Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable ADDRESS 0 ADDRESS 1 ADDRESS 2 ADDRESS 3 ADDRESS 4 ADDRESS 5 e iS SPACE BANK1 OFFSET A NAME HIGH BYTE LOW BYTE This register can be used as a way of storing and retrieving non volatile information in the EEPROM to be used by the software driver The storage is word oriented and the EEPROM word address to be read or written is specified using the six lowest bits of the Pointer Register In PCMCIA mode Bits 0 to 10 of the pointer register are used This register can also be used to sequentially program the Individual Address area of the GENERAL PURPOSE REGISTER TYPE READ WRITE SYMBOL GPR HIGH DATA BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
73. ction of all interrupt bits specified in the Interrupt Status Register ANDed with their 2 Enable bits Modem Modem Interrupt Source Source MINT MINT input pin 00A pin Ethernet Interrupt Enable Modem Modem Interrupt Enable Enable Enable IREQ bit This bit Enable IREQ bit in ECOR This defaults low in PCMCIA mode bit defaults ISA mode Enable Enable IREQ bit in MCOR This bit defaults low 00000000 bit in MCOR This bit defaults low Ethernet Interrupt Status Intr bit in ECSR Bit Modem Interrupt Status Intr bit in MCSR Bit 32 RESET LOGIC POR Internal circuit activated by Power On The pins and bits involved in the different reset nMRESET Output pin to reset modem mechanisms are SRESET Soft Reset bit in ECOR and MCOR RESET Input Pin one SRESET bit for each function SOFT RST EPH Soft Reset bit Table 5 Reset Functions SAMPLES TRIGGERS RESETS THE ISA VS EEPROM FOLLOWING ACTIVATES PCMCIA READ FUNCTIONS MODE RESET Pin All internal logic nMRESET Yes POR Circuit Generates an internal reset of at least 15 msec with same effect as the RESET pin ECOR The Ethernet controller Register function and Ethernet SRESET Bit PCMCIA Configuration Registers except for the bit itself SOFT RST The Ethernet Controller itself except for the and BASE registers It does not reset any PCMCIA Configuration Register
74. dles 16 bit transfers regardless of address alignment Access to packet through fixed window Fast bus interface Compatible with ISA type and faster buses Flexibility Flexible packet and header processing Can be set to Simultasking Early Receive and transmit modes Can access any byte in the packet Can immediately remove undesired packets from queue Can move packets from receive to transmit queue Can alter receive processing order without copying data Can discard or enqueue again a failed transmission Resource allocation Memory dynamically allocated for transmit and receive Can automatically release memory on successful transmission Configuration ISA Uses non volatile jumperless setup via serial EEPROM PCMCIA Uses serial EEPROM for attribute memory storage PCMCIA I O ignores address lines A4 A15 and relies on the PCMCIA host decoding for the slot nROM nPCMCIA on the SMC91C95 is left open with a pullup for ISA mode This pin is sampled at the end of Power On Reset If found low the SMC91C95 is configured for PCMCIA mode PIN REQUIREMENTS FUNCTION Rae SYSTEM ADDRESS BUS AEN SYSTEM DATA BUS 00 015 SYSTEM CONTROL BUS RESET BALE nWE nlORD nlORD nlOWR nlOWR nMEMR nOE IOCHRDY nWAIT nlOCS16 nlOIS16 nSBHE nCE2 INTRO nIREQ INTR1 nINPACK INTR2 nSTSCHG INTR3 MODEM INTERFACE nMRESET nMRESET MINT MINT nMCS nMCS MRDY MRDY nMPWDN nMPWDN MIDLEN1 MIDLEN1 MRINGIN MRINGIN nMRINGOA nMRI
75. e used when the transmitter is disabled Unlike the RESET MMU command the RESET TX FIFOs does not release any memory NOTE 1 Only command 1 uses N2 N1 NO NOTE 2 When using the RESET TX FIFOS command the CPU is responsible for releasing the memory associated with outstanding packets or re enqueuing them Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command NOTE 3 MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it COMMAND SEQUENCING A second allocate command command 1 should not be issued until the present one has completed Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt A second release command commands 4 5 should not be issued if the previous one is still being processed The BUSY bit indicates that a release command is in progress After issuing 57 command 5 the contents of the PNR should not be changed until BUSY goes low After issuing command 4 command 3 should not be issued until BUSY goes low BUSY Readable at bit 0 of the MMU command register address When set indicates that MMU is still processing a release command When clear MMU has already completed last release command BUSY and FAILED bits are set upon the trailing edge of command SPACE BANK2 OFFSET NAME 2 PACKE
76. ecoded by the Modem function Each bit in the register represents an I O address line A value of one means that the SMC91C95 will not decode the corresponding address line for the Modem function a value of zero means that the address line will be decoded If a bit in the register is set to one all bits of lesser significance in the register must also be set to one This register defaults to 7h that is A1 and A2 are not decoded resulting in 8 address locations for the modem function Modem Space Address determined by Modem I O Base Registers The Modem I O space is external to the SMC91C95 The SMC91C95 decodes the address bus A15 through A3 via a internal comparator and generates nMCS for I O cycles that decode to the Modem area as defined by the Modem Base Registers The I O address space consists of eight 8 8 bit locations 90 0 1 1 1 SMC91C95 will tri state the data bus during Modem IC space accesses In ISA mode nMCS is disabled 1 No address decodeing for the modem will be done Ethernet I O Space Address determined by Ethernet I O Base Registers The Ethernet IC space consists of sixteen locations whose base address is determined in PCMCIA mode by the Ethernet IC Base Registers and in ISA mode by the default value of the Base Register either reset or serial EEPROM default in ISA mode only The Ethernet I O space can be configured as an 8 or 16 bit space and is similar to the SMC
77. ed active unless it is active for at least 100ns to filter narrow glitches A POR circuit generates an internal reset upon power up for at least 15msec All hardware reset references in this spec relate to the OR function of the POR and the RESET pin Address BALE IS with ISA Input Address strobe For systems that Latch pullup require address latching the falling edge of BALE latches address lines and nSBHE nWrite nW PCMCIA Write Enable input Used for Enable writing into COR and CSR registers as well as attribute memory space Interrupt INTRO 024 ISA Active high interrupt signal The interrupt line selection is determined by the value of INT SEL1 0 bits in the Configuration Register This interrupt is tri stated when not selected 10 DESCRIPTION OF PIN FUNCTIONS NAME SYMBOL TYPE DESCRIPTION ninterrupt nIREQ Request Interrupt 1 INTR1 nINPACK PCMCIA Active low interrupt request output Pin acts as a Ready pin during power up The pin should be pulled low within 10us of the application of the VCC or Reset which ever occurs later It remains low 0 until the CIS is loaded in the Internal SRAM The high 1 state indicates to the host controller that the device is ready ISA Output Active high interrupt signal The interrupt line selection is determined by the value of INT SEL1 0 bits in the Configuration Register This interrupt is tri stated when not selected PCMCIA Output asserted to acknowledge re
78. erted Reverse Polarity Function In the 10BASE T mode the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally Collision Detection Function In the 10BASE T mode while in half duplex a collision state is indicated when there are simultaneous transmissions and receptions on the twisted pair link During a collision state the nCOLL signal is asserted If the received data ends and the transmit control signal is still active the transmit data is sent to the MAC within 9 bit times The nnCOLL signal is de asserted within 9 bit times after the collision terminates In the AUI mode the external 99 transceiver sends a 10MHz signal to the PHY upon detection of a collision Link Integrity The PHY test for a faulty twisted pair link the absence of transmit data link test pulses are tranmsitted every 16 18ms after the end of the last transmission or link pulse on the twisted pair medium II neither valid data nor link test pulses are received within 10 to 150ms the link is declared bad and both data transmission as as the operational loopback function are disabled Link Integrity function can be disabled for pre 10BASE T twisted pair networks BOARD SETUP INFORMATION ISA MODE The following parameters are obtained from the EEPROM as board setup information ETHERNET INDIVIDUAL ADDRESS IC BASE ADDRESS ROM BASE ADDRESS 8 16 BIT ADAPTER 1
79. et AUTO RELEASE 1 TX EMPTY INT is generated only after transmitting the last packet in the FIFO TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore the FIFO will not be emptied This mode has the advantage of a smaller CPU overhead and faster memory de allocation Note that when AUTO RELEASE 1 80 the CPU is not provided with the packet numbers that completed successfully NOTE The pointer register is shared by any process accessing the SMC91C95 memory In order to allow processes to be interruptable the interrupting process is responsible for reading the pointer value before modifying it saving it and restoring it before returning from the interrupt Typically there would be three processes using the pointer 1 Transmit driven 2 Receive unloading interrupt driven 3 Transmit Status reading interrupt driven loading sometimes interrupt 1 and 3 also share the usage of the Packet Number Register Therefore saving and restoring the PNR is also required from interrupt service routines INTERNAL VS EXTERNAL ATTRIBUTE MEMORY MAP The Internal vs External EPROM attribute memory decodes are shown in Table 11 and Table 12 This allows the designer to not require an external EPROM device if the single or multi function PCMCIA card needs less than 512 bytes of configuration information As can be seen in the map if 512 bytes of CIS o
80. f this bit is not set this functionality is disabled When a Magic Packet is received the ethernet controller will generate an interrupt causing the host to initiate a service routine to find the source of the event The Interrupt bit in the ECSR is also set if the host plans on polling the controller for Wakeup status TYPICAL FLOW OF EVENTS FOR TRANSMIT S W DRIVER ISSUE ALLOCATE MEMORY FOR TX N BYTES the MMU attempts to allocate bytes of RAM WAIT FOR SUCCESSFUL COMPLETION CODE Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt The TX packet number is now at the Allocation Result Register LOAD TRANSMIT DATA Copy the TX packet number into the Packet Number Register Write the Pointer Register then use a block move operation from the upper layer transmit queue into the Data Register ISSUE ENQUEUE PACKET NUMBER TO TX FIFO This command writes the number present in the Packet Number Register into the TX FIFO The transmission is now enqueued No further CPU intervention is needed until a transmit interrupt is generated SERVICE INTERRUPT Read Interrupt Status Register If it is a transmit interrupt read the TX Done Packet Number from the FIFO Ports Register Write the packet number into the Packet Number Register The corresponding status word is now readable from memory II status word shows successful transmission issue RELEASE packet number command to free up
81. face is used transmit data will not be sent out to the cable Rused INT SEL1 0 In ISA mode used to select one out Defaults low of four interrupt pins The three unused interrupts are tristated FULL STEP This bit is used to select the signaling mode for the AUI port When set the AUI port uses full step signaling Defaults low to half step signaling This bit is only meaningful when AUI SELECT is high SET SQLCH When set the squelch level used for the 10BASE T receive signal is 240mV When clear the receive squelch level is 400mV Defaults low 48 SEL1 SELO USED 0 0 1 1 0 1 0 1 49 SPACE BANK1 OFFSET NAME 2 BASE ADDRESS REGISTER TYPE READ WRITE SYMBOL BAR For ISA mode only this register holds the I O address decode option chosen for the I O ROM space It is part of the EEPROM saved setup and is not usually modified during run time NOTE This register should ONLY be used in ISA mode In PCMCIA mode this register is read only HIGH BYTE LOW BYTE 0 A15 A13 and A9 A5 These bits are compared in ISA mode against the I O address on the bus to determine the IOBASE for SMC91C95 registers The 64k I O space is fully decoded by the SMC91C95 down to 16 location space therefore the unspecified address lines A4 A10 A11 and A12 must be all zeros ROM SIZE Determines the ROM decode area in ISA mode memory space as
82. follows 00 ROM disable 01 16k RA14 18 define ROM select 10 32k RA15 18 define ROM select 11 2 64k RA16 18 define ROM select RA18 RA14 These bits are compared in ISA mode against the memory address on the bus to determine if the ROM is being accessed as a function of the ROM SIZE ROM accesses are ROM SIZE RA18 RA17 RA16 RA15 RA14 ZEN read only memory accesses defined by nMEMRD going low For a full decode of the address space unspecified upper address lines have to be 19 1 A20 A23 lines are not directly decoded however ISA systems will only activate nMEMRD only when A20 A23 0 All bits in this register are loaded from the serial EEPROM in ISA Mode only In PCMCIA mode the I O base is set to the default value as in ISA mode as defined below The I O base decode defaults to 300h namely the high byte defaults to 18h ROM SIZE defaults to 01 ROM decode defaults to 000 namely the low byte defaults to 67h SPACE BANK1 OFFSET NAME 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload in ISA mode only The registers can be modified by the software driver but a STORE operation will not modify in ISA mode only the EEPROM Individual Address contents In PCMCIA mode the IEEE Individual Address is stored in the EEPROM but is stored in PCMCIA Tuple format as defined in the Metaformat spe
83. g page 112 Paametr Min Units 1 Aadress set p petore own ow 122 nCE1 nCE2setupbeforeniOWRlow 5 ns 23 nREG setupbeforenIOWRlow 5 t4 nOWRlowwih 165 n 125 AddressholdfromnlOWRhigh 20 126 nCE1 2 hodfolowngniOWRhign 20 ms 27 nREGhodfolowngniIOWRhigh o ms _ 08 Address vaidtonoStevaid 1 95 rs 129 DatahodfolowngnOWR 30 80 AddresvaidtonMCSlow 100 e RCE lwo ao t32 nREGlowtonMcSlow 40 133 Address invalidtonMCShigh 100 34 1 o t36 ns ns nCE1 high to nMCS high nREG high to nMCS high nlOIS16 delay from address 113 A0 9 A15 nREG nCE1 nWE 7 Write Data Setup to nWE Rising Write Data Hold after nWE Rising nOE Low to Valid Data Address nREG Setup to nWE Active Address nREG Hold after nOE Inactive Address nREG Setup to nOE Active Address nREG Hold after Control Inactive nCE1 Setup to nWE Rising nCE1 Low to Valid Data FIGURE 22 CARD CONFIGURATION REGISTERS READ WRITE PCMCIA MODE A15z1 114 Ao 9 A15 Ili nREG nCE1 nCE
84. guration Information Expandable nt 9 Buffered Architecture Insensitive to Bus Externally 7 Latencies No Overruns Underruns Option for Serial or Parallel EEPROM for CIS e Supports 2 for Diskless Applications Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation 5 gt _ _ _ ______ ______ _ 1 PIN 2 ___________ _ _ gt __ __ __ 3 GENERAL DESCRIP TO N Eo sopa i adt ctu 4 4 22322222232222_ __ lt __ 7 DESCRIPTION OF PIN 2 9 nn ti etat c peo reip 17 09 9 21 ___ _ _ __ _ _ _ 32 POWERDOWN REO Co 34 PCMCIA
85. he link integrity test function The SMC91C95 provides a 16 bit data path into RAM The RAM is private and can only be accessed by the system via the arbiter memory is managed by the MMU Byte and word accesses to the RAM are supported If the system to SRAM bandwidth is insufficient the SMC91C95 will automatically use its IOCHRDY line for flow control However for ISA buses IOCHRDY will never be negated BUFFER MEMORY The logical addresses for RAM access are divided into TX area and RX area Each one of the areas is 1 536 kbytes long and accommodates maximum size Ethernet packet 24 The TX area is seen by the CPU as a window through which packets can be loaded into memory before queuing them in the TX FIFO of packets The TX area can also be used to examine the transmit completion status after packet transmission The RX area is associated to the output of the RX FIFO of packets and is used to access receive packet data and status information The logical address is specified by loading the address pointer register The pointer can automatically increment on accesses All accesses to the RAM are done via I O space A bit in the address pointer also specifies if the address refers to the TX or RX area In the TX area the host CPU has access to the next transmit packet being prepared for transmission In the RX area it has access to the first receive packet not processed by the CPU yet The FIFO of
86. he support for determining the function generating the interrupt and informing relevant drivers The registers for the two functions are treated as independent sets One of the only requirements is to set the functions I O base registers with different values to avoid any access conflict MEMORY ARCHITECTURE The concept of presenting the shared RAM as FIFO of packets with a memory management unit allocating memory on a per packet basis responds to the following needs Memory allocation for receive vs transmit A fixed partition between receive and transmit area would not be efficient Being able to dynamically allocate it to transmit and receive represents almost the equivalent of duplicating the memory size for some workstation type of drivers Software overhead By presenting a FIFO of packets the software driver does not have to waste any time in calculating pointers for the different buffers that make up different packets The driver usually deals with one packet at a time With this approach packets accessible always at the same fixed address and access is provided to any byte of the packet Headers can be analyzed without reading out the entire packet The packet can be moved in or out with a block move operation Multiple upper layer support The SMC91C95 facilitates interfacing to multiple upper layer protocols because of the receive packet 69 processing flexibility receive lookahead scheme like
87. her bits of the SMC91C95 can be read or written until the EEPROM operation completes and both bits are clear This mechanism is also valid for reset initiated reloads NOTE If no EEPROM is connected to the SMC91C95 for example for some embedded applications the should be grounded and no accesses to the EEPROM will be attempted Configuration Base and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value 101 DIAGNOSTIC LEDs The following LED drive signals are available for diagnostic and installation aid purposes nTXLED Activated by transmit activity nBSELED Board select LED Activated when the board space is accessed namely on accesses to the SMC91C95 register space or the ROM area decoded by the SMC91C95 The signal is stretched to 125 msec nRXLED Activated by receive activity nLINKLED Reflects the link integrity status ARBITRATION CONSIDERATIONS The arbiter exploits the sequential nature of the CPU accesses to provide a very fast access time Memory bandwidth considerations will have an effect on the CPU cycle time but no effect on access time For normal 8 MHz 10 MHz and 12 5 MHz ISA buses as well as EISA normal cycles the SMC91C95 can be accessed without negating ready When write operations occur the data is written into a FIFO The CPU cycle can complete immediately and the buffered data will
88. ime 15 Output Disable Time from nCE1 high high NOTE Applies only when nWAIT is asserted by the SMC91C95 FIGURE 18 PCMCIA MEMORY READ TIMING 108 5 0 nREG D 15 0 Din Lee We 1 mWEPuseWidh 150 t t2 Address nREG Setup Time to nWE Low t3 Address nREG Setup Time to 180 nWE High t4 nCE1 Low to nWE High Setup 180 Time Data to nWE High Setup Time 80 Data Hold Time from nWE High 1 t7 Write Recovery Time Address 3 nREG Hold from nWE High NOTE Minimum write pulse width must be met whether or not nWAIT is asserted by the SMC91C95 FIGURE 19 PCMCIA MEMORY WRITE TIMING 109 A 15 0 nMCS EX I ls a D MX nlOIS16 aE N D 15 0 FIGURE 20 I O READ TIMING Table on the following page 110 Paametr Min Units Address setupbeforenlORDlow 70 n _ 2 _ 4 nlORD low width 5 Address hold from nlORD high 06 U 08 9 ti t2 t3 t4 t5 t6 t7 t8 t9 36 nREG hold following nIORD high 0 18 Address invalid to nMCS high 10 nCE1hightonMCShign 40 120 nREGhightonMcshigh 4 ms 111 15 0 D 15 0 mie N wo 1 LE FIGURE 21 I O WRITE TIMING Table the followin
89. in may change from cycle to cycle EEPROM EESK Output 4us clock used to shift data in and out Clock of the serial EEPROM EEPROM EECS O4 Output Serial EEPROM chip select Chip Select EEPROM EEDO O4 Output Connected to the DI input of the serial Data Out SDOUT EEPROM EEPROM EEDI with pull Input Connected to the DO output of the Data In down serial EEPROM 103 IC Base 50 052 with pullup Input External switches can be connected to 105 106 these lines to select between predefined EEPROM configurations The values of these pins are readable These pins are used in ISA mode only If in PCMCIA mode these pins are not used nTransmit nTXLED OD16 Internal ENDEC Transmit LED output LED nTransmit nTXEN O162 External ENDEC Active low Transmit Enable Enable output 12 nRoard nBSELED Internal ENDEC Board Select LED activated Select LED by accesses to I O space nlOWR active with AEN low and valid address decode for ISA and with nREG low and and Enable Function bit in the ECOR register is high for PCMCIA The pulse is stretched beyond the access duration to make the LED visible Receive with pullup External ENDEC NRZ receive data input Data 14 DESCRIPTION OF PIN FUNCTIONS SYMBOL DESCRIPTION nReceive nRXLED OD16 Internal ENDEC Receive LED output LED Receive RXCLK with pullup External ENDEC Receive clock input nLink LED nLNKLED OD16 Internal ENDEC Link
90. ions and a 10BASE T interface for twisted pair applications Functions common to both are 1 Manchester encoder decoder to convert NRZ data to Manchester encoded data and back 2 A 32 ms jabber timer to prevent inadvertently long transmissions When jabbing occurs the transmitter is disabled automatic loopback is disabled 10BASE T mode and a collision indication is given to the controller The interface unjabs when the transmitter has been idle for a minimum of 256 ms 3 Aphase lock loop to recover data and clock from the Manchester data stream with up to plus or minus 18ns of jitter 4 Diagnostic loopback capability 5 LED drivers for collision transmission reception and jabber 10BASE T The 10BASE T interface conforms to the twisted pair MAU addendum to the 802 3 specification On the transmission side it converts the NRZ data from the controller to Manchester data and provides the appropriate signal level for driving the media Signal are predistorted before transmission to minimize ISI In half duplex mode the collision detection circuitry monitors the simultaneous occurrence of received signals and transmitted data on the media During 97 transmission data is automatically looped back to the receiver except during collision periods in which case the input to the receiver is network data During collisions should the receive input go idle prior to the transmitter going idle input to the
91. ision drivers The exact nature of the interrupt can be 16COL 16 collisions obtained from the EPH Status Register EPHSR 62 WAKE Magic Packet is received if enabled OVRN Set when the receiver overruns due to a failed memory allocation The OVRN bit of the EPHSR will also be set but if a new packet is received it wil be cleared The RX_OVRN INT bit however latches the overrun condition for the purpose of being polled or generating an interrupt and will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set ALLOC INT Set when an MMU request for TX pages allocation is completed This bit is the complement of the FAILED bit in the ALLOCATION RESULT register The ALLOC INT ENABLE bit should only be set following an allocation command and cleared upon servicing the interrupt TX EMPTY INT Set if the TX FIFO goes empty can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission This bit latches the empty condition and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set If a real time reading of the FIFO empty is desired the bit should be first cleared and then read The TX EMPTY INT ENABLE should only be set after the following steps a b a packet is enqueued for transmission the previous empty condition is cleared acknowledged 63 TX INT
92. itself Clearing this bit EPH STP MON 0 X 0 0 0 0 X 0 PAD E FORCO LOOP TXENA N L 0 X X X X 0 0 0 Normal Operation in promiscuous mode allows it to not receive its own packet MON CSN When set the SMC91C95 monitors carrier while transmitting It must see its own carrier by the end of the preamble If it is not seen or if carrier is lost during transmission the transmitter aborts the frame without CRC and turns itself off When this bit is clear the transmitter ignores its own carrier Defaults low NOCRC Does not append CRC to transmitted frames when set allows software to insert the desired CRC Defaults to zero namely CRC inserted PAD EN When set the SMC91C95 will pad transmit frames shorter than 64 bytes with OO Does not pad frames when reset FORCOL When set the transmitter will force a collision by deliberately not deferring After the collision this bit is automatically reset This bit defaults low to normal operation NOTE The LATCOL bit in EPHSR setting up as a result of FORCOL will reset TXENA to O In order to force another collision TXENA must be set to 1 again LOOP Local Loopback When set transmit frames are internally looped to the receiver after the encoder decoder Collision and Carrier Sense are ignored No data is sent out Defaults low to normal mode TXENA Transmit enabled when set Transmit is disabled if clear When the bit is cleared the SMC91C95 will complete the curre
93. l Attempts of CPU writes to this bit are ignored 8028h Extended Status Register ESR Legi ow RINGEVENT This bit is latched to one at the start of each ring frequency cycle input from ring input from modem the MRINGIN signal going high When this bit and RINGENABLE are both set to a one 1 the Changed bit in the MCSR is set to a one 1 This bit is reset if the 88 host writes a one 1 and the change bit in the MCSR register is unaffected if the host writes a zero 0 RINGENABLE When set this bit gates the RINGEVENT into the Changed bit 802Ah Modem I O BASE Register 0 The Modem I O Base registers determine the base address of the I O range used to access function specific registers These registers allow the function s registers to be placed anywhere the host s I O space I O Base 0 contains the low order byte A7 A0 and I O Base 1 contains the high order byte A15 A8 Since the modem function requires 8 I O locations bits 2 0 of I O Base 0 are always 0 Since only A15 to A4 are decoded by the controller 64K address space it is up to the host to resolve any conflicts with addressing above 64K These registers are still accessable even if the Enable Base and Limit bit in the MCOR is cleared 0 8032h Modem Size Register Modem Size Mask 0 0 0 0 The I O Size Register holds a bit mask used to specify the number of address lines d
94. memory is released When the end of packet is detected the status word is placed at the beginning of the receive packet in memory Byte count is placed at the second word If the CRC checks correctly the packet number is written into the RX FIFO The FIFO being not empty causes INT interrupt to be set If CRC is incorrect the packet memory is released and no interrupt will occur gt Save Bank Select amp Address Registers Mask 91094 Interrupts Read Interrupt Register No Yes Cal TX INTR TXEMPTY No Available for No Yes Y Transmission Wite Allocated Pkt into Packet Number Reg Write Ad Reg amp Copy Data amp Source Address Y Enqueue Packet Y Set Ready for Packet Flag Restore Address Pointer amp Y Bank Select Registers Y Unmask 91 94 Interrupts Disable Allocation Interrupt Y Exit ISR FIGURE 10 ETHERNET INTERRUPT SERVICE ROUTINE Retum Buffers to Upper Layer 73 55 IWOISAHd LNO ovd SSduadv 13X V 1V9I901 q9 VWNSO 53 0CV VWSO 53900V 38VMVM 153 X V AINO S IN YAEWNN L339Vd 3M00 XL ites Alda LON 0313 NOILL3 IdINOO XL
95. mode the CSMA CD algorithm is used to gain access to the media 2 FDSE Full Duplex Switched Ethernet Enabled by FDSE bit in TCR bit When the SMC91C95 is configured for FDSE its transmit and receive paths will operate independently and some CSMA CD functions are disabled such as Carrier Sense Behavior in FDSE Mode The main 802 3 section affected by FDSE is 4 2 8 where the Frame Transmission procedural model is presented The changes are 1 No deferral The transmit channel is dedicated and always available The device will transmit whenever it has a packet ready to be sent while respecting the interframe spacing between transmit packets 2 No collision detection There are collisions in a switched environment The EPH implementation of the procedural model uses as collisionDetect the MAC collision input sourced from the 10BASE 70 T front end AUI front end or External Endec interface This collision input is observed by the Transmit State Machine while transmitting is true that is during Preamble Data Pad and CRC states If collision is active during any of these states the state machine transitions to JAM and BACKOFF states 3 10BASE T loopback Typically 10BASE T drivers are internally looped back to the differential receivers Magic Packet Support If the WAKEUP EN bit in the Control Register Bank1 Offset C is set the controller will come out of any powerdown mode I
96. n The initial allocation request is issued when the CSMA block indicates an active reception If allocation succeeds the DMA block stores the packet number assigned to it and generates write arbitration requests for as long as the CSMA CD FIFO is empty In parallel the CSMA CD completes the address filtering and notifies the DMA of an address match If there is no address match the will release the allocated memory and stop reception When the CSMA CD block notifies the DMA logic that a receive packet was completed if the CRC is OK the DMA will either write the previously stored packet number into the RX PACKET NUMBER FIFO to be processed by the or if the CRC is bad the DMA will just issue a release command to the MMU and the CPU will never see that packet Packets with bad can be received if the BAD bit in the configuration register is set If AUTO RELEASE is set a release is issued by the DMA block to the MMU after a successful transmission TX SUCC set and the TX completion FIFO is clocked together with the TX FIFO preventing the packet number from moving into the TX completion FIFO Based on the RX counter value if a receive packet exceeds 1532 bytes reception is stopped by the DMA and the RX ABORT bit in the Receive Control Register is set The memory allocated to the packet is automatically released If an allocation fails the CSMA CD block will activate RX OVR
97. ncremented for each revision to identify the device used of a given device CHIP ID VALUE DEVICE SMC91C90 SMC91C92 5 91 94 SMC91C95 FEAST 67 SPACE BANK OFFSET NAME EARLY REGISTER HIGH BYTE LOW BYTE DISCRD Set to discard a packet being received This bit can be used in conjunction with ERCV THRESHOLD and INT to process packet header while it is being received and sicard it if the packet is not desired Setting this bit will only discard packets that are still in the process of being received If the RCV DISCRD bit is set prior to the end of a receive packet bit in the Interrupt Status Register will be set to indicate that the packet was discarded and its memory released If the receive 68 TYPE READ WRITE SYMBOL ERCV packet is complete prior to the RCV DISCRD bit being set the packet is received normally and RCV INT bit is set in the Interrupt Status Register The DISCRD bit is self clearing ERCV THRESHOLD Threshold for ERCV interrupt Specified in 64 byte multiples Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD ERCV INT bit of the INTERRUPT STATUS REGISTER is set PC Card 5 0 treats the individual functions of multifunction PCMCIA application independently Card and Socket Services C amp SS 5 0 is designed to provide t
98. net function from asserting nIREQ nIREQ pin on power and RESET is in a high 1 de asserted state BIT 1 Enable Base and Limit This bit enables the on board I O base decoder If set the on 82 rle 5 e SRESET LevIREQ WRATTRI Enable B IREQ 0 1 0 0 0 0 Enable Base and Limit Enable Function board decoder is used to select the function If cleared the decoder is disabled and it is assumed that the host provides for the decoding When the decode is disabled the function is enabled and is configured for 16 bits and not in power down mode the signal 101516 is always asserted It is then up to the host to qualify the usage of lOls16 For multifunction PCMCIA functionality this bit must be set BIT 0 Enable Function This bit enables 1 or disables 0 the Ethernet function While the Ethernet function is disabled it remains in powerdown mode no access to the Ethernet IC space ie The bank register are not accessable is allowed is not generated for this function and nINPACK is not returned for accesses to the Ethernet registers If the Magic Packet function is enabled the device is not completly powered down The MAC controller is still enabled to receive 8002h Ethernet Configuration and Status Register ECSR Eee 0 0 0 0 BIT 7 Not defined BIT 6 Not defined BIT 5 10158 This bit when set indica
99. nly four banks in ISA mode therefore accesses to non existing banks BS2 1 are ignored six banks are accessible in PCMCIA mode 39 SPACE BANKO OFFSET NAME 0 TRANSMIT CONTROL REGISTER TYPE READ WRITE SYMBOL TCR This register holds bits programmed by the CPU to control some of the protocol transmit options HIGH BYTE LOW BYTE FDSE Full Duplex Switched Ethernet When set the SMC91C95 is configured for Full Duplex Switched Ethernet it defaults clear to normal CSMA CD protocol In FDSE mode the SMC91C95 transmit and receive processes are fully independent namely no deferral and no collision detection are implemented When FDSE is set FDUPLX is internally assumed high and MON CSN is assumed low regardless of their actual values EPH LOOP Internal loopback at the EPH block Does not exercise the encoder decoder Serial data is looped back when set Defaults low NOTE After exiting the loopback test an SRESET in the ECOR or the SOFT RST in the RCR must be set before returning to normal operation STP SQET Stop transmission on SQET error If set stops and disables transmitter on SQE test error Does not stop on SQET error and transmits next frame if clear Defaults low FDUPLX When set it enables full duplex operation This will cause frames to be received if they pass the address filter regardless of the source for the frame When clear the node will not receive a frame sourced by
100. nt transmission before stopping When stopping due to an error this bit is automatically cleared TRANSMITS FDUPLX EPH LOOP LOOP LOOPS AT TO NETWORK EPH Block ENDEC Normal CSMA CD No Loopback Full Duplex Switched Ethernet No loopback and no SQET SPACE BANKO OFFSET NAME 2 EPH STATUS REGISTER TYPE READ ONLY SYMBOL EPHSR This register stores the status of the last transmitted frame This register value upon individual transmit packet completion is stored as the first word in the memory area allocated to the packet Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions The register can be used for real time values like TXENA and LINK If TXENA is cleared the register holds the last packet completion status HIGH BYTE LOW BYTE TXUNRN Transmit Underrun Set if underrun occurs it also clears TXENA bit in TCR Cleared by setting TXENA high This bit may only be set if early TX is being used LINK OK State of the 10BASE T Link Integrity Test A transition on the value of this bit generates an interrupt when the LE ENABLE bit in the Control Register is set OVRN Upon FIFO overrun the receiver asserts this bit and clears the FIFO The receiver stays enabled After a valid preamble has been detected on a subsequent frame OVRN is de asserted The RX OVRN INT bit in the Interrupt Status Register
101. ogic and never overlap DMA BLOCK The DMA block resides between the CSMA CD block and the arbiter It can interface both the data path and the control path of the CSMA CD block for different operations Its functions include the following e Start transmission into the CSMA CD block e Generate CSMA CD side addresses for accessing memory during transmit and receive operations e Generate MMU memory verify success Compute byte count and write it in first locations of receive packet e Write transmit status word in first locations of transmit packet e Determine if enough memory is available for reception e De allocate transmit memory after suitable completion e De allocate receive memory upon error conditions process requests and 93 e Initiate retransmissions upon collisions if less than 16 retries e Terminate reception and release memory if packet is too long The specific nature of each operation and its trigger event are 1 TX operations will begin if TXENA is set and TX FIFO is not empty The DMA logic does not need to use the TX PACKET NUMBER it goes directly from the FIFO to the MMU However the DMA logic controls the removal of the PACKET NUMBER from the FIFO Generation of CSMA CD side addresses into memory Independent 11 bit counters are kept for transmit and receive in order to allow full duplex operation MMU requests for allocation are generated by the DMA logic upon receptio
102. on and are not expected to change during run time This register is part of the EEPROM saved setup in ISA mode only In PCMCIA mode this register is initialized to the state as defined below the corresponding bits as if no EEPROM was present in ISA mode i e ENEEP pin is a don t care in PCMCIA mode HIGH NO FULL SET AUI BYTE WAIT STEP SQLCH SEE LOW 16 BIT DIS Reserved INT INT BYTE LINK SEL1 SELO Function 0 1 1 of EN16 pin NO WAIT When set does not request additional 16BIT Used in conjunction with nEN16 and 58 wait states An exception to this are accesses to in PCMCIA mode only to define the width of the the Data Register if not ready for a transfer When system bus If the nEN16 pin is low this bit is clear negates IOCHRDY for two to three 20 MHz forced high Otherwise the bit defaults low and can clocks on any cycle to the SMC91C95 be programmed by the host CPU DIS LINK This bit is used to disable the 10BASE T link test functions When this bit is high the SMC91C95 disables link test functions by not generating nor monitoring the network for link pulses In this mode the SMC91C95 will transmit packets regardless of the link test the EPHSR LINK OK bit will be set and the LINK LED will stay on When low the link test functions are enabled If the link status indicates FAIL the EPHSR LINK OK bit will be low while transmit packets enqueued will be processed by the SMC91C95 AUI SELECT When set the AUI inter
103. ous transmit and receive traffice in some full duplex applications Packet reception transmission determined by memory availability All other resources are always available if memory is available To complement this flexible architecture all ISA bus interface functions are incorporated in the SMC91C95 as well as a 4608 byte packet RAM and serial EEPROM based setup The user can select or modify configuration choices The SMC91C95 stores the Configuration Information Structure CIS on reset or power up from the serial EEPROM This allows the host to access data to allow the setup of the PCMCIA multi function card In ISA mode the serial EEPROM acts as storage for configuration and IEEE Ethernet address information compatible with the existing 9000 family of ISA Ethernet controllers In PCMCIA mode the serial EEPROM stores the CIS as well as the IEEE address information but it does not store any I O or IRQ information since this information is handled by the host s socket controller For CIS requirements above 512 bytes an optional external parallel EEPROM be used in conjunction with the internal CIS This allows additional external non volatile storage for applications that require XIP and use the modem function If the serial EEPROM is not used in PCMCIA mode the parallel EEPROM must be used n this case the parallel EEPROM is selected for the first 512 bytes of storage as well allowing the
104. packets existing beneath the TX and RX areas is managed by the MMU The MMU dynamically allocates and releases memory to be used by the transmit and receive functions The MMU related parameters for the SMC91C95 are RAM size 6 kbytes internal Max number of packets 24 Max pages per packet 6 Max number of pages 24 Page size 256 bytes REGISTER POINTER RCV VS TX AREA SELECTION 11 BIT LOGICAL ADDRESS p 0 FIGURE 4 MAPPING AND PAGING VS RECEIVE AND TX AREA 25 TXPACKET NUMBER PHYSICAL MEMORY RX PACKET NUMBER PAGE 256 bytes REGISTER PACKET CPU SIDE TX FIFO PACKET B STATUS COUNT DATA p STATUS COUNT DATA TO TX COMPLETION FIFO PACKET FIFO PORTS FE REGISTER STATUS COUNT DATA LINEAR ADDRESS FIGURE 5 TRANSMIT QUEUES AND MAPPING 26 MEMORY B ud MMU MAPPING FIFO PORTS REGISTER STATUS COUNT PACKET D DATA CPU SIDE RX FIFO STATUS COUNT PACKET E DATA LINEAR ADDRESS MMU MAPPING FIGURE 6 RECEIVE QUEUE AND MAPPING 27 45
105. put pair 121 TPE Receive TPERXP Diff Input 10BASE T receive differential inputs 122 TPERXN 4 TPE TPETXP Diff Output Internal ENDEC 10BASE T transmit 6 Transmit TPETXN differential outputs 5 TPE TPETXDP Diff Output 10BASE T delayed transmit differential 7 Transmit TPETXDN outputs Used in combination with TPETXP Delayed and TPETXN to generate the 10BASE T transmit pre distortion 1 Powerdown PWRDWN I with pullup Internal ENDEC Powerdown input It keeps the SMC91C95 in powerdown mode when high open Must be low for normal operation Refer to the Powerdown Matrix following for further details Transmit TXCLK External ENDEC Transmit clock input from Clock external ENDEC nWakeup nWAKEUP I with pullup Input When pulled down the device will Enable EN enable Magic Packet MP logic and put the Ethernet function in powerdown mode The pin assertion will override the state of WAKEUP_EN and PWRDN bits in CTR Pwrdwn bit in ECSR and Enable Function bit ECOR When deasserted the WAKEUP_EN and PWRDN bits will be changed to 0 Pwrdwn to 0 and Enable Function to 1 1 14 00 Wakeup WAKEUP O4 Output Asserted high if nWAKEUP EN is asserted and a valid Magic Packet MP pattern is detected The pin remains asserted until WAKEUP is deasserted 118 Bias RBIAS Analog Input A 22 kohm 196 resistor should be connected Resistor between this pin and analog ground 16 OF PIN FUNCTIONS EE SYMBOL
106. r The read access time is 40ns and the cycle time is 185ns If any one of them does not satisfy the application requirements wait states should be added If the access time is the problem IOCHRDY should be negated for all accesses to the SMC91C95 This can be achieved by programming the NO WAIT ST bit in the configuration register to 0 The SMC91C95 will negate IOCHRDY for 100ns to 150ns on every access to any register If the cycle time is the problem programming NO WAIT ST as described before will solve it but at the expense of slowing down all accesses The alternative is to let the SMC91C95 negate IOCHRDY only when the Data Register FIFOs require so Namely if NO WAIT ST is set IOCHRDY will only be negated if a Data Register read cycle starts and there is less than a full word in the read FIFO or if a write cycle starts and there is more than two bytes in the write FIFO The cycle time is defined as the time between leading edges of read from the Data Register or equivalently between trailing edges of write to the Data Register For example in an ISA system the cycle time of a 16 bit transfer will be at least 2 clocks for the I O access to the SMC91C95 one clock for the memory cycle 3 clocks In absolute time it means 375ns for a 8MHz bus and 240ns for a 12 5 MHz bus The cycle time will not increase when configured for full duplex mode because the CSMA CD memory arbitration requests are sequenced by the DMA l
107. r less is required the nFCS and nFWE output pins of the SMC91C95 need not be used if serial EEPROM is being used Internal to the SMC91C95 the memory addressing logic will allow byte or word access on even byte boundaries This implies that on odd byte address access A0 1 the SMC91C95 will generate a arbitrary value of Zero 0 since the PCMCIA specification states that the high byte of a word access in attribute memory is a don t care This allows backward compatibility to 8 bit hosts Table 11 Attribute Memory Decodes Using Serial EPROM ATTRIBUTE EXTERNAL EPROM INTERNAL SRAM CONFIGURATION MEMORYADDRESS STORE STORE 512 BYTES REGISTERS Table 12 Attribute Memory Decodes without Serial EPROM ATTRIBUTE EXTERNAL EPROM INTERNAL SRAM CONFIGURATIO MEMORYADDRESS STORE STORE BYTES N 81 PCMCIA CONFIGURATION REGISTERS DESCRIPTION Ethernet Function Base Address 8000h 8000h Ethernet Configuration Option Register ECOR BIT 7 SRESET This bit when set will clear all internal registers associated with the Ethernet function except itself 6 LevIREQ This bit is read only and reads as a one to indicate level mode interrupts are used Pulse mode interrupts are not supported BIT 5 Not defined BIT 4 Not defined BIT 3 WRATTRIB This bit when when set 1 allows writting into the external attribute memory space BIT 2 Enable IREQ Routing This bit enables 1 or disables 0 the Ether
108. register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO The packet numbers to be processed by the interrupt service routines are read from this register REMPT RX FIFO PACKET NUMBER BYTE Y 0 0 0 0 0 1 0 0 LOW TEMPT TX DONE PACKET NUMBER BYTE Y 1 0 0 REMPTY No receive packets queued in the RX FIFO For polling purposes uses the bit in the Interrupt Status Register TOP OF RX FIFO PACKET NUMBER Packet number presently at the output of the RX FIFO Only valid if REMPTY is clear The packet is removed from the RX FIFO using MMU Commands 3 or 4 TEMPTY No transmit packets in completion queue For polling purposes uses the TX INT bit in the Interrupt Status Register 0 0 0 0 0 TX DONE PACKET NUMBER Packet number presently at the output of the TX Completion FIFO Only valid if TEMPTY is clear The packet is removed when a TX INT acknowledge is issued NOTE For software compatibility with future versions the value read from each FIFO register is intended to be written into the PNR as is without masking higher bits provided TEMPTY and REMPTY 0 respectively SPACE BANK2 OFFSET NAME 6 POINTER REGISTER HIGH CV AUTO READ ETEN BYTE INCR 0 0 0 0 0 LOW BYTE POINTER REGISTER The value of this register determines the address to be accessed within the transmit or receive areas It will auto increment on accesses to the data regi
109. rnal transceivers via its AUI port Only one additional IC is required on most applications The SMC91C95 occupies 16 locations and no memory space except for PCMCIA attribute memory space The same space is used for both ISA and PCMCIA operations The SMC91C95 can directly interface the ISA and PCMCIA buses and deliver no wait state operation Its shared memory is sequentially accessed with 40ns access times to any of its registers including its packet memory DMA services are used by the SMC91C95 virtually decoupling network traffic from local or system bus utilization packet memory management the SMC91C95 integrates a unique hardware Memory Management Unit MMU with enhanced performance decreased software overhead when compared to ring buffer and linked list architectures The SMC91C95 is portable to different CPU and bus platforms due to its flexible bus interface flat memory structure no pointers and its loosely coupled buffered architecture not sensitive to latency The 5 91 95 interfaces directly with Rockwell International L39 C39 controller based modems and Lucent Technologies HSM288xCF modem OVERVIEW A unique architecture allows the SMC91C95 to combine high performance flexibility high integration and simple software interface The SMC91C95 incorporates the SMC91C92 4 functionality for ISA environments with several new features as well as a PCMCIA interface and attribu
110. ster when AUTO INCR is set The increment is by one for every byte access and by two for every word access When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number when is clear the address refers to the transmit area and uses the packet number at the Packet Number Register READ bit Determines the type of access to follow If the READ bit is high the operation intended is a read If the READ bit is low the operation is a write Loading a new pointer value with the READ bit high generates a pre fetch into the Data Register for read purposes Readback of the pointer will indicate the value of the address last accessed by the CPU rather than the last pre fetched This allows any interrupt routine that uses the pointer to save it and restore it without affecting the process being interrupted TYPE READ WRITE SYMBOL PTR POINTER HIGH 0 0 0 POINTER LOW 0 0 0 0 0 0 0 0 The Pointer Register should not be loaded until 400ns after the last write operation to the Data Register to ensure that the Data Register FIFO is empty If the pointer is loaded using 8 bit writes the low byte should be loaded first and the high byte last ETEN bit When set enables EARLY Transmit underrun detection Normal operation when clear For Underrun detection purposes the RAM logical address and packet numbers of the packet being loaded are compared against the logical address and
111. t successful completion The allocation time can take worst case N2 N1 NO 2 200ns 010 2 RESET MMU TO INITIAL STATE Frees all memory allocations clears relevant interrupts resets packet FIFO pointers 011 3 REMOVE FRAME FROM TOP OF FIFO To be issued after CPU has completed processing of present receive frame This command removes the receive packet number from the RX FIFO and brings the next receive frame if any to the RX area output of RX FIFO 100 4 REMOVE AND RELEASE TOP OF RX FIFO Like 3 but also releases all memory used by the packet presently at the RX FIFO output 101 5 RELEASE SPECIFIC PACKET Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER Should not be used for frames pending transmission Typically used to remove transmitted frames after reading their completion status Can be used following 3 to release receive packet memory in a more flexible way than 4 56 110 ENQUEUE PACKET NUMBER INTO TX This is the normal method of transmitting packet just loaded into RAM The packet number to be enqueued is taken from the PACKET NUMBER REGISTER 111 RESET TX FIFOs This command will reset both TX FIFOs the TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO This command provides mechanism for canceling packet transmissions and reordering or bypassing the transmit queue The RESET TX FIFOs command should only b
112. t is set the Intr bit must be cleared by the host writing a 0 into it If the function requires additional service the Intr bit will remain asserted when the host writes the O Base Register 0 amp 1 I O Base 0 amp 1 Address 800 amp 800Ch 800Ah Ethernet I O BASE Register 0 The I O Base registers determine the base address of the I O range used to access function specific registers These registers allow the function s registers to be placed anywhere in the host s I O space I O Base 0 contains the low order byte A7 A0 and I O Base 1 contains the high order byte A15 A8 Since the Ethernet function requires 16 I O locations bits 3 0 of Base 0 are always 0 84 Since only A15 to A4 are decoded by the controller 64K address space it is up to the host to resolve any conflicts with addressing above 64K The default decode value is 300h A9 A8 1 others 0 NOTE These registers are ignored in ISA mode These registers are still accessable even if the Enable Base and Limit bit in the MCOR is cleared 0 Modem Function Base Address 80201 8020h Modem ACIE T EN Register EN SRESET LevIREQ Enable IREQ BIT 7 SRESET This bit when set clears all internal registers associated with the Modem function except itself and asserts the nMRESET pin 6 LevIREQ This bit is read only and reads as a one to indicate level mode interrupts are used Pulse mode interrupts are not supported
113. t is in full duplex RX_ABORT This bit is set if a receive frame is aborted due to length longer than 1532 bytes The frame will not be received The bit is cleared by RESET or by the CPU writing it low Packet Too Long Run out of Memory During Receive RX_ABORT 44 RX_OVRN_INT SPACE BANKO OFFSET NAME 6 COUNTER REGISTER TYPE READ ONLY SYMBOL ECR Counts four parameters for MAC statistics When any counter reaches 15 an interrupt is issued All counters are cleared when reading the register and do not wrap around beyond 15 HIGH NUMBER OF EXC DEFFERED TX BYTE LOW MULTIPLE COLLISION COUNT BYTE Each four bit counter is incremented every time the corresponding event as defined in the EPH STATUS REGISTER bit description occurs Note that the counters can only increment once per enqueued transmit packet never faster limiting the rate of interrupts that can be generated by the counters For example if a packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented by one If a packet experiences between 2 to 16 collisions the MULTIPLE COLLISION COUNT field is incremented by one If a packet experiences NUMBER OF DEFFERED TX SINGLE COLLISION COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 deferral the NUMBER OF DEFERRED IX field is incremented by one even if the packet experienced multiple deferrals during its collision retries The COUNTER REGISTER
114. te registers that comply with the PCMCIA Multi Function specification Mode selection between ISA and PCMCIA is static and is done only once at the end of power on reset The SMC91C95 consists of the same logical I O register structure in ISA PCMCIA modes However some of the signals used to access the PCMCIA differ from the ISA mode Additional registers exist in the PCMCIA attribute space The ROM memory space only exists in ISA mode and the attribute space only exists in PCMCIA mode decoders are included in the SMC91C95 s PCMCIA interface with independent decoders for the LAN and for the modem functions These decoders are used whenever the SMC91C95 is used as a multi function card and they can be bypassed when only one function is enabled The SMC91C95 also merges the LAN s internal interrupt source with the external modem interrupt connected to the SMC91C95 The MMU Memory Management Unit architecture used by the SMC91C95 combines the simplicity and low overhead of fixed areas with the flexibility of linked lists providing improved performance over other methods The SMC91C95 is designed to support full duplex switched Ethernet where transmit and receive are fully independent It has 6 kbytes of internal memory and the MMU manages memory in 256 byte pages The memory size accommodates the increase in interrupt latency resulting from simultaneous LAN and modem operation as well as the potential for simultane
115. tes that the Host can only do 8 bit cycles on 07 00 The Ethernet function is forced in this case to eight bit mode regardless of the nEN16 pin and 16BIT value This bit also disables floats the 101516 signal BIT 4 Not defined BIT 3 Not defined 2 PwrDwn When set 1 this bit puts the SMC91C95 Ethernet function into powerdown mode The Ethernet function is also put into powerdown mode when the Enable Function bit ECOR bit 0 is cleared Refer to the Powerdown Logic section for additional details as to what logic is powered down BIT 1 Intr This bit is read set to a one when this function is requesting interrupt service It is cleared depending upon the setting of IntrACK 83 0 0 0 0 When this bit and Enable IREQ Routing are set IREQOut is asserted All setting and resetting of this bit is edge triggered with exception of the internally generated reset signal for the modem Ethernet related PC card registers The Intr bit can be reset the following ways and priority ranging from 1 highest to 3 lowest A hardware reset power up 2 The function ie interrupt source can only reset this field to zero 0 if the IntrACK field is reset to zero 0 3 The host system can only reset this field to a zero 0 only if the IntrACK bit is set to a one 1 BIT 0 IntrACK This bit controls the clearing of the Intr bit When this bit is cleared Intr reflects the function s interrupt status When this bi
116. the CPU to specify which registers the EEPROM RELOAD or STORE refers to When high the General Purpose Register is the only register read or written When low the RELOAD and STORE functions are enabled RELOAD In ISA Mode The SMC91C95 reads the Configuration Base and Individual Address and STORE writes the Configuration and Base registers Also when set it wil read the EEPROM and update relevant registers with its contents This bit then Clears upon completing the operation In PCMCIA Mode The SMC91C95 reads the contents of the EEPROM stores the 54 contents in the SMC91C95 CIS SRAM as defined in Table 10 STORE In ISA Mode The STORE bit when set stores the contents of all relevant registers in the serial EEPROM This bit is cleard upon completing the operation In PCMCIA Mode The SMC91C95 performs no function NOTE When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high The remaining 14 bits of this register will be invalid During this time attempted read write operations other than polling the EEPROM status will NOT have any effect on the internal registers The CPU can resume accesses to the SMC91C95 after both bits are low A worst case RELOAD operation initiated by RESET or by software takes less than 750 usec PCMCIA EEPROM to SRAM Memory Map As defined in the PCMCIA specification Odd byte attribute memory locations are a don t care In order to utilize the
117. ugh the SMC91C95 s I O space The data path is of The RAM is accessed by mapping it into I O space sequential access nature and typically works in for sequential access Except for the RAM one direction at any given time An internal DMA accesses and the MMU request release type of interface connects the data path to the commands I O accesses are not arbitrated device RAM through the arbiter and MMU The I O space is 16 bits wide Provisions for 8 bit The CSMA CD data path interface is systems are handled by the bus interface accessible to the host CPU 23 The internal interface arbitrate for access and request memory from the MMU when necessary An encoder decoder block interfaces the CSMA CD block on the serial side The encoder will do the Manchester encoding of the transmit data at 10 Mbps while the decoder will recover the receive clock and decode received data Carrier and Collision detection signals are also handled by this block and relayed to the CSMA CD block The encoder decoder block can interface the network through the AUI interface pairs or it can be programmed to use the internal 10BASE T transceiver and connect to a twisted pair network The twisted pair interface takes care of the medium dependent signaling for 10BASE T type of networks lt is responsible for line interface with external pulse transformers and resistors collision detection as well as t
118. will also be set and stay set until cleared by the CPU Note that receive overruns could occur only if receive memory allocations fail Counter Roll over When set one or more 4 bit counters have reached maximum count 15 Cleared by reading the ECR register TX LINK _ _ LOST LATCOL wey UNRN OK OVRN _ ROL DEF CARR TX LTX SQET 16COL LTX MUL SNGL TX 80 DEFR BRD MULT COL COL EXC DEF Excessive deferral When set last current transmit was deferred for more than 1518 2 byte times Cleared at the end of every packet sent LOST Lost carrier sense When set indicates that Carrier Sense was not present at end of preamble Valid only if MON CSN is enabled This condition causes TXENA bit in TCR to be reset Cleared by setting TXENA bit in TCR LATCOL Late collision detected on last transmit frame If set a late collision was detected later than 64 byte times into the frame When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR Cleared by setting TXENA in TCR WAKEUP When this bit is set it indicates that a receive packet was received that had the Magic Packet MP signature of the node s own IP address repetitions in it This bit indicates a valid detection for magic packet enabled by nWAKEUPEN pin 92 QFP or WAKEUP_EN in CTR NOTE If the MP mode is activated using the nWAKEUPEN pin the pin must be deasserted to exit the mode TX_DEFR
119. with no glue to interface to the ISA or PCMCIA bus The functions done in this block are address decoding for and ROM memory including address relocation support for ISA data path routing sequential memory address support optional wait state generation boot ROM support EEPROM setup function bus transceiver control and interrupt generation selection For ISA I O address decoding is done by comparing A15 A4 to the I O BASE address determined in part by the upper byte of the BASE ADDRESS REGISTER and also requiring that AEN be low If the above address comparison is satisfied and the SMC910C95 is in 16 bit mode nlOCS16 will be asserted low 92 A valid comparison does not yet indicate a valid I O cycle is in progress as the addresses could be used for a memory cycle or could even glitch through a valid value Only when nlORD or nlIOWR are activated the I O cycle begins In PCMCIA mode A4 A15 are ignored for I O decodes which rely on the PCMCIA host decoding for the slot Input A10 for ISA is used as an output nFWE for PCMCIA to enable Flash Memory Write for programming the attribute memory It is valid only when nWE is 0 and COR2 is 1 nA11 nFCS is used to select the Flash Memory Chip WAIT STATE POLICY The SMC91C95 can work on most system buses without having to add wait states The two parameters that determine the memory access profile are the read access time and the cycle time into the Data Registe

SMC Networks SMC91C95 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents