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Renesas M16C/6NK User's Manual

1. Symbol 0300h 0301h 0302h T CAN1 Message Box 10 Identifier DLC 0303h 0304h 0305h 0306h 0307h 0308h o309h CAN1 Message Box 10 Data Field 030Ah 3 030Bh 030Ch 030Dh 030Eh Ti 030Fh CAN1 Message Box 10 Time Stamp 0310h 0311h osien CAN1 Message Box 11 Identifier DLC 0314h 0315h 0316h 0317h 0318h D CAN1 Message Box 11 Data Field 031Bh 031Ch 031Dh 031Eh ES 031Fh CAN1 Message Box 11 Time Stamp 0320h 0321h 0322h 0323h CAN1 Message Box 12 Identifier DLC 0324h 0325h 0326h 0327h E rM 0329h o32Ah CAN1 Message Box 12 Data Field 032Bh 032Ch 032Dh 032Eh oTi 032Fh CAN1 Message Box 12 Time Stamp 0330h 0331h 0332h 0333h CAN1 Message Box 13 Identifier DLC 0334h 0335h 0336h 0337h 0338h 0339h o33Ah CAN1 Message Box 13 Data Field 033Bh 033Ch 033Dh 033Eh m 033Fh CAN1 Message Box 13 Time Stamp X Undefined Rev 2 00 Nov 28 2005 page 31 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 14 SFR Information 14 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0
2. Symbol 0100h 0101h oon CANO Message Box 10 Identifier DLC 0104h 0105h 0106h 0107h 0108h o109h CANO Message Box 10 Data Field 010Ah d 010Bh 010Ch 010Dh 010Eh ae O10Fh CANO Message Box 10 Time Stamp 0110h 0111h enen CANO Message Box 11 Identifier DLC 0114h 0115h 0116h 0117h 0118h 0119h O11Ah CANO Message Box 11 Data Field 011Bh 011Ch 011Dh O11Eh ud O11Fh CANO Message Box 11 Time Stamp 0120h 0121h 0122h 0123h CANO Message Box 12 Identifier DLC 0124h 0125h 0126h 0127h 0128h 0129h f 012Ah CANO Message Box 12 Data Field 012Bh 012Ch 012Dh 012Eh D 012Fh CANO Message Box 12 Time Stamp 0130h 0131h 0132h ta 0133h CANO Message Box 13 Identifier DLC 0134h 0135h 0136h 0137h 0138h 0139h 013Ah CANO Message Box 13 Data Field 013Bh 013Ch 013Dh 013Eh Jo 013Fh CANO Message Box 13 Time Stamp X Undefined Rev 2 00 Nov 28 2005 page 23 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 6 SFR Information 6 Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh
3. NOTES 1 Calculated according to the BCLK frequency as follows 0 5 x 10 ZA 1 f BCLK OPS 2 Calculated according to the BCLK frequency as follows n 0 5 x 10 40 n is 1 for 1 wait setting 2 for 2 wait setting and 3 for 3 wait setting BCLK ns When n 1 f BCLK is 12 5 MHz or less 3 This standard value shows the timing when the output is off and does not show hold time of data bus Hold time of data bus varies with capacitor volume and pull up pull down resistance value Hold time of data bus is expressed in t CR X In 1 Vo Voc by a circuit of the right figure For example when Vo 0 2 Vcc C 30 pF R 21 KQ hold time of output L level is t 2 30 pF X 1 KQ X In 1 0 2 Vcc Vcc 6 7 ns Rev 2 00 Nov28 2005 page 303 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Switching Characteristics VCC 5V Referenced to VCC 5V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 27 Memory Expansion Mode and Microprocessor Mode for 2 to 3 wait setting external area access and multiplexed bus selection Measuring Standard Parameter zs tacLk aD Address output delay time Figure 22 3 tnBcLK AD Address output hold time refers to BCLK 4 th RD A
4. Figure20 5 I O Ports 5 Pd A BYTE signal input O NOTE 1 CNVSS CNVSS signal input RESET RESET signal input f QccHeM Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC Figure20 6 I O Pins Rev 2 00 Nov 28 2005 page 253 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Port Pi Direction Register i 0 to 7 9 to 13 0 0 9 Symbol Address After Reset PDO to PD3 03E2h 03E3h 03E6h 03E7h 00h PD4 to PD7 OS3EAh O3EBh 03EEh O3EFh 00h PD9 to PD12 4 03F3h 03F6h 03F7h O3FAh 00h PD13 4 O3FBh 00h roo p oben ae Functions as an input port n eee an output port PDi6 _ Port Pi_6 Direction Bit 1 Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRC2 bit in the PRCR register to 1 write enabled 2 During memory expansion and microprocessor modes the PD register for the pins functioning as bus control pins AO to A19 DO to D15 CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified Not available memory expansion and microprocessor modes in T V ver 3 When using the ports P11 to P13 set the PU37 bit in the PURG register to 1 usable 4 The PD11 to PD13 registers are only in the 128 pin version
5. ES D S FS 8 8 S S N N m E BI P9 6 ANEX1 CTXO SOUTA a gt P9_7 ADTRG SIN4 co P9 3 DAO TB3IN a gt lt P9 2 TB2IN SOUTS a gt s P9_4 DA1 TB4IN o 1 P9 1 TB1IN SIN3 a gt P9 5 ANEXO CRXO CLK4 m o P9 O TBOIN CLK3 a gt 5 lt gt P8 1 TA4IN U P14 0 lt lt BYTE CNVSS P8 7 XCIN a gt 5 P8_3 INT1 lt P8 2 INTO P14 1 SIN4 lt gt P8_4 INT2 ZP P8 5 NMI P8 6 XCOUT P8 O TA4OUT U P7 6 TASOUT CTX1 a gt P7 7 TASIN CRX1 a X 1 P7 1 and P9 1 are N channel open drain pins 2 Not available the bus control pins except CLKOUT pin in T V ver Figure 1 4 Pin Configuration Top View 2 Rev 2 00 Nov28 2005 page 9 of 378 REJO9BO0124 0200 131 NESAS P7 5 TA2IN W SOUT4 8 P7 A TA2OUT N CLK4 P6_7 TXD1 SDA1 gt 8 P7_3 CTS2 RTS2 TAIINV 1 P7 1 RXD2 SCL2 TAOIN TBSIN 1 gt P7 2 CLK2 TA1OUT V E P7 O TXD2 SDA2 TAOOUT E P6 6 RXD1 SCL1 lt gt a P6 A CTST RTS1 CTSO CLKS1 gt P6 5 CLK1 4 vss Package PLQP0128KB A Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 1 6 Pin Characteristics for 128 Pin Package 1 Contro
6. sssssesessesseeseeeeeeennen nennen nnne nnnen nenne nn nennen rnn senten s nnne 17 2 5 ricerca EDEN 17 2 6 User Stack Pointer USP Interrupt Stack Pointer ISP ssssssseeeeneenennnenennenns 17 2 7 Static Base Register SB sssssssssssssssessseseeenen eene nennen nennt sentes en tres en tnn i ni tnns rette nennen nns 17 2 9 Flag Register EEG ue riter ite sa oec aia a E E eaaa tret ext ibas a A EE Erud iei 17 2 9 1 Carry Flag C Flag deett tte cineri iet n bs eld epit edet stu doce Eee xr di k nas a aa ode reas 17 2 8 2 Debug Flag D Flag P ES 17 2 8 3 Zero Flag Z IAQ ut netter oe diete uet cate utar tne deel ad tsa ans ier abest deed 17 2 8 4 Sign Flag S Flag etienne temere t en nna ic CERE CHA raaa Aaaa ASEA ERE RR ann Fa doc aE 17 2 8 5 Register Bank Select Flag B Flag nennen nnne nnne nennen enne 17 2 8 6 Overflow Flag O Flai eth oi eed tiere pas aaae leds te exea a heo Poe Fou S Congue a desk RA 17 2 8 7 Interr pt Enable Flag l Flag 2 i iieri coche apie Fd sr ELE einen 17 28 8 Stack Pointer Select Flag U Flag teet eter tette sec ne eR Det atone xh dou dux 17 2 8 9 Processor Interrupt Priority Level IPL ssssssssssseseneeneeenneeennnenennnenn nennen nnns 17 e GTO ROSCO d ATO eiit pee A veined usd prx Sa 17 Se MEMON aerer e e RN ran er mr nT ea eaa ROI RESTER II NETT PEPERIT TRU TTE 18 4 Spec
7. 1 Referenced to VCC 4 2 to 5 5V at Topr 40 to 85 C unless Main clock input oscillation frequency x vis 5 Flash memory version no wait otherwise specified 2 Relationship between main clock oscillation frequency and supply S 10 0 pacers ee eene ee pases voltage is shown right S 3 Execute program erase of flash memory by VCC 5 0 0 5 V 5 4 When using over 16MHz use PLL clock PLL clock oscillation i frequency which can be used is 16MHz or 20MHz mE Scu 42 5 5 VCC V main clock no division f ripple f ripple Power Supply Ripple Allowable Frequency VCC VP P ripple y V V P rl e Power Supply Ripple Allowable Se MNA NY P P ripple Amplitude Voltage Figure 22 21 Timing of Voltage Fluctuation Rev 2 00 Nov28 2005 page 330 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 22 49 Electrical Characteristics 1 HIGH Output Voltage Parameter PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 7 P3 0 to P8 7 P4 0 to P4 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11 0toP11 7 P12_0 to P12 7 P13_0 to P183 7 P14 0 P14 1 22 Electric Characteristics T V ver Measuring Condition lou 5mA Standard Min Typ Max HIGH Output
8. tw INH INTi Input HIGH Pulse Width twiINL INTi Input LOW Pulse Width Rev 2 00 Nov 28 2005 page 336 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver XIN input TAIIN input TAiOUT input re TAiOUT input Up down input X During event counter mode TAIIN input When count on falling edge thctin uPy fsu UP riN is selected TAIIN input When count on rising edge is selected Two phase pulse input in event counter mode tea TAIIN input tsu TAIN TAOUT tsu TAIN TAOUT tsu TAOUT TAIN TAiOUT input tsu TAOUT TAIN tc TB i tw TBH TBiIN input ADTRG input TXDi RXDi tw INL INTI input Figure 22 23 Timing Diagram Rev 2 00 Nov 28 2005 page 337 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 Usage Precaution 23 1 SFR There is the SFR which can not be read containg bits that will result in unknown data when read Please set these registers to their previous values with the instructions other than the read modify write instructions Table 23 1 lists the registe
9. a i 362 2314 1 Heading CIST Ri Register seite eset eoin sre ueste a or E o eo AREEN 362 23 14 2 Performing CAN Configuration sirsie asas de reve etre tese ee a ayer Pana dcus 364 23 14 3 Suggestions to Reduce Power Consumption sssssssseseeseneeeeeeenn enne 365 23 14 4 CAN Transceiver in Boot Mode ssesssssssesessseseeeeee nennen nnne nenne nnn nnn rnn nennt stern nenne 366 23 15 Programmable I O Ports iontas aaeain aai R enter rennes eater nennen nent nnne nnn 367 23 16 Dedicated afe To aud o ERR 368 23 17 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers 369 23 18 Mask ROM Version sssssssssessseseseseeeenene iaaa aaia Eaa aa naaa estt rsen nnns en 370 23 19 Flash Memory VefsiOn escorts eene cy cabins d eade ada e Ret c oder a BE ance 371 23 19 1 Functions to Prevent Flash Memory from Rewriting seeseeeeeennm 371 239 192 ciae doro MT 371 23 19 3 Walt MOOG sinia Gea e hte Do I oca restes ns ctetu Lieb dtt dde der rena 371 23 19 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode 371 23 19 5 Writing Command and Data sssssssssssessseseeeeeeee nennen nennen nnne nnns nnns ennt nnne nns 371 23 19 6 Program Comtimag sudo coetu ette perte tud efe ete uae Tr esl o a auct 371 23 19 7 Kock Bit Program Command sssrin ides wld Ra
10. YES Block is locked Block is not locked 1 Write the command code and data to even addresses Figure 21 11 Read Lock Bit Status Command Rev 2 00 Nov28 2005 page 277 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit The lock bit is enabled by setting the FMRO2 bit in the FMRO register to 0 lock bit enabled The lock bit allows each block to be individually protected locked against program and erase This helps prevent data from being inadvertently written to or erased from the flash memory e When the lock bit status is set to 0 the block is locked block is protected against program and erase When the lock bit status is set to 1 the block is not locked block can be programmed or erased The lock bit status is set to 0 locked by executing the lock bit program command and to 1 unlocked by erasing the block The lock bit status cannot be set to 1 by any commands The lock bit status can be read by the read lock bit status command The lock bit function is disabled by setting the FMRO2 bit to 1 All blocks are unlocked However individual lock bit status remains unchanged The lock bit function is enabled by setting the FMRO2 bit to 0 Lock bit statu
11. 1 During memory expansion and microprocessor modes the pins are not pulled high although their corresponding register contents can be modified Not available memory expansion and microprocessor modes in T V ver 2 The pin for which this bit is 1 pulled high and the direction bit is O input mode is pulled high Pull up Control Register 1 b7 De pe P4 h3 b P1 He Symbol Address After Reset 1 PUR1 O3FDh 00000000b 00000010b Bit Symbol Bit Name PU10 P4 0to P4 3 Pull Up 2 0 Not pulled high PU11 P4_4 to PA 7 Pull Up 3 1 Pulled high 5 PU12 P5_0 to P5 3 Pull Up 2 P5 4to P5 7 Pull Up 2 P6 0 to P6 3 Pull Up P6 4to P6 7 Pull Up P7 0 P7 2 and P7 3 Pull Up 4 PU17 P7 4to P7 7 Pull Up 1 The values after hardware reset is as follows 00000000b when input on CNVSS pin is L 00000010b when input on CNVSS pin is H CNVSS pin H is not available in T V ver The values after software reset watchdog timer reset and oscillation stop detection reset are as follows 00000000b when the PM 01 to PMOO bits in the PMO register are 00b single chip mode 00000010b when the PM 01 to PMOO bits are 01b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver 2 During memory expansion and microprocessor modes the pins are not pulled high although their corresponding register contents can be modified Not available
12. 1 Clock synchronous type when external clock is selected CKDIR CKPOL Clock synchronous type CLK when internal clock is selected Clock synchronous i control circuit CLK2 O desig circuit CTS RTS disabled CTS RTS selected CT82 ATs O ned CTS RTS disabled n2 Values set to the U2BRG register PCLK1 Bit in PCLKR register SMD2 to SMDO CKDIR Bits in U2MR register CLK1 to CLKO CKPOL CRD CRS Bits in U2CO register Figure 15 3 UART2 Block Diagram Rev 2 00 Nov28 2005 page 151 of 378 REJ09B0124 0200 131 NESAS Transmit receive unit 15 Serial Interface TXD polarity reversing circuit 1 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM IOPOL No reverse 0 Jo Reverse RXD data reverse circuit PAR enabled PRYE PAR disabled 0 Clock synchronous type Clock synchronous type UART 7 bits UART 8 bits 15 Serial Interface UART 7 bits RTi receive register UART SMD2 to SMDO UART 9 bits Clock synchronous type Logic reverse circuit MSB LSB conversion circuit Data bus high order bits Data bus low order bits PRYE PAR enabled 1 PAR disabled SP Stop bit PAR Parity bit Logic rever
13. AN2_7 O PMO1 to PM00 00b 3 ADGSEL1 to ADGSELO 11b OPA1 to OPAO 11b 0 PMO1 to PM00 00b ADGSEL1 to ADGSELO 10b OPA1 to OPAO 11b ADGSEL1 to ADGSELO 00b OPA1 to OPAO 11b Pay OPA1 to OPAO ANEX0 o ANEX1 OPAO 1 ae OPA1 1 oS OPA1 1 01b o os NOTE Comparator 1 Port PO group ANO 0 to ANO 7 can be used as analog input pins even when PMO1 to PMOO bits are set to 01b memory expansion mode and PMO5 to PM04 bits are set to 11b multiplex bus allocated to the entire CS space Not available memory expansion mode in T V ver Figure 16 1 A D Converter Block Diagram Rev 2 00 Nov 28 2005 page 203 of 378 REJ09B0124 0200 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ADCONO 03D6h 00000XXXb RW Function varies Analog Input Pin Select Bit with each operation mode One shot mode A D Operation Mode Repeat mode Select Bit 0 Single sweep mode Repeat sweep mode 0 or Repeat sweep mode 1 0 Software trigger A D conversion disabled ADST A D Conversion Start Flag i A D conversion started Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten
14. SCLi spai X D7 X De X Ds X D4 X D3 X D2 X D1 X DO X D8 ACK NACK i ACK interrupt DMA1 request NACK interrupt 4 Transfer to UiRB register b15 b9 b8 b7 D8 D7 D6 D5 D4 D3 UiRB register 3 IICM2 1 UART transmit receive interrupt CKPH 0 tst bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi sDai X D7 X D6 X D5 X D4 X D8 X D2 X D1 X DO X DB ACK NACK tf Receive interrupt Transmit interrupt DMA1 request Transfer to UiRB register b15 b9 b8 b7 4 IICM2 1 CKPH 1 UiRB register 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi sDai X D7 X De X Ds X D4 X D3 X D2 X D1 X DO X DB ACK NACK A Receive interrupt Transmit interrupt DMA1 request A Transfer to UIRB register Transfer to UiRB register b15 b9 b8 b7 bo b15 b9 b8 b7 DO D7 D6 D5 D4 D3 DI Uu D8 D7 D6 D5 D4 D3 D2 i20to2 UiRB register UiRB register This diagram applies to the case where the following condition is met The CKDIR bit in the UIMR register 0 slave selected Figure 15 24 Transfer to UiRB Register and Interrupt Timing Rev 2 0
15. Initial Value of TXDi and SDAi Outputs CKPOL 0 H CKPOL 1 L The value set in the port register before setting 1 C mode Initial and End Value of SCLi H L H L DMA1 Factor 9 UARTI reception UARTi reception Falling edge of SCLi 9th bit Acknowledgment detection ACK Store Received Data 1st to 8th bits of the received data are stored into bit 7 to bit O in the UiRB register 1stto 7th bits of the received data are stored into bit 6 to bit 0 in the UIRB 1st to 8th bits are register 8th bit is stored into stored into bit 7 to bit bit 8 in the UiRB register 0 in UiRB register Read Received Data i Oto2 NOTES The UiRB register status is read Bit 6 to bit 0 in the UiRB register are read as bit 7 to bit 1 Bit 8 in the VIRB register is read as bit 0 1 If the source or cause of any interrupt is changed the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 interrupt requested Refer to 23 8 Interrupts If one of the bits shown below is changed the interrupt source the interrupt timing etc change Therefore always be sure to set the IR bit to 0 interrupt not requested after changing those bits e SMD2 to SMDO bits in UIMR register e IICM2 bit in UiSMR2 register NOOB WP ICM bit in UISMR register e CKPH bit in UiSMR3 register Set the initial value of SDAi output while the
16. UART1 Special Mode Register 4 U1SMR4 00h UART1 Special Mode Register 3 U1SMR3 000X0X0Xb UART1 Special Mode Register 2 U1SMR2 X0000000b UART1 Special Mode Register U1SMR X0000000b UART2 Special Mode Register 4 U2SMR4 00h UART2 Special Mode Register 3 U2SMR3 000X0X0Xb UART2 Special Mode Register 2 U2SMR2 X0000000b UART2 Special Mode Register U2SMR X0000000b UART2 Transmit Receive Mode Register U2MR 00h UART2 Bit Rate Generator U2BRG XXh UART2 Transmit Buffer Register U2TB an UART2 Transmit Receive Control Register 0 U2CO 00001000b UART2 Transmit Receive Control Register 1 U2C1 00000010b UART2 Receive Buffer Register U2RB xn X Undefined NOTES 1 These registers exist only in the 128 pin version 2 The SSTRF and S6TRF bits in the S3456TRR register are used in the 128 pin version 3 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov 28 2005 page 26 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 9 SFR Information 9 Symbol CANO Messag
17. sss 140 TAS 116 COIDR CHDR osioissa 231 INVC1 S 141 TAS Ciera nna 87 COLMAR C1LMAR e 227 COLBIBE CMBR pra K TA3MR 116 119 121 123 126 128 COMETA W C MCTLIS ces P TAA ett eee eee 116 143 KU PIC ctc enc 86 TA44 143 CORECIC osoin 86 vadit ud M QC LE Be CORECR C1 RECR m 233 Oo COSTA cde TH 23 CONSP a TAAMR 116 119 121 123 126 128 146 COSTA gista Se eg ee ee ae ee eee a E COR E T TT TABSR a 117 132 145 COTECR CITECR oeeeececececee pud P beds D DCN jp COTRMIC sees 86 PO TO P13 sss 255 TE pe MC DE p M ne COTSR C1TSR seeee A M 0 Y 255 d I LIS 931 133 19 n C1MCTLO to C1MCTL15 228 PCLKR eere 61 ae RM RE 2 CARECIC oiiire 87 O e E E 257 Em LH ae f ae CATRMIC ooien 87 PDO to PD13 see 254 Vir NEN i pi ps CANO 1 Slot 0 to 15 PLCO ocececccsecececsesesesececsesesesecscseseseces 63 aic EI LI M Time Stamp 225 226 PMO naa Ete erede RE FUERIS 7 O dL ee ye ae aare 208226 pH gq TB2MR sss 131 133 134 136 146 Message Box 225 226 unmX EN 62 M id gcc p M LM i COIKRB ume ect ad 62 iO a DO 80 San XM IQ EE de COMO eene N 58 PUPO to PUR2 e eL MES E E MUN eM ae PURS sg TBIMR sormama 131 133 134 136 PC RE RE E oj MN QAM s CPSRF LLL 118 132 R TBAIQ is testet 86 CAROD iania el 221 RMADO to RMADS q00 JPBSMBonessdisss Tory Pos NS Due CRCIN PERO 221 ROMCP NNMERO ERE 26
18. 2 Set the FMRO2 bit to 1 3 Execute the block erase command to erase the block where the error occurred 4 Execute the lock bit program command again NOTE If similar error occurs that block cannot be used Full status check completed FMR06 FMRO7 Bits in FMRO register NOTE 1 When either FMRO6 or FMRO07 bit is set to 1 terminated by error the program block erase erase all unlocked block lock bit program and read lock bit status commands cannot be accepted Execute the clear status register command before each command Figure 21 12 Full Status Check and Handling Procedure for Each Error Rev 2 00 Nov28 2005 page 281 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 4 Standard Serial I O Mode In standard serial I O mode the serial programmer supporting the M16C 6N Group M16C 6NK M16C 6NM can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board For more information about the serial programmer contact your serial programmer manufacturer Refer to the user s manual included with your serial programmer for instructions Table 21 7 lists pin functions for standard serial I O mode Figures 21 13 and 21 14 show pin connections for standard serial I O mode 21 4 1 ID Code Check Function The ID code check function determines whether the
19. 4ns min D Ki 1 ry ta BCLK RD I 30ns max i tsu DB RD Ons min 50ns min ta BCLK CS i th BCLK CS gt 30ns max gt Ans min 1 1 i i dagoucap Ch BCLICAD lt gt 30ns max 4 4ns min td BCLK ALE th BCLK ALE th wR AD i 4 Pi 30ns max NE 4ns min 1 n J i 1 0 5 X tcyc 10 ns min i i td BCLK WR thBCLK WR a i 4 1 30ns max Ea Ons min 1 1 Ih BCLK DB ta DB WR th WR DB 0 5 X tcyc 40 ns min 0 5 X tcyc 10 ns min tcyc 1 BCLK Measuring conditions e VCC 3 3 V e Input timing voltage VL 0 6V ViH 2 7V e Output timing voltage VoL 1 65 V Vou 1 65 V Figure 22 16 Timing Diagram 4 Rev 2 00 Nov28 2005 page 323 of 378 RENESAS REJ09B0124 0200 This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Under development 22 Electric Characteristics Normal ver 3 3V VCC wait setting and external area access o xe o i o o o o o o A Q o i 5 xe c o xe o c S o c Q gt x lt LI gt E o E For 2 Read timing 30ns max td BCLK ALE tSU DB RD P4 th RD DB Ons min 50ns min Write timing ta DB WR th wR DB 1 5 X tcyc 40 ns min 0 5 X tcyc 10 ns min Measuring conditions ViL 0 6 V ViH 2 7 V e Output timing voltage VoL 1 65 V
20. A0 DO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO NOTE 1 Not available the bus control pins in T V ver Rev 2 00 Nov 28 2005 page 8 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM P1 0 D8 PO 7 ANO 7 D7 lt gt PO 6 ANO 6 D6 lt PO 5 ANO 5 D5 lt gt PO 4 ANO 4 DA lt gt PO 3 ANO 3 D3 lt PO 2 ANO 2 D2 t PO 1 ANO 1 D1 lt gt PO O ANO 0 DO P11_7 SIN6 P11 6 SOUT6 P11 5 CLK6 P11 4 P11 3 P11_2 SOUT5 lt a P11_1 SIN5 a P11 O CLK5 lt a p1 1 D9 INT4 INTS INT3 gt P2 0 AN2 0 A0 cV P4 5 D13 C P1 6 D14 T pi 7 D15 DO gt p2 1 AN2 1 A1 D1 DO P2 2 AN2 2 A2 D2 D1 te P2 S AN2 3 A3 D3 D2 D4 D3 D5 D4 D6 D5 D7 D6 P2 4 AN2 4 A4I P2 5 AN2 5 A5 gt P2 6 AN2 6 A6 4 P2 7 AN2 7 A7 D7 It p122 lt P3 1 A9 4 vss 4 VCC2 lt p3 2 A10 4 P3 0 A8 gt p3 3 A11 CV p3 4 M2 C p3 5 A13 C p3 6 A14 p3 7 A15 lt P4 0 A16 lt P4 1 A17 P4 2 A18 p4 4 050 lt gt P4 5 CS1 p4 6 CS2 lt P4 7 CS3 2 a P1 2 D10 S
21. BCLK Write signal Read signal Data bus Output CS NOTE 1 These example timing charts indicate bus cycle length After this bus cycle sometimes come read and write cycles in succession Figure 7 7 Typical Bus Timings Using Software Wait 1 Rev 2 00 Nov28 2005 page 54 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 1 Separate bus 3 wait setting Bus cycle Bus cycle 1 BCLK Write signal Read signal 2 Multiplexed bus 1 or 2 wait setting Bus cycle Bus cycle BCLK Write signal Read signal ALE Address bus Ades O Aoo Adress Address bus 5 3 Multiplexed bus 3 wait setting Bus cycle Bus cycle BCLK Write signal Read signal ALE e rn o A fa CS NOTE 1 These example timing charts indicate bus cycle length After this bus cycle sometimes come read and write cycles in succession Figure 7 8 Typical Bus Timings Using Software Wait 2 Rev 2 00 Nov28 2005 page 55 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal Main clock oscillation circuit e Sub
22. Bits in PMO register Bits in CMO register Bits in CM1 register Bits in PCLKR register Bits in CM2 register Bits in CCLKR register Oscillation stop re oscillation detection circuit Pulse generating circuit for clock edge detection and charge discharge control Main clock circuit Programmable counter Charge discharge Phase comparator Main clock Figure 8 1 Clock Generating Circuit Rev 2 00 Nov 28 2005 page 57 of 378 REJ09B0124 0200 1 8 146 CMO06 0 CM17 CM16 11b Reset generating circuit Oscillation stop re oscillation detection interrupt generating circuit Oscillation stop detection reset Oscillation stop re oscillation detection interrupt signal CMe1 switch signal Voltage control oscillator VCO Internal lowpass filter 31 NE SAS PLL clock Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset CMO 0006h 01001000b Bit Name Function b1 bO Clock Output Function 0 0 I O port P5 7 Select Bit 0 1 fC output Valid only in single chip 4 o f8 output 1 1 f32 output 0 Do not stop peripheral function WAIT Mode Peripheral clock in wait mode Function Clock Stop Bit Stop kahan function clock in wait mode
23. CANO Message Box 1 Identifier DLC DMA1 Transfer Counter 003Ch DMA1 Control Register 003Dh 003Eh CANO Message Box 1 Data Field 003Fh The blank areas are reserved 007Fh CANO Message Box 1 Time Stamp B 1 Symbol CANO Message Box 2 Identifier DLC CANO Message Box 2 Data Field 008Fh CANO Message Box 2 Time Stamp 0090h e eo c A 5 e e c m 2 CANO Message Box 3 Identifier DLC CANO Message Box 3 Data Field CANO Message Box 3 Time Stamp CANO Message Box 4 Identifier DLC o o olo O oilojo P S S gt QU o 5 3 3 7 CANO Message Box 4 Data Field o oo gt gt mc 3 Ty CANO Message Box 4 Time Stamp Q e UJ A e UJ N o 45 CANO Message Box 5 Identifier DLC ojojoj Ojojoo w CJ w Go N OcRB SFTS FS oj o ojo lo Ojojoo o zg 35 3 53 5 o o UJ g E CANO Message Box 5 Data Field OOBEh OOBFh CANO Message Box 5 Time Stamp 225 226 B 2 Symbol CANO Message Box 6 Identifier DLC CANO Message Box 6 Data Field O0CEh CANO Message Box 6 Time Stamp o o e o E e e s E e o g N 2 CANO Message Box 7 Identifier DLC CANO Message Box 7 Data Field CANO Message Box 7 Time Stamp CANO Message Box 8 eo A Identifier DLC eojoliojo ojojo m
24. P14 0 P14 1 VOTywe Deswpia 8 bit I O ports in CMOS having a direction register to select an input or output Each pin is set as an input port or output port An input port can be set for a pull up or for no pull up in 4 bit unit by program however P7 1 and P9 1 for the N channel open drain output I Input O Output NOTE P8 5 Input pin for the NMI interrupt Pin states can be read by the P8 5 bit in the P8 register I O Input Output 1 Ports P11 to P14 are only in the 128 pin version Rev 2 00 Nov 28 2005 page 15 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 2 Central Processing Unit CPU 2 Central Processing Unit CPU Figure 2 1 shows the CPU registers The CPU has 13 registers Of these RO R1 R2 R3 AO A1 and FB comprise a register bank There are two register banks Data Registers Address Registers Frame Base Registers Program Counter User Stack Pointer Interrupt Stack Pointer Static Base Register Flag Register Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTE 1 These registers comprise a register bank There are two register b
25. Rewriting the PMO1 to PMOO bits places the microcomputer in the corresponding processor mode regardless of whether the input level on the CNVSS pin is H or L Note however that the PMO1 to PMOO bits cannot be rewritten to 01b memory expansion mode or 11b microprocessor mode at the same time the PMO7 to PMO2 bits are rewritten Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM NOTE 1 Not available memory expansion and mocroprocessor modes in T V ver If the microcomputer is reset in hardware by applying VCC to the CNVSS pin hardware reset the internal ROM cannot be accessed regardless of PMO1 to PMOO bits Figures 6 1 and 6 2 show the processor mode related registers Figure 6 3 shows the memory map in single chip mode Figures 6 4 to 6 7 show the memory map and CS area in memory expansion mode and microprocessor mode Normal ver only Rev 2 00 Nov28 2005 page 39 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode Processor Mode Register 0 pr DO Do Df 208 De Di BO Symbol Address After reset 2 PMO 0004h 00000000b CNVSS pin L 0000001 1b CNVSS pin H 9 Bit symbol b1 b0 0 0 Single chip mode Processor Mode Bit 2 0
26. essen 262 21 2 1 ROM Gode Protect FUNCOM desc onore atenta eu deca Eee anina ee headed sued ee rca ccs SERKA 262 21 22 ID Gode Check FunclioDi as iecur Eo eine ia asas tux detta edis oun Aidan ae th ea a ud 262 21 3 CPU Re wrlte MOde iie DendM NEED II NIE 264 2 3 EWO MOAS tette eomm Le eee 265 21 3 2 EWT MOJ S Oed IM III LIII IMS 265 21 3 9 FMRO FMHRH T R6eglSIetS teri dette eiaa ERN PAER dasdanddsasdatdedesnsdadadwesesessdabenasdesdsgaecasteueas 266 21 3 4 Precautions on CPU Rewrite Mode esses eeneeenenmnnnnn nnne n ener nnnnn nass sisse 271 21 3 5 Software Commands cccccccccccccccsssesssssceeeeeeeececeeesesesseesaseeeeeeeceeeseseseseeesaeeeeeeceesesseceseseeeeaeeeeeeeeeess 273 21 3 6 Data Protect Function 00 0 cccccccccccececcseseeeeeeeeeseeesesseeececeeeeeeeeeeeeeeeeeesessseseseaeeeasseseseeseseeeeeeeeeeseeeees 278 21 3 7 Status Register SRD IRegiStet rentis drerit ea v rena poa stt aAa aN urat 278 21 3 8 Full Status Checked eere Eo tete e terae bete eins fe Es espe usages c ees etd 280 21 4 Standard Serial l OMOGG iibi ied Mete speech e Sacuetvlsd snciee tubs ed eitis dg Soeur idee sustine avv acea esaet 282 21 41 D Code Check FUNCION snsc oett tee esc eoo ter ie Fee staked ees ete cadence 282 21 4 2 Example of Circuit Application in Standard Serial I O Mode ssssseseeee 286 21 5 Parallel VO Mode notre ere a te e idee Eder reir iesus ims esae dvo Rasa S ica scdes Sie agua
27. pi 3 011 S ER e a py 4 D12 g r3 e N g Fo Fo Fo Fo Es J Ca PN R a pio 0 S e p12 1 9 P12 3 S a p12 4 F3 Lo E3 La j Dis g P4 3 A19 zT El E eo a 3 a o 9 o P10_7 AN7 KI3 lt P10 6 ANG KI2 P10_5 AN5 KIT lt P10_4 AN4 KI0 lt P10_3 AN3 c P10_2 AN2 lt P10_1 AN1 lt gt AVSS P10_0 ANO NOTES 2 O M16C 6N Group M16C 6NM O 1 Overview 64 t P12 5 lt P12 6 62 t P12 7 lt a P5 0 WRL WR a P5 1 WRH BHE 59 a P5 2 RD gt P5 3 BCLK gt P13 0 56 lt a P13 1 55 lt a P13 2 lt P13 3 lt P5 4A HLDA a P5 5 HOLD gt P5 6 ALE a P5 7 RDY CLKOUT 49 a P13 4 45 P13 5 INTG a P13 6 INT7 a P13 7 INT8 45 P6 O CTSO RTSO a P6 1 CLKO a P6 2 RXDO SCLO 42 lt P6 3 TXDO SDAO
28. 0260h n 16 4 EID5 to EIDO Data Length Code DLC 0060h n 1645 0260h n 16 5 Data Length Code DLC EID5 to EIDO 0060h n 16 6 0260h n 1646 Data byte 0 Data byte 1 0060h n 16 7 e e 0060h n 16 13 0260h n 16 7 Data byte 1 e e e e 0260h 4 n 16 13 Data byte 7 Data byte 0 e e Data byte 6 0060h n 16 14 0260h n 16 14 Time stamp high order byte Time stamp low order byte 0060h n 16 15 i20 1 0260h n 16 15 Time stamp low order byte n 0 to 15 the number of the slot Rev 2 00 Nov28 2005 page 225 of 378 REJO9BO0124 0200 131 NESAS Time stamp high order byte Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module Figures 19 2 and 19 3 show the bit mapping in each slot in byte access and word access The content of each slot remains unchanged unless transmission or reception of a new message is performed eT seq se s se s m sos se p sos se s 9 DEDE pss sj ET eq epe pepe I9 i sj Data Byte 0 Data Byte 1 Data Byte 7 Time Stamp high order byte Time Stamp low order byte CAN Data Frame SID10to6 SID5toO EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to0 Data Byte 0 Data Byte 1 EE Data Byte 7 NOTE 1 When Da is read the value is the one written upon the transmission slot configuration The
29. 4 The UFORM bit is enabled when the SMD2 to SMDO bits in the UIMR register are set to 001b clock synchronous serial I O mode or 101b UART mode 8 bit transfer data Set this bit to 1 when the SMD2 to SMDO bits are set to 010b IC mode and to 0 when the SMD2 to SMDO bits are set to 100b UART mode 7 bit transfer data or 110b UART mode 9 bit transfer data 5 When changing the CLK1 to CLKO bits set the UiBRG register Figure 15 6 UOMR to U2MR Registers and UOCO to U2CO Registers Rev 2 00 Nov28 2005 page 154 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface UART Transmit Receive Control Register 1 j 0 1 b7 b6 b5 b4 b3 b2 bi bO Symbol UOC1 U1C1 Address 03A5h O3ADh After Reset 00XX0010b sh Snan Fonon oW 0 Transmission disabled Te Transmit Enable Bit 1 Transmission enabled E Transmit Buffer Empty Flag Data present in the UjTB register No data present in the UjTB register Receive Enable Bit Reception disabled Reception enabled Receive Complete Flag No data present in the UjRB register Data present in the UjRB register Nothing is assigned When write set to O When read their contents are indeterminate Data Logic Select Bit 1 No reverse Reverse Error Signal Output Enable Bit
30. M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit y Main Clock Oscillation On chip Oscillator Clock Oscillation On chip Oscillator On chip Oscillator T Medi 3 Medium Speed Mode Medium Speed Mode Medium Speed Mode Medium Speed Mode Mode Low Power Dissipation Mode FLE operation mode High Speed Mode divide by 2 divide by 4 divide by 8 divide by 16 CPU clock PLCO7 1 CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock PLL OM11 16 XIN f XIN 2 XINJA XIN S XIN 16 f Ring Ring CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 f Ringy 2 f Ring 2 CM06 0 CM06 0 CM06 0 CMO6 0 CMO06 1 CM06 0 Ring 4 Ring 4 CMi7 0 PLCO7 0 CM17 0 CM17 0 CM17 1 CM17 1 f Ringy 8 CM05 10 Ring 8 CM16 0 CM11 0 C CM16 0 CM16 1 CM16 0 CM16 1 Ring 16 Ring 16 CM04 1 Medium Speed Mode Medium Speed Mode Medium Speed Mode Medium Speed Mode divide by 2 divide by 4 divide by 8 divide by 16 CPU clock PLCO7 1 CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock 2 PLL gui 210 XIN f XIN 2 XIN A XINy 8 XIN 16 f Ring f Ring CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 f Ring 2 f Ring 2 CM06 0 _____4 CM06 0 CM06 0 CM06 0 CMO06 1 CM06 0 f Ring 4 f Ring 4 CMi7 0 PLCO7 0 CM17 0 CM17 0 CM17 1 CM17 1 f Ring 8 f Ring 8 CM16 0 CM11 0 CM16 0 CM16 1 CM16 0 CM16 1 R
31. Table 7 7 External Bus Status When Internal Area Accessed SFR Accessed Internal ROM Internal RAM Accessed AO to A19 Address output Maintain status before accessed address of external area or SFR DO to D15 When read High impedance High impedance When write Output data Undefined RD WR WRL WRH RD WR WRL WRH output Output H BHE BHE output Maintain status before accessed status of external area or SFR CS0 to CS3 Output H Output H ALE Output L 7 2 10 Software Wait Output L Software wait states can be inserted by using the PM17 bit in the PM1 register the CSOW to CS3W bits in the CSR register and the CSE register The SFR area is unaffected by these control bits This area is always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register See Table 7 8 Bit and Bus Cycle Related to Software Wait for details To use the RDY signal set the corresponding CS3W to CSOW bit to 0 with wait state Figure 7 6 shows the CSE register Table 7 8 shows the software wait related bits and bus cycles Figures 7 7 and 7 8 show the typical bus timings using software wait Chip Select Expansion Control Register b7 b6 b5 b4 b3 b2 bi bO Symbol CSE After Reset Bit Symbol Rw CSEOOW CSO Wait Expansion Bit 1 2 waits CSEO1W CSE10W 1 wa
32. Transmit register empty flag CRD Set to 1 NCH Set to 1 CKPOL Set to 0 UFORM Set to 1 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS 2 Invalid U2RRM 2 UiLCH UiERE Set to 0 IICM Set to 1 ABC Select the timing at which arbitration lost is detected Invalid BBS Bus busy flag 3 to 7 Set to 0 IICM2 See Table 15 12 IC Mode Functions CSC Set this bit to 1 to enable clock synchronization Set to 0 SWC Set this bit to 1 to have SCLi output fixed to L at the falling edge of the 9th bit of clock ALS Set this bit to 1 to have SDAi output stopped when arbitration lost is detected Set to 0 STAC Set to 0 Set this bit to 1 to initialize UARTi at start condition detection SWC2 Set this bit to 1 to have SCLi output forcibly pulled low SDHI Set this bit to 1 to disable SDAi output 7 Set to 0 0 2 4 and NODC Set to 0 CKPH See Table 15 12 IC Mode Functions DL2 to DLO Set the amount of SDAi digital delay STAREQ Set this bit to 1 to generate start condition Set to 0 RSTAREQ Set this bit to 1 to generate restart condition Set to
33. Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 6 2 Example of Circuit Application in CAN I O Mode Figure 21 19 shows example of circuit application in CAN I O mode Refer to the user s manual of your CAN programmer to handle pins controlled by a CAN programmer P6 7 TXD1 P6 5 CLK1 CAN transceiver P9 5 CRXO P9 6 CTXO NOTES 1 Control pins and external circuitry will vary according to programmer For more information refer to the programmer manual 2 In this example modes are switched between single chip mode and CAN I O mode by controlling the CNVSS input with a switch Figure 21 19 Circuit Application in CAN I O Mode Rev 2 00 Nov 28 2005 page 291 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver 22 Electrical Characteristics 22 1 Electrical Characteristics Normal ver Table 22 1 Absolute Maximum Ratings Supply Voltage VCC1 VCC2 0 3 to 6 5 Analog Supply Voltage 0 3 to 6 5 Input RESET CNVSS BYTE 0 3 to VCC 0 3 Voltage PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 P3_0 to P3 7 PA Oto P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2to P7 7 P8 OtoP8 7 P9 0 P9 2to P9 7 P10_0 to P10 7 P11 Oto P11 7 P12 Oto P12 7 P13 OtoP13 7 P14 0 P1
34. b7 b6 b5 b4 b3 b2 bi bod Port P8 Direction Register b7 b6 b5 b4 b3 b2 bi bO After Reset 00X00000b Bit Symbol PD8_0 Port P8 0 Direction Bit 0 Input mode PD8 1 Port P8 1 Direction Bit Functions as an input port PD8 2 PortP8 2 Direction Bit Output mode Functions as an output port PD8 3 Port P8 3 Direction Bit PD8 4 Port P8 4 Direction Bit Nothing is assigned When write set to 0 When read its content is indeterminate PD8 6 Port P8 6 Direction Bit 9 Input mode Functions as an input port 1 Output mode PD8 7 Port P8 7 Direction Bit Functions as an output port Figure20 7 PDO to PD13 Registers Rev 2 00 Nov28 2005 page 254 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Port Pi Register i O to 7 9 to 13 0 0 9 Symbol Address After Reset PO to P3 OSEOh OSE1h O3E4h O3E5h Indeterminate P4 to P7 O3E8h O3E9h O3ECh O3EDh Indeterminate P9 to P12 4 03F 1h 03F4h O3F5h 03F8h Indeterminate P13 4 O3F9h Indeterminate Bit Symbol Port Pi 0 Bit The pin level on any I O port which is set RW Port Pi 1 Bit for input mode can be read by reading RW the corresponding bit in this register Port Pi 2 Bit The pin level on any I O port which is RW Port Pi 3 Bit set for output mode can be controlled Rw by writing to the
35. operation yi voltage VCC OV 0 2VCC or below pete gt lt Supply a clock with td P R 20 To or more cycles to the XIN pin NOTE 1 Use the shortest possible wiring to connect external circuit Figure 5 1 Example Reset Circuit Rev 2 00 Nov28 2005 page 35 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 5 Reset er More than 20 cycles are needed Microprocessor mode BYTE H Address BCLK 28cycles LyJ Content of reset vector _FFFFCh FFFFDh Y FFFFEh Y Microprocessor mode BYTE L Content of reset vector Address FFFFCh FFFFEh i RD WR cso Single chip Address FFFFCh 1 C y Content of reset vector 1 FFFFEh NOTE 1 Not available in T V ver Figure 5 2 Reset Sequence Table 5 1 Pin Status When RESET Pin Level is L Status Pin Name CNVSS VSS PO Input port CNVSS VCC BYTE VSS Data input BYTE VCC Data input P1 Input port Data input Input port P2 P3 P4_0 to PA 3 Input port Address output undefined Address o
36. 0 j 5wheni 3 Timer B3 01D1h 01D0h Timer B5 Timer B4 01D3h 01D2h Timer B3 NOTE TimerB5 01D5h 01D4h Timer B4 1 Overflow or underflow Figure 13 15 Timer B Block Diagram Rev 2 00 Nov 28 2005 page 130 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Timer Bi Mode Register i O to 5 br be b5 b4 bS b2 bi bo Symbol Address After Reset TBOMR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TBBMR O1DBhto01DDh 00XX0000b EEE RW i b1 b0 TMODO 0 0 Timer mode _ 01 Event counter mode Operation Mode Select Bit 1 0 Pulse period measurement mode TMOD1 pulse width measurement mode 11 Do not set a value MRO MR1 Function varies with each operation mode TCKO Count Source Select Bit Function varies with each operation TCK1 mode 1 Timer BO timer B3 2 Timer B1 timer B2 timer B4 timer B5 Timer Bi Register i O to 5 Symbol Address After Reset TBO 0391h 0390h Indeterminate b15 b8 TB1 0393h 0392h Indeterminate br bob bo TB2 0395h 0394h Indeterminate TB3 01D1h 01DOh Indeterminate TB4 01D3h 01D2h Indeterminate TB5 01D5h 01D4h Indeterminate Function o Setting Range RW Eos timer Node ae the count source by n 1 0000h to FFFFh where n set value Event Counter Divide the count source by n 1 0000h to FFFFh where n set value 2 0000h to FFF Pulse
37. 1 Saved simultaneously all 16 bits Finished saving registers Finished saving registers in two operations in four operations PCL 8 low order bit of PC PCM 8 middle order bits of PC PCH 4 high order bits of PC FLGL 8 low order bits of FLG FLGH 4 high order bits of FLG NOTE 1 SP denotes the initial value of the SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4 Figure 10 8 Operation of Saving Registers Rev 2 00 Nov28 2005 page 91 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 5 8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine Thereafter the CPU returns to the program which was being executed before accepting the interrupt request Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction 10 5 9 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points a timing to detect whether an interrupt reque
38. 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set the SMD2 to SMDO bits in the UiMR register to 000b serial interface disabled 3 Set the SMD2 to SMDO bits in the UiMR register to 001b clock synchronous serial I O mode 4 Set the RE bit in the UiC1 register to 1 reception enabled Resetting the UiTB register i O to 2 1 Set the SMD2 to SMDO bits in the UiMR register to 000b serial interface disabled 2 Set the SMD2 to SMDO bits in the UiMR register to 001b clock synchronous serial I O mode 3 1 transmission enabled is written to the TE bit in the UiC1 register regardless of the TE bit 15 1 1 2 CLK Polarity Select Function Use the CKPOL bit in the UiCO register i O to 2 to select the transfer clock polarity Figure 15 12 shows the polarity of the transfer clock 1 When the CKPOL bit in the UiCO register O transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock CLKi NOTE 1 TXDi Xo X p1 A DeJ pa X De X ns A pe A pr RXDi Y po Y pi X D2 X D3 X D4 X bs X pe X D7 2 When the CKPOL bit in the UiCO register 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock CLKi NOTE 2 TXDi Yes X ONENESS s Y e Y 87 RXDi Y po X D1 X D2 X ps X D4 X
39. 1 fj or 16 n 1 fEXT as follows fj frequency of UIBRG count source f1SIO f2SIO f8SIO f32SIO PRYE bit in UiMR register 0 parity disabled fEXT frequency of UiBRG count source external clock STPS bit in UIMR register 1 2 stop bits n value set to UIBRG CRD bit in UiCO register 1 CTS RTS disabled i Oto2 UiIRS bit 0 an interrupt request occurs when transmit buffer becomes empty UOIRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register Figure 15 17 Transmit Operation Rev 2 00 Nov 28 2005 page 170 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Example of Receive Timing when Transfer Data is 8 bit Long parity disabled one stop bit UiBRG count Source RE bit in UiC1 register RXDi Receive data taken in Transfer clock RI bit in UiC1 register RTSi IR bit in SiRIC register i Oto2 Transferred from UARTi receive nye i is generated by falling edge of start bit register to UiRB register a g UU H G S d q f Jt o Set to 0 by an interrupt request acknowledgement or by program Reception triggered when transfer clock The above timing diagram applies to the case where the register bits are set as follows PRYE bit in UIMR register 0 parity disabled STP
40. 1 0 Rev 2 00 Nov 28 2005 page 375 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Appendix 1 Package Dimensions Memo Rev 2 00 Nov28 2005 page 376 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Register Index Register Index A DMOCON DMICON 106 S3IC SAIC oiii 87 SD HGAEY 505 DMOIC DMItIC cccecececeseseseseseseseeese 86 S3TRR to S6TRR e 137 ADCONO 204 207 209 211 013 215 Min i AE ee eee ADCON 204 207 209 211 213215 Ma bi SARA usse ADCOND cau e eet idee ete 2 AA T ipcrM TE 86 F AU sis NIEFlazciscsdis abet niieiiniie TUO EMO aste te 266 TAOIC sss 86 AERA ieia eia ji BOO EWA cseaciamie 266 TAOMR 116 119 121 126 128 C T T e M E 116 143 m RN Bb TAI ena 143 ITE snnnsssisssrinsrriesrrnssrrnesnresnnnenns 144 TAIG Listes 86 COTWKIC uie enu Se 1589 IDEM do AUR nel O eran COAFS CTAFS csupiatepietun sud IFSRO eren tenore 95 M MRNA 116 143 COCONR C1CONR e 232 IFSR1 96 RU 143 COCTLR C1CTLR e 229 IFSR2 cesses ATA 97 TABI Ci ee duet 87 COGMR C1GMR e 227 EDER CICA INTOIC to INT8IC ee 87 TA2MR 116 119 121 123 126 128 146 s EU INVCO
41. 21mA f BCLK 224MHz PLL operation no division Flash Memory 23mA f BCLK 24MHz 21mA f BCLK 20MHz PLL operation no division PLL operation no division Mask ROM Flash Memory 3pA f BCLK 32kHz Wait mode Oscillation capacity Low 0 8pA Stop mode Topr 25 C Flash Memory Version Program Erase Supply Voltage 3 0 0 3V or 5 0 0 5V 5 0 0 5V Program and Erase Endurance 100 times I O Characteristics I O Withstand Voltage 5 0V Output Current 5mA Operating Ambient Temperature 40 to 85 C T version 40 to 85 C V version 40 to 125 C option Device Configuration CMOS high performance silicon gate Package NOTES plastic mold LQFP 1 PC bus is a registered trademark of Koninklijke Philips Electronics N V 2 IEBus is a registered trademark of NEC Electronics Corporation option All options are on request basis Rev 2 00 Nov28 2005 page 2 of 378 REJO9BO0124 0200 31 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 2 Performance Outline of M16C 6N Group 128 pin Version M16C 6NM Number of Basic Instructions 91 instructions Performance Normal ver T V ver Minimum Instruction Execution Time 41 7ns f BCLK 24MHz 1 1 prescaler without software wait 50 0ns f BCLK 2
42. After this the bit is automatically set to O 2 When the RetBusOff bit 1 the CIRECR and CiTECR registers are set to 00h After this this bit is automatically set to 0 3 Change this bit only in the CAN reset initialization mode 4 When the listen only mode is selected do not request the transmission Figure 19 7 COCTLR and C1CTLR Registers Rev 2 00 Nov28 2005 page 229 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM CANI Status Register i 0 1 b7 b6 b5 b4 b3 b2 bi bO Symbol COSTR C1STR Address 0212h 0232h 19 CAN Module After Reset 00h 00h Bit Symbol Bit Name Function Active Slot Bits 1 Successful TrmSucc Transmission Flag 1 Successful Reception Flag 1 Transmission Flag Transmitter Reception Flag Receiver Slot O Slot 1 Slot 2 Slot 14 Slot 15 i 1 No successful transmission The CAN module has transmitted a message successfully 0 No successful reception 1 CAN module received a message successfully 0 CAN module is idle or receiver 1 CAN module is transmitter 0 CAN module is idle or transmitter 1 CAN module is receiver 1 These bits can be changed only when a slot which an interrupt is enabled by the CilCR register is transmitted or received successfully Address 0213h 0233h After
43. CLKMD1 0 o CTS1 pO o 1 CTS RTS disabled rj CTSO from UARTO CRD n1 Values set to the UTBRG register PCLK1 Bit in PCLKR register SMD2 to SMDO CKDIR Bits in U1MR register CLK1 to CLKO CKPOL CRD CRS Bits in U1CO register CLKMDO CLKMD1 RCSP Bits in UCON register Figure 15 2 UART1 Block Diagram Rev 2 00 Nov28 2005 page 150 of 378 REJ09B0124 0200 134 NESAS Transmit receive unit polarity reversing circuit TXD polarity reversing circuit Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM UART2 PCLK1 f2SIO 12 fiSlo ol Main clock PLL clock or on chip oscillator clock e Ld gt f1SIO or f2SIO gt f8SIO 1 8 1 4 f32SIO RXD polarity reversing RXD2 O circuit Clock source selection CLKito CLKO ckpig f1SIO or f2810 0 Internal U2BRG fasio 91lo N register f32Si0 10 _ n2 1 to External UART reception SMD2 to SMDO 116 010 100 101 110 o Clock synchronous sot Reception clock type i control ci Receive ircuit UART transmissiot Transmit 010 100 101 110 i Transmission clock type 001 Clock synchronous type when internal clock is selected No
44. Multiply by 2 Multiply by 4 PLL Multiplying Factor Multiply by 6 4 RW Select Bit 2 Do not set a value RW Nothing is assigned When write set to 0 When read its content is indeterminate Reserved Bit Set to 1 Reserved Bit Set to 0 PLL Off Operation Enable Bit 3 i PLL o 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 This bit can only be modified when the PLCO7 bit 0 PLL turned off The value once written to this bit cannot be modified 3 Before setting this bit to 1 set the CMO7 bit in the CMO register to 0 main clock set the CM17 to CM16 bits in the CM1 register to 00b main clock undivided mode and set the CMO6 bit in the CMO register to 0 CM16 and CM17 bits enable 4 Multiply by 6 is available Normal ver only Figure 8 8 PLCO Register Rev 2 00 Nov28 2005 page 63 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit The following describes the clocks generated by the clock generating circuit 8 1 1 Main Clock The main clock is generated by the main clock oscillation circuit This clock is used as the clock source for the CPU and peripheral function clocks The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins The main c
45. NOTES 1 Referenced to VCC AVCC VREF 3 3 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 AD frequency must be 10MHz or less 3 When sample amp hold is disabled 9AD frequency must be 250kHz or more in addition to a limit of NOTE 2 When sample amp hold is enabled AD frequency must be 1MHz or more in addition to a limit of NOTE 2 Table 22 7 D A conversion Characteristics Standard Min Typ Parameter Measuring Condition Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current NOTES 1 Referenced to VCC AVCC VREF 3 3 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 This applies when using one D A converter with the DAI register i 0 1 for the unused D A converter set to 00h The resistor ladder of the A D converter is not included Also the current lvrer always flows even though VREF may have been set to be unconnected by the ADCON1 register Rev 2 00 Nov28 2005 page 297 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 8 Flash Memory Version Electrical Characteristics Symbol n Parameter Typ Program and Erase Endurance Word Program Time VCC z 5 0V Lock Bit Program Time Block Erase Time 4 Kbyte blo
46. Nom Max D 13 9 14 0 14 1 E 13 9 14 0 14 1 Terminal cross section A2 14 Hp 15 8 16 0 16 2 He 15 8 16 0 16 2 A 17 A1 0 05 0 1 0 15 Index mark bp 0 15 0 20 0 25 bi 0 18 0 09 0 145 0 20 a C4 0 125 JA NG Bi d H i 0 es8 amp i e zm d e 05 z y 9a d q X 0 08 cem ex y 0 08 Detail F A 18 E E L 0 35 0 5 0 65 L 1 0 JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP128 14x20 0 50 PLQP0128KB A 128P6Q A 0 9g NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH bp 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET e c Reference Dimension in Millimeters Terminal cross section Symbol Min Nom Me D 19 9 20 0 20 1 E 139 140 14 1 A2 14 Hp 21 8 220 222 He 15 8 16 0 16 2 A 17 mE 2 1 uj 0 05 0 125 0 2 p 0 17 0 22 0 27 bi 020 z C 0 09 0 145 0 20 L c1 0 125 L 8 o 8 e 05 DetailF z ET y 0 10 Zp 075 Ze 0 75 L 0 35 0 5 0 65 L
47. Output disabled Output enabled 1 The UjLCH bit is enabled when the SMD2 to SMDO bits in the UjMR register are set to 001b clock synchronous serial I O mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit transfer data Set this bit to 0 when the SMD2 to SMDO bits are set to 010b I C mode or 110b UART mode 9 bit transfer data UART2 Transmit Receive Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol U2C1 After Reset 00000010b symbo BitName Function Pw 0 Transmission disabled Transmit Enable Bit 1 Transmission enabled Transmit Buffer Empty Flag Data present in U2TB register No data present in U2TB register Receive Enable Bit Reception disabled Reception enabled Receive Complete Flag No data present in U2RB register Data present in U2RB register UART2 Transmit Interrupt Cause Select Bit Transmit buffer empty TI bit 1 Transmit is completed TXEPT bit 1 UART2 Continuous Receive Mode Enable Bit Continuous receive mode disabled Continuous receive mode enabled Data Logic Select Bit 1 No reverse Reverse Error Signal Output Enable Bit Output disabled Output enabled 70 AD 2o 2o TO 2o 1 The U2LCH bit is enabled when the SMD2 to SMDO bits in the U2MR register are set to 001b clock synchronous serial I O mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit t
48. Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 2 VREF connected m b7 b6 0 0 ANEXO and ANEX1 are not used RW External Op Amp 0 1 ANEXO input is A D converted Connection Mode Bit 10 ANEX1 input is A D converted 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 4 ADCONO Register and ADCON1 Register in One shot Mode Rev 2 00 Nov28 2005 page 207 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter 16 1 2 Repeat Mode In repeat mode analog voltage applied to a selected pin is repeatedly converted to a digital code Table 16 3 lists the specifications of repeat mode Figure 16 5 shows the ADCONO and ADCON1 registers in repeat mode Table 16 3 Repeat Mode Specifications Function The CH2 to CHO bits in the ADCONO register the ADGSEL1 to ADGSELO bits in the ADCON2 register and the OPA1 to OPAO bits in the ADCON1 register select a pin Analog voltage applied to this pin is repeatedly converted to a digital code A D Conversion e When the TRG bit in the ADCONO register is 0 software trigger Start Condition The ADST bit in the ADCONO register is set to 1
49. Sleep Mode STB Pin Normal Operation Mode H EN Pin H CAN Communication impossible possible Connection M6C GNK M16C 6NM PCAB2C252 Switch OFF i 0 1 NOTES M16C GNK M16C 6NM POSSE Switch ON 1 The pin which controls the operation mode of CAN transceiver 2 Connect to enabled port to control CAN transceiver Rev 2 00 Nov 28 2005 page 366 of 378 REJ09B0124 0200 131 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 15 Programmable I O Ports If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the P7 2 to P7 5 P8 O and P8 1 pins go to a high impedance state Setting the SM32 bit in the S3C register to 1 causes the P9 2 pin to go to a high impedance state Setting the SM42 bit in the S4C register to 1 causes the P9 6 pin to go to a high impedance state Setting the SM52 bit in the S5C register to 1 causes the P11 2 pin to go to a high impedance state Setting the SM62 bit in the S6C register to 1 causes the P11 6 pin to go to a high impedance state NOTES 1 When using SI O4 set the SM43 bit in the SAC register to 1 SOUTA output CLK4 function and the port direction bit corresponding for SOUTA pin to 0 input
50. To use the main clock as the clock source for the CPU clock set bits in the following order 1 Set the CMOS5 bit to 0 oscillate 2 Wait until the main clock oscillation stabilizes 3 Set the CM11 CM21 and CMO7 bits all to 0 When the CM21 bit 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CM06 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High During external clock input set the CMOS5 bit to 0 oscillate When the CMO5 bit is set to 1 the XOUT pin goes H Furthermore because the internal feedback resistor remains connected the XIN pin is pulled H to the same level as XOUT via the feedback resistor 10 When entering stop mode from high or medium speed mode on chip oscillator mode or on chip oscillator low power dissipation mode the CMOS6 bit is set to 1 divide by 8 mode 11 After setting the CM04 bit to 1 XCIN XCOUT oscillator function wait until the sub clock oscillates stably before switching the CMO7 bit from O to 1 sub clock 12 To return from on chip oscillator mode to high speed or medium speed mode set the CMO6 and CM15 bits both to 1 Figure 8 2 CMO Register Rev 2 00 Nov28 2005 page 58 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit System Clock Contro
51. VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 6 ADCONO Register and ADCON 1 Register in Single Sweep Mode Rev 2 00 Nov28 2005 page 211 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 1 4 Repeat Sweep Mode 0 In repeat sweep mode 0 analog voltage applied to selected pins is repeatedly converted to a digital code Table 16 5 lists the specifications of repeat sweep mode 0 Figure 16 7 shows the ADCONO and ADCON1 registers in repeat sweep mode 0 Table 16 5 Repeat Sweep Mode 0 Specifications Function Specification The SCAN1 to SCANO bits in the ADCON1 register and the ADGSEL1 to ADGSELO bits in the ADCON2 register select pins Analog voltage applied to the pins is repeatedly converted to a digital code A D Conversion Start Condition e When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Set the ADST bit to 0 A D conversion halted Interrupt Request Generation Timing None generated Analog Input Pin Select from ANO to AN1 2 pins ANO to ANS 4
52. 0 STPREQ Set this bit to 1 to generate stop condition Set to 0 STSPSEL Set this bit to 1 to output each condition Set to 0 ACKD Select ACK or NACK ACKC Set this bit to 1 to output ACK data SCLHI Set this bit to 1 to have SCLi output stopped when stop condition is detected Set to 0 SWC9 Set to 0 Set this bit to 1 to set the SCLi to L hold at the falling edge of the 9th bit of clock IFSRO6 ISFRO7 Set to 1 i Oto2 NOTES UOIRS U1IRS Invalid 2107 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in I2C mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U11RS UORRM and U1RRM bits are in the UCON register Rev 2 00 Nov28 2005 page 177 of 378 REJ09B0124 0200 31 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 12 1 C Mode Functions Function Factor of Interrupt Number 6 7 and 10 06 0 Clock Synchronous Serial I O Mode SMD2 to SMDO 001b IICM 0 I C Mode SMD2 to SMDO 010b IICM 1 IICM2 1 UART transmit receive interrupt IICM2 0 NACK ACK interrupt CKPH 0 No clock delay CKPH 1 Clock delay CKPH 0 CKPH 1 No clock delay Clock delay
53. 0 with the three phase motor control timer function b7 b6 0 0 f1 or f2 Count Source Select Bit 9 1 f8 10 f32 1 fC32 Timer B2 Mode Register b7 b6 b5 b4 b3 b2 bi LT LTT Symbol Address After Reset TB2MR 039Dh 00XX0000b Sa ee nem m T TMODO Set to 00b timer mode when using nw Es BE Mode the three aud motor Cd timer TMOD1 function RW MRo _ Disabled when using the three phase motor control timer function When write set to 0 MR1 When read its content is indeterminate MR2 Set to 0 when using three phase motor control timer function RW When write in three phase motor control timer function set to 0 MR3 When read in three phase motor control timer function its content is indeterminate 10 f32 Test 1 1 fC32 b7 b6 TCKO 00 ftorf2 vox Count Source Select Bit 0 1 f8 Figure 14 8 TA1MR TA2MR and TA4MR Registers and TB2MR Register Rev 2 00 Nov28 2005 page 146 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function The three phase motor control timer function is enabled by setting the INVO2 bit in the INVCO register to 1 When this function is selected timer B2 is used to control the carrier wave and timers A4 A1 and A2 are used to control three phase PWM outputs U U V V W and W The dead time is controlled by a ded
54. 1 enabled enables the maskable interrupt Setting the I flag to 0 disabled disables all maskable interrupts 10 5 2 IR Bit The IR bit is set to 1 interrupt requested when an interrupt request is generated Then when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector the IR bit is set to 0 interrupt not requested The IR bit can be set to 0 in a program Note that do not write 1 to this bit 10 5 3 ILVL2 to ILVLO Bits and IPL Interrupt priority levels can be set using the ILVL2 to ILVLO bits Table 10 3 shows the settings of interrupt priority levels and Table 10 4 shows the interrupt priority levels enabled by the IPL The following are conditions under which an interrupt is accepted I flag 1 IR bit 1 interrupt priority level gt IPL The flag IR bit ILVL2 to ILVLO bits and IPL are independent of each other In no case do they affect one another H 10 3 of interrupt Priority Leve Table 10 4 Interrupt Priority Levels Enabled by IPL IPL Enabled Interrupt Priority Levels Level 0 Interrupt disabled Interrupt levels 1 and above are enabled Level 1 Interrupt levels 2 and above are enabled Level 2 Interrupt levels 3 and above are enabled Level 3 Interrupt levels 5 and above are enabled Level 4 Interrupt levels 5 and above are enabled Level 5 Interrupt levels 6 and above are enabled Level 6 Interrupt levels 7 and above are enabled Level 7 i
55. 1 Sampling Control One time sampling Bit Three times sampling Propagation Time Segment Control Bits o 2 TES VES c A3 c o ooo 00 o 2o8 Ere O 1 fCAN serves for the CAN clock The period is decided by configuration of the CCLKi bit i 0 to 2 4 to 6 in the CCLKR register b15 b7 b6 b5 b C Symbol Address After Reset COCONR 021Bh Indeterminate C1CONR 023Bh Indeterminate b2 b1b0 000 Do not set a value Phase Buffer 001 2Tq Segment 1 0 10 3Tq Control Bits d 110 7Tq 111 8Tq b5 b4 b3 000 Do not set a value Phase Buffer 001 2Tq Segment 2 010 3Tq Control Bits f 110 7Tq 111 8Tq Resynchronization Jump Width Control Bits Figure 19 10 COCONR and C1CONR Registers Rev 2 00 Nov 28 2005 page 232 of 378 7tENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module CANI Receive Error Count Register i 0 1 i 2 Symbol Address After Reset C1RECR 023Ch 00h Reception error counting function D The value is incremented or decremented 00h to FFh 1 according to the CAN module s error status 1 The value is indeterminate in bus off state CANi Transmit Error Count Register i 0 1 b7 b0 Symbol Address After Reset T C1TECR 023Dh 00h Transmission error counting function D The value is incremented or decremented 00h to FFh 1 according to
56. 1 j O to 15 is set to 1 Transmission slot in the bus idle state the TrmActive bit in the CiMCTLj register and the TrmState bit in the CiSTR register are set to 1 Transmitting Transmitter and CAN module starts the transmission 2 If the arbitration is lost after the CAN module starts the transmission the TrmActive and TrmState bits are set to 0 3 If the transmission has been successful without lost in arbitration the SentData bit in the CIMCTLj register is set to 1 Transmission is successfully completed and TrmActive bit is set to 0 Waiting for bus idle or completion of arbitration And when the interrupt enable bits in the CilCR register 1 Interrupt enabled CANi successful transmission interrupt request is generated and the MBOX the slot number which transmitted the message and TrmSucc bit in the CiSTR register are changed 4 When starting the next transmission set the SentData and TrmReq bits to 0 And set the TrmReq bit to 1 after checking that the SentData and TrmReq bits are set to 0 Rev 2 00 Nov28 2005 page 245 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 16 CAN Interrupt The CAN module provides the following CAN interrupts CANi Successful Reception Interrupt i 0 1 CANi Successful Transmission Interrupt CANO 1 Error Interrup
57. 10 One shot timer mode 11 Pulse width measuring mode Noise filter TCK1 to TCKO 00 51 00 5 01 Event counter mode 10 Ne o bo 11 TA3TGH to TASTGL TMOD1 to TMODO 00 Timer mode Noise filter 01 Q 10 O 00 11 TA4TGH to TA4TGL Timer B2 overflow or underflow 10 One shot timer mode 11 Pulse width measuring mode o 01 Event counter mode TCK1 to TCKO TMOD1 to TMODO Bits in TAiMR register i O to 4 TAiTGH to TAITGL Bits in ONSF register or TRGSR register NOTE 1 Be aware that TAOIN shares the pin with RXD2 SCL2 and TBSIN Figure 13 1 Timer A Configuration Rev 2 00 Nov28 2005 page 113 of 378 REJ09B0124 0200 131 NESAS Timer A3 interrupt Timer A4 interrupt Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Main clock PLL clock On chip oscillator clock f f1 or f2 f8 f32 C32 oo CKI to TCKO f PCLKO 0 Q Clock prescaler f1 or f2 xen 1 32 Set the CPSR bit in the Reset CPSRF register to 1 prescaler reset Timer B2 overflow or underflow to a count source of theTimer A Noise filter TCKO Noise filter TCKO TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer BO interr
58. 19 12 Return from Bus Off Function When the protocol controller enters bus off state it is possible to make it forced return from bus off state by setting the RetBusOff bit in the CiCTLR register i 0 1 to 1 Force return from bus off At this time the error state changes from bus off state to error active state If the RetBusOff bit is set to 1 the CIRECR and CiTECR registers are initialized and the State BusOff bit in the CiSTR register is set to 0 CAN module is not in error bus off state However registers of the CAN module such as CiCONR register and the content of each slot are not initialized 19 13 Time Stamp Counter and Time Stamp Function When the CiTSR register i 2 O 1 is read the value of the time stamp counter at the moment is read The period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the CiCONR register The time stamp counter functions as a free run counter The 1 bit time period can be divided by 1 undivided 2 4 or 8 to produce the time stamp counter reference clock Use the TSPreScale bit in the CiCTLR register to select the divide by n value The time stamp counter is equipped with a register that captures the counter value when the protocol controller regards it as a successful reception The captured value is stored when a time stamp value is stored in a reception slot 19 14 Listen Only Mode When the RXOnly bit in the CiCTLR register i
59. 21 3 3 7 FMRO7 Bit This is a read only bit indicating the auto erase operation status The FMRO7 bit is set to 1 when an erase error occurs otherwise it is set to 0 For details refer to 21 3 8 Full Status Check 21 3 3 8 FMR11 Bit EWO mode is entered by setting the FMR11 bit to 0 EWO mode EW1 mode is entered by setting the FMR11 bit to 1 EW1 mode 21 3 3 9 FMR16 Bit This is a read only bit indicating the execution result of the read lock bit status command When the block where the read lock bit status command is executed is locked the FMR16 bit is set to O When the block where the read lock bit status command is executed is unlocked the FMR16 bit is set to 1 Figure 21 5 shows setting and resetting of EWO mode Figure 21 6 show setting and resetting of EW1 mode Rev 2 00 Nov28 2005 page 268 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version Procedure to enter EWO mode z Rewrite control program Single chip mode memory expansion mode 9 In boot mode only or boot mode set the FMRO5 bit to 1 user ROM area access Transfer the rewrite control program in CPU rewrite Set the FMRO1 bit to 1 CPU rewrite mode mode to a space other than the flash memory 9 enabled after writing 0 2 Set CMO CM1 and PM1 registers 1 l Execute software co
60. 23 Usage Precaution 23 14 CAN Module 23 14 1 Reading CiSTR Register i 0 1 The CAN module on the M16C 6N Group M16C 6NK M16C 6NM updates the status of the CISTR register in a certain period When the CPU and the CAN module access to the CiSTR register at the same time the CPU has the access priority the access from the CAN module is disabled Consequently when the updating period of the CAN module matches the access period from the CPU the status of the CAN module cannot be updated See Figure 23 5 When Updating Period of CAN Module Matches Access Period from CPU Accordingly be careful about the following points so that the access period from the CPU should not match the updating period of the CAN module a There should be a wait time of 3fCAN or longer see Table 23 3 CAN Module Status Updating Period before the CPU reads the CiSTR register See Figure 23 6 With a Wait Time of 3fCAN Before CPU Read b When the CPU polls the CiSTR register the polling period must be 3fCAN or longer See Figure 23 7 When Polling Period of CPU is 3fCAN or Longer Table 23 3 CAN Module Status Updating Period 3fCAN Period 3 x XIN Original Oscillation Period x Division Value of CAN Clock CCLK Example 1 Condition XIN 16 MHz CCLK Divided by 1 3fCAN period 3 x 62 5 ns x 1 187 5 ns Example 2 Condition XIN 16 MHz CCLK Divided by 2 3fCAN period 2 3x 62 5 ns x 22 375 ns Example 3 Condition XIN 16 MHz CCLK Divided by 4 3fCAN pe
61. 8 5 Oscillation Stop and Re oscillation Detection Function sessssssseseeneeenneeneen ens 78 8 5 1 Operation When CM27 Bit 0 Oscillation Stop Detection Reset ssssssseee 78 8 5 2 Operation When CM27 Bit 1 Oscillation Stop Re oscillation Detection Interrupt 78 8 5 3 How to Use Oscillation Stop and Re oscillation Detection Function sessesseeeeeese 79 SM ITEM E T T o STET 80 1O MRSC o cc 81 10 1 Type ob Intertilpls s scorre cect sts cdeexastsctetersapsince bra EENE ama exiuen tex e textu sete db estu reser atte exu inae texting Sek xen 81 10 2 Sofware IMSS ese cs EE 82 10 2 1 Undetined Instruction Interr pt uiuo tte teen a deinen 82 10 2 2 Overflow Interrupt simsii arenira enana ananpi aiaia a Tiai anned inkab aa ioiak denA ainra aiii nnns 82 10 2 3 BRK Interrupt srira 82 1O24 INT Instruction Interr pt ssaa O eu vues etu udo acento 82 10 3 Hardware MIS PUPS 3 irai ro dE Ee tn Peter ttt aer ee pee cau qp daca sce wee iD ned rers biete bue dr Pee vane E 83 10 3 11 Special Interrupts scssi ec eet SR e Eua ELSE FEVER Geel ee 83 10 3 2 Peripheral Function Interrupts esssessseeeeeeeneeennn nennen nemen nennen nnne 83 10 4 Interrupts and Interrupt Vector sosisini an ET TE nen nnnnn rnit nenene nnne 84 10 4 1 Fixed Vector Tables tert e
62. A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Set the ADST bit to 0 A D conversion halted Stop Condition Interrupt Request None generated Generation Timing Analog Input Pin Select one pin from ANO to AN7 ANO 0 to ANO 7 AN2 0 to AN2 7 ANEXO to ANEX1 Reading of Result of Read one of the ADO to AD7 registers that corresponds to the selected pin A D Converter Rev 2 00 Nov28 2005 page 208 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 0 ee Symbol Address After Reset Lait AO oe 00000005 Bit Symbol b2 b1 b0 000 ANO is selected 001 AN1 is selected AN2 is selected AN3 is selected AN4 is selected AN5 is selected AN6 is selected ANT is selected 2 3 MDO A D Operation Mode MDi Select Bit 0 Repeat mode 3 Software trigger ome Trigger Select Bit ADTRG trigger A D conversion disabled ADST A D Conversion Start Flag A D conversion started Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be use
63. CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK 7 1 Bus Mode The bus mode either multiplexed or separate can be selected using the PMO5 to PMO4 bits in the PMO register 7 1 1 Separate Bus In this bus mode data and address are separate 7 1 2 Multiplexed Bus In this bus mode data and address are multiplexed 7 1 2 1 When the input level on BYTE pin is high 8 bit data bus DO to D7 and AO to A7 are multiplexed 7 1 2 2 When the input level on BYTE pin is low 16 bit data bus DO to D7 and A1 to A8 are multiplexed D8 to D15 are not multiplexed Do not use D8 to D15 External devices connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer Odd addresses cannot be accessed Table 7 1 shows the difference between a separate bus and multiplexed bus Table 7 1 Difference between Separate Bus and Multiplexed Bus Pin N a S is Multiplexed Bus in Name eparate Bus BYTE LH BYTE L L PO Oto PO_7 DO to D7 X DO to D7 NOTE 2 NOTE 2 1 O Port P1_0 to P1_7 D8 to D15 X D8to D15 EOS NOTE 2 P2 0 AO DO A0 X AO X DO X X AO X P2_1 to P2_7 A1 to A7 A1 to A7 A1 to A7XD1 to D7 A1 to A7XDO to D6 D1 to D7 DO to D6 B XA to A7XD1 to D7X XA1 to A7 X P3 0 A8 D7 A8 x A8 XIX as X D7 X NOTES 1 See Table 7 6 Pin Functions for Each Processor Mode for bus control signals other than the above 2 It changes with a s
64. DMAS Bit in DMiCON Register d Timing at which the bit is set to 1 Timing at which the bit is set to 0 Software Trigger When the DSR bit in the DMIiSL register e Immediately before a data transfer starts is set to 1 When set by writing 0 in a program Peripheral Function When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSELO and DMS bits in the DMISL register has its IR bit set to 1 Rev 2 00 Nov28 2005 page 111 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC 12 5 Channel Priority and DMA Transfer Timing If both DMAO and DMA1 are enabled and DMA transfer request signals from DMAO and DMA are detected active in the same sampling period one period from a falling edge to the next falling edge of BCLK the DMAS bit on each channel is set to 1 DMA requested at the same time In this case the DMA requests are arbitrated according to the channel priority DMAO gt DMA1 The following describes DMAC operation when DMAO and DMA1 requests are detected active in the same sampling period Figure 12 6 shows an example of DMA transfer effected by external factors In Figure 12 6 DMAO request having priority is received first to start a transfer when a DMAO request and DMA1 request are generated simultaneously After one DMAO transfer
65. Main clock turned off PLC07 0 CM11 0 Main clock selected Divide by 4 Divide by 8 Divide by 16 PLCO7 1 CM11 1 PLL clock selected CM21 0 Main clock or PLL clock selected c c E o eo e o 2 e a 23 wa uc c T D c 5 E x oO 2 e a gt wm 9 Rev 2 00 Nov 28 2005 page 77 of 378 No Division Divide by 2 Divide by 4 Divide by 8 Divide by 16 _ setting method See right table 7tENESAS REJO9BO0124 0200 CM21 1 On chip oscillator clock selected CM10 1 Transition to stop mode WAIT instruction Transition to wait mode interrupt CM20 CM21 PLCO7 Hardware Exit stop mode or wait mode CM04 CMO05 CM06 CMO7 Bits in CMO register CM10 CM11 CM16 CM17 Bits in CM1 register Bits in CM2 register Bit in PLCO register Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 5 Oscillation Stop and Re oscillation Detection Function The oscillation stop and re oscillation detection function is such that main clock oscillation circuit stop and re oscillation are detected At oscillation stop re oscillation detection reset or oscillation stop re oscillation detection interrupt request are generated Which one is to be generated can be selected using the CM27 bit in
66. NOTES 1 Block A can be made usable by setting the PM10 bit in the PM1 register to 1 block A enabled addresses 10000h to 26FFFh for CS2 area Block A cannot be erased by the erase all unlocked block command Use the block erase command to erase it 2 The boot ROM area can only be rewritten in parallel I O mode 3 To specify a block use an even address in that block Figure 21 1 Flash Memory Block Diagram Rev 2 00 Nov28 2005 page 261 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 1 1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an H signal is applied to the CNVSS and P5 0 pins and an L signal is applied to the P5 5 pin A program in the boot ROM area is executed In boot mode the FMROS bit in the FMRO register selects access to the boot ROM area or the user ROM area The rewrite control program for standard serial I O mode is stored in the boot ROM area before shipment The boot ROM area can be rewritten in parallel I O mode only If any rewrite control program using erase write mode EWO mode is written in the boot ROM area the flash memory can be rewritten according to the system implemented 21 2 Functions to Prevent Flash Memory from Rewriting The flash memory has a built in ROM code protect function for parallel I O mode and a built in ID
67. P11 6 P12 0to P12 7 P13 O toP13 4 P14 0 P14 169 P1 OtoP1 4 P1 5toP1 7 P5 7 P6 0 P6 4 P7 3to P7 6 P8 0 P8 1 P9 0 P9 2 Figure20 1 I O Ports 1 Rev 2 00 Nov28 2005 page 249 of 378 REJO9BO0124 0200 M16C 6NM 20 Programmable l O Ports Pull up selection Direction register inside dotted line included M Data bus 4 Port latch inside dotted line not included Pull up selection Direction register M Port P1 control register Data bus 4 Port latch 4 a Pull up selection Direction register M Port P1 control register Data bus 4 Port latch Input to respective peripheral functions lt _ 4 Pull up selection Direction register 24 Data bus lt re e oupui e o gt D Port latch m a Input to respective peripheral functions cere Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 P11 to P14 are only in the 128 pin version 131 NESAS Unde
68. The S5TRF and S6TRF bits are only in the 128 pin version 2 When setting the S3TRF to S6TRF bits to 0 use the MOV instruction to write to the these bits after setting to 0 the bit set to 0 and setting other bits to 1 Figure 15 38 S3456TRR Register Rev 2 00 Nov28 2005 page 198 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 19 SI Oi Specifications Transfer Data Format Transfer data length 8 bits Transfer clock e SMi6 bit in SiC register 1 internal clock fj 2 n 1 fj f1SIO f8SIO f32SIO n Setting value of SiBRG register OOh to FFh e SMi6 bit 0 external clock Input from CLKi pin Transmission Reception Before transmission reception can start the following requirements must be met Start Condition Write transmit data to the SiTRR register Interrupt Request When SMi4 bit in SiC register 0 Generation Timing The rising edge of the last transfer clock pulse e When SMi4 bit 1 The falling edge of the last transfer clock pulse CLKi Pin Function I O port transfer clock input transfer clock output SOUTi Pin Function I O port transmit data output high impedance SINi Pin Function I O port receive data input Select Function e LSB first or MSB first selection Whether to start sending receiving data beginning with bit 0 or beginning with bit 7 can be select
69. The following table lists how the INV11 bit works INV11 0 Three phase mode 0 Three phase mode 1 TA11 TA21 and TA41 Registers Not used Used Disabled The ICTB2 counter is INVOO and INVO1 Bit incremented whenever the timer B2 Enabled underflows INV13 Bit Disabled Enabled when INV11 1 and INVO6 0 When the INVO6 bit is set to 1 sawtooth wave modulation mode set the INV11 bit to 0 three phase mode 0 Also when the INV11 bit is set to 0 set the PWCON bit in the TB2SC register to 0 timer B2 is reloaded when the timer B2 underflows The INV13 bit is enabled only when the INVO6 bit is set to 0 Triangular wave modulation mode and the INV11 bit to 1 three phase mode 1 If the following conditions are all met set the INV16 bit to 1 rising edge of the three phase output shift register The INV15 bit is set to 0 dead time timer enabled e The Dij bit iU V or W j 0 1 and DiBj bit always have different values when the INVO3 bit is set to 1 The positive phase and negative phase always output opposite level signals If above conditions are not met set the INV16 bit to O falling edge of a one shot pulse of the timer A1 A2 A4 Figure 14 3 INVC1 Register Rev 2 00 Nov28 2005 page 141 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer
70. at completion of reception Error detection Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select function i Oto2 NOTES Clock phase setting Selectable from four combinations of transfer clock polarities and phases 1 When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit 2 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state 2 The UOIRS and U1IRS bits respectively are bits O and 1 in the UCON register the U2IRS bit is bit 4 in the U2C1 register 3 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in SiRIC register does not change Rev 2 00 Nov28 2005 page 184 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM P7 2 CLK2 P7 1 RXD2 P7 O TXD2 Microcomputer Master 15 Serial Interface P9 3 P7 2 CLK2 P7 1 RXD2 P7 O TXD2 Microcomputer Slave P9 3 P7 2 CLK2 P7 1 RXD2 P7
71. automatically UiBCNIC register clear when bus collision occurs the TE bit is set to 0 T transmission disabled when TE bit in the IR bit in the UIBCNIC register 1 UiC1 register unmatching detected 3 SSS Bit in UiSMR Register transmit start condition select If SSS bit 0 the serial I O starts sending data one transfer clock cycle after the transmission enable condition is met Transfer clock mm f f f f l f l f f fl TLI T D1 D2 D4 Lo Transmission enable condition is met If SSS bit 1 the serial I O starts sending data at the rising edge of RXDi CLKi TXDi NOTE 2 RXDi NOTES 1 The falling edge of RXDi when IOPOL bit 0 the rising edge of RXDi when IOPOL bit 1 2 The transmit condition must be met before the falling edge 1 of RXDi i Oto2 This diagram applies to the case where IOPOL bit 1 reversed Figure 15 31 Bus Collision Detect Function Related Bits Rev 2 00 Nov 28 2005 page 190 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 6 Special Mode 4 SIM Mode UART2 Based on UART mode this is an SIM interface compatible mode Direct and inverse formats can be implemented and this mode allows to output a low from the TXD2 pin when a parity error is detected Table 15 17 lists the specifications of SIM mode T
72. converter Figure 17 2 shows the D A converter related registers Figure 17 3 shows the D A converter equivalent circuit Table 17 1 D A Converter Performance Performance D A conversion Method R 2R method Resolution 8 bits Analog Output Pin 2 channels DAO and DA1 Data bus low order 1 DAO register R 2R resistor ladder DAOE bit DA1 register R 2R resistor ladder DATE bit Figure 17 1 D A Converter Block Diagram Rev 2 00 Nov28 2005 page 219 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 17 D A Converter D A Control Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset DACON O3DCh 00h Bi Symbol d Output disabled DAOE D AO Output Enable Bit Output enabled aw o disabled DA1E D A1 Output Enable Bit Output enabled E Nothing is assigned When write set to 0 When read their contents are 0 1 When not using the D A converter set the DAiE bit i 0 1 to 0 output disabled to reduce the unnecessary current consumption in the chip and set the DAi register to 00h to prevent current from flowing into the R 2R resistor ladder D A Register i i 0 1 b7 bO Symbol Address After Reset DA1 O3DAh 00h Function Setting Range Output value of D A conversion OOh to FFh nw il When not using the D A converter set the DAIE bit i 0 1 to 0 output di
73. di Data bus Port latch J gt Switching between d CMOS and Nch Input to respective peripheral functions f Pull up selection Direction register gt Output 9 Data bus Port latch i o af 5 x NOTE 1 NOTE 1 H Switching between CMOS and Nch O Data bus lt Ed s x NOTE 1 NMI interrupt input 4 Direction register e T gt Output i Data bus Port latch e al P7_1 P9_1 x t NOTE 2 Input to respective peripheral functions A wove Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 eee Symbolizes a parasitic diode Figure20 3 I O Ports 3 Rev 2 00 Nov 28 2005 page 251 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Pull up selection Direction register P10 Oto P10 3 inside dotted line not included P10 4to P10 7 inside dotted line included Data bus Port latch A Input to respective peripheral functions Pull up selection D A output enabled
74. stop and parity bits are inversed Figure 15 21 shows the TXD and RXD input output polarity inverse 1 When the IOPOL bit in the UiMR register 0 no reverse Transfer clock H ais TXDi H dne as ST j Do j D1 j D2 y D3 j D4 j Ds j DEX D7j P J SP TNI Do j D1 j D2 X D3 j D4 X D5 X D6 j D7 YX Pj L 2 When the IOPOL bit 1 reverse TXDi H eux x Re Od Ou yop yvy se v ST DOR DT D2 D3 j D4 A Ds A De A D7 A PSP RXDi reverse i Oto2 ST Start bit P Parity bit SP Stop bit NOTE 1 This applies to the case where the register bits are set as follows UFORM bit in UiCO register 0 LSB first STPS bit in UIMR register 0 1 stop bit e PRYE bit in UiMR register 1 parity enabled Figure 15 21 TXD and RXD I O Polarity Inverse Rev 2 00 Nov28 2005 page 173 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 2 6 CTS RTS Function When the CTS function is used transmit operation start when L is applied to the CTSi RTSi i 0 to 2 pin Transmit operation begins when the CTSi RTSi pin is held L If the L signal is switched to H during a transmit operation the operation stops before the next data When the RTS function is used the CTSi RTSi pin outputs on L signal when the microcomputer is ready to receive The output level becomes H
75. those written in the flash memory Refer to 21 2 Functions to Prevent Flash Memory from Rewriting Table 21 8 Pin Functions for CAN I O Mode VCC1 VCC2 VSS Power supply input Description Apply the Flash Program Erase Voltage to VCC1 pin and VCC2 to VCC2 pin The VCC apply condition is that VCC2 VCC1 Apply 0 V to VSS pin CNVSS Connect to VCC1 pin Reset input Reset input pin While RESET pin is L level input 20 cycles or longer clock to XIN pin Clock input Clock output Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin and open XOUT pin BYTE BYTE Connect this pin to VCC1 or VSS AVCC AVSS Analog power supply input Connect AVCC to VCC1 and AVSS to VSS respectively VREF Reference voltage input Enter the reference voltage for A D and D A converters from this pin PO 0to PO 7 Input port PO Input H or L level signal or open P1 OtoP1 7 Input port P1 Input H or L level signal or open P2 0to P2 7 Input port P2 Input H or L level signal or open P3 0to P3 7 Input port P3 Input H or L level signal or open P4 0to P4 7 Input port P4 Input H or L level signal or open P5 0 CE input Input H level signal P5 1 to P5 4 P5 6 P5 7 Input po
76. 0 1 is set to 1 the module enters listen only mode In listen only mode no transmission such as data frames error frames and ACK response is performed to bus When listen only mode is selected do not request the transmission Rev 2 00 Nov28 2005 page 242 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 15 Reception and Transmission Table 19 3 shows configuration of CAN reception and transmission mode Table 19 3 Configuration of CAN Reception and Transmission Mode RecReq Remote RspLock Communication Mode of Slot Communication environment configuration mode configure the communication mode of the slot Configured as a reception slot for a data frame Configured as a transmission slot for a remote frame At this time the RemActive 1 After completion of transmission this functions as a reception slot for a data frame At this time the RemActive 0 However when an ID that matches on the CAN bus is detected before remote frame transmission this immediately functions as a reception slot for a data frame Configured as a transmission slot for a data frame Configured as a reception slot for a remote frame At this time the RemActive 1 After completion of reception this functions as a transmission slot for a data frame At this time the RemActive 0 Howev
77. 0078h to 007Bh INT2 124 to 127 007Ch to 007Fh 10 6 INT Interrupt INT Instruction Interrupt NOTES Address relative to address in INTB APRONS 128 to 131 0080h to 0083h to 252 to 255 O0FCh to OOFFh These interrupts cannot be disabled using the flag Use the IFSRO07 bit in the IFSRO register to select Use the IFSRO6 bit in the IFSRO register to select Use the IFSR17 bit in the IFSR1 register to select M16C 60 M16C 20 16C Tiny Series Software Manual Furthermore use the IFSRO3 bit in the IFSRO register to select when selecting SI O4 or CAN1 successful reception 6 Use the IFSR16 bit in the IFSR1 register to select Furthermore use the IFSROO bit in the IFSRO register to select when selecting SI O3 or CAN1 successful transmission 7 Use the IFSRO 1 bit in the IFSRO register to select 8 During C mode NACK and ACK interrupts comprise the interrupt source 9 Bus collision detection During IE mode this bus collision detection constitutes the cause of an interrupt During lC mode a start condition or a stop condition detection constitutes the cause of an interrupt 10 Use the IFSRO bit in the IFSRO register to select When the IFSRO2 bit 0 CANO 1 wake up is selected When the IFSRO2 bit 1 CANO wake up error is selected 11 Use the IFSRO2 bit in the IFSRO register to select When the IFSRO2 bit 0 CANO 1 error is selected When the IFSRO2 bit 1 CAN1 wake up error is selected
78. 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Rev 2 00 Nov 28 2005 page 318 of 378 REJ09B0124 0200 Switching Characteristics 22 Electric Characteristics Normal ver VCC 3 3V Referenced to VCC 3 3V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 44 Memory Expansion Mode and Microprocessor Mode for 1 to 3 wait setting and external area access Symbol Parameter ta pcL AD Address output delay time tnigcuk AD Address output hold time refers to BCLK th RD AD Address output hold time refers to RD th wR AD Address output hold time refers to WR taectk cs Chip select output delay time thiectk cs Chip select output hold time refers to BCLK taBcLk aLe ALE signal output delay time tn Bcu ALE ALE signal output hold time taecLk RD RD signal output delay time tngcue RD RD signal output hold time tagcuk wn WR signal output delay time tngcue wn WR signal output hold time taectk pB Data output delay time refers to BCLK tniecuk oB Data output hold time refers to BCLK la pB wR Data output delay time refers to WR th WR DB Data output hold time refers to WR tasck HLpa HLDA output delay time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 v 1
79. 0263h j 0264h 0265h 0266h 0267h 0268h 0269h CAN1 Message Box 0 Data Field 026Ah 9 026Dh DOE CAN1 Message Box 0 Time Stamp 0270h 0271h 0272h CAN1 Message Box 1 Identifier DLC 0273h 0274h 0275h 0276h 0277h 0278h o2zon CAN1 Message Box 1 Data Field 027Bh 027Ch 027Dh 027Eh 027Fh CAN1 Message Box 1 Time Stamp X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov 28 2005 page 28 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 11 SFR Information 11 Address 0280h 0281h 0282h g 0283h CAN1 Message Box 2 Identifier DLC 0284h 0285h 0286h 0287h 0288h 0289h CAN1 Message Box 2 Data Field 028Ah 028Bh 028Ch 028Dh 028Eh uem 028Fh CAN1 Message Box 2 Time Stamp 0290h 0291h 0292h I 0293h CAN1 Message Box 3 Identifier DLC 0294h 0295h 0296h 0297h 0298h 0299h 029Ah CAN1 Message Box 3 Data Field 029Bh 029Ch 029Dh 029Eh Ti 029Fh CAN1 Message Box 3 Time Stamp 02A0h 02A1h 02A2h m O2A3h CAN1 Message Box 4 Identifier DLC 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h CAN1 Message Box 4 Data Field 02ABh 02ACh 02ADh 02AEh E O2AFh CAN1 Message Box 4
80. 1 State Reset State BusOff Bits in CiSTR register Figure 19 12 Transition Between Operational Modes 19 5 1 CAN Reset Initialization Mode 19 CAN Module CAN operation mode State Reset 0 when 11 consecutive recessive bits are TEC 255 detected 128 times or RetBusOff 1 Bus off state State_BusOff 1 The CAN reset initialization mode is activated upon MCU reset or by setting the Reset bit in the CiCTLR register i O 1 to 1 If the Reset bit is set to 1 check that the State Reset bit in the CiSTR register is set to 1 Entering the CAN reset initialization mode initiates the following functions by the module CAN communication is impossible When the CAN reset initialization mode is activated during an ongoing transmission in operation mode the module suspends the mode transition until completion of the transmission successful arbitration loss or error detection Then the State Reset bit is set to 1 and the CAN reset initialization mode is activated The CiMCTLj j 0 to 15 CISTR CilCR CiIDR CIRECR CiTECR and CiTSR registers are initialized All these registers are locked to prevent CPU modification The CiCTLR CiCONR CiGMR CiLMAR and CiLMBR registers and the CANi message box retain their contents and are available for CPU access Rev 2 00 Nov28 2005 page 234 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its co
81. 10 7 NMI Interrupt An NMI interrupt request is generated when input on the NMI pin changes state from high to low The NMI interrupt is a non maskable interrupt The input level of this NMI interrupt input pin can be read by accessing the P8 5 bit in the P8 register This pin cannot be used as an input port 10 8 Key Input Interrupt Of P10 4 to P10 7 a key input interrupt request is generated when input on any of the P10 4 to P10 7 pins which has had the PD10 4 to PD10 7 bits in the PD10 register set to 0 input goes low Key input interrupts can be used as a key on wake up function the function which gets the microcomputer out of wait or stop mode However if you intend to use the key input interrupt do not use P10 4 to P10 7 as analog input ports Figure 10 14 shows the block diagram of the key input interrupt Note however that while input on any pin which has had the PD10 4 to PD10 7 bits set to 0 input mode is pulled low inputs on all other pins of the port are not detected as interrupts L PU25 bit in PUR2 register PD10 7 bit in PD10 register PD10 7 bit in PD10 register Pull up transistor O Pull up PD10_6 bit in transistor PD10 register Key input interrupt request O Y Interrupt control circuit Pull up PD10 5 bit in transistor PD10 register o PD10 4 bit in Pull up PD10 register transistor GL Figure 10 14 Key Input Interrupt Block Diagr
82. 11b after reset If the PMO5 to PM04 bits are set to 11b during memory expansion mode P3 1 to P3 7 and P4 0 to P4 3 become I O ports in which case the accessible area for each CS is 256 bytes Not available memory expansion and microprocessor modes in T V ver 5 Not available in T V ver Do not set a value Figure 6 1 PMO Register Rev 2 00 Nov28 2005 page 40 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode Processor Mode Fisgister 10 b7 b6 b5 b4 b3 b2 bi Tojo Symbol Address After reset PM1 0005h 00001000b Bit symbol PM10 CS2 Area Switch Bit 08000h to 26FFFh Block A disable RW Data Block Enable Bit 10000h to 26FFFh Block A enable PM11 Port P3 7 m P3 4 Function Address output Select Bit 3 Port function PM12 Watchdog Timer Function 0 Watchdog timer interrupt BW Select Bit 1 Watchdog timer reset 4 Internal ee Area ne EM No wait state PM17 Wait Bit 6 With wait state 1 wait Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable For the mask ROM version this bit must be set to 0 For the flash memory version the PM10 bit also controls block A by enabling or disabling it When the PM10 bit is set to 1 OFOOOh to OFFFFh block A can be used as internal ROM area In addition the PM10 bit is automatica
83. 12 Use the IFSR04 bit in the IFSRO register to select SI O5 is only in the 128 pin version In the 100 pin version set the IFSR04 bit to 0 Timer B5 13 Use the IFSR20 bit in the IFSR2 register to select INT7 is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 14 Use the IFSR21 bit in the IFSR2 register to select INT6 is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 15 Use the IFSRO5 bit in the IFSRO register to select SI O6 is only in the 128 pin version In the 100 pin version set the IFSRO5 bit to 0 Timer BO 16 Use the IFSR22 bit in the IFSR2 register to select INT8 is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 17 If the PCLK6 bit in the PCLKR register is set to 1 software interrupt number 13 can be changed to CANO 1 error or key input interupt and software interrupt number 14 can be changed to A D interrupt The software interrupt number of key input is changed from 14 to 13 Use the IFSR26 bit in the IFSR2 register to select when selecting CANO 1 error or key input Rev 2 00 Nov28 2005 page 85 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 5 Interrupt Control 10 Interrupt The following describes how to enable disable the maskable interrupts and ho
84. 2 CM03 XCIN XCOUT aa 0 LOW Capacity Select Bit 3 1 HIGH I O port P8 6 P8 7 CM04 Port XC Select Bit 3 1 XCIN diri generation function 4 CMO05 Main Clock Stop Bit 5 a 9 en uii CMO06 Main Clock Division Select 0 CM16 and CM17 valid Bit O 7 10 12 1 Divide by 8 mode System Clock Select 0 Main clock PLL clock Bit 6 11 or on chip oscillator clock 1 Sub clock Write to this register after setting the PRCO bit in the PRCR register to 1 write enable The fC32 clock does not stop During low speed or low power dissipation mode do not set this bit to 1 peripheral clock turned off when in wait mode The CMOS3 bit is set to 1 high while the CM04 bit is set to 0 I O port or when entered to stop mode To use a sub clock set this bit to 1 Also make sure ports P8 6 and P8 7 are directed for input with no pull ups This bit is provided to stop the main clock when the low power dissipation mode or on chip oscillator low power dissipation mode is selected This bit cannot be used for detection as to whether the main clock stopped or not To stop the main clock set bits in the following order 1 Set the CMO7 bit to 1 sub clock select or the CM21 bit in the CM2 register to 1 on chip oscillator select with the sub clock stably oscillating 2 Set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled 3 Set the CMOS5 bit to 1 stop
85. 23 10 1 Timer A 23 10 1 1 Timer A Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TAiMR i 0 to 4 register and the TAi register before setting the TAiS bit in the TABSR register to 1 count starts Always make sure the TAiMR register is modified while the TAIS bit remains 0 count stops regardless whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TAi register However if the counter is read at the same time it is reloaded the value FFFFh is read Also if the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 2 00 Nov28 2005 page 350 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 1 2 Timer A Event Counter Mode The timer remains idle after reset Set the mode count source counter value etc using the TAiMR i 0 to 4 register the TAi register the UDF register the TAZIE TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before se
86. 30 pF X 1 kO X In 1 0 2 Vcc Vcc 6 7 ns NOTE 1 P11 to P14 are only in the 128 pin version Figure 22 3 Port PO to P14 Measurement Circuit 131 NE SAS Rev 2 00 Nov 28 2005 page 302 of 378 REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Switching Characteristics VCC 5V Referenced to VCC 5V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 26 Memory Expansion Mode and Microprocessor Mode for 1 to 3 wait setting and external area access Measuring Standard condition in Max Address output delay time Figure 22 3 Address output hold time refers to BCLK Address output hold time refers to RD Address output hold time refers to WR Chip select output delay time Lk cs Chip select output hold time refers to BCLK LK ALE ALE signal output delay time LK ALE ALE signal output hold time LK RD RD signal output delay time LK RD RD signal output hold time LK WR WR signal output delay time Lk wR WR signal output hold time LK DB Data output delay time refers to BCLK Data output hold time refers to BCLK 9 Data output delay time refers to WR Data output hold time refers to WR 9 taecik ioa HLDA output delay time Parameter
87. 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two cycles Access to the external area indicated by CSi Access to the external area indicated by CSj BCLK Read signal Data bus Address bus Address Y Address CSi CSj Example 3 To access the external area indicated by CSi in the next cycle after accessing the external area indicated by the same CSi The address bus changes state but the chip select signal does not change state Access to the same external area Access to the external area indicated by CSi BCLK Read signal Data bus Address bus Address X Address CSi NOTE 7 Bus Example 2 To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi The chip select signal changes state but the address bus does not change state Access to the internal ROM or internal RAM Access to the external area indicated by CSi BCLK Read signal Data bus Address bus X Address CSi Example 4 Not to access any area nor instruction prefetch generated in the next cycle after accessing the external area indicated by CSi Neither the
88. 4 pin Register TI 7 i Oto2 NOTES Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in clock synchronous serial I O mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 2 00 Nov28 2005 page 160 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 3 lists the functions of the input output pins during clock synchronous serial I O mode Table 15 3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected Table 15 4 lists the P6 4 pin functions during clock synchronous serial I O mode Note that for a period from when the UARTi operation mode is selected to when transfer starts the TXDi pin outputs an H Figure 15 11 shows the transmit receive timings during clock synchronous serial I O mode Table 15 3 Pin Functions When Not Select Multiple Transfer Clock Output Pin Function TXDi Serial Data Output Outputs dummy data when performing reception only P6 3 P6 7 P7 0 RXDi Serial Data Input PD6 2 and PD6 6 bits in PD6 register 0 P6 2 P6 6 P7 1 PD7 1 bit in PD7 register 0 Can be used as an input port when performing transmission only CLKi Transfer Clock Output CKDIR bit
89. 5 X tcyc 25 ns min th ALE AD i 0 5 X tcyc 15 ns min i ADi i i i Bp wem ee bM Memo H Y taZ RD AD D th RD DB id 1 i DE d AD RD eee i tsupenD 997 thBcLk AD i 125ns max TEE 40ns min i A ons 2 5 X tcyc 45 ns max 4ns min ADi ER nsmin i e e BHE no multiplex i td BCLK ALE 25ns max 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r 1 1 1 it 8ns max th BCLK ALE i th BCLK RD Ons min BCLK 1 4 tn BCLK CS ta BCLK cs i IWRCS um min 0 5 X tcyc 10 ns min e d 1 i i i r 1 1 1 1 1 i i i i9 25ns max i i rh 1 1 1 ILL D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i ta BCLK DB th BCLK DB 40ns max 4ns min 1 4 3 n ta AD ALE 0 5 x tcyc 25 ns m in 1 1 1 td DB wR i 1 2 5 X tcyc 40 ns min 1 1 1 1 1 th WR DB 0 5 X tcyc 10 ns min td BCLK AD 25ns max ADi 4 1 EB 2d 00 d 0 o0 gr xc o ng no multiplex T D gt la BCLICALE th BCLK ALE i 25ns max th WR AD 0 5 X tcyc 10 ns min e e 1 td AD WR r MR i 1 1 i 1 f i 1 i 1 i 1 i 1 i 1 1 1 1 gt lt Ons min 1 1 1 i 1 1 i E 1 1 1 1 T 1 1 i 1 1 i 1 i 1 i f i f i f 1 f T f i f i i 1 i th BCLK AD 1 4ns min aoe T i 1 i i i 1 i i lt gt I i i i i i i i i i i 1 ia AN 4ns min i 1 D oss th BCLK wR td BCLK WR Ons
90. 60 ns n is 2 for 2 wait setting 3 for 3 wait setting Rev 2 00 Nov28 2005 page 314 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC z 3 3V Referenced to VCC 3 3V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 31 Timer A Input Counter Input in Event Counter Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAIIN Input LOW Pulse Width Table 22 32 Timer A Input Gating Input in Timer Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 22 33 Timer A Input External Trigger Input in One shot Timer Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 22 34 Timer A Input External Trigger Input in Pulse Width Modulation Mode Standard Symbol Parameter Min Max tw TAH TAiIN Input HIGH Pulse Width 150 tw TAL TAiIN Input LOW Pulse Width 150 Table 22 35 Timer A Input Counter Increment decrement Input in Event Counter Mode Standard Min Max Parameter te up TAiOUT Input Cycle Time tw uPH TAiOUT Input HIGH Pulse Width tw u
91. A1 _UART1 Reception ACK1 UARTO Reception ACKO UART2 Reception ACK2 INT2 wo Timer B1 INT8 l Timer A2 INT7 Timer AO UARTO Transmission NACKO AD Conversion Key Input 9 l DMA1 UART2 Bus Collision Detection Priority of peripheral function interrupts if priority levels are same cani Successful Reception SI O4 INT5 imer B4 UART1 Bus Collision Detection ws O CANO Successful Reception UART2 Transmission NACK2 CANo 1 Error Key Input l CAN1 Successful Transmission SI O3 INT4 imer B3 UARTO Bus Collision Detection Timer B5 SI O5 2 CANO Successful Transmission CANO 1 Wake up KEK EK ERK EEK EEK EEK EERE KEKE EK EKER EK EKER EK EERE EEE ERE Interrupt request level resolution output to clock generating circuit D Figure 8 1 Clock Generating Circuit D Interrupt request accepted Address Match d Oscillation Stop and Re oscillation Detection Watchdog Timer DBC NMI NOTES 1 If the PCLK6 bit in the PCLKR register is set to 1 the priority level of key input interrupt can be changed 2 The SI O5 SI O6 and INT6 to INT8 registers are only in the 128 pin version Figure 10 10 Interrupts Priority Select Circuit Rev 2 00 Nov28 2005 page 93 of 378 RENESAS REJ09B0124 0200 Under development This document is under de
92. AST boo o3 o3 o obo P c sx 5X5 TXEPT bit in UiCO register IR bit in SiTIC register P d Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set TC 16 n 1 fj or 16 n 1 EXT as follows fj frequency of UiBRG count source f1SIO f2SIO f8SIO f32SIO PRYE bit in UIMR register 1 parity enabled fEXT frequency of UiBRG count source external clock STPS bit in UiMR register O 1 stop bit T n value set to UiBRG CRD bit in UiCO register 0 CTS RTS enabled and CRS bit 0 CTS selected UIIRS bit 1 an interrupt request occurs when transmit completed i 0to2 UOIRS bit is bit O in UCON register m U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register 2 Example of Transmit Timing when Transfer Data is 9 bit Long parity disabled two stop bits Transfer clock TE bit in p a UiC1 register Q B Write data to the UiTB register TI bit in UiC1 register x E Transferred from UiTB register to UARTi H E transmit register Start Stop Stop bit bit bit TXDi STAD XP IXDAKOSKDIXDSXOGXO Do Ter sr oo oo3 o3 0X0 0X b bsysse Nsr bo p TXEPT bit in UiCO register aan CLO o TO y y y yY TL IR bit in SiTIC register rl Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set TC 16 n
93. Bus 16 Bits BYTE pin input L Status of External Data Bus Read data Write 1 byte of data to an even address Write 1 byte of data to an odd address Write data to both even and odd addresses Write 1 byte of data to an odd address Read 1 byte of data from an odd address Write 1 byte of data to an even address Read 1 byte of data from an even address H L L H H L Write data to both even and odd addresses L Read data from both even and odd addresses 8 Bits BYTE pin input H Not used Write 1 byte of data Po ce ce 7 2 5 ALE Signal The ALE signal latches the address when accessing the multiplexed bus space Latch the address when the ALE signal falls Figure 7 3 shows the ALE signal address bus and data bus When BYTE pin input H ALE A0 DO to A7 D7 X Address j Data BN a oe Ce cam mt el Not used Read 1 byte of data When BYTE pin input L ALE Ao X Address y A8 to A19 Address A1 D0 to A8 D7 Address Data 1 If the entire CS space is assigned a multiplexed bus these pins function as I O ports NOTE Figure 7 3 ALE Signal Address Bus Data Bus Rev 2 00 Nov 28 2005 page 48 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 7 2 6 RD
94. DAi register to 00h Switching the oscillation driving capacity Set the driving capacity to LOW when oscillation is stable Rev 2 00 Nov28 2005 page 343 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 6 Oscillation Stop Re oscillation Detection Function If the following conditions are all met the following restriction occur in operation of oscillation stop re oscillation stop detection interrupt Conditions e CM20 bit in CM2 register 1 oscillation stop re oscillation stop detection function enabled CM27 bit in CM2 register 1 oscillation stop re oscillation stop detection interrupt e CMO2 bit in CMO register 0 do not stop peripheral function clock in wait mode Enter wait mode from high speed or middle speed mode Restriction If the oscillation of XIN stops during wait mode the oscillation stop re oscillation stop detection interrupt request is generated after the microcomputer is moved out of wait mode without starting immediately Figures 23 1 and 23 2 show the operation timing at oscillation stop re oscillation stop detection XIN fRING 1 INTO input CPU i Oscillation stop re oscillation TTTA operation Weitmede INTO interrupt request XIN stops i Wait mode is released NOTE 1 This clock is generated by the on chip oscillator It is not supplie
95. DO b8 Receive data D8 Nothing is assigned When write set to O b10 b9 When read their contents are 0 ABT Arbitration Lost Not detected Detecting Flag 1 1 Detected No overrun error Overrun error found No framing error Framing error found No parity error Parity error found No error Error found OER _ Overrun Error Flag 2 FER Framing Error Flag 2 PER Parity Error Flag 2 SUM Error Sum Flag 2 1 The ABT bit is set to 0 by writing 0 in a program Writing 1 has no effect 2 When the SMD2 to SMDO bits in the UiMR register 000b serial interface disabled or the RE bit in the UiC1 register 0 reception disabled all of the SUM PER FER and OER bits are set to 0 no error The SUM bit is set to 0 no error when all of the PER FER and OER bits are 0 no error Also the PER and FER bits are set to 0 by reading the lower byte of the UiRB register UARTI Bit Rate Generator Register i 0 to 2 0 0 9 Symbol UOBRG 03A1h U1BRG 03A9h Indeterminate U2BRG 01F9h Indeterminate Assuming that set value n UiBRG 1 Write to this register while serial I O is neither transmitting nor receiving 2 Use the MOV instruction to write to this register 3 Write to this register after setting the CLK1 to CLKO bits in the UiCO register Address After Reset Indeterminate bo Figure 15 5 UOTB to U2TB Registers UORB to U2RB Registers and
96. Data Field XXh 006Bh XXh 006Ch XXh 006Dh XXh poner CANO Message Box 0 Time Stamp 0070h XXh 0071h XXh 0072h CANO Message Box 1 Identifier DLC XXn 0074h XXh 0075h XXh 0076h XXh 0077h XXh 0078h XXh Eu CANO Message Box 1 Data Field XXh 007Bh XXh 007Ch XXh 007Dh XXh corer CANO Message Box 1 Time Stamp s X Undefined NOTES 1 These registers exist only in the 128 pin version 2 The blank area is reserved and cannot be accessed by users Rev 2 00 Nov28 2005 page 20 of 378 REJO9BO0124 0200 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 3 SFR Information 3 Address 0080h 0081h 0082h 0083h CANO Message Box 2 Identifier DLC 0084h 0085h 0086h 0087h 0088h 0089h CANO Message Box 2 Data Field 008Ah 008Bh 008Ch 008Dh 008Eh Ti O08Fh CANO Message Box 2 Time Stamp 0090h 0091h Den CANO Message Box 3 Identifier DLC 0094h 0095h 0096h 0097h 0098h DT CANO Message Box 3 Data Field 009Bh 009Ch 009Dh 009Eh Ti 009Fh CANO Message Box 3 Time Stamp 00A0h 00A1h 00A2h m OOASh CANO Message Box 4 Identifier DLC 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h CANO Message Box 4 Data Field OOABh OOACh OOADh OOAEh E OOAFh CANO Message Box 4 Time Stamp 00B1h OOB2h 00B3h CANO Message Box 5 Identifier DLC 00B4h OO
97. Direction register e j lt P9_3 P9_4 Data bus Port latch 4 a Input to respective peripheral functions TL 3 Analog output o6 D A output enabled Pull up selection Direction register e ji 2 ore Data bus 4 Port latch r Pull up selection Analog input Direction register Le A lt j oTo Oi i Data bus Port latch m Input to respective peripheral functions L 4 Analog input dee Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC Figure20 4 I O Ports 4 Rev 2 00 Nov 28 2005 page 252 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Pull up selection Direction register f lt Data bus Port latch Pull up selection Direction register Output Data bus 4 Port latch E gt QcMev Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC
98. Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt The NMI interrupt is available since the FMRO and FMR1 registers are forcibly reset when the interrupt request is generated Allocate the jump address for the interrupt service routine to the fixed vector table Flash memory rewrite operation is aborted when the NMI interrupt request is generated Execute the rewrite program again after exiting the interrupt service routine 23 19 11 How to Access To set the FMRO1 FMRO2 or FMR11 bit to 1 write 1 after first setting the bit to 0 Do not generate an interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1 Set the bit while an H signal is applied to the NMI pin 23 19 12 Rewriting in User ROM Area EWO0 Mode The supply voltage drops while rewriting the block where the rewrite control program is stored the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten If this error occurs rewrite the user ROM area while in standard serial I O mode or parallel I O mode or CAN I O mode EW1 Mode Avoid rewriting any block in which the rewrite control program is stored 23 19 13 DMA Transfer In EW1 mode do not perform a DMA transfer while the FMROO bit in the FMRO register is set to 0 au
99. Down Down Down count count count count count count Multiply by 4 processing operation timer A3 and timer A4 If the phase relationship is such that TAkIN pin goes H when the input signal on TAKOUT pin is H the timer counts up rising and falling edges on TAkOUT and TAKIN pins If the phase relationship is such that TAkIN pin goes L when the input signal on TAKOUT pin is H the timer counts down rising and falling edges on TAKOUT and TAKIN pins TOUT Av A v V Y Count up all edges Count down all edges TAKIN w Mw Count up all edges Count down all edges Counter initialization by Z phase input timer A3 The timer count value is initialized to 0 by Z phase input i 2to4 j 2 3 k 3 4 NOTE 1 Only timer A3 is selectable Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply by 4 processing operation Rev 2 00 Nov 28 2005 page 122 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Timer Ai Mode Register i 2 2 to 4 When using two phase pulse signal processing Symbol Address After Reset foftfolo TA2MR to TA4MR 0398h to 039Ah 00h j Bit Symbol t X 6s TMODO i MEI RW TMOD1 Operation Mode Select Bit o 4 Event counter mode RW To use t
100. Ecxe Norm ceneste due sets easccra ste a E ene Ee OE AEE dense tenet aaea 241 19 12 Return from Bus Off Function ssssssssssssssesseseeeeeeenneeeen nennen nnns enhn rnnt rennes enne nnns 242 19 13 Time Stamp Counter and Time Stamp Function ssssssssssseseseeeeeeeeenneeen nennen nnn 242 19 T14 Eisten Only MOGO siorse otro epu eec ret Fees ree uia e d desecdade epa d eet ep dx ete EE ea eer deed s deed 242 19 15 Reception and Transmission ssesssssssseeeeeneeenneeeeenn nnne nnne nennen nennen NOAA 243 19 15 41 FHOCODLIOD iioii toi E T uos lege uta of Ene e Qut eaa rtu Eaa 244 19 15 2 TRANSMISSION accetti a deve dessus te esaet ned denotes dug ppret Du pedet ta dete U nu dines 245 19 16 CAN Intert pt uu occur tcr eaea ees ern ae ke Des Dess e exe EY Hd dea etae dra pua in acu en 246 20 Programmable VO POIS uen ethescedancheicuntidentio egenis ds EAEE E ENEA 247 20 1 PDIHegISIOr i petendi nte mette t pter tL TIE 248 20 2 Pi Register PC14 Register reet ete ori ti ERE sua ER Ra erasa eene up ka rana Ree d eM E Ru pna xeu 248 20 9 PURI RESTO e m 248 20 4 PCR REGISIOM uii eiie tuti rer rope oe EEE Ea raar a ee Mad TR ARE Sas ek e ts Gavan 248 21 Fas Memory Vel SIDE usuiokaestusctca ERE ket MH ada RU Ea Do Eua dU DUM DN RS icHCUbNUD x M eM dA Da Dti peo MEUM 260 ANN uario EE 261 22 a D s foro le ioco DDR CE 262 21 2 Functions to Prevent Flash Memory from Rewriting
101. FFFFh n 1 for up count 1 n 1 fordown count n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer overflow or underflow TAiIN Pin Function I O port or count source input TAiOUT Pin Function I O port pulse output or up down count select input Read from Timer Count value can be read by reading the TAi register Write to Timer e When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Select Function e Free run count function Even when the timer overflows or underflows the reload register content is not reloaded to it Pulse output function Whenever the timer underflows or underflows the output polarity of TAiOUT pin is inverted When TAIS bit is set to 0 stop counting the pin outputs a low i 0to4 j i 1 exceptj 4ifi 0 k i 1 exceptk Oifi 4 Rev 2 00 Nov 28 2005 page 120 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM
102. Figure 18 6 COMCTLj and C1MCTLj Registers RemActive bit Function is revised RspLock bit Bit Name is revised NOTE 2 is revised Figure 18 7 COCTLR and C1CTLR Registers upper e LoopBack bit The expression of Function is revised BasicCAN bit The expression of Function is revised Figure 18 7 COCTLR and C1CTLR Registers lower e TSPreScale bit Bit Symbol is revised Bit1 BitO is deleted e TSReset bit The expression of Function is revised RetBusOff bit The expression of Function is revised RXOnly bit The expression of Function is revised Figure 18 8 COSTR and C1STR Registers upper NOTE 1 is deleted Figure 18 8 COSTR and C1STR Registers lower e State LoopBack bit The expression of Function is revised State BasicCAN bit The expression of Function is revised C 1 REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Date Summary Jul 01 2005 Figure 18 11 CORECR C1RECR Registers COTECR C1TECR Registers COTSR C1TSR Registers and COAFS C1AFS Registers CORECR C1RECR Registers NOTE 2 is deleted COTECR C1TECR Registers NOTE 1 is deleted COTSR C1TSR Registers NOTE 1 is deleted 18 15 1 Reception 1 refer to 18 15 2 Transmission is deleted Figure 19 1 I O Ports 1 P7 0 in 4th figure is deleted Figure 19 3 I O Ports 3 P7 0 is added to middle figure Figure 19 6 I O Pins NOTE 1 is deleted Table 21 4 Electrical Characteristics 1 e Measuring Con
103. Function Three Phase Output Buffer Register i i 0 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address a ia IDBO IDB1 01CAh 01CBh mo L9 m Dui u Phase U Phase Output Buffer i Buffer i Write output level DUBi U Phase Output Buffer i 9 Active level ed 1 Inactive level DVi V Phase Output Buffer i RW DVBi V Phase Output Buffer i When read the value of the three RW W Phase Output Buffer i Phase shift register is read RW W Phase Output Buffer i RW Reserved Bit Set to 0 1 Values of the IDBO and IDB1 registers are transferred to the three phase output shift register by a transfer trigger After the transfer trigger occurs the values written in the IDBO register determine each phase output signal first Then the value written in the IDB1 register on the falling edge of timers A1 A2 and A4 one shot pulse determines each phase output signal Dead Time Timer 2 After Reset If setting value is n the timer stops when counting ntimes a count source selected by the INV12 bit in the INVC1 register after start trigger occurs 1 to 255 WO Positive or negative phase which changes from inactive level to active level shifts when the dead time timer stops NOTES 1 Use the MOV instruction to set the DTT register 2 The DTT register is enabled when the INV15 bit in the INVC1 register is set to 0 dead time enabled No dead time can be set when the INV15 bit is set to 1 dead time d
104. I O ports CS1 1 CS1 CS2 0 I O ports CS2 1 CS2 CS3 0 I O ports CS3 1 CS3 PM02 0 WR PMO2 1 3 PM02 0 PMO2 1 I O ports Function as I O ports or peripheral function I O pins NOTES 1 For setting the PMO1 to PMOO bits to 01b memory expansion mode and the PMO5 to PM04 bits to 11b multiplexed bus assigned to the entire CS space apply H to the BYTE pin external data bus is an 8 bit width While the CNVSS pin is held H VCC do not rewrite the PMO5 to PM04 bits to 11b after reset If the PMO5 to PM04 bits are set to 11b during memory expansion mode P3 1 to P3 7 and P4 0 to P4 3 become I O ports in which case the accessible area for each CS is 256 bytes 2 In separate bus mode these pins serve as the address bus 3 If the data bus is 8 bit width make sure the PMO 2 bit is set to 0 RD BHE WR 4 When accessing the area that uses a multiplexed bus these pins output an indeterminate value during a write Rev 2 00 Nov28 2005 page 51 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 7 2 9 External Bus Status When Internal Area Accessed Table 7 7 shows the external bus status when the internal area is accessed
105. Interrupt 4 CMO05 CMO6 CMO7 Bits in CMO register CM10 CM11 Bits in CM1 register NOTES Medium Speed Mode divided by 8 mode High Speed Mode Medium Speed Mode 1 PLL Operation Mode When low power dissipation mode Low Speed Mode Low Power Dissipation Mode On chip Oscillator Mode On chip Oscillator Dissipation Mode Normal Mode 1 Do not go directly from PLL operation mode to wait or stop mode 2 PLL operation mode can be entered from high speed mode Similarly PLL operation mode can be changed back to high speed mode 3 Write to the CMO and CM1 registers per 16 bits with the CM21 bit in the CM2 register 0 on chip oscillator stops Since the operation starts from the main clock after exiting stop mode the time until the CPU operates can be reduced 4 The on chip oscillator clock divided by 8 provides the CPU clock 5 Before entering stop mode be sure to set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled Figure 8 12 State Transition to Stop Mode and Wait Mode Rev 2 00 Nov 28 2005 page 75 of 378 REJ09B0124 0200 131 NESAS WAIT CPU operation stopped instruction Wait Mode Interrupt WAIT instruction Wait Mode Interrupt WAIT instruction 1 Interrupt WAIT instruction Interrupt Wait Mode Wait Mode Under development This document is under development and its contents are subject to change
106. Interrupt Register i i 0 to 3 Address After Reset b19 b16 b15 b8 0012h to 0010h X00000h b3 bO b7 bo B7 0016h to 0014h X00000h 01BAh to 01B8h X00000h O1BEh to 01BCh X00000h Bit Symbol Function Setting Range i Address setting register for address EH E p g 00000h to FFFFFh Nothing is assigned When write set to 0 b23 b20 When read their contents are indeterminate potter eee eee eee Figure 10 16 AIER Register AIER2 Register and RMADO to RMAD3 Registers Rev 2 00 Nov 28 2005 page 100 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 Watchdog Timer 11 Watchdog Timer The watchdog timer is the function of detecting when the program is out of control Therefore we recommend using the watchdog timer to improve reliability of a system The watchdog timer contains a 15 bit counter which counts down the clock derived by dividing the CPU clock using the prescaler Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register The PM12 bit can only be set to 1 watchdog timer reset Once this bit is set to 1 it cannot be set to 0 watchdog timer interrupt in a program Refer to 5 3 Watchdog Timer Reset for deta
107. M16C 6NM Hardware Manual Date Summary Nov 28 2005 12 1 3 Effect of Software Wait 3rd to 9th lines is moved from next section of 12 1 2 12 1 4 Effect of RDY Signal is added Table 12 2 DMA Transfer Cycles is revised Table 12 3 Coefficient j k is revised 12 5 Channel Priority and DMA Transfer Timing Last sentence Refer to is added Figure 13 12 TAOMR to TA4MR Registers in PWM Mode b2 is revised from 1 to blank Figure 14 1 Three Phase Motor Control Timer Function Block Diagram is revised Figure 14 2 INVCO Register NOTES 5 and 6 are revised Figure 15 5 UOBRG to U2BRG Registers lower NOTE 3 is added Figure 15 6 UOCO to U2CO Registers lower NOTE 5 is added Table 15 9 Example of Bit Rates and Settings 20 MHz and NOTE 1 are added Figure 15 37 SiC Register upper NOTE 7 is added Figure 15 37 SIBRG Register middle NOTE 4 is added Figure 16 1 A D Converter Block Diagram e ADGSEL1 to ADGSELO righit lower is revised from 10b to 11b NOTE 1 is added 16 2 6 Output Impedance of Sensor under A D Conversion e 10th line f XIN is revised to f bAD Figure 16 10 Analog Input Pin and External Sensor Equivalent Circuit e fAD is revised to dAD Figure 17 1 D A Convertoer Block Diagram is revised Figure 17 2 DAO and DA1 Registers Setting Range is added Figure 17 3 D A Converter Equivalent Circuit NOTE 2 is added Figure 18 3 CRC Calculation is partly revised Figure 19 11 COTECR C1TECR Registers 2nd
108. Mask ROM Consumption 21mA f BCLK 24MHz PLL operation no division Flash Memory 23mA f BCLK 24MHz 21mA f BCLK 20MHz PLL operation no division PLL operation no division Mask ROM Flash Memory 3pA f BCLK 32kHz Wait mode Oscillation capacity Low 0 8pA Stop mode Topr 25 C Flash Memory Version Program Erase Supply Voltage 3 0 0 3V or 5 0 0 5V 5 0 0 5V Program and Erase Endurance 100 times l O Characteristics I O Withstand Voltage 5 0V Output Current 5mA Operating Ambient Temperature 40 to 85 C T version 40 to 85 C V version 40 to 125 C option Device Configuration CMOS high performance silicon gate Package NOTES 1 PC bus is a registered trademark of Koninklijke Philips Electronics N V 2 IEBus is a registered trademark of NEC Electronics Corporation option All options are on request basis Rev 2 00 Nov28 2005 page 3 of 378 REJ09B0124 0200 128 pin plastic mold LQFP 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 3 Block Diagram Figure 1 1 shows a block diagram of M16C 6N Group M16C 6NK M16C 6NM Port PO Port P1 Port P2 Port P3 Port P4 Port P5 1 Overview IT Internal peripheral functions Timer 16 bits Output timer A 5 Input timer B 6 Three phas
109. NOT OR XOR Jump ADJNZ SBJNZ Rev 2 00 Nov28 2005 page 338 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 2 External Bus Normal ver only When resetting CNVSS pin with H input contents of internal ROM cannot be read out Rev 2 00 Nov28 2005 page 339 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 3 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock Rev 2 00 Nov28 2005 page 340 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met Refer to 22 Electrical characteristics Rev 2 00 Nov28 2005 page 341 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 5 Power Control When exiting stop mode by hardware reset set RESET pin to L until a main clock oscillation is stabilized e
110. NOTE 1 Not available memory expansion and microprocessor modes in T V ver 20 3 PURj Register 100 pin Version j 0 to 2 128 pin Version j 0 to 3 Figures 20 9 and 20 10 show the PURj register The PURj register bits can be used to select whether or not to pull the corresponding port high in 4 bit unit The port selected to be pulled high has a pull up resistor connected to it when the direction bit is set for input mode However the pull up control register has no effect on PO to P3 P4 0 to P4 3 and P5 during memory expansion and microprocessor modes Although the register contents can be modified no pull up resistors are connected When using the ports P11 to P14 set the PUR37 bit in the PURS register to 1 P11 to P14 are usable NOTE 1 Not available memory expansion and microprocessor modes in T V ver 20 4 PCR Register Figure20 11 shows the PCR register When the P1 register is read after setting the PCRO bit in the PCR register to 1 the corresponding port latch can be read no matter how the PD1 register is set Tables 20 2 and 20 3 list an example connection of unused pins Figure20 12 shows an example connection of unused pins Rev 2 00 Nov28 2005 page 248 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK PO Oto PO 7 P2 0to P2 7 2 P3 0to P3 7 P4 0toP4 7 P5 0toP5 4 P5 6 P11 2toP11 4
111. O When read its content is indeterminate 1 When using multiple transfer clock output pins make sure the following conditions are met The CKDIR bit in the U1MR register 0 internal clock UARTi Special Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Address After Reset vou esi O1EFh 01F3h 01F7h X0000000b 12C Mode Select Bit Other than 12C mode 12C mode Arbitration Lost Detecting Flag Control Bit Update per bit Update per byte Bus Busy Flag STOP condition detected START condition detected busy Reserved Bit S et to 0 Bus Collision Detect Sampling Clock Select Bit Rising edge of transfer clock Underflow signal of timer Aj 2 Auto Clear Function Select Bit of Transmit Enable Bit No auto clear function Auto clear at occurrence of bus collision Transmit Start Condition Select Bit Not synchronized to RXDi Synchronized to RXDi 3 Nothing is assigned When write set to 0 When read its content is indeterminate 1 The BBS bit is set to 0 by writing O in a program Writing 1 has no effect 2 Underflow signal of timer A3 in UARTO underflow signal of timer A4 in UART1 underflow signal of timer AO in UART2 3 When a transfer begins the SSS bit is set to 0 not synchronized to RXDi Figure 15 8 UCON Register and UOSMR to U2SMR Registers Rev 2 00 Nov 28 2005 page 156 of 378 RENESAS REJ09B0124 0200 Un
112. Operation Timing When Measuring Pulse Period Count source Measurement pulse E Transfer Transfer Transfer Transfer pg indeterminate measured value measured w measured value a A value 1 value 1 Reload register counter transfer timing a NOTE 1 NOTE 1 NOTE NOTE 1 AS Mae S ur Timing at which counter reaches 0000h TBiS bit Q IR bit in qr TBIIC register g Set to 0 upon accepting an interrupt request or by MR3 bit in males writing in program TBiMR register g The TBOS to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to bit 5 to bit 7 in the TBSR register iz0to5 NOTES 1 Counter is initialized at completion of measurement 2 Timer has overflown 3 This timing diagram is for the case where the MR1 to MRO bits in the TBiMR register are 10b measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse Figure 13 22 Operation Timing When Measuring Pulse Width Rev 2 00 Nov28 2005 page 137 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function 14 Three Phase Motor Control Timer Function Timers A1 A2 A4 and B2 can be used to output three phase motor drive waveforms Table 1
113. RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Main clock PLL clock or on chip oscillator clock UARTO RXDO O 4 Clock sou CLK1 to CLKO 00h rce selection f1SIO or 281000 t8Sio 9 Th 1o N o t32sio 10h RXD polarity reversing circuit CKDIR Internal f2SIO PCLK1 fISIO 1 8 EFi A ol nisio orf2SIO Lo f8SIO f32SIO 15 Serial Interface UOBRG register UART reception SMD2 to SMDO 010 100 101 110 Clock synchronous oi type 001 Reception control circuit ro d 1 n0 1 UART transmission d nO 010 100 101 110 External lock synchronous lype i o 001 Clock synchronous type when internal clock i selected Transmission control circuit d u o CKPOL CLK Clock synchronous type when external clock is selected Clock synchronous type when internal clock is selected CKDIR CLKO O bversing circuit CTS RTS selected 4 CTS RTS disabled CTS0 Cy 1 2 RTSO nerd VIS CTS RTS disabled 0 CTSo from UART1 5 nO Values set to the UOBRG register PCLK1 Bit in PCLKR register SMD2 to SM
114. RecState 1 Lost in arbitration TrmState RecState Bits in CiISTR register i 0 1 Figure 19 13 Sub Modes of CAN Operation Mode 19 5 3 CAN Sleep Mode The CAN sleep mode is activated by setting the Sleep bit to 1 and the Reset bit to 0 in the CiCTLR register It should never be activated from the CAN operation mode but only via the CAN reset initialization mode Entering the CAN sleep mode instantly stops the clock supply to the module and thereby reduces power dissipation 19 5 4 CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 or CCLK7 bit in the CCLKR register to 1 It should never be activated but only via the CAN sleep mode Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and thereby reduces power dissipation Rev 2 00 Nov28 2005 page 235 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 5 5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification When returning to the CAN operation mode from the bus off state the module has the following two cases In this time the value of any CAN registers except CiSTR CIRECR and CiTECR registers does not change 1 When 11 consecutive recessive bits are detected 128 times The mod
115. SI O3 and INT4 share the vector and interrupt control register When using CAN1 successful transmission or SI O3 interrupt set the IFSR16 bit to 0 CAN1 successful transmission SI O3 When using INT4 interrupt set the IFSR16 bit to 1 INT4 During memory expansion and microprocessor modes when the data bus is 16 bit width BYTE pin is L set this bit to 0 CAN1 successful transmission SI O3 Not available memory expansion and microprocessor modes in T V ver 3 When setting this bit to 0 CAN1 successful transmission SI O3 make sure the IFSROO bit in the IFSRO register is set to 0 CAN1 successful transmission or 1 SI O3 And make sure the POL bit in the C1TRMIC and S3IC registers are set to 0 falling edge 4 CAN1 successful recception SI O4 and INT5 share the vector and interrupt control register When using the CAN1 successful reception or SI O4 interrupt set the IFSR17 bit to 0 CAN1 successful reception SI O4 When using INT5 interrupt set the IFSR17 bit to 1 INT5 During memory expansion and microprocessor modes when the data bus is 16 bit width BYTE pin is L set this bit to 0 CAN1 successful reception SI O4 Not available memory expansion and microprocessor modes in T V ver 5 When setting this bit to 0 CAN1 successful reception SI O4 make sure the IFSRO3 bit in the IFSRO register is set to 0 CAN1 successful reception or 1 SI O4 And make sure the POL bit in the C1T
116. SMD2 to SMDO bits in the UIMR register 000b serial interface disabled Second data transfer to the UiRB register rising edge of SCLi 9th bit First data transfer to the UiRB register falling edge of SCLi 9th bit See Figure 15 26 STSPSEL Bit Functions See Figure 15 24 Transfer to UiRB Register and Interrupt Timing When using UARTO be sure to set the IFSRO6 bit in the IFSRO register to 1 cause of interrupt UARTO bus collision detection When using UART1 be sure to set the IFSRO7 bit in the IFSRO register to 1 cause of interrupt UART1 bus collision detection Rev 2 00 Nov28 2005 page 178 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 1 IICM2 0 ACK and NACK interrupts CKPH 0 no clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi sDai X D7 X D6 X Ds X D4 X D3 X D2 X D1 X DO X D amp ACK NACK j ACK interrupt DMA1 request NACK interrupt Transfer to UiRB register b15 b9 b8 b7 Ds D7 De Ds D4 D3 D2 UiRB register 2 IICM2 0 CKPH 1 clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
117. SRO 022 t0 00200 indeterminate SAR1 0032h to 0030h Indeterminate Set the source address of transfer 00000h to FFFFFh RW Nothing is assigned When write set to 0 When read their contents are 0 1 If the DSD bit in the DMiCON register is 0 fixed this register can only be written to when the DMAE bit in the DMiCON register is 0 DMA disabled If the DSD bit is 1 forward direction this register can be written to at any time If the DSD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read DMAi Destination Pointer i 0 1 b23 b19 b16 b15 b8 b3 b0 b7 bO b7 bo Symbol Address After Reset DARO 0026h to 0024h Indeterminate DAR1 0036h to 0034h Indeterminate Set the destination address of transfer 00000h to FFFFFh RW Nothing is assigned When write set to 0 When read their contents are 0 1 If the DAD bit in the DMiCON register is 0 fixed this register can only be written to when the DMAE bit in the DMiCON register is 0 DMA disabled If the DAD bit is 1 forward direction this register can be written to at any time If the DAD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read DMAi Transfer Counter i 0 1 b8 bO b7 bO Symbol Address After Reset TCR1 0039h
118. Set the MRO bit in the TAiMR register i O to 4 to 0 pulse is not output to use the timer A to exit stop mode e In the main clock oscillation or low power dissipation mode set the CM02 bit in the CMO register to 0 do not stop peripheral function clock in wait mode before shifting to stop mode e When entering wait mode insert a JMP B instruction before a WAIT instruction Do not execute any instructions which can generate a write to RAM between the JMP B and WAIT instructions Disable the DMA transfers if a DMA transfer may occur between the JMP B and WAIT instructions After the WAIT instruction insert at least 4 NOP instructions When entering wait mode the instruction queue roadstead the instructions following WAIT and depending on timing some of these may execute before the microcomputer enters wait mode Program example when entering wait mode Program Example JMP B L1 Insert JMP B instruction before WAIT instruction L1 FSET l WAIT Enter wait mode NOP More than 4 NOP instructions NOP NOP NOP e When entering stop mode insert a JMP B instruction immediately after executing an instruction which sets the CM10 bit in the CM1 register to 1 and then insert at least 4 NOP instructions When entering stop mode the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to 1 all clock stops and some of these may execute before the microcomputer
119. Start condition detection or stop condition detection See Table 15 13 STSPSEL Bit Functions Factor of Interrupt Number 15 17 and 19 0 9 UARTI transmission Transmission started or completed selected by UilRS UARTI transmission Falling edge of SCLi next to the 9th bit UARTI transmission Rising edge of SCLi 9th bit No acknowledgment detection NACK Rising edge of SCLi 9th bit Factor of Interrupt Number 16 18 and 20 1 6 UARTI reception When 8th bit received CKPOL 0 rising edge CKPOL 1 falling edge UARTi reception Falling edge of SCLi 9th bit Acknowledgment detection ACK Rising edge of SCLi 9th bit Timing for Transferring Data from UART Reception Shift Register to UiRB Register CKPOL 0 rising edge CKPOL 1 falling edge Falling and rising edges of SCLi 9th bit Falling edge of SCLi 9th bit Rising edge of SCLi 9th bit UARTi Transmission Output Delay Not delayed Delayed Functions of P6 3 P6 7 and P7 0 Pins TXDi output SDAi input output Functions of P6 2 P6_6 and P7 1 Pins RXDi input SCLi input output Functions of P6_1 P6_5 and P7_2 Pins CLKi input or output selected Cannot be used in I C mode Noise Filter Width 15 ns 200 ns Read RXDi and SCLi Pins Levels Possible when the corresponding port direction bit 0 Always possible no matter how the corresponding port direction bit is set
120. TAIMR register 1 trigger selected by the TAITGH and TAITGL bits Figure 13 14 Example of 8 bit Pulse Width Modulator Operation Rev 2 00 Nov28 2005 page 129 of 378 RENESAS REJ09B0124 0200 13 Timers Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 2 Timer B Figure 13 15 shows a block diagram of the timer B Figures 13 16 and 13 17 show the timer B related registers Timer B supports the following three modes Use the TMOD1 and TMODO bits in the TBiMR register i 0 to 5 to select the desired mode Timer mode The timer counts an internal count source Event counter mode The timer counts pulses from an external device or over flows or underflows of other timers Pulse period pulse width measuring mode The timer measures pulse period or pulse width of an external signal High order Bits of Data Bus Select clock source TCK1to TCKO oo Timer Low order Bits of Data Bus 10 Pulse period measurement mode TMOD1 to TMODO pulse width measurement mode L d High ord ow order igh oraer 8 bits 8 bits 1 Reload Register 01 Event counter Counter Counter Reset Circuit TCK1 to TCKO TMOD1 to TMODO Bits in TBiMR register TBi Addresses TBj TBiS Bit in TABSR register or TBSR register Timer BO 0391h 0390h Timer B2 Timer B1 0393h 0392h Timer BO iz0to5 Timer B2 0395h 0394h Timer B1 j i 1 except j 2 when i
121. Table 22 17 Timer A Input Counter Increment decrement Input in Event Counter Mode Standard Min Max Parameter te up TAiOUT Input Cycle Time tw uPH TAiOUT Input HIGH Pulse Width tw uPL TAiOUT Input LOW Pulse Width tsu UP TIN TAiOUT Input Setup Time thcTIN uP TAiOUT Input Hold Time Table 22 18 Timer A Input Two phase Pulse Input in Event Counter Mode Standard Min Max Parameter tetta TAiIN Input Cycle Time tsuctain Taout TAIOUT Input Setup Time tsurAoUr TAIN TAilN Input Setup Time Rev 2 00 Nov28 2005 page 300 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC 25V Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 19 Timer B Input Counter Input in Event Counter Mode Standard Min Max Parameter TBilN Input Cycle Time counted on one edge TBilN Input HIGH Pulse Width counted on one edge TBilN Input LOW Pulse Width counted on one edge TBilN Input Cycle Time counted on both edges TBilN Input HIGH Pulse Width counted on both edges TBilN Input LOW Pulse Width counted on both edges Table 22 20 Timer B Input Pulse Period Measurement Mode Standard Min Max Parameter TBilN Inpu
122. U flag is 1 The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is configured with three bits for specification of up to eight processor interrupt priority levels from level 0 to level 7 If a requested interrupt has priority greater than IPL the interrupt request is enabled 2 8 10 Reserved Area When white to this bit write 0 When read its content is indeterminate Rev 2 00 Nov28 2005 page 17 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 3 Memory 3 Memory Figure 3 1 shows a memory map of the M16C 6N Group M16C 6NK M16C 6NM The address space extends the 1 Mbyte from address 00000h to FFFFFh The internal ROM is allocated in a lower address direction beginning with address FFFFFh For example a 512 Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh As for the flash memory version 4 Kbyte space block A exists in OFOOOh to OFFFFh 4 Kbyte space is mainly for storing data In addition to storing data 4 Kbyte space also can store programs The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh Therefore store the start address of each interrupt routine here The internal RAM is allocated in an upper addre
123. XXh Port P9 Register XXh Port P8 Direction Register 00X00000b Port P9 Direction Register 00h Port P10 Register XXh Port P11 Register 1 XXh Port P10 Direction Register 00h Port P11 Direction Register 1 00h Port P12 Register 1 XXh Port P13 Register 1 XXh Port P12 Direction Register 1 00h Port P13 Direction Register 1 00h Pull up Control Register 0 00h 00000000b 1 Pull up Control Register 1 00000010b Pull up Control Register 2 00h Port Control Register 00h X Undefined NOTES 1 At hardware reset the register is as follows 00000000b where L is input to the CNVSS pin 00000010b where H is input to the CNVSS pin CNVSS pin H is not available in T V ver At software reset watchdog timer reset and oscillation stop detection reset the register is as follows 00000000b where the PMO1 to PMOO bits in the PMO register are 00b single chip mode 00000010b where the PMO1 to PMOO bits in the PMO register are 01b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver 2 These registers exist only in the128 pin version 3 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov28 2005 page 34 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 5 Reset 5 Reset Hardware reset software reset watchdog timer reset
124. address bus nor the chip select signal changes state between these two cycles Access to the external No access area indicated by CSi BCLK Read signal Data bus Address bus CSi 1 These examples show the address bus and chip select signal when accessing areas in two successive cycles The chip select bus cycle may be extended more than two cycles depending on a combination of these examples Shown above is the case where separate bus is selected and the area is accessed for read without wait states i 0 to 3 j 0 to 3 not including i however Figure 7 2 Example of Address Bus and CSi Signal Output Rev 2 00 Nov28 2005 page 47 of 378 REJ09B0124 0200 34 NE ESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 2 4 Read and Write Signals 7 Bus When the data bus is 16 bit width the read and write signals can be chosen to be a combination of RD WR and BHE or a combination of RD WRL and WRH by using the PMO2 bit in the PMO register When the data bus is 8 bit width use a combination of RD WR and BHE Table 7 3 shows the operation of RD WRL and WRH signals Table 7 4 shows the operation of RD WR and BHE signals Table 7 3 Operation of RD WRL and WRH Signals Data Bus Width 16 Bits BYTE pin input L Table 7 4 Operation of RD WR and BHE Signals Data Bus Width RD WR BHE AO Status of External Data
125. also the clock source for the peripheral function clocks If the sub clock is activated fC32 can be used as the count source for timers A and B When the operation mode is returned to the high and medium speed modes set the CMO6 bit in the CMO register to 1 divide by 8 mode 8 4 1 7 On chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on chip oscillator mode The CPU clock can be selected like in the on chip oscillator mode The on chip oscillator clock is the clock source for the peripheral function clocks If the sub clock is activated fC32 can be used as the count source for timers A and B Table 8 3 lists the setting clock related bit and modes Table 8 3 Setting Clock Related Bit and Modes CM2 Register CM1 Register CMO Register CM21 CM11 CM17 CM16 CMO06 CMO05 PLL Operation Mode High Speed Mode Medium Divide by 2 Speed Divide by 4 Mode bDivide by 8 Divide by 16 Low Speed Mode Low Power Dissipation Mode On chip Divide by 1 00b OscillatonDivide by 2 01b Mode pDivide by 4 10b Divide by 8 Divide by 16 11b On chip Oscillator NOTE 2 NOTE 2 Low power Dissipation Mode 0 or 1 NOTES 1 When the CMOB bit is set to 1 main clock turned off in low speed mode the mode goes to low power dissipation mode and the CMO6 bit is set to 1 divide by 8 mode simultaneously 2 The di
126. applied to the CTSi RTSi i 0 to 2 pin Transmit and receive operation begins when the CTSi RTSi pin is held L If the L signal is switched to H during a transmit or receive operation the operation stops before the next data When the RTS function is used the CTSi RTSi pin outputs on L signal when the microcomputer is ready to receive The output level becomes H on the first falling edge of the CLKi pin e CRD bit in UiCO register 1 CTS RTS function disabled CTSi RTSi pin is programmable I O function CRD bit 0 CRS bit in UiCO register 0 CTS function is selected CTSi RTSi pin is CTS function e CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 15 1 1 8 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6 0 pin and accepts as input the CTSO from the P6 4 pin To use this function set the register bits as shown below e CRD bit in UOCO register 0 enables UARTO CTS RTS e CRS bit in UOCO register 1 outputs UARTO RTS e CRD bit in U1CO register 0 enables UART1 CTS RTS CRS bit in U1CO register 0 inputs UART1 CTS RCSP bit in UCON register 1 inputs CTSO from the P6_4 pin e CLKMD1 bit in UCON register 0 CLKS1 not used Note that when using the CTS RTS separate function UART1 CTS RTS separate function cannot be used Figure 15 16 shows CTS RTS separate function usage Microcomputer TXDO P6 3 RXD
127. auto program and to 1 ready when an auto program operation is completed After the completion of an auto program operation the FMROG6 bit in the FMRO register indicates whether or not the auto program operation has been completed as expected Refer to 21 3 8 Full Status Check An address that is already written cannot be altered or rewritten Figure 21 8 shows a flow chart of the program command programming The lock bit protects each block from being programmed inadvertently Refer to 21 3 6 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EWO mode the microcomputer enters read status register mode as soon as an auto program operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto program operation starts It is set to 1 when auto program operation is completed The microcomputer remains in read status register mode until the read array command is written After completion of an auto program operation the status register indicates whether or not the auto program operation has been completed as expected Write the command code xx40h to an address to be the written Write data to an address to be written Full status check Program operation is completed NOTE 1 Write the command code and data to even addresses Figure 21 8 Program Command Rev 2 00 Nov28 2005 page 274
128. b4 TASTGL 0 0 Selects an input to the TASIN pin 1 Timer A3 Event Trigger o 1 Selects TB2 2 Select Bit 1 0 Selects TA2 2 1 1 Selects TA4 2 TA4TGL Timer A4 Event T rigger Set to 01b TB2 underflow before TA4TGH Select Bit using a U phase output control circuit port direction bit to 0 input mode TASTGH Symbol Address e Haa TABSR 0380h ED ee mm Im TAOS Timer A0 Count Start Flag 0 Stops counting TA1S Timer A1 Count Start Flag 1 Starts counting TA2S Timer A2 Count Start Flag TASS Timer A3 Count Start Flag Figure 14 7 TRGSR Register and TRBSR Register Rev 2 00 Nov28 2005 page 145 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Timer Ai Mode Register i 1 2 4 b7 b6 b5 b4 b3 b2 bi BED BDRD n Address Afer Reset TA1MR TA2MR TA4MR 0397h 0398h 039Ah stl See 1 TMODO TMODO Set to 10b one shot timer mode Operation Mode with the three phase motor ae TMOD1 Select Bit timer function MRO Pulse Output Function Set to 0 with the three phase ca Select Bit control timer function External Trigger Set to 0 with the three phase moto rw Select Bit control timer function Set to 1 selected by the Trigger Select Bit TRGSR Red with the three phase RW motor control timer function Set to
129. becomes L by reading data in an external memory space The BHE signal becomes L by accessing an odd address Select WR BHE and RD for an external 8 bit data bus ALE is a signal to latch the address While the HOLD pin is held L the microcomputer is placed in a hold state In a hold state HLDA outputs a L signal Output 1 0 While applying a L signal to the RDY pin the microcomputer is placed in a wait state Input Output 1 In this manual hereafter VCC refers to VCC1 unless otherwise noted 2 Connect to VSS in T V ver 3 Not available the bus control pins in T V ver Rev 2 00 Nov 28 2005 page 13 of 378 REJO9BO0124 0200 31 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 10 Pin Description 100 pin and 128 pin Versions 2 Signal Name Main clock input Pin Name XIN Main clock output XOUT Description I O pins for the main clock oscillation circuit Connect a ceramic resonator or crystal oscillator between XIN and XOUT To use the external clock input the clock from XIN and leave XOUT open Sub clock input XCIN Sub clock output XCOUT I O pins for a sub clock oscillation circuit Connect a crystal oscillator between XCIN and XCOUT To use the external clock input the cl
130. being executed refer to 10 5 7 Saving Registers The value of the PC that is saved to the stack area is not the correct return address Therefore follow one of the methods described below to return from the address match interrupt Rewrite the content of the stack and then use the REIT instruction to return Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return Table 10 6 shows the value of the PC that is saved to the stack area when an address match interrupt request is accepted Table 10 7 shows the relationship between address match interrupt sources and associated registers Note that when using the external bus in 8 bit width no address match interrupts can be used for external areas External bus is available Nomal ver only Figure 10 16 shows the AIER AIER2 and RMADO to RMADS registers Table 10 6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted Instruction at Address Indicated by RMADi Register Value of PC that is Saved to Stack Area 16 bit operation code Address indicated by RMADi Instruction shown below among 8 bit operation code instructions register 2 ADD B S IMM8 dest SUB B S IMM8 dest AND B S IMM8 dest OR B S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMMB8 dest PUSHM src POPM dest JM
131. bit changes to 0 from 1 h CLKi Receive data is taken in RXDi Transferred from UARTI receive register Read out from the UiRB register q RI bit in to the UiRB register UiC1 register o IR bit in n i SiRIC register g MEE dp MENU 4 Set to 0 when interrupt request is accepted or set to 0 in a program The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input as follows to the CLKi pin before receiving data is high CKDIR bit in UiMR register 1 external clock D e TE bit in UiC1 register 1 transmission enabled CRD bit in UiCO register 0 CTS RTS enabled CRS bit 1 RTS selected RE bit in UiC1 register 1 reception enabled e CKPOL bit in UiCO register O transmit data output at the falling edge and receive Write dummy data to the UiTB register data taken in at the rising edge of the transfer clock fEXT frequency of external clock Figure 15 11 Transmit and Receive Operation Rev 2 00 Nov28 2005 page 162 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 1 1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I O mode follow the procedures below Resetting the UiRB register i 0 to 2
132. bit of the next data e Framing error 9 This error occurs when the number of stop bits set is not detected Parity error During reception if a parity error is detected parity error signal is output from the TXD2 pin During transmission a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs Error sum flag This flag is set to 1 when any of the overrun framing and parity errors is encountered 1 If an overrun error occurs the value of the U2RB register will be indeterminate The IR bit in the S2RIC register does not change 2 A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 transmit is completed and U2ERE bit to 1 error signal output after reset Therefore when using SIM mode set the IR bit to O interrupt not requested after setting these bits 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register Rev 2 00 Nov28 2005 page 191 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 18 Registers to Be Used and Settings in SIM Mode Register 0 to 7 Set transmission data 0 to 7 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate S
133. bit to 0 Timer A2 When using INT7 interrupt set the IFSR20 bit to 1 INT7 The INT7 interrupt is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 3 Timer A3 and INT6 share the vector and interrupt control register When using the timer A3 interrupt set the IFSR21 bit to 0 Timer A3 When using INT6 interrupt set the IFSR21 bit to 1 INT6 The INT6 interrupt is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 4 Timer B1 and INT8 share the vector and interrupt control register NN When using the timer B1 interrupt set the IFSR22 bit to 0 Timer B1 When using INT8 interrupt set the IFSR22 bit to 1 INT8 The INT8 interrupt is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 5 When the PCLK6 bit in the PCLKR register 1 CANO 1 error and key input share the vector and interrupt control register When using the CANO 1 error interrupt set the IFSR26 bit to 0 CANO 1 error When using the key input interrupt set the IFSR26 bit to 1 key input 6 When using the INT6 to INT8 interrupts set these bits after settig the PU37 bit in the PUR3 register to 1 Figure 10 13 IFSR2 Register Rev 2 00 Nov 28 2005 page 97 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt
134. branches to the address set in the corresponding interrupt vector Figure 10 2 shows the interrupt vector Vector address L Low order address Middle order address High order address Vector address H Figure 10 2 Interrupt Vector 10 4 1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh Table 10 1 lists the fixed vector tables In the flash memory version of microcomputer the vector addresses H of fixed vectors are used by the ID code check function For details refer to 21 2 Functions to Prevent Flash Memory from Rewriting Table 10 1 Fixed Vector Tables Vector table Addresses sa rt Undefined Instruction UND instruction FFFDChto FFFDFh M16C 60 M16C 20 M16C Tiny Overflow INTO instruction FFFEOh to FFFES3h Series Software Manual BRK Instruction FFFE4h to FFFE7h Address Match FFFE8h to FFFEBh 10 10 Address Match Interrupt Single Step FFFEChto FFFEFh Oscillation Stop and Re oscillation Detection FFFFOh to FFFF3h 8 Clock Generating Circuit Watchdog Timer 11 Watchdog Timer DBC FFFF4h to FFFF7h NMI FFFF8h to FFFFBh 10 7 NMI Interrupt Reset FFFFCh to FFFFFh 5 Reset NOTES 1 Do not normally use this interrupt because it is provided exclusively for use by development tools 2 If the contents of address FFFE7h is FFh program execution starts from the address shown by the vector in the relocatable vector table
135. by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level Non Maskable Interrupt An interrupt which cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level Rev 2 00 Nov28 2005 page 81 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 2 Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts 10 2 1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction 10 2 2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to 1 the operation resulted in an overflow The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB 10 2 3 BRK Interrupt A BRK interrupt occurs when executing the BRK instruction 10 2 4 INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction Software interrupt Nos 0 to 63 can be specified for the INT instruction Because software interrupt Nos 1 to 31 are assigned to peripheral function interrupts the same interrupt routine as for peripheral function int
136. clock oscillation circuit On chip oscillator PLL frequency synthesizer 8 Clock Generating Circuit Table 8 1 lists the clock generating circuit specifications Figure 8 1 shows the clock generating circuit Figures 8 2 to 8 8 show the clock related registers Table 8 1 Clock Generating Circuit Specifications Use of Clock Main Clock Oscillation Circuit CPU clock source Peripheral function clock source Sub Clock Oscillation Circuit CPU clock source Clock source of Timer A B On chip Oscillator CPU clock source Peripheral function clock source CPU and peripheral function clock sources when the main clock stops oscillating PLL Frequency Synthesizer CPU clock source Peripheral function clock source Clock Frequency 0 to 16 MHz 32 768 kHz About 1 MHz 16 MHz 20 MHz 24 MHz Usable Oscillator eCeramic oscillator Crystal oscillator Crystal oscillator Pins to Connect Oscillator XIN XOUT XCIN XCOUT Oscillation Stop and Re Oscillation Detection Function Available Available Available Available Oscillation Status After Reset Oscillating Stopped Stopped Stopped Other NOTE Externally derived clock can be input 1 24 MHs is available Normal ver only Rev 2 00 Nov28 2005 page 56 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its conte
137. condition is generated by setting the RSTAREQ bit in the UISMR4 register to 1 start A stop condition is generated by setting the STPREQ bit in the UiISMR4 register to 1 start The output procedure is described below 1 Set the STAREQ bit RSTAREQ bit or STPREQ bit to 1 start 2 Set the STSPSEL bit in the UISMR4 register to 1 output Table 15 13 and Figure 15 26 show the functions of the STSPSEL bit Rev 2 00 Nov28 2005 page 180 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 13 STSPSEL Bit Functions Function STSPSEL Bit 0 STSPSEL Bit 1 Output of SCLi and SDAi Pins Output of transfer clock and Output of a start stop condition data according to the STAREQ Output of start stop condition is RSTAREQ and STPREQ bits accomplished by a program using ports not automatically generated in hardware Start Stop Condition Interrupt Start stop condition detection Finish generating start stop condition Request Generation Timing 1 When slave CKDIR bit 1 external clock STSPSEL bit o SCLi ist 2nd 3rd 4th 5th 6th 7th 8th 9th bit SDAi l Start condition Stop condition detection interrupt detection interrupt 2 When master CKDIR bit 0 internal clock CKPH bit 1 clock delayed STSPSEL bit Setto 1 in Set to 0 in Set to 1
138. corresponding bit in Port Pi 4 Bit this register RW Port Pi 5 Bit 0 L level RW Port Pi 6 Bit Pelee RW Port Pi_7 Bit RW b7 b6 b5 b4 b3 b2 bi bo 1 Since P7_1 and P9_1 are N channel open drain ports the data is high impedance 2 During memory expansion and microprocessor modes the Pi register for the pins functioning as bus control pins AO to A19 DO to D15 CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLk cannot be modified Not available memory expansion and microprocessor modes in T V ver 3 When using the ports P11 to P13 set the PU37 bit in the PUR register to 1 usable If this bit is set to 0 unusable the P11 to P13 regisrers are set to 00h 4 The P11 to P13 registers are only in the 128 pin version Port P8 Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset O3FOh Indeterminate Bit symbol Bit name Function Port P8 OB Port P8 1 Bi Port P8 2 Bi Eo by writing to th ding bit i y writing to the corresponding bit in Port P8 4B this register Except for P8 5 RW Port P8 _5 Bi 0 L level RO Port P8 _6 Bi tee RW Port P8 _7 Bi RW t The pin level on any I O port which is set RW t for input mode can be read by reading RW the corresponding bit in this register t t The pin level on any I O port which is RW set for output mode can be controlled Rw Port P14 Control Regisrer 128 pin version b7
139. counting can be read in the TBi register at any time FFFFh is read while reloading Setting value is read between setting values in the TBi register at count stop and starting a counter 23 10 2 2 Timer B Event Counter Mode The timer remains idle after reset Set the mode count source counter value etc using the TBiIMR i 0 to 5 register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1 count starts Always make sure the TBiMR register is modified while the TBiS bit remains O count stops regardless whether after reset or not The counter value can be read out on the fly at any time by reading the TBi register However if this register is read at the same time the counter is reloaded the read value is always FFFFh If the TBi register is read after setting a value in it while not counting but before the counter starts counting the read value is the one that has been set in the register Rev 2 00 Nov28 2005 page 354 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 2 3 Timer B Pulse Period pulse Width Measurement Mode The timer remains idle after reset Set the mode count source etc using the TBiMR i 0 to 5 register before setting the TBiS bit in the TABSR or TBSR register to 1 count starts Always make sure the TBiMR regis
140. depend on use of sample and hold 2 0AD frequency must be 10 MHz or less When sample and hold is disabled AD frequency must be 250 kHz or more When sample and hold is enabled AD frequency must be 1 MHz or more Rev 2 00 Nov28 2005 page 202 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM fADO 0 A D conversion rate selection 1 3 1 ADTRG O Software trigger 9 VREFO Port PO group ANO 0O 1 2 A D trigger 16 A D Converter XXX LLLI ADCON register HH Decoder for A D register CH2 to CHO 000b ANO_1 O o 001b ANO 2O 010b NG 011b ANO 3O o 100b ANO 4 O 101b Port P10 group ANO O ANO O ANO O ANOO Decoder for channel selection ADGSEL1 to ADGSE OPA1 to OPA0 00b LO 00b ote ANO O ANO O ANO O ANO O PMO1 to PM00 00b ADGSEL1 to ADGSELO 10b OPA1 to OPAO 00b ate ANO_5 O ANO_6 O ANO_7 O o SN IO Port P2 group AN2 0O CH2 to CHO 000b PMO1 to PM00 00b ADGSEL1 to ADGSELO 11b OPA1 to OPA0 00b 001b AN2 10 010b AN2 20 o AN2 3O 011b AN2_4 O AN2_5 O AN2_6 O 100b HIS
141. dissipation mode or on chip oscillator low power dissipation mode program to a space other the flash memory Jump to the low power dissipation mode or on chip oscillator low power dissipation mode program transferred to a space other than the flash memory In the following steps use the low power dissipation mode in a space other than the flash memory NOTES Set the FMR01 bit to 1 after setting it to 0 CPU rewrite mode enabled Set the FMSTP bit to 1 the flash memory stops operating It is in a low power dissipation state 0 Switch the clock source of the CPU clock Turn main clock stops Process in low power dissipation mode or on chip oscillator low power dissipation mode Start Wait Switch main clock gt until oscillation gt clock source of oscillation stabilizes the CPU clock 2 Set the FMSTP bit to 0 flash memory operation Set the FMR01 bit to 0 CPU rewrite mode disabled Wait until the flash memory circuit stabilizes tps us Jump to a desired address in the flash memory 1 Set the FMSTP bit in the FMRO register to 1 after setting the FMRO 1 bit in the FMRO register to 1 CPU rewrite mode 2 Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock 3 Add tps us wait time by program Do not access the flash memory during this wait time 4 Before entering wait mode or stop mode be sure to set the FMRO 1 bit to 0 CPU rewrite dis
142. e The flag is set to 0 interrupt disabled e The D flag is set to 0 single step interrupt disabled e The U flag is set to 0 ISP selected However the U flag does not change state if an INT instruction for software interrupt Nos 32 to 63 is executed The temporary register within the CPU is saved to the stack The PC is saved to the stack The interrupt priority level of the acknowledged interrupt in IPL is set The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC 4 5 6 7 DH as DH After the interrupt sequence is completed an instruction is executed from the starting address of the interrupt routine NOTE 1 Temporary register cannot be modified by users CPU clock Address bus Address Indeterminate 1 J SP 2 J SP 4 J vec J vec 2 J PC Interrupt 1 SP 2 SP 4 vec vec 2 Data bus ETa Indeterminate 1 contents leote ER J contents i RD Indeterminate 1 WR 2 NOTES 1 The indeterminate state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to accept instructions 2 The WR signal timing shown here is for the case where the stack is located in the internal RAM Figure 10 5 Time Required f
143. for the watchdog timer refer to 11 1 Count Source Protective Mode After reset the on chip oscillator is turned off It is turned on by setting the CM21 bit in the CM2 register to 1 on chip oscillator clock and is used as the clock source for the CPU and peripheral function clocks in place of the main clock If the main clock stops oscillating when the CM20 bit in the CM2 register is 1 oscillation stop re oscillation detection function enabled and the CM27 bit is 1 oscillation stop re oscillation detection interrupt the on chip oscillator automatically starts operating supplying the nec essary clock for the microcomputer 8 1 4 PLL Clock The PLL clock is generated by a PLL frequency synthesizer This clock is used as the clock source for the CPU and peripheral function clocks After reset the PLL clock is turned off The PLL frequency synthe sizer is activated by setting the PLCO7 bit to 1 PLL operation When the PLL clock is used as the clock source for the CPU clock wait a fixed period of tsu PLL for the PLL clock to be stable and then set the CM11 bit in the CM1 register to 1 Before entering wait mode or stop mode be sure to set the CM11 bit to 0 CPU clock source is the main clock Furthermore before entering stop mode be sure to set the PLCO7 bit in the PLCO register to 0 PLL stops Figure 8 11 shows the procedure for using the PLL clock as the clock source for the CPU The PLL cloc
144. i Lupe cc neqoe 1 Starts counting Up Down Flag b7 b6 b5 b4 b3 b2 bi Address After Reset 0384h 00h TAOUD Timer AO Up Down Flag 0 Down count TA1UD Timer A1 Up Down Flag UP count TA2UD Timer A2 Up Down Flag Enabled by setting the MR2 bit in i the TAIMR register to 0 TASUD Timer A3 Up Down Flag switching source in UDF register TA4UD Timer A4 Up Down Flag during event counter mode TA2P Timer A2 Two Phase Pulse 0 Two phase pulse signal Signal Processing Select Bit processing disabled Two phase pulse signal TA3P Timer A3 Two Phase Pulse processing enabled 2 3 Signal Processing Select Bit TAAP Timer A4 Two Phase Pulse 4 Signal Processing Select Bit 1 Use the MOV instruction to write to this register 2 Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to 0 input mode 3 When not using the two phase pulse signal processing function set the corresponding bit to timer A2 to timer A4 to 0 Figure 13 5 TABSR Register and UDF Register Rev 2 00 Nov28 2005 page 117 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers One Shot Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ONSF 0382h 00h Bit Symbol Bit Name Function TAOOS Timer AO One Shot Start Flag The timer starts counting by setting this bit to 1 whi
145. if a DMA request may occur simultaneously when the DMAE bit is being written follow the steps below Step 1 Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously Step 2 Make sure that the DMAi is in an initial state as described above 1 and 2 in a program If the DMAi is not in an initial state the above steps should be repeated 12 4 DMA Request The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and DSELS to DSELO bits in the DMISL register i 0 1 on either channel Table 12 4 shows the timing at which the DMAS bit changes state Whenever a DMA request is generated the DMAS bit is set to 1 DMA requested regardless of whether or not the DMAE bit is set If the DMAE bit was set to 1 enabled when this occurred the DMAS bit is set to 0 DMA not requested immediately before a data transfer starts This bit cannot be set to 1 ina program it can only be set to O The DMAS bit may be set to 1 when the DMS or the DSEL3 to DSELO bits change state Therefore always be sure to set the DMAS bit to 0 after changing the DMS or the DSEL3 to DSELO bits Because if the DMAE bit is 1 a data transfer starts immediately after a DMA request is generated the DMAS bit in almost all cases is 0 when read in a program Read the DMAE bit to determine whether the DMAC is enabled Table 12 4 Timing at Which DMAS bit Changes State
146. in Set to 0 in a program a program a program a program ist 2nd 3rd _4th 5th 6th 7th 8th 9th bit t Set STAREQ bit Set STPREQ bit 1 start Start condition 1 start detection interrupt Stop condition detection interrupt Figure 15 26 STSPSEL Bit Functions 15 1 3 3 Arbitration Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is updated If the ABC bit 0 updated per bit the ABT bit is set to 1 at the same time unmatching is detected during check and is set to 0 when not detected In cases when the ABC bit is set to 1 if unmatching is detected even once during check the ABT bit is set to 1 unmatching detected at the falling edge of the clock pulse of 9th bit If the ABT bit needs to be updated per byte set the ABT bit to 0 undetected after detecting acknowledge in the first byte before transferring the next byte Setting the ALS bit in the UiSMR2 register to 1 SDA output stop enabled causes arbitration lost to occur in which case the SDAi pin is placed in the high impedance state at the same time the ABT bit is set to 1 unmatching detected Rev 2 00 Nov28 2005 page 181 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6N
147. in UiMR register 0 P6 1 P6 5 P7 2 Transfer Clock Input CKDIR bit 1 PD6 1 and PD6_5 bits in PD6 register 0 PD7 2 bit in PD7 register 0 CTSi RTSi CTS Input CRD bit in UiCO register 0 P6 0 P6 4 P7 3 CRS bit in UiCO register 0 PD6_0 and PD6_4 bits in PD6 register 0 PD7_3 bit in PD7 register 0 RTS Output CRD bit 0 CRS bit 1 I O Port CRD bit 1 i Oto2 Table 15 4 P6_4 Pin Functions Bit set Value Pin Function U1CO Register UCON Register PD6 Register CRD bit CRS bit RCSP bit CLKMD1 bit CLKMDO bit PD6_4 bit Input 0 Output 1 Q or ux li NOTES 1 In addition to this set the CRD bit in the UOCO register to O CTSO RTSO enabled and the CRS bit in the UOCO register to 1 RTSO selected 2 When the CLKMD1 bit 1 and the CLKMDO bit 0 the following logic levels are output High if the CLKPOL bit in the U1CO register 0 Low if the CLKPOL bit 1 Rev 2 00 Nov28 2005 page 161 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 1 Example of Transmit Timing when internal clock is selected TC oe Transfer clock LT IL LT IL UT IL LT UT IL LT IL TE bit in l UiC1 register Write data to the UiTB register TI bit in UiC1 register Transferred from the
148. informs the transmission side that the recep tion has become ready The output level of the RTSi pin goes to H when reception starts So if the RTSi pin is connected to the CTSi pin on the transmission side the circuit can transmission and reception data with consistent timing With the internal clock the RTS function has no effect If a low level signal is applied to the NMI pin when the IVPCR 1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the RTS2 and CLK2 pins go to a high imped ance state 23 12 1 2 Transmission When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit 2 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in UiTB register e If CTS function is selected input on the CTSi pin L 23 12 1 3 Reception In operating the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside from the TXDi i 0 to
149. internal RAM 1 DMA transfer is not effective to any interrupt DMA transfer is affected neither by the flag nor by the interrupt control register 2 The selectable causes of DMA requests differ with each channel 3 Make sure that no DMAC related registers addresses 0020h to 003Fh are accessed by the DMAC Rev 2 00 Nov 28 2005 page 104 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM DMAO Request Cause Select Register b7 b6 b5 b4 b3 b2 bi bO 12 DMAC Symbol Address After Reset DMOSL 03B8h 00h Bit Symbol Bit Name Function Select Bit Request Bit DMA Request Cause See NOTE 1 Nothing is assigned When write set to 0 When read their contents are O A DMA request is generated by setting Software DMA this bit to 1 when the DMS bit is 0 basic cause and the DSEL3 to DSELO bits are 0001b software trigger The value of this bit when read is 0 1 The causes of DMAO requests can be selected by a combination of the DMS bit and the DSEL3 to DSELO bits in the manner described below DSEL3 to DSELO Bits DMS 0 basic cause of request DMS 1 extended cause of request 0000b Falling edge of INTO pin 0001b Software trigger 0010b Timer AO 0011b Timer A1 0100b Timer A2 0101b Timer A3 0110b Timer A4 Two edg
150. is 16 bit long when the this pin is held L and 8 bit long when the this pin is held H Set it to either one Connect this pin to VSS when an single chip mode Bus control pins 9 I Input O NOTES DO to D7 Inputs and outputs data DO to D7 when these pins are set as the separate bus D8 to D15 Inputs and outputs data D8 to D15 when external 16 bit data bus is set as the separate bus AO to A19 Output address bits AO to A19 AO0 DO to A7 D7 Input and output data DO to D7 and output address bits AO to A7 by time sharing when external 8 bit data bus are set as the multiplexed bus A1 DO to A8 D7 Input and output data DO to D7 and output address bits A1 to A8 by time sharing when external 16 bit data bus are set as the multiplexed bus CS0 to CS3 Output CSO to CS3 signals CSO to CS3 are chip select signals to specify an external space WRL WR WRH BHE RD Output WRL WRH WR BHE RD signals WRL and WRH or BHE and WR can be switched by program e WRL WRH and RD are selected The WRL signal becomes L by writing data to an even address in an external memory space The WRH signal becomes L by writing data to an odd address in an external memory space The RD pin signal becomes L by reading data in an external memory space e WR BHE and RD are selected The WR signal becomes L by writing data in an external memory space The RD signal
151. its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 5 3 How to Use Oscillation Stop and Re oscillation Detection Function The oscillation stop re oscillation detection interrupt shares the vector with the watchdog timer interrupt If the oscillation stop re oscillation detection and watchdog timer interrupts both are used read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt Where the main clock re oscillated after oscillation stop the clock source for CPU clock and peripheral function must be switched to the main clock in the program Figure 8 14 shows the procedure to switch the clock source from the on chip oscillator to the main clock Simultaneously with oscillation stop re oscillation detection interrupt request occurrence the CM22 bit becomes 1 When the CM22 bit is set at 1 oscillation stop re oscillation detection interrupt are disabled By setting the CM22 bit to 0 in the program oscillation stop re oscillation detection interrupt are enabled e f the main clock stops during low speed mode where the CM20 bit is 1 an oscillation stop re oscillation detection interrupt request is generated At the same time the on chip oscillator starts oscillating In this case although the CPU clock is derived from the sub clock as it was before the interrupt occurred the peripheral function clocks now are derive
152. level returns due to the E occurrence of a parity error RXD2 pin level 1 interrupt routine TXEPT bit in E The level is U2CO register detected by the The IR bit is set to 1 at the Drupi routne IR bit in falling edge of transfer clock Da S2TIC register The above timing diagram applies to the case where data is Set to 0 by an interrupt request acknowledgement or a program transferred in the direct format iti TC 16 n 1 fi or 16 n 1 fEXT STPS bit in U2MR register 0 1 stop bit Sy PRY bit in U2MR register 1 even parity fi frequency of U2BRG count source f1SIO f2SIO f8SIO f32SIO UFORM bit in U2CO register 0 LSB first fEXT frequency of U2BRG count source external clock U2LCH bit in U2C1 register 0 no reverse n value set to U2BRG U2IRS bit in U2C1 register 1 transmit is completed NOTE 1 Because TXD2 and RXD2 are connected a composite waveform consisting of the TXD2 output and the parity error signal sent back from receiving end is generated 2 Reception Transfer clock RE bit in U2C1 register Transmit waveform Start Parity Stop from transmitting end bit bit bit ARRARAS Sh STAPKE KEXP SPD SD T PY SP TXD2 An L level is output from TXD2 due to the occurrence of a parity error mE 9998999997 999999990 IR bit in H Read the U2RB register Read the U2RB register S2RIC register N P al The above timing diagram applies to the case where da
153. logic This function reverses the logic value of the transmit receive data Transfer clock output from multiple pins selection UART1 The output pin can be selected in a program from two UART1 transfer clock pins that have been set Separate CTS RTS pins UARTO CTSO and RTSO are input output from separate pins 1 When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit in the UiCO register 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state 2 The UOIRS and U1IRS bits respectively are bits 0 and 1 in the UCON register the U2IRS bit is bit 4 in the U2C1 register 3 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in the SiRIC register does not change Rev 2 00 Nov 28 2005 page 159 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 2 Registers to Be Used and Settings in Clock Synchronous Serial I O Mode 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER Overrun error flag
154. max BCLK tcyc i i i i j mi i EM i 1 4 d AD ALE thiALEADS i 14 0 9 xCtoyo 40 nsmin p 0 5 X tcyc 15 ns min i i i i us v J laz RD AD 114 8ns maxi H tac3 RD DB a 5x tcyc 60 ns max i i i T i tt i T i qta AD RD i Ons min i i i i i i t BCLK AD i MC 40ns max i th BCLK ALE H i td BCLK ALE i i 40ns max e Aa Ans min i i ta BCLK RD t gt 40ns max i Write timing BCLK ta BCLK CS 40ns max ta D D 1 td BCLK DB rt 50ns max Data output th BCLK Cs th RD CS 0 5 X tcyc 10 ns min 4 Address Data input re gt gt th RD DB tsu DB RD 1 Ons min 50ns min th BCLK AD 4ns min th RD AD 1 0 5 X tcyc 10 ns min th BCLK RD i Ons min th wR Cs X tcyc 10 ns min th BCLK DB 4ns min td DB WR 4 5 X tcyc 50 ns min 0 5 X tcyc 40 ns min i Id BCLK AD 1 40ns max f i td BCLK ALE th BCLK ALE i gt 40ns max yi a 4ns min T 18 ta AD WR d gt Ons min d n ta BCLK WR toye BCLK Measuring conditions e VCC 3 3 V e Input timing voltage ViL 0 6 V ViH 2 7V e Output timing voltage VoL 1 65 V VoH 1 65 V Figure 22 19 Timing Diagram 7 Rev 2 00 Nov 28 2005 page 326 of 378 REJ09B0124 0200 131 NESAS o th wR DB 0 5 X tcyc 10 ns min th BCLK
155. mode 2 The S5C and S6C registers are only in the 128 pin version When using these registers set these registers after setting the PU37 bit in the PURSG registger to 1 Pins P11 to P14 are usable The input threshold voltage of pins differs between programmable I O ports and peripheral functions Therefore if any pin is shared by a programmable I O port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions VIH and VIL neither high nor low the input level may be determined differently depending on which side the programmable I O port or the peripheral function is currently selected When changing the PD14_i bit i O 1 in the PC14 register from 0 input port to 1 output port follow the procedures below 128 pin version only Setting Procedure 1 Set P14 i bit MOV B 00000001b PC14 P14_i bit setting 2 Change PD14_i bit to 1 by MOV instruction MOV B 00110001b PC14 Change to output port Indeterminate values are read from the P3 7 to P3 4 PD3 7 to PD3 4 bits by reading the P3 and PD3 registers when the PMO1 to PMOO bits in the PMO register are set to 01b memory expansion mode or 11b microprocessor mode and setting the PM11 bit to 1 Use the MOV instruction when rewriting the P3 and PD3 registers including the case that the size specifier is W and the P2 and PD2 registers are rewritten Normal ver onl
156. on the first falling edge of the CLKi pin e CRD bit in UiCO register 1 disables UARTO CTS RTS function CTS RTSi pin is programmable I O function e CRD bit 0 CRS bit in UiCO register 0 CTS function is selected CTSi RTSi pin is CTS function e CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 15 1 2 7 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6 0 pin and accepts as input the CTSO from the P6 4 pin To use this function set the register bits as shown below e CRD bit in UOCO register 0 enables UARTO CTS RTS e CRS bit in UOCO register 1 outputs UARTO RTS CRD bit in U1CO register 0 enables UART1 CTS RTS e CRS bit in U1CO register 0 inputs UART1 CTS RCSP bit in UCON register 1 inputs CTSO from the P6 4 pin e CLKMD1 bit in UCON register 0 CLKS1 not used Note that when using the CTS RTS separate function UART1 CTS RTS separate function cannot be used Figure 15 22 shows CTS RTS separate function usage Microcomputer TXDO P6 3 RXDO P6 2 Figure 15 22 CTS RTS Separate Function Rev 2 00 Nov28 2005 page 174 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 3 Special Mode 1 I C Mode FC mode is provided for use as a simplified I C interface compatible mod
157. one timer operated using fC32 Rev 2 00 Nov 28 2005 page 296 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 6 A D Conversion Characteristics Standard Min Typ Parameter Measuring Condition Resolution VREF VCC Integral 10 bits VREF ANEXO ANEX1 input ANO to AN7 input Nonlinearity VCC ANO 0to ANO 7 input AN2_0 to AN2 7 input Error 5V_ External operation amp connection mode VREF ANEXO ANEX1 input ANO to AN7 input VCC ANO 0to ANO 7 input AN2_0 to AN2 7 input 3 3V External operation amp connection mode 8 bits VREF AVCC VCC 3 3V Absolute 10 bits VREF ANEXO ANEX1 input ANO to AN7 input Accuracy VCC ANO 0to ANO 7 input AN2_0 to AN2_7 input 5V_ External operation amp connection mode VREF ANEXO ANEX1 input ANO to AN7 input VCC ANO 0to ANO 7 input AN2_0 to AN2 7 input 3 3V External operation amp connection mode 8 bits VREF AVCC VCC 3 3V Differential Nonlinearity Error Offset Error Gain Error Resistor Ladder VREF VCC 10 bit Conversion Time VREF VCC 5V AD 10MHz Sample amp Hold Available 8 bit Conversion time VREF VCC 5V AD 10MHz Sample amp Hold Available Sampling Time Reference Voltage Analog Input Voltage
158. op amp Figure 16 9 shows an example of how to connect the pins in external operation amp NOTE 1 ANO i and AN2 i can be used the same as ANI Microcomputer ADGSEL1 to ADGSELO bits in ADCON register 00b Resistor ladder e Successive conversion register to ADGSELO bits 10b o to ADGSELO bits 11b o ANEX1 Comparator External op amp Figure 16 9 External Op Amp Connection Rev 2 00 Nov 28 2005 page 216 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter 16 2 5 Current Consumption Reducing Function When not using the A D converter its resistor ladder and reference voltage input pin VREF can be separated using the VCUT bit in the ADCON1 register When separated no current will flow from the VREF pin into the resistor ladder helping to reduce the power consumption of the chip To use the A D converter set the VCUT bit to 1 VREF connected and then set the ADST bit in the ADCONO register to 1 A D conversion start The VCUT and ADST bits cannot be set to 1 at the same time Nor can the VCUT bit be set to 0 VREF unconnected during A D conversion Note that this does not affect VREF for the D A converter irrelevant 16 2 6 Output Impedance of Sensor under A D C
159. oscillation Detection Function sessssessesseeeeeeeeeenneeeen nnns 344 29 7 MOVE CMON esiti eI MINIMUM EIN IM LP IPIE ea DNLeNe 345 Pier EUM 346 23 91 Reading Address 00000h 5 3 n iiem lank eei itum UE ix Uus iEin ix iaa eio Eie exe Sees 346 29 82 Seting Pease rm 346 23 8 3 NMI IBEGITUDL sedate rout etat tens rnti timete onctensnntainantsbasnasieenshdecbantbndactaes betiSeaaidneeuiantsS stented 346 23 8 4 Changing Interrupt Generate Factor sssssssssseseseeeeeee nennen nennen nnne rennes 347 23 855 INFE Inter UD sra or Dae e ten bant Ra Puedes AEn ao brut tom E 347 23 8 6 Rewrite Interrupt Control Register desioen sienai eisiaa nennen nnne nenne nnns entren 348 23 8 7 Watchdog Timer ntermpt 5er crure cu etu ttr doter e saeva eek curve e SR v AKE 348 usps 349 23 9 1 Write to DMAE Bit in DMiCON Register lt span ancikan anaa aaea aa enn 349 ISBN EE 350 239 310 TITIO A aa eite futt teta nt c t tp fete a US f DT EE 350 29 102 Mimer B e candies 354 23 11 Thee Phase Motor Control Timer Function ssssssssssseseeneeeeeeeenneeen nennen nnn en nnns nennen 356 ose mE 357 23 12 1 Clock Synchronous Serial VO Mod minisinour tee tenet enar ina ra uc x ede E Eee dues 357 23 12 2 Special MOGd6S emori rte cic s rs ut Exe Lu arterial ni totaled 358 cow pecore 359 29 19 A D COME ME riss 360 23 14 CAN on
160. ososEosEo os 5os eoe e en T Teos ees eos eo o Eo TT TT pesqsospsogso sos gt lt Tsos se sos sce v EET EerEosos ososEos o os ece sce e en Lp ens ea ers eroe E101 eoo gt lt gt lt gt lt gt lt LLL LL gt lt Jsinrd sibg sing s07 sips gt lt gt lt sibs siDa sibs sipz sib1 Sibo gt lt gt lt gt lt gt lt Jet017 feo tefeto15 E10 rales E10 12 e10 17 eroto E109 eroe E107 eroe gt lt gt lt Jeios eta eros ere E101 eo0 gt lt gt lt gt lt gt lt gt lt gt lt lt I i 0 1 NOTES 1 EP is undefined 2 These registers can be written in CAN reset initialization mode of the CAN module Figure 19 5 Bit Mapping of Mask Registers in Word Access Rev 2 00 Nov 28 2005 page 227 of 378 RENESAS REJ09B0124 0200 Addresses CANO 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h CAN1 0360h 0362h 0364h 0366h 0368h 036Ah 036Ch 036Eh 0370h gt CiGMR register gt CiLMAR register gt CiLMBR register gt CiGMR register gt CiLMAR register gt CiLMBR register Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 4 CAN SFR Registers Figures 19 6 to 19 11 show the CAN SFR registers CANi Message Control Register j i 0 1 j O to 15 b7 b6 b5 b4 b3 b2 bi bO S
161. output Read from Timer Count value can be read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Value written to the TAi register is written to both reload register and counter Select Function Gate function Counting can be started and stopped by an input signal to TAiIN pin Pulse output function When TAIS bit is set to 0 stop counting the pin outputs a low i 0to4 Timer Ai Mode Register i 2 O to 4 b7 b6 b5 b4 b3 b2 bi bO It fol I fofo TAOME to TAAM R Bodo sn Tn remi TMODO Operation Mode bibo TMOD1 Select Bit 0 0 Timer mode AW 0 Pulse is not output Pulse Output Function TAiOUT pin is a normal port pin aW Select Bit 1 Pulse is output TAiOUT pin is a pulse output pin 00 Gate function not available J TAIIN pin functions as I O port RW Gate Function Select Bit Counts while input on the TAiIN pin is low 1 Counts while input on the TAiIN pin RW is high 1 RW Set to 0 in timer mode RW Count Source Select Bit 1 The port direction bit for the TAiIN pin is set to 0 input mode Figure 13 7 TAOMR to TA4MR Registers in Timer Mode Rev 2 00 Nov28 2005 page 119 of 378 RENESAS REJ09B0124 0200 Wheneve
162. output a low level signal from the SCLi pin even while sending or receiving data Setting the SWC2 bit to 0 transfer clock allows the transfer clock to be output from or supplied to the SCLi pin instead of outputting a low level signal If the SWC9 bit in the UISMR4 register is set to 1 SCL hold low enabled when the CKPH bit in the UiSMRS register 1 the SCLi pin is fixed to low level output at the falling edge of the clock pulse next to the ninth Setting the SWC9 bit 0 SCL hold low disabled frees the SCLi pin from low level output 15 1 3 5 SDA Output The data written to bit 7 to bit O D7 to DO in the UiTB register is sequentially output beginning with D7 The ninth bit D8 is ACK or NACK The initial value of SDAi transmit output can only be set when IICM 1 1 C mode and the SMD2 to SMD O bits in the UiMR register 000b serial interface disabled The DL2 to DLO bits in the UiSMRS register allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output Setting the SDHI bit in the UiSMR2 register 1 SDA output disabled forcibly places the SDAi pin in the high impedance state Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock This is because the ABT bit may inadvertently be set to 1 detected 15 1 3 6 SDA Input When the IICM2 bit 0 the 1st to 8th bits D7 to DO of received data are stored in the bit 7 to bit O in the UiRB register The 9
163. re oscillation detection function For details about the oscillation stop and re oscillation detection function refer to 8 Clock Generating Circuit 10 3 1 5 Single Step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development tools 10 3 1 6 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADO to RMADS registers that corresponds to one of the AIERO or AIER1 bit in the AIER register or the AIER20 or AIER21 bit in the AIER2 register which is 1 address match interrupt enabled For details refer to 10 10 Address Match Interrupt 10 3 2 Peripheral Function Interrupts The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged The peripheral function interrupt is a maskable interrupt See Table 10 2 Relocatable Vector Tables about how the peripheral function interrupt occurs Refer to the descriptions of each function for details Rev 2 00 Nov28 2005 page 83 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes Set the start address of each interrupt routine in the respective interrupt vectors When an interrupt request is accepted the CPU
164. registers Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol FMRO Bit Symbol Address 01B7h 21 Flash Memory Version After Reset 00000001b Bit Name Function RY BY Status Flag 0 Busy being written or erased 1 Ready CPU Rewrite Mode Select Bit 2 Disables CPU rewrite mode Enables CPU rewrite mode Lock Bit Disable Select Bit 3 Enables lock bit Disables lock bit Flash Memory Stop Bit 4 5 Enables flash memory operation Stops flash memory operation placed in low power dissipation mode flash memory initialized FMRO05 FMRO6 Reserved Bit User ROM Area Select Bit 4 Effective in only boot mode Program Status Flag 9 Erase Status Flag 6 Set to 0 0 Boot ROM area is accessed 1 User ROM area is accessed 0 Terminated normally 1 Terminated in error 0 Terminated normally 1 Terminated in error 1 This status includes writing or reading with the lock bit program or read lock bit status command 2 To set this bit to 1 write 0 and then 1 in succession Make sure no interrupts or no DMA transfers will occur before writing 1 after writing O Write to this bit when the NMI pin is in the high state Also while in EWO mode write to this bit from a program in other than the flash memory To set this bit to 0 in a read array m ode 3 To set this bit to 1 write 0 and then 1 in succession when the F
165. rising edge of PWM pulse and continues counting The timer is not affected by a trigger that occurs during counting 16 bit PWM High level width n fj n set value of the TAi register e Cycle time 29 1 fj fixed fj count source frequency f1 f2 f8 f32 fC32 8 bit PWM e High level width n X m 1 fj n set value of the TAI register high order address e Cycle time 25 1 X m 1 fj m set value of the TAI register low order address Count Start Condition e The TAIS bit in the TABSR register is set to 1 start counting e The TAIS bit 1 and external trigger input from the TAiIN pin e The TAIS bit 1 and one of the following external triggers occurs Timer B2 overflow or underflow Timer Aj overflow or underflow Timer Ak overflow or underflow Count Stop Condition The TAIS bit is set to 0 stop counting Interrupt Request Generation Timing On the falling edge of the PWM pulse TAiIN Pin Function I O port or trigger input TAiOUT Pin Function Pulse output Read from Timer An indeterminate value is read by reading the TAi register Write to Timer i O0to4 j i 1 exceptj 4ifi 0 When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Trans
166. set Table 15 14 Special Mode 2 Specifications Specification Transfer data format Transfer data length 8 bits Transfer clock Master mode The CKDIR bit in the UiMR register 0 internal clock fj 2 n 1 fj 1SIO f2SIO f8SIO f32SIO n Setting value of the UiBRG register OOh to FFh e Slave mode The CKDIR bit 1 external clock selected Input from CLKi pin Transmit receive control Controlled by input output ports Transmission start condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in the UiTB register Reception start condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in the UiTB register Interrupt Request Generation Timing For transmission one of the following conditions can be selected e The UilRS bit 0 transmit buffer empty when transferring data from the UiTB register to the UARTi transmit register at start of transmission e The UiIRS bit 1 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception e When transferring data from the UARTi receive register to the UiRB register
167. stop bit PRYE bit in UIMR register 1 parity enabled Figure 15 19 Transfer Format Rev 2 00 Nov28 2005 page 172 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 2 4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the UiRB register Figure 15 20 shows serial data logic 1 When the UiLCH bit in the UiC1 register O no reverse Transfer clock d aba st Do X_D1 X pei D3 X p4j D5 X De X oj P Y sP 2 When the UiLCH bit 1 reverse W Transfer clock T H L TDi reverse Sr Do D1 X D2 D3 X D4 D5 D6 X D7 P SP i Oto2 ST Start bit P Parity bit SP Stop bit NOTE 1 This applies to the case where the register bit are set as follows CKPOL bit in UiCO register 0 transmit data output at the falling edge of the transfer clock UFORM bit in UiCO register O LSB first STPS bit in UIMR register 0 1 stop bit e PRYE bit in UIMR register 1 parity enabled Figure 15 20 Serial Data Logic Switching 15 1 2 5 TXD and RXD I O Polarity Inverse Function This function inverses the polarities of the TXDi pin output and RXDi pin input The logic levels of all input output data including the start
168. subject to the same conditions as the source read cycle with the transfer cycle changing accordingly When calculating transfer cycles take into consideration each condition for the source read and the destination write cycle respectively For example when data is transferred in 16 bit unit using an 8 bit bus 2 on Figure 12 5 two source read bus cycles and two destination write bus cycles are required 12 1 4 Effect of RDY Signal During memory expansion and microprocessor modes DMA transfers to and from an external area are affected by the RDY signal Refer to 7 2 6 RDY Signal NOTE 1 Not available the bus control pins in T V ver Rev 2 00 Nov28 2005 page 108 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC 1 When the transfer unit is 8 or 16 bits and the source of transfer is an even address bis ome Ames jo neam AS Q0 num RD signal WR signal Data bus CPU use Source Destination CPU use 2 When the transfer unit is 16 bits and the source address of transfer is an odd address or when the transfer unit is 16 bits and an 8 bit bus is used oa _ L4 Address X Dummy Y bus CPU use B Source e Jens iz Destination A cycle CPU use RD signal WR signal Data bus CPU use 3 When the source read cycle under condi
169. the CM2 register The oscillation stop and re oscillation detection function can be enabled or disabled using the CM20 bit in the CM2 register Table 8 9 lists a specification overview of the oscillation stop and re oscillation detection function Table 8 9 Specification Overview of Oscillation Stop and Re oscillation Detection Function Oscillation Stop Detectable Clock and f XIN 2 2 MHz Frequency Bandwidth Enabling Condition for Oscillation Stop Set CM20 bit to 1 enable and Re oscillation Detection Function Operation at Oscillation Stop Reset occurs when CM27 bit 0 Re oscillation Detection Oscillation stop re oscillation detection interrupt occurs when the CM27 bit 1 8 5 1 Operation When CM27 Bit 0 Oscillation Stop Detection Reset Where main clock stop is detected when the CM20 bit is 1 oscillation stop re oscillation detection function enabled the microcomputer is initialized coming to a halt oscillation stop reset refer to 4 Special Function Register SFR 5 Reset This status is reset with hardware reset Also even when re oscillation is detected the microcomputer can be initialized and stopped it is however necessary to avoid such usage During main clock stop do not set the CM20 bit to 1 and the CM27 bit to O 8 5 2 Operation When CM27 Bit 1 Oscillation Stop Re oscillation Detection Interrupt Where the main clock corresponds to the CPU clock source and the CM20 bit
170. these bits to 110b when transfer data is 9 bit long CKDIR Select the internal clock or external clock STPS Select the stop bit PRY PRYE Select whether parity is included and whether odd or even IOPOL Select the TXD RXD input output polarity CLKO CLK1 Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selected when transfer data is 8 bit long Set this bit to 0 when transfer data is 7 or 9 bit long TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Select the source of UART2 transmit interrupt U2RRM Set to 0 UiLCH Set this bit to 1 to use inverted data logic UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 i Oto2 NOTES UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD1 bit 0 CLKMD1 Set to 0 RCSP Set this bit to 1 to accept as input the UARTO CTSO signal from the P6 4 pin 7 Set
171. tide 287 21 5 1 User ROM and Boot ROM Areas c cccccccccccccsccsssessseaeeseeeeecesseeeseeesseseeseeceeeessecesessaaeseeeeeeeeeess 287 21 5 2 ROM Code Protect FUDCLOFi i eoi iieri des tan pe coe ei eno teo t Posi usine sect leen d Apa aea ban detwe ss Pause sau duds 287 21 6 CAN I O Mode 288 21 6 1 ID Code Check Function ccccceccecessscceeeeececeeecesessessaeeseeeceeeeeseseseseesaeeeeueceeceeseseeeeestseseeeeeeeeeess 288 21 6 2 Example of Circuit Application in CAN I O Mode ssssseseeeeeee enne 291 22 El ctrical CharacteriStiCS osiers occ RO Ron a ERE RRA SER sacs CD Sep M EOS m MUI DRP CUR aaa 292 22 1 Electrical Characteristics Normal ver sssssssssssssssseeeeeeeenneee nennen nennen nennen nennen nnn 292 22 2 Electrical Characteristics T V ver sssssssssssssssseseeeeee nennen nnne nenne seen rnnn rsen nnne nnn 328 23 Usage PrIeealllof Essai ns trig lale bua B Dua Mata ntu 338 239 SED uenis ME Ee 338 23 1 External BUS sossvinsiced cesta cenntactadectasthssiuakesests exasvanedearsiadscecoaesbeeedaaaen s eie eu PR EEr nE guesses EVENE 339 23 9 External Clo6I citare dote eet dde rines ialesceudusnatvexdeeytaceat ven per euh tu dtd ex ku ces uia duet ela 340 294 POL Frequency Sylthesizer dc utei e e ccm det rete eee bre eed e Pr 341 23 SP OWS COMMON i Beide a MIDIMNMUINEIMI III M DE 342 23 6 Oscillation Stop Re
172. timer mode Select Clock source 00 TCK1 to TCKO f1 or f2 One shot 8 e Pulse width modulation TMOD1 to TMODO 11 The timer counts an internal count source The timer counts pulses from an external device or overflows and underflows of other timers The timer outputs a pulse only once before it reaches the minimum count 0000h Pulse width modulation mode The timer outputs pulses in a given width successively Select clock TMOD1 to TMODO 00 MR2 0 TMOD1 to TMODO 10 TMOD to TMODO MR2 32 fC32 e Timer gate function TMOD1 to TMODO 00 MR2 1 e Event counter Polarity TAINO selection 01 TB2 overflow 1 10 TAj overflow 1 1 TAk overflow 1 Pulse output TCK1 to TCKO TMOD1 to TMODO MR2 to MR1 Bits TAiTGH to TAiTGL Bits in ONSF register If i 0 bits TAIS Bit in TABSR register TAiUD Bit in UDF register i 0to4 j i 1except j 4 wheni 0 k i 1 except k 0 wheni 4 NOTE 1 Overflow or underflow TMOD1 to TMODO 01 High order 8 bits To external trigger circuit Decrement Toggle Flip Flop in TAiMR register in TRGSR register if i 1 to 4 Figure 13 3 Timer A Block Diagram Rev 2 00 Nov28 2005 page 115 of 378 REJ09B0124 0200 131 NESAS Counter Increment Decrement Always counts down except in event counter mode O TMOD1 to TMODO TAi Timer AO Timer A1 Timer A2 Timer A3 Timer A4 A
173. to 0 1 The bits used for transmit receive data are as follows Bit 0 to bit 6 when transfer data is 7 bit long e Bit 0 to bit 7 when transfer data is 8 bit long e Bit 0 to bit 8 when transfer data is 9 bit long 2 Set bit 4 to bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are included in the UCON register Rev 2 00 Nov28 2005 page 168 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 7 lists the functions of the input output pins during UART mode Table 15 8 lists the P6 4 pin functions during UART mode Note that for a period from when the UARTi operation mode is selected to when transfer starts the TXDi pin outputs an H Figure 15 17 shows the typical transmit timings in UART mode Figure 15 18 shows the typical receive timing in UART mode Table 15 7 I O Pin Functions TXDi Serial Data Output Outputs H when performing reception only P6 3 P6 7 P7 0 RXDi Serial Data Input PD6 2 and PD6 6 bits in PD6 register 0 P6 2 P6 6 P7 1 PD7 1 bit in PD7 register 0 Can be used as an input port when performing transmission only CLKi I O Port CKDIR bit in UiMR register 0 P6 1 P6 5 P7 2 Transfer Clock Input CKDIR bit in UiIMR register 1 PD6 1 and PD6 5 bits in PD6 register 0 PD7 2 bit in PD7 register 0 CTS
174. to BCLK 4 th RD AD Address output hold time refers to RD NOTE 1 h wR AD Address output hold time refers to WR NOTE 1 ta gcuk cs Chip select output delay time tnBcuk cs Chip select output hold time refers to BCLK 4 tn RD CS Chip select output hold time refers to RD NOTE 1 tniwR cs Chip select output hold time refers to WR NOTE 1 ta BcLk RD RD signal output delay time thiBcLk RD RD signal output hold time tagcu wR WR signal output delay time thecLk wR WR signal output hold time taBcLk bB Data output delay time refers to BCLK tnBcuk oB Data output hold time refers to BCLK 4 ta DB wr Data output delay time refers to WR NOTE 2 th wR DB Data output hold time refers to WR NOTE 1 taecik Hioa HLDA output delay time taBcLk aLe ALE signal output delay time refers to BCLK thiBcLk ALeE ALE signal output hold time refers to BCLK 4 ta AD ALE ALE signal output delay time refers to Address NOTE 3 th ALE AD ALE signal output hold time refers to Address NOTE 4 ta aD RD RD signal output delay from the end of Address 0 ta AD WR WR signal output delay from the end of Address 0 taziRb AD Address output floating start time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 Beck OPS 2 Calcul
175. value is 0 when read on the reception slot configuration Figure 19 2 Bit Mapping in Byte Access Z lt lt lt o 08 012 o lt 1 foo Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Time Stamp high order byte Time Stamp low order byte CAN Data Frame SID10 to6 SIDS5toO EID17to14 EID13to6 EID5toO DLC3 t00 Data Byte 0 Data Byte 1 77777 Data Byte 7 NOTE 1 When x is read the value is the one written upon the transmission slot configuration The value is 0 when read on the reception slot configuration Figure 19 3 Bit Mapping in Word Access Rev 2 00 Nov28 2005 page 226 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 3 Acceptance Mask Registers 19 CAN Module Figures 19 4 and 19 5 show the CiGMR register i 0 1 the CILMAR register and the CiLMBR register in which bit mapping in byte access and word access are shown Addresses CANO 0160h 0161h i2 0 1 NOTES 1 is undefined CAN1 0360h 0361h 0362h 0363h 0364h 0366h 0367h 0368h 0369h 036Ah 036Ch 036Dh 036Eh 036Fh 0370h 2 These registers can be written in CAN reset initialization mode of the CAN module Figure 19 4 Bit Mapping of Mask Registers in Byte Access b8 bO EE pessos sosso sos T Tsos ses sos sco s v TET EerEosos
176. value may be stored in the ADi register This problem occurs when a divide by n clock derived from the main clock or a sub clock is selected for CPU clock When operating in one shot or single sweep mode Check to see that A D conversion is completed before reading the target ADi register Check the IR bit in the ADIC register to see if A D conversion is completed e When operating in repeat mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it If A D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCONO register to 0 A D conversion halted the conversion result of the A D converter is indeterminate The contents of ADi registers irrelevant to A D conversion may also become indeterminate If while A D conversion is underway the ADST bit is set to 0 in a program ignore the values of all ADi registers When setting the ADST bit to 0 in single sweep mode during A D conversion and A D conversion is aborted disable the interrupt before setting the ADST bit to 0 The applied intermediate potential may cause more increase in power consumption than other analog input pins ANO to AN3 ANO 0 to ANO 7 and AN2 0 to AN2 7 since the AN4 to AN7 are used with the KIO to KI3 Rev 2 00 Nov28 2005 page 361 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM
177. 0 Nov28 2005 page 179 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 3 1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined A start condition detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state A stop condition detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state Figure 15 25 shows the detection of start and stop condition Because the start and stop condition detected interrupts share the interrupt control register and vector check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt 3 to 6 cycles lt duration for setting up 3 to 6 cycles lt duration for holding Duration for Duration for setting up holding SCLi SDAi Start condition SDAi Stop condition i Oto2 NOTE 1 When the PCLK1 bit in the PCLKR register 1 this is the cycle number of f1SIO and when the PCLK1 bit 0 this is the cycle number of f2SIO Figure 15 25 Detection of Start and Stop Condition 15 1 3 2 Output of Start and Stop Condition A start condition is generated by setting the STAREQ bit in the UISMR4 register i 0 to 2 to 1 start A restart
178. 0 to 7 Set a transfer rate SMD2 to SMDO Set to 001b CKDIR Select the internal clock or external clock IOPOL Set to 0 CLK1 to CLKO Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first TE Set this bit to 1 to enable transmission reception Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS 2 Select the source of UART2 transmit interrupt U2RRM 2 Set this bit to 1 to use continuous receive mode UiLCH Set this bit to 1 to use inverted data logic UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 2 Set to 0 NODC Select clock output mode 4to7 Set to 0 0 to 7 Set to 0 UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set this bit to 1 to use continuous receive mode CLKMDO Select the transfer clock output pin when the CLKMD 1 bit 1 CLKMD1 Set this bit to 1 to output UART1 transfer clock from two pins RCSP Set this bit to 1 to accept as input the UARTO CTSO signal from the P6
179. 0038h Indeterminate RW Set the transfer count minus 1 The written value is stored in the DMAi transfer counter reload register and when the DMAE bit in the DMICON register is set to 1 DMA enabled or the DMAi transfer counter underflows when the DMASL bit in the DMiCON 0000h to FFFFh register is 1 repeat transfer the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter When read the DMAi transfer counter is read Figure 12 4 SARO and SAR1 Registers DARO and DAR1 Registers TCRO and TCR1 Registers Rev 2 00 Nov28 2005 page 107 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC 12 1 Transfer Cycle The transfer cycle consists of a memory or SFR read source read bus cycle and a write destination write bus cycle The number of read and write bus cycles is affected by the source and destination addresses of transfer During memory expansion and microprocessor modes it is also affected by the BYTE pin level Furthermore the bus cycle itself is extended by a software wait or RDY signal NOTES 1 Not available memory expansion and microprocessor modes in T V ver 2 Not available the bus control pins in T V ver 12 1 1 Effect of Source and Destination Addresses If the transfer unit and data bus both are 16 bits and the source address of transfer beg
180. 0110b Timer A4 SI 04 0111b Timer BO Two edges of INT1 pin 1000b Timer B1 1001b Timer B2 1010b UARTO transmit 1011b UARTO receive ACKO 1100b UART2 transmit 1101b UART2 receive ACK2 1110b A D conversion 1111b DMAi Control Register i O 1 b7 b6 b5 b4 b3 UART1 transmit ACK1 b2 bi bO KATT Symbol DMOCON DM1CON Address After Reset 002Ch 00000X00b 003Ch 00000X00b A Transfer Unit Bit 9s 16 bits Repeat Transfer Mode ME Single transfer 0 DMA not requested DMA Request Bit 1 DMA requested 1 Disabled DMA Enable Bit Enabled Source Address Direction Fixed Select Bit 2 Forward Destination Address 0 Fixed Direction Select Bit 2 1 Forward RW Nothing is assigned When write set to 0 When read their contents are O 1 The DMAS bit can be set to 0 by writing 0 in a program This bit remains unchanged even if 1 is written 2 At least one of the DAD and DSD bits must be 0 address direction fixed Figure 12 3 DM1SL Register DMOCON and DM1CON Registers Rev 2 00 Nov 28 2005 page 106 of 378 REJ09B0124 0200 131 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC DMAi Source Pointer i 0 1 b23 b19 b16 b15 b8 b b3 bO b7 bO b7 bo Symbol Address After Reset 7 DODI 01 0 0 0
181. 015Eh 015Fh 0160h 0161h CANO Message Box 14 Identifier DLC CANO Message Box 14 Data Field CANO Message Box 14 Time Stamp CANO Message Box 15 Identifier DLC CANO Message Box 15 Data Field CANO Message Box 15 Time Stamp 0163h CANO Global Mask Register 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h CANO Local Mask A Register COLMAR CANO Local Mask B Register COLMBR Address 0140h O14in Oi42h 0143h ore 0147h 0148h 0149h Oi4An 014Bh_ Oi4Ch O151n 0152h 0153h 0154h 0157h 0158h 0159h Ot5An o15Bh Km 0161h _ 0163h 0164h 0167h 0168h 0169h Ot6An Ot6Dh 016Eh_ ot6Fh 0170h X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov28 2005 page 24 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 7 SFR Information 7 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h
182. 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh O1AEh O1AFh 01BOh 01B1h 01B2h 01B3h 01B4h 01B5h Flash Memory Control Register 1 1 OX00XX0Xb 01B6h 01B7h Flash Memory Control Register 0 1 00000001b 01B8h 00h Address Match Interrupt Register 2 00h 01BAh XOh O1BBh Address Match Interrupt Enable Register 2 XXXXXX00b 01BCh 00h Address Match Interrupt Register 3 00h 01BEh XOh 01BFh X Undefined NOTES 1 These registers are included in the flash memory version Cannot be accessed by users in the mask ROM version 2 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov 28 2005 page 25 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 8 SFR Information 8 Address 01COh Timer B3 B4 B5 Count Start Flag 000XXXXXb 01C1h 01C2h XXh 01C3h 01C4h XXh Timer A2 1 Register XXh Timer A1 1 Register XXh 01C5h 01C6h Timer A4 1 Register XXN Three Phase PWM C
183. 0MHz 1 1 prescaler without software wait Operation Mode Single chip memory expansion and microprocessor modes Single chip mode Address Space 1 Mbyte Memory Capacity See Table 1 3 Product List Peripheral Function Port Input Output 113 pins Input 1 pin Multifunction Timer Timer A 16 bits X 5 channels Timer B 16 bits X 6 channels Three phase motor control circuit Serial Interface 3 channels Clock synchronous UART I C bus IEBus 4 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits X 2 channels DMAC 2 channels CRC Calculation Circuit CRC CCITT CAN Module 2 channels with 2 0B specification Watchdog Timer 15 bits X 1 channel with prescaler Interrupt Internal 34 sources External 12 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequency synthesizer Equipped with a built in feedback resistor Oscillation Stop Detection Function Main clock oscillation stop and re oscillation detection function Electrical Characteristics Supply Voltage VCC 3 0 to 5 5V f BCLK 24MHz VCC 42 to 5 5V f BCLK 20MHz 1 1 prescaler without software wait 1 1 prescaler without software wait Power
184. 1 0001h to FFFFh Count source f1 f2 f8 f32 fC32 Dead Time Count source X p or no dead time p Setting value of the DTT register O1h to FFh Count source f1 f2 f1 divided by 2 f2 divided by 2 Active Level Enable to select H or L Positive and Negative Phase Concurrent Active Disable Function Positive and negative phases concurrent active disable function Positive and negative phases concurrent active detect function Interrupt Frequency NOTE For Timer B2 interrupt select a carrier wave cycle to cycle basis through 15 times carrier wave cycle to cycle basis 1 Forced cutoff with NMI input is effective when the IVPCR 1 bit in the TB2SC register is set to 1 three phase output forcible cutoff by NMI input enabled If an L signal is applied to the NMI pin when the IVPCR1 bit is 1 the related pins go to a high impedance state regardless of which functions of those pins are being used Related pins P7 2 CLK2 TA1OUT V e P7_3 CTS2 RTS2 TA1IN V e P7_4 TA2OUT W CLK4 e P7_5 TA2IN W SOUT4 P8 O TA4OUT U SINA e P8 1 TAA4IN U Rev 2 00 Nov 28 2005 page 138 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM INVOO to INVO7 Bits in INVCO register INV10 to INV15 Bits in INVC1 register DUi DUBi Bits in IDBi register i 0 1 TA1S to TA
185. 1 Memory expansion mode 5 10 Do not set a value 1 1 Microprocessor mode 5 ME RD BHE WR PM02 R W Mode Select Bit 3 RD WRH WAL a this bit to 1 resets the Software Reset Bit microcomputer When read its content is 0 b5b4 0 0 Multiplexed bus is unused Multiplexed Bus Space Separate bus in the entire CS space Select Bit 3 0 1 Allocated to CS2 space 1 0 Allocated to CS1 space 1 1 Allocated to the entire CS space 4 Address output Port P4 0 ES P4 3 Function Port function Select Bit 3 Address is not output 0 BCLK is output PM0O7 de Output Disable 1 BCLK is not output Bit Pin is left high impedance 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable 2 The PMO1 to PMOO bits do not change at software reset watchdog timer reset and oscillation stop detection reset Effective in memory expansion and microprocessor modes Normal ver 3 Effective when the PMO1 to PMOO bits are set to 01b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver These bits are reserved bit in T V ver and set to 0 4 To set the PMO1 to PMOO bits are 01b and the PMOS5 to PM04 bits are 11b multiplexed bus assigned to the entire CS space apply an H signal to the BYTE pin external data bus is 8 bit width While the CNVSS pin is held H VCC do not rewrite the PMO5 to PM04 bits to
186. 10 45 is 2 for 1 wait setting 3 for 2 wait setting and 4 for 3 wait setting f BCLK eee l 3 Calculated according to the BCLK frequency as follows 0 5 X 10 M s So GS 45 ns n is 2 for 2 wait setting 3 for 3 wait setting Rev 2 00 Nov28 2005 page 299 of 378 RENES AS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC 25V Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 13 Timer A Input Counter Input in Event Counter Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 22 14 Timer A Input Gating Input in Timer Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 22 15 Timer A Input External Trigger Input in One shot Timer Mode Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAIIN Input LOW Pulse Width Table 22 16 Timer A Input External Trigger Input in Pulse Width Modulation Mode Standard Symbol Parameter Min MaX tw TAH TAIIN Input HIGH Pulse Width 100 tw TAL TAiIN Input LOW Pulse Width 100
187. 10 4 2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area Table 10 2 lists the relocatable vector tables Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses Rev 2 00 Nov28 2005 page 84 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt Table 10 2 Relocatable Vector Tables Interrupt Source BRK Instruction Vector Address Address L to Address H 0 to 3 0000h to 0003h Software Interrupt Number o Reference M16C 60 M16C 20 16C Tiny Series Software Manual CANO 1 Wake up 9 4 to 7 0004h to 0007h CANO Successful Reception 8 to 11 0008h to 000Bh CANO Successful Transmission 12 to 15 000Ch to 000Fh 19 CAN Module INT3 16 to 19 0010h to 0013h 10 6 INT Interrupt Timer B5 SI O5 20 to 23 0014h to 0017h Timer B4 UART1 Bus Collision Detection 24 to 27 0018h to 001Bh Timer B3 UARTO Bus Collision Detection 28 to 31 001Ch to 001Fh 13 Timers 15 Serial Interface CAN1 Successful Reception SIO4 INT5 32 to 35 0020h to 0023h CO N A A Go Po CAN1 Successful Transmission SIO3 INT4 36 to
188. 12 1x51 CRCIN register Figure 18 1 CRC Circuit Block Diagram CRC Data Register b8 b0 b7 Symbol Address After Reset CRCD 03BDh to 03BCh Indeterminate Seting Range When data is written to the CRCIN register after setting the initial value in the CRCD register the CRC code can 0000h to FFFFh RW be read out from the CRCD register CRC Input Register 2 2 Address After Reset O3BEh Indeterminate Seng Range Data input 00h to FFh RW Figure 18 2 CRCD Register and CRCIN Register Rev 2 00 Nov28 2005 page 221 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CRC Calculation Setup procedure and CRC operation when generating CRC code 80C4h e CRC operation performed by the M16C CRC code Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial X X X 1 1 0001 0000 0010 0001b e Setting procedure 1 Reverse the bit positions of the value 80C4h by program in 1 byte unit 80h Oth C4h gt 23h b15 2 Write 0000h initial value CRCD register 3 Write 01h CRCIN register Two cycles later the CRC code for 80h i e 9188h has its bit positions reversed to become 1189h which is stored in the CRCD register bo CRCD register 4 Write 23h CRCIN
189. 13 Timers Timer Ai Mode Register i O to 4 When not using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi bo Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h TMODO b1 bo TMODI Operation Mode Select Bit Event counter made ti MRO Select Bit 1 Pulse is output TAiOUT pin functions as pulse output i PE Counts falling edge of external signal EE Count Polarity Select Bit Counts rising edge of external signal FRE Up Down Switching A UDF register a ET Select Bit Input signal to TAiOUT pin 3 Le pee Operation Type 0 Reload type TCK1 Can be 0 or 1 when not using two phase pulse signal processing 0 Pulse is not output Pulse Output Function TAiOUT pin functions as I O port 1 During event counter mode the count source can be selected using the ONSF and TRGSR registers 2 Effective when the TAiTGH and TAITGL bits in the ONSF or TRGSR register are 00b TAiIN pin input 3 Count down when input on TAiOUT pin is low or count up when input on that pin is high The port direction bit for TAiOUT pin is set to 0 input mode Figure 13 8 TAOMR to TA4MR Registers in Event Counter Mode when not using two phase pulse signal processing Rev 2 00 Nov28 2005 page 121 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Table 13 3 Specifications in Event Counter M
190. 16C 6NM Hardware Manual Date Summary 291 Figure 21 19 Circuit Application in CAN I O Mode VCC1 and VCC2 are added 293 Table 22 2 Recommended Operating Conditions 1 is partly revised 297 Table 22 4 Electrical Characteristics 1 HOLD and RDY are added to Vr Vr 299 Table 22 12 Memory Expansion Mode and Microprocessor Mode is added 302 to 304 Switching Characteristics are added 306 to 312 Figures 22 5 to 22 11 Timing Diagram 2 to 8 are added 313 to 327 Characteristics of 3 3 V in Normal ver are added 328 to 337 22 2 Electrical Characteristics T V ver is added 339 23 2 External Bus Normal ver only is added 342 23 5 Power Control 4th and 5th items When entering wait mode When entering stop mode are revised 360 Figure 23 4 Use of Capacitors to Reduce Noise is partly revised 361 23 13 A D Converter Last item The applied intermediate is added 367 23 15 Programmable I O Ports 5th and 6th items Indeterminate values When the PMO 1 are added 371 23 19 2 Stop Mode is revised 23 19 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode is partly revised 23 19 8 Operation Speed is revised M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Publication Data Rev 1 00 Sep 30 2004 Rev 2 00 Nov 28 2005 Published by Sales Strategic Planning Div Renesas Technology Corp 2005 Renesas Technology Corp All rights reserved Printed in Japan M16C 6
191. 2 pin when receiving data When an internal clock is selected set the TE bit in the UiC1 register to 1 transmission enabled and write dummy data to the UiTB register and the shift clock will thereby be generated When an external clock is selected set the TE bit to 1 and write dummy data to the UiTB register and the shift clock will be generated when the external clock is fed to the CLKi input pin When successively receiving data if all bits of the next receive data are prepared in the UARTi receive register while the RI bit in the UiC1 register 1 data present in the UiRB register an overrun error occurs and the OER bit in the UiRB register is set to 1 overrun error occurred In this case because the content of the UiRB register is indeterminate a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted Note that when an overrun error occurred the IR bit in the SiRIC register does not change state To receive data in succession set dummy data in the lower order byte of the UiTB register every time reception is made When an external clock is selected the conditions must be met while if the CKPOL bit 0 the external clock is in the high state if the CKPOL bit 1 the external clock is in the low state The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmissio
192. 3 0387h 0388h 116 0389h Timer A1 Register 143 038Ah 116 038Bh Timer A2 Register 143 038Ch 038Dh Timer A3 Register 116 A D Register 6 038Eh 116 038Fh Timer A4 Register 143 Timer BO Register 131 A D Register 4 A D Register 5 A D Register 7 eoo w w C2 O 0 0 m 2 o 2 23 2 Timer B1 Register 131 e C2 AR s A D Control Register 2 Timer B2 Register Timer AO Mode Register 116 A D Control Register 0 ADCONO 204 207 209 Timer A1 Mode Register 119 A D Control Register 1 211 213 215 Timer A2 Mode Register 121 123 146 D A Register 0 220 Timer A3 Mode Register 126 123 Timer A4 Mode Register 128 123 146 D A Register 1 220 Timer BO Mode Register 131 133 Timer B1 Mode Register 134 136 D A Control Register 220 Timer B2 Mode Register Timer B2 Special Mode Register 144 Port P14 Control Register Pull Up Control Register 3 UARTO Transmit Receive Mode Register 154 Port PO Register UARTO Bit Rate Generator 153 Port P1 Register Port PO Direction Register Port P1 Direction Register UARTO Transmit Receive Control Register 0 154 Port P2 Register UARTO Transmit Receive Control Register 1 155 Port P3 Register Port P2 Direction Register Port P3 Direction Register UART1 Transmit Receive Mode Register 154 Port P4 Register UART1 Bit Rate Generator 153 Port P5 Register Port P4 Direction Register Port P5 Direction Register UART1 Transmit Receive Control Register 0 154 Por
193. 3 TB5 ssssasanassssasansssanssassasanauuuuauususouuuuus 131 CSE TESO e E een 86 a r S TB5MR n 131 133 134 136 _ SORIC to S2RIC 5 86 TBS Revecssessscessccssssstessesesssestessesesneee 132 D SOTIC to S2TIC sc ceed 6 TORO TORI cuisine 107 DAO DAY isses 290 S3456TRR u eeecescesessessesseseeseeseesens HOB TROSPLas esi tetendit 118 145 DACONL oues eocatitmcna idet 220 S3BRGto S6BRG 197 DARO DAR1 oii 107 SS3Ct0 S6C oe eects 197 Rev 2 00 Nov28 2005 page 377 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Register Index U UOBCNIC to U2BONIC 86 UOBRG to U2BRG sss 153 VOCO tO UPDU niae 154 lOO io UPON csse darte 155 UOMR to U2MR e 154 WORB to U2RB aucto 153 UOSMR to U2SMR 156 UOSMR2 to U2SMR2 157 UOSMR3 to U2SMRS3 157 UOSMR4 to U2SMRA 158 UOTB to UTE eee eee neers Ree 153 ere Pa NET 156 UP oc UL 117 Ww WDC shee coe 102 WDTS c 102 Rev 2 00 Nov28 2005 page 378 of 378 RENESAS REJ09B0124 0200 REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Rev Date Page Summary 1 00 Sep 30 2004 First edition issued Nov 01 2004 Revised edition issued Revised parts and revised contents are as follows except for expressional change Table 1 2 Per
194. 352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh CAN1 Message Box 14 Identifier DLC CAN1 Message Box 14 Data Field CAN1 Message Box 14 Time Stamp CAN1 Message Box 15 Identifier DLC CAN1 Message Box 15 Data Field CAN1 Message Box 15 Time Stamp 0361h 0363h CAN1 Global Mask Register 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh O036Eh 036Fh 0370h CAN1 Local Mask A Register C1LMAR CAN1 Local Mask B Register C1LMBR Address O340h 0341h 0342h 0343h ET O347h o348n 0349h o34an os4Bh O34Ch 0351h 0352h 0353h 0354h 0357h 0358h 0359h osoAn oseBh O35Ch 0361h 0363h 0364h 0367h 0368h 0369h 036An_ O36Dh 036Eh_ oseFh 0370h X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov 28 2005 page 32 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 15 SFR Information 15 Count Start Flag 00h Clock Prescaler Reset Flag OXXXX
195. 39 0024h to 0027h 19 CAN Module 15 Serial Interface 10 6 INT Interrupt UART2 Bus Collision Detection 9 40 to 43 0028h to 002Bh 15 Serial Interface DMAO 44 to 47 002Ch to 002Fh DMA1 48 to 51 0030h to 0033h 12 DMAC CANO 1 Error 9 0 52 to 55 0034h to 0037h 19 CAN Module A D Key Input O 56 to 59 0038h to 003Bh 16 A D Convertor 10 8 Key Input Interrupt UART2 Transmission NACK2 60 to 63 003Ch to 003Fh UART2 Reception ACK2 9 64 to 67 0040h to 0043h UARTO Transmission NACKO 68 to 71 0044h to 0047h UARTO Reception ACKO 72 to 75 0048h to 004Bh UART1 Transmission NACK1 76 to 79 004Ch to 004Fh UART1 Reception ACK1 9 80 to 83 0050h to 0053h 15 Serial nterface Timer AO 84 to 87 0054h to 0057h Timer A1 88 to 91 0058h to 005Bh 13 Timers Timer A2 INT7 9 492 to 95 005Ch to 005Fh 13 Timers Timer A3 INT6 96 to 99 0060h to 0063h 10 6 INT Interrupt Timer A4 100 to 103 0064h to 0067h 13 Timers Timer BO SI O6 9 104 to 107 0068h to 006Bh 13 Timers 15 Serial Interface Timer B1 INT8 9 108 to 111 006Ch to 006Fh 13 Timers 10 6 INT Interrupt Timer B2 112 to 115 0070h to 0073h 13 Timers INTO 116 to 119 0074h to 0077h INT1 120 to 123
196. 4 1 VREF XIN P7 1 P9 1 0 3 to 6 5 PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 0 3 to VCC 0 3 P3_0 to P3 7 PA Oto P4 7 P5 Oto P5 7 P6_0 to P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10 0toP10 7 P11 OtoP11 7 P12 OtoP12 7 P13 0 to P13 7 P14 0 P14 1 XOUT P7 1 P9 1 0 8 to 6 5 Power Dissipation 700 Operating Ambient When the Microcomputer is Operating 40 to 85 Temperature Flash Program Erase 0 to 60 Storage Temperature 65 to 150 NOTE 1 Ports P11 to P14 are only in the 128 pin version Rev 2 00 Nov28 2005 page 292 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 22 2 Recommended Operating Conditions 1 Parameter Supply Voltage VCC1 VCC2 22 Electric Characteristics Normal ver Standard Typ Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input P3 1 to P3 7 P4_0 to P4 7 P5_0 to P5 7 P6_0 to P6 7 Voltage P7 0 P7 2 to P7 7 P8 0 to P8 7 P9 0 P9 2 to P9 7 P10_0 to P10 7 P11_0 to P11 7 P12 0 to P12 7 P13_0 to P13 7 P14 0 P14 1 XIN RESET CNVSS BYTE P7 1 P9 1 PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 During single chip mode PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 Data input during me
197. 4 1 lists the specifications of the three phase motor control timer function Figure 14 1 shows the block diagram for three phase motor control timer function Also the related registers are shown on Figures 14 2 to 14 8 Table 14 1 Three Phase Motor Control Timer Function Specifications Three Phase Waveform Output Pin Specification Six pins U U V V W W Forced Cutoff Input Input L to NMI pin Used Timers Timer A4 A1 A2 used in the one shot timer mode Timer A4 U and U phase waveform control Timer A1 V and V phase waveform control Timer A2 W and W phase waveform control Timer B2 used in the timer mode Carrier wave cycle control Dead time timer 3 eight bit timer and shared reload register Dead time control Output Waveform Triangular wave modulation Sawtooth wave modification e Enable to output H or L for one cycle Enable to set positive phase level and negative phase level respectively Carrier Wave Cycle Triangular wave modulation count source X m 1 X 2 Sawtooth wave modulation count source X m 1 m Setting value of the TB2 register 0000h to FFFFh Count source f1 f2 f8 f32 fC32 Three Phase PWM Output Width Triangular wave modulation count source X n X 2 Sawtooth wave modulation count source X n n Setting value of the TA4 TA1 and TA2 registers of the TAA TA44 TA1 TA11 TA2 and TA21 registers when setting the INV11 bit to
198. 4S Bits in TABSR register PWCON Bits in TB2SC register 14 Three Phase Motor Control Timer Function ICTB2 Register n 1 to 15 Value to be written to INVOS bit INVO1 INV11 INVOO Reload Control Signal for Timer A1 Circuit to set Interrupt Write signal to INVO3 bit T Generation Frequency RESET Timer B2 NMI Interrupt 5 Request Bit ICTB2 Counter n 1 to 15 Timer B2 Underflow Timer Mode Write signal to Timer B2 Start Trigger Signal for Timers A1 A2 A4 f1 or f2 INVO7 INV10 Reload Control Signal for Timer A4 Timer A4 One Shot Pulse When setting the TA4S bit to 0 signal is set to 0 Reload Control Signal for Timer A1 Timer A1 One Shot Pulse When setting the TA1S bit to 0 signal is set to 0 Reload Control Signal for Timer A2 Timer A2 One Shot Pulse When setting the TA2S bit to 0 signal is set to 0 NOTE INVO6 Transfer Trigger Reload Register n 1 to 255 Trigger Dead Time Timer n 1 to 255 U phase Output Control Circuit Three Phase Output Shift Register U Phase Dead Time Timer n 1 to 255 a gt o V Phase Output Control Circuit W Phase Output Control Circuit Inverse Control W Phase Output Signal Switching to P8_0 P8_1 and P7_2 to P7_5 is not shown in this diagram 1 Transfer trigger is generated only when the IDBO and IDB1 registers are set and the first timer B2 underfl
199. 5 Reserved Bt Bit Reserved Bt Set o to Setow o PCLK5 Pin Function Swirch Bit n SUD odaii Software Interrupt Number SFR 0 Normal mode PCLK6 Location Switch Bit 1 Swiching mode 2 PCLK7 A D Clock Direct Input Bit i Su d m 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 If this bit is set to 1 the software interrupt number and SFR location can b changed as follows 1 Software interrupt number of the key input interrupt in the vector table can be changed from 14 to 13 No 13 is changed from the CANO 1 error interrupt to the CANO 1 error key input interrupt No 14 is changed from the A D key input interrupt to the A D interrupt 2 Address of the KUPIC register in the SFR can be changed from 004Eh to 004Dh Address 004Dh is changed from the CO1ERRIC register to the CO1ERRIC KUPIC register Address 004Eh is changed from the ADIC KUPIC register to the ADIC register 3 When this bit 1 the A D clock is set to divide by 1 of fAD mode regardless of whether the PCLKO bit is set 4 When the PCLKS5 bit and the SM43 bit in the S4C register 1 the pin function of SI O4 can be changed as follows P8 O TA4OUT U SINA P7_5 TA2IN W SOUT4 P7 AITA2OUT W CLKA 5 SI O5 and SI O6 are only in the 128 pin version Figure 8 5 PCLKR Register Rev 2 00 Nov28 2005 page 61 of 378 RENESAS REJ09B0124 0200 Under development This document is under developm
200. 5ns max Id BCLK AD Ta BCLK ALE i i 25ns max gt MC 4ns min i Measuring conditions e VCC 5V e Input timing voltage th BCLK ALE 5 X tcyc 15 ns min tac3 RD DB 1 5x tcyc 45 ns max i ta BCLK RD i gt 25ns max i 0 5 X tcyc 10 ns min coer Data input th BCLK CS thiRD cs gt 4ns min i i 4 Address 74 gt gt th RD DB tSU DB RD Ons min 40ns min th BCLK AD 4ns min 1 th BCLK RD aa Ons min th BCLK cs gt 4ns min th BCLK DB 4ns min gt 1 1 1 D D 1 i i P ta DB WR 1 5 X tcyc 40 ns min td AD wR 4 Ons min Vit 0 8 V ViH 2 0 V e Output timing voltage VoL 0 4 V VoH 2 4 V Figure 22 10 Timing Diagram 7 Rev 2 00 Nov28 2005 page 311 of 378 REJO9BO0124 0200 131 NESAS th wR DBy 0 5 X tcyc 10 ns min 1 th BCLK AD 4ns min 1 th wR AD 0 5 X tcyc 10 ns min th BCLK WR Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode For 3 wait setting external area access and multiplexed bus selection Read timing _tcyc i E E 1 th RD CS 1 0 5 X tcyc 10 ns min i i th BCLK cs td BCLK CS 1 1 4ns min i n i i i 25ns max it gt ta AD ALE 0
201. 9 13 CAN SFR REgIStErS siete eerie itte eee eei a a taii Leda esae isa uterus elects deut teed 224 192 CAN Message BOX C ne adadaees 225 19 3 Acceptance Mask Registers sssessssssssseeeseeee eene enne nennen enn nhnner nnne nnne nennen 227 19 4 CAN SERCR6GISIBIS eee itte tete te inrer a te Re dad Rate uve Sopa Bate gura EE a ia aa 228 19 5 Operational M OGSS abet vssisdsenecupee 234 19 5 1 CAN Reset Initialization Mode ssssssssssseseeeeeeeeeeneneenne enne ennt rnnt nennen 234 19 5 2 CAN Operation MOde nite esci edere pea oe a a ea ae SERES s cR aR ruS 235 19 53 CAN Sleep MOG 235 19 5 4 CAN Interface Sleep Mode sssssssssssssseeeseeeeeneeee nme een nnns etre nnne nnns nennen 235 19 5 5 zcxe mice EET 236 19 6 Configuration CAN Module System CIock ssssssssssssssssseseeneeee nnne entren nnne nnne nennen 237 19 7 Bit Timing Configuration serisinin aaia ioie es nnen nnn nnn nenne set aE AEE aaea 237 19 8 BIETSTO ite ete eteuidaunte tutus timui HELL d e tee LEE 238 19 8 1 CalCulation Of Bit fate vc EH 238 19 9 Acceptance Filtering Function and Masking Function 239 19 10 Acceptance Filter Support Unit ASU 0 c eee ccc e cee eee eneeeeeeeeeeeaeeeeeeaeeseaaeeeseaeeeseaeeeseaeeeseeesseaeeeseeees 240 1 9 11
202. 9 CAN1 Message Box 0 Data Field CAN1 Message Control Register 10 CIMCTL10 CAN1 Message Control Register 11 CIMCTL11 CAN1 Message Control Register 12 CIMCTL12 CAN1 Message Control Register 13 CIMCTL13 CAN1 Message Control Register 14 CIMCTL14 CAN1 Message Control Register 15 CIMCTL15 0231h CAN1 Control Register C1CTLR Sese CAN1 Status Register C1STR CAN1 Message Box 1 Identifier DLC 0233h 0234h O235h CANI Slot Status Register C1SSTR _ CAN Interrupt Control Register C1ICR 0238h 0239h CAN1 Extended ID Register CAIDR 023Ah CAN1 Message Box 1 Data Field 023Bh CAN1 Configuration Register C1CONR 023Ch CANO Extended ID Register CAN1 Message Box 0 Time Stamp CAN1 Receive Error Count Register CIRECR 023Dh CAN1 Transmit Error Count Register_ C1TECR 233 E CAN1 Time Stamp Register C1TSR 233 027Fh CAN1 Message Box 1 Time Stamp The blank areas are reserved B 5 Symbol CAN1 Message Box 2 Identifier DLC CAN1 Message Box 2 Data Field 028Fh CAN1 Message Box 2 Time Stamp 0290h eo N c A a e N c N 2 CAN1 Message Box 3 Identifier DLC CAN1 Message Box 3 Data Field CAN1 Message Box 3 Time Stamp oo NIN gt gt N 2 CAN1 Message Box 4 Identifier DLC Qo N gt AIC olo ioo m IMS P gt gt gt NO a S a CAN1 Message Bo
203. 99 11 Watchdog TVET RR c PUPC 101 11 1 Count Source Protective Mode sssssssssssssseeses eene nennen rnnt reset nnns rnnt n entren inneren nnns 102 12 DMAC c e 103 12 TRAMSTOR GY IER e 108 12 1 1 Effect of Source and Destination Addresses sssssssssssseseseseeeeeenneeeneennn nene 108 12 1 2 Effect of BYTE Pin Level eese reote rone htt ocio cure Lune tour nanus a HR RE ANEA EEEE RANES 108 12 1 3 Effect of Software Waitsa iisa pP ege eiie tud bue uie eee eae 108 12 1 4 Effect of RDY Signal oxssexidiicata nter tucked M t bs c s tv pk bna vae 108 122 DMA Transter Gy ClOS cm 110 12 3 DMA Enable seeren EREE VE EAEE AER aE SEEEN ESEESE 111 eaa a a e a DEED IL E E E E T E E E T 111 12 5 Channel Priority and DMA Transfer TIMINg isisisi a eanan 112 13 TIME T m TOE 113 ES E E E A E T 115 LEN cm 119 13 12 Event Counter Mode isis iu concierto ce rut aet esce dave aca HERE E RE ceo 2a yc X Xa Y Rz 120 13 1 3 One Shot Timer MOdle 3 ste reete e pa ERI EXE ER EUER Rn SERE YEN E reed DE n ERE RA a eee 125 13 1 4 Pulse Width Modulation PWM Mode esssssssseseeeeeeeneeen nennen nennen nnne nnns entren nnns nre 127 ucc UU UR UE 130 19 2 1 Timer Mode sing eter tette ne Maori eco bxc utar eda i lun eteskun esie AES 133 13 2 2 Event Counter Mode niii ere I Re FERE anaa ERR RR ODE
204. 9B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 14 3 Suggestions to Reduce Power Consumption When not performing CAN communication the operation mode of CAN transceiver should be set to standby mode or sleep mode When performing CAN communication the power consumption in CAN transceiver in not performing CAN communication can be substantially reduced by controlling the operation mode pins of CAN transceiver Tables 23 4 and 23 5 show recommended pin connections Table 23 4 Recommended Pin Connections In case of PCA82C250 Philips product Standby Mode Rs Pin High speed Mode i d Power Consumption in less than 170 pA CAN Transceiver less than 70 mA CAN Communication impossible possible Connection M16C GNK M16C 6NM PCA82C250 H output i 2 0 1 NOTES M16C 6NK M16C 6NM PCA82C250 L output 1 The pin which controls the operation mode of CAN transceiver 2 In case of Ta 25 C 3 Connect to enabled port to control CAN transceiver Table 23 5 Recommended Pin Connections In case of PCA82C252 Philips product Sleep Mode STB Pin Normal Operation Mode H EN Pin H Power Consumption in less than 50 uA CAN Transceiver less than 35 mA CAN Communication impossible possible Connection M16C 6N
205. AD ke 4ns min th wR AD 0 5 X tcyc 10 ns min Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode For 3 wait setting external area access and multiplexed bus selection Read timing i i i y A i i i i th RD cs th BCLK Cs 0 5 X tcyc 10 ns min 6ns min i 1 o i i i i i i i i i i 1 i i i i i i i i i ta BCLK CS 1 40ns max i rod H i i i i ta AD ALE 0 5 X tcyc 40 ns min th ALE AD 14 3 59 4 ln 5 X tcyc 15 ns min I E 1 _ Data input REEL i th RD DB dc Ti ADi DBi 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T 1 1 i T taz RD AD j td BCLK AD 8ns max taca RD DB i tSU DB RD onsin th BCLK AD 40ns max aa 2 5 X tcyc 60 ns max 50ns min f 1 a 4ns min ADi oe ip emm oj s Pe BHE no multiplex i td BCLK ALE 40ns max th RD AD j 0 5 X tcyc 10 ns min NE th BCLK RD ta BCLK RD Ons min 1 40ns max ih BCLK CS 1 i i i i 4ns min 1 th WR CS 40ns max 0 5 X tcyc 10 ns min e td BCLK CS i th BCLK DB 1 i ta BCLK DB 1 3 50ns max 1 4ns min h i i i i i 1 1 l i i 1 i i i i i i i i i i i i i
206. AM Capacity Package Type Remarks M306NKFHGP M306NMFHGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A Flash PLQP0128KB A M306NKFJGP M306NMFJGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A memory version PLQP0128KB A M306NKFHT GP M306NMFHTGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFJTGP M306NMFJTGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFHVGP M306NMFHVGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFJVGP M306NMFJVGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A Normal ver M306NKME XXXGP M306NMME XXXGP 192 Kbytes 16 Kbytes PLQP0100KB A Mask PLQP0128KB A M306NKMG XXXGP M306NMMG XXXGP D Under development NOTE 256 Kbytes 20 Kbytes PLQP0100KB A PLQP0128KB A 1 In the flash memory version there is 4 Kbyte space block A Type No M30 6N KM GT XXX GP L Package type ROM version Normal ver GP Package PLQP0100KB A PLQP0128KB A ROM No Omitted on flash memory version Characteristics no Normal ver T V ROM capacity E 192 Kbytes G 256 Kbytes H 384 Kbytes J 512 Kbytes Memory type M Mask ROM version F Flash memory version T ver Automotive 85 C version V ver Automotive 125 C version Shows the number of CAN module pin co
207. AN1 Message Box 10 Data Field CAN1 Message Box 14 Data Field CAN1 Message Box 10 Time Stamp CAN1 Message Box 14 Time Stamp 030Fh 0310h 034Fh 0350h e oo Eire are F Q c1 A E e wo k Nm 2 eo C3 c N 2 CAN1 Message Box 11 Identifier DLC CAN1 Message Box 15 Identifier DLC e wo A wo 2 OO Gla w CO CO GO k k k K NY OQ On amp aja 5 gt e oo pire co 2 CAN1 Message Box 11 Data Field CAN1 Message Box 15 Data Field oo C3 C9 AL Ke 5s CAN1 Message Box 11 Time Stamp CAN1 Message Box 15 Time Stamp oo C3 C2 m a a gt CAN1 Message Box 12 Identifier DLC CAN1 Global Mask Register 99 wo o 9 ze oojo o olo o C3 G2 CO CO GO CO CO PO PDO POPP PO PO PO NIDIA N 2 2 2 25 2 25 2 Ce o oO ojo o w QOO NO Ou amp aja sa a gt e C2 N 2 CAN Local Mask A Register C1LMAR e C2 N Ke 2 CAN1 Message Box 12 Data Field CAN1 Message Box 12 Time Stamp CAN1 Local Mask B Register C1LMBR CAN1 Message Box 13 Identifier DLC The blank areas are reserved B 7 Symbol Symbol Count Start Flag 117 132 145 i Clock Prescaler Reset Flag 118 132 AD Hogisigre One Shot Start Flag 118 Trigger Select Register 118 145 Up Down Flag 117 A D Register 1 A D Register 2 Timer AO Register 116 A D Register
208. AS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 21 Noise Connect a bypass capacitor approximately 0 1 uF across the VCC1 and VSS pins and VCC2 and VSS pins using the shortest and thicker possible wiring Figure 23 11 shows the bypass capacitor connection Bypass Capacitor Connecting Pattern Connecting Pattern M16C 6N Group M16C 6NK M16C 6NM Connecting Pattern N Connecting Pattern Bypass Capacitor Figure 23 11 Bypass Capacitor Connection Rev 2 00 Nov28 2005 page 374 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Appendix 1 Package Dimensions Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP100 14x14 0 50 PLQP0100KB A 100P6Q A FP 100U FP 100UV 0 6g NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 2 DOES NOT INCLUDE TRIM OFFSET bp 1 IReference Dimension in Millimeters 8i Symbol Min
209. AVE qa aa AREE EL nerd 134 13 2 3 Pulse Period and Pulse Width Measurement Mode sssesemm e 135 14 Three Phase Motor Control Timer Function 0 cccecceeeeeeeeeeceeeeeeeeeeeeaeceeeeeeeeseneeeeeeees 138 15 Senal ILS tare ditesadeku bx nennen araea a aieiaiei Aii ea arataa E UR pap era d DUE 149 jii 149 15 1 4 Clock Synchronous Serial VO MOGeO rte tdt e ete euren crecer ee tente eue ea Ru emp 159 15 1 2 Clock Asynchronous Serial I O UART Mode sssssessseseeeeneeneenn nennen enne 167 15 1 3 Special Mode 1 IC Mode 175 15 14 Special MOGE e araa a a NA E HE 184 15 1 5 Special Mode 3 IE Mode sssssssssssseeeeeeeneennenee nennen nennen nenne en rnn sen nn sinn entree 189 15 1 6 Special Mode 4 SIM Mode UART2 sssesssesseseeeeseseee enne p a aa a dada enitn nnn 191 15 2 SW ON e eeas 196 15 241 Sl Ot Operatiorr TIMING i sous ta reor tirer ona eed eels evan eu poda xoa be tea las ose gta aee dee cx 200 15 2 2 CLK Polarity Selection iiie dede uii eri e erred Rene deca eX i ie 200 15 2 3 Functions for Setting an SOUTi Initial Value sssssssssesee eene 201 A 3 T6 A D Converter sie cocto oerte eeu duobus dice vetus rau sued a a tenu a D mes e aet euntes aoi uu Sade 202 16 1 Mode DoscriplON ee Em 206 diss Onesshot mp 206 16 1 2 Repeat MOMS certio
210. All maskable interrupts are disabled Rev 2 00 Nov 28 2005 page 88 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 5 4 Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt request is generated during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt request is generated during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence The CPU behavior during the interrupt sequence is described below Figure 10 5 shows time required for executing the interrupt sequence 1 The CPU obtains interrupt information interrupt number and interrupt request level by reading address 000000h Then the IR bit applicable to the interrupt information is set to O interrupt requested 2 The FLG register prior to an interrupt sequence is saved to a temporary register within the CPU 3 The I D and U flags in the FLG register become as follows
211. B5h OOB6h 00B7h OOB8h OOB9h OOBAh CANO Message Box 5 Data Field OOBBh OOBCh OOBDh OOBEh p OOBFh CANO Message Box 5 Time Stamp X Undefined Address 0080h oo8in oo82n 0083h E 0087h oo88h 0089h 008Ah_ oo8Bh 008Ch_ 0091h 0092h 0093h ooer 0097h 0098h oo99n oo9An oooBh Km ooA h ooA2n ooASh ooA4n OoA7h OoA8h OoAoh OoABh OoACh ooB1n ooBen ooB3h oogen O0B7h ooBah ooBon ooBAh ooBBh cose ooBFh Rev 2 00 Nov28 2005 page 21 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 4 SFR Information 4 Address 00COh 00C1h gocan CANO Message Box 6 Identifier DLC 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h CANO Message Box 6 Data Field OOCAh OOCBh 00CCh 00CDh OOCEh VER OO0CFh CANO Message Box 6 Time Stamp 00DOh 00D1h 00D2h f O0D3h CANO Message Box 7 Identifier DLC 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h i OODAh CANO Message Box 7 Data Field OODBh 00DCh OODDh OODEh m O0DFh CANO
212. C 6NM 16 A D Converter A D Control Register 0 ppp Symbol Address After Reset LLnL 2e UM 0000000 St Symbol Analog Input Pin Select Bit Invalid in single sweep mode MDO A D Operation Mode b4b3 MDi Select Bit 0 10 Single sweep mode Software trigger ore Trigger Select Bit ADTRG trigger A D conversion disabled Refer to NOTE 2 for ADCON2 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bO LDBLLISLL acon oom ton Bi Syma When single sweep mode is selected b1 bO 00 ANO AN1 2 pins A D Sweep Pin Select Bit 0 1 ANO to AN3 4 pins 10 ANO to ANS 6 pins 1 ANO to AN7 8 pins 2 MD2 A D Operation Mode Set to 0 when single sweep mode RW Select Bit 1 is selected 0 8 bit mode BITS 8 10 Bit Mode Select Bit 4 10 bit mode Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 3 1 VREF connected b7 b6 RW External Op Amp i i ANEXO and ANEX1 are not used Do not set a value Connection Mode Bit 1 0 Do not set a value 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON register to select the desired pin 3 If the VCUT bit is reset from 0
213. CM20 bit to 0 disable before entering stop mode After exiting stop mode set the CM20 bit back to 1 enable Set the CM20 bit to 0 disable before setting the CMO5 bit in the CMO register When the CM20 bit is 1 oscillation stop re oscillation detection function enabled the CM27 bit is 1 oscillation stop re oscillation detection interrupt and the CPU clock source is the main clock the CM21 bit is set to 1 on chip oscillator clock if the main clock stop is detected If the CM20 bit is 1 and the CM23 bit is 1 main clock turned off do not set the CM21 bit to 0 Effective when the CMO7 bit in the CMO register is 0 Where the CM20 bit is 1 oscillation stop re oscillation detection function enabled the CM27 bit is 1 oscillation stop re oscillation detection interrupt and the CM11 bit is 1 the CPU clock source is PLL clock the CM21 bit remains unchanged even when main clock stop is detected If the CM22 bit is 0 under these conditions an oscillation stop re oscillation detection interrupt request is generated at main clock stop detection it is therefore necessary to set the CM21 bit to 1 on chip oscillator clock inside the interrupt routine This bit is set to 1 when the main clock is detected to have stopped and when the main clock is detected to have restarted oscillating When this bit changes state from O to 1 an oscillation stop and re oscillation detection interrupt reque
214. Control Register 7 C1MCTL7 CAN1 Message Control Register 8 C1MCTL8 CAN1 Message Control Register 9 C1MCTL9 CAN1 Message Control Register 10 C1MCTL10 00h CAN1 Message Control Register 11 C1MCTL11 00h CAN1 Message Control Register 12 C1MCTL12 00h CAN1 Message Control Register 13 C1MCTL13 00h CAN1 Message Control Register 14 C1MCTL14 00h CAN1 Message Control Register 15 C1MCTL15 00h 0230h X0000001b 0231h CAN1 Control Register C1CTLR XX0X0000b 0232h 00h 0233h CAN1 Status Register C1STR X0000001b 0234h 00h 0235h CAN Slot Status Register C1SSTR Ooh 0236h 00h 0237h CAN1 Interrupt Control Register C1ICR Ooh 0238h 00h 0239h CAN1 Extended ID Register C1IDR 00h 023AN_ Cant Configuration Register C1CONR on CAN1 Receive Error Count Register C1RECR CAN1 Transmit Error Count Register C1TECR CAN1 Time Stamp Register C1TSR X Undefined Rev 2 00 Nov28 2005 page 27 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 10 SFR Information 10 0240h 0241h 0242h XXh 0243h CANO Acceptance Filter Support Register o 0244h e CAN1 Acceptance Filter Support Register XXh Peripheral Clock Select Register CANO 1 Clock Select Register 0260h 0261h 0262h CAN1 Message Box 0 Identifier DLC
215. D Address output hold time refers to RD NOTE 1 h wR AD Address output hold time refers to WR NOTE 1 ta gcuk cs Chip select output delay time tnBcuk cs Chip select output hold time refers to BCLK 4 tn RD CS Chip select output hold time refers to RD NOTE 1 tniwR cs Chip select output hold time refers to WR NOTE 1 ta BcLk RD RD signal output delay time thiBcLk RD RD signal output hold time tagcu wR WR signal output delay time thecLk wR WR signal output hold time taBcLk bB Data output delay time refers to BCLK tnBcuk oB Data output hold time refers to BCLK 4 ta DB wr Data output delay time refers to WR NOTE 2 th wR DB Data output hold time refers to WR NOTE 1 taecik Hioa HLDA output delay time taBcLk aLe ALE signal output delay time refers to BCLK thiBcLk ALeE ALE signal output hold time refers to BCLK 4 ta AD ALE ALE signal output delay time refers to Address NOTE 3 th ALE AD ALE signal output hold time refers to Address NOTE 4 ta aD RD RD signal output delay from the end of Address 0 ta AD WR WR signal output delay from the end of Address 0 taziRb AD Address output floating start time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 Beck OPS 2 Calculated according to th
216. DO CKDIR Bits in UOM CLK1 to CLKO CKPOL CRD CRS RCSP Bit in UCON register R register Bits in UOCO register Figure 15 1 UARTO Block Diagram Main clock PLL clock or on chip oscillator clock UART1 RXD polarity reversing RXD1 O circuit Clock source selection CLK1 to CLKO f1S10 or f2sio 99 l CKDIR PCLK1 Ho gt f8SIO La f32SIO Receive clock Transmit clock 1 9 f1SIO or f2SIO Transmit receive unit TXD 010 100 101 110 146 L Clock synchronous type 001 internal U1BRG UART reception SMD2 to SMDO Reception Receive clock control circuit fssio OU register UART transmission fa2sio 9 Lo 1 n1 1 External type yP 001 Wig 910 100 101 110 Clock synchronous So i Transmission Transmit clock control circuit Clock synchronous ty 12 Clock synchronous type when external clock is selected when internal clock is selected 0 pe R o CKPOL CLK Clock synchronous type CLKMDO when internal clock is selected polarity reversing circuit CLK1O aie 4 Clock output pin select CTS1 RTS1 CTSO0 CLKS1 1 CTS RTS selected CTS RTS disabled RTS1 1 e VSS 919 oe
217. Di pin i 0 to 2 output level and RXDi pin input level do not match a UARTi bus collision detect interrupt request is generated Use the IFSRO6 and IFSRO bits in the IFSRO register to enable the UARTO UART 1 bus collision detect function Table 15 16 Registers to Be Used and Settings in IE Mode Register 0 to 8 Set transmission data 0 to 8 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 110b CKDIR Select the internal clock or external clock STPS Set to 0 PRY Invalid because the PRYE bit 0 PRYE Set to 0 IOPOL Select the TXD RXD input output polarity CLK1 CLKO Select the count source for the UiBRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output mode CKPOL Set to 0 UFORM Set to 0 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Select the source of UART2 transmit interrupt U2RRM UiLCH UiERE Set to 0 0 to 3 7 Set to 0 ABSCS Select the sampling timing at which to detect a bus collision ACSE Set this bit to 1 to use the auto clear function of transmit en
218. Error LM 0 Bus error interrupt disabled Enable Bit 2 1 Bus error interrupt enabled Sleep Late 0 Sleep mode disabled Sleep RW Select Bit 2 1 Sleep mode enabled clock supply stopped PortE an m Enable 0 I O port function otEn ec 1 CTX CRX function MsgOrder Nothing is assigned When write set to 0 When read its content is indeterminate 1 When the Reset bit is set to 1 CAN reset initialization mode check that the State Reset bit in the CiSTR register is set to 1 Reset mode 2 Change this bit only in the CAN reset initialization mode 3 When using CANO 1 wake up interrupt set these bits to 1 b8 bo Symbol Address After Reset COCTLR 0211h XX0X0000b C1CTLR 0231h XX0X0000b b1 bO 0 0 Period of 1 bit time 0 1 Period of 1 2 bit time 1 0 Period of 1 4 bit time 1 1 Period of 1 8 bit time Time Samp Counter 0 Nothing is occurred Teens Reset Bit 1 1 Force reset of the time stamp counter PW Return From ee Off 0 Nothing is occurred HaIBUSENT Command Bit 2 1 Force return from bus off aw Nothing is assigned When write set to 0 When read its content is indeterminate b4 E RXOnI Listen a Mode _ 0 Listen only mode disabled y Select Bit 3 1 Listen only mode enabled 4 Time Stamp TSPreScale Prescaler 3 Nothing is assigned When write set to O b7 b6 When read their contents are indeterminate 1 When the TSReset bit 1 the CiTSR register is set to 0000h
219. F4h ID6 DBC vector OFFFFBh to OFFFF8h ID7 NMI vector OFFFFFh to OFFFFCh ROMCP Reset vector Figure 21 3 Address for ID Code Stored Rev 2 00 Nov 28 2005 page 263 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 CPU Rewrite Mode In CPU rewrite mode the user ROM area can be rewritten when the CPU executes software commands The user ROM area can be rewritten with the microcomputer is mounted on a board without using a parallel serial or CAN programmer In CPU rewrite mode only the user ROM area shown in Figure 21 1 can be rewritten The boot ROM area cannot be rewritten Program and the block erase command are executed only in the user ROM area Erase write 0 EWO mode and erase write 1 EW1 mode are provided as CPU rewrite mode Table 21 3 lists the differences between EWO and EW1 modes Table 21 3 EWO Mode and EW1 Mode Operation Mode Single chip mode Single chip mode e Memory expansion mode 3 Boot mode Space where Rewrite User ROM area User ROM area Control Program can be e Boot ROM area Placed Space where Rewrite The rewrite control program must be The rewrite control program can be Control Program can be transferred to any space other than the executed in the user ROM area Executed flash memory e g RAM before being executed Space which can be
220. ID codes sent from the serial programmer matches those written in the flash memory Refer to 21 2 Functions to Prevent Flash Memory from Rewriting Rev 2 00 Nov 28 2005 page 282 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version Table 21 7 Pin Functions for Standard Serial I O Mode VCC1 VCC2 VSS Power supply input Description Apply the Flash Program Erase Voltage to VCC1 pin and VCC2 to VCC2 pin The VCC apply condition is that VCC2 VCC1 Apply 0 V to VSS pin CNVSS Connect to VCC1 pin Reset input Reset input pin While RESET pin is L level input 20 cycles or longer clock to XIN pin Clock input XOUT Clock output Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin and open XOUT pin BYTE BYTE Connect this pin to VCC1 or VSS AVCC AVSS Analog power supply input Connect AVCC to VCC1 and AVSS to VSS respectively VREF Reference voltage input Enter the reference voltage for A D and D A converters from this pin PO 0to PO 7 Input port PO Input H or L level signal or open P1 Oto P1 7 Input port P1 Input H or L level signal or open P2 0to P2 7 Input port P2 Input H or L lev
221. INT6 to INT8 CLK5 CLK6 SIN5 and SING are only in the 128 pin version Rev 2 00 Nov 28 2005 page 295 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 5 Electrical Characteristics 2 Standard Min Typ Max Parameter Measuring Condition Power Supply Output pins are open Mask ROM f BCLK 24MHz Current and other pins are VSS PLL operation VCC 3 0 to 5 5V No division On chip oscillation No division Flash Memory f BCLK 24MHz PLL operation No division On chip oscillation No division Flash Memory f BCLK 10MHz Program VCC 5V Flash Memory f BCLK 10MHz Erase VCC 5V Mask ROM f BCLK 32kHz Low power dissipation mode ROM Flash Memory f BCLK 32kHz Low power dissipation mode RAM f BCLK 32kHz Low power dissipation mode Flash memory Mask ROM On chip oscillation Flash Memory Wait mode f BCLK 32kHz Wait mode 3 Oscillation capacity High f BCLK 32kHz Wait mode 3 Oscillation capacity Low Stop mode Topr 25 C NOTES 1 Referenced to VCC 3 0 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 24MHz unless otherwise specified 2 This indicates the memory in which the program to be executed exists 3 With
222. K M16C 6NM 15 Serial Interface 15 1 3 4 Transfer Clock Data is transmitted received using a transfer clock like the one shown in Figure 15 24 The CSC bit in the UISMR2 register is used to synchronize the internally generated clock internal SCLi and an external clock supplied to the SCLi pin In cases when the CSC bit is set to 1 clock synchronization enabled if a falling edge on the SCLi pin is detected while the internal SCLi is high the internal SCLi goes low at which time the value of the UiBRG register is reloaded with and starts counting in the low level interval If the internal SCLi changes state from low to high while the SCLi pin is low counting stops and when the SCLi pin goes high counting restarts In this way the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin signal The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit To use this function select an internal clock for the transfer clock The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from low level output at the falling edge of the 9th clock pulse If the SCLHI bit in the UISMR4 register is set to 1 enabled SCLi output is turned off placed in the high impedance state when a stop condition is detected Setting the SWC2 bit in the UiISMR2 register 1 0 output makes it possible to forcibly
223. K M16C 6NM PCA82C252 i output i 2 0 1 NOTES M16C 6NK M16C 6NM PCA82C252 H output 1 The pin which controls the operation mode of CAN transceiver 2 Ta 25 C 3 Connect to enabled port to control CAN transceiver Rev 2 00 Nov28 2005 page 365 of 378 31 NE SAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 14 4 CAN Transceiver in Boot Mode 23 Usage Precaution When programming the flash memory in boot mode via CAN bus the operation mode of CAN transceiver should be set to high speed mode or normal operation mode If the operation mode is controlled by the microcomputer CAN transceiver must be set the operation mode to high speed mode or normal operation mode before programming the flash memory by changing the switch etc Tables 23 6 and 23 7 show pin connections of CAN transceiver Table 23 6 Pin Connections of CAN Transceiver In case of PCA82C250 Philips product Standby Mode Rs Pin High speed Mode SL CAN Communication impossible possible Connection M16C 6NK M16C 6NM PCA82C250 i 0 1 NOTES M16C 6NK M16C 6NM PCA82C250 Switch ON 1 The pin which controls the operation mode of CAN transceiver 2 Connect to enabled port to control CAN transceiver Table 23 7 Pin Connections of CAN Transceiver In case of PCA82C252 Philips product
224. L clock becomes stable tsu PLL L Set the CM11 bit to 1 PLL clock for the CPU clock source NOTE 1 PLL operation mode can be entered from high speed mode Figure 8 11 Procedure to Use PLL Clock as CPU Clock Source Rev 2 00 Nov28 2005 page 67 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 2 CPU Clock and Peripheral Function Clock Two type clocks CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions 8 2 1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer The clock source for the CPU clock can be chosen to be the main clock sub clock on chip oscillator clock or the PLL clock If the main clock or on chip oscillator clock is selected as the clock source for the CPU clock the selected clock source can be divided by 1 undivided 2 4 8 or 16 to produce the CPU clock Use the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to select the divide by n value When the PLL clock is selected as the clock source for the CPU clock the CMO6 bit should be set to 0 and the CM17 to CM16 bits to OOb undivided After reset the main clock divided by 8 provides the CPU clock During memory expansion or microprocessor mode
225. LK CS i 4ns min th BCLK AD SO 4ns min SHE BHE lt _ __ gt td BCLK ALE lh BCLK ALE i gt gt 25ns max 4ns min i td BCLK WR i td BCLK DB 40ns max 25ns max gt i i 0 5 X tcyc 10 ns min 1 1 1 1 1 1 1 1 1 1 1 i 1 i 1 1 1 1 1 1 1 i 1 i 1 i D i 1 1 1 i r i 1 i 1 1 1 1 1 1 ta DB WR 0 5 X tcyc 40 ns min 0 5 X tcyc 10 ns min f teyc Ye NBCLK Measuring conditions e VCC 5V e Input timing voltage Vi 0 8 V Vin 2 0 V e Output timing voltage Vo 0 4 V Vou 2 4 V Figure 22 6 Timing Diagram 3 Rev 2 00 Nov 28 2005 page 307 of 378 REJO9BO0124 0200 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode For 1 wait setting and external area access Read timing td BCLK CS i 25ns max td BCLK AD no Sy Pan oe i td BCLK ALE B 7 25ns max at i ta BcLK cs al 25ns max i 1 h BCLK ALE 1 og 4ns min i i 1 ta BCLK RD lt gt 25ns max i tac2 RD DB 1 5 X tcyc 45 ns max tSU DB RD 40ns min i td BCLK AD i 25ns max td BCLK ALE 1 tcvc Ye NBCLK Measuring conditions e VCC 5V e Input timing voltage
226. M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 8 Pin Characteristics for 128 Pin Package 3 Control Interrupt Timer Pin UART Pin CAN Module Bus Control Pin Pin Pin Pin NOTE 1 Not available the bus control pins in T V ver Rev 2 00 Nov 28 2005 page 12 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 6 Pin Description Tables 1 9 to 1 11 list the pin descriptions 1 Overview Table 1 9 Pin Description 100 pin and 128 pin Versions 1 Signal Name Power supply input Pin Name VCC1 VCC2 VSS VoTme SS Besepio Apply 3 0 to 5 5V to the VCC1 and VCC2 pins and OV to the VSS pin The VCC apply condition is that VCC2 VCC1 Analog power supply input AVCC AVSS Applies the power supply for the A D converter Connect the AVCC pin to VCC1 Connect the AVSS pin to VSS Reset input RESET The microcomputer is in a reset state when applying L to the this pin CNVSS CNVSS Switches processor mode Connect this pin to VSS to when after a reset to start up in single chip mode Connect this pin to VCC1 to start up in microprocessor mode External data bus width select input Switches the data bus in external memory space The data bus
227. M16C 6NM 9 Protection 9 Protection In the event that a program runs out of control this function protects the important registers so that they will not be rewritten easily Figure 9 1 shows the PRCR register The following lists the registers protected by the PRCR register The PRCO bit protects the CMO CM1 CM2 PLCO PCLKR and CCLKR registers e The PRC1 bit protects the PMO PM1 PM2 TB2SC INVCO and INVC1 registers e The PRC2 bit protects the PD7 PD9 S3C S4C S5C and S6C registers NOTE 1 The S5C and S6C registers are only in the 128 pin version Set the PRC2 bit to 1 write enabled and then write to any address and the PRC2 bit will be set to 0 write protected The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1 Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction The PRCO and PRC1 bits are not automatically set to 0 by writing to any address They can only be set to 0 in a program Protect Register b7 b6 b5 b4 b3 b2 bi bO KEPT Address 000Ah Bit Name Protect Bit O Protect Bit 1 Protect Bit 2 Reserved Bit After Reset XX000000b Enable write to CMO CM1 CM2 PLCO PCLKR CCLKR registers 0 Write protected 1 Write enabled Enable write to PMO PM1 PM2 TB2SC INVCO INVC1 registers 0 Write p
228. MD2 to SMDO Set to 101b CKDIR Select the internal clock or external clock STPS Set to 0 PRY Set this bit to 1 for direct format or O for inverse format PRYE Set to 1 IOPOL Set to 0 CLK1 CLKO Select the count source for the U2BRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Set to 0 CKPOL Set to 0 UFORM Set this bit to O for direct format or 1 for inverse format TE Set this bit to 1 to enable transmission Tl Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag Set to 1 Set to 0 Set this bit to 0 for direct format or 1 for inverse format Set to 1 U2SMR Set to 0 U2SMR2 Set to 0 U2SMR3 Set to 0 U2SMR4 Set to 0 NOTE 1 Not all register bits are described above Set those bits to 0 when writing to the registers in SIM mode Rev 2 00 Nov 28 2005 page 192 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 1 Transmission Transfer clock TE bit in U2C1 register TI bit in U2C1 register Transferred from U2TB register to UART2 transmit register Parity Stop TXD2 Parity error signal sent back from receiving end An L
229. MRO 1 bit 1 Make sure no interrupts or no DMA transfers will occur before writing 1 after writing O 4 Write to this bit from a program in oth er than the flash memory 5 Effective when the FMRO1 bit 1 CPU rewrite mode If the FMRO 1 bit 0 although the FMSTP bit can be set to 1 by writing 1 in a program the flash memory is neither placed in low power dissipation state nor initialized 6 This bit is set to 0 by executing the clear status command Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol FMR1 Bit Symbol b0 Address 01B5h After Reset 0X00XX0Xb Bit Name Function Reserved Bit EW1 Mode Select Bit 1 The value in this bit when read is indeterminate 0 EWO mode 1 EW1 mode Reserved Bit The value in this bit when read is indeterminate FMR16 b7 Figure 21 4 FMRO Register and FMR Rev 2 00 Nov 28 2005 page 266 of 378 REJ09B0124 0200 Reserved Bit Lock Bit Status Flag Set to 0 0 Lock 1 Unlock Reserved Bit Set to 0 1 To set this bit to 1 write 0 and then 1 in succession when the FMRO 1 bit in the FMRO register 1 Make sure no interrupts or no DMA transfers will occur before writing 1 after writing O Write to this bit when the NMI pin is in the high state The FMRO1 and FMR11 bits both are set to 0 by setting the FMRO bit to 0 1 Register 134 NE ESAS Under development This document is under dev
230. Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics operating margin noise tolerated dose noise width dose in electrical characteristics due to internal ROM different layout pattern etc When switching to the mask ROM version conduct equivalent tests as system evaluation tests conducted in the flash memory version Rev 2 00 Nov28 2005 page 369 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 18 Mask ROM Version When using the masked ROM version write nothing to internal ROM area Rev 2 00 Nov28 2005 page 370 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 19 Flash Memory Version 23 19 1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses OFFFDFh OFFFE3h OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh If wrong data are written to theses addresses the flash memory cannot be read or written in standard serial I O mode and CAN I O mode The ROMCP register is mapped in address OFFFFFh If wrong data is written to this address the flash memory cannot be read or written in parallel I O mode In the flash memory version of microcomputer these addresses are allo
231. Message Box 7 Time Stamp OOEOh OOE1h OOE2h OOESh CANO Message Box 8 Identifier DLC OOE4h OOE5h OOE6h OOE7h OOE8h San CANO Message Box 8 Data Field OOEBh OOEDh OOEEh pu OOEFh CANO Message Box 8 Time Stamp OOFih OOF2h OOF3h CANO Message Box 9 Identifier DLC OOF4h OOF5h OOF6h OOF7h OOF8h OOF9h OOFAh CANO Message Box 9 Data Field OOFBh OOFCh OOFDh OOFEh D O0FFh CANO Message Box 9 Time Stamp X Undefined Address OOCOh ooCih 00C2h 00C3h_ Goes OOC7h 00C8h OoCoh ooCAn ooCBh O0CCh 00D1h ooD2n o0D3h oone O0D7h _00D8h ooDoh ooDAn ooDBh oopen 00Eth_ ooE2n ooEsn ooE4n O0E7h OoE8h ooEon ooEBh OOF ih 00F2h_ OOF 3h ooren ooF7h ooF8h ooFon ooFan OoFBh Km ooFFh Rev 2 00 Nov 28 2005 page 22 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 5 SFR Information 5
232. N Group M16C 6NK M16C 6NM Hardware Manual 44 NESAS RenesasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
233. O P6 2 CLKO P6 1 RTSO Pe 0 CTSO P6 4 Figure 15 16 CTS RTS Separate Function Rev 2 00 Nov28 2005 page 166 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 2 Clock Asynchronous Serial I O UART Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format Table 15 5 lists the specifications of the UART mode Table 15 6 lists the registers used in UART mode and the register values set Table 15 5 UART Mode Specifications Specification Transfer Data Format Character bit transfer data Selectable from 7 8 or 9 bits Start bit 1 bit Parity bit Selectable from odd even or none Stop bit Selectable from 1 or 2 bits Transfer Clock e CKDIR bit in UiMR register 0 internal clock fj 16 n 1 fj f1SIO f2SIO f8SIO f32SIO n Setting value of the UiBRG register 00h to FFh The CKDIR bit 1 external clock fEXT 16 n 1 fEXT Input from CLKi pin n Setting value of the UiBRG register OOh to FFh Transmission Reception Control Selectable from CTS function RTS function or CTS RTS function disabled Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission e
234. O TXD2 Microcomputer Slave Figure 15 27 Serial Bus Communication Control Example UART2 Rev 2 00 Nov28 2005 page 185 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 15 Registers to Be Used and Settings in Special Mode 2 Register i 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER Overrun error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 001b CKDIR Set this bit to O for master mode or 1 for slave mode IOPOL Set to 0 CLK1 CLKO Select the count source for the UiBRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output format CKPOL Clock phases can be set in combination with the CKPH bit in the UiSMR3 register UFORM Set to 0 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Select UART2 transmit interrupt cause U2RRM 9 UiLCH UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 CKPH Clock phases can be set in combination with the CKPOL bit in the
235. O mode FMROO bit does not switch back to 1 ready Low power dissipation mode or on chip oscillator low power dissipation mode is entered Use the following the procedure to change the FMSTP bit setting 1 Set the FMSTP bit to 1 2 Set tps the wait time to stabilize flash memory circuit 3 Set the FMSTP bit to 0 4 Set tps the wait time to stabilize flash memory circuit Figure 21 7 shows a flow chart illustrating how to start and stop the flash memory processing before and after low power dissipation mode or on chip oscillator low power dissipation mode Follow the procedure on this flow chart When entering stop or wait mode the flash memory is automatically turned off When exiting stop or wait mode the flash memory is turned back on The FMRO register does not need to be set 21 3 3 5 FMRO5 Bit This bit selects the boot ROM or user ROM area in boot mode Set to 0 to access read the boot ROM area or to 1 user ROM access to access read write or erase the user ROM area 21 3 3 6 FMRO6 Bit This is a read only bit indicating an auto program operation state The FMR0OSG bit is set to 1 when a program error occurs otherwise it is set to 0 Refer to 21 3 8 Full Status Check Rev 2 00 Nov28 2005 page 267 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version
236. OM Single chip mode Set CMO CM1 and PM1 registers Set the FMR01 bit to 1 CPU rewrite mode enabled after writing 0 Set the FMR11 bit to 1 EW1 mode after writing 0 EW1 mode 9 Execute the software commands Set the FMR01 bit to 0 CPU rewrite mode disabled NOTES 1 In EW1 mode do not enter the memory expansion mode or boot mode Not availabie memory expansion mode in T V ver 2 In CPU rewrite mode set the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to CPU clock frequency of 10 0 MHz or less Set the PM17 bit in the PM1 register to 1 with wait state 3 Set the FMRO 1 bit to 1 immediately after setting it to 0 Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to 1 Set the FMR11 bit to 1 immediately after setting it to 0 while the FMRO 1 bit is set to 1 Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to 1 Set the FMRO1 and FMR11 bits while H is applied to the NMI pin Figure 21 6 Setting and Resetting of EW1 Mode Rev 2 00 Nov28 2005 page 269 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version Low power dissipation mode or on chip oscillator low power dissipation mode program Transfer a low power
237. P1 7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5 Oto P5 7 P6_0 to P6 7 P7 0toP7 7 P8 0to P8 4 P8 6 P8 7 P9_0 to P9 7 P10 Oto P10 7 P11 Oto P11 7 P12_0 to P12 7 P13_0 to P13 7 P14 0 P14 1 2 The mean output current is the mean value within 100 ms 3 The total louipeak for ports PO P1 P2 P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 80mA max The total loLpeak for ports P3 P4 P5 P6 P7 P8 Oto P8 4 P12 and P13 must be 80mA max The total lou pea for ports PO P1 and P2 must be 40mA max The total lou pea for ports P3 P4 P5 P12 and P13 must be 40mA max The total lou pea for ports P6 P7 and P8 0 to P8 4 must be 40mA max The total loHpeak for ports P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 40mA max 4 P11 to P14 are only in the 128 pin version Rev 2 00 Nov28 2005 page 293 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 3 Recommended Operating Conditions 2 Standard Typ Parameter Main Clock Input Oscillation No Wait Mask ROM Version VCC 3 0 to 5 5V Flash Memory Version Frequency 9 9 Sub Clock Oscillation Frequency On chip Oscillation Frequency PLL Clock Oscillation Frequency CPU Operation Clock VCC 3 0 to 5 5V PLL Frequency Synthesizer Stabilization Wait T
238. PL TAiOUT Input LOW Pulse Width tsu UP TIN TAiOUT Input Setup Time thcTIN uP TAiOUT Input Hold Time Table 22 36 Timer A Input Two phase Pulse Input in Event Counter Mode Standard Min Max Parameter tetta TAiIN Input Cycle Time tsuctain Taout TAIOUT Input Setup Time tsurAoUr TAIN TAilN Input Setup Time Rev 2 00 Nov28 2005 page 315 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC z 3 3V Referenced to VCC 3 3V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 37 Timer B Input Counter Input in Event Counter Mode Standard Min Max Parameter TBiIN Input Cycle Time counted on one edge TBilN Input HIGH Pulse Width counted on one edge TBilN Input LOW Pulse Width counted on one edge TBilN Input Cycle Time counted on both edges TBilN Input HIGH Pulse Width counted on both edges TBilN Input LOW Pulse Width counted on both edges Table 22 38 Timer B Input Pulse Period Measurement Mode Standard Min Max Parameter TBilN Input Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 39 Timer B Input Pulse Width Measurement Mode Standard Min Max Parameter TBilN In
239. PS IMM8 JSRS IMM8 MOV B S IMM dest However dest AO or A1 Instructions other than the above Address indicated by RMADi register 1 Value of PC that is saved to stack area Refer to 10 5 7 Saving Registers Table 10 7 Relationship Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt 0 AIERO Address Match Interrupt 1 Address Match Interrupt 2 AIER20 Address Match Interrupt 3 AIER21 Rev 2 00 Nov 28 2005 page 99 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 bi KAI Symbol Address After Reset ODDEN T AIER 0009h XXXXXX00b Address Match Interrupt O i Interrupt disabled AIERO Enable Bit Interrupt enabled AIER1 Address Match Interrupt 1 Interrupt disabled Enable Bit Interrupt enabled Nothing is assigned When write set to 0 When read their contents are indeterminate Address Match Interrupt Enable Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset AIER2 01BBh XXXXXX00b Address Match Interrupt 2 Interrupt disabled AIER20 Enable Bit Interrupt enabled RW AIER21 Address Match Interrupt 3 Interrupt disabled Enable Bit Interrupt enabled Nothing is assigned When write set to 0 When read their contents are indeterminate Address Match
240. PU and SFR when the PMOS bit in the PMO register is set to 1 microcomputer reset Then the microcomputer executes the program in an address determined by the reset vector Set the PMOS3 bit to 1 while the main clock is selected as the CPU clock and the main clock oscillation is stable In the software reset the microcomputer does not reset a part of the SFR Refer to 4 Special Function Register SFR for details Processor mode remains unchanged since the PMO1 to PMOO bits in the PMO register are not reset 5 3 Watchdog Timer Reset The microcomputer resets pins the CPU and SFR when the PM12 bit in the PM1 register is set to 1 reset when watchdog timer underflows and the watchdog timer underflows Then the microcomputer executes the program in an address determined by the reset vector In the watchdog timer reset the microcomputer does not reset a part of the SFR Refer to 4 Special Function Register SFR for details Processor mode remains unchanged since the PMO1 to PMOO bits in the PMO register are not reset 5 4 Oscillation Stop Detection Reset The microcomputer resets and stops pins the CPU and SFR when the CM27 bit in the CM2 register is 0 reset at oscillation stop re oscillation detection if it detects main clock oscillation circuit stop Refer to 8 5 Oscillation Stop and Re Oscillation Detection Function for details In the oscillation stop detection reset the microcomputer does not reset a part of the SFR R
241. Period Measures a pulse period or width Modulation Mode Pulse Width Modulation Mode NOTES 1 The register must be accessed in 16 bit unit 2 The timer counts pulses from an external device or overflows or underflows of other timers Figure 13 16 TBOMR to TB5MR Registers and TBO to TB5 Registers Rev 2 00 Nov 28 2005 page 131 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Count Start Flag Address After Reset 0380h 00h 1 Starts counting Timer B3 B4 B5 Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBSR 01COh 000XXXXXb Nothing is assigned When write set to 0 When read their contents are indeterminate Timer B3 Count Start Flag 0 Stops counting Timer B4 Count Start Flag 1 Starts counting Timer B5 Count Start Flag Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CPSRF 0381h OXXXXXXXb l Bit Name Function Nothing is assigned When write set to 0 b6 bO When read their contents are indeterminate Setting this bit to 1 initializes the CPSR Clock Prescaler Reset Flag Prescaler for the timekeeping clock RW When read the value of this bit is O Figure 13 17 TABSR Register TBSR Register and CPSRF Register Rev 2 00 Nov 28 2005 page 132 of 378 RENESAS REJ09B0124 0200 Under development Thi
242. REJ09B0124 0200 Everywhere you imagine gg 2 NI ESAS M16C 6N Group M16C 6NK M16C 6NM Hardware Manual RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY M16C 60 SERIES Before using this material please visit our website to verify that this is the most updated document available Rev 2 00 Renesas Technology Revision date Nov 28 2005 www renesas com Keep safety first in your circuit designs e Renesas Technology Corporation puts the maximum effort into making semiconductor prod ucts better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with ap propriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringe ment of any third party s rights originating in the use of any p
243. RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version M16C 6N Group M16C 6NM Flash memory version FESSES AHEAD ESTE TS d TEES ERE pees Te se ee We e olt oae ak eoe eal eal ps eel e7feslesl eo alea es eel d Connect oscillator j circuit t Figure 21 14 Pin Connections for Standard Serial I O Mode 2 Rev 2 00 Nov28 2005 page 285 of 378 REJO9BO0124 0200 131 NESAS Mode setup method VCC1 VSS VSS to VCC1 VCC2 Package PLQP0128KB A Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 4 2 Example of Circuit Application in Standard Serial I O Mode Figures 21 15 and 21 16 show example of circuit application in standard serial I O mode 1 and mode 2 respectively Refer to the user s manual of your serial programmer to handle pins controlled by a serial programmer Note that when using the standard serial I O mode 2 make sure a main clock input oscillation frequency is set to 5 MHz 10 MHz or 16 MHz SCLK input P6 6 CLK1 TXD output P6 7 TXD1 BUSY output P6 4 RTS1 RXD input P6 6 RXD1 Reset input User reset signal NOTES 1 Control pins and external circuitry will vary according to programmer For m
244. RMIC and S4IC registers are set to 0 falling edge Figure 10 12 IFSR1 Register Rev 2 00 Nov28 2005 page 96 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Interrupt Request Cause Select Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address IFSR2 01CFh Interrupt Request Cause IFSR20 Select Bit 2 6 Interrupt oa Cause IRSE Select Bit 3 Interrupt Vnd Cause IFSR22 Select Bit 4 INT6 Interrupt Polarity IFSHES Switching Bit 1 6 IFSR24 INT7 Interrupt Polarity Switching Bit 1 6 INT8 Interrupt Polarity Irene Switching Bit 1 8 Interrupt Request Cause IFSR26 Select Bit 5 After Reset X0000000b Function Timer A2 INT7 Timer A3 INT6 One edge Both edges One edge Both edges One edge Both edges CANO 1 error key input Nothing is assigned When write set to 0 When read its content is indeterminate 10 Interrupt 1 When setting this bit to 1 both edges make sure the POL bit in the INT6IC to INT8IC registers are set to 0 falling edge The INT6IC to INT8IC registers are only in the 128 pin version In the 100 pin version make sure the INT6 to INT8 interrupt polarity switching bitis set to 0 falling edge 2 Timer A2 and INT7 share the vector and interrupt control register When using the timer A2 interrupt set the IFSR20
245. Reset X0000001b X0000001b 0 Operation mode State Reset Reset State Flag 1 Reset mode IN State Loop Back 0 Not Loop back mode LoopBack State Flag 1 Loop back mode State Message Order 0 Word access MsgOrder State Flag 1 Byte access State Basic CAN Mode BasicCAN State Flag 0 Not Basic CAN mode 1 Basic CAN mode State Bus Error 0 No error has occurred BusError State Flag 1 A CAN bus error has occurred State_ Error Passive 0 CAN module is not in error passive state ErPass State Flag 1 CAN module is in error passive state b7 Figure 19 8 COSTR and C1STR Registers Rev 2 00 Nov 28 2005 page 230 of 378 REJ09B0124 0200 Nothing is assigned When write set to 0 When read its content is indeterminate State_ Error Bus Off 0 CAN module is not in error bus off state BusOff State Flag 1 CAN module is in error bus off state 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module CANI Slot Status Register i 0 1 b8 bO b7 bo Symbol Address After Reset COSSTR 0215h 0214h 0000h C1SSTR 0235h 0234h 0000h 0 Reception slot The message has been read Transmission slot Transmission is not completed Reception slot The message has not been read Transmission slot Transmission is completed Slot status bits Each bit corresponds to the slot with the same number CANI Interru
246. S bit in UIMR register 0 CRD bit in UiCO register 0 CTSU RT Figure 15 18 Receive Operation 1 stop bit Si enabled and CRS bit 1 RT Si selected 15 1 2 1 Bit Rates In UART mode the frequency set by the UiBRG register i 0 to 2 divided by 16 become the bit rates Table 15 9 lists example of bit rates and settings Table 15 9 Example of Bit Rates and Settings Bit rate bps Count Source of BRG Peripheral Funct jon Clock 16MHz Peripheral Function Clock 20MHz Peripheral Function Clock 24MHz Set Value of BRG n 103 67h Actual Time bps Set Value of BRG n E Actual Time bps Set Value of o En 51 33h 25 19h 103 67h 64 40h 32 20h E 86 64 42 39 32 23 56h 40h 2 2Ah 9 27h 20h 3 17h 1Fh a 51 E 31 25 19 13h NOTE 1 24 MHz is available Normal ver only Rev 2 00 Nov28 2005 page 171 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 2 2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode follow the procedures below Resetting the UiRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception di
247. S pin Figure 23 4 shows an example connection of each pin Make sure the port direction bits for those pins that are used as analog inputs are set to 0 input mode Also if the TGR bit in the ADCONO register 1 external trigger make sure the port direction bit for the ADTRG pin is set to 0 input mode When using key input interrupt do not use any of the four AN4 to AN7 pins as analog inputs A key input interrupt request is generated when the A D input voltage goes low The AD frequency must be 10 MHz or less Without sample and hold limit the AD frequency to 250 kHz or more With the sample and hold limit the AD frequency to 1 MHz or more When changing an A D operation mode select analog input pin again in the CH2 to CHO bits in the ADCONO register and the SCAN1 to SCANO bits in the ADCON1 register Microcomputer ANi ANi ANO i and AN 2 i i 0 to 7 NOTES 1 C1 2 0 47 uF C2 2 0 47 uF C3 gt 100 pF C4 gt 0 1 uF reference 2 Use thick and shortest possible wiring to connect capacitors Figure 23 4 Use of Capacitors to Reduce Noise Rev 2 00 Nov28 2005 page 360 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A D conversion an incorrect
248. SAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC z 3 3V Referenced to VCC 3 3V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 29 External Clock Input XIN Input Standard Min Max Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min Max lacRp o8 Data input access time for setting with no wait NOTE 1 tace RD DB Data input access time for setting with wait NOTE 2 Parameter laRD o amp Data input access time when accessing multiplexed bus area NOTE 3 tsu DB RD Data input setup time tsurov scLK RDY input setup time tsuHoLo scik HOLD input setup time tn RD D8 Data input hold time inecucaoy RDY input hold time tngcuuoto HOLD input hold time NOTES 1 Calculated according to the BCLK frequency as follows 0 5x 10 _ Bcuk 90 ns 2 Calculated according to the BCLK frequency as follows n 0 5 x 10 BCLK 60 ns nis 2 for 1 wait setting 3 for 2 wait setting and 4 for 3 wait setting 3 Calculated according to the BCLK frequency as follows 0 5 X 10 M s Uc laa GS
249. SET Hysteresis XIN HIGH Input Current PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 P3 0 to P8 7 P4 0 to P4 7 P5 0 to P5 P6 0 to P6 7 P7_0 to P7 7 P8 0 to P8 P9 0to P9 7 P10 0to P10 7 P11_0 to P11 P12_0 to P12 7 P13_0 to P138 7 P14 0 P14 XIN RESET CNVSS BYTE LOW Input Current PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 P3 0 to P8 7 P4 0 to P4 7 P5 0 to P5 P6 0 to P6 7 P7 O0 to P7 7 P8_0 to P8 P9 0to P9 7 P10 0to P10 7 P11_0 to P11 P12_0 to P12 7 P13_0 to P183 7 P14 0 P14 XIN RESET CNVSS BYTE Pull up Resistance PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 7 P3 0 to P3 7 P4 O0 to PA 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 OtoP8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11 0toP11 7 P12 0toP12 7 P13 OtoP13 7 P14 0 P14 1 Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage NOTES At stop mode 1 Referenced to VCC 4 2 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 20MHz unless otherwise specified 2 P11 to P14 INT6 to INT8 CLK5 CLK6 SIN5 and SING are only in the 128 pin version Rev 2 00 Nov28 2005 page 331 of 378 REJ09B0124 0200 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Table 22 50 Electrical Characteristics 2 Sta
250. SINA 4 P9 6 ANEX1 CTXO SOUTA lt gt M16C 6N Group M16C 6NK P4 3 A19 P4 4 CSO P4 5 CS1 P4 6 CS2 P4 7 CS3 P5 O WRL WR P5 1 WRH BHE P5 2 RD P5 S BCLK P5 4 HLDA P5 5 HOLD P5 6 ALE P5 7 RDY CLKOUT P6_0 CTSO RTSO P6_1 CLKO P6 2 RXDO SCLO P6 3 TXDO SDAO P6 4 CTS1 RTS1 CTSO CLKS1 P6 5 CLK1 P6 6 RXD1 SCL1 P6 7 TXD1 SDA1 P7_0 TXD2 SDA2 TAOOUT P7_1 RXD2 SCL2 TAOIN TBSIN 1 O Q P9_5 ANEX0 CRX0 CLK4 P7_2 CLK2 TA10UT V m a E3 o g m S P7 S CTS2 RTS2 TA1IN V c SIN4 S CLK4 gt F P8 5 NMI gt P8 4 INT2 ZP lt gt SOUT4 8 P8_2 INTO gt P8 1 TAAIN U a P8 7 XCIN o P8 6 XCOUT c P8_3 INT1 lt gt P7 5 TA2IN W P8 O TA4OUT U P9 3 DAO TB3IN a 5 P9_2 TB2IN SOUT3 c P9_O TBOIN CLK3 am 5 P9_4 DA1 TB4IN lt P7 6 TA3OUT CTX1 gt 1 P9 1 TB1IN SINS lt a F P7_7 TASIN CRX1 a P7 A TA2OUT W NOTES Package PLQP0100KB A 1 P7 1 and P9 1 are N channel open drain pins 2 Not available the b
251. Symbol Address After Reset Lil jojo TBOMR to TB2MR 039Bh to 039Dh 00XX0000b EMEN EE TB3MR to TB5MR 01DBh to 01DDh 00XX0000b i fof db Poi Bit Symbol TMOD RW Operation Mode Select Bit 0 0 Timer mode RW RW MRO Has no effect in timer mode AW MR1 Can be set to 0 or 1 Bw TBOMR TB3MR registers Set to 0 in timer mode RW TB1MR TB2MR TB4MR TB5MR register s Nothing is assigned When write set to 0 When read its content is indeterminate When write in timer mode set to 0 MR3 When read in timer mode its content is indeterminate b7 b6 TCKO 0 0 f1 or f2 RW Count Source Select Bit A i ps TOM 11 132 Figure 13 18 TBOMR to TB5MR Registers in Timer Mode Rev 2 00 Nov28 2005 page 133 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 2 2 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers Table 13 7 lists specifications in event counter mode Figure 13 19 shows TBiMR register in event counter mode Table 13 7 Specifications in Event Counter Mode Count Source Specification e External signals input to TBiIN pin effective edge can be selected in program Timer Bj overflow or underflow Count Operation Down count When the timer underflows it reloads the reload register co
252. TA4 register is changed whenever the timer B2 signal interrupt is generated Default value of the timer TA41 m TA4 m First time TA4 m Second time TA4 n The TA4 and TA41 registers are changed whenever the Third time TA4 n Fourth time TA p timer B2 interrupt is generated Fifth time TA4 p First time TA41 n TA4 n Default value of the IDBO and IDB1 registers Second time TA41 p TA4 p DUO 1 DUBO 0 DU1 0 DUB1 1 Default value of the IDBO and IDB1 registers They are changed to DUO 1 DUBO 0 DU1 1 DUB1 0 by DUO 1 DUBO 0 DU1 0 DUB1 1 the sixth timer B2 interrupt They are changed to DUO 1 DUBO 0 DU1 1 DUB1 0 by the third timer B2 interrupt Figure 14 9 Triangular Wave Modulation Operation Rev 2 00 Nov 28 2005 page 147 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Sawtooth Wave _ l Signal Wave gt i Timer B2 Timer A4 Start Trigger Signall Timer A4 One Shot Pulse J Rewrite the IDBO and IDB1 registers Transfer the counter to the U Phase Output Signal U Phase Output Signal INV14 0 L active INV14 1 H active INV14 Bits in the INVC1 register NOTES 1 Internal signals See Figure 14 1 Three Phase Motor Control Timer Functions Block Diagram The above applie
253. This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 10 Acceptance Filter Support Unit ASU The acceptance filter support unit has a function to judge valid invalid of a received ID through table search The IDs to receive are registered in the data table a received ID is stored in the CiAFS register i 0 1 and table search is performed with a decoded received ID The acceptance filter support unit can be used for the IDs of the standard frame only The acceptance filter support unit is valid in the following cases When the ID to receive cannot be masked by the acceptance filter Example IDs to receive 078h 087h 111h When there are too many IDs to receive it would take too much time to filter them by software Figure 19 18 shows the write and read of the CiAFS register in word access Addresses CANO CAN1 When write E o gose pe Tespsx sssz sbr sbo oum oum 3 8 Decoder when eas T I I I I 1 Eewpseses s see see sta sbe om zen Figure 19 18 Write read of CiAFS Register in Word Access Rev 2 00 Nov28 2005 page 240 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register i 0 1 is set to 1 Basic CAN mode enabled slots 14 and 15 corres
254. Time Stamp 02Bih 02B2h 02B3h CAN1 Message Box 5 Identifier DLC 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h O2BAh CAN1 Message Box 5 Data Field O2BBh O2BCh 02BDh O2BEh p O2BFh CAN1 Message Box 5 Time Stamp X Undefined Address O280h o28in 0282h o283n E 0287h o288h 0289h 028Ah_ 028Bh_ O28Ch o201n o202n o203n E 0297h 0298h 0299h o29An o2oBn Km o2A n o2A2n 02A3h_ 02A4h O2A7h 02A8h_ O2Aoh O2ABh O2ACh o2B1n ooBen o2B3n ioo o2B7h 02B8h_ ooBon 02BAh_ 02BBh_ reese 02BFh _ Rev 2 00 Nov 28 2005 page 29 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 12 SFR Information 12 Address 02COh 02C1h 02C2h 7 OPC3h CAN1 Message Box 6 Identifier DLC 02C4h 02C5h 02C6h 02C7h 02C8h O2C9h CAN1 Message Box 6 Data Field 02CAh O2CBh 02CCh 02CDh O2CEh Ti OPCFh CAN1 Message Box 6 Time Stamp 02DOh 02D1h O2D3h CAN1 Message Box 7 Identifier DLC 02D4h 02D5h 02D6h 02D7h 02D8h 02D9
255. UOBRG to U2BRG Registers Rev 2 00 Nov 28 2005 page 153 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface UARTIi Transmit Receive Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOMR to U2MR 03A0h 03A8h 01F8h 00h Bit Name Function b2b1bO 000 Serial interface disabled 00 1 Clock synchronous serial I O mode Serial Interface Mode 010 12C mode 2 SMD1 Select Bit 1 100 UART mode transfer data 7 bit long 101 UART mode transfer data 8 bit long 110 UART mode transfer data 9 bit long Do not set a value except above Internal External Clock Select Bit 0 Internal clock 1 External clock 3 Stop Bit Length Select Bit 0 1 stop bit 1 2 stop bits Effective when the PRYE bit 1 0 Odd parity 1 Even parity 0 Parity disabled 1 Parity enabled 0 1 Odd Even Parity Select Bit Parity Enable Bit TXD RXD I O Polarity Reverse Bit No reverse Reverse 1 To receive data set the corresponding port direction bit for each RXDi pin to 0 input mode 2 Set the corresponding port direction bit for SCL and SDA pins to 0 input mode 3 Set the corresponding port direction bit for each CLKi pin to 0 input mode UARTIi Transmit Receive Control Register 0 i O to 2 b7 b6 b5 b4 b3 b2 bi bO Sy
256. UiCO register NODC Set to 0 0 2 4to7 Set to 0 0 to 7 Set to 0 i Oto2 NOTES UOIRS U1IRS Select UARTO and UART1 transmit interrupt cause UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD1 bit 0 CLKMD1 RCSP 7 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in Special Mode 2 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 2 00 Nov28 2005 page 186 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 4 1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiCO register Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated Figure 15 28 shows the transmission and reception timing in master internal clock Figure 15 29 shows the transmission and reception timing CKPH 0 in slave external clock Figure 15 30 shows the transmission and reception timing CKPH 1 in slave external clock Clock output CKPOL 0 CKPH 0 Clock output CKPOL 1 CKPH 0 Clock o
257. UiTB register to the UARTi transmit register CTSi gt Stopped pulsing because CTSi H Stopped pulsing because the TE bit 0 CLKi TB 099g J gadgeagc 99999 Zi TXEPT bit in is 1 UiCO register o l l IR bit in n 1 1 SITIC register o Set to 0 when interrupt request is accepted or set to 0 in a program TC TCLK 2 n 1 fj fj frequency of UIBRG count source f1SIO f2SIO f8SIO f32SIO n value set to the UIBRG register i Oto2 The above timing diagram applies to the case where the register bits are set as follows CKDIR bit in UiMR register 0 internal clock ao CRD bit in UiCO register 0 CTS RTS enabled CRS bit in UiCO register 0 CTS selected CKPOL bit in UiCO register 0 transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock UIRS bit 0 an interrupt request occurs when the transmit buffer becomes empty UOIRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register 2 Example of Receive Timing when external clock is selected RE bit in u BUT UiC1 register o TE bitin E OO UiC1 register o Write dummy data to the UiTB register TI bit in nb UiC1 register 9 Transferred from the UiTB register to the UARTi transmit register H RTSi Even if the reception is completed the RTS does not change The RTS becomes L i h 1 fEXT 7 when the RI
258. User ROM area User ROM area Rewritten However this excludes blocks with the rewrite control program Software Command Program and block erase commands Restriction cannot be executed in a block having the rewrite control program Erase all unlocked block command cannot be executed when the lock bit in a block having the rewrite control program is set to 1 unlocked or when the FMRO 2 bit in the FMRO register is set to 1 lock bit disabled Read status register command cannot be used Modes after Program or Read status register mode Read array mode Erasing CPU Status during Auto Operating Maintains hold state I O ports maintains Write and Auto Erase the state before the command was executed Flash Memory Status Read the FMROO FMRO6 and FMRO7 Read the FMROO FMRO6 and FMRO7 Detection bits in the FMRO register by program bits in the FMRO register by program Execute the read status register command to read the SR7 SR5 and SRA bits in the status register NOTES nu 1 Do not generate an interrupts except NMI interrupt and DMA transfer 2 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit 1 3 Not available in T V ver Rev 2 00 Nov28 2005 page 264 of 378 RENESAS REJ09B0124 0200 Under development Th
259. V External operation amp connection mode 8 bits VREF AVCC VCC 5 0V Absolute 10 bits VREF ANEXO ANEX1 input ANO to AN7 input Accuracy VCC ANO 0to ANO 7 input AN2_0 to AN2 7 input 5V_ External operation amp connection mode 8 bits VREF AVCC VCC 5 0V Differential Nonlinearity Error Offset Error Gain Error Resistor Ladder VREF VCC 10 bit Conversion Time VREF VCC 5V AD 10MHz Sample amp Hold Available 8 bit Conversion time VREF VCC 5V AD 10MHz Sample amp Hold Available Sampling Time Reference Voltage Analog Input Voltage NOTES 1 Referenced to VCC AVCC VREF 4 2 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 dAD frequency must be 10MHz or less 3 When sample amp hold is disabled AD frequency must be 250kHz or more in addition to a limit of NOTE 2 When sample amp hold is enabled AD frequency must be 1MHz or more in addition to a limit of NOTE 2 Table 22 52 D A conversion Characteristics Standard Min Typ Parameter Measuring condition Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current NOTES 1 Referenced to VCC AVCC VREF 4 2 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 This applies when using one D A converter with the DAI register i 0 1 for the unused D A converter
260. Voltage OV to AVCC VCC Operating Clock 9AD fAD divide by 2 of fAD divide by 3 of fAD divide by 4 of fAD divide by 6 of fAD divide by 12 of fAD Resolution 8 bits or 10 bits selectable Integral Nonlinearity Error When AVCC VREF 5 V With 8 bit resolution x2LSB With 10 bit resolution ANO to AN7 input ANO 0 to ANO 7 input and AN2 0 to AN2 7 input x3LSB ANEXO and ANEX1 input including mode in which external operation amp is selected 7LSB When AVCC VREF 3 3 V With 8 bit resolution 2LSB With 10 bit resolution ANO to AN7 input ANO 0 to ANO 7 input and AN2 0 to AN2 7 input 5LSB ANEXO and ANEX1 input including mode in which external operation amp is selected 7LSB Operating Modes One shot mode repeat mode single sweep mode repeat sweep mode 0 and repeat sweep mode 1 Analog Input Pins 8 pins ANO to AN7 2 pins ANEXO and ANEX1 8 pins ANO 0 to ANO 7 8 pins AN2_0 to AN2 7 A D Conversion Software trigger Start Condition The ADST bit in the ADCONO register is set to 1 A D conversion starts External trigger retriggerable Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts Conversion Speed Per Pin e Without sample and hold 8 bit resolution 49 6AD cycles 10 bit resolution 59 9AD cycles e With sample and hold 8 bit resolution 28 6AD cycles 10 bit resolution 33 9AD cycles NOTES 1 Does not
261. Voltage PO 0 to PO 7 P1 Oto P1 7 P2 O0 to P2 7 P3 0 to P8 7 P4 0 to P4 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11 0toP11 7 P12 0to P12 7 P13 Oto P13 7 P14 0 P14 1 lon 200pA HIGH Output Voltage XOUT HIGHPOWER lou 1mA LOWPOWER lou 0 5mA HIGH Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied LOW Output Voltage PO 0 to PO 7 P1 Oto P1 7 P2 O to P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 O to P5 7 P6 0 to P6 7 P7 O0 to P7 7 P8 O to P8 4 P8 6 P8 7 P9 0 to P9 7 P10_0 to P10 7 P11 0toP11 7 P12 0to P12 7 P13_0 to P13 7 P14 0 P14 1 lo 5mA LOW Output Voltage PO 0 to PO 7 P1_0 to P1 7 P2_0 to P2 7 P3 0 to P3 7 P4 0 to PA 7 P5 O to P5 7 P6 0 to P6 7 P7 O0 to P7 7 P8 O to P8 4 P8 6 P8 7 P9 0 to P9 7 P10 0 to P10 7 P11 0toP11 7 P12 0to P12 7 P13_0 to P13 7 P14 0 P14 1 lo 200pA LOW Output Voltage XOUT HIGHPOWER lo 1mA LOWPOWER lo 0 5mA LOW Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied Hysteresis TAOIN to TA4IN TBOIN to TBSIN INTO to INT8 NMI ADTRG CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 CLKO to CLK6 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD2 SIN3 to SING Hysteresis RE
262. Vou 1 65 V e Input timing voltage Figure 22 17 Timing Diagram 5 7tENESAS Rev 2 00 Nov 28 2005 page 324 of 378 REJO9BO0124 0200 22 Electric Characteristics Normal ver This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Under development 3 3V VCC o D o o a N o o o A a pn S z D c G o E o c Q m E G Q x i gt EI o E o o o o o o oO o wx c LJ o x lt 0 Ke c D c 0 o 1S gt e LE o LL o E ES ke o tc td BCLK CS tSU DB RD n gt tn RD DB Ons min 50ns min Write timing 0 5 X tcyc 10 ns min th WR DB th wR AD 0 5 X tcyc 10 ns min 2 5 X tcyc 40 ns min td DB wR Fe 30ns max Measuring conditions e VCC 3 3 V Vit 0 6 V VH 2 7 V e Output timing voltage VoL 1 65 V VoH 1 65 V e Input timing voltage Figure 22 18 Timing Diagram 6 131 NE SAS Rev 2 00 Nov 28 2005 page 325 of 378 REJO9BO0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Memory Expansion Mode and Microprocessor Mode 22 Electric Characteristics Normal ver VCC 3 3V For 2 wait setting external area access and multiplexed bus selection Read timing td BCLK CS 40ns
263. XXXb One Shot Start Flag 00h Trigger Select Register 00h Up Down Flag 00h 1 Timer AO Register ee Timer A1 Register AE Timer A2 Register E Timer A3 Register ES Timer A4 Register E Timer BO Register AL Timer B1 Register AE 0394h XXh Timer B2 Register XXh Timer AO Mode Register 00h Timer A1 Mode Register 00h Timer A2 Mode Register 00h Timer A3 Mode Register 00h Timer A4 Mode Register 00h Timer BO Mode Register 00XX0000b Timer B1 Mode Register 00XX0000b Timer B2 Mode Register 00XX0000b Timer B2 Special Mode Register XXXXXX00b UARTO Transmit Receive Mode Register 00h UARTO Bit Rate Generator XXh UARTO Transmit Buffer Register A UARTO Transmit Receive Control Register 0 00001000b UARTO Transmit Receive Control Register 1 00XX0010b UARTO Receive Buffer Register ER UART1 Transmit Receive Mode Register 00h UART1 Bit Rate Generator XXh UART1 Transmit Buffer Register X UART1 Transmit Receive Control Register 0 00001000b UART1 Transmit Receive Control Register 1 00XX0010b UART1 Receive Buffer Register X UART Transmit Receive Control Register 2 X0000000b DMAO Request Cause Select Register DMA1 Request Cause Select Register CRC Data Register O3BDh O3BEh CRC Input Register OSBFh X Undefined NOTES 1 The TA2P to TA4P bits in the UDF r
264. Y Signal This signal is provided for accessing external devices which need to be accessed at low speed If input on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle one wait state is inserted in the bus cycle While in a wait state the following signals retain the state in which they were when the RDY signal was acknowledged AO to A19 DO to D15 CSO to CS3 RD WRL WRH WR BHE ALE HLDA Then when the input on the RDY pin is detected high at the falling edge of BCLK the remaining bus cycle is executed Figure 7 4 shows example in which the wait state was inserted into the read cycle by the RDY signal To use the RDY signal set the corresponding bit CS3W to CSOW bits in the CSR register to 0 with wait state When not using the RDY signal the RDY pin must be pulled up In an instance of separate bus RD CSi i 0 to 3 RDY tsu RDY BCLK A Accept timing of RDY signal In an instance of multiplexed bus tsu RDY BCLK A Q9 Wait using RDY signal Accept timing of RDY signal es Wait using software tsu RDY BCLK RDY input setup time Shown above is the case where CSEi1W to CSEiOW i 0 to 3 bits in the CSE register are 00b one wait state Figure 7 4 Example in which Wait State was Inserted into Read Cycle by RDY Signal Rev 2 00 Nov28 2005 page 49 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and it
265. a BCLK signal with the same frequency as the CPU clock can be output from the BCLK pin by setting the PMO7 bit of PMO register to 0 output enabled Note that when entering stop mode from high or medium speed mode on chip oscillator mode or on chip oscillator low power dissipation mode or when the CMO5 bit in the CMO register is set to 1 main clock turned off in low speed mode the CMO6 bit in the CMO register is set to 1 divide by 8 mode NOTE 1 Not available memory expansion and microprocessor modes in T V ver 8 2 2 Peripheral Function Clock f1 f2 f8 32 f181O f2SIO f8SIO f32SIO fAD fCANO fCAN1 C32 These are operating clocks for the peripheral functions Two of these fi i 1 2 8 32 and fiSIO are derived from the main clock PLL clock or on chip oscillator clock by dividing them by i The clock fi is used for timers A and B and fiSIO is used for serial interface The f8 and f32 clocks can be output from the CLKOUT pin The fAD clock is produced from the main clock PLL clock or on chip oscillator clock and is used for the A D converter The fCANi i 20 1 clock is derived from the main clock PLL clock or on chip oscillator clock by dividing them by 1 undivided 2 4 8 or 16 and is used for the CAN module When the WAIT instruction is executed after setting the CMO2 bit in the CMO register to 1 peripheral function clock turned off during wait mode or when the microcomputer is in low power
266. able interrupts can all be disabled without causing a problem use the flag Otherwise use the corresponding ILVL2 to ILVLO bit for the interrupt whose interrupt generate factor is to be changed 3 Refer to 23 8 6 Rewrite Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution Figure 23 3 Procedure for Changing Interrupt Generate Factor 23 8 5 INT Interrupt Either an L level of at least tW INH or an H level of at least tW INL width is necessary for the signal input to pins INTO to INT8 regardless of the CPU operation clock e If the POL bit in the INTOIC to INT8IC registers the IFSR10 to IFSR15 bits in the IFSR1 register or the IFSR23 to IFSR25 bits in the IFSR2 register are changed the IR bit may inadvertently set to 1 interrupt requested Be sure to set the IR bit to 0 interrupt not requested after changing any of those register bits NOTES 1 The pins INT6 to INT8 are only in the 128 pin version 2 The INT6IC to INT8IC registers are only in the 128 pin version 3 The IFSR23 to IFSR25 bits are effective only in the128 pin version In the 100 pin version these bits are set to 0 one edge Rev 2 00 Nov28 2005 page 347 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 8 6 Rewrite I
267. able 15 18 lists the registers used in the SIM mode and the register values set Figure 15 32 shows the typical transmit receive timing in SIM mode Table 15 17 SIM Mode Specifications Specification Transfer data format Direct format Inverse format Transfer clock The CKDIR bit in the U2MR register 0 internal clock fi 16 n 1 fi f1SIO f28IO f8SIO f32SIO n Setting value of the U2BRG register 00h to FFh e The CKDIR bit 1 external clock fEXT 16 n 1 fEXT Input from CLK2 pin n Setting value of the U2BRG register 00h to FFh Transmission start condition Before transmission can start the following requirements must be met The TE bit in the U2C1 register 1 transmission enabled e The TI bit in the U2C1 register 0 data present in the U2TB register Reception start condition Before reception can start the following requirements must be met The RE bit in the U2C1 register 1 reception enabled Start bit detection Interrupt request generation timing For transmission When the serial I O finished sending data from the U2TB transfer register U2IRS bit 1 For reception When transferring data from the UART2 receive register to the U2RB register at completion of reception Error detection NOTES e Overrun error This error occurs if the serial I O started receiving the next data before reading the U2RB register and received the bit one before the last stop
268. able bit SSS Select the transmit start condition 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 IFSRO6 IFSRO7 Set to 1 i 0 to 2 NOTES UOIRS U1IRS Select the source of VARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD1 bit 0 CLKMD1 RCSP 7 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in IE mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 2 00 Nov 28 2005 page 189 of 378 REJ09B0124 0200 131 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 1 ABSCS Bit in UISMR Register bus collision detect sampling clock select If ABSCS bit 0 bus collision is determined at the rising edge of the transfer clock Transfer clock TXDi RXDi Timer Aj If ABSCS bit 1 bus collision is determined when timer Aj one shot timer mode underflows Timer Aj timer A8 when UARTO timer A4 when UART1 timer AO when UART2 2 ACSE Bit in UiSMR Register auto clear of transmit enable bit Transfer clock L Ld f f f If L L f LILI ST DO D3 D4 D5 D6 D7 D8 SP D1 D2 TXDi L RXDi IR bit in If the ACSE bit 1
269. abled Figure 21 7 Processing Before and After Low Power Dissipation Mode or On chip Oscillator Low Power Dissipation Mode Rev 2 00 Nov28 2005 page 270 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 4 Precautions on CPU Rewrite Mode 21 3 4 1 Operating Speed Set the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode EWO or EW1 mode Also set the PM17 bit in the PM1 register to 1 with wait state 21 3 4 2 Prohibited Instructions The following instructions cannot be used in EWO mode because the CPU tries to read data in flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 21 3 4 3 Interrupts EWO Mode To use interrupts having vectors in a relocatable vector table the vectors must be relocated to the RAM area The NMI and watchdog timer interrupts are available since the FMRO and FMR1 registers are forcibly reset when either interrupt request is generated Allocate the jump addresses for each interrupt service routines to the fixed vector table Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt request is generated Execute the rewrite program again after exiting the interrupt routine The add
270. acteristics timing charts Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note Application examples of peripheral functions Sample programs Introduction to the basic functions in the M16C family Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product a document etc NOTE 1 Before using this material please visit our website to verify that this is the most updated document available Table of Contents cigaNz 4ziille m m HX B 1 LOVE deme en Idm EMEND MEME I ee ere one eee UEM 1 a ES Pere MISERIS ID C DUE DLL IE 1 1 2 T ioi e sel cL 2 1 3 Block DiaQram E 4 a dureolngsri e 5 JEU ESremife UirzWle nee LEE EET 6 TO PUN DOSCHIPUOM xe e EEUU 13 2 Central Processing Unit CPU scccinsrcxsncassarscniadudonmmontentudnsdensncatnonnndaibuisbaduanmndadslanciiccibacuendnens 16 2 1 Data Registers RO R1 R2 arid RIS eese inue tecen es een nantur dire een eaa ex ada Dd eR Au DER o ARR ce 16 2 2 Address Registers AQ and AT usciti entgegen oe rang aa rester ued abuse d gene gus vege a ker yea exon e aae uda ee hes 16 2 3 Frame Base Register FB sisremare aa eene nennen nennen aaie ah ai ahaaa ai narast 17 2 4 Interrupt Table Register INTB
271. al Delay 3 to 4 cycles of UIBRG count source Setup Bit 1 2 4 to 5 cycles of UiBRG count source 5 to 6 cycles of UIBRG count source 6 to 7 cycles of UIBRG count source 7 to 8 cycles of UIBRG count source 1 The DL2 to DLO bits are used to generate a delay in SDAi output by digital means during I2 C mode In other than I2C mode set these bits to 000b no delay 2 The amount of delay varies with the load on SCLi and SDAi pins Also when using an external clock the amount of delay increases by about 100 ns Figure 15 9 UOSMR2 to U2SMR2 Registers and UOSMR3 to U2SMR3 Registers Rev 2 00 Nov28 2005 page 157 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM UARTi Special Mode Register 4 i 0 to 2 15 Serial Interface b7 b6 b5 b4 b3 b2 bi bO Symbol UOSMR4 to U2SMR4 Address 01ECh 01FOh 01F4h After Reset 00h Start Condition Generate Bit 1 0 Clear 1 Start RSTAREQ Restart Condition Generate Bit 1 0 Clear 1 Start 0 Clear 1 Start Stop Condition Generate Bit 1 0 Start and stop conditions not output SCL SDA Output i 1 Start and stop conditions output Select Bit 0 ACK ACK Data Bit 1 NACK ACK Data Output Enable Bit 0 Serial interface data output 1 ACK data output 1 Set to 0 when each condition is SCL Output S
272. am 10 9 CANO 1 Wake up Interrupt CANO 1 wake up interrupt request is generated when a falling edge is input to CRXO or CRX1 One interrupt is allocated to CANO 1 The CANO 1 wake up interrupt is enabled only when the PortEn bit 1 CTX CRX function and Sleep bit 1 Sleep mode enabled in the CiCTLR register i 0 1 Figure 10 15 shows the block diagram of the CANO 1 wake up interrupt Please note that the wake up message will be lost Sleep bit in COCTLR register PortEn bit in COCTLR register CO1WKIC register CRX0 O Sleep bit in C1CTLR register Interrupt control CANO 1 wake up circuit interrupt request Figure 10 15 CANO 1 Wake up Interrupt Block Diagram Rev 2 00 Nov 28 2005 page 98 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad dress indicated by the RMADi register i 0 to 3 Set the start address of any instruction in the RMADi register Use the AIERO and AIER1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2 register to enable or disable the interrupt Note that the address match interrupt is unaffected by the flag and IPL For address match interrupts the value of the PC that is saved to the stack area varies depending on the instruction
273. and oscillation stop detection reset are available to reset the microcomputer 5 1 Hardware Reset The microcomputer resets pins the CPU and SFR by setting the RESET pin If the supply voltage meets the recommended operating conditions the microcomputer resets all pins when an L signal is applied to the RESET pin see Table 5 1 Pin Status When RESET Pin Level is L The oscillation circuit is also reset and the main clock starts oscillation The microcomputer resets the CPU and SFR when the signal applied to the RESET pin changes low L to high H The microcomputer executes the program in an address indicated by the reset vector The internal RAM is not reset When an L signal is applied to the RESET pin while writing data to the internal RAM the internal RAM is in an indeterminate state Figure 5 1 shows an example of the reset circuit Figure 5 2 shows a reset sequence Table 5 1 lists pin states while the RESET pin is held low L 5 1 1 Reset on a Stable Supply Voltage 1 Apply L to the RESET pin 2 Apply 20 or more clock cycles to the XIN pin 3 Apply H to the RESET pin 5 1 2 Power on Reset 1 Apply L to the RESET pin 2 Raise the supply voltage to the recommended operating level 3 Insert td P R ms as wait time for the internal voltage to stabilize 4 Apply 20 or more clock cycles to the XIN pin 5 Apply H to the RESET pin Recommended
274. anks Figure 2 1 CPU Registers 2 1 Data Registers RO R1 R2 and R3 The RO register consists of 16 bits and is used mainly for transfers and arithmetic logic operations R1 to R3 are the same as RO The RO register can be separated between high ROH and low ROL for use as two 8 bit data registers R1H and R1L are the same as ROH and ROL Conversely R2 and RO can be combined for use as a 32 bit data register R2RO R3R1 is the same as R2RO 2 2 Address Registers A0 and A1 The AO register consists of 16 bits and is used for address register indirect addressing and address register relative addressing They also are used for transfers and arithmetic logic operations A1 is the same as AO In some instructions A1 and AO can be combined for use as a 32 bit address register A1A0 Rev 2 00 Nov28 2005 page 16 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 2 Central Processing Unit CPU 2 3 Frame Base Register FB FB is configured with 16 bits and is used for FB relative addressing 2 4 Interrupt Table Register INTB INTB is configured with 20 bits indicating the start address of an interrupt vector table 2 5 Program Counter PC PC is configured with 20 bits indicating the address of an instruction to be executed 2 6 User Stack Pointer USP Interrupt Stack Pointer ISP Stack pointer SP comes in two
275. apacity Address XXXXXh 16 Kbytes 043FFh 20 Kbytes 053FFh 31 Kbytes O7FFFh NOTES 1 During memory expansion mode or microprocessor mode cannot be used 2 In memory expansion mode cannot be used 3 As for the flash memory version 4 Kbyte space block A exists 4 When using the masked ROM version write nothing to internal ROM area 5 Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 block A enabled addresses 10000h to 26FFFh for CS2 area and the PM13 bit in the PM1 register is 1 internal RAM area is expanded over 192 Kbytes Not available memory expansion and microprocessor modes in T V ver And not available external area in T V ver Figure 3 1 Memory Map Rev 2 00 Nov 28 2005 page 18 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR SFR Special Function Register is the control register of peripheral functions Tables 4 1 to 4 16 list the SFR information Table 4 1 SFR Information 1 4 Special Function Register SFR Processor Mode Register 0 1 00000000b CNVSS pin is L 00000011b CNVSS pin is H 3 Processor Mode Register 1 00001000b System Clock Control Register 0 01001000b System Clock Control Register 1 00100000b Ch
276. at 15 1 1 4 Continuous Receive Mode In continuous receive mode receive operation becomes enable when the receive buffer register is read It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode However a dummy read of the receive buffer register is required when starting the operation mode When the UiRRM bit i 0 to 2 1 continuous receive mode the TI bit in the UiC1 register is set to 0 data present in UITB register by reading the UiRB register In this case i e VIRRM bit 1 do not write dummy data to the UiTB register in a program The UORRM and U1RRM bits are bit 2 and bit 3 in the UCON register respectively and the U2RRM bit is bit 5 in the U2C1 register Rev 2 00 Nov28 2005 page 164 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 1 5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register i 0 to 2 1 reverse the data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the UiRB register Figure 15 14 shows serial data logic 1 When the UiLCH bit in the UiC1 register 0 no reverse Tee LLP LPL LL S TXDi H aaeierss as DO jJ D J D2 j D3 A D4 J D5 jJ D6 j D7 2 When the UiLCH bit i
277. ated according to the BCLK frequency as follows 9 aa PT 50 ns n is 2 for 2 wait setting 3 for 3 wait setting 3 Calculated according to the BCLK frequency as follows 0 5 X 10 Beg PS 4 Calculated according to the BCLK frequency as follows 0 5 X 10 mm 15 f BCLK Ins Rev 2 00 Nov 28 2005 page 319 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver VCC z 3 3V XIN input TAiIN input lt tw UPH TAiOUT input re TAiOUT input Up down input X During event counter mode TAIIN input When count on falling edge Tn iN UP Tsu UP TIN is selected TAIIN input When count on rising edge is selected Two phase pulse input in event counter mode TAIN input tsu TAIN TAOUT tsu TAIN TAOUT TAiOUT input tsu TAOUT TAIN tc TB TBIIN input tw TBL tc AD ADTRG input tw CKL th C Q TXDi td C Q tsu D C lt gt lt th C D RXDi l INTI input Figure 22 13 Timing Diagram 1 Rev 2 00 Nov 28 2005 page 320 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electr
278. ates whether or not the auto erase operation has been completed as expected The lock bit can protect each block from being programmed inadvertently Refer to 21 3 6 Data Protect Function In EW1 mode do not execute this command when the lock bit for any block storing the rewrite control program is set to 1 unlocked or when the FMRO2 bit in the FMRO register is set to 1 lock bit disabled In EWO mode the microcomputer enters read status register mode as soon as an auto erase operation starts The status register can be read The SH7 bit in the status register is set to 0 busy at the same time an auto erase operation starts It is set to 1 ready when an auto erase operation is completed The microcomputer remains in read status register mode until the read array command or read lock bit status command is written Only blocks 0 to 12 can be erased by the erase all unlocked block command The block A cannot be erased Use the block erase command to erase the block A 21 3 5 7 Lock Bit Program Command The lock bit program command sets the lock bit for a specified block to 0 locked By writing xx77h in the first bus cycle and xxDOh to the highest order even address of a block in the second bus cycle the lock bit for the specified block is set to 0 The address value specified in the first bus cycle must be the same highest order even address of a block specified in the second bus cycle Figure 21 10 shows a fl
279. b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PC14 O3DEh XX00XXXXb Bit Symbol The pin level on any I O port which is set P140 Port P14_0 Bit for input mode can be read by reading the RW corresponding bit in this register The pin level on any I O port which isset for output mode can be controlled by writing to the corresponding bit in this register P141 Port P14 1 Bit Bun em 9 1 H level Nothing is assigned When write set to 0 b3 b2 When read their contents are indeterminate Port P14 0 Direction O Input mode PHAR Functions as an input port Port P14 1 Direction 1 Output mode PD141 Functions as an output port RW Nothing is assigned When write set to 0 b7 b6 When read their contents are indeterminate 1 When using the port P14 set the PU37 bit in the PURS register to 1 usable Figure20 8 PO to P13 Registers and PC14 Register Rev 2 00 Nov28 2005 page 255 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Pull up Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PURO 03FCh 00h Bit Symbol Bit Name 4 PUOO PO 0 to PO 3 Pull Up 0 Not pulled ica PO 4 to PO 7 Pull Up 1 Pulled high 2 P1_0 to P1_3 Pull Up P1_4 to P1_7 Pull Up P2_0 to P2_3 Pull Up PUO6G P3 0 to P3 3 Pull Up PUO7 P3 4to P3 7 Pull Up
280. bed below The transmit shift register is initialized and the content of the UiTB register is transferred to the trans mit shift register In this way the serial I O starts sending data synchronously with the next clock pulse applied However the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock e The receive shift register is initialized and the serial I O starts receiving data synchronously with the next clock pulse applied The SWC bit is set to 1 SCL wait output enabled Consequently the SCLi pin is pulled low at the falling edge of the ninth clock pulse Note that when UARTi transmission reception is started using this function the TI bit does not change state Note also that when using this function the selected transfer clock should be an external clock Rev 2 00 Nov28 2005 page 183 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 4 Special Mode 2 Multiple slaves can be serially communicated from one master Transfer clock polarity and phase are selectable Table 15 14 lists the specifications of Special Mode 2 Figure 15 27 shows communication control example for Special Mode 2 Table 15 15 lists the registers used in Special Mode 2 and the register values
281. bled If this interrupt is unused connect the NMI pin to VCC via a resistor pull up The input level of the NMI pin can be read by accessing the P8 5 bit in the P8 register Note that the P8 5 bit can only be read when determining the pin level in NMI interrupt routine e Stop mode cannot be entered into while input on the NMI pin is low This is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to 0 Do not go to wait mode while input on the NMI pin is low This is because when input on the NMI pin goes low the CPU stops but CPU clock remains active therefore the current consumption in the chip does not drop In this case normal condition is restored by an interrupt generated thereafter The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles 300 ns or more Rev 2 00 Nov28 2005 page 346 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 8 4 Changing Interrupt Generate Factor If the interrupt generate factor is changed the IR bit of the interrupt control register for the changed interrupt may inadvertently be set to 1 interrupt requested If you changed the interrupt generate factor for an interrupt that needs to be used be sure to set the IR bit for that interrupt to O interrupt not requested Cha
282. by 6 of fAD or divide by 12 of fAD Frequency Select Bit 2 2 Nothing is assigned When write set to 0 When read their contents are O 1 If the ADCONe register is rewritten during A D conversion the conversion result will be indeterminate 2 The 9AD frequency must be 10 MHz or less The selected AD frequency is determined by a combination of the CKSO bit in the ADCONO register the CKS1 bit in the ADCON 1 register and the CKS2 bit in the ADCON2 register Divide by 4 of fAD Divide by 2 of fAD ot tap Divide by 12 of fAD EP Divide by 6 of fAD ES Divide by 3 of fAD Ep 1 0 HH EARE Symbol Address After Reset ADO 03C1h to O3COh Indeterminate AD1 03C3h to O3C2h Indeterminate AD2 03C5h to O3C4h Indeterminate A D Register i i 2 O to 7 AD3 03C7h to 03C6h Indeterminate os AD4 O3C9h to 03C8h Indeterminate bO b7 AD5 OSCBh to O3CAh Indeterminate AD6 03CDh to O3CCh Indeterminate AD7 O3CFh to OSCEh Indeterminate When BITS bit in ADCON1 When BITS bit is 0 register is 1 10 bit mode 8 bit mode Low order 8 bits of A D conversion result A D conversion result High order 2 bits of When read the content is A D conversion result indeterminate Nothing is assigned When write set to O When read their contents are 0 Figure 16 3 ADCON2 Register and ADO to AD7 Registers Rev 2 00 Nov28 2005 page 205 of 378 131 NE SAS REJ09B0124 0200 Under development This document is unde
283. cated to the vector addresses H of fixed vectors 23 19 2 Stop Mode When the microcomputer enters stop mode execute the instruction which sets the CM10 bit to 1 stop mode after setting the FMRO 1 bit to 0 CPU rewrite mode disabled and disabling the DMA transfer 23 19 3 Wait Mode When entering wait mode set the FMRO 1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 23 19 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode If the CMO5 bit is set to 1 main clock stopped do not execute the following commands Program Block erase Erase all unlocked blocks Lock bit program Read lock bit status 23 19 5 Writing Command and Data Write commands and data to even addresses in the user ROM area 23 19 6 Program Command By writing xx40h in the first bus cycle and data to the write address in the second bus cycle an auto program operation data program and verify will start The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle 23 19 7 Lock Bit Program Command By writing xx77h in the first bus cycle and xxDOh to the highest order even address of a block in the second bus cycle the lock bit for the specified block is set to 0 The address value specified in the first bus cycle must be the same highest order even address of a block specif
284. caution 23 12 3 SI Oi i 3 to 6 The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10ns may be output when changing the SMi3 bit in the SiC register from 0 I O port to 1 SOUTi output and CLKi function while the SMi2 bit in the SiC register to 0 SOUTi output and the SMi6 bit is set to 1 internal clock And then the SOUTi pin is held high impedance If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from 0 to 1 set the default value of the SOUTi pin by the SMi7 bit NOTE 1 SI O5 and SI O6 are only in the 128 pin version Rev 2 00 Nov28 2005 page 359 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 13 A D Converter Set the ADCONO except bit 6 ADCON1 and ADCON2 registers when A D conversion is stopped before a trigger occurs When the VCUT bit in the ADCON1 register is changed from 0 VREF not connected to 1 VREF connected start A D conversion after passing 1 us or longer To prevent noise induced device malfunction or latch up as well as to reduce conversion errors insert capacitors between the AVCC VREF and analog input pins ANi i 0 to 7 ANO i and AN2 i each and the AVSS pin Similarly insert a capacitor between the VCC pin and the VS
285. ce When the PLL to is added NOTE 1 is added Table 8 2 Example for Setting PLL Clock Frequencies NOTES 2 and 3 are added 8 2 1 CPU Clock and BCLK 10th line The sentence During memory expansion is added 8 4 1 2 PLL Operation Mode NOTE 1 is added 8 4 1 6 On chip Oscillator Mode Last sentence When the operation mode is is added 8 1 1 7 On chip Oscillator Low Power Dissipation Mode Last sentence When the operation mode is is deleted Table 8 4 Pin Status During Wait Mode is revised Table 8 6 Interrrupts to Stop Mode and Use Conditions is added Table 8 7 Pin Status in Stop Mode is revised Figure 8 13 State Transition in Normal Operation Mode NOTE 7 is deleted Figure 10 4 Interrupt Control Registers 2 NOTE 2 is added 10 5 8 Returning from an Interrupt Routine Last sentence Register bank is added 10 5 9 Interrupt Priority First sentence If two or more is revised 10 5 10 Interrupt Priority Resolution Circuit First sentence The interrupt priority level is revised Figure 10 12 IFSR1 Register NOTES 2 and 4 are revised 10 10 Address Match Interrupt Second line from the bottom The sentence Note that when is added Table 12 1 DMAC Specifications DMA transfer Cycles is added 12 1 Transfer Cycle 3rd and 4th sentences During Furthermore are revised and NOTES 1 and 2 are added 12 1 2 Effect of BYTE Pin Level is added C 3 REVISION HISTORY M16C 6N Group M16C 6NK
286. ce frequency Pulse Width Modify the pulse width as follows Modulation PWM period 28 1 X m 1 fj 00h to FEh Mode High level PWM pulse width m 1 n fj High order address 8 bit PWM where n high order address set value 00h to FFh low order address set value fj Low order address count source frequency Function varies with each operation mode NOTES 1 The register must be accessed in 16 bit unit 2 The timer counts pulses from an external device or overflows or underflows in other timers 3 If the TAi register is set to 0000h the counter does not work and timer Ai interrupt requests are not generated either Furthermore if pulse output is selected no pulses are output from the TAiOUT pin 4 Use the MOV instruction to write to the TAi register 5 f the TAI register is set to 0000h the pulse width modulator does not work the output level on the TAiOUT pin remains low and timer Ai interrupt requests are not generated either The same applies when the 8 high order bits in the TAi register are set to 00h while operating as an 8 bit pulse width modulator Figure 13 4 TAOMR to TA4MR Registers and TAO to TA4 Registers Rev 2 00 Nov28 2005 page 116 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol After Reset TABSR 00h
287. ceiving slot 1 interrupt enabled the CANi successful reception interrupt request is generated and the MBOX bit in the CiSTR register is changed It shows the slot number where the message was stored and the RecSucc bit in the CiSTR register is active 4 Read the message out of the slot after setting the New Data bit to 0 the content of the slot is read or still under processing by the CPU by a program 5 When next CAN message is received before the the NewData bit is set to 0 by a program or a receive request to a slot is canceled the MsgLost bit in the CiMCTLj register is set to 1 message has been overwritten The new received message is transferred to the slot Generating of an interrupt request and change of the CiSTR register are same as in 3 Rev 2 00 Nov28 2005 page 244 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 15 2 Transmission Figure 19 21 shows the timing of the transmit sequence CTX TrmReq bit TrmActive bit CiMCTLj register SentData bit CANi Successful Transmission Interrupt TrmState bit TrmSucc bit CiSTR register MBOX bit Transmission slot No Figure 19 21 Timing of Transmit Sequence 1 If the TrmReq bit in the CiMCTLj register i 0
288. chdog timer Figure 11 2 shows the watchdog timer related registers Prescaler 4 16 H CPU clock i i PM12 0 HOLD za wee 9 Watchdog timer Interrupt request PM12 1 Watchdog timer Reset P On chip oscillator clock Write to WDTS register Internal RESET signal L active CMO7 Bit in CMO register WDC7 Bit in WDC register PM12 Bit in PM1 register PM22 Bit in PM2 register Figure 11 1 Watchdog Timer Block Diagram Rev 2 00 Nov28 2005 page 101 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 Watchdog Timer Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 bi b Symbol Address After Reset Ljejo wc O00Fh OOXXXXXXD High order Bit of Watchdog Timer Po 0 Divided by 16 WDC7 Prescaler Select Bit 1 Divided by 128 Watchdog Timer Start Register x Symbol Address After Reset fT WDTS OOOEh Indeterminate Function The watchdog timer is initialized and starts counting after a write instruction to this register The watchdog timer value is always initialized to 7FFFh regardless of whatever value is written 1 Write to the WDTS register after the watchdog timer interrupt request is generated Figure 11 2 WDC Register and WDTS Register 11 1 Count Source Protective Mode In this mode a on chip oscillator clock is use
289. ck 2 VCC 5 0V 8 Kbyte block 32 Kbyte block 64 Kbyte block Erase All Unlocked Blocks Time Flash Memory Circuit Stabilization Wait Time NOTES 1 Referenced to VCC 4 5 to 5 5V 3 0 to 3 6V Topr 0 to 60 C unless otherwise specified 2 Program and Erase Endurance refers to the number of times a block erase can be performed If the program and erase endurance is n n 100 each block can be erased n times For example if a 4 Kbyte block A is erased after writing 1 word data 2 048 times each to a different address this counts as one program and erase endurance Data cannot be written to the same address more than once without erasing the block Rewrite prohibited 3 n denotes the number of blocks to erase Table 22 9 Flash Memory Version Program Erase Voltage and Read Operation Voltage Characteristics at Topr 0 to 60 C Flash Program Erase Voltage Flash Read Operation Voltage VCC 3 3 0 3V or 5 0 0 5V VCC 3 0 to 5 5V Table 22 10 Power Supply Circuit Timing Characteristics Measuring Standard Time for Internal Power Supply Stabilization During Powering On VCC 3 0 to 5 5V STOP Release Time Low Power Dissipation Mode Wait Mode Release Time ta P R Time for Internal Power Supply Stabilization During Powering On CPU clock LILI ta R S Interrupt for a Stop mode release STOP Release Time r b Wait mode
290. ck diagram of flash memory The user ROM area is divided into several blocks each of which can individually be protected locked against programming or erasure The user ROM area can be rewritten in all of CPU rewrite standard serial I O mode parallel I O mode and CAN I O mode Block A is enabled for use by setting the PM10 bit in the PM1 register to 1 block A enabled CS2 area at addresses 10000h to 26FFFh The boot ROM area is located at the same addresses as the user ROM area It can only be rewritten in parallel I O mode refer to 21 1 1 Boot Mode A program in the boot ROM area is executed after a hardware reset occurs while an H signal is applied to the CNVSS and P5 0 pins and an L signal is applied to the P5_5 pin refer to 21 1 1 Boot Mode A program in the user ROM area is executed after a hardware reset occurs while an L signal is applied to the CNVSS pin However the boot ROM area cannot be read 00F000h 1 OOFEFFh Block A 4 Kbytes 1 080000h Block 12 64 Kbytes Block 11 64 Kbytes Block 10 64 Kbytes OAFFFFh 0BO000h Block 9 64 Kbytes OBFFFFh 0C0000h Block 8 64 Kbytes Block 7 64 Kbytes Block 5 32 Kbytes ODFFFFh OE0000h Block 4 8 Kbytes Block 6 64 Kbytes Block 3 8 Kbytes Block 2 8 Kbytes Block 5 to 0 32 8 8 8 4 4 Kbytes Block 1 4 Kbytes Block 0 4 Kbytes OF FGOOR 4 Kbytes User ROM area Boot ROM area 2 Shown here is a block diagram during single chip mode
291. clock the division value of the baud rate prescaler and the number of Tq of one bit Table 19 2 shows the examples of bit rate Table 19 2 Examples of Bit rate 1Mbps 500kbps 10Tq 1 125kbps 10Tq 4 20Tq 2 83 3kbps 10Tq 6 20Tq 3 33 3kbps 10Tq 15 NOTES 1 The number in indicates a value of CAN division value multiplied by baud rate prescaler division value 2 24 MHz is available Normal ver only 19 8 1 Calculation of Bit rate f1 2 X fCAN division value X baud rate prescaler division value X number of Tq of one bit NOTES 1 fCAN division value 1 2 4 8 16 fCAN division value a value selected in the CCLKR register 2 Baud rate prescaler division value P 1 P 0 to 15 P a value selected in the BRP bit in the CICONR register i 0 1 Rev 2 00 Nov28 2005 page 238 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 9 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message The CiGMR register i 0 1 the CiLMAR register and the CiLMBR register can perform masking to the standard ID and the extended ID of 29 bits The CiIGMR register corresponds to slots 0 to 13 the CiLMAR register corresponds to slot 14 and the CiLMBR register corresponds to slo
292. code check function for standard serial I O mode and CAN I O mode to prevent the flash memory from reading or rewriting 21 2 1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I O mode Figure 21 2 shows the ROMCP register The ROMCP register is located in the user ROM area The ROM code protect function is enabled when the ROMCR bits are set to other than 11b In this case set the bit 5 to bit O to 111111b When exiting ROM code protect erase the block including the ROMCP register by the CPU rewrite mode or the standard serial I O mode or CAN I O mode 21 2 2 ID Code Check Function Use the ID code check function in standard serial I O mode and CAN I O mode The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match If the ID codes do not match commands sent from the serial programmer are not accepted However if the four bytes of the reset vector are FFFFFFFFh ID codes are not compared allowing all commands to be accepted The ID codes are 7 byte data stored consecutively starting with the first byte into addresses OFFFDFh OFFFESh OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh The flash memory must have a program with the ID codes set in these addresses Figure 21 3 shows the ID code store addresses Rev 2 00 Nov28 2005 page 262 of 378 RENESAS REJ09B0124 0200 Under development This docu
293. conversion result is stored in the bit 0 to bit 9 in the ADi register i 0 to 7 If the BITS bit is set to 0 8 bit conversion accuracy the A D conversion result is stored in the bit O to bit 7 in the ADi register 16 2 2 Sample and Hold If the SMP bit in the ADCON register is set to 1 with sample and hold the conversion speed per pin is increased to 28 oAD cycles for 8 bit resolution or 33 AD cycles for 10 bit resolution Sample and hold is effective in all operation modes Select whether or not to use the sample and hold function before starting A D conversion 16 2 3 Extended Analog Input Pins In one shot and repeat modes the ANEXO and ANEX1 pins can be used as analog input pins Use the OPA1 to OPAO bits in the ADCON1 register to select whether or not use ANEXO and ANEX1 The A D conversion results of ANEXO and ANEX1 inputs are stored in the ADO and AD1 registers respectively 16 2 4 External Operation Amplifier Op Amp Connection Mode Multiple analog inputs can be amplified using a single external op amp via the ANEXO and ANEX1 pins Set the OPA1 to OPAO bits in the ADCON1 register to 11b external op amp connection mode The inputs from ANi i 0 to 7 are output from the ANEXO pin Amplify this output with an external op amp before sending it back to the ANEX1 pin The A D conversion result is stored in the corresponding ADi register The A D conversion speed depends on the response characteristics of the external
294. ct to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode Single chip mode 00000h SFR 00400h PM13 bit in PM1 register 0 Internal RAM Internal RAM Internal ROM XXXXXh Address XXXXXh Address YYYYYh Can not use PM13 bit 1 internal ROM FFFFFh NOTES 1 If the PM13 bit in the PM1 register is set to 0 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used 2 For the mask ROM version set the PM10 bit in the PM1 register to 0 block A disabled addresses 08000h to 26FFFh for CS2 area Figure 6 3 Memory Map in Single chip Mode Rev 2 00 Nov28 2005 page 42 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode ll When PM13 0 and PM10 0 Memory expansion mode Microprocessor mode Internal RAM Internal RAM Reserved area Reserved area Reserved area Reserved area External area External area Memory expansion mode 320 Kbytes Microprocessor mode 832 Kbytes Internal RAM Internal ROM Capacity Address XXXXXh Capacity Address YYYYYh 16 Kbytes 192 Kbytes Dooooh 20 Kbytes 256Kbytes Doo00h 31 Kbytes 384 Kbytes Dooooh 512 Kbytes NOTES 1 If the PM13 bit in the PM1 register is set to 0 192 Kbytes of the internal ROM can be used 2 Not available memory expansion and microprocessor modes in T V ver Figu
295. ction share the vector and interrupt control register When using the timer B3 interrupt set the IFSRO6 bit to 0 Tmer B3 When using UARTO bus collision detection set the IFSRO6 bit to 1 UARTO bus collision detection 8 Timer B4 and UART1 bus collision detection share the vector and interrupt control register When using the timer B4 interrupt set the IFSRO7 bit to 0 Timer B4 When using UART1 bus collision detection set the IFSRO7 bit to 1 UART1 bus collision detection Figure 10 11 IFSRO Register Rev 2 00 Nov28 2005 page 95 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Interrupt Request Cause Select Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address IFSR1 01DFh 10 Interrupt After Reset 00h Le mmm G INT3 Interrupt Polarity i Switching Bit INT4 Interrupt Polarity IFSR14 Switching Bit 0 One edge 1 Both edges 1 One edge Both edges 1 INT5 Interrupt Polarity IFSR19 Switching Bit One edge Both edges 1 IFSR16 Interrupt FOR Cause CAN1 successful transmission SI 03 3 Select Bit 2 INT4 IFSR17 Interrupt Er est Cause CAN1 successful reception SI O4 5 Select Bit 4 INT5 1 When setting this bit to 1 both edges make sure the POL bit in the INTOIC to INT5IC register is set to 0 falling edge 2 CAN1 successful transmission
296. d Rev 2 00 Nov28 2005 page 243 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 15 1 Reception Figure 19 20 shows the behavior of the module when receiving two consecutive CAN messages that fit into the slot of the shown CiMCTLj register i 0 1 j 0 to 15 and leads to losing overwriting of the first message CANbus RecReq bit InvalData bit NewData bit CiMCTLj register MsgLost bit CANi Successful Reception Interrupt RecState bit RecSucc bit CiSTR register MBOX bit Receive slot No i20 1 j20t015 Figure 19 20 Timing of Receive Data Frame Sequence 1 On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register becomes 1 CAN module is receiver immediately given the module has no transmission pending 2 After successful reception of the message the NewData bit in the CiMCTLj register of the receiving slot becomes 1 stored new data in slot The InvalData bit in the CiMCTLj register becomes 1 message is being updated at the same time and the InvalData bit becomes 0 message is valid again after the complete message was transferred to the slot 3 When the interrupt enable bit in the CilCR register of the re
297. d CM17 bits enabled Figure 8 3 CM1 Register Rev 2 00 Nov28 2005 page 59 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset iW N E dojo CM2 000Ch 0X000000b 2 0 Oscillation stop re oscillation detection function disabled 1 Oscillation stop re oscillation detection function enabled Main clock or PLL clock System Clock Select a Ell 2 2 5 6 7 8 11 On chip oscillator clock _ On chip oscillator oscillating Oscillation Stop Main clock stop re oscillation Re Oscillation Detection not detected Apa Flag 9 Main clock stop re oscillation detected Main clock oscillating CM23 XIN Monitor Flag 10 Mainclock tured off RO ee Oscillation Stop Re Oscillation Detection Enable Bit 2 3 4 Nothing is assigned When write set to 0 When read its content is indeterminate Operation Select Bit 0 Oscillation stop detection reset behavior if oscillation stop 1 Oscillation stop re oscillation re oscillation is detected 2 detection interrupt Write to this register after setting the PRCO bit in the PRCR register to 1 write enable The CM20 CM21 and CM27 bits do not change at oscillation stop detection reset Set the
298. d Read Operation Voltage Characteristics at Topr 0 to 60 C Flash Program Erase Voltage Flash Read Operation Voltage VCC 5 0 0 5V VCC 4 2 to 5 5V Table 22 55 Power Supply Circuit Timing Characteristics Measuring Standard Condition Min Typ Max Time for Internal Power Supply Stabilization During Powering On VCC 4 2 to 5 5V STOP Release Time Low Power Dissipation Mode Wait Mode Release Time Parameter ta P R Time for Internal Power Supply Stabilization During Powering On CPU clock LILI ta R S Interrupt for a Stop mode release STOP Release Time or b Wait mode release ta w s Low Power Dissipation Mode CPU clock TTT T Wait Mode Release Time ta R S Figure 22 22 Power Supply Circuit Timing Diagram Rev 2 00 Nov 28 2005 page 334 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Timing Requirements 22 Electric Characteristics T V ver VCC 5V Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 56 External Clock Input XIN Input Parameter External Clock Input Cycle Time Standard Min Max External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time TAiIN Input Cycle Time Paramet
299. d for the watchdog timer count source The watchdog timer can be kept being clocked even when CPU clock stops as a result of runaway Before this mode can be used the following register settings are required 1 Set the PRC1 bit in the PRCR register to 1 enable writes to the PM1 and PM2 registers 2 Set the PM12 bit in the PM1 register to 1 reset when the watchdog timer underflows 3 Set the PM22 bit in the PM2 register to 1 on chip oscillator clock used for the watchdog timer count source 4 Set the PRC1 bit in the PRCR register to 0 disable writes to the PM1 and PM2 registers b Write to the WDTS register watchdog timer starts counting xwx rr Setting the PM22 bit to 1 results in the following conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer count source Watchdog timer count 32768 Watchdog timer period on chip oscillator clock The CM10 bit in the CM1 register is disabled against write Writing a 1 has no effect nor is stop mode entered The watchdog timer does not stop when in wait mode or hold state Rev 2 00 Nov28 2005 page 102 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC 12 DMAC The DMAC Direct Memory Access Controller allows data to be transferred without the CPU i
300. d from the on chip oscillator clock To enter wait mode while using the oscillation stop and re oscillation detection function set the CMO2 bit to 0 peripheral function clocks not turned off during wait mode Since the oscillation stop and re oscillation detection function is provided in preparation for main clock stop due to external factors set the CM20 bit to 0 oscillation stop re oscillation detection function disabled where the main clock is stopped or oscillated in the program that is where the stop mode is selected or the CMOS5 bit is altered e This function cannot be used if the main clock frequency is 2 MHz or less In that case set the CM20 bit to 0 Switch the main clock Determine several times whether the CM23 bit is set to 0 main clock oscillates Set the CMO6 bit to 1 divide by 8 Set the CM22 bit to 0 main clock stop re oscillation not detected Set the CM21 bit to 0 main clock for the CPU clock source 1 CMO6 bit Bit in CMO register CM21 CM22 CM 23 bits Bits in CM2 register NOTE 1 If the clock source for CPU clock is to be changed to PLL clock set to PLL operation mode after set to high speed mode Figure 8 14 Procedure to Switch Clock Source from On chip Oscillator to Main Clock Rev 2 00 Nov28 2005 page 79 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK
301. d in same way as ANO to ANT Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 After rewriting the MD1 to MDO bits set the CH2 to CHO bits over again using another instruction A D Control Register 1 b7 b6 b5 b4 b3 b2 bi Symbol Address After Reset Pia le ADCON1 03D7h 00h meu come cu ccce cc U A D Sweep Pin Select Bit Invalid in repeat mode A D Operation Mode Set to 0 when repeat mode is Select Bit 1 selected Hh 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode A Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 2 VREF connected aw b7 b6 0 0 ANEXO and ANEX1 are not used RW External Op Amp 0 1 ANEXO input is A D converted Connection Mode Bit 10 ANEX1 input is A D converted 1 External op amp connection mode 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 5 ADCONO Register and ADCON1 Register in Repeat Mode Rev 2 00 Nov28 2005 page 209 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter 16 1 3 Single Sweep Mode In single sweep mode analog voltage that is applied to selected pins is converted one by one to a digital code Table 16 4 l
302. d mode When the CM21 bit 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CMO6 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High Figure 8 13 State Transition in Normal Operation Mode Rev 2 00 Nov 28 2005 page 76 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 8 8 Allowed Transition and Setting 9 Current state State after transition 8 Clock Generating Circuit High Speed Mode Medium Speed Mode Low Power Dissipation Mode Low Speed Mode PLL Operation Mode 2 High Speed Mode Medium Speed Mode On chip Oscillator D chip Oscillator Low Power Dissipation Mode Mode Low Speed Mode Low Power Dissipation Mode PLL Operation Mode On chip Oscillator Mode On chip Oscillator Low Power Dissipation Mode Stop Mode Wait Mode Cannot transit NOTES 1 Avoid making a transition when the CM20 bit 1 oscillation stop re oscillation detection function enabled Set the CM20 bit to 0 oscillation stop re oscillation detection function disabled before transiting On chip oscillator clock oscillates and stops in low speed mode In this mode the on chip oscillator can be used as peripheral function clock Sub c
303. d rd eer Bod Oo oj oJ oloolol oj oj o ooj oloo TM CO E WI DH O CN D o1 BY Gd PO s s Sls s S s s s s S S 35 3 35 eo A oo pare e eo ok m 2 CANO Message Box 13 Identifier DLC OoO oilojlo par ar ear are w w w CO O1 A S aa a F eo A wo NJ a CANO Message Box 13 Data Field 013Dh 013Eh 013Fh The blank areas are reserved O CO O OF SEE SF BEBE 5 35 35 3 5 B 3 Symbol Timer B3 B4 B5 Count Start Flag Timer A1 1 Register Timer A2 1 Register Timer A4 1 Register Three Phase PWM Control Register 0 Three Phase PWM Control Register 1 INVC1 Three Phase Output Buffer Register 0 IDBO Three Phase Output Buffer Register 1 IDB1 Dead Time Timer DTT Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 Interrupt Cause Select Register 2 IFSR2 Timer B3 Register TB3 Timer B4 Register TB4 Timer B5 Register TB5 SI O6 Transmit Receive Register S6TRR SI O6 Control Register Sec SI O6 Bit Rate Generator SeBRG SI O3 4 5 6 Transmit Receive Register S3456TRR Timer B3 Mode Register TB3MR Timer B4 Mode Register TB4MR Timer B5 Mode Register Interrupt Cause Select Register 0 Interrupt Cause Select Register 1 SI O3 Transmit Receive Register SI O3 Control Register SI O3 Bit Rate Generator SI O4 Trans
304. data is written to the SiTRR register during this period SOUTi immediately goes to a high impedance state with the data hold time thereby reduced 4 When the SMi6 bit 1 internal clock the transfer clock stops in the high state if the SMi4 bit 0 or stops in the low state if the SMi4 bit 1 Co Rev 2 00 Nov28 2005 page 199 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 2 1 SI Oi Operation Timing Figure 15 39 shows the SI Oi operation timing 1 5 cycle max 1 SI Oi internal clock CLKi output Signal written to the SiTRR register SOUTi output SINi input IR bit in SilC register SiTRFbitin S3456TRR register o i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in the SiC register are set as follows e SMi2 0 SOUTi output e SMi3 1 SOUTi output CLKi function e SMi4 0 transmit data output at the falling edge and receive data input at the rising edge of the transfer clock SMi5 0 LSB first e SMi6 1 internal clock NOTES 1 If the SMi6 bit 1 internal clock the serial I O starts sending or receiving data a maximum of 1 5 transfer clock cycles after writing to the SiTRR register 2 When the SMi6 bit 1 internal clock the SOUTi pin is placed in the high impedance state after the transfer fini
305. ddresses TAj TAk 0387h 0386h Timer A4 Timer A1 0389h 0388h Timer AO Timer A2 038Bh 038Ah Timer A1 Timer A3 038Dh 038Ch Timer A2 Timer A4 038Fh 038Eh Timer A3 Timer AO Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Timer Ai Mode Register i 2 O to 4 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h Bit Symbol b1 b0 0 0 Timer mode Operation Mode Select Bit 9 1 Event counter mode 1 0 One shot timer mode 1 Pulse width modulation mode MR1 MR2 MR3 TCKO i i i Count Source Select Bit E uncuon varies wilt each TCK1 operation mode Timer Ai Register i 0 to 4 Address After Reset ous us 0387h to 0386h Indeterminate 0389h to 0388h Indeterminate Lo 1 038Bh to 038Ah Indeterminate 038Dh to 038Ch Indeterminate 038Fh to O38Eh Indeterminate weds Fuion J Setting Range Timer E the count source by n 1 where n Event Divide the count source by FFFFh n 1 Counter where n set value when M up Or 0000h to FFFFh Mode by n 1 when counting down 2 One shot Divide the count source by n where n set 3 4 value and cause the timer to stop 0000h to FFFFh 9 WO Pulse Width Modify the pulse width as follows Modulation PWM period 216 1 fj Mode High level PWM pulse width n fj 0000h to FFFEh 4 5 16 bit PWM where n set value fj count sour
306. de CLKOUT NOTES When fC selected Does not become a CLKOUT pin When f8 f32 selected H Retains status before stop mode 1 Not available memory expansion and microprocessor modes in T V ver 2 Not available the bus control pins in T V ver Rev 2 00 Nov 28 2005 page 73 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 4 3 3 Exiting Stop Mode Stop mode is exited by a hardware reset NMI interrupt or peripheral function interrupt When the hardware reset or NMI interrupt is used to exit wait mode set all ILVL2 to ILVLO bits in the interrupt control registers for the peripheral function interrupt to 000b interrupt disabled before setting the CM10 bit in the CM1 register to 1 When the peripheral function interrupt is used to exit stop mode set the CM10 bit to 1 after the following settings are completed 1 The ILVL2 to ILVLO bits in the interrupt control registers for the peripheral function interrupt used to exit stop mode must have larger value than that of the RLVL2 to RLVLO bits The ILVL2 to ILVLO bits in all other interrupt control registers for the peripheral function interrupts which are not used to exit stop mode must be set to 000b interrupt disabled 2 Set the flag to 1 3 Start operation of peripheral function be
307. de Boot mode Parallel I O mode Boot mode ROM Programmer NOTES None Serial programmer Parallel programmer CAN programmer 1 The PM13 bit remains set to 1 while the FMRO 1 bit in the FMRO register 1 CPU rewrite mode enabled The PM13 bit is reverted to its original value by setting the FMRO 1 bit to 0 CPU rewrite mode disabled However if the PM13 bit is changed during CPU rewrite mode its changed value is not reflected until after the FMRO 1 bit is set to 0 2 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit 1 3 When using the standard serial I O mode 2 make sure a main clock input oscillation frequency is set to 5 MHz 10 MHz or 16 MHz 4 Not available in T V ver Rev 2 00 Nov 28 2005 page 260 of 378 REJ09B0124 0200 131 NE ESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 1 Memory Map The flash memory contains the user ROM area and a boot ROM area The user ROM area has space to store the microcomputer operating program in single chip mode or memory expansion mode and a separate 4 Kbyte space as the block A Not available memory expansion mode in T V ver Figure 21 1 shows the blo
308. der development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface UARTi Special Mode Register 2 i O to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset KITII UOSMR to U2SMR2 01EEh 01F2h 01F6h X0000000b 12C Mode Select Bit 2 See Table 15 12 I C Mode Functions RW Clock Synchronous Disabled Bit Enabled Disabled SCL Wait Output Bit Enabled Disabl SDA Output Stop Bit dien UARTi Initialization Disabled Bit Enabled SCL Wait Output 0 Transfer clock Bit 2 1 L output SDA Output Disable 0 Enabled Bit 1 Disabled high impedance Nothing is assigned When write set to 0 When read its content is indeterminate UARTi Special Mode Register 3 i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOSMR3 to U2SMR3 01EDh 01F1h 01F5h 000X0X0Xb Nothing is assigned When write set to 0 When read its content is indeterminate 0 Without clock delay 1 With clock delay Nothing is assigned When write set to O When read its content is indeterminate Clock Output Select 0 CLKi is CMOS output Clock Phase Set Bit Bit 1 CLKi is N channel open drain output Nothing is assigned When write set to O When read its content is indeterminate Without delay 1 to 2 cycle s of UIBRG count source PAM 2 to 3 cycles of UIBRG count source SDAi Digit
309. ding receiving data beginning with bit 0 or beginning with bit 7 can be selected Serial data logic switch This function reverses the logic of the transmit receive data The start and stop bits are not reversed e TXD RXD I O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input The logic levels of all I O data is reversed Separate CTS RTS pins UARTO CTSO and RTSO are input output from separate pins 1 The UOIRS and U1IRS bits are bits 0 and 1 in the UCON register The U2IRS bit is bit 4 in the U2C1 register 2 If an overrun error occurs the value of the UiRB register will be indeterminate The IR bit in the SiRIC register does not change 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTI receive register to the UiRB register Rev 2 00 Nov28 2005 page 167 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Table 15 6 Registers to Be Used and Settings in UART Mode Register 0 to 8 Function Set transmission data 0 to 8 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set these bits to 100b when transfer data is 7 bit long Set these bits to 101b when transfer data is 8 bit long Set
310. dissipation mode the fi fiSIO fAD fC ANO and fCAN1 clocks are turned off The fC32 clock is derived from the sub clock and is used for timers A and B This clock can be used when the sub clock is activated NOTE 1 fCANO and fCAN1 clocks stop at H in CANO 1 sleep mode 8 3 Clock Output Function During single chip mode the f8 f32 or fC clock can be output from the CLKOUT pin Use the CMO1 to CMOO0 bits in the CMO register to select Rev 2 00 Nov28 2005 page 68 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 4 Power Control Normal operation mode wait mode and stop mode are provided as the power consumption control All mode states except wait mode and stop mode are called normal operation mode in this document 8 4 1 Normal Operation Mode Normal operation mode is further classified into seven sub modes In normal operation mode because the CPU clock and the peripheral function clocks both are on the CPU and the peripheral functions are operating Power control is exercised by controlling the CPU clock frequency The higher the CPU clock frequency the greater the processing capability The lower the CPU clock frequency the smaller the power consumption in the chip If the unnecessary oscillator circuits are turned off the power consumption is further reduced Before the clock s
311. dition of Vo is revised from Lo 200pA to Lo 200pA Table 21 5 Electrical Characteristics 2 Mask ROM 5th item e f XCIN is changed to f BCLK Table 21 6 A D Conversion Characteristics Tolerance Level Impedance is deleted 22 14 Programmable I O Ports last 1 to 2 lines e 1 Setting Procedure is revised from 00010000b to 00000001b e 2 Setting Procedure is revised from 00010011b to 00110001b Revised edition issued Memory expansion and microprocessor modes are added to Normal ver Electric Characteristics of T V ver is added Revised parts and revised contents are as follows except for expressional change 1 1 Applications Comment of T V ver is added Table 1 1 Performance Outline 100 pin version Operation Mode of Normal ver is revised Table 1 2 Performance Outline 128 pin version Operation Mode of Normal ver is revised Table 1 3 Product List NOTE 1 is added Figure 1 3 Pin Configuration 1 Bus control pins are added and NOTE 2 is added Tables 1 4 and 1 5 Pin Characteristics in 100 pin version 1 2 are added Figure 1 4 Pin Configuration 2 Bus control pins are added and NOTE 2 is added 10 to 12 Tables 1 6 to 1 8 Pin Characteristics in 128 pin version 1 2 3 are added 13 to 15 Tables 1 8 to 1 10 Pin Description 1 2 3 are revised 18 3 Memory Last 2 sentences In memory expansion Use T V ver are added Figure 3 1 Memory Map NOTES 1 and 2 are add
312. does not enter reset mode for the CPU read has the higher priority ization mode O Updated without fail in period of A CAN i20 1 Figure 23 7 When Polling Period of CPU is 3fCAN or Longer Rev 2 00 Nov28 2005 page 363 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 14 2 Performing CAN Configuration If the Reset bit in the CiCTLR register i 0 1 is changed from 0 operation mode to 1 reset initialization mode in order to place the CAN module from CAN operation mode into CAN reset initializa tion mode always be sure to check that the State Reset bit in the CiSTR register is set to 1 reset mode Similarly if the Reset bit is changed from 1 to 0 in order to place the CAN module from CAN reset initialization mode into CAN operation mode always be sure to check that the State Reset bit is set to 0 operation mode The procedure is described below To place CAN Module from CAN Operation Mode into CAN Reset Initialization Mode e Change the Reset bit from 0 to 1 Check that the State Reset bit is set to 1 To place CAN Module from CAN Reset Initialization Mode into CAN Operation Mode e Change the Reset bit from 1 to 0 e Check that the State Reset bit is set to 0 Rev 2 00 Nov28 2005 page 364 of 378 RENESAS REJ0
313. driving the A D converter turns out to be approximately 13 9 kQ Rev 2 00 Nov28 2005 page 217 of 378 RENESAS REJ09B0124 0200 16 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Microcomputer Sensor equivalent circuit R 7 8 KQ VV e Sampling time C 1 5 pF Sample and hold enabled JAD N f 2 Sample and hold disabled AD Figure 16 10 Analog Input Pin and External Sensor Equivalent Circuit Rev 2 00 Nov 28 2005 page 218 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 17 D A Converter 17 D A Converter This is an 8 bit R 2R type D A converter These are two independent D A converters D A conversion is performed by writing to the DAi register i 0 1 To output the result of conversion set the DAiE bit in the DACON register to 1 output enabled Before D A conversion can be used the corresponding port direction bit must be set to 0 input mode Setting the DAiE bit to 1 removes a pull up from the corresponding port Output analog voltage V is determined by a set value n decimal in the DAi register V VREF X n 256 n 0 to 255 VREF reference voltage Table 17 1 lists the performance of the D A converter Figure 17 1 shows the block diagram of the D A
314. during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ADCON1 03D7h 00h Bi symbol Function varies with each operation mode A D Sweep Pin Select Bit A D Operation Mode 0 Any mode other than repeat Select Bit 1 sweep mode 1 Repeat sweep mode 1 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode Refer to NOTE 2 for ADCON2 CKS1 Frequency Select Bit 1 Register 0 VREF not connected VCUT VREF Connect Bit 2 1 VREF connected be External Op Amp Function varies Connection Mode Bit with each operation mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 2 ADCONO Register and ADCON1 Register Rev 2 00 Nov28 2005 page 204 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 2 x b6 5 b4 b3 b2 bi bO Symbol Address After Reset ADCON2 03D4h 00h Function b2 b1 0 0 Port P10 group is selected 1 0 Port PO group is selected 1 Port P2 group is selected 0 Selects fAD divide by 2 of fAD or divide by 4 of fAD 1 Selects divide by 3 of fAD divide
315. e Table 15 10 lists the specifications of the IC mode Figure 15 23 shows the block diagram for I C mode Table 15 11 lists the registers used in the I C mode and the register values set Table 15 12 lists the functions in IPC mode Figure 15 24 shows the transfer to the UiRB register and interrupt timing As shown in Table 15 12 the microcomputer is placed in I C mode by setting the SMD2 to SMDO bits to 010b and the IICM bit to 1 Because SDAi transmit output has a delay circuit attached SDAi output does not change state until SCLi goes low and remains stably low Table 15 10 1 C Mode Specifications Specification Transfer Data Format Transfer data length 8 bits Transfer Clock During master The CKDIR bit in the UiMR register 0 internal clock fj 2 n 1 fj f1SIO f2SIO f8SIO f32SIO n Setting value of the UiBRG register 00h to FFh During slave The CKDIR bit 1 external clock Input from SCLi pin Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in the UiTB register Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register 0 data present in the UiTB register Inte
316. e 21 6 lists errors and FMRO register state Figure 21 12 shows a flow chart of the full status check and handling procedure for each error Table 21 6 Errors and FMRO Register Status FRMOO Register Status Register Status Error Occurrence Conditions FMRO7 bit FMROG bit SR5 SR4 Command e Command is written incorrectly Sequence e A value other than xxDOh or xxFFh is written in the second error bus cycle of the lock bit program block erase or erase all unlocked block command Erase error e The block erase command is executed on a locked block e The block erase or erase all unlocked block command is executed on an unlock block and auto erase operation is not completed as expected Program error e The program command is executed on locked blocks The program command is executed on unlocked blocks but program operation is not completed as expected e The lock bit program command is executed but program operation is not completed as expected NOTES 1 The flash memory enters read array mode by writing command code xxFFh in the second bus cycle of these commands The command code written in the first bus cycle becomes invalid 2 When the FMRO2 bit in the FMRO register is set to 1 lock bit disabled no error occurs even under the conditions above Rev 2 00 Nov28 2005 page 280 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents a
317. e BCLK frequency as follows 9 aa cor 40 ns nis 2 for 2 wait setting 3 for 3 wait setting 3 Calculated according to the BCLK frequency as follows 0 5 X 10 f BCLK ne 4 Calculated according to the BCLK frequency as follows 0 5 X 10 ao 15 f BCLK Ins Rev 2 00 Nov 28 2005 page 304 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver XIN input TAIIN input TAiOUT input re TAiOUT input Up down input X During event counter mode TAIIN input When count on falling edge thctin uPy fsu UP riN is selected TAIIN input When count on rising edge is selected Two phase pulse input in event counter mode tea TAIIN input tsu TAIN TAOUT tsu TAIN TAOUT tsu TAOUT TAIN TAiOUT input tsu TAOUT TAIN tc TB i tw TBH TBiIN input ADTRG input TXDi RXDi tw INL INTI input Figure 22 4 Timing Diagram 1 Rev 2 00 Nov 28 2005 page 305 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode Effecti
318. e Control Register 0 COMCTLO 00h CANO Message Control Register 1 COMCTL1 00h CANO Message Control Register 2 COMCTL2 00h CANO Message Control Register 3 COMCTLS 00h CANO Message Control Register 4 COMCTL4 00h CANO Message Control Register 5 COMCTL5 00h CANO Message Control Register 6 COMCTL6 00h CANO Message Control Register 7 COMCTL7 00h CANO Message Control Register 8 COMCTL8 00h CANO Message Control Register 9 COMCTL9 00h CANO Message Control Register 10 COMCTL10 00h CANO Message Control Register 11 COMCTL11 00h CANO Message Control Register 12 COMCTL12 00h CANO Message Control Register 13 COMCTL13 00h CANO Message Control Register 14 COMCTL14 00h CANO Message Control Register 15 COMCTL15 00h s X0000001b 0211h CANO Control Register COCTLR XX0X0000b 0212h 00h 0213h CANO Status Register COSTR X0000001b 0214h 00h 0215h CANO Slot Status Register COSSTR 00h 0216h 00h 0217h CANO Interrupt Control Register COICR Ooh 0218h 00h 0219h CANO Extended ID Register COIDR 00h BEAD CANO Configuration Register COCONR a CANO Receive Error Count Register CORECR CANO Transmit Error Count Register COTECR CANO Time Stamp Register COTSR CAN1 Message Control Register 0 C1MCTLO CAN1 Message Control Register 1 C1MCTL1 CAN1 Message Control Register 2 C1MCTL2 CAN1 Message Control Register 3 C1MCTLS CAN1 Message Control Register 4 C1MCTL4 CAN1 Message Control Register 5 C1MCTL5 CAN1 Message Control Register 6 C1MCTL6 CAN1 Message
319. e GR ar ELE a hoe diene aD i 371 23 19 8 Operation SPCC tenemento eese cxi iq esit pasa tenuis egeat ee aiei 371 23 19 9 Prohibited Instr Cllonis uec rnt Lettera eo etes etre tu vies tdi Dixerat tede tet uu deed 372 23 19 10 IMTS rrUpt e 372 29 191 How tO ACCOSS c ectetur ep oe Sunutue scccueatedzes Saas its i cotat cud tame expos e eset eee ieha 372 23 19 12 Rewriting in User ROM Area sssssssssssseeeeeeeeeee nennen nennen enne nnne nnne nenne nennen nnne nens 372 23 19 13 DMA TrANS OT TL 372 23 20 Flash Memory Programming Using Boot Program ssseeeeeennneeenmenn nnne 373 23 20 1 Programming Using Serial l O Mode ssssssssssesseseseseeneeeneneeneee enne nnns 373 23 20 2 Programming Using CAN VO Mode rta ron Cnt rh eek et veg atu cepe eds x dure A 373 23 21 NOISE airan o abet tert ceidteteain tee baie e n E ILLIC 374 Appendix 1 Package Dimensions uo cceosioeocao eoa ono nep te haee pns ounbio nO nas punc ura ero rEdeRRE EDS ci cBE Ea ES 375 Register n Me 377 Specifications written in this manual are believed to be accurate but are not guaranteed to be entirely free of error Specifications in this manual may be changed for functional or performance improvements Please make sure your manual is the latest edition A 6 SFR Page Reference CANO 1 Wake up Interrupt Control R
320. e IR bit in the interrupt control register does not change state due to a DMA transfer A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register 1 DMA enabled However if the cycle in which a DMA request is generated is faster than the DMA transfer cycle the number of transfer requests generated and the number of times data is transferred may not match For details refer to 12 4 DMA Request Rev 2 00 Nov28 2005 page 103 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 12 1 DMAC Specifications 12 DMAC Item Specification No of Channels 2 cycle steal method Transfer Memory Space From any address in the 1 Mbyte space to a fixed address From a fixed address to any address in the 1 Mbyte space e From a fixed address to a fixed address Maximum No of Bytes Transferred 128 Kbytes with 16 bit transfer or 64 Kbytes with 8 bit transfer DMA Request Factors O Falling edge of INTO or INT1 Both edge of INTO or INT1 Timer AO to timer A4 interrupt requests Timer BO to timer B5 interrupt requests UARTO transfer UARTO reception interrupt requests UART1 transfer UART1 reception interrupt requests UART2 transfer UART2 reception interrupt requests SI OS SI O4 interrupt requests A D conversion interrupt requests Software trigger
321. e PMO register is set to 0 output enable a clock with the same frequency as that of the CPU clock is output as BCLK from the BCLK pin Refer to 8 2 CPU Clock and Peripheral Function Clock Table 7 6 shows the pin functions for each processor mode Rev 2 00 Nov28 2005 page 50 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus Table 7 6 Pin Functions for Each Processor Mode Memory Expansion Mode or Microprocessor Mode Memory Expansion Mode 01b CS2 is for multiplexed bus and 11b multiplexed bus for the entire space others are for separate bus 10b CS1 is for multiplexed bus and others are for separate bus PMO5 to PM04 Bits 00b separate bus Data Bus Width BYTE Pin PO Oto PO 7 8 bits 16 bits H e DO to D7 8 bits H DO to D7 16 bits L 8 bits H I O ports P1_0 to P1_7 1 0 ports D8 to D15 I O ports D8 to D15 I O ports P2_0 AO AO0 DO AO A0 DO P2_1 to P2_7 A1 to A7 A1 to A7 D1 to D7 A1 to A7 DO to D6 A1 to A7 D1 to D7 P3 0 A8 A8 D7 A8 P3 1 to P3 3 A9 to A11 I O ports PM11 0 A12 to A15 I O ports PM11 1 I O ports PMO6 0 A16 to A19 I O ports PMO6 1 I O ports CSO 0 I O ports CSO 1 CSO CS1 0
322. e TAiS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the TAOTGL and TAOTGH bits and the TRGSR register are modified while the TAIS bit remains 0 count stops regardless whether after reset or not When setting the TAIS bit to 0 count stop the followings occur A counter stops counting and a content of reload register is reloaded e TAiOUT pin outputs L After one cycle of the CPU clock the IR bit in the TAiIC register is set to 1 interrupt request Output in one shot timer mode synchronizes with a count source internally generated When an external trigger has been selected one cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one shot timer mode The IR bit is set to 1 when timer operation mode is set with any of the following procedures Select one shot timer mode after reset Change an operation mode from timer mode to one shot timer mode Change an operation mode from event counter mode to one shot timer mode To use the Timer Ai interrupt the IR bit set the IR bit to O after the changes listed above have been made When a trigger occurs while counting a counter reloads the reload register to continue counting after generating a re trigger and counting down once To generate a trigger while counting generate a second trigger between occurring the previous trigger and operating longer than one cycl
323. e mode 1 the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger Then the value of the TAi register is transferred by the next trigger The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger 6 Do not write to these registers when the timer B2 underflows 7 Follow the procedure below to set the TAi1 register a Write value to the TAi1 register b Wait one timer Ai count source cycle and c Write the same value as a to the TAi1 register Timer B2 Register b15 b8 b7 bO Address After Reset 0395h 0394h Indeterminate If setting value is n count source is divided by n 1 a The timers A1 A2 and A4 start every time an underflow occurs DOSORHIB 1 Use a 16 bit data for read and write Figure 14 5 TA1 TA2 TAA TA11 TA21 and TA41 Registers and TB2 Register Rev 2 00 Nov28 2005 page 143 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Timer B2 Interrupt Occurrence Frequency Set Counter 0 3 bo Symbol Address After Reset ICTB2 01CDh Indeterminate When the INVO1 bit in the INVCO register is set to 0 the ICTB2 counter increments whenever the timer B2 underflows and the setting value is n the timer B2 interrupt is generated every
324. e motor control circuit A D converter 10 bits X 8 channels Expandable up to 26 channels UART or Clock synchronous serial I O 8 channels System clock generating circuit XIN XOUT XCIN XCOUT PLL frequency synthesizer On chip oscillator Clock synchronous serial I O 8 bits X 4 channels 4 o 2d uod 8d Hog CRC arithmetic circuit CCITT Polynomial X X24 X5 1 CAN module 2 channels Watchdog timer 15 bits M16C 60 series CPU core Memory ROH ROL SB ROM R1H R1L DMAC 2 channels D A converter 8 bits X 2 channels RAM Multiplier t F4 ora uod 6a uoa S 8a voa 8 1 ROM size depends on microcomputer type 2 RAM size depends on microcomputer type 3 Ports P11 to P14 are only in the 128 pin version 4 8 bits X 2 channels in the 100 pin version Figure 1 1 Block Diagram Rev 2 00 Nov28 2005 page 4 of 378 REJ09B0124 0200 34 NESAS Port P14 Port P13 Port P12 8 Wash Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 4 Product List 1 Overview Table 1 3 lists the M16C 6N Group M16C 6NK M16C 6NM products and Figure 1 2 shows the type numbers memory sizes and packages Table 1 3 Product List As of Nov 2005 Type No ROM Capacity R
325. e of a timer count source When the external trigger is selected as count start condition do not input again the external trigger between 300 ns before the counter reachs 0000h If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 2 00 Nov28 2005 page 352 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 1 4 Timer A Pulse Width Modulation Mode The timer remains idle after reset Set the mode count source counter value etc using the TAiMR i 0 to 4 register the TAI register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register are modified while the TAIS bit remains 0 count stops regardless whether after reset or not The IR bit is set to 1 when setting a timer operation mode with any of the following procedures Select the pulse width modulation mode after reset Change an operation mode from timer mode to pulse width modulation mode Change an operation mode from event counter mode to pulse width m
326. e set to 0 input mode 2 Over flow or under flow Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CPSRF 0381h OXXXXXXXb Nothing is assigned When write set to 0 When read their contents are indeterminate Setting this bit to 1 initializes the Clock Prescaler Reset Flag prescaler for the timekeeping clock When read its content is 0 Figure 13 6 ONSF Register TRGSR Register and CPSRF Register Rev 2 00 Nov28 2005 page 118 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 1 1 Timer Mode In timer mode the timer counts a count source generated internally Table 13 1 lists specifications in timer mode Figure 13 7 shows TAiMR register in timer mode Table 13 1 Specifications in Timer Mode Item Specification Count Source f1 f2 f8 82 fC32 Count Operation Down count When the timer underflows it reloads the reload register contents and continues counting Divide Ratio 1 n 1 n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TAIIN Pin Function I O port or gate input TAiOUT Pin Function I O port or pulse
327. e the sub clock for the CPU clock set the CMO7 bit in the CMO register to 1 sub clock after the sub clock becomes oscillating stably During stop mode all clocks including the sub clock are turned off Refer to 8 4 Power Control Microcomputer Microcomputer Built in feedback resistor Built in feedback resistor XCIN External clock Oscillator LJ secl eee VSS XCOUT Open NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by each oscillator the oscillator manufacturer When the oscillation drive capacity is set to low check that oscillation is stable Also place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally Figure 8 10 Examples of Sub Clock Connection Circuit Rev 2 00 Nov 28 2005 page 65 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 1 3 On chip Oscillator Clock This clock approximately 1 MHz is supplied by a on chip oscillator This clock is used as the clock source for the CPU and peripheral function clocks In addition if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source this clock is used as the count source
328. e value recommended by each oscillator the oscillator manufacturer When the oscillation drive capacity is set to low check that oscillation is stable Also place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally Figure 8 9 Examples of Main Clock Connection Circuit Rev 2 00 Nov28 2005 page 64 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 1 2 Sub Clock The sub clock is generated by the sub clock oscillation circuit This clock is used as the clock source for the CPU clock as well as the timer A and timer B count sources In addition an fC clock with the same frequency as that of the sub clock can be output from the CLKOUT pin The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins The sub clock oscillator circuit contains a feedback resistor which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin Figure 8 10 shows the examples of sub clock connection circuit After reset the sub clock is turned off At this time the feedback resistor is disconnected from the oscilla tor circuit To us
329. ead while outputting a parity error signal the PER bit is set to 0 and at the same time the TXD2 output is returned high When transmitting a transmission finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit Therefore whether a parity signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission finished interrupt service routine Figure 15 34 shows the output timing of the parity error signal m LD LE LE LE LE LI LS LE LPL LPL Ly clock v RXD2 7 st Do Dt o2 s f p4 f ps y pe y v y ey sP TXD2 NOTE 1 RI bitin U2C1 register o o l This timing diagram applies to the case where the direct format is ST Start bit implemented P Even Parity NOTE SP Stop bit 1 The output of microcomputer is in the high impedance state pulled up externally Figure 15 34 Parity Error Signal Output Timing Rev 2 00 Nov28 2005 page 194 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 6 2 Format When direct format set the PRY bit in the U2MR register to 1 the UFORM bit in the U2CO register to 0 and the U2LCH bit in the U2C1 register to O When inverse format set the PRY bit to 0 UFORM bit to 1 and U2LCH bit to 1 Figure 15 35 shows the SIM i
330. ector Address SP Value 16 bit Bus without Wait 8 bit Bus without Wait 18 cycles 20 cycles 19 cycles 19 cycles 20 cycles Figure 10 6 Interrupt response time 10 5 6 Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL When a software interrupt or special interrupt request is accepted one of the interrupt priority levels listed in Table 10 5 is set in the IPL Table 10 5 shows the IPL values of software and special interrupts when they are accepted Table 10 5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted Interrupt Sources Value that is Set to IPL Oscillation Stop and Re oscillation Detection Watchdog Timer NMI 7 Software Address Match DBC Single Step Not changed Rev 2 00 Nov28 2005 page 90 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 5 7 Saving Registers In the interrupt sequence the FLG register and PC are saved to the stack At this time the 4 high order bits of the PC and the 4 high order IPL and 8 low order bits in the FLG register 16 bits in total are saved to the stack first Next the 16 low order bits of the PC are saved Figure 10 7 shows the stack status before and after an interrupt request is accepted T
331. ed 19 Table 4 1 SFR Information 1 Value of After Reset in PMO is revised CSR Register is added to 0008h CSE Register is added to 001Bh NOTES 1 3 and 4 are added Table 4 16 SFR Information 16 e Value of After Reset in PUR1 is revised NOTE 1 is added 35 to 37 5 Reset Layout is changed 36 Figure 5 2 Reset Sequence is revised 36 Table 5 1 Pin Status When RESET Pin Level is L is revised C 2 REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Date Summary 5 2 Software Reset 5 3 Watchdog Timer Reset 5 4 Oscillation Stop Detection Reset Last sentence Processor mode remains is added to each section 5 5 Internal Space is added 6 1 Types Processor Mode is added Table 6 1 Features of Processor Modes is added 6 2 Setting Processor Modes is added Table 6 2 Processor Mode After Hardware Reset and Table 6 3 PMO1 to PMOO Bits Set Values and Processor Modes are added 40 Figure 6 1 PMO Register is revised 41 Figure 6 2 PM1 Register is revised 43 44 Figures 6 4 to 6 7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode 1 to 4 are added 45 to 55 7 Bus is added 56 Table 8 1 Clock Generating Circuit Specifications NOTE 1 is added 63 Figure 8 8 PLCO Register NOTE 4 is added 64 Figure 8 9 Examples of Main Clock Connection Circuit is revised 65 Figure 8 10 Examples of Sub Clock Connection Circuit is revised 66 8 1 4 PLL Clock 9th line The senten
332. ed e Function for setting an SOUTI initial value set function When the SMi6 bit in the SiC register 0 external clock the SOUTi pin output level while not transmitting can be selected e CLK polarity selection Whether transmit data is output input timing at the rising edge or falling edge of transfer clock can be selected i 3 to 6 5 and 6 are only in the 128 pin version NOTES 1 To set the SMi6 bit in the SiC register to 0 external clock follow the procedure described below e f the SMi4 bit in the SiC register 0 write transmit data to the SiTRR register while input on the CLKi pin is high The same applies when rewriting the SMi7 bit in the SiC register e If the SMi4 bit 1 write transmit data to the SITRR register while input on the CLKi pin is low The same applies when rewriting the SMi7 bit Because shift operation continues as long as the transfer clock is supplied to the SI Oi circuit stop the transfer clock after supplying eight pulses If the SMi6 bit 1 internal clock the transfer clock automatically stops 2 Unlike UARTO to UART2 SI Oi is not separated between the transfer register and buffer Therefore do not write the next transmit data to the SITRR register during transmission When the SMi6 bit 1 internal clock SOUTi retains the last data for a 1 2 transfer clock period after completion of transfer and thereafter goes to a high impedance state However if transmit
333. ed by users Rev 2 00 Nov28 2005 page 19 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 2 SFR Information 2 Symbol CANO 1 Wake up Interrupt Control Register CO1WKIC XXXXX000b CANO Successful Reception Interrupt Control Register CORECIC XXXXX000b CANO Successful Transmission Interrupt Control Register COTRMIC XXXXXO000b INTS Interrupt Control Register INTSIC XX00X000b Timer B5 Interrupt Control Register TBSIC SI O5 Interrupt Control Register S5IC XXXXX000b Timer B4 Interrupt Control Register TB4IC UART1 Bus Collision Detection Interrupt Control Register U1BCNIC XXXXX000b Timer B3 Interrupt Control Register TB3IC UARTO Bus Collision Detection Interrupt Control Register UOBCNIC EAR OOO CAN1 Successful Reception Interrupt Control Register C1RECIC SI OA Interrupt Control Register S4IC XX00X000b INT5 Interrupt Control Register INTSIC CAN1 Successful Transmission Interrupt Control Register C1TRMIC SI O3 Interrupt Control Register S3IC XX00X000b INT4 Interrupt Control Register INT4IC UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b DMAO Inte
334. efer to 4 Special Function Register SFR for details Processor mode remains unchanged since the PMO1 to PMOO bits in the PMO register are not reset 5 5 Internal Space Figure 5 3 shows CPU register status after reset Refer to 4 Special Function Register SFR for SFR states after reset Data Register RO Data Register R1 Data Register R2 Data Register R3 Address Register A0 Address Register A1 Frame Base Register FB b19 bO 00000h Interrupt Table Register INTB Content of addresses FFFFEh to FFFFCh Program Counter PC b15 bO User Stack Pointer USP Interrupt Stack Pointer ISP Static Base Register SB Flag Register FLG Figure 5 3 CPU Register Status After Reset Rev 2 00 Nov 28 2005 page 37 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode 6 Processor Mode Note 6 Processor Mode explains as an example of a Normal ver T V ver is available single chip mode only Not available memory expansion mode and microprocessor mode 6 1 Types of Processor Mode Three processor modes are available to choose from single chip mode memory expansion mode and microprocessor mode Not available memory expansion and microprocessor modes in T V ver Table 6 1 shows the features of these processor modes Table 6 1 Features of Processor Modes Access Space Pins W
335. eferenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 63 Timer B Input Counter Input in Event Counter Mode Standard Min Max Parameter TBiIN Input Cycle Time counted on one edge TBilN Input HIGH Pulse Width counted on one edge TBilN Input LOW Pulse Width counted on one edge TBilN Input Cycle Time counted on both edges TBilN Input HIGH Pulse Width counted on both edges TBilN Input LOW Pulse Width counted on both edges Table 22 64 Timer B Input Pulse Period Measurement Mode Standard Min Max Parameter TBilN Input Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 65 Timer B Input Pulse Width Measurement Mode Standard Min Max Parameter TBilN Input Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 66 A D Trigger Input Standard Min Max tc aD ADTRG Input Cycle Time trigger able minimum 1000 tw ADL ADTRG Input LOW Pulse Width 125 Table 22 67 Serial Interface Symbol Parameter Standard Min Max Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time pe 22 68 External Interrupt INTi Input t Symbol oo Prae Eee Unit oo Prae Eee Unit anan Unit
336. egister COTWKIC CANO Successful Reception Interrupt Control Register CORECIC CANO Successful Transmission Interrupt Control Register COTRMIC INT3 Interrupt Control Register Proce ESOT Mads Register B Timer B5 Interrupt Control Register Processor Mode Register 1 SI O5 Interrupt Control Register System Clock Control Register 0 Timer B4 Interrupt Control Register System Clock Control Register 1 UART1 Bus Collision Detection Interrupt Control Register U1 BCNIC Chip Select Control Register Timer B3 Interrupt Control Register Address Match Interrupt Enable Register TO Bus Collision Detection Interrupt Control Regi Protect Register CAN Successful Reception Interrupt Control Register C1 RECIC SI OA Interrupt Control Register INT5 Interrupt Control Register CAN1 Successful Transmission Interrupt Control Register C1 TRMIC SI O8 Interrupt Control Register Watchdog Timer Start Register INT4 Interrupt Control Register Watchdog Timer Control Register UART2 Bus Collision Detection Interrupt Control Register UPBCNIC DMAO Interrupt Control Register Address Match Interrupt Register 0 DMA1 Interrupt Control Register 0012h CANO 1 Error Interrupt Control Register CO1ERRIC A D Conversion Interrupt Control Register ADIC Key Input Interrupt Control Register UART2 Transmit Interrupt Control Register S2TIC Address Match Interrupt Register 1 UART2 Receive Interrupt Control Register S2RIC UARTO Transmit Interrupt Control Registe
337. egister are set to 0 after reset However the contents in these bits are indeterminate when read 2 The blank areas are reserved and cannot be accessed by users Rev 2 00 Nov 28 2005 page 33 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 16 SFR Information 16 Symbol an A D Register 0 A D Register 1 A D Register 2 A D Register 3 A D Register 4 A D Register 5 A D Register 6 O3CEh A D Register 7 A D Control Register 2 ADCON2 00h A D Control Register 0 ADCONO 00000XXXb A D Control Register 1 ADCON1 00h D A Register 0 DAO 00h D A Register 1 00h D A Control Register 00h Port P14 Control Register 1 XX00XXXXb Pull Up Control Register 3 1 00h Port PO Register XXh Port P1 Register XXh Port PO Direction Register 00h Port P1 Direction Register 00h Port P2 Register XXh Port P3 Register XXh Port P2 Direction Register 00h Port P3 Direction Register 00h Port P4 Register XXh Port P5 Register XXh Port P4 Direction Register 00h Port P5 Direction Register 00h Port P6 Register XXh Port P7 Register XXh Port P6 Direction Register 00h Port P7 Direction Register 00h Port P8 Register
338. egister to 1 write enabled 2 If the INV11 bit in the INVC1 register is 0 three phase mode 0 or the INVOG bit in the INVCO register is 1 Sawtooth wave modulation mode set this bit to 0 timer B2 underflow 3 Related pins are U P8 O TA4OUT U P8_1 TA4IN V P7 2 CLK2 TA1OUT V P7 S CTS2 RTS2 TA1IN W P7 4 TA2OUT W P7 5 TA2IN If a low level signal is applied to the NMI pin when the IVPCR1 bit 1 the target pins go to a high impedance state regardless of which functions of those pins are being used After forced interrupt cutoff input H to the NMI pin and set the IVPCR1 bit to 0 this forced cutoff will be reset Figure 14 6 ICTB2 Register and TB2SC Register Rev 2 00 Nov 28 2005 page 144 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Trigger Select Register b7 b6 b5 b4 b3 b2 bi bO 1 Set the corresponding 2 Overflow or underflow Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address m TRGSR 0383h sbo Btname Fusion R TA1TGL TA1TGL Timer A1 Event Trigger Set to 01b TB2 underflow before R Ww TA1TGH Select Bit using a V phase output control circuit TA2TGL Timer A2 Event Trigger Set to 01b TB2 underflow before Ww TA2TGH TA2TGH Select Bit using a W phase output control circuit b5
339. el signal or open P3 0to P3 7 Input port P3 Input H or L level signal or open P4_0 to P4 7 Input port P4 Input H or L level signal or open P5 0 CE input Input H level signal P5 1 to P5 4 P5 6 P5 7 Input port P5 Input H or L level signal or open P5_5 EPM input Input L level signal P6_0 to P6_3 Input port P6 Input H or L level signal or open P6 A RTS1 BUSY output Standard serial I O mode 1 BUSY signal output pin Standard serial I O mode 2 Monitors the boot program operation check signal output pin P6 5 CLK1 SCLK input Standard serial I O mode 1 Serial clock input pin Standard serial I O mode 2 Input L P6 6 RXD1 RXD input Serial data input pin P6 7 TXD1 TXD output Serial data output pin P7 0to P7 7 Input port P7 Input H or L level signal or open P8 0 to P8 3 P8 6 P8 7 Input port P8 Input H or L level signal or open P8 4 P8 4 input Input L level signal P8_5 NMI NMI input Connect this pin to VCC1 P9_0 to P9_4 P9_7 Input port P9 Input H or L level signal or open P9 5 CRXO CRX input Input H or L level signal or connect to a CAN transceiver P9 6 CTXO CTX output Input H level signal open or connect to a CAN transceiver P10_0 to P10 7 Input por
340. elect 8 1 Sawtooth wave modulation mode 9 Transfer trigger is generated when the INVO7 Software Trigger Select bit is set to 1 Trigger to the dead time timer Bit is also generated when setting the INVO6 bit to 1 Its value is 0 when read 1 Set the INVCO register after the PRC1 bit in the PRCR register is set to 1 write enable Rewrite the INVOO to INVO2 and INVO6 bits when the timers A1 A2 A4 and B2 stop 2 The INVOO and INVO1 bits are enabled only when the INV11 bit is set to 1 three phase mode 1 The ICTB2 counter is incremented by one every time the timer B2 underflows regardless of INVOO and INVO1 bit settings when the INV11 bit is set to 0 three phase mode 0 When setting the INVO1 bit to 1 set the timer A1 count start flag before the first timer B2 underflow When the INVOO bit is set to 1 the first interrupt is generated when the timer B2 underflows n 1 times if n is the value set in the ICTB2 counter Subsequent interrupts are generated every n times the timer B2 underflows 3 Set the INVO1 bit to 1 after setting the ICTB2 register 4 Set the INVO2 bit to 1 to operate the dead time timer U V and W phase output control circuits and ICTB2 counter 5 When the INVOS bit is set to 1 the pins applied to U V W output three phase PWM The U U V V W and W pins including pins shared with other output functions are all placed in high impedance states when the following conditions are all m
341. elopment and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 3 1 FMROO Bit This bit indicates the flash memory operating status It is set to 0 while the program block erase erase all unlocked block lock bit program or read lock bit status command is being executed otherwise it is set to 1 21 3 3 2 FMRO1 Bit The microcomputer can accept commands when the FMR01 bit is set to 1 CPU rewrite mode Set the FMROS5 bit to 1 user ROM area access as well if in boot mode 21 3 3 3 FMRO2 Bit The lock bit is disabled by setting the FMRO2 bit to 1 lock bit disabled Refer to 21 3 6 Data Protect Function The lock bit is enabled by setting the FMRO2 bit to 0 lock bit enabled The FMRO2 bit does not change the lock bit status but disables the lock bit function If the block erase or erase all unlocked block command is executed when the FMRO2 bit is set to 1 the lock bit status changes 0 locked to 1 unlocked after command execution is completed 21 3 3 4 FMSTP Bit This bit resets the flash memory control circuits and minimizes power consumption in the flash memory Access to the flash memory is disabled when the FMSTP bit is set to 1 Set the FMSTP bit by program in a space other than the flash memory Set the FMSTP bit to 1 if one of the followings occurs A flash memory access error occurs while erasing or programming in EW
342. ence voltage input VREF Applies the reference voltage for the A D converter and D A converter A D converter ANO to AN7 ANO 0 to ANO 7 AN2 0 to AN2 7 Analog input pins for the A D converter ADTRG This is an A D trigger input pin ANEXO This is the extended analog input pin for the A D converter and is the output in external op amp connection mode ANEX1 This is the extended analog input pin for the A D converter D A converter DAO DA1 These are the output pins for the D A converter CAN module I Input O NOTES CRXO0 CRX1 These are the input pins for the CAN module CTXO CTX1 Output These are the output pins for the CAN module I O Input Output 1 Ask the oscillator maker the oscillation characteristic 2 INT6 to INT8 CLK5 CLK6 SIN5 SIN6 SOUT5 SOUTE6 are only in the 128 pin version 3 Not available the bus control pins in T V ver Rev 2 00 Nov28 2005 page 14 of 378 REJO9BO0124 0200 31 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 11 Pin Description 100 pin and 128 pin Versions 3 Signal Name Pin Name PO 0 to PO 7 P1 OtoP1 7 P2 0to P2 7 P3 0 to P3 7 P4 Oto PA 7 P5_0 to P5 7 P6_0 to P6 7 P7_0 to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 Oto P9 7 P10_0 to P10 7 P11_0 to P1t_7 P12_0 to P12 7 P13_0 to P13 7
343. ent and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit CANO 1 Clock Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset CCLKR 025Fh 00h Bit Symbol Function b2 b1 bO CCLKO 000 No division 00 1 Divide by 2 010 Divide by 4 CCLK1 CANO Clock Select Bits 2 0 1 1 Divide by 8 1 Divide by 16 1 1 1 11 0 0 ot 10 p not set a value 132 CCLK2 CCLK3 CANO CPU Interface 0 CANO CPU interface operating Sleep Bit 3 1 CANO CPU interface in sleep b6 b5 b4 CCLK4 000 No division 00 1 Divide by 2 0 1 0 Divide by 4 CCLK5 CAN 1 Clock Select Bits 2 O 1 1 Divide by 8 100 Divide by 16 1 01 CCLK6 110 p not set a value 111 CCLK7 CAN1 CPU Interface 0 CAN1 CPU interface operating Sleep Bit 3 1 CAN1 CPU interface in sleep 1 Write to this register after setting the PRCO bit in the PRCR register to 1 Write enabled 2 Set only when the Reset bit in the CiCTLR register i 0 1 1 Reset Initialization mode 3 Before setting this bit to 1 set the Sleep bit in the CiCTLR register to 1 Sleep mode enabled Figure 8 6 CCLKR Register Processor Mode Register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset eolo o PM2 001Eh XXX00000b Bit Symbol Bit Name Function i Specifying Wait when 0 2 waits je PM20 Accessing SFR at PLL 1 1 wait Operation 2 b1 Reserved Bit Set to 0 0 CPU cloc
344. ent is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 Flash Memory Version Aside from the built in flash memory the flash memory version microcomputer has the same functions as the masked ROM version In the flash memory version the flash memory can perform in four rewrite mode CPU rewrite mode standard serial I O mode parallel I O mode and CAN I O mode Table 21 1 lists the specifications of the flash memory version See Tables 1 1 and 1 2 Performance outline for the items not listed in Table 21 1 Table 21 2 shows the outline of flash memory rewrite mode Table 21 1 Flash Memory Version Specifications Flash Memory Operating Mode 4 modes CPU rewrite standard serial I O parallel I O CAN I O Erase Block User ROM Area See Figure 21 1 Flash Memory Block Diagram 1 block 4 Kbytes In units of word in units of byte Collective erase block erase Program and erase controlled by software command Lock bit protects each block 8 commands 100 times Parallel I O standard serial I O and CAN I O modes are supported Boot ROM Area Program Method Erase Method Program and Erase Control Method Protect Method Number of Commands Program and Erase Endurance ROM Code Protection NOTES 1 The boot ROM area contains a standard serial I O mode and CAN I O mode rewrite control program which is stored in it when shipped from the factory Th
345. enters stop mode or before the interrupt routine for returning from stop mode Program example when entering stop mode Program Example FSET l BSET CM10 Enter stop mode JMP B L2 Insert JMP B instruction L2 NOP More than 4 NOP instructions NOP NOP NOP Wait for main clock oscillation stabilization time before switching the clock source for CPU clock to the main clock Similarly wait until the sub clock oscillates stably before switching the clock source for CPU clock to the Sub clock Rev 2 00 Nov28 2005 page 342 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution Suggestions to reduce power consumption Ports The processor retains the state of each I O port even when it goes to wait mode or to stop mode A current flows in active I O ports A pass current flows in input ports that high impedance state When entering wait mode or stop mode set non used ports to input and stabilize the potential A D converter When A D conversion is not performed set the VCUT bit in the ADCON1 register to 0 VREF not connection When A D conversion is performed start the A D conversion at least 1 us or longer after setting the VCUT bit to 1 VREF connection D A converter When not performing D A conversion set the DAiE bit i 0 1 in the DACON register to 0 input disabled and
346. er Standard Min Max TAIIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width TAiIN Input Cycle Time Parameter Standard Min Max TAiIN Input HIGH Pulse Width TAIIN Input LOW Pulse Width TAiIN Input Cycle Time Parameter Standard Min Max TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Table 22 60 Timer A Input External Trigger Input in Pulse Width Modulation Mode Symbol Parameter Standard Min Max 100 tw TAH TAiIN Input HIGH Pulse Width tw TAL TAiIN Input LOW Pulse Width Table 22 61 Timer A Input Counter Increment decrement Input in Event Counter Mode te uP TAiOUT Input Cycle Time Parameter 100 Standard Min Max tw uPH TAiOUT Input HIGH Pulse Width tw uPL TAiOUT Input LOW Pulse Width tsu UP TIN TAiOUT Input Setup Time th TIN UP TAiOUT Input Hold Time Table 22 62 Timer A Input Two phase Pulse Input in Event Counter Mode tetta TAiIN Input Cycle Time Parameter Standard Min Max tsuctain Taout TAIOUT Input Setup Time tsurAoUT TAIN TAIN Input Setup Time Rev 2 00 Nov28 2005 page 335 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Timing Requirements VCC 25V R
347. er only 8 4 1 3 Medium speed Mode The main clock divided by 2 4 8 or 16 provides the CPU clock If the sub clock is activated fC32 can be used as the count source for timers A and B 8 4 1 4 Low speed Mode The sub clock provides the CPU clock The main clock is used as the clock source for the peripheral function clock when the CM21 bit in the CM2 register is set to 0 on chip oscillator turned off and the on chip oscillator clock is used when the CM21 bit is set to 1 on chip oscillator oscillating The fC32 clock can be used as the count source for timers A and B 8 4 1 5 Low Power Dissipation Mode In this mode the main clock is turned off after being placed in low speed mode The sub clock provides the CPU clock The fC32 clock can be used as the count source for timers A and B Simultaneously when this mode is selected the CMO6 bit in the CMO register becomes 1 divide by 8 mode In the low power dissipation mode do not change the CMO6 bit Consequently the medium speed divide by 8 mode is to be selected when the main clock is operated next Rev 2 00 Nov28 2005 page 69 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 4 1 6 On chip Oscillator Mode The on chip oscillator clock divided by 1 undivided 2 4 8 or 16 provides the CPU clock The on chip oscillator clock is
348. er transmission does not start as long as RspLock bit remains 1 thus no automatic response Response transmission starts when the RspLock bit is set to O TrmReq RecReq Remote RspLock RemActive RspLock Bits in CIMCTLj register i 0 1 j O to 15 When configuring a slot as a reception slot note the following points 1 Before configuring a slot as a reception slot be sure to set the CIMCTLj register to 00h 2 A received message is stored in a slot that matches the condition first according to the result of reception mode configuration and acceptance filtering operation Upon deciding in which slot to store the smaller the number of the slot is the higher priority it has 8 In normal CAN operation mode when a CAN module transmits a message of which ID matches the CAN module never receives the transmitted data In loop back mode however the CAN module receives back the transmitted data In this case the module does not return ACK When configuring a slot as a transmission slot note the following points 1 Before configuring a slot as a transmission slot be sure to set the CIMCTLj registers to 00h 2 Set the TrmReq bit in the CiMCTLj register to 0 not transmission slot before rewriting a transmission slot 3 A transmission slot should not be rewritten when the TrmActive bit in the CIMCTLj register is 1 transmitting If it is rewritten an indeterminate data will be transmitte
349. er reset When the TBiS bit 1 start counting the MR3 bit is set to 0 no overflow by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to 1 overflow The MR3 bit cannot be set to 1 ina program The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Figure 13 20 TBOMR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode Rev 2 00 Nov28 2005 page 136 of 378 REJ09B0124 0200 131 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Count source Measurement pulse s Transfer Transfer indeterminate value P measured value Timing at which counter reaches 0000h q TBiS bit o IR bit in mt TBilC register g Set to 0 upon accepting an interrupt request or by writing in program MR3 bit in E TBiMR register ag The TBOS to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to bit 5 to bit 7 in the TBSR register iz0to5 NOTES 1 Counter is initialized at completion of measurement 2 Timer has overflown 3 This timing diagram is for the case where the MR1 to MPO bits in the TBiMR register are 00b measure the interval from falling edge to falling edge of the measurement pulse Figure 13 21
350. eration timing when measur ing a pulse width Table 13 8 Specifications in Pulse Period and Pulse Width Measurement Mode Count Source f1 f2 f8 f32 fC32 Count Operation Up count Counter value is transferred to reload register at an effective edge of measurement pulse The counter value is set to 0000h to continue counting Count Start Condition Set the TBiS bit to 1 start counting Count Stop Condition Set the TBiS bit to 0 stop counting Interrupt Request Generation Timing e When an effective edge of measurement pulse is input e Timer overflow When an overflow occurs the MR3 bit in the TBIMR register is set to 1 overflow simultaneously The MR3 bit is set to 0 no overflow by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to 1 At this time make sure the TBiS bit is set to 1 start counting TBilN Pin Function Measurement pulse input Read from Timer Contents of the reload register measurement result can be read by reading TBi register Write to Timer Value written to the TBi register is written to neither reload register nor counter i Oto5 NOTES 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register 2 Interrupt request is not generated when the first effective edge is input after the timer started c
351. erface DMAO DMA1 request UART1 DMAO only UARTI transmit NACK interrupt request DMAO UARTO UART2 UARTi receive ACK interrupt request DMA1 request Start stop condition detection interrupt request This diagram applies to the case where the SMD2 to SMDO bits in the UiMR register 010b and the IICM bit in the UiSMR register 1 i Oto2 IICM Bit in UiSMR register IICM2 SWC ALS SWC2 SDHI Bits in UiSMR2 register STSPSEL ACKD ACKC Bits in UiSMR4 register NOTE 1 If the IICM bit 1 the pins can be read even when the PD6 2 PD6 6 or PD7 1 bit 1 output mode Figure 15 23 I C Mode Block Diagram Rev 2 00 Nov28 2005 page 176 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 15 11 Registers to Be Used and Settings in IPC Mode Register Bit 0 to 7 Set transmission data 15 Serial Interface 0 to 7 Reception data can be read 8 ACK or NACK is set in this bit ABT Arbitration lost detection flag Invalid OER Overrun error flag UiBRG 0 to 7 Set a transfer rate Invalid UiMR 1 SMD2 to SMDO Set to 010b CKDIR Set to 0 Set to 1 IOPOL Set to 0 CLK1 CLKO Select the count source for the UiBRG register Invalid CRS Invalid because the CRD bit 1 TXEPT
352. errupts can be executed by executing the INT instruction In software interrupt Nos 0 to 31 the U flag is saved to the stack during instruction execution and is set to 0 ISP selected before executing an interrupt sequence The U flag is restored from the stack when returning from the interrupt routine In software interrupt Nos 32 to 63 the U flag does not change state during instruction execution and the SP then selected is used Rev 2 00 Nov28 2005 page 82 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 3 Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral function interrupts 10 3 1 Special Interrupts Special interrupts are non maskable interrupts 10 3 1 1 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low For details refer to 10 7 NMI Interrupt 10 3 1 2 DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development tools 10 3 1 3 Watchdog Timer Interrupt Generated by the watchdog timer Once a watchdog timer interrupt is generated be sure to initialize the watchdog timer For details about the watchdog timer refer to 11 Watchdog Timer 10 3 1 4 Oscillation Stop and Re oscillation Detection Interrupt Generated by the oscillation stop and
353. ersion when the PM10 bit is set to 1 OF000h to OFFFFh block A can be used as internal ROM area 3 Not available memory expansion and microprocessor modes in T V ver Figure 6 6 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode 3 lll When PM13 1 and PM10 1 Memory expansion mode Microprocessor mode SFR SFR Internal RAM Internal RAM Reserved Reserved area 1 area 1 Reserved area External area External area Memory expansion mode 320 Kbytes Microprocessor mode 832 Kbytes Internal ROM Capacity Capacity 16 Kbytes 043FFh 192 Kbytes 20 Kbytes 053FFh 256 Kbytes 31 Kbytes 384 Kbytes A0000h NOTES 1 For the flash memory version when the PM10 bit is set to 1 OF000h to OFFFFh block A can be used as internal ROM area 2 Not available memory expansion and microprocessor modes in T V ver Figure 6 7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode 4 Rev 2 00 Nov28 2005 page 44 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 7 Bus explains as an example of a Normal ver Not available the bus control pins in T V ver During memory expansion or microprocessor mode some pins serve as the bus control pins to perform data input output to and from external devices These bus control pins include AO to A19 DO to D15
354. es of INTO pin 0111b Timer BO Timer B3 1000b Timer B1 Timer B4 1001b Timer B2 Timer B5 1010b UARTO transmit 1011b UARTO receive 1100b UART2 transmit 1101b UART2 receive 1110b A D conversion 1111b UART1 transmit Figure 12 2 DMOSL Register Rev 2 00 Nov28 2005 page 105 of 378 REJO9BO0124 0200 34 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC DMA1 Request Cause Select Register b7 b6 b5 b4 b3 b2 bi bO Symbol DM1SL Address After Reset O3BAh 00h DSELO DSEL1 DSEL2 DSEL3 b5 b4 DMA Request Cause Select Bit See NOTE 1 Nothing is assigned When write set to 0 When read their contents are 0 A DMA request is generated by setting this bit to 1 when the DMS bit is 0 basic cause and the DSEL3 to DSELO bits are 0001b software trigger The value of this bit when read is O Software DMA Request Bit 1 The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSELS to DSELO bits in the manner described below DMS 0 basic cause of request DMS 1 extended cause of request DSEL3 to DSELO Bits 0000b Falling edge of INT1 pin 0001b Software trigger 0010b Timer AO 0011b Timer A1 0100b Timer A2 0101b Timer A3 SI 03
355. et The INVO2 bit is set to 1 three phase control timer function e The INVOS bit to 0 three phase control timer output disabled Direction registers of each port are set to 0 input mode 6 The INVO3 bit is set to 0 when the following conditions are all met Reset A concurrent active state occurs while INVO4 bit is set to 1 The INVOS bit is set to 0 by program Asignal applied to the NMI pin changes H to L When both the INVO4 and INVOS bits are set to 1 the INVOS3 bit is set to 0 7 The INVOS bit cannot be set to 1 by program Set the INV04 bit to 0 as well when setting the INVOS bit to 0 8 The following table describes how the INVO6 bit works INVO6 0 INVOG 1 Mode Triangular wave modulation mode Sawtooth wave modulation mode Timing to Transfer from the IDBO Transferred once by generating a Transferred every time a transfer trigger and IDB1 Registers to Three transfer trigger after setting the IDBO is generated Phase Output Shift Register and IDB1 registers Timing to Trigger the Dead Time On the falling edge of a one shot pulse By a transfer trigger or the falling edge of Timer when the INV16 Bit 0 of the timer A1 A2 or A4 a one shot pulse of the timer A1 A2 or A4 INV13 Bit Enabled when the INV11 bit 1 and the Disabled INVO6 bit 0 Transfer trigger Timer B2 underflows and write to the INVO7 bit or write to the TB2 register when INV10 1 9 When the INVOG bit is set to 1 se
356. etup of PMO5 to PM04 and area to access See Table 7 6 Pin Functions for Each Processor Mode for details Rev 2 00 Nov28 2005 page 45 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 7 2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait 7 2 1 Address Bus Table 7 2 PM06 and PM11 Bits Set Value and Address Bus Width The address bus consists of 20 lines AO to A19 Tm The address bus width can be chosen to be 12 Set Value Pin Function Address Bus Width 16 or 20 bits by using the PMO6 bit in the PMO P3 4 to P3 7 12 bits register and the PM11 bit in the PM1 register P4_0 to P4 3 Table 7 2 shows the PMO6 and PM11 bits set A12 to A15 16 bits values and address bus widths P4 Oto P4 3 When processor mode is changed from single chip A12 to A15 20 bits mode to memory expansion mode the address A16 to A19 bus is indeterminate until any external areais NOTE accessed 1 No values other than those shown above can be set 7 2 2 Data Bus When input on the BYTE pin is high data bus is an 8 bit width 8 lines DO to D7 comprise the data bus when input on the BYTE pin is low data bus is a 16 bit width 16 lines DO to D15 comprise the data bus Do not change the input level on the BYTE p
357. f BCLK OPS 2 Calculated according to the BCLK frequency as follows n 0 5 x 10 40 ns Measuring Standard condition in Max Figure 22 12 NOTE 1 4 NOTE 2 NOTE 1 n is 1 for 1 wait setting 2 for 2 wait setting and 3 for 3 wait setting f BCLK When n 1 f BCLK is 12 5 MHz or less 3 This standard value shows the timing when the output is off and does not show hold time of data bus Hold time of data bus varies with capacitor volume and pull up pull down resistance value Hold time of data bus is expressed in t CR X In 1 Vo Voc by a circuit of the right figure For example when Vor 0 2 Vcc C 30 pF R 1 kQ hold time of output L level is t 30 pF X 1 KQ X In 1 0 2 Vcc Vcc 6 7 ns 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Switching Characteristics VCC 3 3V Referenced to VCC 3 3V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 45 Memory Expansion Mode and Microprocessor Mode for 2 to 3 wait setting external area access and multiplexed bus selection Measuring Standard Parameter is ta cLk ap Address output delay time Figure 22 12 tnBcLK AD Address output hold time refers
358. ferred to counter when reloaded next k i 1 exceptk Oifi 4 Rev 2 00 Nov 28 2005 page 127 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi HEARANN TAOMR IO TAAMR 0396h 10 039Ah 00h EN Bit Symbol por or TMODO Operation Mode b1 bo TMOD1 Select Bit PWM mode 0 Pulse is not output Pulse Output Function TAiOUT pin is a normal port pin Select Bit 3 Pulse is output TAiOUT pin is a pulse output pin EN Trigger Select 0 Falling edge of input signal to TAiIN pin 2 Bit 1 1 Rising edge of input signal to TAiIN pin 2 0 Write 1 to TAIS bit in the TABSR register Trigger Select Bit 1 Selected by TAITGH to TAITGL bits 16 8 Bit PWM Mode x Functions as a 16 bit pulse width modulator Select Bit Functions as an 8 bit pulse width modulator D HARER b7 b6 00 f1 or f2 Count Source Select Bit O 1 f8 10 f32 11 fC32 D ABRE 1 Effective when the TAITGH and TAiTGL bits in the ONSF or TRGSR register are 00b TAiIN pin input 2 The port direction bit for the TAiIN pin is set to 0 input mode 3 Set to 1 pulse is output PWM pulse is output Figure 13 12 TAOMR to TA4MR Registers in Pulse Width Modulation Mode Rev 2 00 Nov28 2005 page 128 of 378 RENESAS REJ09B0124 0200 Under development This docume
359. formance Outline of M16C 6N Group 128 pin Version M16C 6NM Interrupt Internal interrupt source is revised from 32 sources to 34 sources Table 21 2 Recommended Operating Conditions 1 e loutpea y Unit is revised from V to mA Table 21 3 Recommended Operating Conditions 2 e NOTE 3 VCC 3 0 0 3 V is revised to VCC 3 3 0 3 V 22 9 1 2 Timer A Event Counter Mode is revised Jul 01 2005 Revised edition issued The contents of product are revised T V ver is added Revised parts and revised contents are as follows except for expressional change Table 1 1 Performance outline of M16C 6N Group 100 pin Version M16C 6NM Performance outline of T V ver is added Table 1 2 Performance outline of M16C 6N Group 128 pin Version M16C 6NN Performance outline of T V ver is added Table 1 3 Product List is revised T V ver is added Figure 1 2 Type No Memory Size and Package Characteristics is added Flgure 4 1 SFR Information 1 The value of After Reset in CM2 Register is revised Figure 4 7 SFR Information 7 NOTE 1 is revised Figure 7 4 CM2 Register The value of After Reset is revised Figure 7 13 State Transition in Normal Operation Mode NOTE 7 is revised 9 10 Address Match Interrupt After of 13th line Note that when using the external bus in 8 bit width no address match interrupts can be used for external areas is deleted Figure 14 37 upper SiC Register NOTE 4 is revised
360. ge LOWPOWER With no load applied Hysteresis HOLD RDY TAOIN to TAIN TBOIN to TBSIN INTO to INT5 NMI ADTRG CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 CLKO to CLK3 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD2 SIN3 Hysteresis RESET Hysteresis XIN HIGH Input PO Oto PO 7 P1 OtoP1 7 P2 OtoP2 7 Current P3 Oto P3 7 P4 OtoP4 7 P5 OtoP5 7 P6 Oto P6 7 P7_0 to P7 7 P8 OtoPS8 7 P9 Oto P9 7 P10 O to P10 7 P11 Oto P11 7 P12 Oto P12 7 P193 0 to P13_7 P14 O0 P14 1 XIN RESET CNVSS BYTE LOW Input PO 0to PO 7 P1_0 to P1_7 P2 OtoP2 7 Current P3 Oto P3 7 P4 Oto P4 7 P5 OtoP5 7 P6 Oto P6 7 P7_0 to P7 7 P8 OtoPS8 7 P9 Oto P9 7 P10 O to P10 7 P11 Oto P11 7 P12 Oto P12 7 P13 0 to P13 7 P14 O0 P14 1 XIN RESET CNVSS BYTE Pull up PO Oto PO 7 P1_0 to P1_7 P2 OtoP2 7 Resistance P3 Oto P3 7 P4 Oto P4 7 P5 OtoP5 7 P6 Oto P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10 7 P11_0 to P11 7 P12_0 to P12 7 P13 O to P13 7 P14 0 P14 1 Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage 1 Referenced to VCC 3 0 to 3 6V VSS OV at Topr 40 to 85 C f BCLK 24MHz unless otherwise specified 2 P11 to P14 INT6 to INT8 CLK5 CLK6 SIN5 and SING are only in the 128 pin version Rev 2 00 Nov28 2005 page 313 of 378 RENE
361. h 2 O2DAh CAN1 Message Box 7 Data Field 02DBh 02DCh 02DDh O2DEh m O2DFh CAN1 Message Box 7 Time Stamp 02E0h 02E1h 02E2h m O2E3h CAN1 Message Box 8 Identifier DLC 02E4h O2E5h 02E6h 02E7h 02E8h n CAN1 Message Box 8 Data Field O2EBh O2ECh O2EDh O2EEh E O2EFh CAN1 Message Box 8 Time Stamp O2F1h O2F2h B O2F3h CAN1 Message Box 9 Identifier DLC 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h O2FAh CAN1 Message Box 9 Data Field O2FBh O2FCh O2FDh O2FEh xm O2FFh CAN1 Message Box 9 Time Stamp X Undefined Address O2COh O2Cih O2C2h O2C3h Sees O2C7h O2C8h O2Coh o2CAn o2CBh O2CCh 02D1h O2D3h oane O2D7h o2D8h_ o2Doh _02DAh o2DBh Km 02Eth_ o2E2n 02E3h_ O2E4n O2E7h O2E8h o2Eon o2EBh o2ECh o2Fth 02F2h_ 02F3h_ roar o2F7h 02F8h_ o2ron 02FAn_ O2FBh Km o2FFh Rev 2 00 Nov 28 2005 page 30 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 13 SFR Information 13
362. h the rewrite control program is stored 21 3 4 8 DMA Transfer In EW1 mode do not perform a DMA transfer while the FMROO bit in the FMRO register is set to 0 auto programming or auto erasing Rev 2 00 Nov 28 2005 page 271 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 4 9 Writing Command and Data Write commands and data to even addresses in the user ROM area 21 3 4 10 Wait Mode When entering wait mode set the FMRO 1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 21 3 4 11 Stop Mode When the microcomputer enters stop mode execute the instruction which sets the CM10 bit to 1 stop mode after setting the FMRO 1 bit to 0 CPU rewrite mode disabled and disabling the DMA transfer 21 3 4 12 Low Power Dissipation Mode and On chip Oscillator Low Power Dissipation Mode If the CMO5 bit is set to 1 main clock stopped do not execute the following commands Program Block erase Erase all unlocked blocks Lock bit program Read lock bit status Rev 2 00 Nov28 2005 page 272 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 5 Software Commands Software commands are descr
363. he count source for each timer acts as a clock to control such timer operations as counting reloading etc Figures 13 1 and 13 2 show block diagrams of Timer A and Timer B configuration respectively Main clock PLL clock On chip fH oscillator clock f1 or f2 f8 f32 fC32 TCK1 to TCKO 00 Fi hols ils Noise M pee an 4 Clock prescaler XcINCO 1 32 Set the CPSR bit in the CPSRF register to 1 prescaler reset TMOD 1 to TMODO 00 Timer mode 10 R 10 One shot timer mode 11 Pulse width measuring mode p filter TCK1 to TCKO 00 Q 01 O 10 Oise o 00 01 Event counter mode Q 11 TAOTGH to TAOTGL TMOD1 to TMODO 00 Timer mode 11 10 One shot timer mode 11 Pulse width measuring mode Noise filter TCK1 to TCKO 00 01 10 LE JN eo on o 00 o 01 Event counter mode 11 TA1TGH t0 TA1TGL TMOD1 to TMODO 00 Timer mode O Oo lo 10 One shot timer mode 11 Pulse width measuring mode Noise 0 TCK1 to TCKO 2 Oo filter 10 Ad O a 99 o 00 01 Event counter mode O 11 TA2TGH to TA2TGL Reset Timer AO interrupt Timer A1 interrupt Timer A2 interrupt TMOD1 to TMODO 00 Timer mode lo PCLKO Bit in PCLKR register
364. he other necessary registers must be saved in a program at the beginning of the interrupt routine Use the PUSHM instruction and all registers except SP can be saved with a single instruction SP New SP value Content of previous stack SP Content of previous stack SP value before Content of previous stack interrupt request Content of previous stack ae c cur MENNUNME P Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged PCL 8 low order bit of PC PCM 8 middle order bits of PC PCH 4 high order bits of PC FLGL 8 low order bits of FLG FLGH 4 high order bits of FLG Figure 10 7 Stack Status Before and After Acceptance of Interrupt Request The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request is even or odd If the SP Note is even the FLG register and the PC are saved 16 bits at a time If odd they are saved in two steps 8 bits at a time Figure 10 8 shows the operation of the saving registers NOTE 1 When any INT instruction in software numbers 32 to 63 has been executed this is the SP indicated by the U flag Otherwise it is the ISP 1 SP contains even number 2 SP contains odd number Address Sequence in which order Address Sequence in which order registers are saved registers are saved 2 Saved simultaneously all 16 bits Saved 8 bits ata time
365. hich are Assigned I O Ports Single chip Mode SFR internal RAM internal ROM All pins are I O ports or peripheral function I O pins Memory Expansion Mode SFR internal RAM internal ROM Some pins serve as bus control pins external area Microprocessor Mode SFR internal RAM external area Some pins serve as bus control pins NOTES 1 Refer to 7 Bus 2 Not available in T V ver Rev 2 00 Nov28 2005 page 38 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode 6 2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PMO1 to PMOO bits in the PMO register Table 6 2 shows the processor mode after hardware reset Table 6 3 shows the PMO1 to PMOO bits set values and processor modes Table 6 2 Processor Mode After Hardware Reset CNVSS Pin Input Leve VSS Single chip mode NOTES 1 If the microcomputer is reset in hardware by applying VCC to the CNVSS pin the internal ROM cannot be accessed regardless of PMO1 to PMOO bits 2 The multiplexed bus cannot be assigned to the entire cs space 3 Not available in T V ver Do not set a value Table 6 3 PMO1 to PMOO Bits Set Values and Processor Modes Single chip mode Memory expansion mode Do not set a value Microprocessor mode NOTE 1 Not available in T V ver Do not set a value
366. hold time refers to BCLK LK ALE ALE signal output delay time LK ALE ALE signal output hold time LK RD RD signal output delay time LK RD RD signal output hold time LK WR WR signal output delay time LK wWR WR signal output hold time Lk DB Data output delay time refers to BCLK Data output hold time refers to BCLK 4 Data output delay time refers to WR NOTE 2 Data output hold time refers to WR NOTE 1 taecik ioa HLDA output delay time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 f BCLK Parameter 10 ns 2 Calculated according to the BCLK frequency as follows 0 5 x 10 BCLK is 12 5 MH less BCLK 40 ns f BCLK is 12 5 MHz or less 3 This standard value shows the timing when the output is off and does not show hold time of data bus Hold time of data bus varies with capacitor volume and pull up pull down resistance value Hold time of data bus is expressed in tzZ CR X In 1 Vo Voc by a circuit of the right figure For example when Vo 0 2 Vcc C 30 pF R 1 KQ hold time of output L level is t 2 30 pF X 1 KQ X In 1 0 2 Vcc Vcc 6 7 ns NOTE 1 P11 to P14 are only in the 128 pin version Figure 22 12 Port PO to P14 Measurement Circuit Rev 2 00 Nov28 2005 page 317 of 378 RENESAS REJ09B0124
367. i o th BCLK ALE i ve gt i 25ns max Es i 4ns min ta BCLI WR a gt lt 1 25ns max i Ons min 1 1 i td BCLK DB i gt 40ns max gt th BCLK CS gt 4ns min th BCLK AD hpi 4ns min p Ons min th BCLK Cs gt 4ns min A i h BCLK AD nir 4ns min th wR AD 1 0 5 X tcyc 10 ns min th BCLK wR Ih BCLK DB rg td DB wR 0 5 X tcyc 40 ns min Vit 0 8 V Vin 2 0 V e Output timing voltage VoL 0 4 V Vou 2 4 V Figure 22 7 Timing Diagram 4 Rev 2 00 Nov28 2005 page 308 of 378 REJO9BO0124 0200 131 NESAS th WR DB 0 5 X tcyc 10 ns min This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Under development 22 Electric Characteristics Normal ver wait setting and external area access For 2 o E o z t o a 0 o o o A a o t 2 D G o E c 2 0 c G Q x ui 2 A fo E o z Read timing td BCLK ALE tsu DB RD 4 gt th RD DB Ons min 40ns min Write timing 0 5 X tcyc 10 ns min 0 5 X tcyc 10 ns min 1 5 X tcyc 40 ns min Measuring conditions Vit 2 0 8 V ViH 2 0 V e Output timing voltage Vo 0 4 V Vou 2 4 V e Input timing voltage Figure 22 8 Timing Diagram 5 134 NESAS Rev 2 00 Nov28 2005 page 309 of 378 REJ09B0124 0200 This d
368. i i i i i ta AD ALE AXE ta DB WR 0 5 X tcyc 40 ns min i i 1 th wR DB i i 2 5 X BE 50 ns min i i i i i 1 0 5 X teyc 10 ns min td BCLK AD th BCLK AD pe max 1 4ns min i i i i i i aoe am no multiplex rom dd ALE MEAE th WR AD e K ta ap wr 1 0 5X toye 10 ns min 1 f f f 1 i 1 f i f i 1 i i i i gt lt Ons min i i 1 ip 1 D 1 1 f i f i f i f i f i f f T f i f i i 1 i th BCLK WR fd BCLK WR 1 1 1 i i 1 1 i 1 4ons max b 4 i D pou ERRE EEEE EARS iiisgy toye BCLK Measuring conditions e VCC 3 3V e Input timing voltage ViL 0 6 V V H 2 7 V e Output timing voltage VoL 1 65 V Vou 1 65 V Figure 22 20 Timing Diagram 8 Rev 2 00 Nov 28 2005 page 327 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver 22 2 Electrical Characteristics T V ver Table 22 46 Absolute Maximum Ratings Parameter iti Rated Value Supply Voltage VCC1 VCC2 0 3 to 6 5 Analog Supply Voltage 0 3 to 6 5 Input RESET CNVSS BYTE 0 3 to VCC 0 3 Voltage PO Oto PO 7 P1 Oto P1 7 P2_0 to P2 7 P3 Oto P3 7 P4 Oto P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2toP7 7 P8 OtoP8 7 P9 0 P9 2to P9 7 P10_0
369. i RTSi CTS Input CRD bit in UiCO register 0 P6 0 P6 4 P7 3 CRS bit in UiCO register 0 PD6_0 and PD6_4 bits in PD6 register 0 PD7_3 bit in PD7 register 0 RTS Output CRD bit 0 CRS bit 1 I O Port CRD bit 1 i Oto2 Table 15 8 P6_4 Pin Functions Bit set Value Pin Function U1CO Register UCON Register PD6 Register CRD bit CRS bit RCSP bit CLKMD1 bit PD6_4 bit Input 0 Output 1 CTSO 0 or 1 NOTE 1 In addition to this set the CRD bit in the UOCO register to 0 CTSO RTSO enabled and the CRS bit in the UOCO register to 1 RTSO selected Rev 2 00 Nov 28 2005 page 169 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 1 Example of Transmit Timing when Transfer Data is 8 bit Long parity enabled one stop bit The transfer clock stops momentarily as CTSi is H when the stop bit is checked The transfer clock starts as the transfer starts immediately CTSi changes to L TC je r Transfer clock TE bit in UiC1 register Write data to the UiTB register TI bit in qi o UiC1 register Transferred from UiTB register to UARTi transmit register CTSi f Stopped pulsing Start Parity Stop because the TE bit i bit bit bit 0i TXDi stDqXD1XD2XD3XD4XD5XDEXD7X P SP
370. ial Function Register SFR RM 19 SA a MET E E A E 35 Del Rardiwaro RO Okorn EEUU 35 5 1 1 Reset on a Stable Supply Voltage ccceseceeesceeeseceeeeneeeeeaeeeeeneeeeeeeeseaaneeseaaeseseaeeseaeeeseaeeesseeensaaees 35 51 2 docs 35 5 2 S0ftWare RESE b udr 37 5 3 Watchdog Timer R SCt ccccecsecceeeeseeeceeeeeeneeeeeeeneaeeeeeeeaaeeeeeeesaaeeeeeeaaeaaeeeesgaeeeeseesaaesessessaesessesseneeeesensags 37 5 4 Oscillation Stop Detection Reset ssssssssssessssesesesee eene a nennt nen nrn Raae entres entree nnns 37 5 5 Int nmnal Space mL eo haat a RT eA eee 37 6 Processor NOU MET c I 38 Gil Types Of ProCeSSOr oro M 38 6 2 Setting Processor Modes ssssssssssssssssseeeeeeeeee nennen enne nn rnns rents en tns rennes ets nennen een ns nennen nns 39 n Y E eYe eo om 45 FeRNEUIM em HW 45 rex SOP arate BUS ss ccagevviiesdawssyave a a 45 7 1 2 Multiplexed sc 45 7 2 BUS CONTO RT DET E 46 Tat Address BIS eremi iu Stic exem ig ruf teta rusa tis aevi tec dete m MENU ARM SEE LEE LL EE 46 roudaicHp c 46 72 3 Chip Select Signal coetu a tn esce enses Puto eeu rug op xe suu ta pa Rud XR SS aka Rx E
371. ibed below The command code and data must be read and written in 16 bit unit to and from even addresses in the user ROM area When writing command code the high order 8 bits D15 to D8 are ignored Table 21 4 lists the software commands Table 21 4 Software Commands Read Array First Bus Cycle Second Bus Cycle Software Command Data Data Mode Address D15 to DO Mode Address D15 to DO Read Status Register Clear Status Register Program Block Erase Erase All Unlocked Block Lock Bit Program Read Lock Bit Status SR D data in SRD register D7 to DO WA Address to be written The address specified in the first bus cycle is the same even address as the address specified in the second bus cycle WD 16 bit write data BA x XX Highest order block address must be an even address Any even address in the user ROM area High order 8 bits of command code ignored NOTE 1 It is only blocks 0 to 12 that can be erased by the erase all unlocked block command Block A cannot be erased The block erase command must be used to erase the block A 21 3 5 1 Read Array Command FFh The read array command reads the flash memory By writing command code xxFFh in the first bus cycle read array mode is entered Content of a specified address can be read in 16 bit unit after the next bus cycle The microcomputer remains in read array mode until another command is writ
372. ic Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode VCC 3 3V Effective for setting with wait BCLK RD Separate bus WR WRL WRH Separate bus RD Multiplexed bus WR WRL WRH Multiplexed bus RDY input tsu RDY BCLK 2 th BCLK RDY Common to setting with wait and setting without wait tsu HOLD BCLK th BCLK HOLD HOLD input HLDA output PO P1 P2 P3 P4 Di P5_0 to P5 200 7 gt lt td BCLK HLDA gt lt NOTE 1 The above pins are set to high impedance regardless of the input level of the BYTE pin the PMO6 bit in the PMO register and the PM11 bit in the PM1 register Measuring conditions e VCC 3 3V e Input timing voltage Determined with Vit 0 6 V Viu 2 7 V e Output timing voltage Determined with Vor 1 65 V Vou 1 65 V Figure 22 14 Timing Diagram 2 Rev 2 00 Nov 28 2005 page 321 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode VCC z 3 3V For setting with no wait Read timing 1 ta BcLk cs th BCLK cs lt gt 30ns max lt gt 4ns min 1 nee 1 th BCLK AD i 4ns min i i 1 tat fa BCLK ALE fhBcL ALE P i lt th RD AD i gt gt 30ns max gt i 4ns mi
373. icated dead time timer Figure 14 9 shows the example of triangular modulation waveform and Figure 14 10 shows the example of sawtooth modulation waveform Triangular waveform as a Carrier Wave TB2S bit in TABSR register Timer B2 Timer A1 reload control signal 1 Timer A4 start trigger signal 1 TA4 register 2 TA4 1 register 2 Reload register 2 C mM X m X m X n XnXprX p X T q Timer A4 m m m in NES a a one shot pulse i LI L p sev ip t i i i Rewrite the IDBO and IDB1 registers signal U phase output signal L active _ U phase INV14 1 H active _ U phase INVOO INVO1 Bits in the INVCO register INV11 INV14 Bits in the INVC1 register NOTES 1 Internal signals See Figure 14 1 Three Phase Motor Control Timer Functions Block Diagram 2 Applies only when the INV11 bit is set to 1 three phase mode The above applies to INVCO 00XX11XXb and INVC1 010XXXXOb X varies depending on each system Examples of PWM output change are a When INV11 1 three phase mode 1 b When INV11 0 three phase mode 0 INVO1 0 and ICTB2 2h The timer B2 interrupt is INVO1 0 ICTB2 1h The timer B2 interrupt is generated generated with every second timer B2 underflow or whenever the timer B2 underflows INVO1 1 INVOO 1 and ICTB2 1h The timer B2 interrupt is Default value of the timer TA4 m generated on the falling edge of the timer A reload control The
374. icrocomputer remains in read status register mode until the read array command or read lock bit status command is written Also execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated Write the command code xx20h Write xxDOh to the highest order block address Full status check 9 Block erase operation is completed NOTES 1 Write the command code and data to even addresses 2 Refer to Figure 21 12 Full Status Check and Handling Procedure for Each Error 3 Execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated Figure 21 9 Block Erase Command Rev 2 00 Nov28 2005 page 275 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 5 6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A By writing xxA7h in the first bus cycle and xxDOh in the second bus cycle an auto erase erase and verify operation will run continuously in all blocks except the block A The FMROO bit in the FMRO register indicates whether an auto erase operation has been completed After the completion of an auto erase operation the FMRO7 bit in the FMRO register indic
375. ied in the second bus cycle 23 19 8 Operation Speed Before entering CPU rewrite mode EWO or EW1 mode set the CM11 bit in the CM1 register to 0 main clock select 10 MHz or less for CPU clock using the CMO6 bit in the CMO register and CM17 to CM16 bits in the CM1 register Also set the PM17 bit in the PM1 register to 1 with wait state Rev 2 00 Nov28 2005 page 371 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 19 9 Prohibited Instructions The following instructions cannot be used in EWO mode because the CPU tries to read data in flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 23 19 10 Interrupt EWO Mode To use interrupts having vectors in a relocatable vector table the vectors must be relocated to the RAM area e The NMI and watchdog timer interrupts are available since the FMRO and FMR1 registers are forcibly reset when either interrupt request is generated Allocate the jump addresses for each interrupt service routines to the fixed vector table Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt request is generated Execute the rewrite program again after exiting the interrupt routine The address match interrupt is not available since the CPU tries to read data in the flash memory EW1 Mode
376. ils about watchdog timer reset When the main clock on chip oscillator clock or PLL clock is selected for CPU clock the divide by n value for the prescaler can be selected to be 16 or 128 If a sub clock is selected for CPU clock the divide by n value for the prescaler is always 2 no matter how the WDC7 bit is set The period of watchdog timer can be calculated as given below The period of watchdog timer is however subject to an error due to the prescaler With main clock on chip oscillator clock or PLL clock selected for CPU clock Prescaler dividing 16 or 128 X Watchdog timer count 32768 Watchdog timer period 2 9 CPU clock With sub clock selected for CPU clock Prescaler dividing 2 X Watchdog timer count 32768 Watch ti iod atchdog timer perio CPU clock For example when CPU clock 16 MHz and the divide by n value for the prescaler 16 the watchdog timer period is approx 32 8 ms The watchdog timer is initialized by writing to the WDTS register The prescaler is initialized after reset Note that the watchdog timer and the prescaler both are inactive after reset so that the watchdog timer is activated to start counting by writing to the WDTS register In stop mode wait mode and hold state the watchdog timer and prescaler are stopped Counting is resumed from the held value when the modes or state are released Figure 11 1 shows the block diagram of the wat
377. ime f rippte Power Supply Ripple Allowable Frequency VCC V P P ripple Power Supply Ripple Allowable Amplitude Voltage VCC 5V VCC 3V Veciavat Power Supply Ripple Rising Falling Gradient VCC 5V VCC 3V NOTES 1 Referenced to VCC 3 0 to 5 5V at Topr 40 to 85 C unless otherwise specified 2 Relationship between main clock oscillation frequency and supply voltage is shown right 3 Execute program erase of flash memory by VCC 3 3 0 3 V or VCC 5 0 0 5V 4 When using 16MHz and over use PLL clock PLL clock oscillation frequency which can be used is 16MHz 20MHz or 24MHz Main clock input oscillation frequency Mask ROM version Flash memory version no wait 16 0 aggneeneenas ms 3 0 5 5 VCC V main clock no division f XIN operating maximum frequency MHz firippie f ripple Power Supply Ripple Allowable Frequency VCC V P P ripple V V fol ag e Power S pply Ripple ligwabi CC Cw d aW P P ripple Amplitude Voltage Figure 22 1 Timing of Voltage Fluctuation Rev 2 00 Nov28 2005 page 294 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 4 Electrical Characteristics 1 VCC 5V Standard Min Typ Max Vcc 2 0 Vcc Pa
378. ime consists of the following four segments e Synchronization segment SS This serves for monitoring a falling edge for synchronization Propagation time segment PTS This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay on the CAN bus the input comparator delay and the output driver delay Phase buffer segment 1 PBS1 This serves for compensating the phase error When the falling edge of the bit falls later than expected the segment can become longer by the maximum of the value defined in SJW Phase buffer segment 2 PBS2 This segment has the same function as the phase buffer segment 1 When the falling edge of the bit falls earlier than expected the segment can become shorter by the maximum of the value defined in SJW Figure 19 15 shows the bit timing Bit time lt gt SJW SJW Sampling point The range of each segment Bit time 8 to 25Tq Configuration of PBS1 and PBS2 PBS1 gt PBS2 SS 1Tq PBS1 SJW PTS 1Tq to 8Tq PBS2 gt 2 when SJW 1 PBS1 2Tq to 8Tq PBS2 gt SJW when 2 lt SJW lt 4 PBS2 2Tq to 8Tq SJW 1Tq to 4Tq Figure 19 15 Bit Timing Rev 2 00 Nov28 2005 page 237 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 8 Bit rate Bit rate depends on f1 the division value of the CAN module system
379. in Rev 2 00 Nov28 2005 page 206 of 378 RENESAS REJ09B0124 0200 16 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 0 ee Symbol Address After Reset roi 25s 3 00000XXXxb Bt Symbol b2 b1 b0 000 ANO is selected 001 AN1 is selected AN2 is selected AN3 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected 2 3 MDO A D Operation Mode b4 b3 Mi usc Bi 0 0 0 One shot mode 3 H Software trigger tre Trigger Select Bit ADTRG trigger A D conversion disabled ADST A D Conversion Start Flag JUD conversion started Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to ANT Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 After rewriting the MD1 to MDO bits set the CH2 to CHO bits over again using another instruction A D Control Register 1 b7 b6 b5 b4 b3 b2 bi Symbol Address After Reset PIER le ADCON 1 03D7h 00h A D Sweep Pin Select Bit Invalid in one shot mode A D Operation Mode Set to 0 when one shot mode Select Bit 1 is selected Mh 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode
380. in while in operation 7 2 3 Chip Select Signal The chip select hereafter referred to as the CS signals are output from the CSi i 0 to 3 pins These pins can be chosen to function as I O ports or as CS by using the CSi bit in the CSR register Figure 7 1 shows the CSR register During 1 Mbyte mode the external area can be separated into up to 4 by the CSi signal which is output from the CSi pin Figure 7 2 shows the example of address bus and CSi signal output Chip Select Control Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CSR 0008h 00000001b t CS0 Output Enable Bit 0 Chip select output disabled CST Output Enable Bit functions as I O port RW L 1 Chip select output enabled CS2 CS2 Output Enable Bit j P RW CS3 CS3 Output Enable Bit CSOW CS0 Wait Bit 0 With wait state CS1W CS1 Wait Bit 1 Without wait state 1 2 3 CS2W CS2 Wait Bit RW CS3 Wait Bit Where the RDY signal is used in the area indicated by CSi i 0 to 3 or the multiplexed bus is used set the CSiW bit to 0 Wait state If the PM17 bit in the PM1 register is set to 1 with wait state set the CSiW bit to 0 with wait state When the CSiW bit 0 with wait state the number of wait states in terms of clock cycles can be selected using the CSEi1W to CSEiOW bits in the CSE register Not available this register in T V ver Figure 7 1 CSR Register Rev 2 00 Nov28 2005 page 46 of
381. ing 16 Ring 16 ae High Speed mode PLE operationmode On chip Oscillator On chip Oscillator CM07 1 3 CM07 0 2 4 Mode Low Power Dissipation Made Low Speed Mode Low Speed Mode CPU clock f XCIN CM07 0 CM05 1 1 8 Low Power Dissipation Mode CPU clock f XCIN CM07 0 CMO6 1 CM15 1 Sub clock oscillation CM04 CM05 CMO06 CMO7 Bits in CMO register CM11 CM15 CM16 CM17 Bits in CM1 register CM20 CM21 Bits in CM2 register PLCO7 Bit in PLCO register NOTES 1 Avoid making a transition when the CM20 bit is set to 1 oscillation stop re oscillation detection function enabled Set the CM20 bit to 0 oscillation stop re oscillation detection function disabled before transiting Wait for the main clock oscillation stabilization time Switch clock after oscillation of sub clock is sufficiently stable Change the CM17 and CM16 bits before changing the CMO6 bit Transit in accordance with arrow The PM20 bit in the PM2 register become effective when the PLCO7 bit is set to 1 PLL on Change the PM20 bit when the PLCO7 bit is set to 0 PLL off Set the PM20 bit to 0 2 waits when PLL clock gt 16 MHz PM20 bit to 0 SFR accessed with two wait states before setting the PLCO7 bit to 1 PLL operation Set the CMO6 bit to 1 divide by 8 mode before changing back the operation mode from on chip oscillator mode to high or middle spee
382. ing to remote frame Slot Select Bit RecR Reception Slot 0 Not reception slot eoned Request Bit 3 1 Reception slot Transmission 0 Not transmission slot TrmR Slot Request Bit 9 1 Transmission slot 1 As for write only writing O is possible The value of each bit is written when the CAN module enters the respective state 2 In Basic CAN mode slots 14 and 15 serve as data format identification flag The RemActive bit is set to 0 if the data frame is received and it is set to 1 if the remote frame is received 3 One slot cannot be defined as reception slot and transmission slot at the same time 4 This register can not be set in CAN reset initialization mode of the CAN module Figure 19 6 COMCTLj and C1MCTLj Registers Rev 2 00 Nov28 2005 page 228 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM CANi Control Register i 0 1 b7 b6 b5 b4 b3 Symbol COCTLR C1CTLR Address 0210h 0230h 19 CAN Module After Reset X0000001b X0000001b CAN Module Reset Reset Bit 1 0 Operation mode 1 Reset initialization mode Loop Back Mode 0 Loop back mode disabled LoopBack Select Bit 2 Message Order Select Bit 2 1 Loop back mode enabled 0 Word access 1 Byte access B CAN Basic CAN S 0 Basic CAN mode disabled asic Select Bit 2 1 Basic CAN mode enabled BusErrEn Bus
383. ing used to exit wait mode When exiting stop mode by the peripheral function interrupt the interrupt routine is performed when an interrupt request is generated and the CPU clock is supplied again When stop mode is exited by the peripheral function interrupt or NMI interrupt the CPU clock source is as follows in accordance with the CPU clock source setting before the microcomputer had entered stop mode When the sub clock is the CPU clock before entering stop mode Sub clock When the main clock is the CPU clock source before entering stop mode Main clock divided by 8 When the on chip oscillator clock is the CPU clock source before entering stop mode On chip oscillator clock divided by 8 Rev 2 00 Nov28 2005 page 74 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit Figure 8 12 shows the state transition from normal operation mode to stop mode and wait mode Figure 8 13 shows the state transition in normal operation mode Table 8 8 shows a state transition matrix describing allowed transition and setting The vertical line shows current state and horizontal line show state after transition All oscillators stopped Stop Mode Interrupt Stop Mode CM10 1 Interrupt CM07 0 CMO6 1 CMO5 0 CM11 0 CM10 1 3 CM10 1 6 Stop Mode Interrupt CM10 16 Stop Mode
384. input signal to TAiIN pin 2 i 0 TAIOS bit is enabled MR2 Trigger Select Bit 1 Selected by TAITGH to TAITGL bits MR3 Set to 0 in one shot timer mode b7 b6 TCKO 00 f1orf2 Count Source Select Bit 9 1 8 10 f32 RW RW RW RW RW RW Ww ISKI 11 fC32 1 Effective when the TAITGH and TAITGL bits in the ONSF or TRGSR register are 00b TAiIN pin input 2 The port direction bit for the TAiIN pin is set to 0 input mode Figure 13 11 TAiMR Register in One shot Timer Mode Rev 2 00 Nov28 2005 page 126 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 1 4 Pulse Width Modulation PWM Mode In pulse width modulation mode the timer outputs pulses of a given width in succession The counter functions as either 16 bit pulse width modulator or 8 bit pulse width modulator Table 13 5 lists specifications in pulse width modulation mode Figure 13 12 shows TAiMR register in pulse width modulation mode Figures 13 13 and 13 14 show examples of how a 16 bit pulse width modulator operates and how an 8 bit pulse width modulator operates respectively Table 13 5 Specifications in Pulse Width Modulation Mode Specification Count Source f1 f2 f8 f32 fC32 Count Operation e Down count operating as an 8 bit or a 16 bit pulse width modulator The timer reloads a new value at a
385. ins with an odd address the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address Similarly if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address 12 1 2 Effect of BYTE Pin Level During memory expansion and microprocessor modes if 16 bits of data are to be transferred on an 8 bit data bus input on the BYTE pin high the operation is accomplished by transferring 8 bits of data twice Therefore this operation requires two bus cycles to read data and two bus cycles to write data Furthermore if the DMAC is to access the internal area internal ROM internal RAM or SFR unlike in the case of the CPU the DMAC does it through the data bus width selected by the BYTE pin NOTE 1 Not available the bus control pins in T V ver 12 1 3 Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted the number of bus cycles required for that access increases by an amount equal to software wait states Figure 12 5 shows the example of the transfer cycles for a source read For convenience the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown In reality the destination write cycle is
386. ion bit for CSi i 1 to 3 to 0 input mode and the CSi bit in the CSR register to 0 chip select disabled BHE ALE HLDA XOUT 9 Open BCLK 9 HOLD RDY NMI P8 5 Connect via resistor to VCC pull up AVCC Connect to VCC AVSS VREF Connect to VSS NOTES 1 When setting the port for output mode and leave it open be aware that the port remains in input mode until it is switched to output mode in a program after reset For this reason the voltage level on the pin becomes indeterminate causing the power supply current to increase while the port remains in input mode Furthermore by considering a possibility that the contents of the direction registers could be changed by noise or noise induced runaway it is recommended that the contents of the direction registers be periodically reset in software for the increased reliability of the program 2 Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins within 2 cm 3 If the CNVSS pin has the VSS level applied to it these pins are set for input ports until the processor mode is switched over in a program after reset For this reason the voltage levels on these pins become indeterminate causing the power supply current to increase while they remain set for input ports 4 When the ports P7_1 and P9_1 are set for output mode make sure a low level signal is output from the pins The ports P7_1 and P9_1 are N channel open drain out
387. ip Select Control Register 00000001b Address Match Interrupt Enable Register XXXXXX00b Protect Register XX000000b Oscillation Stop Detection Register 2 0X000000b Watchdog Timer Start Register XXh Watchdog Timer Control Register OOXXXXXXb Address Match Interrupt Register 0 00h 00h XOh Address Match Interrupt Register 1 00h 00h XOh Chip Select Expansion Control Register 4 00h PLL Control Register 0 0001X010b Processor Mode Register 2 XXX00000b DMAO Source Pointer XXh XXh XXh DMAO Destination Pointer XXh XXh XXh DMAO Transfer Counter XXh DMAO Control Register DMOCON 00000X00b DMA1 Source Pointer DMA1 Destination Pointer DMA1 Transfer Counter DMA1 Control Register DM1CON 00000X00b X Undefined NOTES 1 The PMOO and PM01 bits in the PMO register do not change at software reset watchdog timer reset and oscillation stop detection reset Effective when memory expansion and microprocessor modes Normal ver 2 The CM20 CM21 and CM27 bits in the CM2 register do not change at oscillation stop detection reset 3 CNVSS pin H is not available in T V ver Do not set a value 4 These registers are not available in T V ver 5 The blank areas are reserved and cannot be access
388. is 1 oscillation stop re oscillation detection function enabled the system is placed in the following state if the main clock comes to a halt Oscillation stop re oscillation detection interrupt request is generated The on chip oscillator starts oscillation and the on chip oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock CM21 bit 1 on chip oscillator clock is the clock source for CPU clock e CM22 bit 1 main clock stop detected CM23 bit 1 main clock stopped Where the PLL clock corresponds to the CPU clock source and the CM20 bit is 1 the system is placed in the following state if the main clock comes to a halt Since the CM21 bit remains unchanged set it to 1 on chip oscillator clock inside the interrupt routine Oscillation stop re oscillation detection interrupt request is generated CM22 bit 1 main clock stop detected CM23 bit 1 main clock stopped e CM21 bit remains unchanged Where the CM20 bit is 1 the system is placed in the following state if the main clock re oscillates from the stop condition Oscillation stop re oscillation detection interrupt request is generated CM22 bit 1 main clock re oscillation detected e CM23 bit 0 main clock oscillation CM21 bit remains unchanged Rev 2 00 Nov28 2005 page 78 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and
389. is area can only be rewritten in parallel I O mode 2 Can be programmed in byte units in only parallel I O mode 3 Definition of program and erase endurance The programming and erasure times are defined to be per block erasure times For example assume a case where a 4K byte block A is programmed in 2 048 operations by writing one word at a time and erased thereafter In this case the block is reckoned as having been programmed and erased once If a product is 100 times of programming and erasure each block in it can be erased up to 100 times 3 Table 21 2 Flash Memory Rewrite Modes Overview Flash M Beanie Wade CPU Rewrite Mode Standard Serial I O Mode Parallel I O Mode CAN I O Mode Function The user ROM area is rewritten when the CPU executes software commands EWO mode Rewrite in areas other than flash memory EW1 mode Can be rewritten in the flash memory The user ROM area is rewritten using a dedicated serial programmer Standard serial I O mode 1 Clock synchronous serial I O Standard serial I O mode 2 UART The boot ROM and user ROM areas are rewritten using a dedicated parallel programmer The user ROM area is rewritten busing a dedicated CAN programmer Areas which can be Rewritten User ROM area User ROM area User ROM area Boot ROM area User ROM area Operation Mode Single chip mode Memory expansion mode EWO mode Boot mode EWO mo
390. is completed a bus arbitration is returned to the CPU When the CPU has completed one bus access a DMA1 transfer starts After one DMAt transfer is completed the bus arbitration is again returned to the CPU In addition DMA requests cannot be counted up since each channel has one DMAS bit Therefore when DMA requests as DMA1 in Figure 12 6 occurs more than one time the DMAS bit is set to 0 as soon as getting the bus arbitration The bus arbitration is returned to the CPU when one transfer is completed Refer to 7 2 7 HOLD Signal for details about bus arbitration between the CPU and DMA Normal ver only An example where DMA requests for external causes are detected active at the same time a DMA transfer is executed in the shortest cycle BCLK DMAO Ro M UL Bus arbitration cu ZZ ili GL INTO DMAO request bit INT1 DMA1 request bit Figure 12 6 DMA Transfer by External Factors Rev 2 00 Nov28 2005 page 112 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 Timers Eleven 16 bit timers each capable of operating independently of the others can be classified by function as either timer A five and timer B six T
391. is document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 1 EWO Mode The microcomputer enters CPU rewrite mode by setting the FMRO 1 bit in the FMRO register to 1 CPU rewrite mode enabled and is ready to accept commands EWO mode is selected by setting the FMR11 bit in the FMR1 register to 0 To set the FMRO bit to 1 set to 1 after first writing 0 The software commands control programming and erasing The FMRO register or the status register indicates whether a program or erase operation is completed as expected or not 21 3 2 EW1 Mode EW1 mode is selected by setting FMR11 bit to 1 by writing 0 and then 1 in succession after setting the FMRO 1 bit to 1 by writing 0 and then 1 in succession Both bits must be set to 0 first before setting to 1 The FMRO register indicates whether or not a program or erase operation has been completed as expected The status register cannot be read in EW1 mode When an erase program operation is initiated the CPU halts all program execution until the operation is completed or erase suspend is requested Rev 2 00 Nov28 2005 page 265 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 3 3 FMRO FMR1 Registers Figure 21 4 shows FMRO and FMR1
392. isabled The INVO6 bit in the INVCO register determines start trigger of the DTT register Figure 14 4 IDBO and IDB1 Registers and DTT Register Rev 2 00 Nov28 2005 page 142 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Timer Ai Ai 1 Register i 1 2 4 0 9 0 b15 b8 b7 bo Symbol Address After Reset TA1 TA2 TA4 0389h 0388h 038Bh 038Ah 038Fh 038Eh Indeterminate TA11 TA21 TA41 7 01C3h 01C2h 01C5h 01C4h 01C7h 01C6h_ Indeterminate If setting value is n the timer stops when the nth count source is counted after a start trigger is generated Positive phase changes to negative phase and vice 0000 tO REREN wo versa when the timers A1 A2 and A4 stop 1 Use a 16 bit data for read and write 2 If the TAi or TAi1 register is set to 0000h no counters start and no timer Ai interrupt is generated 3 Use the MOV instruction to set the TAi and TAi1 registers 4 When the INV15 bit in the INVC1 register is set to 0 dead timer enabled phase switches from an inactive level to an active level when the dead time timer stops 5 When the INV11 bit in the INVC1 register is set to 0 three phase mode 0 the value of the TAi register is transferred to the reload register by a timer Ai start trigger When the INV11 bit is set to 1 three phas
393. ists the specifications of single sweep mode Figure 16 6 shows the ADCONO and ADCON1 registers in single sweep mode Table 16 4 Single Sweep Mode Specifications Function The SCAN1 to SCANO bits in the ADCON register and the ADGSEL1 to ADGSELO bits in the ADCON2 register select pins Analog voltage applied to this pins is converted one by one to a digital code A D Conversion e When the TRG bit in the ADCONO register is 0 software trigger Start Condition The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Completion of A D conversion If a software trigger is selected the ADST Stop Condition bit is set to 0 A D conversion halted Set the ADST bit to 0 Interrupt Request Completion of A D conversion Generation Timing Analog Input Pin Select from ANO to AN1 2 pins ANO to ANS 4 pins ANO to AN5 6 pins ANO to AN7 8 pins Reading of Result of Read one of the ADO to AD7 registers that corresponds to the selected pin A D Converter NOTE 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 2 00 Nov28 2005 page 210 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16
394. it 3 waits Do not set a value 1 wait CS1 Wait Expansion Bit 1 2 waits CSE11W CS20WE 3 waits Do not set a value 1 wait CS2 Wait Expansion Bit 1 2 waits CSE21W CSE30W 3 waits Do not set a value 1 wait CS3 Wait Expansion Bit 1 2 waits CSE31W 3 waits Do not set a value 1 Set the CSiW bit i 0 to 3 in the CSR register to 0 with wait state before writing to the CSEi1W to CSEIOW bits If the CSiW bit needs to be set to 1 without wait state set the CSEi1W to CSEiOW bits to 00b before setting it 2 Not available this register in T V ver Figure 7 6 CSE Register Rev 2 00 Nov28 2005 page 52 of 378 REJ09B0124 0200 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus Table 7 8 Software Wait Related Bits and Bus Cycles CSE Register i CS31W to CS30W Bits Area Bus Mode M2 Register PM1 Register CS21W to CS20W Bits Software Bus Cycle 6 PM20 Bit PM17 Bit i CS11W to CS10W Bits Wait CS01W to CS00W Bits 3 BCLK cycles 2 BCLK cycles No wait 1 BCLK cycle 1 wait 2 BCLK cycles External Separate No wait 1 BCLK cycle read 2 BCLK cycles write 1 wait 2 BCLK cycles 2 waits 3 BCLK cycles 3 waits 4 BCLK cycles 1 wait 2 BCLK cycles 1 wait 3 BCLK cycles 2 waits 3 BCLK cycles 3 waits 4 BCLK cycles 1
395. it Transfer BYTE L DMBIT 0 8 bits BYTE H This condition does not exist NOTE 1 Not available memory expansion and microprocessor modes in T V ver Table 12 3 Coefficient j k Internal Area External Area 9 Internal ROM RAM SFR Separate Bus Multiplexed Bus No Wait With Wait 1 Wait 2 Waits With Wait With Wait No Wait 1 Wait 2 Waits 3 Waits 1 Wait 2 Waits 3 Waits NOTES 1 Depends on the set value of the PM20 bit in the PM2 register 2 Depends on the set value of the CSE register 3 Not available external area in T V ver Rev 2 00 Nov28 2005 page 110 of 378 REJO9BO0124 0200 11 N ESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 DMAC 12 3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register i 0 1 to 1 enabled the DMAC operates as follows 1 Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is 1 forward or the DARi register value when the DAD bit in the DMiCON register is 1 forward 2 Reload the DMAi transfer counter with the DMAi transfer counter reload register value If the DMAE bit is set to 1 again while it remains set the DMAC performs the above operation However
396. it in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Set the ADST bit to 0 A D conversion halted Interrupt Request Generation Timing None generated Analog Input Pins to be Given Priority when A D Converted Select from ANO 1 pin ANO to AN1 2 pins ANO to AN2 3 pins ANO to AN3 4 pins Reading of Result of A D Converter NOTE Read one of the ADO to AD7 registers that corresponds to the selected pin 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 2 00 Nov28 2005 page 214 of 378 RENESAS REJ09B0124 0200 16 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi GD m XS Analog Input Pin Select Bit Invalid in repeat sweep mode 1 E mm ME 7 Mi Select Bit 0 Repeats sweep mode 1 EXAImNO 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi FT LL Symbol Address After Reset ADCON1 03D7h 00h Bit Symbol When repeat
397. ithout software wait Operation Mode Single chip memory expansion and microprocessor modes Single chip mode Address Space 1 Mbyte Memory Capacity See Table 1 3 Product List Peripheral Function Port Input Output 87 pins Input 1 pin Multifunction Timer Timer A 16 bits X 5 channels Timer B 16 bits X 6 channels Three phase motor control circuit Serial Interface 3 channels Clock synchronous UART I C bus IEBus 2 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits X 2 channels DMAC 2 channels CRC Calculation Circuit CRC CCITT CAN Module 2 channels with 2 0B specification Watchdog Timer 15 bits X 1 channel with prescaler Interrupt Internal 32 sources External 9 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequency synthesizer Equipped with a built in feedback resistor Oscillation Stop Detection Function Main clock oscillation stop and re oscillation detection function Electrical Characteristics Supply Voltage VCC 3 0 to 5 5V f BCLK 24MHz VCC 42 to 5 5V f BCLK 20MHz 1 1 prescaler without software wait 1 1 prescaler without software wait Power Mask ROM Consumption
398. ition Min Figure 22 3 Address output hold time refers to BCLK Max 4 Address output hold time refers to RD 0 Address output hold time refers to WR NOTE 1 Chip select output delay time Lk cs Chip select output hold time refers to BCLK LK ALE ALE signal output delay time LK ALE ALE signal output hold time LK RD RD signal output delay time LK RD RD signal output hold time LK WR WR signal output delay time Lk wR WR signal output hold time LK DB Data output delay time refers to BCLK Data output hold time refers to BCLK 4 Data output delay time refers to WR NOTE 2 Data output hold time refers to WR 9 NOTE 1 ta BCLK HLDA HLDA output delay time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 c cud Bcuk Vma 2 Calculated according to the BCLK frequency as follows Q 5X10 oms fBCLK is 12 5 MHz or less f BCLK 3 This standard value shows the timing when the output is off and does not show hold time of data bus Hold time of data bus varies with capacitor volume and pull up pull down resistance value Hold time of data bus is expressed in t CR X In 1 Vo Voc by a circuit of the right figure For example when Vo 0 2 Vcc C 30 pF R 21 KQ hold time of output L level is t 2
399. k frequency is determined by the equation below When the PLL clock frequency is 16 MHz or more set the PM20 bit in the PM2 register to 0 2 waits PLL clock frequency f XIN X multiplying factor set by the PLCO2 to PLCOO bits in the PLCO register However PLL clock frequency 16 MHz 20 MHz or 24 MHz NOTE 1 24 MHz is available Normal ver only The PLCO2 to PLCOO bits can be set only once after reset Table 8 2 shows the example for setting PLL clock frequencies Table 8 2 Example for Setting PLL Clock Frequencies XIN Multiply PLL Clock MHz PLCO2 PLCO1 PLCOO Factor MHz 8 4 10 5 NOTES 1 PLL clock frequency 16 MHz 20 MHz or 24 MHz 2 24 MHz is available Normal ver only 3 Multiply by 6 is available Normal ver only Rev 2 00 Nov28 2005 page 66 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit Using the PLL clock as the clock source for the CPU Set the CMO7 bit to 0 main clock the CM17 to CM16 bits to 00b main clock undivided and the CMO6 bit to 0 CM16 and CM17 bits enabled 1 Set the PLCO2 to PLCOO bits multiplying factor o NMNEMEMEMMENM When PLL clock 16 MHz Set the PM20 bit to 0 2 wait state Set the PLCO7 bit to 1 PLL operation o Wait until the PL
400. k is used for the WDT Count Source watchdog timer count source Protective Bit 3 4 1 On chip oscillator clock is used for the watchdog timer count source b4 b3 Reserved Bit Set to 0 Nothing is assigned When write set to 0 b7 b5 When read their contents are indeterminate 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable 2 The PM20 bit become effective when the PLCO7 bit in the PLCO register is set to 1 PLL on Change the PM20 bit when the PLCO7 bit is set to 0 PLL off Set the PM20 bit t 0 2 waits when PLL clock gt 16MHz 3 Once this bit is set to 1 it cannot be set to 0 in a program 4 Setting the PM22 bit to 1 results in the following conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer count source The CM10 bit in the CM1 register is disabled against write Writing a 1 has no effect nor is stop mode entered The watchdog timer does not stop when in wait mode or hold state Figure 8 7 PM2 Register Rev 2 00 Nov28 2005 page 62 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit PLL Control Register 0 b7 b6 b5 b4 b3 b2 bi bi Jopo hX TI Symbol Address After Reset ZN PLCO 001Ch 0001X010b b2 b1 bO Do not set a value RW
401. l Interrupt Pin Timer Pin UART Pin CAN Module Pin 1 Overview Bus Control Pin co Oo O1 AJ oO Pp TA4IN U TA4OUT U SIN4 TASIN TA30UT TA2IN W SOUTA TA20UT W CLK4 TA1IN V CTS2 RTS2 TA10UT V CLK2 TAOIN TBSIN RXD2 SCL2 TAOOUT TXD2 SDA2 TXD1 SDA1 RXD1 SCL1 CLK1 CTS1 RTS1 CTSO CLKS1 TXDO SDAO RXDO SCLO CLKO CTSO RTSO NOTE 1 Not available the bus control pins except CLKOUT pin Pin No 50 in T V ver Rev 2 00 Nov 28 2005 page 10 of 378 REJ09B0124 0200 RENESAS RDY CLKOUT Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 7 Pin Characteristics for 128 Pin Package 2 Control Interrupt Timer Pin UART Pin CAN Module Bus Control Pin Pin Pin Pin AO DO D15 D14 D13 D12 D11 NOTE 1 Not available the bus control pins in T V ver Rev 2 00 Nov28 2005 page 11 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change
402. l Register 1 b7 b6 b5 b4 b3 b2 bi bO LL LIele e e omo ooiooooop Bit Symbol RW All e Stop Control 0 Clock on ome 1 All clocks off stop mode RW CM11 System Clock Select Bit 1 4 Main clock y 1 PLL clock 6 CM15 XIN XOUT ae Capacity 0 LOW ew Bit 6 1 HIGH No division mode ewe ein Clock Division Divide by 2 mode Select Bit 1 7 Divide by 4 mode Divide by 16 mode 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 If the CM10 bit is 1 stop mode XOUT goes H and the internal feedback resistor is disconnected The XCIN and XCOUT pins are placed in the high impedance state When the CM11 bit is set to 1 PLL clock or the CM20 bit in the CM2 register is set to 1 oscillation stop re oscillation detection function enabled do not set the CM10 bit to 1 When the PM22 bit in the PM2 register is set to 1 watchdog timer count source is on chip oscillator clock writing to the CM10 bit has no effect Effective when the CMO7 bit is 0 and the CM21 bit is O After setting the PLCO7 bit in the PLCO register to 1 PLL operation wait until tsu PLL elapses before setting the CM11 bit to 1 PLL clock When entering stop mode from high or medium speed mode or when the CMO5 bit is set to 1 main clock turned off in low speed mode the CM15 bit is set to 1 drive capability high Effective when the CMO6 bit is 0 CM16 an
403. lation Rev 2 00 Nov28 2005 page 222 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 CAN Module The CAN Controller Area Network module for the M16C 6N Group M16C 6NK M16C 6NM of microcomputers is a communication controller implementing the CAN 2 0B protocol The M16C 6N Group M16C 6NK M16C 6NM contains two CAN modules which can transmit and receive messages in both standard 11 bit ID and extended 29 bit ID formats Figure 19 1 shows a block diagram of the CAN module External CAN bus driver and receiver are required Data Bus CiCONR Register CiCTLR Register CilDR Register CiMCTLj Register CiLMBR Register Cd i NEED x Message Box slots 0 to 15 Protocol yp Y N Controller Acceptance Filter 1 slots 0 to 15 Message ID 16 Bit Timer DLC Message Data Time Stamp CANO 1 Error Int i Y i CANI Successful Reception Int CiTECR Register CiSTR Register CiSSTR Register CilCR Register CANi Successful Transmission Int Data Bus CANO 1 Wake Up Int Figure 19 1 CAN Module Block Diagram CTX CRX CAN I O pins Protocol controller This controller handles the bus arbitration and the CAN protocol services i e bit timing stuffing error status etc Message box This memory block consists of 16 slots that can be configured either as transmitter or
404. le the TMOD1 to TMODO bits in the TAiMR register i Timer A2 One Shot Start Flag 0 to 4 10b one shot timer mode and the MR2 bit in the TAiMR register Timer A3 One Shot Start Flag _ 0 TAIOS bit enabled i TA4OS Timer A4 One Shot Start Flag When read its content is 0 0 Z phase input disabled 1 Z phase input enabled Timer A1 One Shot Start Flag TAZIE Z phase Input Enable Bit b7 b6 TAOTGL 0 0 Input on TAOIN is selected 1 Jimer A0 Eventrrigger 0 1 TB2 is selected 2 meen fo 10 TA4 is selected 2 11 TA1 is selected 2 1 Make sure the PD7_1 bit in the PD7 register is set to 0 input mode 2 Over flow or under flow Trigger Select Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TRGSR 0383h 00h TA1TGL Input on TAIN is selected 1 Timer A1 Event Trigger TB2 is selected 2 Select Bit TAO is selected 2 TAITGH TA2 is selected 2 RW TA2TGL Input on TA2IN is selected 1 RW Timer A2 Event Trigger TB2 is selected 2 Select Bit TA1 is selected 2 TA2TGH TAS is selected 2 TASTGL l Input on TASIN is selected 1 Timer A3 Event Trigger TB2 is selected 2 Select Bit TA2 is selected 2 TASTGH TA4 is selected 2 TA4TGL Input on TAIN is selected 1 Timer A4 Event Trigger TB2 is selected 2 Select Bit TAS is selected 2 TA4TGH TAO is selected 2 1 Make sure the port direction bits for the TA1IN to TA4IN pins ar
405. lied to only one 4 Kbyte block The rewrite control program in standard serial I O and CAN I O modes are written in the boot ROM area before shipment Do not rewrite the boot ROM area if using the serial programmer In parallel I O mode the boot ROM area is located in addresses OFFOOOh to OFFFFFh Rewrite this address range only if rewriting the boot ROM area Do not access addresses other than addresses OFFOOOh to OFFFFFh 21 5 2 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read and rewritten in parallel I O mode Refer to 21 2 Functions to Prevent Flash Memory from Rewriting Rev 2 00 Nov28 2005 page 287 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 6 CAN I O Mode 21 Flash Memory Version In CAN I O mode the CAN programmer supporting the M16C 6N Group M16C 6NK M16C 6NM can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board For more information about the CAN programmer contact your CAN programmer manufacturer Refer to the user s manual included with your CAN programmer for instructions Table 21 8 lists pin functions for CAN I O mode Figures 21 17 and 21 18 show pin connections for CAN I O mode 21 6 1 ID Code Check Function The ID code check function determines whether the ID codes sent from the CAN programmer matches
406. lly set to 1 when the FMRO 1 bit in the FMRO register is 1 CPU rewrite mode Effective when the PMO1 to PMOO bits are set to 01b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver This bit is reserved bit in T V ver and set to 0 The PM12 bit is set to 1 by writing a 1 in a program Writing a 0 has no effect Be sure to set this bit to 0 except for products with internal ROM area over 192 Kbytes The PM13 bit is automatically set to 1 when the FMRO 1 bit in the FMRO register is 1 CPU rewrite mode When the PM17 bit is set to 1 with wait state one wait state is inserted when accessing the internal RAM or internal ROM When the PM17 bit is set to 1 and accesses an external area set the CSiW bit i 0 to 3 in the CSR register to 0 with wait state The access area is changed by the PM13 bit as listed in the table below RAM Up to addresses 00400h to 03FFFh 15 Kbytes ROM Up to addresses D0000h to FFFFFh 192 Kbytes Addresses 04000h to 07FFFh are usable Addresses 04000h to 07FFFh are reserved External Addresses 80000h to CFFFFh are usable Addresses 80000h to CFFFFh are reserved Memory expansion mode External area is not available in T V ver Figure 6 2 PM1 Register Rev 2 00 Nov28 2005 page 41 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subje
407. lock oscillates and stops in PLL operation mode In this mode sub clock can be used as peripheral function clock PLL operation mode can only be entered from and changed to high speed mode Set the CMO6 bit to 1 divide by 8 mode before transiting from on chip oscillator mode to high or medium speed mode When exiting stop mode the CMO6 bit is set to 1 divide by 8 mode If the CMOS bit is set to 1 main clock stop then the CMO6 bit is set to 1 divide by 8 mode A transition can be made only when sub clock is oscillating State transitions within the same mode divide by n values changed or sub clock oscillation turned on or off are shown in the table below Sub Clock Oscillating Sub Clock Turned Off CM04 0 Sub clock turned off CM04 1 Sub clock oscillating CM06 0 CM17 0 CM16 0 CPU clock no division mode CM06 0 CM17 0 CM16 1 CPU clock divide by 2 mode CM06 0 CM17 1 CM16 0 CPU clock divide by 4 mode CM06 0 CM17 1 CM16 1 CPU clock divide by 16 mode CM06 1 CPU clock divide by 8 mode CM07 0 No Divide Divide Divide Divide No Divide Divide Divide Divide Division by 2 by 4 by 8 Division by 2 by 4 by 8 by 16 No Division Divide by 2 Main clock PLL clock or on chip oscillator clock selected CMO7 1 Sub clock selected CM05 0 Main clock oscillating CMO05 1
408. lock oscillator circuit contains a feedback resistor which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin Figure 8 9 shows the examples of main clock connection circuit After reset the main clock divided by 8 is selected for the CPU clock The power consumption in the chip can be reduced by setting the CMO5 bit in the CMO register to 1 main clock oscillator circuit turned off after switching the clock source for the CPU clock to a sub clock or on chip oscillator clock In this case XOUT goes H Furthermore because the internal feedback resis tor remains on XIN is pulled H to XOUT via the feedback resistor Note that if an externally generated clock is fed into the XIN pin the main clock cannot be turned off by setting the CMO5 bit to 1 unless the sub clock is selected as a CPU clock If necessary use an external circuit to turn off the clock During stop mode all clocks including the main clock are turned off Refer to 8 4 Power Control Microcomputer Microcomputer Built in feedback resistor Built in feedback resistor XIN 4 External clock Oscillator L XOUT Open NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use th
409. m m m NoD 3 25 23 eo oo m co 2 CANO Message Box 8 o eojojojo ojo ITI m m ITI QU o sa s gt Data Field oo eoo IT m moO FS CANO Message Box 8 eo Time Stamp eoo 71M ail e e gt e o T E e o TI MN m CANO Message Box 9 o Identifier DLC oojojo ojojo TM 1 7 QD 1 amp 2 2 2 2 CANO Message Box 9 o Data Field o oilolo ooo mmim m mg ou 2 2 2 OOEFh CANO Message Box 9 Time Stamp 225 226 Regse Symbo Page ides Register Symbol Page 0140 rorath CANO Message Box 10 Identifier DLC oeh CANO Message Box 14 Identifier DLC 0144n CANO Message Box 10 Data Field CANO Message Box 14 Data Field CANO Message Box 10 Time Stamp CANO Message Box 14 Time Stamp 010Fh 0110h 0111h 014Fh 0150h 0151h eo A Ul 2 ie CANO Message Box 11 Identifier DLC CANO Message Box 15 Identifier DLC o A A w gt oo AA CANO Message Box 11 Data Field CANO Message Box 15 Data Field CANO Message Box 11 Time Stamp CANO Message Box 15 Time Stamp CANO Message Box 12 Identifier DLC CANO Global Mask Register CANO Local Mask A Register COLMAR CANO Message Box 12 Data Field CANO Message Box 12 Time Stamp CANO Local Mask B Register COLMBR olojojo ojojo o oj o oj o o o o rd ord ird rd Se Der S ert ort Feri ord Bor
410. mbol Address After Reset UOCO to U2CO 03A4h OSACh 01FCh 00001000b Bit Name Function BRG Count Source Select Bit 5 00 f1SIO or f2SIO is selected 01 f8SIO is selected 10 f82SI0 is selected 1 1 Do not set a value CTS RTS Function Select Bit 1 Effective when CRD 0 0 CTS function is selected 2 1 RTS function is selected Transmit Register Empty Flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed CTS RTS Disable Bit 0 CTS RTS function enabled CTS RTS function disabled P6 0 P6 4 P7 3 can be used as I O ports Data Output Select Bit 3 TXDi SDAi and SCLi pins are CMOS output TXDi SDAi and SCLi pins are N channel open drain output Transmit data is output at falling edge of transfer clock and receive data is CLK Polarity input at rising edge Select Bit Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Transfer Format LSB first Select Bit 4 MSB first 1 CTS1 RTS1 can be used when the CLKMD1 bit in the UCON register 0 only CLK1 output and the RCSP bit in the UCON register 0 CTSO RTSO not separated 2 Set the corresponding port direction bit for each CTSi pin to 0 input mode 3 SCL2 P7 1 is N channel open drain output The NCH bit in the U2CO register is N channel open drain output regardless of the NCH bit
411. memory expansion and microprocessor modes in T V ver 3 If the PMO1 to PMOO bits are set to 01b memory expansion mode or 11b microprocessor mode in a program during single chip mode the PU11 bit becomes 1 Not available memory expansion and microprocessor modes in T V ver 4 The P7 1 pin does not have pull up 5 The pin for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high Pull up Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Address After Reset O3FEh 00h Bit Symbol Bit Name Function RW si PU20 P8_0 to P8 3 Pull Up 0 Not pulled high P8 4 P8 6 and P8 7 Pull Up 1 1 Pulled high 3 P9 0 P9 2 and P9 3 Pull Up 2 P9 4to P9 7 Pull Up P10 0 to P10_3 Pull Up PU25 P10 4to P10 7 Pull Up Nothing is assigned When write set to 0 When read their contents are O 1 The P8 5 pin does not have pull up 2 The P9 1 pin does not have pull up 3 The pin for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high Figure20 9 PURO PUR1 and PUR2 Registers Rev 2 00 Nov28 2005 page 256 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Pull up Control Register 3 128 pin version b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PUR3 03DFh 00h x Unusable 2 1 The pi
412. ment is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version ROM Code Protect Control Address 9 b7 b6 b5 b4 b3 b2 bi bO PEE EEEPE Rome oeren d ra RW RW ROM Code Protect Level 1 Protect enabled ROMCP cet Bit 1 2 2 4 Protect disabled 1 The ROMCP address is set to FFh when a block including the ROMCP address is erased 2 When the ROM code protection is active by the ROMCP 1 bit setting the flash memory is protected against reading or rewriting in parallel I O mode 3 Set the bit 5 to bit O to 111111b when the ROMCP bit is set to a value other than 11b If the bit 5 to bit O are set to values other than 111111b the ROM code protection may not become active by setting the ROMCP1 bit to a value other than 11b 4 To make the ROM code protection inactive erase a block including the ROMCP address in CPU rewrite mode standard serial I O mode or CAN I O mode 5 When a value of the ROMCPaddress is 00h or FFh the ROM code protect function is disabled Figure 21 2 ROMCP Register Address OFFFDFh to OFFFDCh ID1 Undefined instruction vector OFFFE3h to OFFFEOh ID2 Overflow vector OFFFE7h to OFFFE4h BRK instruction vector OFFFEBh to OFFFE8h ID3 Address match vector OFFFEFh to OFFFECh ID4 Single step vector OFFFF3h to OFFFFOh 1D5 Oscilation stop and re oscillation detection Watchdog timer vector OFFFF7h to OFFF
413. min 1 i 1 1 7 pa pi pi pog pog 1 T pog m Pg 25ns max rm A i 1 L 1 IE E E PIETEI IEE toye BCLK Measuring conditions e VCC 5V e Input timing voltage ViL 0 8 V ViH 2 0V e Output timing voltage VoL 0 4 V VoH 2 4 V Figure 22 11 Timing Diagram 8 Rev 2 00 Nov28 2005 page 312 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Table 22 28 Electrical Characteristics VCC 3 3V Standard Min Typ Max Parameter Measuring Condition HIGH Output PO 0to PO 7 P1_0 to P1_7 P2 OtoP2 7 lou 1mA Voltage P3 0to P3 7 P4 Oto P4 7 P5 OtoP5 7 P6 Oto P6 7 P7 0 P7 210 P7 7 P8 OtoP8 4 P8 6 P8 7 P9 0 P9 2toP9 7 P10 OtoP10 7 P11 OtoP11 7 P12 Oto P12 7 P13 OtoP13 7 P14 O0 P14 1 HIGH Output XOUT HIGHPOWER lou 0 1mA Vcc 0 5 Voltage LOWPOWER lon 50pA Vcc 0 5 HIGH Output XCOUT HIGHPOWER With no load applied Voltage LOWPOWER With no load applied LOW Output PO 0to PO 7 P1_0 to P1_7 P2_0 to P2_7 lot 1mA Voltage P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6 7 P7_0 to P7_7 P8_0 to P8_4 P8 6 P8 7 P9_0 to P9 7 P10 OtoP10 7 P11 OtoP11 7 P12 Oto P12 7 P13 OtoP13 7 P14 O0 P14 1 LOW Output XOUT HIGHPOWER lo 0 1mA Voltage LOWPOWER lo 50pA LOW Output XCOUT HIGHPOWER With no load applied Volta
414. mit Receive Register SI O4 Control Register SI O4 Bit Rate Generator S4BRG SI O5 Transmit Receive Register S5TRR SI O5 Control Register S5C SI O5 Bit Rate Generator S5BRG UARTO Special Mode Register 4 UOSMR4 UARTO Special Mode Register 3 UOSMR3 UARTO Special Mode Register 2 UOSMR2 UARTO Special Mode Register UOSMR UART1 Special Mode Register 4 U1SMR4 UART1 Special Mode Register 3 U1SMR3 UART1 Special Mode Register 2 U1SMR2 UART1 Special Mode Register U1SMR UART2 Special Mode Register 4 U2SMR4 Flash Memory Control Register 1 UART2 Special Mode Register 3 U2SMR3 UART2 Special Mode Register 2 U2SMR2 Flash Memory Control Register 0 UART2 Special Mode Register U2SMR UART2 Transmit Receive Mode Register U2MR Address Match Interrupt Register 2 UART2 Bit Rate Generator U2BRG 01BAh 01BBh Address Match Interrupt Enable Register 2 AIER2 Rene ener Bufer megIster vere 01BCh UART2 Transmit Receive Control Register 0 U2CO Address Match Interrupt Register 3 UART2 Transmit Receive Control Register 1 U2C1 01BEh O1BFh O1FFh UART2 Receive Buffer Register U2RB The blank areas are reserved B 4 CANO Message Control Register 0 COMCTLO CANO Message Control Register 1 COMCTL1 CANO Message Control Register 2 COMCTL2 CANO Message Control Register 3 COMCTL3 ANO Message Control Register 4 MCTL4 CANO Nee Centro GTT 5 COMCTLS CAN Acceptance Filte
415. mmands Jump to the rewrite control program transferred to i Execute the read array command 3 a space other than the flash memory In the following steps use the rewrite control program in a space other than the flash memory Set the FMRO1 bit to 0 CPU rewrite mode disabled In boot mode only Set the FMROS bit to 0 Boot ROM area accessed 4 Jump to a desired address in the flash memory NOTES 1 In CPU rewrite mode set the CMO6 bit in the CMO register and CM17 to CM16 bits in the CM1 register to CPU clock frequency of 10 MHz or less Set the PM17 bit in the PM1 register to 1 with wait state 2 Set the FMRO bit to 1 immediately after setting it to 0 Do not generate an interrupts or DMA transfer between setting the bit to 0 and setting it to 1 Set the bit to 0 if setting to 0 Set this bit in a space other than the flash memory while the NMI pin is held H 3 Exit CPU rewrite mode after executing the read array command 4 When CPU rewrite mode is exited while the FMRO5 bit is set to 1 the user ROM area can be accessed 5 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit 1 6 Not available the memory expansion mode in T V ver Figure 21 5 Setting and Resetting of EWO Mode Procedure to enter EW1 mode Program in the R
416. mory expansion and microprocessor modes LOW Input P3 1to P3 7 P4_0 to P4 7 P5 Oto P5 7 P6 Oto P6 7 Voltage P7 0 to P7 7 P8 0 to P8 7 P9 0 to P9 7 P10 0 to P10 7 P11 0 to P11 7 P12_0 to P12 7 P13 0toP13 7 P14 0 P14 1 XIN RESET CNVSS BYTE PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 During single chip mode PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 Data input during memory expansion and microprocessor modes loH peak HIGH Peak P0 0to PO 7 P1_0 to P1 7 P2_0 to P2_7 P3_0 to P3_7 Output Current P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 HIGH Average PO 0 to PO 7 P1_0 to P1_7 P2_0 to P2 7 P3_0 to P3_7 Output Current P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 loL peak LOW Peak PO Oto PO 7 P1_0 to P1_7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0toP7 7 P8_0 to P8 4 P8 6 P8 7 P9_0 to P9 7 P10 Oto P10 7 P11_0 to P11 7 P12_0 to P12 7 P13_0 to P13 7 P14 O0 P14 1 NOTES 1 Referenced to VCC 3 0 to 5 5V at Topr 40 to 85 C unless otherwise specified LOW Average PO 0 to PO 7 P1_0 to
417. mory expansion and microprocessor modes the PDi registers for the pins functioning as bus control pins AO to A19 DO to D15 CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified No direction register bit for P8 5 is available NOTE 1 Not available memory expansion and microprocessor modes in T V ver 20 2 Pi Register 100 pin Version i 0 to 10 128 pin Version i 0 to 13 PC14 Register Figure20 8 shows the Pi register Data input output to and from external devices are accomplished by reading and writing to the Pi register The Pi register consists of a port latch to hold the input output data and a circuit to read the pin status For ports set for input mode the input level of the pin can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register For ports set for output mode the port latch can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register The data written to the port latch is output from the pin The bits in the Pi register correspond one for one to each port During memory expansion and microprocessor modes the Pi registers for the pins functioning as bus control pins AO to A19 DO to D15 CSO to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified About the port P14 128 pin version Figure20 8 shows the PC14 register
418. n 2 The pins P11 to P14 are only in the 128 pin version Rev 2 00 Nov 28 2005 page 288 of 378 REJO9BO0124 0200 31 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version M16C 6N Group M16C 6NK Flash memory version Connect oscilator Mode setup method VCC1 VSS VSS to VCC1 Package PLQP0100KB A Figure 21 17 Pin Connections for CAN I O Mode 1 Rev 2 00 Nov 28 2005 page 289 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 102 01 1100 9091 98 97 196 95 64 93 921 91 90 189 88 B7 86 185 B4 83 182181 180 79 178 7 7 76 75 74 73 721 7 1 70169 68 6 7 166 16 M16C 6N Group M16C 6NM Flash memory version 1J 2 3 4 5 6 L7 J 8 9 1 0 ft 1 12 13 ft 4 ft 5 16 17 18 19 20 P1 P2 P3 P4 P5 P6 P7 28 29 80 81 82 3 B4 5 36 97 38 Connect oscillator circuit Mode setup method VCC1 VSS VSS to VCC1 VCC2 VSS VCC1 Package PLQP0128KB A Figure 21 18 Pin Connections for CAN I O Mode 2 Rev 2 00 Nov28 2005 page 290 of 378 RENESAS REJ09B0124 0200
419. n a count start and an effective edge input For pulse width measurement pulse widths are successively measured Use program to check whether the measurement result is an H level width or an L level width Rev 2 00 Nov28 2005 page 355 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 11 Thee Phase Motor Control Timer Function If there is a possibility that you may write data to TAi 1 register i 1 2 4 near Timer B2 overflow read the value of TB2 register verify that there is sufficient time until Timer B2 overflows before doing an immediate write to TAi 1 register In order to shorten the period from reading TB2 register to writing data to TAi 1 register ensure that no interrupt will be processed during this period If there is not enough time till Timer B2 overflows only write to TAi 1 register after Timer B2 overflowed Rev 2 00 Nov28 2005 page 356 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 12 Serial Interface 23 12 1 Clock Synchronous Serial I O Mode 23 12 1 1 Transmission reception With an external clock selected and choosing the RTS function the output level of the RTSi pin goes to L when the data receivable status becomes ready which
420. n a program after reset For this reason the voltage level on the pin becomes indeter minate causing the power supply current to increase while the port remains in input mode Furthermore by considering a possibility that the contents of the direction registers could be changed by noise or noise induced runaway it is recommended that the contents of the direction registers be periodi cally reset in software for the increased reliability of the program 2 Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins within 2 cm 3 When the ports P7 1 and P9 1 are set for output mode make sure a low level signal is output from the pins The ports P7 1 and P9 1 are N channel open drain outputs 4 With external clock input to XIN pin 5 The ports P11 to P14 are only in the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PURS register to 0 P11 to P14 unusable without causing any problem Table 20 3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Normal ver only Connection Ports PO to P7 P8 O0 to P8 4 After setting for input mode connect every pin to VSS via a resistor pull down P8 6 P8 7 P9 to P14 or after setting for output mode leave these pins open O 9 9 o P4 5 CS1 to P4 7 CS3 Connect to VCC via a resistor pulled high by setting the PD4 register s corresponding direct
421. n enabled e The TI bit in the UiC1 register O data present in the UiTB register Rev 2 00 Nov28 2005 page 357 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 12 2 Special Modes 23 12 2 1 Special Mode 1 C Mode When generating start stop and restart conditions set the STSPSEL bit in the UiSMRA register to 0 start and stop conditions not output and wait for more than half cycle of the transfer clock before setting each condition generate bit STAREQ RSTAREQ and STPREQ bits from 0 clear to 1 start 23 12 2 2 Special Mode 2 If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the RTS2 and CLK2 pins go to a high impedance state 23 12 2 3 Special Mode 4 SIM Mode A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 transmission complete and U2ERE bit in the U2C1 register to 1 error signal output after reset Therefore when using SIM mode be sure to set the IR bit to 0 no interrupt request after setting these bits Rev 2 00 Nov28 2005 page 358 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Pre
422. n for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high 2 f the PU37 bit is set to 0 unusable the P11 to P14 regisrers are set to 00h Figure20 10 PUR3 Register Port Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset O3FFh 00h Bit Symbol Operation performed when the P1 register is read 0 When the port is set for input the input levels of P1 O to P1 7 pins Port P1 Control Bit are read When set for output the port latch is read 1 The port latch is read regardless of whether the port is set for input or output Nothing is assigned When write set to 0 When read their contents are O Figure20 11 PCR Register Rev 2 00 Nov28 2005 page 257 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Table 20 2 Unassigned Pin Handling in Single chip Mode Ports PO to P7 P8 O0 to P8 4 After setting for input mode connect every pin to VSS via a resistor pull down P8 6 P8 7 P9 to P14 or after setting for output mode leave these pins open 9 9 XOUT Open NMI P8 5 Connect via resistor to VCC pull up AVCC Connect to VCC AVSS VREF BYTE Connect to VSS NOTES 1 When setting the port for output mode and leave it open be aware that the port remains in input mode until it is switched to output mode i
423. n nm d i i 30ns max Ons min T t 1 1 td BCLK RD 1 1 th BCLK RD iter 30ns max gt at Ons min tac1 RD DB 0 5 X tcyc 60 ns max i gt 1 1 i tsu 0B RD 4 He th RD DB 50ns min Ons min i td BCLK Cs 30ns max i th BCLK CS lt gt 4ns min p ta BCLK AD th BCLK AD lt gt 30ns max gt 4ns min td BCLK ALE th BCLK ALE i h WR AD A 30ns max i 4ns min 1 1 0 5 X tcyc 10 ns min i f i t dd BCLICWR 1 th BCLK WR gt gt lt i 1 30ns max Ons min i i rei Ih BCLK DB ta DB wR th wR DB 1 0 5 X tcyc 40 ns min 0 5 X tcyc 10 ns min teye ye NBCLK Measuring conditions e VCC 3 3V e Input timing voltage Vil 0 6 V Viu 2 7 V e Output timing voltage VoL 1 65 V Vou 1 65 V Figure 22 15 Timing Diagram 3 Rev 2 00 Nov 28 2005 page 322 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode VCC 3 3V For 1 wait setting and external area access Read timing td BCLK Cs 1 i th BCLK CS 4 30ns max i gt gt 4ns min td BCLK AD i i i i i th BCLK AD p 30ns max i n EE BEC i t td BCLK ALE th BCLK ALE i 30ns max gt
424. n the UiC1 register 1 reverse Tawerk 77 D IUU UUU covey Do y Dt o2 ps pa y vs X pe J 07 i Oto2 This applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock and the UFORM bit 0 LSB first Figure 15 14 Serial Data Logic Switching 15 1 1 6 Transfer Clock Output From Multiple Pins UART1 Use the CLKMD1 to CLKMDO bits in the UCON register to select one of the two transfer clock output pins Figure 15 15 shows the transfer clock output from the multiple pins function usage This function can be used when the selected transfer clock for UART1 is an internal clock Microcomputer TXD1 P6_7 CLKS1 P6_4 CLK1 P6_5 IN CLK Transfer enabled when Transfer enabled when the CLKMDO bit in the the CLKMDO bit 1 UCON register 0 This applies to the case where the CKDIR bit in the U1MR register 0 internal clock and the CLKMD1 bit in the UCON register 1 transfer clock output from multiple pins Figure 15 15 Transfer Clock Output From Multiple Pins Rev 2 00 Nov 28 2005 page 165 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 1 7 CTS RTS Function When the CTS function is used transmit and receive operation start when L is
425. nabled e The TI bit in the UiC1 register 0 data present in UiTB register If CTS function is selected input on the CTSi pin L Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled Start bit detection Interrupt Request Generation Timing For transmission one of the following conditions can be selected e The UiIRS bit 0 transmit buffer empty when transferring data from the UiTB register to the UARTi transmit register at start of transmission e The UilRS bit 21 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception e When transferring data from the UARTIi receive register to the UiRB register at completion of reception Error Detection e Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data e Framing error This error occurs when the number of stop bits set is not detected e Parity error This error occurs when if parity is enabled the number of 1 s in parity and character bits does not match the number of 1 s set Error sum flag This flag is set to 1 when any of the overrun framing or parity errors occur Select Function i Oto2 NOTES LSB first MSB first selection Whether to start sen
426. nal Do not set a value TBOMR TB3MR registers Set to 0 in event counter mode TB1MR TB2MR TBAMR TB5MR registers Nothing is assigned When write set to 0 When read its content is indeterminate When write in event counter mode set to 0 When read in event counter mode its content is indeterminate Has no effect in event counter mode Can be set to 0 or 1 0 Input from TBiIN pin 2 Event Clock Select Bit ps TBj overflow a underflow j i 1 exceptj 2 if i 0 j 5ifi 3 1 Effective when the TCK1 bit 0 input from TBiIN pin If the TCK1 bit 1 TBj overflow or underflow these bits can be set to 0 or 1 2 The port direction bit for the TBiIN pin must be set to 0 input mode Figure 13 19 TBOMR to TB5MR Registers in Event Counter Mode Rev 2 00 Nov28 2005 page 134 of 378 RENESAS REJ09B0124 0200 13 Timers Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 2 3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode the timer measures pulse period or pulse width of an external signal Table 13 8 lists specifications in pulse period and pulse width measurement mode Figure 13 20 shows TBiMR register in pulse period and pulse width measurement mode Figure 13 21 shows the operation timing when measuring a pulse period Figure 13 22 shows the op
427. nce rob eeu ots te t used tuuc tn eode Du fu tuve td eeu Edu s 84 10 4 2 Relocatable Vector Tables ssssssssssseeeeeneneeeeenn nennen nnne nnne nennen rennen 84 10 5 Interrupt Control sissies nine M R 86 VOLS Ws FAG M 88 10 52 IR Bit ee Basta EE 88 10 5 3 ILVL2 to ILVLO Bits and IL ciet cepto tr cbe ER hin Ek eed anu eid tain 88 10 5 4 Interrupt Sequeriee scito ertet esee ta e dor se sign teint tec ia t ati a ah eee tais 89 10 5 5 Interrupt Response TIITig iiiiiiuieiie iier Aann Aa AERE ANEREN EAKAS te EYE ER nS CRY RR na EORR EY Ra RE RYE EYE 90 10 5 6 Variation of IPL when Interrupt Request is Accepted ssessseee e 90 10 5 7 Saving Registers ect etie croient cre Pal RS uae da a nc EHE dente os tu rs eR ho 91 10 5 8 Returning from an Interrupt Routine ssssissresine iiis iA R enne 92 106 9 Interrupt F HONY em r 92 10 5 10 Interrupt Priority Resolution Circuit sesssesssssssseseneeeeeeneneen nee nennen 92 10 6 INT LE 0 MEE 94 10 7 NMI lcu O 98 10 8 Koy Input IMerrupt a 98 109 CANOT Wake Up Intertupt ss noe eie Recent roa ttn o aa eed A a niet ten aa 98 10 10 Address Match IME p sisi ss sdie sana vadeds seats cite dextre perd einn Jigs cee bete rex ERE sina agencies Ducere e nid rera Bee exa e
428. nd 2 are revised NOTE 3 is added 21 3 2 EW1 Mode Last sentence When an erase program is added 21 3 3 4 FMSTP Bit 8th line Procedure to change the FMSTP bit setting 1 to 4 are added Figure 21 5 Setting and Resetting of EWO Mode e First frame memory expansion mode is added e NOTE 5 is revised and NOTE6 is added Figure 21 6 Setting and Resetting of EW1 Mode NOTE 1 is revised Figure 21 7 Processing Before and After Low Power Dissipation Mode or On chipOscillator Low Power Dissipation Mode Title First and second frames left and top of right on chip oscillator low power dissipation mode is addded 21 3 4 11 Stop Mode is revised 21 3 4 12 Low Power Dissipation Mode and On chip Oscillator Low Power Dissipation Mode is partly revised 21 3 5 5 Block Erase Command Last sentence Also execute is added Figure 21 9 Block Erase Command NOTES 2 and 3 are added Figure 21 12 Full Status Check and Handling Procedure for Each Error Erase error 4 is added Table 21 7 Pin Functions for Standard Serial I O Mode Description of VCC1 VCC2 VSS is revised Description of P8 4 is revised NOTE 1 is revised NOTE 2 is added Figures 21 15 and 21 16 Circuit Application in Serial I O Mode 1 2 e VCC1 and VCC2 are added Table 21 8 Pin Functions for CAN I O Mode Description of VCC1 VCC2 VSS is revised e Description of P8 4 is revised NOTE 1 is added REVISION HISTORY M16C 6N Group M16C 6NK M
429. ndard Min Typ Max Parameter Measuring Condition Power Supply Output pins are open Flash Memory f BCLK 20MHz Current and other pins are VSS PLL operation VCC 4 2 to 5 5V No division On chip oscillation No division Flash Memory f BCLK 10MHz Program VCC 5V Flash Memory f BCLK 10MHz Erase VCC 5V Flash Memory f BCLK 32kHz Low power dissipation mode RAM f BCLK 32kHz Low power dissipation mode Flash memory Mask ROM On chip oscillation Flash Memory Wait mode f BCLK 32kHz Wait mode 3 Oscillation capacity High f BCLK 32kHz Wait mode 3 Oscillation capacity Low Stop mode Topr 25 C NOTES 1 Referenced to VCC 4 2 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 20MHz unless otherwise specified 2 This indicates the memory in which the program to be executed exists 3 With one timer operated using fC32 Rev 2 00 Nov 28 2005 page 332 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Table 22 51 A D Conversion Characteristics Standard Min Typ Max Parameter Measuring Condition Resolution VREF VCC Integral 10 bits VREF ANEXO ANEX1 input ANO to AN7 input Nonlinearity VCC ANO 0to ANO 7 input AN2_0 to AN2 7 input Erro 5
430. ng Wait Mode Table 8 4 lists the pin status during wait mode Table 8 4 Pin Status During Wait Mode Memory Expansion Mode Microprocessor Mode AO to A19 DO to D15 Retains status before wait mode Does not become a bus control pin Single chip Mode CSO to CS3 BHE RD WR WRL WRH H HLDA BCLK H ALE uos I O ports Retains status before wait mode Retains status before wait mode CLKOUT When fC selected Does not become a CLKOUT pin Does not stop When f8 f32 CMO2 bit 0 Does not stop selected CMO2 bit 1 Retains status before wait mode NOTES 1 Not available memory expansion and microprocessor modes in T V ver 2 Not available the bus control pins in T V ver 8 4 2 4 Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset NMI interrupt or peripheral function interrupt If the microcomputer is to be moved out of wait mode by a hardware reset or NMI interrupt set the peripheral function interrupt priority ILVL2 to ILVLO bits to 000b interrupt disabled before executing the WAIT instruction The peripheral function interrupts are affected by the CMO2 bit If the CMO 2 bit is 0 peripheral function clocks not turned off during wait mode peripheral function interrupts can be used to exit wait mode If the CMO2 bit is 1 peripheral function clocks turned off during wait mode the
431. nging the interrupt generate factor referred to here means any act of changing the source polarity or timing of the interrupt assigned to each software interrupt number Therefore if a mode change of any peripheral function involves changing the generate factor polarity or timing of an interrupt be sure to set the IR bit for that interrupt to O interrupt not requested after making such changes Refer to the description of each peripheral function for details about the interrupts from peripheral functions Figure 23 3 shows the procedure for changing the interrupt generate factor Changing the interrupt source Disable interrupt 9 Change the interrupt generate factor including a mode change of peripheral function Use the MOV instruction to set the IR bit to 0 interrupt not requested 9 Enable interrupt 2 9 End of change IR bit A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES 1 The above settings must be executed individually Do not execute two or more settings simultaneously using one instruction 2 Use the flag for the INTi interrupt i 0 to 8 6 to 8 are only in the 128 pin version For the interrupts from peripheral functions other than the INTi interrupt turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor In this case if the mask
432. nput P0_0 to PO 7 P1_0 to P1_7 P2_0 to P2 7 P3_0 to P3 7 Voltage P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 XIN RESET CNVSS BYTE loH peak HIGH Peak PO Oto PO 7 P1_0 to P1_7 P2_0 to P2 7 P3_0 to P3_7 Output Current P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 HIGH Average PO 0 to PO 7 P1_0 to P1 7 P2_0 to P2 7 P3_0 to P3_7 Output Current P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 loL peak LOW Peak PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 P3_0 to P3_7 Output Current P4 0 to P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 OtoP7 7 P8 0 to P8 4 P8 6 P8 7 P9_0 to P9 7 P10 Oto P10 7 P11 Oto P11 7 P12 Oto P12 7 P13_0 to P13 7 P14 0 P14 1 LOW Average P0 0 to PO 7 P1_0 to P1 7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5_0 to P5 7 P6 Oto P6 7 P7 Oto P7 7 P8 0to P8 4 P8 6 P8 7 P9_0 to P9 7 P10 Oto P10 7 P11 Oto P11 7 P12_0 to P12 7 P13_0 to P13 7 P14 0 P14 1 NOTES 1 Referenced to VCC 4 2 to 5 5V at Top
433. nt is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Count source Input signal to TAIIN pin PWM pulse output H from TAiOUT pin op IR bit in TAiIC ae register 0 i 01to4 Set to 0 upon accepting an interrupt request or by writing in program fj Frequency of count source f1 f2 f8 82 fC32 NOTES 1 n 0000h to FFFEh 2 This timing diagram is the following case TAi register 0003h e The TAITGH and TAITGL bits in the ONSF or TRGSR register 00b TAIIN pin input e The MR1 bit in the TAiMR register 1 rising edge e The MR2 bit in the TAiMR register 1 trigger selected by the TAITGH and TAITGL bits Figure 13 13 Example of 16 bit Pulse Width Modulator Operation Count source 1 Input signal to TAIIN pin Underflow signal of 8 bit prescaler 2 PWM pulse output from TAiOUT pin IR bit in TAiIC register iz0to4 Set to 0 upon accepting an interrupt request or by writing in program fj Frequency of count source f1 f2 f8 f32 C32 NOTES 1 The 8 bit prescaler counts the count source 2 The 8 bit pulse width modulator counts the output from the 8 bit prescaler underflow signal 3 m 00h to FFh n 00h to FEh 4 This timing diagram is the following case e TAI register 0202h e The TAITGH and TAITGL bits in the ONSF or TRGSR register 00b TAiIN pin input e The MR1 bit in the TAIMR register 0 falling edge e The MR2 bit in the
434. ntents and continues counting Divide Ratio 1 n 1 n set value of the TBi register 0000h to FFFFh Count Start Condition Set TBiS bit to 1 start counting Count Stop Condition Set TBiS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TBilN Pin Function Count source input Read from Timer Count value can be read by reading the TBi register Write to Timer i Oto5 When not counting and until the 1st count source is input after counting start Value written to the TBi register is written to both reload register and counter When counting after 1st count source input Value written to the TBi register is written to only reload register Transferred to counter when reloaded next j i 1 exceptj 2ifi 0 j 5ifi 3 NOTE 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Timer Bi Mode Register i 0 to 5 Bi p6 tuse tbe aS pE BIL DO Symbol Address After Reset 1 TBOMR to TB2MR OS39Bh to O39Dh 00XX0000b TB3MR to TBBMR 01DBh to 01DDh 00XX0000b Bit Symbol Bit Name Function TMODO btbo Operation Mode Select Bit 0 1 Event counter mode TMOD1 Counts falling edge of external signal Count Polarity Select Counts rising edge of external signal Bit 1 Counts falling and rising edges of external sig
435. ntents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 5 2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CiCTLR register i 0 1 to 0 If the Reset bit is set to 0 check that the State Reset bit in the CiSTR register is set to 0 If 11 consecutive recessive bits are detected after entering the CAN operation mode the module initiates the following functions The module s communication functions are released and it becomes an active node on the network and may transmit and receive CAN messages Release the internal fault confinement logic including receive and transmit error counters The module may leave the CAN operation mode depending on the error counts Within the CAN operation mode the module may be in three different sub modes depending on which type of communication functions are performed Module idle The modules receive and transmit sections are inactive Module receives The module receives a CAN message sent by another node Module transmits The module transmits a CAN message The module may receive its own message simultaneously when the LoopBack bit in the CiCTLR register 1 Loop back mode enabled Figure 19 13 shows sub modes of the CAN operation mode Module idle TrmState 0 RecState 0 Start Detect transmission an SOF Finish transmission Module transmits Module receives TrmState 1 TrmState 0 RecState 0
436. nterface format 1 Direct format clock L noms D0 D1 j D2 D3 D4 D5 D6 D7 P P Even parity 2 Inverse format Transfer P E clock TAS ae D7 A De Do Da pay D2 X_D1X Do P P Odd parity Figure 15 35 SIM Interface Format Rev 2 00 Nov28 2005 page 195 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 2 SI Oi i 3 to 6 SI Oi is exclusive clock synchronous serial I Os Figure 15 36 shows the block diagram of SI Oi and Figures 15 37 and 15 38 show the SI Oi related registers Table 15 19 lists the specifications of SI Oi NOTE 1 100 pin version supports SI O3 and SI O4 128 pin version supports SI O3 SI O4 SI O5 and SI O6 Clock source select 2 f2SIO PCLK1z0 SMi1 to SMiO Main clock 5 eP Data bus PLL clock O or on chip oscillator clock PCLK1 1 f8SIO 01b f32S1 O Synchronous Ta SiBRG register 10b O SMi6 CLK polarity SI Oi reversing SI O counter i interrupt circuit request SMi2 SMi3 SOUTI e sd SMi5 LSB d MSB SINi C SiTRR register 8 i 3 to 6 5 and 6 are only in the 128 pin version n A value set in the SIBRG register Figure 15 36 SI Oi Block Diagram Rev 2 00 Nov28 2005 page 196 of 378 RENESAS REJ09B0124 0200 Under development This doc
437. nterrupt Control Register a The interrupt control register for any interrupt should be modified in places where no interrupt requests may be generated Otherwise disable the interrupt before rewriting the interrupt control register b To rewrite the interrupt control register for any interrupt after disabling that interrupt be careful with the instruction to be used Changing any bit other than IR bit If while executing an instruction an interrupt request controlled by the register being modified is generated the IR bit of the register may not be set to 1 interrupt requested with the result that the interrupt request is ignored If such a situation presents a problem use the instructions shown below to modify the register Usable instructions AND OR BCLR BSET Changing IR bit Depending on the instruction used the IR bit may not always be set to 0 interrupt not requested Therefore be sure to use the MOV instruction to set the IR bit to O c When using the flag to disable an interrupt refer to the sample program fragments shown below as you set the flag Refer to b for details about rewrite the interrupt control registers in the sample program fragments Examples 1 through 3 show how to prevent the flag from being set to 1 interrupt enabled before the interrupt control register is rewritten owing to the effects of the internal bus and the instruction queue buffer Example 1 Using the NOP instr
438. ntervention Two DMAC channels are included Each time a DMA request occurs the DMAC transfers one 8 or 16 bit data from the source address to the destination address The DMAC uses the same data bus as used by the CPU Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method it can transfer one word 16 bits or one byte 8 bits of data within a very short time after a DMA request is generated Figure 12 1 shows the block diagram of the DMAC Table 12 1 shows the DMAC specifications Figures 12 2 to 12 4 show the DMAC related registers Address bus Ad aurea porter SA c I vane aurea agar om cwmrsecepamersew E gt V V V DMAt transfer counter reload register TCR1 DMA1 forward address pointer 5 Data bus low order bits Data bus high order bits NOTE 1 Pointer is incremented by a DMA request Figure 12 1 DMAC Block Diagram A DMA request is generated by a write to the DSR bit in the DMIiSL register i 0 1 as well as by an interrupt request which is generated by any function specified by the DMS and DSEL3 to DSELO bits in the DMiSL register However unlike in the case of interrupt requests DMA requests are not affected by the flag and the interrupt control register so that even when interrupt requests are disabled and no interrupt request can be accepted DMA requests are always accepted Furthermore because the DMAC does not affect interrupts th
439. nth time timer B2 underflow occurs When the INV01 bit is set to 1 the INVOO bit selects count timing of the ICTB2 counter and setting value is n the timer B2 interrupt is generated every nth time timer B2 underflow meeting the condition selected in the INVOO bit occurs Nothing is assigned When write set to 0 EH 1 Use the MOV instruction to set the ICTB2 register 2 If the INVO1 bit is set to 1 set the ICTB2 register when the TB2S bit is set to 0 timer B2 counter stopped If the INVO1 bit is set to 0 and the TB2S bit to 1 timer B2 counter start do not set the ICTB2 register when the timer B2 underflows 3 If the INVOO bit is set to 1 the first interrupt is generated when the timer B2 underflows n 1 times n being the value set in the ICTB2 counter Subsequent interrupts are generated every n times the timer B2 underflows Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TB2SC 039Eh XXXXXX00b 0 Timer B2 underflow Timer B2 Belo Timing 1 Timer A output at odd numbered Switching Bit 2 occurrences 0 Three phase output forcible cutoff by NMI input high impedance Three Phase Output Port disabled NMI Control Bit 1 3 1 Three phase output forcible cutoff by NMI input high impedance enabled IVPCR1 Nothing is assigned When write set to 0 b7 b2 When read their contents are O 1 Write to this register after setting the PRC1 bit in the PRCR r
440. nts are subject to change M16C 6N Group M16C 6NK M16C 6NM Sub clock oscillation circuit XCIN XCOUT O Sub clock 8 Clock Generating Circuit CMO01 CM00 00b 1 0 ports PMO1 PM00 00b CM01 CM00 01b fC32 PMO1 PMO0 00b EE ON o CLKOUT PMO1 PM00 00b CM01 CM00 11b X On chip Divider Divider R oO CANO r 29 L o R L o CAN1 r 2 Lo Poko By CCLKO 1 and 2 Oo By CCLK4 5 and 6 f2 PCLKO 0 f S e gt 32 On chip oscillator clock PCLKO 1 CM10 1 stop mode Main clock Main clock oscillation circuit CM05 t oscillator Oscillation stop re oscillation X detection circuit PLL frequency synthesizer qr clock 1 0 CM11 D PCLKO 0 f1SIO PCLKi 1 ges a gt PCLK1 0 f8SIO Seo b jc ld CM21 1 CM07 0 Divider Oc 0 CPU clock M f 0 M X CM07 1 BCLK WAIT instruction RESET Software reset Interrupt request level judgment output PMOO PMO1 CM00 CMO1 CM02 CM04 CM05 CMO6 CMO7 CM10 CM11 CM16 CM17 PCLKO PCLK1 CM21 CM27 CCLKO to CCLK2 CCLK4 to CCLK6
441. o 0 5mA LOW Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied Hysteresis HOLD RDY TAOIN to TA4IN TBOIN to TBSIN INTO to INT8 NMI ADTRG CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 CLKO to CLK6 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD2 SIN3 to SING Hysteresis RESET Hysteresis XIN HIGH Input Current PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 O to P5 P6 0 to P6 7 P7_0 to P7 7 P8 0 to P8 P9 0to P9 7 P10 0to P10 7 P11_0 to P11 P12 0to P12 7 P18 Oto P13 7 P14 0 P14 XIN RESET CNVSS BYTE LOW Input Current PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 P3 0 to P8 7 P4 0 to P4 7 P5 0 to P5 P6 0 to P6 7 P7 O0 to P7 7 P8 0 to P8 P9 Oto P9 7 P10 0to P10 7 P11_0 to P11 P12_0 to P12 7 P13_0 to P138 7 P14 0 P14 XIN RESET CNVSS BYTE ReuiLuP Pull up Resistance PO 0 to PO 7 P1 Oto P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5_0 to P5 P6 0to P6 7 P7 0 P7_2 to P7 7 P8_0 to P8_4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11 0toP11 7 P12 0to P12 7 P13_0 to P13 7 P14 0 P14 1 Rexin Rixcin Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage VRAM At stop mode NOTES 1 Referenced to VCC 4 2 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 24MHz unless otherwise specified 2 P11 to P14
442. o at a point that does not generate the interrupt request for that register For details refer to 23 8 Interrupt Use the IFSRO7 bit in the IFSRO register to select Use the IFSRO6 bit in the IFSRO register to select This bit can only be reset by writing 0 Do not write 1 Use the IFSRO4 bit in the IFSRO register to select The SSIC register is only in the 128 pin version In the 100 pin version set the IFSRO4 bit to 0 Timer B5 If the PCLK6 bit in the PCLKR register is set to 1 CO1ERRIC KUPIC register can be assigned in an address 004Dh and the ADIC register can be assigned in an address 004Eh SFR location of the KUPIC register is changed from address 004Eh to address 004Dh 7 Use the IFSRO5 bit in the IFSRO register to select The S6IC register is only in the 128 pin version In the 100 pin version set the IFSROS5 bit to 0 Timer BO 8 When the IFSRO bit in the IFSRO register 0 CANO 1 wake up or error CANO 1 wake up is selected When the IFSRO2 bit 1 CANO wake up error or CAN1 wake up error CANO wake up error is selected 9 When the IFSRO 2 bit 0 CANO 1 error is selected When the IFSRO2 bit 1 CAN1 wake up error is selected Figure 10 3 Interrupt Control Registers 1 Rev 2 00 Nov28 2005 page 86 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt Interrupt C
443. o interrupts or no DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction Rev 2 00 Nov28 2005 page 345 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 8 Interrupt 23 8 1 Reading Address 00000h Do not read the address 00000h in a program When a maskable interrupt request is accepted the CPU reads interrupt information interrupt number and interrupt request priority level from the address 00000h during the interrupt sequence At this time the IR bit for the accepted interrupt is set to 0 If the address 00000h is read in a program the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0 This causes a problem that the interrupt is canceled or an unexpected interrupt request is generated 23 8 2 Setting SP Set any value in the SP USP ISP before accepting an interrupt The SP USP ISP is set to 0000h after reset Therefore if an interrupt is accepted before setting any value in the SP USP ISP the program may go out of control Especially when using NMI interrupt set a value in the ISP at the beginning of the program For the first and only the first instruction after reset all interrupts including NMI interrupt are disabled 23 8 3 NMI Interrupt The NMI interrupt cannot be disa
444. ock from XCIN and leave XCOUT open BCLK output BCLK Outputs the BCLK signal Clock output CLKOUT The clock of the same cycle as fC f8 or f32 is output INT interrupt input NTO to INT8 9 Input pins for the INT interrupt NMI interrupt input NMI Input pin for the NMI interrupt Key input interrupt input KIO to KI3 Input pins for the key input interrupt TAOOUT to TA4OUT These are timer AO to timer A4 I O pins TAOIN to TA4IN These are timer AO to timer A4 input pins ZP Input pin for the Z phase These are timer BO to timer B5 input pins Three phase motor control output TBOIN to TBSIN U U V V W W These are Three phase motor control output pins Serial interface CTSO to CTS2 These are send control input pins RTSO to RTS2 These are receive control output pins CLKO to CLK6 These are transfer clock I O pins RXDO to RXD2 These are serial data input pins SING to SIN6 These are serial data input pins TXDO to TXD2 These are serial data output pins SOUTS to SOUT6 9 These are serial data output pins CLKS1 This is output pin for transfer clock output from multiple pins function C mode SDAO to SDA2 These are serial data I O pins SCLO to SCL2 These are transfer clock I O pins however SCL2 for the N channel open drain output Refer
445. ocument is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Under development 22 Electric Characteristics Normal ver o D i fo a N o o o pn Q O pen E D c G o o c m c G Q x ui gt i o E o rn o o e o o 3 c wx o X o o c G D amp E D o h F e LE o LL ng Read timi ta BCLK CS 4 25ns max Ons min 40ns min Write timing 0 5 X tcyc 10 ns min h WR AD 0 5 X tcyc 10 ns min 2 5 X tcyc 40 ns min Measuring conditions Vit 2 0 8 V ViH 2 0 V e Output timing voltage VoL 0 4 V Vou 2 4 V e Input timing voltage Figure 22 9 Timing Diagram 6 134 NESAS Rev 2 00 Nov28 2005 page 310 of 378 REJO9BO0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode For 1 or 2 wait setting external area access and multiplexed bus selection Read timing Write timing BCLK f teyc Ye NBCLK td BCLK CS td AD ALE ALE AD 1 0 5 X tcyc 25 ns min DA y p P td BCLK AD 25ns max td BCLK ALE lt gt 25ns max gt tans min ta BCLK Cs 25ns max we 1 Da ta AD ALE 0 5 X tcyc 25 ns min p 2
446. ode when processing two phase pulse signal with timers A2 A3 and A4 Specification Count Source e Two phase pulse signals input to TAiIN or TAiOUT pins Count Operation Up count or down count can be selected by two phase pulse signal When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divide Ratio 1 FFFFh n 1 for up count 1 n 1 for down count n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer overflow or underflow TAiIN Pin Function Two phase pulse input TAiOUT Pin Function Two phase pulse input Read from Timer Count value can be read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter When counting after 1st count source input Value written to TAi register is written to reload register Transferred to counter when reloaded next Select Function Normal processing operation timer A2 and timer A3 The timer counts up rising edges or counts down falling edges on TAjIN pin when input signals on TAjOUT pin is H TAjOUT TAjIN i Y Y Up Up Up
447. odulation mode To use the Timer Ai interrupt the IR bit set the IR bit to 0 by program after the above listed changes have been made When setting TAiS bit to 0 count stop during PWM pulse output the following action occurs Stop counting e When TAiOUT pin is output H output level is set to L and the IR bit is set to 1 When TAiOUT pin is output L both output level and the IR bit remain unchanged If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 2 00 Nov28 2005 page 353 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 2 Timer B 23 10 2 1 Timer B Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TBIMR i 0 to 5 register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 4 count starts Always make sure the TBiMR register is modified while the TBiS bit remains 0 count stops regardless whether after reset or not NOTE 1 The TBOS to TB2S bits are the bits 5 to 7 in the TABSR register the TB3S to TB5S bits are the bits 5 to 7 in the TBSR register A value of a counter while
448. of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 1 3 One shot Timer Mode In one shot timer mode the timer is activated only once by one trigger When the trigger occurs the timer starts up and continues operating for a given period Table 13 4 lists specifications in one shot timer mode Figure 13 11 shows the TAiMR register in the one shot timer mode Table 13 4 Specifications in One shot Timer Mode Count Source Specification f1 f2 f8 f32 C32 Count Operation e Down count When the counter reaches 0000h it stops counting after reloading a new value e Ifa trigger occurs when counting the timer reloads a new count and restarts counting Divide Ratio 1 n n set value of the TAi register 0000h to FFFFh However the counter does not work if the divide by n value is set to 0000h Count Start Condition The TAIS bit in the TABSR register 1 start counting and one of the following triggers occurs e External trigger input from the TAiIN pin Timer B2 overflow or underflow Timer Aj overflow or underflow Timer Ak overflow or underflow The TAiOS bit in the ONSF register is set to 1 timer starts Count Stop Condition e When the counter is reloaded after reaching 0000h TAiS bit is set to 0 stop counting Interrupt Request Generation Timing When the coun
449. of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 5 5 Block Erase Command The block erase command erases each block By writing xx20h in the first bus cycle and xxDOh to the highest order even address of a block in the second bus cycle an auto erase operation erase and verify will start in the specified block The FMROO bit in the FMRO register indicates whether an auto erase operation has been completed The FMROO bit is set to 0 busy during auto erase and to 1 ready when the auto erase operation is completed After the completion of an auto erase operation the FMRO7 bit in the FMRO register indicates whether or not the auto erase operation has been completed as expected Refer to 21 3 8 Full Status Check Figure 21 9 shows a flow chart of the block erase command programming The lock bit protects each block from being programmed inadvertently Refer to 21 3 6 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EWO mode the microcomputer enters read status register mode as soon as an auto erase operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto erase operation starts It is set to 1 when an auto erase operation is completed The m
450. on to write to this register 3 The SSBRG and S6BRG registers are only in the 128 pin version 4 Write to this register after setting the SMi1 to SMi0 bits in the SiC register SI Oi Transmit Receive Register i 3 to 6 o Symbol Address After Reset S3TRR 01E0h Indeterminate S4TRR 01E4h Indeterminate S5TRR 3 01E8h Indeterminate S6TRR 3 01D6h Indeterminate Setting Range 1 Write to this register while serial I O is neither transmitting nor receiving Description Transmission reception starts by writing transmit data to this register After transmission reception finishes reception data can be read by reading this register 1 Write to this register while serial I O is neither transmitting nor receiving 2 To receive data set the corresponding port direction bit for SINI to 0 input mode 3 The SSTRR and S6TRR registers are only in the 128 pin version 1 Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to 1 write enabled 2 Set the SMi3 bit to 1 SOUTi output CLKi function and the corresponding port direction bit to 0 input mode 3 Set the SMiS bit to 1 SOUTi output CLKi function 4 When the SM32 SM52 or SM62 bit 1 the corresponding pin is placed in the high impedance state regardless of which functions of those pins are being used SI OA4 is effective only when the SM43 bit 1 SOUTA output CLK4 function 5 When using SI O4 se
451. ontrol Register Symbol Address After Reset INT3IC 2 0044h XX00X000b C1RECIC S4IC INTSIC 2 7 0048h XX00X000b C1TRMIC SSIC INTAIC 2 8 0049h XX00X000b b7 b6 b5 b4 b3 b2 bi INTOIC to INT2IC 005Dh to 005Fh XX00X000b X NZ TA2IC INT7IC 9 0057h XX00X000b Xo TTL TASIC INT6IC 10 0058h XX00X000b TB1IC INT8IC 11 005Bh XX00X000b Eit Symbol Level 0 interrupt disabled Level 1 i Interrupt Priority Level gaa g Select Bit Level 4 Level 5 Level 6 Level 7 Interrupt not requested o Interrupt Request Bit Interrupt requested E Selects falling edge 4 gt a Polarity Select Bit Selects rising edge fase e es lResevedBit Bit Seto to 0 Nothing is assigned When write set to O b7 b6 When read their contents are indeterminate To rewrite the interrupt control registers do so at a point that does not generate the interrupt request for that register For details refer to 23 8 Interrupt When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode set the ILVL2 to ILVLO bits in the INT5IC to INT3IC registers to 000b interrupt disabled Not available memory expansion and microprocessor modes in T V ver This bit can only be reset by writing 0 Do not write 1 If the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register are 1 both edges set the POL bit in the INTOIC to INT8IC registe
452. ontrol Register O 00h Three Phase PWM Control Register 1 00h Three Phase Output Buffer Register 0 00h Three Phase Output Buffer Register 1 00h Dead Time Timer XXh Timer B2 Interrupt Occurrence Frequency Set Counter XXh Interrupt Cause Select Register 2 X0000000b XXh O1D1h Timer B3 Register XXh 5 Dn Timer B4 Register 01D4h XXh Timer B5 Register XXh SI O6 Transmit Receive Register 1 S6TRR XXh SI O6 Control Register 1 Sec 01000000b SI O6 Bit Rate Generator 1 S6BRG XXh SI O3 4 5 6 Transmit Receive Register 2 S3456TRR XXXX0000b Timer B3 Mode Register TB3MR 00XX0000b Timer B4 Mode Register TBAMR 00XX0000b Timer B5 Mode Register TB5MR 00XX0000b Interrupt Cause Select Register 0 IFSRO 00h Interrupt Cause Select Register 1 IFSR1 00h SI O3 Transmit Receive Register S3TRR XXh SI O3 Control Register S3C 01000000b SI O3 Bit Rate Generator S3BRG XXh SI O4 Transmit Receive Register SATRR XXh SI O4 Control Register S4C 01000000b SI O4 Bit Rate Generator S4BRG XXh SI O5 Transmit Receive Register 1 S5TRR XXh SI O5 Control Register 1 S5C 01000000b SI O5 Bit Rate Generator 1 S5BRG XXh UARTO Special Mode Register 4 UOSMR4 00h UARTO Special Mode Register 3 UOSMR3 000X0X0Xb UARTO Special Mode Register 2 UOSMR2 X0000000b UARTO Special Mode Register UOSMR X0000000b
453. onversion To carry out A D conversion properly charging the internal capacitor C shown in Figure 16 10 has to be completed within a specified period of time T sampling time as the specified time Let output impedance of sensor equivalent circuit be RO microcomputer s internal resistance be R precision error of the A D converter be X and the resolution of A D converter be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode Lu VC is generally VC VIN 1 e C RO R X And when t T VCSVIN E VINZVIN 1 1 T C RO R X j Y T a COGAHOXR CY Hence RO R Cejn X Y Figure 16 10 shows analog input pin and external sensor equivalent circuit When the difference between VIN and VC becomes 0 1LSB we find impedance RO when voltage between pins VC changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f 6AD 10 MHz T 0 3 us in the A D conversion mode with sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 3 us R 7 8 KQ C 1 5 pF X 0 1 and Y 1024 Hence 0 3 X 105 RO 7 8 X108 13 9 X 108 1 1 5 X 10 In 1024 Thus the allowable output impedance of the sensor circuit capable of thoroughly
454. or Executing Interrupt Sequence Rev 2 00 Nov28 2005 page 89 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 5 5 Interrupt Response Time Figure 10 6 shows the interrupt response time The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed Specifically it consists of a time from when an interrupt request is generated till when the instruction then executing is completed a on Figure 10 6 and a time during which the interrupt sequence is executed b on Figure 10 6 Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine b Interrupt response time a A time from when an interrupt request is generated till when the instruction then executing is completed The length of this time varies with the instruction being executed The DIVX instruction requires the longest time which is equal to 30 cycles without wait state the divisor being a register b A time during which the interrupt sequence is executed For details see the table below Note however that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single step interrupts Interrupt V
455. or count register CITECR register 8 bits Indication of the error status of the CAN module in transmission the counter value is incremented or decremented according to the error occurrence e CANi time stamp register CiTSR register 16 bits Indication of the value of the time stamp counter e CANI acceptance filter support register CiIAFS register 16 bits Decoding the received ID for use by the acceptance filter support unit Explanation of each register is given below Rev 2 00 Nov28 2005 page 224 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 2 CANi Message Box i 0 1 Table 19 1 shows the memory mapping of the CANi message box It is possible to access to the message box in byte or word Mapping of the message contents differs from byte access to word access Byte access or word access can be selected by the MsgOrder bit of the CiCTLR register Table 19 1 Memory Mapping of CANi Message Box Address 19 CAN Module Message Content Memory mapping CANO 0060h n 16 0 Byte access 8 bits 0260h n 16 0 SID10 to SID6 Word access 16 bits SID5 to SIDO 0060h ne 164 1 0260h n 16 1 SID5 to SIDO SID10 to SID6 0060h n 16 2 0260h n 16 2 EID17 to EID14 EID13 to EID6 0060h n 16 3 0260h n 16 3 EID13 to EID6 EID17 to EID14 0060h n 16 4
456. or peripheral function interrupts not used to exit wait mode are set to 000b interrupt disable 2 Set the I flag to 1 3 Start operating the peripheral functions used to exit wait mode When the peripheral function interrupt is used an interrupt routine is performed as soon as an interrupt request is acknowledged and the CPU clock is supplied again When the microcomputer exits wait mode by the peripheral function interrupt the CPU clock is the same clock as the CPU clock executing the WAIT instruction Rev 2 00 Nov28 2005 page 72 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 4 3 Stop Mode 8 Clock Generating Circuit In stop mode all oscillator circuits are turned off so are the CPU clock and the peripheral function clocks Therefore the CPU and the peripheral functions clocked by these clocks stop operating The least amount of power is consumed in this mode If the voltage applied to VCC is VRAM or more the internal RAM is retained However the peripheral functions clocked by external signals keep operating Table 8 6 lists the interrupts to stop mode and use conditions Table 8 6 Interrupts to Stop Mode and Use Conditions Interrupt NMI Interrupt Can be used Condition Key Input Interrupt Can be used INT Interrupt Can be used Timer A Interrupt Timer B interru
457. ore information refer to the programmer manual 2 In this example modes are switched between single chip mode and standard serial 1 O mode by controlling the CNVSS input with a switch 3 If in standard standard serial I O mode 1 there is a possibility that the user reset signal will go low during standard serial I O mode break the connection between the user reset signal and RESET pin by using for example a jumper switch Figure 21 15 Circuit Application in Standard Serial I O Mode 1 P6 5 CLK1 P6 7 TXD1 P6 A RTS1 P6 6 RXD1 Reset input User reset signal NOTES 1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the CNVSS input with a switch Figure 21 16 Circuit Application in Standard Serial I O Mode 2 Rev 2 00 Nov28 2005 page 286 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 5 Parallel I O Mode In parallel I O mode the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C 6N Group M16C 6NK M16C 6NM Contact your parallel programmer manufacturer for more information on the parallel programmer Refer to the user s manual included with your parallel programmer for instructions 21 5 1 User ROM and Boot ROM Areas An erase block operation in the boot ROM area is app
458. ounting 3 Value read from the TBi register is indeterminate until the second valid edge is input after the timer starts counting Rev 2 00 Nov 28 2005 page 135 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Timer Bi Mode Register i 0 to 5 Symbol TBOMR to TB2MR TB3MR to TBBMR Bit Name Operation Mode Select Bit Address 039Bh to 039Dh 01DBh to 01DDh 13 Timers After Reset 00XX0000b 00XX0000b Function Pulse period pulse width measurement mode Measurement Mode Select Bit Pulse period measurement Measurement between a falling edge and the next falling edge of measured pulse Pulse period measurement Measurement between a rising edge and the next rising edge of measured pulse Pulse width measurement Measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge 1 1 Do not set a value Timer Bi Overflow Flag 1 TBOMR and TB3MR registers Set to 0 in pulse period and pulse width measurement mode TB1MR TB2MR TB4MR TB5MR registers Nothing is assigned When write set to 0 When read its content turns out to be indeterminate 0 Timer did not overflow 1 Timer has overflown Count Source Select Bit b7 b6 00 f1 orf2 01 f8 10 f32 11 fC32 1 This flag is indeterminate aft
459. ources for the CPU clock can be switched over the new clock source to which switched must be oscillating stably If the new clock source is the main clock sub clock or PLL clock allow a sufficient wait time in a program until it becomes oscillating stably Note that operation modes cannot be changed directly from low speed or low power dissipation mode to on chip oscillator or on chip oscillator low power dissipation mode Nor can operation modes be changed directly from on chip oscillator or on chip oscillator low power dissipation mode to low speed or low power dissipation mode Where the CPU clock source is changed from the on chip oscillator to the main clock change the operation mode to the medium speed mode divide by 8 mode after the clock was divided by 8 the CMO6 bit in the CMO register was set to 1 in the on chip oscillator mode 8 4 1 1 High speed Mode The main clock divided by 1 provides the CPU clock If the sub clock is activated C32 can be used as the count source for timers A and B 8 4 1 2 PLL Operation Mode The main clock multiplied by 2 4 or 6 provides the PLL clock and this PLL clock serves as the CPU clock If the sub clock is activated fC32 can be used as the count source for timers A and B PLL operation mode can be entered from high speed mode If PLL operation mode is to be changed to wait or stop mode first go to high speed mode before changing NOTE 1 The main clock multiplied by 6 is available Normal v
460. ow chart of the lock bit program command programming Execute read lock bit status command to read lock bit state lock bit data The FMROO bit in the FMRO register indicates whether a lock bit program operation is completed Refer to 21 3 6 Data Protect Function for details on lock bit functions and how to set it to 1 unlocked Write command code xx77h to the highest order block address Write xxDOh to the highest order block address Full status check Lock bit program operation is completed NOTE 1 Write the command code and data to even addresses Figure 21 10 Lock Bit Program Command Rev 2 00 Nov28 2005 page 276 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 5 8 Read Lock Bit Status Command 71h The read lock bit status command reads the lock bit state of a specified block By writing xx71h in the first bus cycle and xxDOh to the highest order even address of a block in the second bus cycle the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked Read the FMR16 bit after the FMROO bit in the FMRO register is set to 1 ready Figure 21 11 shows a flow chart of the read lock bit status command programming Write the command code xx71h Write xxDOh to the highest order block address
461. ows if the INVO6 bit is set to 0 triangular wave modulation mode Figure 14 1 Three Phase Motor Control Timer Function Block Diagram Rev 2 00 Nov28 2005 page 139 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Three Phase PWM Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset INVCO 01C8h 00h Bit i 0 The ICTB2 counter is incremented by one on the Interrupt Enable Output rising edge of the timer A1 reload control signal Polarity Select Bit 1 The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 2 0 ICTB2 counter is incremented by one when Interrupt Enable Output timer B2 underflows Specification Bit 1 Selected by the INVOO bit 2 0 No three phase control timer functions 1 Three phase control timer function 5 Mode Select Bit 0 Disables three phase control timer output 5 Culpa Control Bit 1 Enables three phase control timer output 6 Positive and Negative 0 Enables concurrent active output Phases Concurrent Active 3 p Disable Function Enable Bit 1 Disables concurrent active output Positive and Negative Phases Concurrent Active Output Detect Flag 0 Not detected 1 Detected 7 Modulation Mode 0 Triangular wave modulation mode S
462. peripheral functions using the peripheral function clocks stop operating so that only the peripheral functions clocked by external signals can be used to exit wait mode Table 8 5 lists the interrupts to exit wait mode Rev 2 00 Nov28 2005 page 71 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit Table 8 5 Interrupts to Exit Wait Mode and Use Conditions CMO2 Bit 0 CM02 Bit 1 NMI Interrupt Can be used Can be used Serial Interface Interrupt Can be used when operating with Can be used when operating with internal or external clock external clock Key Input Interrupt Can be used Can be used A D Conversion Interrupt Can be used in one shot mode or Do not use single sweep mode Timer A Interrupt Can be used in all modes Can be used in event counter mode Timer B interrupt or when the count source is fc32 INT Interrupt Can be used Can be used CANO 1 Wake up Interrupt Can be used in CAN sleep mode Can be used in CAN sleep mode If the microcomputer is to be moved out of wait mode by a peripheral function interrupt set up the following before executing the WAIT instruction 1 Set the ILVL2 to ILVLO bits in the interrupt control register for peripheral function interrupts used to exit wait mode The ILVL2 to ILVLO bits in all other interrupt control registers f
463. pins ANO to AN5 6 pins ANO to AN7 8 pins Reading of Result of A D Converter NOTE Read one of the ADO to AD7 registers that corresponds to the selected pin 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 2 00 Nov28 2005 page 212 of 378 RENESAS REJ09B0124 0200 16 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi CECI S X Analog Input Pin Select Bit Invalid in repeat sweep mode 0 ES oreo pages M Select Bit 0 Repeats sweep mode 1 EN MC a 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 SEL NS MELLON NEN CN Symbol Address After reset Li day Ie ADCON1 03D7h 00h When repeat sweep mode 0 is selected b1 b0 0 0 ANO AN1 2 pins A D Sweep Pin Select Bit p 1 ANO to ps iR 10 ANO to AN5 6 pins 1 1 ANO to AN7 8 pins 2 A D Operation Mode Set to 0 when repeat sweep Select Bit 1 mode 0 is selected ie 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode E Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 3 1 VREF connected b7 b6 0 0 ANEXO and ANEX1 are not used RW 0 1 Do not set a value 1 0 Do not set a value 1 1 External op amp connection mode External Op Amp Connec
464. pond to Basic CAN mode In normal operation mode each slot can handle only one type message at a time either a data frame or a remote frame by setting CiMCTLj regisrer j O to 15 However in Basic CAN mode slots 14 and 15 can receive both types of message at the same time When slots 14 and 15 are defined as reception slots in Basic CAN mode received messages are stored in slots 14 and 15 alternately Which type of message has been received can be checked by the RemActive bit in the CiMCTLj register Figure 19 19 shows the operation of slots 14 and 15 in Basic CAN mode Slot 14 Locked Msg n Msg n 2 Msgn lost 7 Slot 15 Locked empty Locked empty Locked Msg n1 Msg n 1 Msg n 2 Figure 19 19 Operation of Slots 14 and 15 in Basic CAN Mode When using Basic CAN mode note the following points 1 Setting of Basic CAN mode has to be done in CAN reset initialization mode 2 Select the same ID for slots 14 and 15 Also setting of the CILMAR and CiLMBR register has to be the same 8 Define slots 14 and 15 as reception slot only 4 There is no protection available against message overwrite A message can be overwritten by a new message 5 Slots 0 to 13 can be used in the same way as in normal CAN operation mode Rev 2 00 Nov28 2005 page 241 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module
465. ps X De X D7 i 0to2 This applies to the case where the UFORM bit in the UiCO register 0 LSB first and the UiLCH bit in the UiC1 register O no reverse NOTES 1 When not transferring the CLKi pin outputs a high signal 2 When not transferring the CLKi pin outputs a low signal Figure 15 12 Transfer Clock Polarity Rev 2 00 Nov28 2005 page 163 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 1 3 LSB First MSB First Select Function Use the UFORM bit in the UiCO register i 0 to 2 to select the transfer format Figure 15 13 shows the transfer format 1 When the UFORM bit in the UiCO register O LSB first CLKi TXDi X Do X D1 X D2 X D3 X D4 X Ds X De X D7 RXDi X po X D1 X D2 X D3 X D4 X D5 X De X D7 2 When the UFORM bit in the UiCO register 1 MSB first CLKi TXDi X D7 X De X DS X D4 X D3 X D2 X D1 X DO RXDi X pz X De X D5 X D4 X D3 X D2 X D1 X DO i Oto2 This applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock and the UiLCH bit in the UiC1 register 0 no reverse Figure 15 13 Transfer Form
466. pt Can be used when counting external pulses in event counter mode Serial Interface Interrupt Can be used when external clock is selected CANO 1 Wake up Interrupt Can be used when CAN sleep mode is selected 8 4 3 1 Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to 1 all clocks turned off At the same time the CMO6 bit in the CMO register is set to 1 divide by 8 mode and the CM15 bit in the CM1 register is set to 1 main clock oscillator circuit drive capability high Before entering stop mode set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled Also if the CM11 bit in the CM1 register is 1 PLL clock for the CPU clock source set the CM11 bit to 0 main clock for the CPU clock source and the PLCO7 bit in the PLCO register to 0 PLL turned off before entering stop mode 8 4 3 2 Pin Status in Stop Mode Table 8 7 lists the pin status in stop mode Table 8 7 Pin Status in Stop Mode AO to A19 DO to D15 CSO to CS3 BHE Memory Expansion Mode Microprocessor Mode Retains status before stop mode RD WR WRL WRH H HLDA BCLK H ALE indeterminate Single chip Mode Does not become a bus control pin I O ports Retains status before stop mode Retains status before stop mo
467. pt Control Register i 0 1 b8 bO Symbol Address After Reset COICR 0217h 0216h 0000h C1ICR 0237h 0236h 0000h Interrupt enable bits 0 Interrupt disabled Each bit corresponds with a slot with the same 1 Interrupt enabled number Enabled disabled of successful transmission interrupt or successful reception interrupt can be selected 1 This register can not be set in CAN reset initialization mode of the CAN module CANi Extended ID Register i 0 1 b8 bo Symbol Address After Reset COIDR 0219h 0218h 0000h C1IDR 0239h 0238h 0000h Extended ID bits 0 Standard ID Each bit corresponds with a slot with the same 1 Extended ID number Selection of the ID format that each slot handles 1 This register can not be set in CAN reset initialization mode of the CAN module Figure 19 9 COSSTR C1SSTR Registers COICR C1ICR Registers and COIDR C1IDR Registers Rev 2 00 Nov28 2005 page 231 of 378 31 NE SAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module CANI Configuration Register i 0 1 b cbo Do 07 IAS bi pO Symbol Address After Reset COCONR 021Ah Indeterminate C1CONR 023Ah Indeterminate Divide by 1 of fCAN Divide by 2 of fCAN Divide by 3 of fCAN ooog Oooog 2oo amp Zz 2o o2o8 Prescaler Division Ratio Select Bits Divide by 15 of CAN Divide by 16 of fCAN
468. put Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 40 A D Trigger Input Standard Min Max tc aD ADTRG Input Cycle Time trigger able minimum 1500 tw ADL ADTRG Input LOW Pulse Width 200 Table 22 41 Serial Interface Symbol Parameter Standard Min Max Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Es 22 42 External Interrupt INTi Input t Symbol oo Pam Eee Unit oo Pam Eee Unit anan Unit tw INH INTi Input HIGH Pulse Width twiINL INTi Input LOW Pulse Width Rev 2 00 Nov 28 2005 page 316 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Switching Characteristics VCC z 3 3V Referenced to VCC 3 3V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 43 Memory Expansion Mode and Microprocessor Mode for setting with no wait Measuring Standard condition Min Max Address output delay time Figure 22 12 Address output hold time refers to BCLK 4 Address output hold time refers to RD 0 Address output hold time refers to WR NOTE 1 Chip select output delay time Lk cs Chip select output
469. put at the falling edge of the transfer clock or in the low state if the SMi4 bit 1 transmit data output at the rising edge of the transfer clock Figure 15 41 SOUTi s Initial Value Setting Rev 2 00 Nov28 2005 page 201 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter 16 A D Converter The microcomputer contains one A D converter circuit based on 10 bit successive approximation method configured with a capacitive coupling amplifier The analog inputs share the pins with P10 O to P10 7 P9 5 P9 6 PO Oto PO 7 and P2 Oto P2 7 Similarly ADTRG input shares the pin with P9 7 Therefore when using these inputs make sure the corresponding port direction bits are set to 0 input mode When not using the A D converter set the VCUT bit to 0 VREF unconnected so that no current will flow from the VREF pin into the resistor ladder helping to reduce the power consumption of the chip The A D conversion result is stored in the ADi registers bits for ANi ANO i and AN2 i pins i 0 to 7 Table 16 1 shows the performance of the A D converter Figure 16 1 shows the block diagram of the A D converter and Figures 16 2 and 16 3 show the A D converter related registers Table 16 1 A D Converter Performance Method of A D Conversion Successive approximation capacitive coupling amplifier Analog Input
470. put can be fixed high or low when not transferring Figure 15 41 shows the timing chart for setting an SOUTi initial value and how to set it NOTE 1 When CANO function is selected P7 4 P7 5 and P8 O0 can be used as input output pins for SI O4 When CANO function is not selected P9 5 P9 6 and P9 7 can be used as input output pis for SI O4 Example When H selected for SOUTi initial value Setting of the initial value of SOUTi Signal written to output and starting of a pegian transmission reception SMi7 bit Set the SMi3 bit to 0 SOUTi pin functions as an I O port SMi3 bit Set the SMi7 bit to 1 SOUTI internal SOUTi initial value H SOUTI output Portoutput Set the SMi3 bit to 1 inae aa SOUTi pin functions as SOUTi output initial value to H l O port SOUTI from the SOUTi pin Write to the SiTRR register i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in the SiC register are set as follows SMi2 0 SOUTi output SMi5 0 LSB first i j j e o exon cee Serial transmit reception starts 1 Setting the SOUTi Port selection switching i H level is output NOTES 1 If the SMi6 bit 1 internal clock or if the SMi2 bit 1 SOUTi output disabled this output goes to the high impedance state 2 SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4 bit in the SiC register O transmit data out
471. puts 5 With external clock input to XIN pin 6 If the PMO7 bit in the PMO register is set to 1 BCLK not output connect this pin to VCC via a resistor pulled high 7 The ports P11 to P14 are only in the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PURS register to 0 P11 to P14 unusable without causing any problem Rev 2 00 Nov28 2005 page 258 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports Microcomputer Microcomputer Port PO to P14 Input mode Port P6 to P14 Input mode except for P8_5 2 i except for P8_5 2 i Input mode Input mode Output mode Output mode Port P4 5 CS to P4 7 CS3 In single chip mode In memory expansion mode or in microprocessor mode 9 NOTES 1 If the PMO7 bit in the PMO register is set to 1 BCLK not output connect this pin to VCC via a resistor pulled high 2 The ports P11 to P14 are only in the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PURS register to 0 P11 to P14 unusable without causing any problem 3 Not available in T V ver Figure 20 12 Unassigned Pins Handling Rev 2 00 Nov28 2005 page 259 of 378 RENESAS REJ09B0124 0200 Under development This docum
472. r 40 to 85 C unless otherwise specified 2 The mean output current is the mean value within 100 ms 3 The total loteak for ports PO P1 P2 P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 80mA max The total lot peak for ports P3 P4 P5 P6 P7 P8 0 to P8 4 P12 and P13 must be 80mA max The total lou pea for ports PO P1 and P2 must be 40mA max The total lou pea for ports P3 P4 P5 P12 and P13 must be 40mA max The total lou pea for ports P6 P7 and P8 0 to P8 4 must be 40mA max The total lou pea for ports P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 40mA max 4 P11 to P14 are only in the 128 pin version Rev 2 00 Nov28 2005 page 329 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Table 22 48 Recommended Operating Conditions 2 Standard Typ Parameter Main Clock Input Oscillation No Wait Flash Memory VCC 4 2 to 5 5V Frequency 9 Sub Clock Oscillation Frequency On chip Oscillation Frequency PLL Clock Oscillation Frequency CPU Operation Clock VCC 4 2 to 5 5V PLL Frequency Synthesizer Stabilization Wait Time f rippte Power Supply Ripple Allowable Frequency VCC V P P ripple Power Supply Ripple Allowable Amplitude Voltage VCC 5V Vec awatl Power Supply Ripple Rising Falling Gradient VCC 5V NOTES
473. r SOTIC 0017h UARTO Receive Interrupt Control Register SORIC UART1 Transmit Interrupt Control Register S1TIC UARTI Receive Interrupt Control Register S1RIC imer AO Interrupt Control Register imer A1 Interrupt Control Register imer A2 Interrupt Control Register NT7 Interrupt Control Register imer A3 Interrupt Control Register TASIC 001Eh Processor Mode Register 2 NT6 Interrupt Control Register INT6IC imer A4 Interrupt Control Register TA4IC imer BO Interrupt Control Register TBOIC DMAO Source Pointer 1 06 Interrupt Control Register S6IC 0022h imer B1 Interrupt Control Register TB1IC 0023h INT8 Interrupt Control Register INT8IC 0024h Timer B2 Interrupt Control Register TB2IC IL INTO Interrupt Control Register INTOIC DMAO Destination Pointer INT1 Interrupt Control Register INT1IC 0026h INT2 Interrupt Control Register INT2IC 0027h 0028h Oscillation Stop Detection Register 001Bh Chip Select Expansion Control Register 001Ch PLL Control Register 0 DMAO Transfer Counter CANO Message Box 0 Identifier DLC 002Ch DMAO Control Register DMOCON CANO Message Box 0 Data Field DMA1 Source Pointer 0032h 0033h 0034h CANO Message Box 0 Time Stamp DMA1 Destination Pointer 0036h 0037h 0038h
474. r Support Register C1AFS CANO Message Control Register 6 COMCTL6 CANO Message Control Register 7 COMCTL7 CANO Message Control Register 8 COMCTL8 233 233 CANO Message Control Register 9 COMCTL9 CANO Message Control Register 10 COMCTL10 CANO Message Control Register 11 COMCTL11 CANO Message Control Register 12 COMCTL12 CANO Message Control Register 13 COMCTL13 CANO Message Control Register 14 COMCTL14 CANO Message Control Register 15 COMCTL15 02T1h CANO Control Register COCTLR ae CANO Status Register COSTR CANO Acceptance Filter Support Register COAFS m CANO Slot Status Register 0216h 0217h CANO Interrupt Control Register 0219h CANO Configuration Register 021Ch CANO Receive Error Count Register CORECR 021Dh CANO Transmit Error Count Register COTECR 021Eh Peripheral Clock Select Register PCLKR CANO Time Stamp Register CoTSR CANO 1 Clock Select Register CCLKR CAN1 Message Control Register 0 C1MCTLO CAN1 Message Control Register 1 C1MCTL1 CAN1 Message Control Register 2 C1MCTL2 CAN1 Message Box 0 Identifier DLC CAN1 Message Control Register 3 C1MCTL3 CAN1 Message Control Register 4 C1MCTL4 CAN1 Message Control Register 5 C1MCTL5 CAN1 Message Control Register 6 C1MCTL6 CAN1 Message Control Register 7 C1MCTL7 CAN1 Message Control Register 8 C1MCTL8 CAN1 Message Control Register 9 C1MCTL
475. r development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM P8_2 to P8_4 P525 P7 7 P9 7 P11 0 P11 1 P11 5 P11 7 P13_5 to P13 7 2 Figure20 2 I O Ports 2 Pull up selection Direction register 20 Programmable l O Ports E e hd Data bus Output Port latch xis Switching between CMOS and qe Nch Input to respective peripheral functions Pull up selection Direction register lt Data bus Port latch Input to respective peripheral functions Pull up selection Direction register lt Data bus Port latch Input to respective peripheral functions f Qc Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 P11 to P13 are only in the 128 pin version Rev 2 00 Nov 28 2005 page 250 of 378 REJO9BO0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Pull up selection Direction register 20 Programmable l O Ports i lt
476. r development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Interrupt Request Cause Select Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol IFSRO Bit Symbol IFSROO IFSRO1 IFSRO2 IFSROS IFSRO4 IFSRO5 IFSRO6 IFSRO7 Address 01DEh Bit Name Interrupt Request Cause Select Bit 1 Interrupt Request Cause Select Bit 2 Interrupt Request Cause Select Bit 3 Interrupt Request Cause Select Bit 4 Interrupt Request Cause Select Bit 5 Interrupt Request Cause Select Bit 6 Interrupt Request Cause Select Bit 7 Interrupt Request Cause Select Bit 8 10 Interrupt After Reset 00h Function O CAN1 successful transission 1 SI O3 0 A D conversion 1 Key input O CANO 1 wake up or error 1 CANO wake up error or RW CAN1 wake up error 0 CAN1 successful reception RW 1 SI 04 0 Timer B5 1 SI O5 0 Timer BO 1 SI O6 0 Timer B3 1 UARTO bus collision detection 0 Timer B4 1 UART1 bus collision detection 1 When the IFSR16 bit in the IFSR1 register 0 CAN1 successful transmission and SI OS share the vector and interrupt control register When using the CAN1 successful transmission interrupt set the IFSROO bit to 0 CAN1 successful transmission When using SI O3 interrupt set the IFSROO bit to 1 SI O3 2 When the PCLK6 bit in the PCLKR register 0 A D conversion and key input share
477. r development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 1 Mode Description 16 1 1 One shot Mode In one shot mode analog voltage applied to a selected pin is A D converted once Table 16 2 lists the specifications of one shot mode Figure 16 4 shows the ADCONO and ADCON1 registers in one shot mode Table 16 2 One shot Mode Specifications Specification Function The CH2 to CHO bits in the ADCONO register the ADGSEL1 to ADGSELO bits in the ADCON register and the OPA1 to OPAO bits in the ADCON1 register select a pin Analog voltage applied to the pin is converted to a digital code once A D Conversion Start Condition e When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Completion of A D conversion If a software trigger is selected the ADST bit is set to 0 A D conversion halted e Set the ADST bit to 0 Interrupt Request Generation Timing Completion of A D conversion Analog Input Pin Select one pin from ANO to AN7 ANO 0 to ANO 7 AN2 0 to AN2 7 ANEXO to ANEX1 Reading of Result of A D Converter Read one of the ADO to AD7 registers that corresponds to the selected p
478. r na ee Desc pene cts E ence pa nter REEL NES U quiae radeg d ku NESRETNA EESE 208 16 1 3 Single Sweep Mode nte e Wee tip e a dx eet duel ceed ea FERE deg axe exer ANRE 210 16 1 4 Repeat Sweep Mode O 1 oed el i Rea reine FER en b c hone 212 16 1 5 Repeat Sweep Mode 1 sssssssssssssssseeesesen nennen nen nennen nennen nennen entren ses nnns enters nennen enn 214 102 FUICU ON m P EIE 216 16 2 1 Resolution Select FUNCOM cicer oco Gol ene etn Milan ean 216 16 2 2 Sample and Hold s src tence eeeeeeeeeeeeeeaeee tease nennen enne annaia Eanna aasan Eai Baaada inna 216 16 2 3 Extended Analog Input PINS wedi oiii e aor em idee bx A 216 16 2 4 External Operation Amplifier Op Amp Connection Mode ssssseeeeeeeennees 216 16 2 5 Current Consumption Reducing Function sse eene enne 217 16 2 6 Output Impedance of Sensor under A D Conversion sesssssssseeeeeneeeemeennne 217 IZ DA COnvene m 219 xe ele I e E a E E eee ESE 221 19 CAN Module odes aen mouche rai EET rer UNE 223 19 1 CAN Module Related Registers ssssessssssssssseseeeseeeenen nennen entren nnns nennen eerte etes nnne nnne 224 19 171 CAN Message BOX isi asrina a iret Idee cendi eese foa Fosse bus erit Leser eate nidia 224 19 1 2 Acceptance Mask Registers eeesssssssssseeeseeeeeeeeenne nennen nnn nnne nenne nter nnn nntene nnn nnns 224 1
479. r the timer underflows the output polarity of TAIOUT pin is inverted Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 1 2 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers Timers A2 A3 and A4 can count two phase external signals Table 13 2 lists specifications in event counter mode when not processing two phase pulse signal Figure 13 8 shows TAiMR register in event counter mode when not processing two phase pulse signal Table 13 3 lists specifications in event counter mode when processing two phase pulse signal with the timers A2 A3 and A4 Figure 13 9 shows TA2MR to TA4MR registers in event counter mode when processing two phase pulse signal with the timers A2 A3 and A4 Table 13 2 Specifications in Event Counter Mode when not processing two phase pulse signal Count Source External signals input to TAiIN pin effective edge can be selected in program Timer B2 overflows or underflows Timer Aj overflows or underflows Timer Ak overflows or underflows Count Operation Up count or down count can be selected by external signal or program When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divided Ratio 1
480. r to 0 falling edge INT6IC to INT8IC registers are in the 128 pin version Set the POL bit in the S3IC register to 0 falling edge when the IFSROO bit in the IFSRO register 1 and the IFSR16 bit in the IFSR1 register 0 SI O3 selected Set the POL bit in the S4IC register to 0 falling edge when the IFSROS bit in the IFSRO register 1 and the IFSR17 bit in the IFSR1 register 0 SI O4 selected Use the IFSROS bit in the IFSRO register and the IFSR17 bit in the IFSR1 register to select Use the IFSROO bit in the IFSRO register and the IFSR16 bit in the IFSR1 register to select Use the IFSR20 bit in the IFSR2 register to select The INT7IC register is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 Use the IFSR21 bit in the IFSR2 register to select The INT6IC register is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 Use the IFSR22 bit in the IFSR2 register to select The INT8IC register is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 O Figure 10 4 Interrupt Control Registers 2 Rev 2 00 Nov 28 2005 page 87 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 5 1 I Flag The I flag enables or disables the maskable interrupt Setting the flag to
481. rameter PO 0 to PO 7 P1 Oto P1 7 P2_0 to P2 7 lou 5mA Measuring Condition Symbol Von HIGH Output Voltage P3 0 to P3 7 P4 0 to P4 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11_0 to P11 7 P12_0 to P12 7 P13_0 to P13 7 P14 0 P14 1 HIGH Output Voltage PO 0 to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 to P3 7 P4 O0 to PA 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10_0 to P10_7 P11 0toP11 7 P12 0to P12 7 P13 Oto P13 7 P14 0 P14 1 lon 2004A Vcc 0 3 HIGH Output Voltage XOUT HIGHPOWER lou 1mA LOWPOWER lou 0 5mA HIGH Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied LOW Output Voltage P0_0 to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 Oto P5 7 P6 0 to P6 7 P7_0 to P7 7 P8 O to P8 4 P8 6 P8 7 P9_0 to P9 7 P10_0 to P10 7 P11 0toP11 7 P12 0to P12 7 P13 OtoP13 7 P14 0 P14 1 lo 5mA LOW Output Voltage PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 Oto P5 7 P6 0 to P6 7 P7 O0 to P7 7 P8 O to P8 4 P8 6 P8 7 P9_0 to P9 7 P10 0 to P10 7 P11 0toP11 7 P12 0toP12 7 P13 OtoP13 7 P14 0 P14 1 lo 200A LOW Output Voltage XOUT HIGHPOWER lo 1mA LOWPOWER l
482. ransfer data Set this bit to 0 when the SMD2 to SMDO bits are set to 010b I2C mode or 110b UART mode 9 bit transfer data Figure 15 7 UOC1 U1C1 Registers and U2C1 Register Rev 2 00 Nov28 2005 page 155 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM UART Transmit Receive Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol UCON UARTO Transmit Interrupt Vons Cause Select Bit 15 Serial Interface After Reset X0000000b Transmit buffer empty TI bit 1 Transmission completed TXEPT bit P UART1 Transmit Interrupt Cause Select Bit Transmit buffer empty TI bit 1 Transmission completed TXEPT bit 1 UARTO Continuous Receive Mode Enable Bit UART1 Continuous Receive Mode Enable Bit Continuous receive mode disabled Continuous receive mode enabled Continuous receive mode disabled Continuous receive mode enabled UART1 CLK CLKS Select Bit 0 ffective when the CLKMD1 bit 1 Clock output from CLK1 Clock output from CLKS1 UART1 CLK CLKS Select Bit 1 1 oOo omio0 o j ojo CLK output is only CLK1 Transfer clock output from multiple pins function selected Separate UARTO CTS RTS Bit O CTS RTS shared pin CTS RTS separated CTSO supplied from the P6 4 pin Nothing is assigned When write set to
483. re 6 4 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode 1 E When PM13 1 and PM10 0 Memory expansion mode Microprocessor mode SFR SFR Internal RAM Internal RAM Reserved area Reserved area External area Memory expansion mode 320 Kbytes Microprocessor mode 832 Kbytes Internal RAM Internal ROM Capacity Address XXXXXh Capacity Address YYYYYh 16 Kbytes 192 Kbytes Dooooh 20 Kbytes 256 eR 31 Kbytes 384 Kbytes A0000h 5i2Kbytes 80000 NOTE 1 Not available memory expansion and microprocessor modes in T V ver Figure 6 5 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode 2 Rev 2 00 Nov28 2005 page 43 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode lll When PM13 0 and PM10 1 Memory expansion mode Microprocessor mode SFR SFR Internal RAM Internal RAM Reserved area Reserved area LEN 08000h Reserved area 2 Reserved area 2 XXXXXh External area External area Memory expansion mode 320 Kbytes rb beca mode 832 Kbytes Internal ROM Capacly Capacity 16 Kbytes 03FFFh 192 Kbytes 20 Kbytes 03FFFh 256 Kbytes 31 Kbytes 384Kbytes Dooooh 512 Kbytes NOTES 1 If the PM13 bit in the PM1 register is set to 0 192 Kbytes of the internal ROM can be used 2 For the flash memory v
484. re subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version Full status check FMRO6 1 and Command 1 Execute the clear status register command and set the SR4 and SR5 FMRO7 1 sequence error bits to 0 completed as expected 2 Rewrite command and execute again 1 Execute the clear status register command and set the SR5 bit to 0 2 Execute the lock bit read status command Set the FMRO2 bit in the FMRO register to 1 lock bit disabled if the lock bit in the block where the error occurred is set to 0 locked 3 Execute the block erase or erase all unlocked block command again 4 Execute 1 2 and 3 at least 3 times until an erase error is not generated NOTE If similar error occurs that block cannot be used If the lock bit is set to 1 unlocked in 2 above that block cannot be used FMRO6 0 When a program operation is executed 1 Execute the clear status register command and set the SR4 bit to 0 completed as expected 2 Execute the read lock bit status command and set the FMRO2 bit to 1 if the lock bit in the block where the error occurred is set to 0 8 Execute the program command again NOTE When a similar error occurs that block cannot be used If the lock bit is set to 1 in 2 above that block cannot be used When a lock bit program operation is executed 1 Execute the clear status register command and set the SR4 bit to 0
485. receiver Each slot contains an individual ID data length code a data field 8 bytes and a time stamp Acceptance filter This block performs filtering operation for received messages For the filtering operation the CiGMR register i 0 1 the CILMAR register or the CILMBR register is used 16 bit timer Used for the time stamp function When the received message is stored in the message memory the timer value is stored as a time stamp Wake up function CANO 1 wake up interrupt request is generated by a message from the CAN bus Interrupt generation function The interrupt requests are generated by the CAN module CANi successful reception interrupt CANi successful transmission interrupt CANO 1 error interrupt and CANO 1 wake up interrupt Rev 2 00 Nov 28 2005 page 223 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 1 CAN Module Related Registers The CANi i 0 1 module has the following registers 19 1 1 CAN Message Box A CAN module is equipped with 16 slots 16 bytes or 8 words each Slots 14 and 15 can be used as Basic CAN Priority of the slots The smaller the number of the slot the higher the priority in both transmission and reception A program can define whether a slot is defined as transmitter or receiver 19 1 2 Acceptance Mask Registers A CAN module is equipped with 3 mask
486. register NOTE 1 is added Table 19 2 Examples of Bit rate NOTE 2 is added 19 15 1 Reception 5 is partly revised 20 Programmable I O Ports 8th line Each pin functions is partly revised Last sentence When using is added NOTE 1 is added 20 1 PDi Register 4 th line The sentence During memory expansion is added NOTE 1 is added 20 2 Pi Register 9 th line The sentence During memory expansion is added NOTE 1 is added 20 3 PURj Register e 5 th line The sentence However the pull up is added NOTE 1 is added Figure20 7 PDi Registers upper NOTE 2 is added Figure20 8 Pi Registers upper NOTE 2 is added Figure20 9 PURO Register upper NOTE 1 is added Figure20 9 PUR1 Register middle NOTES 1 2 and 3 are added C 4 REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Date Summary Table 20 3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Normal ver only is added Figure 20 12 Unassigned Pins Handling Figure of memory expansion mode or microprocessor mode is added NOTES 1 and 3 are added Table 21 2 Flash Memory Rewrite Modes Overview Operation Mode of CPU Rewrite Mode is revised NOTE2 is revised NOTE 4 is added 21 1 Memory Map 2nd sentence The user ROM is revised Figure 21 2 ROMCP Register is revised Table 21 3 EWO Mode and EW1 Mode Flash Memory Status Detection of EWO Mode is revised NOTES 1a
487. register Two cycles later the CRC code for 80C4h i e 8250h has its bit positions reversed to become 0A41h which is stored in the CRCD register bO CRCD register e Details of CRC operation As shown in 3 above bit position of 01h 000000015 written to the CRCIN register is inversed and becomes 10000000b Add 1000 0000 0000 0000 0000 0000b as 10000000b plus 16 digits to 0000 0000 0000 0000 0000 0000b as 0000 0000 0000 0000b plus 8 digits as the default value of the CRCD register to perform the modulo 2 division Modulo 2 operation is 1000 1000 Dat operation that complies 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 4 Pata with the law given below 1000 1000 0001 0000 1 ox Generator polynomial 1000 0001 0000 1000 0 0 is 24 1000 1000 0001 0000 1 140 1 1001 0001 1000 1000 A 1 120 CRC code Se 0001 0001 1000 1001b 1189h the remainder 1001 0001 1000 1000b 9188h with inversed bit position can be read from the CRCD register When going on to 4 above 23h 0010001 1b written in the CRCIN register is inversed and becomes 11000100b Add 1100 0100 0000 0000 0000 0000b as 11000100b plus 16 digits to 1001 0001 1000 1000 0000 0000b as 1001 0001 1000 1000b plus 8 digits as a remainder of 3 left in the CRCD register to perform the modulo 2 division 0000 1010 0100 0001b 0A41h the remainder with inversed bit position can be read from CRCD register Figure 18 3 CRC Calcu
488. release ta w s Low Power Dissipation Mode CPU clock 5 mlllll Wait Mode Release Time Figure 22 2 Power Supply Circuit Timing Diagram Rev 2 00 Nov28 2005 page 298 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Timing Requirements VCC 25V Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 22 11 External Clock Input XIN Input Standard Min Max Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min Max lacRp o8 Data input access time for setting with no wait NOTE 1 tace RD DB Data input access time for setting with wait NOTE 2 Parameter laRD o amp Data input access time when accessing multiplexed bus area NOTE 3 tsu DB RD Data input setup time tsurov scLK RDY input setup time tsuHoLo scik HOLD input setup time tn RD D8 Data input hold time inecucaoy RDY input hold time tngcuuoto HOLD input hold time NOTES 1 Calculated according to the BCLK frequency as follows 0 5 X 10 4 f BCLK Ins 2 Calculated according to the BCLK frequency as follows n 0 5 x
489. ress match interrupt is not available since the CPU tries to read data in the flash memory 21 3 4 4 Interrupts EW1 Mode Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt e The NMI interrupt is available since the FMRO and FMR1 registers are forcibly reset when the interrupt request is generated Allocate the jump address for the interrupt service routine to the fixed vector table Flash memory rewrite operation is aborted when the NMI interrupt request is generated Execute the rewrite program again after exiting the interrupt service routine 21 3 4 5 How to Access To set the FMRO1 FMRO02 or FMR11 bit to 1 write 1 after first setting the bit to 0 Do not generate an interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1 Set the bit while an H signal is applied to the NMI pin 21 3 4 6 Rewriting in User ROM Area EWO Mode The supply voltage drops while rewriting the block where the rewrite control program is stored the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten If this error occurs rewrite the user ROM area while in standard serial I O mode or parallel I O mode or CAN I O mode 21 3 4 7 Rewriting in User ROM Area EW1 Mode Avoid rewriting any block in whic
490. riod 3 x 62 5 ns x 4 750 ns Example 4 Condition XIN 16 MHz CCLK Divided by 8 3fCAN period 3x 62 5 ns x 8 1 5 us Example 5 Condition XIN 16 MHz CCLK Divided by 16 3fCAN period 3x 62 5 ns x 16 3 us Rev 2 00 Nov28 2005 page 362 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution fCAN CPU read signal Updating period of CAN module CPU reset signal CiSTR register b8 State Reset bit 0 CAN operation d 1 CAN Bosniak X When the CAN module s State Reset bit updating period matches the CPU s read ization mode period it does not enter reset mode for the CPU read has the higher priority i2 0 1 Figure 23 5 When Updating Period of CAN Module Matches Access Period from CPU Waittime CPU read signal Doro rorod Updating period of the CAN module CPU reset signal CiSTR register Oo b8 Reset state flag 0 CAN operation To eevee O Updated without fail in period of 3fCAN ization mode i 2 0 1 Figure 23 6 With a Wait Time of 3TCAN Before CPU Read CPU read signal AfCAN Updating period of the CAN module f CPU reset signal CiSTR register b8 State Reset bit 0 CAN operation mode X When the CAN module s State Reset bit updating period matches the CPU s read 1 CAN reset initial period it
491. roduct data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts pro grams and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons It is therefore recommended that custom ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor poration product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all informa tion as a total system before making a final decision on the applicability of the information and products Renesas Technology Corporation assumes no responsibility for any dam age liability or other los
492. rotected 1 Write enabled Enable write to PD7 PD9 S3C S4C S5C S6C registers 2 0 Write protected 1 Write enabled 1 Bero m Nothing is assigned When write set to 0 When read their contents are indeterminate 1 The PRC2 bit is set to 0 by writing to any address after setting it to 1 Other bits are not set to 0 by writing to any address and must therefore be set in a program 2 The S5C and S6C registers are only in the 128 pin version Figure 9 1 PRCR Register Rev 2 00 Nov28 2005 page 80 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 Interrupt 10 1 Type of Interrupts Figure 10 1 shows the types of interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Software Non maskable interrupt Interrupt NMI DBC 9 Oscillation stop and re oscillation detection Special Watchdog timer Non maskable interrupt Hardware Single step Address match Peripheral function Maskable interrupt NOTES 1 The peripheral functions in the microcomputer are used to generate the peripheral interrupt 2 Do not normally use this interrupt because it is provided exclusively for use by development tools Figure 10 1 Interrupts Maskable Interrupt An interrupt which can be enabled disabled
493. rrupt Control Register DMOIC XXXXXO000b DMA1 Interrupt Control Register DM1IC XXXXX000b CANO 1 Error Interrupt Control Register CO1ERRIC XXXXX000b A D Conversion Interrupt Control Register ADIC Key Input Interrupt Control Register KUPIC XXXXX000b UART2 Transmit Interrupt Control Register S2TIC XXXXX000b UART2 Receive Interrupt Control Register S2RIC XXXXX000b UARTO Transmit Interrupt Control Register SOTIC XXXXX000b UARTO Receive Interrupt Control Register SORIC XXXXX000b UART1 Transmit Interrupt Control Register S1TIC XXXXX000b UART1 Receive Interrupt Control Register S1RIC XXXXX000b Timer AO Interrupt Control Register TAOIC XXXXX000b Timer A1 Interrupt Control Register TA1IC XXXXX000b Timer A2 Interrupt Control Register TA2IC INTZ Interrupt Control Register INT7IC XX00X000b Timer A3 Interrupt Control Register TASIC INT6 Interrupt Control Register INT6IC XX00X000b Timer A4 Interrupt Control Register TA4IC XXXXX000b Timer BO Interrupt Control Register TBOIC SI O6 Interrupt Control Register S6IC XXXXX000b Timer B1 Interrupt Control Register TB1IC INT8 Interrupt Control Register INT8IC XX00X000b Timer B2 Interrupt Control Register TB2IC XXXXX000b INTO Interrupt Control Register INTOIC XX00X000b INT1 Interrupt Control Register INT1IC XX00X000b INT2 Interrupt Control Register INT2IC XX00X000b 0060h XXh 0061h XXh Sgr CANO Message Box 0 Identifier DLC 0064h XXh 0065h XXh 0066h XXh 0067h XXh 0068h XXh L 00696 CANO Message Box 0
494. rrupt Request When start or stop condition is detected acknowledge undetected and acknowledge Generation Timing detected Error Detection Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 8th bit of the next data Select Function Arbitration lost Timing at which the ABT bit in the UiRB register is updated can be selected SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable Clock phase setting With or without clock delay selectable i Oto2 NOTES 1 When an external clock is selected the conditions must be met while the external clock is in the high state 2 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in the SiRIC register does not change Rev 2 00 Nov 28 2005 page 175 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM STSPSEL 1 Delay o PS STSPSEL 0 ACKC 1 TACKC 0 Noise Filter Start condition detection Stop condition detection Falling edge detection hes Start and stop condition generation block SDA STSP SCL STSP IICM2 1 Transmission register IICM 1 and IICM2 0 IICM2 1 Eg IICM 1 and IICM2 0 b Q peu n PT 9th bit ACK UARTi 9th bit falling edge SWC 15 Serial Int
495. rs contain bits that will result in unknown data when read and Table 23 2 lists the instruction table for read modify write Table 23 1 Registers Contain Bits that Will Result in Unknown Data When Read Address Timer A1 1 Register 01C3h 01C2h Timer A2 1 Register 01C5h 01C4h Timer A4 1 Register 01C7h 01C6h Dead Time Timer 01CCh Timer B2 Interrupt Occurrences Frequency Set Counter 01CDh SI O6 Bit Rate Generator 01D9h SI O3 Bit Rate Generator 01E3h SI O4 Bit Rate Generator 01E7h SI O5 Bit Rate Generator 01EBh UART2 Bit Rate Generator 01F9h UART2 Transmit Buffer Register 01FBh 01FAh Up Down Flag 0384h Timer AO Register 0387h 0386h Timer A1 Register 0389h 0388h Timer A2 Register 038Bh 038Ah Timer A3 Register 038Dh 038Ch Timer A4 Register 038Fh 038Eh UARTO Bit Rate Generator 03A1h UARTO Transmit Buffer Register O3A3h 03A2h UART1 Bit Rate Generator 03A9h UART1 Transmit Buffer Register OSABh O3AAh NOTES 1 It is affected only in three phase motor control timer function 2 These registers are only in the 128 pin version 3 It is affected only in one shot timer mode and pulse width modulation mode Table 23 2 Instruction Table for Read Modify Write Bit Manipulation BCLR BNOT BSET BTSTC BTSTS Shift RCLC RORC ROT SHA SHL Arithmetic ABS ADC ADCF ADD DEC EXTS INC MUL MULU NEG SBB SUB Logical AND
496. rt P5 Input H or L level signal or open P5_5 EPM input Input L level signal P6_0 to P6_4 P6_6 Input port P6 Input H or L level signal or open P6 5 CLK1 SCLK input Input L level signal P6 7 TXD1 TXD output Input H level signal P7 0to P7 7 Input port P7 Input H or L level signal or open P8 0 to P8 3 P8 6 P8 7 Input port P8 Input H or L level signal or open P8 4 P8 4 Input Input L level signal P8 5 NMI NMI input Connect this pin to VCC1 P9 0to P9 4 P9 7 Input port P9 Input H or L level signal or open P9 5 CRXO CRX input Connect to a CAN transceiver P9 6 CTXO CTX output Connect to a CAN transceiver P10 Oto P10 7 Input port P10 Input H or L level signal or open P11 0to P117 Input port P11 Input H or L level signal or open P12 Oto P12 7 Input port P12 Input H or L level signal or open P13 0to P13 7 Input port P13 Input H or L level signal or open P14 0 P14 1 NOTES Input port P14 Input H or L level signal or open 1 When using CAN I O mode the PO 0 to PO 7 P1 Oto P1 7 pins may become indeterminate while the P8 4 pin is H and the RESET pin is L If this causes a problem apply L to the P8 4 pi
497. s Channel Priority DMAO DMA1 DMAO takes precedence Transfer Unit 8 bits or 16 bits Transfer Address Direction forward or fixed The source and destination addresses cannot both be in the forward direction Transfer Mode Single Transfer Transfer is completed when the DMAi transfer counter underflows after reaching the terminal count Repeat Transfer When the DMAi transfer counter underflows it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is continued with it DMA Interrupt Request Generation Timing When the DMAi transfer counter underflowed DMA Start Up Data transfer is initiated each time a DMA request is generated when the The DMAE bit in the DMAiCON register 1 enabled DMA Shutdown Single Transfer When the DMAE bit is set to 0 disabled After the DMAi transfer counter underflows Repeat Transfer When the DMAE bit is set to 0 disabled Reload Timing for Forward Address Pointer and Transfer Counter When a data transfer is started after setting the DMAE bit to 1 enabled the forward address pointer is reloaded with the value of the SARi or the DARi pointer whichever is specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register DMA Transfer Cycles i 2 0 1 NOTES Minimum 3 cycles between SFR and
498. s and descriptions used for bit function in each register are shown below 1 2 8 4 5 XXX Register b7 b6 b5 b4 b3 b2 bi bO 1 Address Afte Reset XXX Bit Name Function b1bO 0 0 XXX 2 0 1 XXX 1 0 Do not set a value 11 XXX Nothing is assigned When write set to O A When read its content is indeterminate 3 Reserved Bit 4 Function varies depending on mode of operation 0 XXX 1 XXX Blank Set to 0 or 1 according to the application 0 Setto 0 1 Setto 1 X Nothing is assigned RW Read and write RO Read only WO Write only Nothing is assigned Reserved bit Reserved bit Set to specified value Nothing is assigned Nothing is assigned to the bit concerned As the bit may be use for future functions set to O when writing to this bit Do not set to this value The operation is not guaranteed when a value is set Function varies depending on mode of operation Bit function varies depending on peripheral function mode Refer to respective register for each mode Follow the text in each manual for binary and hexadecimal notations 3 M16C Family Documents The following documents were prepared for the M16C family Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications pin assignments memory maps peripheral specifications electrical char
499. s after reset The operating clock can changes from on chip oscillator clock on chip oscillation oscillating to BCLK by using oscicllation stop re oscillation detection function or setting the CM21 bit in the CM2 register Figure 23 1 Operation Timing at Oscillation Stop Re oscillation Stop Detection at Wait Mode when moving out of wait mode by using INTO interrupt XIN fRING 1 p FLU UTI LULL LATI CPU N Oscillation stop re oscillation ormal processing see Normal processin operation p g detection interrupt request p g XIN stops NOTE 1 This clock is generated by the on chip oscillator It is not supplies after reset The operating clock can changes from on chip oscillator clock on chip oscillation oscillating to BCLK by using oscicllation stop re oscillation detection function or setting the CM21 bit in the CM2 register Figure 23 2 Operation Timing at Oscillation Stop Re oscillation Stop Detection at Normal Processing Rev 2 00 Nov 28 2005 page 344 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 7 Protection Set the PRC2 bit to 1 write enabled and then write to any address and the PRC2 bit will be set to 0 write protected The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1 Make sure n
500. s contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 7 2 7 HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit When the input on HOLD pin is pulled low the microcomputer is placed in a hold state after the bus access then in process finishes The microcomputer remains in a hold state while the HOLD pin is held low during which time the HLDA pin outputs a low level signal Table 7 5 shows the microcomputer status in the hold state Bus using priorities are given to HOLD DMAC and CPU in order of decreasing precedence see Figure 7 5 Bus using Priorities However if the CPU is accessing an odd address in word units the DMAC cannot gain control of the bus during two separate accesses HOLD DMAC CPU Figure 7 5 Bus using Priorities Table 7 5 Microcomputer Status in Hold State BCLK Output AO to A19 DO to D15 CSO to CS3 RD WRL WRH High impedance WR BHE 1 O Ports PO P1 P3 P4 High impedance P6 to P10 Maintains status when hold signal is received HLDA Output L Internal Peripheral Circuits ON but watchdog timer stops ALE Signal Undefined NOTES 1 When I O port function is selected 2 The watchdog timer does not stop when the PM22 bit in the PM2 register is set to 1 the count source for the watchdog timer is the on chip oscillator clock 7 2 8 BCLK Output If the PMO7 bit in th
501. s document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 2 1 Timer Mode In timer mode the timer counts a count source generated internally Table 13 6 lists specifications in timer mode Figure 13 18 shows TBiMR register in timer mode Table 13 6 Specifications in Timer Mode Specification Count Source f1 f2 f8 f32 fC32 Count Operation Down count When the timer underflows it reloads the reload register contents and continues counting Divide Ratio 1 n 1 n set value of the TBi register 0000h to FFFFh Count Start Condition Set the TBiS bit to 1 start counting Count Stop Condition Set the TBiS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TBilN Pin Function I O port Read from Timer Count value can be read by reading the TBi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TBi register is written to both reload register and counter When counting after 1st count source input Value written to the TBi register is written to only reload register Transferred to counter when reloaded next i Oto5 NOTE 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Timer Bi Mode Register i 0 to 5 eee et
502. s for the acceptance filter e CANI global mask register i 0 1 CIGMR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slots 0 to 13 e CANI local mask A register CILMAR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slot 14 e CANI local mask B register CILMBR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slot 15 19 1 3 CAN SFR Registers e CANi message control register j i 0 1 j O to 15 CIMCTLj register 8 bits X 16 Control of transmission and reception of a corresponding slot e CANI control register CiICTLR register 16 bits Control of the CAN protocol e CANi status register CiSTR register 16 bits Indication of the protocol status e CANI slot status register CISSTR register 16 bits Indication of the status of contents of each slot e CANI interrupt control register CilCR register 16 bits Selection of interrupt enabled or disabled for each slot e CANI extended ID register CiIDR register 16 bits Selection of ID format standard or extended for each slot e CANi configuration register CICONR register 16 bits Configuration of the bus timing e CANi receive error count register CIRECR register 8 bits Indication of the error status of the CAN module in reception the counter value is incremented or decremented according to the error occurrence e CANi transmit err
503. s is retained If the block erase or erase all unlocked block command is executed while the FMRO2 bit is set to 1 the target block or all blocks are erased regardless of lock bit status The lock bit status of each block are set to 1 after an erase operation is completed Refer to 21 3 5 Software Commands for details on each command 21 3 7 Status Register SRD Register The status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected The FMROO FMRO6 and FMRO7 bits in the FMRO register indicate status register states Table 21 5 shows the status register In EWO mode the status register can be read when the followings occur Any even address in the user ROM area is read after writing the read status register command Any even address in the user ROM area is read from when the program block erase erase all unlocked block or lock bit program command is executed until when the read array command is executed 21 3 7 1 Sequencer Status SR7 and FMROO Bits The sequence status indicates the flash memory operation state It is set to 0 while the program block erase erase all unlocked block lock bit program or read lock bit status command is being executed otherwise it is set to 1 21 3 7 2 Erase Status SR5 and FMR07 Bits Refer to 21 3 8 Full Status Check 21 3 7 3 Program Status SR4 and FMRO6 Bits Refer to 21 3 8 Full Status Check Rev 2 00 No
504. s operate using sophisticated instructions featuring a high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Being equipped with two CAN Controller Area Network modules in M16C 6N Group M16C 6NK M16C 6NM the microcomputer is suited to car audio and industrial control systems The CAN modules comply with the 2 0B specification In addition this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability makes it suitable for control of various OA and communication equipment which requires high speed arithmetic logic operations 1 1 Applications Car audio and industrial control systems other Normal ver product Automotive industrial control systems and other automobile other T V ver product Rev 2 00 Nov28 2005 page 1 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 2 Performance Outline Tables 1 1 and 1 2 list a performance outline of M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 1 Performance Outline of M16C 6N Group 100 pin Version M16C 6NK Number of Basic Instructions Performance Normal ver T V ver 91 instructions Minimum Instruction Execution Time 41 7ns f BCLK 24MHz 1 1 prescaler without software wait 50 0ns f BCLK 20MHz 1 1 prescaler w
505. s resulting from the information contained herein Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten tially at stake Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product con tained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be im ported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein How to Use This Manual 1 Introduction This hardware manual provides detailed information on the M16C 6N Group M16C 6NK M16C 6NM of microcomputers Users are expected to have basic knowledge of electric circuits logical circuits and microcomputers 2 Register Diagram The symbol
506. s to INVCO 01XX110Xb and INVC1 010XXX00b X varies depending on each system The examples of PWM output change are Default value of the IDBO and IDB1 registers DUO 0 DUBO 1 DU1 1 DUB1 1 They are changed to DUO 1 DUBO 0 DU1 1 DUB1 1 by the timer B2 interrupt Figure 14 10 Sawtooth Wave Modulation Operation Rev 2 00 Nov28 2005 page 148 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 Serial Interface Serial interface is configured with 7 channels UARTO to UART2 and SI O3 to SI O6 NOTE 1 100 pin version supports 5 channels UARTO to UART2 SI O3 SI O4 128 pin version supports 7 channels UARTO to UART2 SI O3 to SI O6 15 1 UARTI i 0 to 2 UAHRTi each have an exclusive timer to generate a transfer clock so they operate independently of each other Figures 15 1 to 15 3 show the block diagram of UARTIi Figure 15 4 shows the block diagram of the UARTi transmit receive UARTI has the following modes e Clock synchronous serial I O mode e Clock asynchronous serial I O mode UART mode e Special mode 1 lC mode Special mode 2 Special mode 3 Bus collision detection function IE mode Special mode 4 SIM mode UART2 Figures 15 5 to 15 10 show the UARTi related registers Refer to tables listing each mode for register setting Rev 2 00 Nov28 2005 page 149 of 378
507. sabled 2 Set the RE bit in the UiC1 register to 1 reception enabled e Resetting the UiTB register i O to 2 1 Set the SMD2 to SMDO bits in the UiMR register to 000b serial interface disabled 2 Set the SMD2 to SMDO bits in the UiMR register to 001b 101b 110b 3 1 transmission enabled is written to the TE bit in the UiC1 register regardless of the TE bit 15 1 2 3 LSB First MSB First Select Function As shown in Figure 15 19 use the UFORM bit in the UiCO register to select the transfer format This function is valid when transfer data is 8 bit long 1 When the UFORM bit in the UiCO register 0 LSB first CLKi TXDi st Xf Do X D1 X D2 X pa X D4 X D5 X De X Dz X P Y SP RXDi st X Do X D1 X D2 X pa X D4 X ps X pe X Dz X P Y SP 2 When the UFORM bit 1 MSB first CLKi TDi Nsr D7 X DeX DS X D4X pa X D2X D1 X Do X P Y SP Ri sT pz X DeY D5X p4X ps X D2X p1 Y DOX P Y se i Oto2 ST Start bit P Parity bit SP Stop bit NOTE 1 This applies to the case where the register bits are set as follows e CKPOL bit in UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock e UiLCH bit in UiC1 register O no reverse e STPS bit in UIMR register 0 1
508. sabled to reduce the unnecessary current consumption in the chip and set the DAi register to poe to prevent current from flowing into the R 2R resistor ladder Figure 17 2 DACON Register DAO and DA1 Registers DAIE bit DAiregister AVSS D VREF 2 i 0 1 NOTES 1 The above diagram shows an instance in which the DAi register is assigned 2Ah 2 VREF is not related to VCUT bit setting in the ADCON1 register Figure 17 3 D A Converter Equivalent Circuit Rev 2 00 Nov 28 2005 page 220 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CRC Calculation 18 CRC Calculation The Cyclic Redundancy Check CRC operation detects an error in data blocks The microcomputer uses a generator polynomial of CRC CCITT X 6 X X5 1 to generate CRC code The CRC code consists of 16 bits which are generated for each data block in given length separated in 8 bit unit After the initial value is set in the CRCD register the CRC code is set in that register each time one byte of data is written to the CRCIN register CRC code generation for one byte data is finished in two cycles Figure 18 1 shows the block diagram of the CRC circuit Figure 18 2 shows the CRC related registers Figure 18 3 shows the calculation example using the CRC operation Data bus high order CRC code generating circuit x16 4x
509. se circuit MSB LSB conversion circuit SMD2 to SMDO UART 9 bits UART 1 Clock synchronous p 0 UART 7 bits UART 8 bits Clock synchronous type synchronous type 1 Y UiRB register UiTB register UARTi transmit register UART 7 bits Error signal output disable MES No reverse UiERE 1 Error signal output enable Reverse SMD2 to SMDO STPS PRYE IOPOL CKDIR Bits in UiMR register CLK1 to CLKO CKPOL CRD CRS Bits in UiCO register UiERE Bit in UiC1 register Figure 15 4 UARTi Transmit Receive Unit Rev 2 00 Nov28 2005 page 152 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface UARTIi Transmit Buffer Register i 0 to 2 b15 b8 015 b8 Symbol Address bO b7 bo UOTB 03A3h to 03A2h U1TB O3ABh to 03AAh U2TB 01FBh to 01FAh After Reset Indeterminate Indeterminate Indeterminate b8 b0 Transmit data z Nothing is assigned When write set to 0 b15 b9 When read their contents are indeterminate 1 Use the MOV instruction to write to this register UARTIi Receive Buffer Register i 0 to 2 b15 b8 b7 Symbol Address bO b7 bo UORB 03A7h to 03A6h U1RB O3AFh to OSAEh U2RB O1FFh to O1FEh After Reset Indeterminate Indeterminate Indeterminate Receive data D7 to
510. selected input on the CTSi pin L Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in the UiTB register Interrupt Request Generation Timing For transmission one of the following conditions can be selected e The UiIRS bit 0 transmit buffer empty when transferring data from the UiTB register to the UARTi transmit register at start of transmission e The UiIRS bit 21 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception e When transferring data from the UARTi receive register to the UiRB register at completion of reception Error Detection Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select Function i Oto2 NOTES CLK polarity selection Transfer data input output can be selected to occur synchronously with the rising or the falling edge of the transfer clock e LSB first MSB first selection Whether to start sending receiving data beginning with bit O or beginning with bit 7 can be selected Continuous receive mode selection Reception is enabled immediately by reading the UiRB register Switching serial data
511. set to 00h The resistor ladder of the A D converter is not included Also the current lvaer always flows even though VREF may have been set to be unconnected by the ADCON1 register Rev 2 00 Nov28 2005 page 333 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Table 22 53 Flash Memory Version Electrical Characteristics Symbol m Parameter Typ Program and Erase Endurance Word Program Time VCC 5 0V Lock Bit Program Time Block Erase Time 4 Kbyte block 2 VCC 5 0V 8 Kbyte block 32 Kbyte block 64 Kbyte block Erase All Unlocked Blocks Time Flash Memory Circuit Stabilization Wait Time NOTES 1 Referenced to VCC 4 5 to 5 5V Topr 0 to 60 C unless otherwise specified 2 Program and Erase Endurance refers to the number of times a block erase can be performed If the program and erase endurance is n n 100 each block can be erased n times For example if a 4 Kbyte block A is erased after writing 1 word data 2 048 times each to a different address this counts as one program and erase endurance Data cannot be written to the same address more than once without erasing the block Rewrite prohibited 3 n denotes the number of blocks to erase Table 22 54 Flash Memory Version Program Erase Voltage an
512. shes Figure 15 39 SI Oi Operation Timing 15 2 2 CLK Polarity Selection The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock Figure 15 40 shows the polarity of the transfer clock 1 When SMi4 bit in SiC register 0 CLKi NOTE 1 l N SOUTI X Do X D1 X D2 X D3 X D4 X Ds X De X D7 SINi X Do X D1 X D2 X D3 X D4 X Ds X De X D7 2 When SMi4 bit in SiC register 1 CLKi i l NOTE 2 SOUTI X T D1 X D2 X ps X D4 X ps X pe X D7 SINI X Do X D1 X D2 X pa X D4 X Ds X De X D7 i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in the SiC register are set as follows SMI5 0 LSB first SMi6 1 internal clock NOTES 1 When the SMi6 bit 1 internal clock a high level is output from the CLKi pin if not transferring data 2 When the SMi6 bit 1 internal clock a low level is output from the CLKi pin if not transferring data Figure 15 40 Polarity of Transfer Clock Rev 2 00 Nov28 2005 page 200 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 2 3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in the SiC register O external clock the SOUTi pin out
513. ss direction beginning with address 00400h For example a 31 Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh In addition to storing data the internal RAM also stores the stack used when calling subroutines and when interrupts are generated The SFR is allocated to the addresses from 00000h to 003FFh Peripheral function control registers are located here Of the SFR any area which has no functions allocated is reserved for future use and cannot be used by users The special page vector table is allocated to the addresses from FFEOOh to FFFDBh This vector is used by the JMPS or JSRS instruction For details refer to M16C 60 M16C 20 M16C Tiny Series Software Manual In memory expansion and microprocessor modes some areas are reserved for future use and cannot be used by users Use T V ver in single chip mode The memory expansion and microprocessor modes cannot be used 00000h SFR 00400h Internal RAM XXXXXh m Internal ROM 3 OFFFFh data area 10000h External area 28000h External area Single step 80000h m H d Fa detection watchdog timer YYYYYh n DBC Int ROM i nternal ROI f NMi program area 4 FFFFFh FFFFFh E Reset j FFEOOh Special page vector table FFFDCh Undefined instruction 3 Overflow BRK instruction Address match Internal ROM Capacity Address YYYYYh 192 Kbytes D0000h 256 Kbytes CO0000h 384 Kbytes A0000h 512 Kbytes 80000h Internal RAM C
514. st is generated Use this bit in an interrupt routine to discriminate the causes of interrupts between the oscillation stop and re oscillation detection interrupt and the watchdog timer interrupt This bit is set to 0 by writing O in a program Writing 1 has no effect Nor is it set to 0 by an oscillation stop and re oscillation detection interrupt request acknowledged If an oscillation stop or a re oscillation is detected when the CM22 bit 1 no oscillation stop and re oscillation detection interrupt requests are generated 10 Read the CM23 bit in an oscillation stop and re oscillation detection interrupt handling routine to determine the main clock status 11 When the CM21 bit 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CM06 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High Figure 8 4 CM2 Register Rev 2 00 Nov28 2005 page 60 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 bi bO IIIe D feka osn Oh 8 Clock Generating Circuit Timers A B and A D Clock 0 Divide by 2 of fAD f2 Select Bit 1 fAD f1 Clock source for the timers A B the dead time timer and A D SI O Clock Select Bit 0 f2SIO Clock source for UARTO to UART2 4 f1SIO SI O3 to SI O6
515. st is generated or not the interrupt request that has the highest priority is accepted For maskable interrupts peripheral functions interrupt any desired priority level can be selected using the ILVL2 to ILVLO bits However if two or more maskable interrupts have the same priority level their interrupt priority is resolved by hardware with the highest priority interrupt accepted The watchdog timer and other special interrupts have their priority levels set in hardware Figure 10 9 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine DBC Oscillation Stop and Re oscillation Detection Watchdog Timer Peripheral Function Single Step Address Match Figure 10 9 Hardware Interrupt Priority 10 5 10 Interrupt Priority Resolution Circuit The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point Figure 10 10 shows the circuit that judges the interrupt priority level Rev 2 00 Nov28 2005 page 92 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt Priority level of each interrupt inia value Highest Timer B2 Timer BO SI O6 2 l Timer A3 INT6 2 Timer
516. sweep mode 1 is selected b1 b0 4 00 ANO 1 pin A D Sweep Pin Select Bit 0 1 ANO AN1 2 pins 0 ANO to AN2 3 pins 11 ANO to AN3 4 pins 2 A D Operation Mode Set to 1 when repeat sweep Select Bit 1 mode 1 is selected M 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode ES Refer to NOTE 2 for ADCON2 M ers aia i VCUT VREF Connect Bit 3 1 VREF connected b7 b6 0 0 ANEXO and ANEX1 are not used RW External Op Amp 0 1 i Do not set a value Connection Mode Bit o 10 Do not set a value 1 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2_7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON register to select the desired pin 3 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 8 ADCONO Register and ADCON 1 Register in Repeat Sweep Mode 1 Rev 2 00 Nov28 2005 page 215 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 A D Converter 16 2 Function 16 2 1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register If the BITS bit is set to 1 10 bit conversion accuracy the A D
517. t Error Passive State Error BusOff State Bus Error this feature can be disabled separately CANO 1 Wake up Interrupt When the CPU detects the CANi successful reception transmission interrupt request the MBOX bit in the CiSTR register must be read to determine which slot has generated the interrupt request Rev 2 00 Nov28 2005 page 246 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports 20 Programmable I O Ports The programmable input output ports hereafter referred to simply as I O ports consist of 87 lines PO to P10 in the 100 pin version and consist of 113 lines PO to P14 in the 128 pin version Each port can be set for input or output every line by using a direction register and can also be chosen to be or not be pulled high every 4 lines P8_5 is an input only port and does not have a pull up resistor Port P8_5 shares the pin with NMI so that the NMI input level can be read from the P8_5 bit in the P8 register Table 20 1 lists the number of pins of the I O ports of each package Figures 20 1 to 20 5 show the I O ports Figure20 6 shows the I O pins Each pin functions as an I O port a peripheral function input output pin or a bus control pin For details on how to set peripheral functions refer to each functional description in this manual If any pin is used as a peripheral function inpu
518. t SI O4 output or D A converter output pin set the direction bit for that pin to 0 input mode Any pin used as an output pin for peripheral functions other than the SI O4 and D A converter is directed for output no matter how the corresponding direction bit is set When using any pin as a bus control pin refer to 7 2 Bus Control NOTE 1 Not available the bus control pins in T V ver Table 20 1 Number of Pins of I O Ports of Each Package NENNEN 128 pin Version 100 pin Version I O Ports 131 NESAS PO 0 to PO 7 P1 OtoP1 7 P2 0toP2 7 P3_0 to P3 7 P4_0 to P4 7 P5 0to P5 7 P6 0 to P6 7 P7 0to P7 7 P8_0 to P8 4 P8 5 is an in P9 0 to P9 7 P10 0 to P10 P11 0 to P11 P12 0 to P12 P13 0 to P13 P8 6 P8 7 put port 7 _7 e ET P14_0 P14_1 Rev 2 00 Nov 28 2005 page 247 of 378 REJ09B0124 0200 PO 0to PO 7 P1 OtoP1 7 P2 0toP2 7 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 7 P6 0 to P6 7 P7 0to P7 7 P8 0 to P8 4 P8 6 P8 7 P8 5 is an input port P9 0 to P9 7 P10 0 to P10 7 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Programmable l O Ports 20 1 PDi Register 100 pin Version i 0 to 10 128 pin Version i 0 to 13 Figure20 7 shows the PDi register This register selects whether the I O port is to be used for input or output The bits in this register correspond one for one to each port During me
519. t 15 The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the corresponding slot of the CiIDR register upon acceptance filtering operation When the masking function is employed it is possible to receive a certain range of IDs Figure 19 16 shows correspondence of the mask registers and slots Figure 19 17 shows the acceptance function Seo Oe Slot 6 C Sew register lt CiLMAR register Slot 14 CiLMBR register Slot 15 i 0 1 Figure 19 16 Correspondence of Mask Registers to Slots ID of the ID stored in The value of the Mask Bit Values received message the slot mask register 0 ID to which the received message corresponds match is handled as Don t care 1 ID to which the received message corresponds match is checked Acceptance Signal Acceptance judge signal 0 The CAN module ignores the current incoming message Not stored in any slot 1 The CAN module stores the current incoming message in a slot of which ID matches Figure 19 17 Acceptance Function When using the acceptance function note the following points 1 When one ID is defined in two slots the one with a smaller number alone is valid 2 When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode slots 14 and 15 receive all IDs which are not stored into slots 0 to 13 Rev 2 00 Nov 28 2005 page 239 of 378 RENESAS REJ09B0124 0200 Under development
520. t Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 21 Timer B Input Pulse Width Measurement Mode Standard Min Max Parameter TBilN Input Cycle Time TBilN Input HIGH Pulse Width TBilN Input LOW Pulse Width Table 22 22 A D Trigger Input Standard Min Max tc aD ADTRG Input Cycle Time trigger able minimum 1000 tw ADL ADTRG Input LOW Pulse Width 125 Table 22 23 Serial Interface Symbol Parameter Standard Min Max Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Es 22 24 External Interrupt INTi Input t Symbol oo Prae Eee Unit oo Prae Eee Unit anan Unit tw INH INTi Input HIGH Pulse Width twiINL INTi Input LOW Pulse Width Rev 2 00 Nov 28 2005 page 301 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Switching Characteristics 22 Electric Characteristics Normal ver VCC 5V Referenced to VCC 5V VSS 0 V at Topr 40 to 85 C unless otherwise specified Table 22 25 Memory Expansion Mode and Microprocessor Mode for setting with no wait Measuring Standard Parameter Address output delay time cond
521. t P10 Input H or L level signal or open P11 Oto P11 7 Input port P11 Input H or L level signal or open P12 0to P12 7 Input port P12 Input H or L level signal or open P13 0 to P13 7 Input port P13 Input H or L level signal or open P14 0 P14 1 NOTES Input port P14 Input H or L level signal or open 1 When using the standard serial I O mode It is necessary to input H to the TXD1 P6 7 pin while the RESET pin is L Therefore the internal pull up is enabled for the TXD1 P6 7 pin while the RESET pin is L 2 When using the standard serial I O mode the PO 0 to PO 7 P1 O0 to P1 7 pins may become indeterminate while the P8 4 pin is H and the RESET pin is L If this causes a problem apply L to the P8 4 pin 3 The pins P11 to P14 are only in the 128 pin version Rev 2 00 Nov 28 2005 page 283 of 378 REJ09B0124 0200 RENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version M16C 6N Group M16C 6NK Flash memory version Connect oscillator Mode setup method circuit VSS VSS to VCC1 VCC2 Package PLQP0100KB A Figure 21 13 Pin Connections for Standard Serial I O Mode 1 Rev 2 00 Nov28 2005 page 284 of 378
522. t P6 Register UART1 Transmit Receive Control Register 1 155 Port P7 Register Port P6 Direction Reg Port P7 Direction Reg UART Transmit Receive Control Register 2 156 Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register DMAO Request Cause Select Register Port P12 Register Port P13 Register DMA1 Request Cause Select Register Port P12 Direction Register Port P13 Direction Register Pull up Control Register 0 O3BDh CRG Data Megister Pull up Control Register 1 OSBEh CRC Input Register Pull up Control Register 2 03BFh UARTO Transmit Buffer Register 153 UARTO Receive Buffer Register 153 UART1 Transmit Buffer Register 153 UART1 Receive Buffer Register 153 Port Control Register The blank areas are reserved B 8 This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Rev 2 00 Nov 28 2005 RENESAS TEE 1 Overview The M16C 6N Group M16C 6NK M16C 6NM of single chip microcomputers are built using the high performance silicon gate CMOS process using an M16C 60 Series CPU core and are packaged in 100 pin and 128 pin plastic molded LQFP These single chip microcomputer
523. t the INV11 bit to 0 three phase mode 0 and the PWCON bit in the TB2SC register to 0 reload timer B2 with timer B2 underflow Figure 14 2 INVCO Register Rev 2 00 Nov28 2005 page 140 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Three Phase Motor Control Timer Function Three Phase PWM Control Register 1 b7 b6 b5 b4 b3 b2 bi BLLLLLLL rer ew idc Ded 0 Timer B2 underflow Ti A1 A2 A4 Start Trigger a Bit 1 Timer B2 underflow and write to the timer B2 Timer A1 1 A2 1 A4 1 Three phase mode 0 3 Control Bit 2 Three phase mode 1 Dead Time Timer f1 or f2 Count Source Select Bit 1 f1 divided by 2 or f2 divided by 2 Carrier Wave Detect Timer A1 reload control signal is 0 Flag 4 Timer A1 reload control signal is 1 Output Polarity Control Active L of an output waveform Bit Active H of an output waveform Enables dead time Dead Time Disable Bit Disaliles dead time Falling edge of a one shot pulse of Dead Time Timer the timer A1 A2 A4 Trigger Select Bit 1 Rising edge of the three phase output shift register U V W phase Reserved Bit Set to 0 1 Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 write enable The timers A1 A2 A4 and B2 must be stopped during rewrite 2
524. t the SM43 bit to 1 SOUTA output CLK4 function and the corresponding port direction bit for SOUTA pin to 0 input mode 6 The S5C and S6C registers are only in the 128 pin version When using the S5C and S6C registers set these registers after setting the PU37 bit in the PURG register to 1 Pins P11 to P14 are usable 7 When changing the SMi1 to SMi0 bits set the SiBRG register RW 00h to FFh Figure 15 37 S3C to S6C Registers S3BRG to S6BRG Registers and S3TRR to S6TRR Registers Rev 2 00 Nov28 2005 page 197 of 378 REJ09B0124 0200 RENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM SI O3 4 5 6 Transmit Receive Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset S3456TRR 01DAh XXXX0000b 15 Serial Interface SI O3 Transmit Receive 0 During transmission reception RW Complete Flag 1 Transmission reception completed SI O4 Transmit Receive 0 During transmission reception Complete Flag 1 Transmission reception completed S5TRF SI O5 Transmit Receive 0 During transmission reception Complete Flag 1 Transmission reception completed SI O6 Transmit Receive 0 During transmission reception SeTRF Complete Flag 1 Transmission reception completed RW Nothing is assigned When write set to 0 When read their contents are indeterminate 1 The S3TRF to S6TRF bits can only be reset by writing to 0
525. ta is Set to 0 by an interrupt request acknowledgement or a program received in the direct format STPS bit in U2MR register 0 1 stop bit TC 16 n 1 fi or 16 n 1 fEXT PRY bit in U2MR register 1 even parity fi frequency of U2BRG count source f1SIO f2SIO f8SIO f32SIO UFORM bit in U2CO register 0 LSB first fEXT frequency of U2BRG count source external clock U2LCH bit in U2C1 register 0 no reverse n value set to U2BRG U2IRS bit in U2C1 register 1 transmit is completed NOTE 1 Because TXD2 and RXD2 are connected a composite waveform consisting of transmit waveform from the transmitting end and parity error signal from receiving end is generated Figure 15 32 Transmit and Receive Timing in SIM Mode Rev 2 00 Nov 28 2005 page 193 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Figure 15 33 shows the example of connecting the SIM interface Connect TXD2 and RXD2 and apply pull up SIM card Figure 15 33 SIM Interface Connection 15 1 6 1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 The parity error signal is output when a parity error is detected while receiving data This is achieved by pulling the TXD2 output low with the timing shown in Figure 15 32 If the R2RB register is r
526. ten Therefore contents from multiple addresses can be read consecutively 21 3 5 2 Read Status Register Command 70h The read status register command reads the status register refer to 21 3 7 Status Register SRD Register for detail By writing command code xx70h in the first bus cycle the status register can be read in the second bus cycle Read an even address in the user ROM area Do not execute this command in EW1 mode 21 3 5 3 Clear Status Register Command 50h The clear status register command clears the status register By writing xx50h in the first bus cycle the FMRO7 FMRO6 bits in the FMRO register are set to 00b and the SR5 SR4 bits in the status register are set to 00b Rev 2 00 Nov28 2005 page 273 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 5 4 Program Command 40h The program command writes 2 byte data to the flash memory By writing xx40h in the first bus cycle and data to the write address in the second bus cycle an auto program operation data program and verify will start The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle The FMR0OO bit in the FMRO register indicates whether an auto program operation has been completed The FMROO bit is set to 0 busy during
527. ter is modified while the TBiS bit remains O count stops regardless whether after reset or not To set the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit 1 count starts be sure to write the same value as previously written to the TMODO TMOD1 MRO MR1 TCKO and TCK1 bits and a 0 to the MR2 bit The IR bit in the TBilC register goes to 1 interrupt request when an effective edge of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a timer overflow occur at the same time use another timer to count the number of times Timer B has overflowed To set the MR3 bit to 0 no overflow set the TBiMR register with setting the TBiS bit to 1 and counting the next count source after setting the MR3 bit to 1 overflow Use the IR bit in the TBilC register to detect only overflows Use the MR3 bit only to determine the interrupt factor When a count is started and the first effective edge is input an indeterminate value is transferred to the reload register At this time Timer Bi interrupt request is not generated A value of the counter is indeterminate at the beginning of a count The MR3 bit may be set to 1 and Timer Bi interrupt request may be generated betwee
528. ter reaches 0000h TAiIN Pin Function I O port or trigger input TAiOUT Pin Function I O port or pulse output Read from Timer An indeterminate value is read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Select Function i O0to4 j i 1 exceptj 4ifi 0 Pulse output function The timer outputs a low when not counting and a high when counting k i 1 exceptk Oifi 4 Rev 2 00 Nov 28 2005 page 125 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi b L fol 0o Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h 01 io i i Bit Symbol Select Bit 1 Pulse is output TMODO bi bo RW TMOD1 Operation Mode Select Bit 1 0 One shot timer mode RW TAiour pin functions as a pulse output pin 0 Pulse is not output External Trigger Select 0 Falling edge of input signal to TAiIN pin 2 z Pulse Output Function TAiour pin functions as I O port MR1 Mu j mau Bit 1 1 Rising edge of
529. th bit D8 is ACK or NACK When the IICM2 bit 1 the 1st to 7th bits D7 to D1 of received data are stored in the bit 6 to bit O in the UiRB register and the 8th bit DO is stored in the bit 8 in the UiRB register Even when the IICM2 bit 1 providing the CKPH bit 1 the same data as when the IICM2 bit 0 can be read out by reading the UiRB register after the rising edge of the corresponding clock pulse of 9th bit Rev 2 00 Nov28 2005 page 182 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 3 7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to 0 start and stop conditions not generated and the ACKC bit in the UiSMR4 register is set to 1 ACK data output the value of the ACKD bit in the UISMR4 register is output from the SDAi pin If the IICM2 bit 0 a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse If ACKi is selected for the cause of DMA1 request a DMA transfer can be activated by detection of an acknowledge 15 1 3 8 Initialization of Transmission Reception If a start condition is detected while the STAC bit 1 UARTi initialization enabled the serial I O operates as descri
530. the CAN module s error status 1 The value is indeterminate in bus off state CANi Time Stamp Register i 0 1 b8 b0 b7 50 Symbol Address After Reset COTSR 021Fh 021Eh 0000h C1TSR 023Fh 023Eh 0000h Time stamp function 0000h to FFFFh Ea CANI Acceptance Filter Support Register i O 1 b15 b8 b7 bO b7 bo Symbol Address After Reset C1AFS 0245h 0244h Indeterminate Function Setting Values Write the content equivalent to the standard frame ID of the received message The value is converted standard frame ID when read Standard frame ID Figure 19 11 CORECR C1RECR Registers COTECR C1TECR Registers COTSR C1TSR Registers and COAFS C1AFS Registers Rev 2 00 Nov28 2005 page 233 of 378 131 NESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 5 Operational Modes The CAN module has the following four operational modes CAN Reset Initialization Mode CAN Operation Mode CAN Sleep Mode CAN Interface Sleep Mode Figure 19 12 shows transition between operational modes MCU Reset ae Reset 0 CAN reset initialization mode State_Reset 1 Reset 1 Sleep 0 an Reset 1 Reset 0 CCLK3 1 or CCLK7 1 CAN interface sleep mode CA CAN sleep mode CCLK3 0 or CCLK7 0 CCLKS CCLK7 Bits in CCLKR register Reset Sleep RetBusOff Bits in CICTLR register i O
531. the vector and interrupt control register When using the A D conversion interrupt set the IFSRO1 bit to 0 A D conversion When using the key input interrupt set the IFSRO 1 bit to 1 key input 3 If this bit is set to 0 the software interrupt number 1 is selected CANO 1 wake up and the interrupt number 13 is selected CANO 1 error If this bit is set to 1 the interrupt number 1 is selected CANO wake up error and the interrupt number 13 is selected CAN1 wake up error 4 When the IFSR17 bit in the IFSR1 register 0 CAN1 successful reception and SI O4 share the vector and interrupt control register When using the CAN1 successful reception interrupt set the IFSRO3 bit to 0 CAN1 successful reception When using SI O4 interrupt set the IFSROS bit to 1 SI O4 5 Timer B5 and SI O5 share the vector and interrupt control register When using the timer B5 interrupt set the IFSROA bit to 0 Timer B5 When using SI O5 interrupt set the IFSRO4 bit to 1 SI O5 The SI O5 interrupt is only in the 128 pin version In the 100 pin version set the IFSRO4 bit to 0 Timer B5 6 Timer BO and SI O6 share the vector and interrupt control register When using the timer BO interrupt set the IFSRO5 bit to 0 Timer BO When using SI O6 interrupt set the IFSRO5 bit to 1 SI O6 The SI O6 interrupt is only in the 128 pin version In the 100 pin version set the IFSRO5 bit to 0 Timer BO 7 Timer B3 and UARTO bus collision dete
532. tion 1 has one wait state inserted BCLK Address bus CPU use RD signal W R signal C d 1 q 3 POL OP RO ot Data i bus CPU use X Source h Destination iiid CPU use 4 When the source read cycle under condition 2 has one wait state inserted ee 4 LL LL RD signal WR signal Data i i l mn bus CPU use Source X Source 1 X Destination NOTE 1 The same timing changes occur with the respective conditions at the destination as at the source Figure 12 5 Transfer Cycles for Source Read Rev 2 00 Nov28 2005 page 109 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible Table 12 2 shows the number of DMA transfer cycles Table 12 3 shows the coefficient j k The number of DMAC transfer cycles can be calculated as follows No of transfer cycles per transfer unit No of read cycles X j No of write cycles X k Table 12 2 DMA Transfer Cycles Transfer Unit Bus Width 16 bits 8 bit Transfer BYTE L Access Address Single chip Mode 12 DMAC Memory Expansion Mode Microprocessor Mode No of Read Cycles No of Write Cycles No of Read Cycles 8 bits BYTE H DMBIT 1 16 bits 16 b
533. tion Mode Bit 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON register to select the desired pin 3 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 16 7 ADCONO Register and ADCON 1 Register in Repeat Sweep Mode 0 Rev 2 00 Nov28 2005 page 213 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 1 5 Repeat Sweep Mode 1 In repeat sweep mode 1 analog voltage selectively applied to all pins is repeatedly converted to a digital code Table 16 6 lists the specifications of repeat sweep mode 1 Figure 16 8 shows the ADCONO and ADCON1 registers in repeat sweep mode 1 Table 16 6 Repeat Sweep Mode 1 Specifications Specification Function The input voltages on all pins selected by the ADGSEL1 to ADGSELO bits in the ADCON register are A D converted repeatedly with priority given to pins selected by the SCAN1 to SCANO bits in the ADCON1 register and ADGSEL1 to ADGSELO bits Example If ANO selected input voltages are A D converted in order of ANO AN1 ANO AN2 gt ANO gt ANS and so on A D Conversion Start Condition e When the TRG b
534. to programming or auto erasing Rev 2 00 Nov28 2005 page 372 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 20 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program be careful about the pins state and connection as follows 23 20 1 Programming Using Serial I O Mode CTXO pin This pin automatically outputs H level CRXO pin Connect to CAN transceiver or connect via resister to VCC pull up Figure 23 9 shows a pin connection example for programming using serial I O mode 1O pin connector M16C 6NK M16C 6NM VCC monitor input CLK1 P6_5 RxpiPe c NMI P8_5 TXD1 P6 7 RTS1 P6 4 PC card type Flash Programmer EPM P5 5 CRXO P9 5 CE P5 0 user reset signal Figure 23 9 Pin Connection for Programming Using Serial I O Mode 23 20 2 Programming Using CAN I O Mode RTS1 pin This pin automatically outputs H and L level Figure 23 10 shows a pin connection example for programming using CAN I O mode TO molas M16C 6NK M16C 6NM VCC monitor input CAN H E BGA rj CTXO P9 6 CANL 82C250 CRX0 P9_5 EPM P5_5 CE P5_0 RTS1 P6_4 PC card type NMI P8_5 CAN Programmer user reset signal Figure 23 10 Pin Connection for Programming Using CAN I O Mode Rev 2 00 Nov 28 2005 page 373 of 378 131 NES
535. to P10 7 P11 OtoP11 7 P12 OtoP12 7 P138 OtoP13 7 P14 0 P14 1 VREF XIN P7 1 P9 1 0 3 to 6 5 PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 0 3 to VCC 0 3 P3 Oto P3 7 P4 Oto P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10 OtoP10 7 P11 OtoP11 7 P12 OtoP12 7 P13 Oto P13 7 P14 O P14 1 XOUT P7 1 P9 1 0 3 to 6 5 Power Dissipation Topr 25 C 700 Operating Ambient When the Microcomputer is Operating T version 40 to 85 Temperature V version 40 to 125 option Flash Program Erase 0 to 60 Storage Temperature 65 to 150 option All options are on request basis NOTE 1 Ports P11 to P14 are only in the 128 pin version Rev 2 00 Nov28 2005 page 328 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics T V ver Table 22 47 Recommended Operating Conditions 1 Standard Parameter Supply Voltage VCC1 VCC2 Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input P0_0 to PO 7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 Voltage P4_0 to P4 7 P5 Oto P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 XIN RESET CNVSS BYTE P7_1 P9_1 LOW I
536. top 0 Disabled Enable Bit 1 Enabled E 0 SCL L hold disabled SCL Wait Bit 3 1 SCL L hold enabled generated Figure 15 10 UOSMR4 to U2SMR4 Registers Rev 2 00 Nov 28 2005 page 158 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 1 Clock Synchronous Serial I O Mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data Table 15 1 lists the specifications of the clock synchronous serial I O mode Table 15 2 lists the registers used in clock synchronous serial I O mode and the register values set Table 15 1 Clock Synchronous Serial I O Mode Specifications Specification Transfer Data Format Transfer data length 8 bits Transfer Clock The CKDIR bit in the UiMR register 0 internal clock fj 2 n 1 e fj f1SIO f2SIO f8SIO f32SIO n Setting value of the UIBRG register 00h to FFh The CKDIR bit 1 external clock Input from CLKi pin Transmission Reception Control Selectable from CTS function RTS function or CTS RTS function disabled Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in the UiTB register e If CTS function is
537. tten Step 1 Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously Step 2 Make sure that the DMAi is in an initial state in a program If the DMAi is not in an initial state the above steps should be repeated NOTES 1 The DMAS bit remains unchanged even if 1 is written However if 0 is written to this bit it is set to 0 DMA not requested In order to prevent the DMAS bit from being modified to 0 1 should be written to the DMAS bit when 1 is written to the DMAE bit In this way the state of the DMAS bit immediately before being written can be maintained Similarly when writing to the DMAE bit with a read modify write instruction 1 should be written to the DMAS bit in order to maintain a DMA request which is generated during execution N Read the TCRi register to verify whether the DMAi is in an initial state If the read value is equal to a value which was written to the TCRi register before DMA transfer start the DMAi is in an initial state If a DMA request occurs after writing to the DMAE bit the value written to the TCRi register is 1 If the read value is a value in the middle of transfer the DMAi is not in an initial state Rev 2 00 Nov28 2005 page 349 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 Timers
538. tting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the UDF register the TAZIE TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register are modified while the TAIS bit remains 0 count stops regardless whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TAi register However FFFFh can be read in underflow while reloading and 0000h in overflow When setting the TAi register to a value during a counter stop the setting value can be read before a counter starts counting Also if the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 2 00 Nov28 2005 page 351 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 10 1 3 Timer A One shot Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TAiMR i 0 to 4 register the TAI register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before setting th
539. types USP and ISP each configured with 16 bits Your desired type of stack pointer USP or ISP can be selected by the U flag of FLG 2 7 Static Base Register SB SB is configured with 16 bits and is used for SB relative addressing 2 8 Flag Register FLG FLG consists of 11 bits indicating the CPU status 2 8 1 Carry Flag C Flag This flag retains a carry borrow or shift out bit that has occurred in the arithmetic logic unit 2 8 2 Debug Flag D Flag This flag is used exclusively for debugging purpose During normal use it must be set to 0 2 8 3 Zero Flag Z Flag This flag is set to 1 when an arithmetic operation resulted in 0 otherwise it is 0 2 8 4 Sign Flag S Flag This flag is set to 1 when an arithmetic operation resulted in a negative value otherwise it is 0 2 8 5 Register Bank Select Flag B Flag Register bank 0 is selected when this flag is 0 register bank 1 is selected when this flag is 1 2 8 6 Overflow Flag O Flag This flag is set to 1 when the operation resulted in an overflow otherwise it is 0 2 8 7 Interrupt Enable Flag I Flag This flag enables a maskable interrupt Maskable interrupts are disabled when the flag is 0 and are enabled when the flag is 1 The I flag is set to 0 when the interrupt request is accepted 2 8 8 Stack Pointer Select Flag U Flag ISP is selected when the U flag is 0 USP is selected when the
540. ua rt dudes 46 2 4 Read and Write Signals eiit ee ertet xe atibus ex s rb tu sex e tu ie ieee tee eda 48 T2 SALE Sigal me 48 ZO BEY SGI ctor crane docstoc ges ccc eta E quM Sup tenet eee 49 F2 BI BOLK QutQut ERE 50 7 2 ZIHOED SAIN oasis verona tabem terete Suan curta mra T a EEEa EEE EEEE tu 50 7 2 9 External Bus Status When Internal Area Accessed sssssssssseeeseeeeeenenee een 52 EU DBEDUULICAIrIG m TERASS 52 8 Clock Generating Circuit e nnne nent 56 8 1 Types of Clock Generating Circuit eene nnne nnne nenne nnne trennen rsen nennen 56 MMUEIEeLdqC ER 64 8 1 2 SUD OIOCK zer tti oe eet tie D reor enitn feet DuC Ane bre cte bates ce Ante dre 65 8 1 3 On chip Oscillator ClOCK 2 tiroir itte batte is For ester eee sine aaa aED 66 Rm PILL ClOCK CIT 66 8 2 CPU Clock and Peripheral Function Clock ssssssesseseseeeeeeeeneeenee enne 68 8 23 CPU Clock and BOUK sipsirin xr reto used eren itur suce totus a LE Rec E O aaa aa aea 68 8 2 2 Peripheral E nctioni CIOGK erc ch to fe A a gus lene a Haein 68 8 3 Clock Output Function essssssssssseseseseeeee eene ee tnnt nit nnr se tnns iens sen aa a nnne seen etre nas 68 8 4 Power Control e NEE 69 8 4 1 Normal Operation Mode RT E i 69 8 4 2 Walt MOUG rss E S 71 8 4 3 Stop oo C entities eon aia acini ai ed inde lee 73
541. uction to keep the program waiting until the interrupt control register is modified INT SWITCH 1 FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h NOP NOP FSET Enable interrupt The number of the NOP instruction is as follows e The PM20 bit in the PM2 register 1 1 wait 2 The PM20 bit 0 2 waits 3 When using HOLD function 4 Example 2 Using the dummy read to keep the FSET instruction waiting INT SWITCH2 FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h MOV W MEM RO Dummy read FSET l Enable interrupt Example 3 Using the POPC instruction to changing the I flag INT SWITCH3 PUSHC FLG FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h POPC FLG Enable interrupt 23 8 7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt request is generated Rev 2 00 Nov28 2005 page 348 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 9 DMAC 23 9 1 Write to DMAE Bit in DMiCON Register i 0 1 When both of the conditions below are met follow the steps below Conditions The DMAE bit is set to 1 again while it remains set DMAi is in an active state A DMA request may occur simultaneously when the DMAE bit is being wri
542. ule enters instantly into error active state and the CAN communication becomes possible immediately 2 When the RetBusOff bit in the CiCTLR register 1 Force return from buss off The module enters instantly into error active state and the CAN communication becomes possible again after 11 consecutive recessive bits are detected Rev 2 00 Nov28 2005 page 236 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 CAN Module 19 6 Configuration CAN Module System Clock The M16C 6N Group M16C 6NK M16C 6NM has a CAN module system clock select circuit Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the CICONR register i 0 1 For the CCLKR register refer to 8 Clock Generating Circuit Figure 19 14 shows a block diagram of the clock generating circuit of the CAN module system Divide by 1 undivided CAN module pivide by 2 _ Prescaler O d system clock Divi o fCAN 1 2 Baud rate divider by prescaler division value CCLKR register P 1 CAN module fCAN CAN module system clock P The value written in the BRP bit in the CICONR register i 0 1 P 0 to 15 fCANCLK CAN communication clock fCANCLK fCAN 2 P 1 Figure 19 14 Block Diagram of CAN Module System Clock Generating Circuit 19 7 Bit Timing Configuration The bit t
543. ument is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM SI Oi Control Register i 3 to 6 Symbol Address After Reset S3C 01E2h 01000000b S4C 01E6h 01000000b b7 b6 b5 b4 b3 b2 bi bO S5C 6 01EAh 01000000b S6C 6 01D8h 01000000b Bit Name Internal Synchronous Clock Select Bit 7 SOUTi Output Disable Bit 4 Description b1bO 00 Selecting f1SIO or f2SIO 0 1 Selecting f8SIO 10 Selecting f32SIO 1 1 Do not set a value SOUTi output SOUTi output disabled high impedance 15 Serial Interface S I Oi Port Select Bit 5 Input output port SOUTI output CLKi function CLK Polarity Select Bit Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Transfer Direction Select Bit LSB first 1 MSB first Synchronous Clock Select Bit SOUTi Initial Value Set Bit SI Oi Bit Rate Generator i 3 to 6 0 Symbol Address After Reset S3BRG 01E3h Indeterminate S4BRG 01E7h Indeterminate S5BRG 3 01EBh Indeterminate External clock 2 Internal clock 3 Effective when the SMi3 bit 0 0 L output 1 H output SeBRG 3 01D9h Indeterminate Description Assuming that set value n SiBRG divides the count source by n 1 2 Use the MOV instructi
544. unt etc 6N Group M16C Family Figure 1 2 Type No Memory Size and Package Rev 2 00 Nov28 2005 page 5 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview 1 5 Pin Configuration Figures 1 3 and 1 4 show the pin configuration top view Tables 1 4 to 1 8 list the pin characteristics PIN CONFIGURATION top view gt P2 3 AN2 3 A8 a P2 4 AN2 4 A4I gt P2 5 AN2 5 A5 gt P2 6 AN2 6 A6l a gt P2 7 AN2 7 ATI 4 vss S INT3 4 INT4 5 INTS D7 1 1 AN2 1 A1 1 2 3 7 5 D 6 D 7 D VA P2 2 AN2 2 A2 a gt P3 0 A8 4 VCC2 lt P3 1 A9 lt p lt gt p lt q P lt p lt p lt P4 E g 5 a 8 F5 a g o N 2 8 E T g 2 P1 2 D10 lt P4 2 A18 P1 1 D9 lt gt P1 0 D8 PO 7 ANO 7 D7 a gt PO 6 ANO 6 D6 PO 5 ANO 5 D5 PO 4 ANO 4 D4 lt PO 3 ANO 3 D3 lt gt PO 2 ANO 2 D2 lt PO 1 ANO 1 D1 lt gt PO O ANO 0 DO lt gt P10 7 AN7 KI3 lt gt P10 6 ANG KI2 lt P10 5 AN5S KH lt P10 4 ANA KIO lt P10_3 AN3 lt lt P10 2 AN2 lt P10 1 AN1 lt AVSS P10_0 ANO lt VREF AVCC P9 7 ADTRG
545. upt TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B1 interrupt TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B2 interrupt 01 Event counter mode TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B3 interrupt PCLKO Bit in PCLKR register filter TCKO Noise filter TCKO Noise filter TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B4 interrupt TMOD 1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B5 interrupt TCK1 to TCKO TMOD1 to TMODO Bits in TBiMR register i O to 5 NOTE 1 Be aware that TB5IN shares the pin with RXD2 SCL2 and TAOIN Figure 13 2 Timer B Configuration Rev 2 00 Nov28 2005 page 114 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6 13 1 Timer A NM 13 Timers Figure 13 3 shows a block diagram of the timer A Figures 13 4 to 13 6 show the timer A related registers The timer A supports the following four modes Except in event counter mode timers AO to A4 all have the same function Use the TMOD1 to TMODO bits in the TAiMR register i O to 4 to select the desired mode Timer mode Event counter mode e One shot
546. us control pins except CLKOUT pin in T V ver Figure 1 3 Pin Configuration Top View 1 Rev 2 00 Nov28 2005 page 6 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 4 Pin Characteristics for 100 Pin Package 1 Control Interrupt Timer Pin UART Pin CAN Module Bus Control Pin Pin Pin Pin INIo BR a Pp TA4IN U TA4OUT U SIN4 TASIN TA3OUT TA2IN W SOUT4 TA2OUT W CLK4 TAIIN V CTS2 RTS2 TA1OUT V CLK2 TAOIN TBSIN RXD2 SCL2 TAOOUT TXD2 SDA2 TXD1 SDA1 RXD1 SCL1 CLK1 CTS1 RTS1 CTSO CLKS1 TXDO SDAO RXDO SCLO CLKO CTSO RTSO RDY CLKOUT ALE HOLD HLDA BCLK RD WRH BHE WRL WR CS3 CS2 CS1 CS0 A19 A18 NOTE 1 Not available the bus control pins except CLKOUT pin Pin No 37 in T V ver Rev 2 00 Nov 28 2005 page 7 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 5 Pin Characteristics for 100 Pin Package 2 Control Interrupt Timer Pin UART Pin CAN Module Bus Control Pin Pin Pin Pin
547. ut during two phase pulse signal processing This function can only be used in timer A3 event counter mode during two phase pulse signal processing free running type x4 processing with Z phase entered from the ZP pin Counter initialization by Z phase input is enabled by writing 0000h to the TA3 register and setting the TAZIE bit in the ONSF register to 1 Z phase input enabled Counter initialization is accomplished by detecting Z phase input edge The active edge can be selected to be the rising or falling edge by using the POL bit in the INT2IC register The Z phase pulse width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source The counter is initialized at the next count timing after recognizing Z phase input Figure 13 10 shows the relationship between the two phase pulse A phase and B phase and the Z phase If timer A3 overflow or underflow coincides with the counter initialization by Z phase input a timer A3 interrupt request is generated twice in succession Do not use the timer A3 interrupt when using this function TSOUT A phase oo TA3IN B phase ZP 1 i Input equal to or greater than one clock cycle of count source Timer A3 m XmetX 1X 2 X 3 X 4 X5 NOTE 1 This timing diagram is for the case where the POL bit in the INT2IC register 1 rising edge Figure 13 10 Two phase Pulse A phase and B phase and Z Phase Rev 2 00 Nov 28 2005 page 124
548. utput CKPOL 0 CKPH 1 Clock output CKPOL 1 CKPH 1 il H Data input timing f i f f f f f i Figure 15 28 Transmission and Reception Timing in Master Mode Internal Clock Rev 2 00 Nov 28 2005 page 187 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface Slave control input Clock input CKPOL 0 CKPH 0 Clock input CKPOL 1 CKPH 0 Data output timing Data input timing oo or ce Xs yo Xs c9 Figure 15 29 Transmission and Reception Timing CKPH 0 in Slave Mode External Clock Slave control input Clock input H CKPOL 0 CKPH 1 Clock input H CKPOL 1 CKPH 1 Data output timing Data input timing w o or Xe os os X os X os X o LT 111111 Figure 15 30 Transmission and Reception Timing CKPH 1 in Slave Mode External Clock Rev 2 00 Nov28 2005 page 188 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 Serial Interface 15 1 5 Special Mode 3 IE Mode In this mode one bit of IEBus is approximated with one byte of UART mode waveform Table 15 16 lists the registers used in IE mode and the register values set Figure 15 31 shows the functions of bus collision detect function related bits If the TX
549. utput undefined P4 4 Input port CSO output H is output CSO output H is output P4 5 to P4_7 Input port Input port Pulled high Input port Pulled high Input port WR output H is output WR output H is output Input port BHE output undefined BHE output undefined Input port RD output H is output RD output H is output Input port BCLK output BCLK output HLDA output The output value depends on the input to the HOLD pin HLDA output The output value depends on the input to the HOLD pin HOLD input HOLD input ALE output L is output ALE output L is output RDY input RDY input P6 P7 P8 Oto P8 4 P8 6 P8 7 P9 P10 Input port Input port P11 P12 P13 P14 0 P14 109 NOTES Input port Input port 1 Shown here is the valid pin state when the internal power supply voltage has stabilized after power on When CNVSS VCC the pin state is indeterminate until the internal power supply voltage stabilizes CNVSS VCC is not available in T V ver 2 P11 P12 P13 P14 0 and P14 1 pins are only in the 128 pin version Rev 2 00 Nov28 2005 page 36 of 378 REJO9BO0124 0200 131 NE ESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 5 Reset 5 2 Software Reset The microcomputer resets pins the C
550. v28 2005 page 278 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 21 5 Status Register Bits in Status Register Bits in FMRO Register Status Name Reserved 21 Flash Memory Version Contents Value after Reset Reserved Reserved Reserved Program status Terminated normally Terminated in error Erase status Terminated normally Terminated in error Reserved Sequencer status Busy Ready DO to D7 These data bus are read when the read status register command is executed NOTE 1 The FMRO6 bit SR4 and FMRO7 bit SR5 are set to 0 by executing the clear status register command When the FMRO6 bit SR4 or FMRO7 bit SR5 is set to 1 the program block erase erase all unlocked block and lock bit program commands are not accepted Rev 2 00 Nov28 2005 page 279 of 378 REJ09B0124 0200 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Flash Memory Version 21 3 8 Full Status Check If an error occurs when a program or erase operation is completed the FMRO6 FMRO7 bits in the FMRO register are set to 1 indicating a specific error Therefore execution results can be confirmed by check ing these bits full status check Tabl
551. ve for setting with wait BCLK RD Separate bus WR WRL WRH Separate bus RD Multiplexed bus WR WRL WRH Multiplexed bus RDY input tsu RDY BCLK th BCLK RDY Common to setting with wait and setting without wait tsu HOLD BCLK th BCLK HOLD HOLD input HLDA output PO P1 P2 P3 P4 2 P5 0to P5 2 gt lt gt lt ta BCLK HLDA td BCLK HLDA NOTE 1 The above pins are set to high impedance regardless of the input level of the BYTE pin the PMO6 bit in the PMO register and the PM11 bit in the PM1 register Measuring conditions e VCC 5V e Input timing voltage Determined with Vit 1 0 V Viu 4 0 V e Output timing voltage Determined with Vo 2 5 V Vou 2 5 V Figure 22 5 Timing Diagram 2 Rev 2 00 Nov28 2005 page 306 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Electric Characteristics Normal ver Memory Expansion Mode and Microprocessor Mode For setting with no wait Read timing ta BCLK CS 1 th BCLK CS lt _ 25ns max d 4ns min T it td BCLK AD td BCLK ALE lt gt i i 25ns max i D ta BCLK RD th BCLK RD 4 gt 25ns max gt i 1 Ons min lact RD DB i 0 5 X tcyc 45 ns max i SU DB RD arer th RD DB 40ns min Ons min tn BC
552. velopment and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Interrupt 10 6 INT Interrupt INTI interrupt i 0 to 8 is triggered by the edges of external inputs The edge polarity is selected using the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register INT4 share the interrupt vector and interrupt control register with CAN1 successful transmission and SI O3 INT5 share with CAN1 successful reception and SI O4 INT6 share with Timer A3 INT7 share with Timer A2 INT8 share with Timer B1 To use the INT4 to INT8 interrupts set the each bits as follows To use the INT4 interrupt Set the IFSR16 bit in the IFSR1 register to 1 INT4 To use the INT5 interrupt Set the IFSR17 bit in the IFSR1 register to 1 INT5 e To use the INT6 interrupt Set the IFSR21 bit in the IFSR2 register to 1 INT6 e To use the INT7 interrupt Set the IFSR20 bit in the IFSR2 register to 1 INT7 e To use the INT8 interrupt Set the IFSR22 bit in the IFSR2 register to 1 INT8 After modifying the IFSR16 IFSR17 IFSR20 IFSR21 and IFSR22 bits set the corresponding IR bit to 0 interrupt not requested before enabling the interrupt NOTE 1 INT6 to INT8 interrupts are only in the 128 pin version Figures 10 11 to 10 13 show the IFSRO IFSR1 and IFSR2 registers Rev 2 00 Nov28 2005 page 94 of 378 RENESAS REJ09B0124 0200 Unde
553. vide by n value can be selected the same way as in on chip oscillator mode Rev 2 00 Nov28 2005 page 70 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Clock Generating Circuit 8 4 2 Wait Mode In wait mode the CPU clock is turned off so are the CPU because operated by the CPU clock and the watchdog timer However if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source the watchdog timer remains active Because the main clock sub clock and on chip oscillator clock all are on the peripheral functions using these clocks keep operating 8 4 2 1 Peripheral Function Clock Stop Function If the CMO2 bit in the CMO register is 1 peripheral function clocks turned off during wait mode the f1 f2 f8 f32 f1SIO f8SIO f32SIO fAD fCANO and fCAN1 clocks are turned off when in wait mode with the power consumption reduced that much However fC32 remains on 8 4 2 2 Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction When the CM11 bit 1 CPU clock source is the PLL clock be sure to set the CM11 bit in the CM1 register to 0 CPU clock source is the main clock before going to wait mode The power consumption of the chip can be reduced by setting the PLCO7 bit in the PLCO register to 0 PLL stops 8 4 2 3 Pin Status Duri
554. w to set the priority in which order they are accepted What is explained here does not apply to non maskable interrupts Use the I flag in the FLG register IPL and the ILVL2 to ILVLO bits in the each interrupt control register to enable disable the maskable interrupts Whether an interrupt is requested is indicated by the IR bit in the each interrupt control register Figures 10 3 and 10 4 show the interrupt control registers Interrupt Control Register Symbol Address CO1WKIC 8 0041h CORECIC 0042h COTRMIC 0043h TBS5IC SSIC 5 0045h TB4IC U1BCNIC 2 0046h TBSIC UOBONIC 3 0047h U2BCNIC 004Ah DMOIC DM1IC 004Bh 004Ch CO1ERRIC 6 9 004Dh ADIC KUPIC 6 004Eh SOTIC to S2TIC 0051h 0053h SORIC to S2RIC 0052h 0054h b7 b6 b5 b4 b3 b2 bi bO TAOIC TA1 IC 0055h 0056h TA4IC 0059h TBOIC S6IC 7 005Ah TB2IC 005Ch Bit Symbol ILVLO 004Fh 0050h Level 1 Interrupt Priority Level Select Bit Co ee Oe ae Cc 4 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt not requested Interrupt Request Bit Interrupt requested Noting is assigned When write set to O When read their contents are indeterminate After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Level 0 interrupt disabled 1 To rewrite the interrupt control registers do s
555. wait 3 BCLK cycles OlooOooIlo oloijo NOTES 1 To use the RDY signal set this bit to 0 2 To access in multiplexed bus mode set the corresponding bit of CSOW to CS3W to 0 with wait state 3 After reset the PM17 bit is set to 0 without wait state all of the CSOW to CS3W bits are set to 0 with wait state and the CSE register is set to 00h one wait state for CS0 to CS3 Therefore the internal RAM and internal ROM are accessed with no wait state and all external areas are accessed with one wait state 4 When the selected CPU clock source is the PLL clock the number of wait cycles can be altered by the PM20 bit in the PM2 register When using PLL clock over 16 MHz be sure to set the PM20 bit to 0 2 wait cycles 5 When the PM17 bit is set to 1 and access an external area set the CSiW bits i 0 to 3 to 0 with wait sate Rev 2 00 Nov28 2005 page 53 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Bus 1 Separate bus No wait setting Bus cycle 1 Bus cycle BCLK Write signal Read signal Data bus s pij 2 Separate bus 1 wait setting Bus cycle Bus cycle 1 Write signal Read signal Data bus Address bus Address X Address X CS 3 Separate bus 2 wait setting Bus cycle 1 Bus cycle 1
556. wo phase pulse signal processing set this bit to O Fw MR2 To use two phase pulse signal processing set this bit to 1 W W W W R To use two phase pulse signal processing set this bit to 0 R R MR3 TCKO Count Operation Type 0 Reload type Select Bit 1 Free run type Two Phase Pulse Signal N TCK1 Processing Operation 0 Normal processing operation RW Select Bit 1 2 1 Multiply by 4 processing operation 1 The TCK1 bit is valid for the TASMR register No matter how this bit is set timers A2 and A4 always operate in normal processing mode and x4 processing mode respectively 2 If two phase pulse signal processing is desired following register settings are required Set the TAiP bit in the UDF register to 1 two phase pulse signal processing function enabled Set the TAITGH and TAITGL bits in the TRGSR register to 00b TAiIN pin input Set the port direction bits for TAiIN and TAiOUT to 0 input mode Figure 13 9 TA2MR to TA4MR Registers in Event Counter Mode when using two phase pulse signal processing with timer A2 A3 or A4 Rev 2 00 Nov28 2005 page 123 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Timers 13 1 2 1 Counter Initialization by Two Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z phase counter initialization inp
557. x 4 Data Field D o o oilo m PO Po P S S gt QU o ssa s gt gt gt mac 3 GOO DIN 2 CAN1 Message Box 4 Time Stamp ojoo MININ w w gt S 7 So o nv UJ N CAN1 Message Box 5 Identifier DLC wo ojojoj RO PO POP PO w w Ww PAKES sS FS eo n UJ jN ma oo NMIN W 2 CAN1 Message Box 5 Data Field N w 2 oo mM UJ UJ oj mI 02BDh 02BEh O2BFh CAN1 Message Box 5 Time Stamp B 6 Symbol 02COh 02C1h 02C2h 02C3h CAN1 Message Box 6 Identifier DLC 02C4h CAN1 Message Box 6 Data Field 02CEh CAN1 Message Box 6 Time Stamp 02D0h 02D1h 2 o N a a CAN1 Message Box 7 Identifier DLC oo NIN 99 2 N ojo N CAN1 Message Box 7 Data Field olooo PO PO PO PO olg go 0905 JEJE o n e UJ E o n 8 Q E CAN1 Message Box 7 Time Stamp CAN1 Message Box 8 Identifier DLC CAN1 Message Box 8 Data Field CAN1 Message Box 8 Time Stamp OQ oo NO PO B yam ss o N TI N CAN1 Message Box 9 Identifier DLC O O O O RO PO POP PO TM 1 7 OD 1 AJ 3 5 2 2 o N T co oo NIN TT oO aa CAN1 Message Box 9 Data Field o o gt oo MIN T T oW Lm 02FDh 02FEh O2FFh CAN1 Message Box 9 Time Stamp Symbol Symbol 0340h CAN1 Message Box 10 Identifier DLC en CAN1 Message Box 14 Identifier DLC C
558. y When the PMO1 to PMOO bits are rewritten L is output from the P3 7 to P3 4 pins during 0 5 cycles of the BCLK by setting the PMO1 to PMOO bits in the PMO register to 01b memory expansion mode or 11b microprocessor mode from 00b single chip mode after setting the PM11 bit to 1 Normal ver only Rev 2 00 Nov28 2005 page 367 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 16 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage latch up occurs When different power supplied to the system and input voltage of unused dedicated input pin is larger than voltage of VCC pin connect dedicated input pin to VCC via resistor approximately 1kQ Figure 23 8 shows the circuit connection This note is also applicable when VINPUT exceeds VCC during power up The resistor is not necessary when VCC pin voltage is same or larger than dedicated input pin voltage m di Different power supply TRI Dedicated input pin e g NMI M16C 6NK M16C 6NM Figure 23 8 Circuit Connection Rev 2 00 Nov 28 2005 page 368 of 378 RENESAS REJ09B0124 0200 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution 23 17 Electrical Characteristic Differences Between
559. ymbol Address After Reset COMCTLO to COMCTL15 0200h to 020Fh 00h C1MCTLO to CIMCTL15 0220h to 022Fh 00h When set to reception slot Successful 0 The content of the slot is read or still under Reception Flag processing by the CPU 1 The CAN module has stored new data in the slot NewData When set to transmission slot 0 Transmission is not started or completed yet 1 Transmission is successfully completed Successful SentData Transmission Flag When set to reception slot Under Reception 0 The message is valid 1 The message is invalid The message is being updated InvalData When set to transmission slot TrmActive Transmission 0 Waiting for bus idle or completion of arbitration Flag 1 Transmitting When set to reception slot 0 No message has been overwritten in this slot MsgLost Overwrite Flag 1 This slot already contained a message but it has been overwritten by a new one Remote Frame 0 Data frame transmission reception status i Transmission 1 Remote frame transmission reception status RemActive Reception Status Flag When set to reception remote frame slot 0 After a remote frame is received it will be answered automatically 1 After a remote frame is received no transmission will be started as long as this bit is set to 1 Not responding Auto Response RspLock Lock Mode Select Bit Remote Frame 0 Slot not corresponding to remote frame Remote Corresponding 1 Slot correspond

Renesas M16C/6NK User's Manual

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