Renesas Asynchronous SH7145F User's Manual
Contents
1. init_sci Initialize SCI aid i rov sci i Receive lst byte of serial data i rov sci i Receive 2nd byte of serial data i rov sci i Receive 3rd byte of serial data while 1 LOOP ok ok ok oko ok ok ok KK KK k ok k ok ok ok KARA ok ok k kkk kkk kkk kkk kkk kkk kk kkk kkk k REJ06B0357 01000 Rev 1 00 March 2004 Page 14 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception Function init_sci Operation Initialize serial scil Asynchronous receive operation Data 8bit Stop bit s C ILBIE Parity bit No kkkkk AR A k k k kk k k k k k k k k k kok k k kk k kk k k k k k kk k kkk kk kk kkk kkk kkk kkk void init_sci void unsigned long i P_STBY MSTCR1 BIT MSTP17 0 disable SCI1 standby mode Initialize SCI Asynchronous mode P_SCI1 SCR_1 BYTE amp 0x03 clear TIE RIE TE RE MPIE TEIE P_SCI1 SCR_1 BIT CKE 0 clock internal SCK output w P_SCI1 SMR_1 BYTE 0x00 8bit No parity lstop bit K CA 0 Asynchronous mode ey CHR 0 data length 8bits PE 0 No parity ff OE 0 0 even parity STOP 0 1 stop bit CKS 0 clock source P 25MHz P SCI1 BRR 1 40 19200bps 25MHz Peripheral P_SCI1 SDCR_1 BIT DIR 0 LSB first send for i 0 i lt 0x0300 i Wait lbit P SCI1 SCR 1 BIT TIE 0 TXI1 interrupt disable P SCI1 SCR 1 BIT RIE 0 RXI12. lt Transmit data register 1 TXD1 TSR_1 TDR_1 23 ne ee ee Receive data control SCI1 receive data input pin Receive shift register 1 Receive data register 1 RXD1 RSR_1 RDR_1 Figure 2 SCI ch1 Block Diagram e Asynchronous Mode Serial data communication is performed using synchronization by character unit This allows serial communication with a standard dedicated asynchronous communication chip such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA In addition the asynchronous mode supports serial communication among multiple processors multiprocessor communication function REJ06B0357 01000 Rev 1 00 March 2004 Page 3 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception On Chip Peripheral Clock Po This is the reference clock for operation of on chip peripheral functions The clock signal is generated by a clock oscillator Receive Shift Register RSR_1 This register is used to receive serial data Serial data is input to RSR_1 from the RxD_1 pin When one frame of data has been received it is automatically transferred to the receive data register RDR_1 RSR_1 cannot be accessed by the CPU Receive Data Register RDR_1 Received data is stored in this 8 bit register When one frame of data has been received it is automatically transferred from RSR_1 RSR_1 and RDR_1 are in a double buff
3. ERI interrupt disable Initialize SCI1 PORT P_PORTA PACRL2 BIT PA4MD 1 set TXD1 PA4 134pinGSH7145 y P_PORTA PACRL2 BIT PA3MD 1 set RXD1 PA3 133pin SH7145 a P_SCI1 SCR_1 BYTE 0x30 TE RE 1 Transmit and Receive Enable BR k k k k k k o k kok kok k kok kok k k k k k k k k k kok kok kok kok k k k k kok kok kk k kok k kk kk kk k kk k kk k kk kk HK Function rov sci x Operation Serial data receive and send function calls Argument None x Value returned None y o kok ok KK kok kok k kok k kok k k k k oko k kok k k kok k kok k kok k kok k k kk k kok k kk kk kk k kk k kk k k HK unsigned char rcv sci unsigned char rev count while P_SCI1 SSR_1 BIT RDRF 0 Wait until reception finishes Rev_data rev_count P_SCI1 RDR_1 get receive data REJ06B0357 01000 Rev 1 00 March 2004 Page 15 of 17 ENESAS SH7145F Asynchronous Serial Data Transmission Reception P_SCI1 SSR_1 BIT RORF 0 trans sci Rev data rev count rev count t return rev count 4 r Clear RDRF Transmit receive data Increment storage address y A S E E K K KK KK k k k oko k k k k ko k k k k kok k k kok k k k k k kok kok k k k kk k k k k k k kok k k k k k kk kk kk k k k k k k kkk Function Operation Argument Value returned trans_sci Write 1 character to serial output trans_data None sI aA S EEk k k k
4. RDR_1 Clear RDRF flag in SSR_1 to 0 Clear TDRE flag in SSR_1 to 1 Transfer data from TDR_1 to TSR_1 10 11 12 13 Write receive data to TDR_1 14 15 16 Repeat Repeat REJ06B0357 01000 Rev 1 00 March 2004 Page 7 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 4 Software 1 Module Descriptions Table 4 lists the modules used in the task example Table 4 Module Descriptions Module Label Function Main routine main Calls modules SCI routine init_sci Initial settings of SCI1 Receive routine rev Sci Receives serial data Transmit routine trans_sci Transmits serial data Error handling err_int Handles receive errors 2 Argument Descriptions Table 5 lists the arguments used in the task example Table 5 Argument Descriptions Argument Function Module Rev_data 0 2 Stores SCI 1 receive data Receive routine trans data Transmits data from SCI 1 Transmit routine 3 On Chip Register Descriptions Table 6 lists the on chip registers used in the task example The set values shown are the values used in the task example and differ from the initial settings REJ06B0357 01000 Rev 1 00 March 2004 Page 8 of 17 SH7145F a E N ESAS Asynchronous Serial Data Transmission Reception Table 6 On Chip Register Descriptions Register Bit Set Value Function MSTCR1 MSTP17 Module standby control register 1 SC
5. in on chip RAM Clear RDRF flag in SSR 1 to 0 Transmit receive data without modification 4 Data Transfer Routine Z possible to write to TDR 1 Yes Write transmit data to TDR 1 Clear TDRE bit in SSR 1 to 0 REJ06B0357 01000 Rev 1 00 March 2004 Page 13 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 6 Program Listing A xkkkkkkkkkkkkkkkkkk kkkkkkkkkkkk kkkkk kkkkkkk kkkkk kkkkk kkkkkkkk SH7145F Application Note x ad Function 7 J SCIL External input clock 12 5MHz Internal CPU clock 50MHz Internal peripheral clock 25MHz Written 2003 7 Rev 1 0 ok ok ok ok ok KKK KKK kok k KARR ok k AAA oo include iodefine h include lt machine h gt define COUNT 3 Function Definition void main void void init sci void unsigned char rcv sci unsigned char void trans sci char void err int void void dummy_f void volatile unsigned char Rev_data COUNT S EEK Kk ko k k kok k kok k k kok k k kok kok kok k k k k k k k k k kk k kok k kk k k kk k kok k kk kk main Program o e ok k KK kok ko kok oko k oko kok kok kok k kkk kkk kok kok kok k kok k k kok k k kk k kk k kk kk void main void unsigned char i 0
6. k k k k k k k k k k k kok k k k k k k k k k kok k k kok k k k k k kok k k k k kok k kk k k kk k kk kk k kk kkk k void trans_sci char tarans_data while P_SCI1 SSR_1 BYTE amp 0x80 r P_SCI1 TDR_1 P_SCI1 SSR_1 BYTE amp Ox7F unsigned char trans_data BOR RK k kok kok k oko kok kok kok kok k IK RK kok Interrupt handling Kk k k k k k k kk k kk k kk k kk kk k kk kk pragma interrupt err int void err int void if P_SCI1 P_SCI1 if P_SCI1 P_SCI1 if P_SCI1 P SCIL SS SS SS SS SS SS pragma interrupt dummy f void dummy f void Other Interrupt s T ORER 1 T ORER 0 T FER 1 T FER 0 T PER 1 T PER 0 Write data t Clear flag Overrun error ORER flag clear Framing error FER flag clear Parity error PER flag clear o TDR transmit Wait until data can be written to TDR until TDRE is set to 1 2 ai azi KV REJ06B0357 01000 Rev 1 00 March 2004 Page 16 of 17 4 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception Keep safety first in your circuit designs Renesas Technology Corp puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors
7. may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corp or a third party Renesas Technology Corp assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corp without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor for the latest product information before purchasing a product listed herein The information described he
8. I standby control bit Standby cancelled when MSTP17 0 SCR 1 H 70 Serial control register 1 SCI 1 Transmit and receive control interrupt control transmit and receive clock source control TIE Transmit interrupt enable TXI interrupt reguests enabled when set to 1 RIE Receive interrupt enable RXI and ERI interrupt requests enabled when set to 1 TE Transmit enable Transmit operations enabled when set to 1 RE Receive enable Receive operations enabled when set to 1 MPIE Multiprocessor interrupt enable In asynchronous mode enabled when MP 1 in SMR In the task example disabled because MP 0 TEIE Transmit end interrupt enable TEI interrupt requests enabled when set to 1 CKE1 CKE2 Clock enable 1 0 Selects clock source and SCK pin function In the task example clock source is on chip clock and SCK pin is not used SMR 1 H 00 Serial mode register 1 Selects communication format and the clock source for on chip baud rate generator C A Communication mode Asynchronous mode when cleared to 0 CHR Character length enabled in asynchronous mode only 8 bit transmission and reception when 0 PE Parity enable enabled in asynchronous mode only No parity transmission and reception when 0 O E Parity mode enabled in asynchronous mode when PE 1 In this example PE 0 and this bit is disabled STOP Stop bit leng
9. Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corp for further details on these materials or the products contained therein REJ06B0357 01000 Rev 1 00 March 2004 Page 17 of 17
10. RENESAS APPLICATION NOTE SH7145F Asynchronous Serial Data Transmission Reception Summary The SH7144 series is a single chip microprocessor based on the SH 2 RISC Reduced Instruction Set Computer CPU core and integrating a number of peripheral functions This application note describes asynchronous serial data transmission reception using the SCI Serial Communication Interface module of the SH7145F It is intended to be used as reference by users designing software applications The program examples contained in this application note have been tested However operation should be confirmed before using them in an actual application Device for Which Operation Has Been Confirmed SH7145F Contents 1 Specifications 2244x tz dered nacieti erecta aceindls decetrebdns eR aaa aea EEEa ss nu 2 2 F nctions USO ccs sscs a cases canst anaana aaa aana aiaa ewan ddeennancen 3 Sy OperatlOnivs nahi eked edit dil ae ie eed eee 6 d SOMWANEC oak aaa a AAR vacdunaeedessaelvaedatarvensacalvecduday eaddethvaadatadvens 8 He a 0 E DE 1 Ee E E E A E T 11 6 POOMSE a 14 REJ06B0357 01000 Rev 1 00 March 2004 Page 1 of 17 2CENESAS ae Asynchronous Serial Data Transmission Reception 1 Specifications As shown in figure 1 asynchronous serial data transmission is performed using channel 1 chl of the SCI module of the SH7145F In this task example 3 bytes of serial data are received by the SH7145 and the receive data is then tran
11. age 5 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 3 Operation Figure 3 shows the operation of asynchronous mode data transmission in the task example To help explain figure 3 table 3 lists the software and hardware processing that is performed 1 3 2 4 Start Data Stop Start bit bits bit bit i 0 1 0 Data bits DO to D7 RDRF SSR_1 bit Receive operation Transmit operation TDR_1 register TSR_1 register TXD1 pin TDRE SSR 1 bit Notes 1 The start bit transmit data parity bit and stop bit are output in that order from the TxD1 pin 2 To perform continuous reception read data transferred to RDR until reception of next data is complete Figure 3 Data Transmission Operation REJ06B0357 01000 Rev 1 00 March 2004 Page 6 of 17 u ENESAS SH7145F Asynchronous Serial Data Transmission Reception Table3 Processing Software Processing 1 Hardware Processing RSR 1 receives serial data and transfers it to RDR 1 Set RDRF flag in SSR 1 to 1 Read data from RDR 1 Clear RDRF flag in SSR 1 to 0 Clear TDRE flag in SSR_1 to 1 Transfer data from TDR_1 to TSR_1 2 3 4 5 Write receive data to TDR_1 6 7 8 Set TDRE flag in SSR_1 to 1 and output transmit data from pin TXD1 RSR_1 receives serial data and transfers it to RDR_1 Set RDRF flag in SSR_1 to 1 Read data from
12. er configuration allowing continuous reception of data RDR_1 is a receive only register so it can only be read by the CPU Transmit Shift Register TSR_1 This register is used to transmit serial data In order to transmit data the data is first transferred from the transmit data register TDR_1 to TSR_1 Then the transmit data is output from the TxD 1 pin TSR_1 cannot be accessed directly by the CPU Transmit Data Register TDR_1 Data to be transmitted is stored in this 8 bit register When it is detected that TDR 1 is empty data that has been written to TDR 1 is automatically transferred to TSR_1 TDR_1 and TSR I are in a double buffer configuration This allows data to be transferred to TSR 1 after one frame of data has been transmitted and the next frame of data is still being written to TDR 1 making possible continuous transmission of data It is always possible to read or write to the TDR from the CPU but before writing to the TDR it should be confirmed that the value of the TDRE bit in the serial status register SSR 1 is 1 Serial Mode Register SMR 1 This 8 bit register is used to select the serial data communication format and the clock source for the on chip baud rate generator Serial Control Register SCR 1 This register is used for transmit and receive control interrupt control and to select the transmit and receive clock source Serial Status Register SSR 1 This register comprises the SCI1 status flag a
13. formed by hardware REJ06B0357 01000 Rev 1 00 March 2004 Page 10 of 17 u SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 5 Flowcharts 1 Main Routine TE Initialize SCI module Pew Pea Pew T ee eee Receive 1st byte of data r tk Receive 2nd byte of data ee eee Receive 3rd byte of data REJ06B0357 01000 Rev 1 00 March 2004 Page 11 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 2 SCI1 Initialize Routine Cancel SCI1 module standby status Clear to 0 bits TIE RIE TE RE MPIE and TEIE in SCR 0 Select on chip clock as clock source using CKE1 and CKEO in SCR 0 Using SMR 1 select asynchronous mode 8 data bits no parity 1 stop bit and Po as baud rate generator clock source Using BRR 1 set communication speed to 19 200 bps Using DIR bit in SDCR 1 select LSB first communication Wait a 1 bit transfer time Yes Using SCR 1 enable ERI interrupt Using PACRL2 set PA3 pin 133 to RXD function and PA4 pin 134 to RXD function Set bits TE and RE in SCR 1 to 1 to enable transmit operation and receive operation RTE REJ06B0357 01000 Rev 1 00 March 2004 Page 12 of 17 4 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 3 Data Receive Routine o RDR 1 finishes receiving data Read receive data from RDR 1 and store it
14. nd the transmit and receive multiprocessor bits TDRE RDRF ORER PER and FER can be cleared only Serial Direction Control Register SDCR 1 This register is used to select whether the LSB or MSB is first For 8 bit communication either LSB first or MSB first may be selected but LSB first should be used for 7 bit communication REJ06B0357 01000 Rev 1 00 March 2004 Page 4 of 17 4 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception e Bit Rate Register BRR_1 This 8 bit register is used to adjust the bit rate The SCI has independent baud rate generators for the individual channels allowing different bit rates to be set for each See the hardware manual for details on setting values execution rate relationships etc Table 2 shows the function allocations for the task example Table 2 Function Allocations Function Classification Function Allocation TXD1 Pin Channel 1 transmit data output pin RXD1 Pin Channel 1 transmit data input pin SMR_1 SCH Sets communication format to asynchronous mode SCR 1 SCH Enables transmit operation SSR 1 SCH Status flag showing SCI1 operation status SDCR 1 SCH Specifies LSB first BRR 1 SCH Sets communication bit rate TSR 1 SCH Register for transmitting serial data TDR 1 SCH Register for storing transmit data RSR 1 SCH Register for receiving serial data RDR 1 SCH Register for storing receive data REJ06B0357 01000 Rev 1 00 March 2004 P
15. re may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corp is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the
16. smitted The communication format is 192 000 bps 8 bit one stop bit and no parity Serial data transfer 3 3 V target MCU 33V SH7145 Figure 1 Asynchronous Serial Data Transmission Reception by SH7145 Table 1 Asynchronous Serial Data Transmission Format Format Item Setting Bit rate 19200 bps Data length 8 bits Parity bit No Stop bit 1 bit Serial parallel conversion format LSB first REJ06B0357 01000 Rev 1 00 March 2004 Page 2 of 17 4 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception 2 Functions Used In this task example the SCI Serial Communication Interface is used to perform asynchronous serial data transmission reception Figure 2 shows a block diagram of channel 1 ch1 of the SCI module The functions of the elements shown in figure 2 are described below SCIO synchronous serial transfer function block On chip peripheral clock Po 128 P9 32 Po 8 Pot p Transfer rate generator SCI1 clock I O pin SCK1 o Baud rate generator External Bit rate register 1 clock Clock r Transmit receive operation control settings Serial mode register 1 SMR_1 Interrupt requests Serial control register 1 TEL 1 Transmit receive SCR 1 control circuit Serial status register 1 SSR 1 ERI 1 Serial direction control register 1 SDCR 1 SCI1 transmit data output pin Transmit shift register 1
17. th enabled in asynchronous mode only 1 stop bit transmission and reception when 0 REJ06B0357 01000 Rev 1 00 March 2004 Page 9 of 17 2 SH7145F E N ESAS Asynchronous Serial Data Transmission Reception Register i Bi Set Value Function SMR_1 MP 0 Multiprocessor mode enabled in asynchronous mode only Multiprocessor communication disabled when 0 CKS1 0 Clock select 1 0 CKS2 0 When value is 00 Po clock selected using on chip baud rate generator as clock source BRR_1 H 40 Bit rate register 1 8 bit register for adjusting bit rate SDCR_1 H F2 Serial direction control register 1 DIR bit bit 3 selects LSB first or MSB first In task example DIR 0 LSB first SSR_1 H xx Serial status register 1 Comprises SCI1 status flag and transmit and receive multiprocessor bits Only 0 may be written to the status flag to clear it TDRE Transmit data register empty status flag RDRF Receive data register full status flag ORER Overrun error status flag FER Framing error status flag PER Parity error status flag TEND k Transmit end status flag MPB 0 Multiprocessor bit MPBT 0 Multiprocessor bit transfer PACRL2 PA4MD1 0 Port A control register L2 PA4MDO 1 Function setting for port A multiplex pin TXD1 PA3MD1 0 Port A control register L2 PA3MDO 1 Function setting for port A multiplex pin RXD1 Can only be cleared to 0 Setting to 1 is per
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