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Philips UDA1334BT User's Manual

1. THD N S total harmonic distortion plus noise to signal ratio fs 44 1 kHz at 0 dB fs 44 1 kHz at 60 dB A weighted fs 96 kHz at 0 dB fs 96 kHz at 60 dB A weighted signal to noise ratio fs 44 1 kHz code 0 A weighted fs 96 kHz code 0 A weighted channel separation power supply rejection ratio fripple 1 kHz Vripple 30 mV p p dB 14 2 3 0 V supply voltage Vopo Vppa 3 0 V fi 1 KHZ Tamb 25 C Ri 5 kQ all voltages with respect to ground pins Vasa and Vssp unless otherwise specified SYMBOL DAC PARAMETER CONDITIONS Vo rms output voltage RMS value unbalance between channels at 0 dB FS digital input THD N S total harmonic distortion plus noise to signal ratio fs 44 1 kHz at 0 dB fs 44 1 kHz at 60 dB A weighted fs 96 kHz at 0 dB fs 96 kHz at 60 dB A weighted signal to noise ratio fs 44 1 kHz code 0 A weighted fs 96 kHz code 0 A weighted channel separation power supply rejection ratio fripple 1 kHz Vripple 30 mV p p dB 2002 May 22 13 Philips Semiconductors Product specification Low power audio DAC UDA1334BT 14 3 Timing Vopo Vppa 1 8 to 3 6 V Tamb 20 to 85 C Ri 5 KQ all voltages with respect to ground pins Vssa and Vssp unless otherwise specified note 1 SYMBOL PARAMETER CONDITIONS MIN TYP
2. WS DIGITAL INTERFACE DATAI SYSCLK MUTE INTERPOLATION FILTER SFORO DEEM PCS NOISE SHA VOUTL VOUTR MGU676 Fig 1 Block diagram 2002 May 22 5 Philips Semiconductors Low power audio DAG 7 PINNING Product specification UDA1334BT B W 5 V tolerant digital input pad note 1 SYMBOL PIN PAD TYPE DESCRIPTION CK 5 V tolerant digital input pad note 1 bit clock input S word select input 5 V tolerant digital input pad note 1 serial data input 1 2 4 5 Vppp digital supply pad digital supply voltage Vssp digital ground pad digital ground SYSCLK 6 5 V tolerant digital input pad note 1 system clock input SFOR1 7 5 V tolerant digital input pad note 1 serial format select 1 MUTE 5 V tolerant digital input pad note 1 mute control 8 DEEM 9 Pos i SFORO 1 5 V tolerant digital input pad note 1 3 level input pad note 2 digital input pad note 2 de emphasis control power control and sampling frequency select serial format select 0 Vref DAC analog pad analog supply pad DAG reference voltage DAG analog supply voltage analog output pad analog ground pad DAG output left DAG analog ground 12 Vppa 13 j Vssa 15 i Notes analog output pad DAC output right 1 5 V tolerant is only supported if the power supply voltage is between 2 7 and 3 6 V For lower power supply voltages this is
3. 1 All supply connections must be made to the same power supply 2 Short circuit test at Tamb 0 C and Vppa 3 V DAC operation after short circuiting cannot be warranted 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling However it is good practice to take normal precautions appropriate to handling MOS devices 11 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rin a thermal resistance from junction to ambient in free air 145 K W 12 QUALITY SPECIFICATION In accordance with SNW FQ 611 D 13 DC CHARACTERISTICS Vopo Vppa 2 0 V Tamb 25 C Ri 5 KQ all voltages with respect to ground pins Vssa and Vs5sp unless otherwise specified SYMBOL PARAMETER CONDITIONS min typ max UNIT Supplies Vppa DAG analog supply voltage note 1 1 8 2 0 3 6 V IDDA DAC analog supply current normal operating mode at 2 0 V supply voltage 2 3 mA at 3 0 V supply voltage 3 5 mA Sleep mode at 2 0 V supply voltage 125 uA at 3 0 V supply voltage 175 uA 2002 May 22 11 Philips Semiconductors Product specification Low power audio DAC UDA1334BT SYMBOL PARAMETER CONDITIONS lbop digital supply current normal operating mode at 2 0 V supply voltage at 3 0 V supply voltage Sleep mode at 2 0 V supply voltage clock running no clock running Sleep mode at 3 0 V supply voltage clock runni
4. INTEGRATED CIRCUITS DATA SHEET lana ITSTREAM CONVERSION UDA1334BT Low power audio DAC Product specification 2002 May 22 Philips PHILIPS Semiconductors DH l LI E Philips Semiconductors Bk Low power audio DAC Product specification UDA1334BT CONTENTS 13 1 FEATURES ae 14 1 1 1 General 14 2 1 2 Multiple format data interface 143 1 3 DAC digital sound processing j 1 4 Advanced audio configuration 15 2 APPLICATIONS 16 3 GENERAL DESCRIPTION 17 4 ORDERING INFORMATION 17 1 5 QUICK REFERENCE DATA 17 2 6 BLOCK DIAGRAM 17 3 7 PINNING 17 4 8 FUNCTIONAL DESCRIPTION IR 8 1 System clock 8 2 Interpolation filter 18 8 3 Noise shaper 19 8 4 Filter stream DAC 20 8 5 Power on reset 8 6 Feature settings 8 6 1 Digital interface format select 8 6 2 Mute control 8 6 3 De emphasis control 8 6 4 Power control and sampling frequency select 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION 2002 May 22 2 DC CHARACTERISTICS AC CHARACTERISTICS 2 0 V supply voltage 3 0 V supply voltage Timing APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS Philips Semiconductors Low power audio DAG 1 FEATURES 1 1 General e 1 8 to
5. MAX UNIT System clock timing see Fig 6 Tsys system clock cycle time fsys 512fs tcwH system clock HIGH time fsys lt 19 2 MHz fsys gt 19 2 MHz Low system clock LOW time fsys lt 19 2 MHz fsys gt 19 2 MHz Reset timing treset reset time us Serial interface timing see Fig 7 feck bit clock frequency 64f Hz bit clock HIGH time 50 ns teckL bit clock LOW time 50 ns tr fall time 20 ns 0 ns th DATAI hold time data input tsu ws set up time word select 20 ns Iwer hold time word select 10 ns Note 1 The typical value of the timing is specified at fs 44 1 kHz sampling frequency 2002 May 22 14 Philips Semiconductors Product specification Low power audio DAC UDA1334BT MGR984 Fig 6 System clock timing WS BCK tsu DATAI gt gt th DATAI lt _ Ty BOK MGL880 Fig 7 Serial interface timing 2002 May 22 15 Philips Semiconductors Product specification Low power audio DAC UDA1334BT 15 APPLICATION INFORMATION analog digital supply voltage supply voltage R7 R6 cg 12 o 12 Fe H uF system R5 SYSCLK clock Iro VOUTL rf R3 left if pe output 47 uF 100 Q E new Ri 220kQ CIS 10n 63 V 77 72 VOUTR Ei R4 right UDA1334BT T output 47 uF 100 Q
6. 3 6 V power supply voltage Integrated digital filter plus DAC Supports sample frequencies from 8 to 100 kHz Automatic system clock versus sample rate detection Low power consumption No analog post filtering required for DAC Slave mode only applications Easy application 5016 package wech 2 Multiple format data interface 12S bus and LSB justified format compatible 1f5 input data rate 1 3 DAC digital sound processing Digital de emphasis for 44 1 kHz sampling rate Mute function 1 4 Advanced audio configuration High linearity wide dynamic range and low distortion Standby or Sleep mode in which the DAG is powered down 4 ORDERING INFORMATION TYPE Product specification UDA1334BT BITSTREAM CONVERSION 2 APPLICATIONS This audio DAC is excellently suitable for digital audio portable application such as portable MD MP3 and DVD players 3 GENERAL DESCRIPTION The UDA1334BT supports the 12S bus data format with word lengths of up to 24 bits and the LSB justified serial data format with word lengths of 16 20 and 24 bits The UDA1334BT has basic features such as de emphasis at 44 1 kHz sampling rate and mute PACKAGE NUMBER DESCRIPTION VERSION UDA1334BT 2002 May 22 plastic small outline package 16 leads body width 3 9 mm SOT109 1 Philips Semiconductors Product specification Low power audio DAC UDA1334BT 5 QUICK REFERENCE DATA SYMBOL PARAMETER CONDI
7. 8 652 90011 There is no soldering method that is ideal for all surface mount IC packages Wave soldering can still be used for certain surface mount ICs but it is not suitable for fine pitch SMDs In these situations reflow soldering is recommended 17 2 Reflow soldering Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example convection or convection infrared heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 220 C for thick large packages and below 235 C for small thin packages 17 3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed 2002 May 22 18 Product specification UDA1334BT If wave soldering is used the following conditions must be observed for optimal results e Use a double wave soldering m
8. TIONS Supplies Vppa DAG analog supply voltage digital supply voltage S DAG analog supply current normal operating mode Sleep mode BS 125 uA digital supply current normal operating mode Sleep mode clock running no clock running ambient temperature Digital to analog converter Vppa Vppp 2 0 V Vo rms output voltage RMS value at 0 dB FS digital input note 1 THD NJ S total harmonic fs 44 1 kHz at 0 dB distortion plus noise to signal fs 44 1 kHz at 60 dB A weighted ratio fs 96 kHz at 0 dB fs 96 kHz at 60 dB A weighted signal to noise ratio fs 44 1 kHz code 0 A weighted channel separation Digital to analog converter Vppa Vppp 3 0 V output voltage RMS value at 0 dB FS digital input note 1 THD NJ S total harmonic fs 44 1 kHz at 0 dB distortion plus noise to signal fs 44 1 kHz at 60 dB A weighted ratio fs 96 kHz at 0 dB fs 96 kHz at 60 dB A weighted signal to noise ratio 44 1 kHz code 0 A ene channel separation Power dissipation at f 44 1 kHz power dissipation playback mode at 2 0 V supply voltage at 3 0 V supply voltage Sleep mode at 2 0 V supply voltage clock running no clock running Note 1 The DAC output voltage scales proportionally to the power supply voltage 2002 May 22 4 Philips Semiconductors Product specification Low power audio DAC UDA1334BT 6 BLOCK DIAGRAM
9. be supported for power supply voltages down to 2 4 V For lower voltages in 192f mode the sampling frequency should be limited to 55 kHz 2 Not supported in the low sampling frequency mode An example is given in Table 2 for a 12 228 MHz system clock input 2002 May 22 Product specification UDA1334BT Table 2 Example using a 12 228 MHz system clock CLOCK MODE 128f 192f SAMPLING FREQUENCY 96 kHz 64 kHz 48 kHz 32 kHz 24 kHz 16 kHz 256f 384f 512f 768fs Note 1 This mode can only be supported for power supply voltages down to 2 4 V For lower voltages in 192f mode the sampling frequency should be limited to 55 kHz 8 2 Interpolation filter The interpolation digital filter interpolates from 1fs to 64f by cascading FIR filters see Table 3 Table 3 Interpolation filter characteristics ITEM CONDITION VALUE dB Pass band ripple 0 to 0 45f 0 02 50 gt 0 55f 0 to 0 45f The 5th order noise shaper operates at 64fs It shifts in band quantization noise to frequencies well above the audio band This noise shaping technique enables high signal to noise ratios to be achieved The noise shaper output is converted into an analog signal using a Filter Stream DAG FSDAC Stop band Dynamic range 8 3 Noise shaper Philips Semiconductors Low power audio DAC 8 4 Filter stream DAC The FSDAC is a semi digital reconstruction filter that converts the 1 bit da
10. ering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 5 Wave soldering is suitable for LQFP TQFP and QFP packages with a pitch e larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 6 Wave soldering is suitable for SSOP and TSSOP packages with a pitch e equal to or larger than 0 65 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 5 mm 2002 May 22 19 Philips Semiconductors Low power audio DAC 18 DATA SHEET STATUS PRODUCT STATUS Development DATA SHEET STATUS Objective data Product specification UDA1334BT DEFINITIONS This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification product This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible Product data Production Notes This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at a
11. ethod comprising a turbulent wave with high upward pressure followed by a smooth laminar wave e For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end e Forpackages with leads on four sides the footprint must be placed at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications 17 4 Manual soldering Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 sec
12. ling rate in the noise shaper in order to improve the signal to noise ratio In this mode the oversampling ratio of the noise shaper will be 128f instead of 64fs ze AeW 2007 Ol ws ___ LEFT mer VL ANNAN LNR DATA seXeey EC seer CX OK OX OX duse 12S BUS FORMAT w f LEFT G EE RIGHT o T 2 WS fT RIGHT Ge T EKAA a Ze EE AE KEE EK DATA user X B3 X B4 X B5 X B6 X GE NG use B2 X B3 X B4 X B5 eek XereXiseX LSB JUSTIFIED FORMAT 20 BITS ws boxe LEFT a RIGHT o T BNS E NAAT NTAS ASNA SASA NS TN EP EE SG DATA use 82 X 83 Y B4 X B5 Y Be X B7 X B8 Yo XB10X ____ B23 Lse Xmse B2 X B3 Y B4 X B5 Y B6 X B7 Y B8 X B9 YB10X Xs23X isBX MGS752 LSB JUSTIFIED FORMAT 24 BITS Fig 5 Digital audio formats pya olpne Jamod MOT LEES LO SJOJONPUODILUAS Se uolyeayioeds JoNPOLId Philips Semiconductors Product specification Low power audio DAC UDA1334BT 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 60134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vop supply voltage note 1 4 0 V Txtal max maximum crystal temperature Tstg storage temperature Tamb ambient temperature electrostatic handling voltage human body model machine model Isc DAC short circuit current of DAC note 2 output short circuited to Vssa Ge 450 mA output short circuited to Vopa 300 mA Note
13. maximum 3 3 V tolerant 2 Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a maximum of 0 5 V above that level BCK ws DATAI VDDD UDA1334BT Vssp SYSCLK 6 SFOR1 MUTE 8 VOUTR VSSA VOUTL VDDA Vref DAC SFORO PCS DEEM MGU675 Fig 2 Pin configuration 2002 May 22 6 Philips Semiconductors Low power audio DAG 8 FUNCTIONAL DESCRIPTION 8 1 System clock The UDA1334BT operates in slave mode only this means that in all applications the system must provide the system clock and the digital audio interface signals BCK and WS The system clock must be locked in frequency to the digital interface signals The UDA1334BT automatically detects the ratio between the SYSCLK and WS frequencies The BCK clock can be up to 64f5 or in other words the BCK frequency is 64 times the Word Select WS frequency or less f ok lt 64 x fws Remarks 1 The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I O data interface 2 For LSB justified formats it is important to have a WS signal with a duty factor of 50 The modes which are supported are given in Table 1 Table 1 Supported sampling ranges CLOCK MODE SAMPLING RANGE 8 to 55 kHz 8 to 100 kHz 8 to 100 kHz 8 to 100 kHz 8 to 100 kHZME 8 to 100 kHz 128f Notes 1 This mode can only
14. new R2 220kQ C25 10n 63 V Ed 7 Vref DAC ce C7 100 nF 47 uF je V ii V MGU677 Fig 8 Typical application diagram 2002 May 22 16 Philips Semiconductors Product specification Low power audio DAC UDA1334BT 16 PACKAGE OUTLINE S016 plastic small outline package 16 leads body width 3 9 mm SOT109 1 y 1 Q A3 A nee na Le detail X 0 25 VE O SS scale DIMENSIONS inch dimensions are derived from the original mm dimensions A UNIT max A1 Az As bp c D EM e He 0 25 10 0 4 0 6 2 0 19 9 8 3 8 E 5 8 0 0100 0 39 0 16 0 0075 0 38 0 15 1 75 inches 0 069 Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT109 1 076E07 MS 012 EJ TE ISSUE DATE 2002 May 22 17 Philips Semiconductors Low power audio DAG 17 SOLDERING 17 1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages document order number 939
15. ng no clock running SE input pins note 2 HIGH level input voltage at 2 0 V supply voltage 1 3 3 3 V at 3 0 V supply voltage 2 0 5 0 V LOW level input voltage at 2 0 V supply voltage EE ee CCA ee at 3 0 V supply voltage 0 5 0 8 input leakage current 1 A 10 pF input capacitance ut pin PCS HIGH level EN voltage Vppp 0 5 V LOW level input voltage reference voltage output resistance on pin Vref DAC maximum output current THD N S lt 0 1 RL 800 Q load resistance load capacitance note 3 Notes 1 All supply connections must be made to the same external power supply unit 2 At3 V supply voltage the input pads are TTL compatible However at 2 0 V supply voltage no TTL levels can be accepted but levels from 3 3 V domain can be applied to the pins 3 When the DAC drives a capacitive load above 50 pF a series resistance of 100 must be used to prevent oscillations in the output operational amplifier 2002 May 22 12 Philips Semiconductors Low power audio DAG 14 AC CHARACTERISTICS 14 1 2 0 V supply voltage Product specification UDA1334BT Vopnp Vppa 2 0 V fi 1 KHZ Tamb 25 C Ri 5 kQ all voltages with respect to ground pins Vssa and Vssp unless otherwise specified SYMBOL DAC output voltage RMS value AVo PARAMETER unbalance between channels CONDITIONS at 0 dB FS digital input MIN TYP MAX UNIT
16. ny time in order to improve the design manufacturing and supply Changes will be communicated according to the Customer Product Process Change Notification CPCN procedure SNW SQ 650A 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this data sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors philips com 19 DEFINITIONS Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without f
17. onds between 270 and 320 C Philips Semiconductors Product specification Low power audio DAC UDA1334BT 17 5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD WAVE REFLOW BGA LBGA LFBGA SQFP TFBGA VFBGA not suitable suitable HBCC HBGA HLQFP HSQFP HSOP HTQFP HTSSOP HVQEN J not suitable 3 suitable PACKAGE HVSON SMS PLCC SO SOJ suitable suitable LQFP QFP TQFP not recommended 4 5 suitable SSOP TSSOP VSO not recommended suitable Notes 1 For more detailed information on the BGA packages refer to the LF BGA Application Note AN01026 order a copy from your Philips Semiconductors sales office 2 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 3 These packages are not suitable for wave soldering On versions with the heatsink on the bottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 4 If wave sold
18. set by control pins SFOR1 SFORO MUTE DEEM and PCS 8 6 1 DIGITAL INTERFACE FORMAT SELECT The digital audio interface formats see Fig 5 can be selected via the pins SFOR1 and SFORO as shown in Table 4 Table 4 Data format selection SFOR1 SFORO LOW LOW LOW HIGH HIGH LOW INPUT FORMAT 12S bus input LSB justified 16 bits input LSB justified 20 bits input HIGH HIGH LSB justified 24 bits input 8 6 2 MUTE CONTROL The output signal can be soft muted by setting pin MUTE to HIGH level as shown in Table 5 Table 5 Mute control MUTE LOW FUNCTION mute off HIGH 8 6 3 DE EMPHASIS CONTROL De emphasis can be switched on for fs 44 1 kHz by setting pin DEEM at HIGH level The function description of pin DEEM is given in Table 6 Table 6 De emphasis control DEEM FUNCTION LOW HIGH de emphasis off de emphasis on Remark the de emphasis function in only supported in the normal operating mode not in the low sampling frequency mode 2002 May 22 Product specification UDA1334BT 8 6 4 POWER CONTROL AND SAMPLING FREQUENCY SELECT Pin PCS is a 3 level pin and is used to set the mode of the UDA1334BT The definition is given in Table 7 Table7 PCS function definition FUNCTION normal operating mode low sampling frequency mode PCS LOW MID HIGH Power down or Sleep mode The low sampling frequency mode is required to have a higher oversamp
19. ta stream of the noise shaper to an analog output voltage The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier In this way very high signal to noise performance and low clock jitter sensitivity is achieved No post filter is needed due to the inherent filter function of the DAC On board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output The output voltage of the FSDAC scales proportionally with the power supply voltage Product specification UDA1334BT 8 5 Power on reset The UDA1334BT has an internal Power on reset circuit see Fig 3 which resets the test control block The reset time see Fig 4 is determined by an external capacitor which is connected between pin Vret pac and ground The reset time should be at least 1 us for Vref DAC lt 1 25 V When Vppa is switched off the device will be reset again for Vrernac lt 0 75 V During the reset time the system clock should be running RESET CIRCUIT 50 kQ UDA1334BT MGU678 Fig 3 Power on reset circuit VDDD V 3 0 VDDA V 3 0 Vref DAC V 1 5 1 25 0 75 0 gt a gt 1 us MGL984 Fig 4 Power on reset timing 2002 May 22 Philips Semiconductors Low power audio DAC 8 6 Feature settings The features of the UDA1334BT can be
20. urther testing or modification 2002 May 22 20 DISCLAIMERS Life support applications These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES 2002 May 22 21 Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES 2002 May 22 22 Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES 2002 May 22 23 Lett make t tt Philips Semiconductors

Philips UDA1334BT User's Manual

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