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Philips Q549.2E User's Manual

Contents

1.
2. A 1 2 3 4 5 6 8 9 10 11 12 13 14 1029 F5 5 6 1 06 F6 9E36 C6 1E50 D6 9E40 ANALOGUE EXTERNAL 0 SEATES HOTEL 1 1 11 F ek ee ee n Ms iudi 1 07 F1 2 11 1808 H1 9EA3 A11 1812 H9 9EA4 G11 B 2 1_ 24 av3 sTANDBY 2 03 9EA5 G11 B 1 79 2 2 09 12 9EA7 A11 74 4066___ AV1 B 9EA1 AV1 PB A
3. E EEEE an C gt pn 8 PERE 2 spud 7004 208 2900 s 16 Sa 9 LO i E RNC a gt RA 1 82 14 7005RA GA 7578 SSE 5 3103 02 T 81518 Elaa gt TM BA s 210 5 Tr WES m 59 e CO SES LO 340 3369 3384 5390 42100 io N ks 3124 8130 vs 5 88 818 181818 Tele ges
4. 1X09
5. 1 2 3 4 5 6 7 8 9 10 11 12 13 1 00 D9 2 00 4 2C01 D4 3 2 02 4 2 13 4 2 14 F5 2 15 5 PNX5100 SDRAM 2C16 F5 A A 2C17 5 2 18 6 1V8 PNX5100 1 8 5100 2 19 F6 2 29 10 5 PNXS100E 2 30 10 2 32 11 C PNXS100 DDR2 A0 DDR2 Y26 PNX5100 DDR2 D0 x _ 2033 F11 PNX5100 DDR2 A1 925 25 PNX5100 DDR2 D1 mss Ac 2C34 F12 PNX5100 DDR2 A2 5 2 PNX5100 DDR2 D2 8 8 428 2 35 F12 PNX5100 DDR2 A3 E 3 3 PNX5100 DDR2 D3 wor 2636 F12 PNX5100 DDR2 A4 e 4 PNX5100 DDR2 D4 PNXS100 DDR2 AS 2 T24 5 5 PNX5100 DDR2 D5 6 5 2 38 12 PNX5100 DDR2 A6 22 6 PNXS100 DDR2 D6 PNX5100 DDR2 VREF CTRL 4 PNX5100
6. NY 2009 May 08 1 2 3 4 5 6 7 8 10 11 12 13 1001 11 6 26 F12 LEE 1015 C12 6E29 H12 A 1022 A7 6E30 111 Vay ANALOGUE EXTERNALS 102387 6E3116 1024 B7 6E32 111 3E63 1025 6E34 E6 AP SCART QUT R 3E37 1027 D6 6E35 F6 1 0 mm 4708 mm SCART OUT 1028 E6 6E36 H7 150 5 lt sle 1E00A12 6 716 Pur 995 all 5 1 01 C14 7 01 1 A2 7 01 1 6 AP SCART OUT L Boe Sly res 555 5 8 res 8 1E02 C8 7 01 2 B2 5 ues 8 8 85558 LJ DEL pp 8 zE o 6 1 16 F7 7 05 H1 1 a i BCB478S COL 1E20 E22 1 18 12 7E09 H11 AUDIO IN2 rm 11 Fi AVI AUDIO R lt QEOT 1E19 G12 TE14 H5 5 amag 1602 2 1 sm 1E22 H13 7E15 C3 5 2 ge 1 23 111 9E10 13 15 140 16V ocx ole 2 hex slg gta mz
7. 1 2 3 4 5 6 7 8 9 2F62A6 9FG2 1 A2 2F63 A6 9FG2 2 A2 FPGA WOW LVDS IN OUT i 2F65A6 9FG24 A2 A 260 With FPGA RES 276546 9 2 4 A2 With FPGA No FPGA i 2F62 2F66B6 9FG3 1B2 a IX851A 9FG8 1 RX51001A 1 S RX51001A 2F67 B6 9FG3 2 B2 1 1 9 2268 B6 9FG3 3 2 52 2 RES _ de 2F70C6 9FG4 1 C2 9FG8 2 ABA 851 1 27982 RX51001A IXF1A 4 RES S 2F71 C6 9FG4 2 C2 I 2 64 4 7 2 72 6 9FG4 3 C2 a IX851B 9FG8 3 RX51001B TXF1B Se RX51001B 2F73 D6 9FG4 4 C2 B ETT 3 gt 2F74 D6 9FG5 1 E2 9 5 gt S re 2F75 D6 9FG5 2 D2 529 TX851B 9FG84 RX51001B 1 1 x RX51001B 2F76 E6 9FG5 3 D2 1 T igor 7 2F77E6 9 65 4 D2 3FH4 FFL3 RES SDA DISP gt Wy 2F78 E6 9 6 1 F2 3FF6 4 2F66 4p7 1008 2F79 9FG6 2 2 TX851C 4 RX51001C IXF1C
8. AEE 3310 7901 RES E LD2985BM18R Y y 100K RES 43V3 3 5 F300 gt OUT pe 1V8 a ae 4 808 8 6 Eu 7300 2 INH BP lg 8 2 LM393PT 818 8 47 7801 5 gle 8 5 F302 E amp 3 a OSX 8 52 4 859 8128 5 3V3 z 5 F303 1 2305 4 8 io 5 slcoct Y 8 8 8 5 2 gly Box 47K RES 7300 1 LM393PT PE wow FETA 828 1304 3318 F316 5 43V3 43V3 4 10K RES z 3V3 FEES gc 55 89 5258 2782 BES F304 1302 e x x x 5 6 5 8 2 2305 EX gt 1 9 J gt AE ud lt F306 p 1 B3B PH SM4 TBT LF x 8 8 88 E 3 5 8 5 5 asggsg fF 8 88 8528 82 8 9 8 8 8 x E LS 8 8 8 8 719 gt gt gt gt gt zd lt 55 528 x 5 7302 8 S L 8 s LPC2103FBD48_ NP S 5 g gt 88 E vss VSSA 5 8 x1 MicRO 5997xboMars
9. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2H00 C3 FHDO E13 A 2 01 FHD1 F11 2H03 F6 FHD2 D13 2 10 011 00 010 4 8543 STANDBY CONTROLLER 2H11H7 IHO1 D11 2912 H6 02 03 2 0 H13 1H03 010 2HDO F12 1804 G4 2 0 06 010 2 1 B3 1H07 D10 B 3H00 E2 08 H5 3H01 E2 09 C13 3H02 B11 14 F5 2 gd 7 00 6 3H03 B11 15 10 T PNX85439EH M2 24182 3H04 B11 1H16 F5 3H05 B11 17 65 3H06 C11 1H18 14 IXTAL 3H07 C11 19 F4 2 lo An io 3H08 C11 1H20 F7 3H32 aL wa AKT 5 1 501 SPL SDI 3H10 B2 21 12 ae 1 1 9 oL po ny STANDBY 3H12C12 26 4 BOLT ON TS ENn N BOLT ON TS ENn 21 3H02 RES B 3H13 B1 1H32 C10 gt 10K RESET NVM Act ALS 3 65 100R SCL UP MIPS 5 1 5 AA 3H14 B2 1H33 H7 REDDE 3Hi4 RES RESET PNX5100 RESET PNX5100 1
10. 1 2 3 4 5 6 7 8 9 10 11 12 13 noes A 1105 BS 9101 1 1 C1 9102 F5 1M2A G1 9103 F5 YIN MICROCONTROLLER BLOCK LITEON Hd 1 84 E1 9106 H8 2101 A6 9107 A5 2102 A7 9108 A5 B 2103 A8 9109 A5 B 2104 B7 9110 B5 2105 B10 9111 2106813 911282 33 ava 2107 11 9113 B3 LD2985BM18R 1 2108 12 9114 B2 1M83 Fil 2 E 2109 D7 9119 H6 F120 SCL NSCL SPI CLOCK 1 5 2110 D7 9121 G4 2 121 T SPLDATAJN NSPEDATA RETURN SDA d e IN sour 2 Ns 85 85 7116 2 2111 G4 C140 B10 3 122 e SDA 51913 4 915 815 5 9 22 LM393PT 2112 H7 F101 A8 C 4 F123 CONTROL 1 N CONTROL 1 SPI LATCH 116 gt amp 124 CONTROL 2 CONTROL 2 PWM CLOCK 815 5 2113 H7 F102 F5 F125 43V3 F108 2114 F9 F103 H7 6 gt 6 128 e _9113_ E 2115 F9 F104 5 pier 2116 9 F105 D7 8 e Xg 9 ESE 45822 2117 F9 F106 B12 10 gt 5 gt 2118 H8 F107 F130 VLED m 5 i ii amet T B 2119
11. 1 2 3 4 5 6 7 8 9 10 11 12 13 1 1 9102 5 1M2A G1 9103 F5 MICROCONTROLLER BLOCK LITEON 1 1 84 E1 9106 8 2101 9107 A5 2102 A7 9108 A5 2103 A8 9109 A5 B 2104 B7 9110 B5 2105 B10 9111 s 2106 B13 9112 B2 ave 2107 11 9113 LD2985BM18R RES A 2108 B12 9114 B2 210907 9119 H6 1 SPI CLOCK ETT 1 jw o gt 211007 9121 04 2 _9111_ 5 SPI DATA IN N SPI DATA RETURN SDA 41V8 8 8 7116 2 2111 04 C140 B10 SDA 39 se 8 8 815 2 8 82 LM393PT 2112 H7 F101 A8 4 54 CONTROL 1 CONTROL 1 SPI LATCH TT F116 T 5 CONTROL 2 CONTROL 2 PWM CLOCK COM 515 e 5 S 2113 7 F102 F5 pe 313 NTT F106 A 2114 F9 F103 H7 7 tt a m 2115 F9 104 5 8 LCS FOS ey wl 2116 F9 F105 D7 lt _ SFE 2 2117 F9 106 12 VLEDI 22 18 33 2118 H8 F107 C7 B 12 Y 2306 B 2119 H6 F108 D7 13 2120 6 F109 G3 D T 8 4 1105
12. Reset system is switched HIGH by the Reset system is switched HIGH by the Release reset MPEG4 module Reset system is connected USB rest 7 AVC at the end of the bootscript AVC at the end of the bootscript BOLT ON IO High 4to1 HDMI and channel decoder AVC releases Reset Ethernet when the AVC releases Reset Ethernet when the MPEG4 module will start booting end of the AVC bootscript is detected end of the AVC boot script is detected autonomously This cannot be done through the bootscript the is on the standby pP Reset Audio and Audio Mute Up are Reset Audio and Audio Mute Up are Wisi 060 ma Switched by MIPS code later on in the Switched by MIPS code later on in the Timing need to be updated if startup process startup process more mature info is available oe x Log SW event i 7 ae Bootscript ready POR polling positive sTi7100PorFailure in 1250 ms No Yes Wait 200 ms Y yes Set FC slave address of Standby to 60h Start alive polling ke yes POR poling positive RPC start comm protocol Timing needs to No Log
13. 1 2 3 4 5 6 7 8 9 10 11 12 13 Catered A 2150 4 20 6 2151 4 24 4 1 DEMODULATOR ey Gu 2753 B3 50 B8 2154 4 51 C3 2755 B3 52 C3 1750 2756 B4 FT53 C3 2157 B3 54 C3 12 275884 55 F7 3V3A 3V3D 3V3 1V2 3 3 2159 B3 FT56 G8 2T60 C8 FT57 G6 2751 2161 E10 FT58 H7 L kiei i 2T62 D12 FT59 I7 3150 2152 12 DRxse26K XK A2 gt 9 8 9 21288 8 Box BOX 2163 D9 FT60 C10 228 100p 2 VDDL 5528526 ARA 216426 Frei 011 805 Blas nes 3 9 kk jy 8 2165 G6 62 11 amo 9 8 ATN NTS aug 1755 9 rz zo 44 E 2T66 G6 FT63 16 F V e is 8 8 55 FE SOP 2167 G7 IT50 5 2208 100 8 E 5 MERR 9 FT50 2168 G7 51 5 aros 1756 2755 157 12 FE CLK 1 41 eS RES 3 DEMODULATOR MVAL 19 gt FE VALID 2168 G7 1783 B5 1 FE DATAO 21067 1155 4 Bos 100n HL s FE DATA 2171 68 1156 ams 52 1760 2 13 me a FE DATAZ 2172 G8 IT57 B4 PDN AAA ot 48 NIPD 5 14 F
14. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ort 1651 F14 FCAC D7 2 0 5 FCAD D7 2CA1 5 D7 2CA2 B5 FCAF D8 2CA3 5 FCAG D8 PNX5100 LVDS 2CA4 B5 FCAH D8 2 5 5 2 5 2 C5 2 C5 E7 2CA9 C5 FCAPE7 2CAA 05 FCAR E7 A DKA __ RES 2CABD5 FCAS B12 2CAS app 2CAC E5 FCAT B12 2 1 4 2 407 2CAD 5 FCAV C12 RES ses RES 2 5 FCAW C12 T 2CAF 5 FCAY C12 K 2CAG F5 FCAZ C12 IXB RES RES D 2224 I 2 5 2 2 2 2CAV 2CAJ F5 FCB1 C12 b 2 F5 2 12 M E is JB uus 888588888 FERESIS HF 2CAMG5 FCB3D12 PE E 2CAN G5 FCB4 D12 FI RE41S HF 961 4 so 51 E emn zahl ES 8 59 2CAP G5 5 012 D IX3C 8 B 595080504080 5711 2 5 FCB6 012 1 RES FCBN _ S 8 RSESERIESIERES s 2CAS A10 FCB7 D12 8 8 8 2CA5 47 las 2CAZ 47 SDA
15. 33 Bota 5A00 43V3 mPCI E x 1 1 5A01 45V mPCI EMT Py 1 4 AUDIO IN HDMI ho es atv 12V gt DDR SUPPLY USB CONNECTOR 48V3F 43V3F Bota e 45V 7A01 32 5 We gt BO6a e f a i 9 7A00 1 7A02 1V8 PNX85XX 4 74 1VB PNXB5XX 1V8 PNXB5XX teo ewaco 12V Botb 5 11 REF 3V3 307 waned 1 1Ve HDMI 28 7AT 2V5 REF jd ji RES M 8 L 3V3 STANDBY 3V3 STANDBY 45V B10A 3 47 45V EDID e 4AUDIO POWER AUDIO POWER AW 1 59 HDMI 3 AIN 5V BOib gt 4 OH Homia INTERFACE SINGLE DC DC cae BIN 5V CONNECTOR Bn m HDMI SIDE DIN 5V SUPPLY CONNECTOR 5102 424VF gt 1P02 1M59 HDMI 1 CNN TO 1 59 CONNECTOR SSB 312v 12V gt a 001 16 16 EIS wit 002 VLED2 E 1 84 5V EDID 5V EDID gt 6 06 AMBI LIGHT MODUL
16. 1 20 1 1 95 1 1 99 1 1001 2 1003 2 2U21 B1 2U22 D2 2U23 D2 2U24 A7 2025 B8 2026 9 2027 F7 2028 F8 2029 E8 2U2A 2U2B E8 2U2C B1 2U30 D2 2U31 D3 2U32 E1 2U33 F1 2U34 F1 2U35 F1 2U36 F1 2U37 C1 2040 2041 2 2042 2 2043 2 2044 2 2045 2 2046 2 2047 D8 2048 D8 2049 D7 2051 D1 2052 D1 2053 1 3035 6 3037 6 303 8 3U3W A8 3U3Y E6 3032 F6 3U40 E8 3U41 B5 3U42 E9 3U43 E8 3U44 E9 3U45 E9 3U46 A8 3U47 E8 3U4A 3U4B B4 3U55 C3 3U56 C3 3U57 C3 3U58 C3 3U59 B6 3U60 E5 3U61 E5 3U62 F5 3U63 F5 3U64 C2 3U65 C2 3U66 D1 3U67 D2 3U80 E3 3U81 E3 3U82 E4 3U83 E4 3U84 F2 3U85 F4 3U86 F4 3088 3U89 F3 3U90 A3 3U91 A3 3U92 A3 3U93 B2 3U94 B3 3U95 B3 3U96 A4 3U97 A4 3U98 C3 5U06 F2 5U07 A1 5U08 E7 5U10 A1 5U11A1 5U12 A1 5U13 A1 5U14 A1 5U15 B1 5U16 B1 5U17 F2 5U20 F2 5U21 F2 6U0B E8 6U0C 6040 700 9 B7 E7 7000 9 7010 4 7011 B3 7040 1 7040 2 4 7041 1 F4 7041 2 F5 7050 C7 9006 2 9007 B3 9008 B5 D1 CU71 D1 FU10 F1 FU11 F1 FU12 F1 FU13 C1 FU14 C1 FU15 C2 FU16 C1 FU17 C2 FU18 C2 FU19 C1 FU1A E1 FU1B E1 FU1C E1 FU1D F1 FU1F
17. IP14 1 HDMIA RX2 amp ERX DDC SCL 9P20 _ DDCA SCL 2 3 _ HDMIA RX2 JS ERX DDC SDA _9 19_ DDCA SDA 4 5 HDMIA RX1 4 iis 5 gt e 6 s HDMIA RX1 1 5 HDMIA RXO 5 8 515 15 9 re 10 lt HDMIA RXC 11 12 HDMIA RXC TM 13 PCEC HDMI 14 45 ERX DDC SCL 7 07 5 16 lt ERX DDC SDA M24C02 WDW6 lt lt oc 17 5 B 18 EIN 5V oot 19 7 ERX HOTPLUG EDID NVM 256x8 we HDMI 4 5 P524 2 11 po DC1ROT9WBER220 HDMI CONNECTOR 4 gt WiTEBROT ERX HOTPLUG x 5 IP68 aR lt lt HOT PLUG A lt 10K 829 52 EIN 5v B 3 M96 1 2 5 9P324 4 ERX HOTPLUG 3 2190322 02 pe EIN 5V 415 __ FP37 5 5 e5 2294 4 ERX DDC SDA PUE 6208 EIN 5V 6 gt e 9 P293 lt ERX DDC SCL 4 7 FP38 x 8 L BAT54 9 8 9 32 1 1 5 c PCEC HDMI 1 9P30 1 8 HDMIA RXC 2P23 11 12 5 2 9P302 7 5 HDMIA RXC pu 13 3 9 30 3 6 _ 44 5 4 9P304 522 HDMIA RXO 1 9P31 1 83 HDMIA RX1 15 85 HDMIA RXI T 16 2 9P31 2 7 lt HDMIA RX1 5V DDC 17 3 9 31 3 6 HDMIA RX2 18 4 9P31 4 55 HDMIA RX2 19 5 20 212 b3 2 l 524 726 9 28 13
18. AGC MPEG 2 Y DVB T QAM TS SAW FEC Lan gt 2 gt IFAMP ADC gt gt KH DVB T QAM ATV DAC gt Demodulator Stereo Decoder SIF Integrated Tuner DAC gt 5 Audio gt Presaw Sense System Controller GPIO Pin Configuration VSSAH_CVBS INP VDDAH_CVBS INN CVBS VSSAH_AFE1 SIF VDDAH AFE1 VSSAL_AFE2 VDDAL_AFE1 VDDAL_AFE2 VSSAL_AFE1 IF AGC RF AGC PDP PDN 11 LA L3 La 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 xi 49 32 RSTN xos 0000 31 saw_sw 88 OSC 51 30 GPIO2 VDDAH OSC 52 29 VSYNC 53 1 28 VSSL vssH 54 27 vssL ss 26 VDDL L 56 DRXK 25 VSSH 057 QAM I2C SDA1 58 23 2 5 1 0 59 22 MD7 21 12C_SDA2 61 20 MDS 12 _5 12 62 19 BSCE T 18 VDDH 128 DA 64 17 VSSH 123 4 5 6 7 8 9 10 11 12 13 14 15 16 a 128 WS 1 L VDDL VDDL VSSL VSSL MD3 GPIO1 MD2 MSTRT MD1 MERR MDO VSSH MVAL VDDH MCLK Figure 8 2 Pin configuration 2009 May 08 18440 300 090303 eps 090303 Data Sheets Q549 2E LA EM GEJ 8 3 Diagram SSB
19. A 1 2 3 4 5 6 7 8 9 10 11 12 13 eee A 1106 5 9101 5 1 1 1 9102 F5 1M2A G1 9103 F5 MB MICROCONTROLLER LITEON 1 1 84 1 9106 H8 2101 9107 A5 2102 A7 9108 A5 B 2103 A8 9109 A5 B 2104 B7 9110 B5 2105 B10 9111 2106 B13 9112 B2 avs ava 2107 11 9113 B3 7 A IN Y Y RES 2108 12 9114 2 1M83 210907 9119 H6 F120 sci ssc _9107_ SPI CLOCK 1 5 6 2110 D7 9121 G4 2 121 e SPEDATAN SPLDATA RETURN 9108 c SDA 85 8 gt 7116 2 2111 64 C140 B10 C 2 9 RES zz SDA 51813 lw g 4 815 815 5 8 LM393PT 2112 H7 F101 A8 4 Fe 27 CONTROL 1 ST AT 5 F124 o ZZ CONTROL2 CONTROL 2 2 2 PWM CLOCK 315 5 PN in ud geo i 125 7 E pne BLANK A 2115 F9 F104 F5 _ M F127 RES 7 EEPROM CS 8 14 2116 9 F105 07 9 Fraa TEMP SENSOR 2117 F9 106 12 10 e gt gt 2118 H8 F107 C7 F130 VLED1 8 43 11 e B 4 mis d D ia d ES gig 1105 3 ton RES 2121 H6 F112 G8 51 Be 5 5181 VLED1 VLED1 F 5 E slg 3138 2122 FO Fite 10 pleases i1 5 8 587 1 17 SEE
20. SINGLE 5108 RES VOS pe 16 30R or gt 1100 1100 5102 8 6 5 65 Eize eod BC St e lt SPI LATCH2CONN T3 0A 32V 10u ae 1101 109 1 84 els e T 1 2 9 2 0A T 63V lt gt SPI CLOCK BUF ATS C 5 e F102 lt SPI DATA OUT 505 3 5 e 103 SPI DATA RETURN 508 508 2 y F104 7 SPI LATCH1CONN L 2 PWM CLOCK BUF 4 12V F106 6 e 48V3 M 7 2 e 5108 BLANK BUF AA ea xy e F109 gt EEPROM CS RES sce scg B 9 TEMP SENSOR 208 508 1 111 2 PROG 11 44 eU ace 12 4 D 2 ros 7100 15 aven 29 NCP3163BMNR2G c F125 14 44 15 16 15 LPK SENSE LVI 19 502382 1470 502382 1470 3101 DRV_COL 12 SPI LATCH1 yee SWI_EMIT 12 79101 SPLLATCHICONN B 9102 5 SWI COL C 20 9103 RES 21 S998 9104 SP LATCH2CONN HOST 2 1 2459 x SPI LATCH2 _ 23 1 59 24 5 1 1 2 16V p gt 26 gt I a gt 4 id A A RES CONTROL1 28 8 lt 9 VV 3110 RES 2 CONTROL2 29 T 228 5 E 30 6 gt 43V3 2 8 si 7 1104 1735446 7 GND GND HS EE E 1 D Oy lt
21. FOE ral J 8 Big E lt z 8 Gets nc E 9 C LP il 2084 olf 8 g a A gt tea EX 5 oot 7 se E 5 Og ig 10 5 E um HE a g 8 024 pad war 4 BS je N EX d D og OQ il 7 p 9 fod a d pina ijt 1 w 4 zn 15 1 K et Gc E 1 32 B POS a VM Eas B 5 Hrs jr 90 ANa je A E Pe F 90a 93 D 72 080577 pe sree E Geel f 0111504 E ES 5 A Ei aa N on dr 183 4 PE 2 LL tdV P 6 BB am NS 00H VONZ i 77 z ig 2 N z 3 raat CUBO o Hi Jo 28 T z qw a ee TE x 2 E H 8 8 SUE SS 3277 of O DET ral lt 3 i 11 ig
22. 10000 012 090121 090121 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright 1 Circuit Diagrams and PWB Layouts Q549 2E LA __ SSB Temperature amp Fan control 10 11 12 13 gt PHILIPS UJ owner AN 2 3 4 JL Te TEMPERATURE 8 FAN CONTROL 1 01 49 12V 50 FAN1 DRV T 51 2 50 1u0 2F51 100p 2F52 1u0 1F02 12V 52 FAN2 DRV wns 1 Or 53 2 2F53 100 2F54 100 2F55 100 351 12V 1KO AA 3F59 SML 310 6F51 7F52 FAN1 DRV y 10 56 2 5 amp 1 51 3F53 1 52 7F53 BC857BW 10R RES FAN2 DRV y ofS IF55 7 55 BCP53 10R RES 3 IF56 3258 1 100R 100R 12V 3F52 10K 3260 1 0 1 J SML 310 7 50 u LM75ADP 3 05 3F61 IF63 1 3F62 VA 100R F65 2 gt V 100R 3F66 100R a IF67 3V3 FAN1 OUT FAN CTRL 1 1 9F51 3F68 3F64 RES NA 9F52 3F65 RES 1K0 FAN1 OUT TACH
23. RXC B N HDMI RXC B P RXO0 B B P HDMI RX1 B N RX1 B P HDMI RX2 B N HDMI RX2 B P RX2 A N RX2 A P HDMI RX1 A N RX1 N A 1 05 CVBS TER OUT 7 16 7 06 2 __ 1 01 1 Y_CVBS MON OUT SC Y CVBS MON OUT S lt DRX1 gt lt c_REGIMBEAU_CVBS SWITCH gt CONTROL 7E09 HDMI SIDE DRXC _s AV1 CONNECTOR gt gt m ANALOGUE EXTERNALSD E gt 1 2 ABO SEAL AVI PB E 5 AVI G m gt CRXO AV1 CVBS 9EA7 AV1 Y_CVBS un gt SCART s P HDMI 1 S 7E04 CONNECTOR 1P03 AV3_PB BRX2 gt Sm gt AV3 PR S AVY BRX1 EXT2 BRNO gt AV2 Y CVBS BRE gt AV2 BLK BRXC 2 gt gt BRXC 5 AV2 STATUS gt Dmm SCART2 CONTROL ANALOGUE EXTERNALS gt 1 05 _ gt G VGA B VGA ARXO ARKO gt H SYNC VGA_ S I Ane gt VSYNCVGA 5 HDMI 3 5 CONNECTOR CONNECTOR 1E03 AV4 PR AV4 PB CRX2 72 EXT3 Arce 1 04 gt fe
24. Alignments Q549 2E LA ESI GE The first line group 1 indicates hardware options 1 to 4 the second line group 2 indicate software options 5 to 8 Every 5 digit number represents 16 bits so the maximum value will be 65536 if all options are set When all the correct options are set the sum of the decimal values of each Option Byte OB will give the option number See Table 6 3 Option and display code overview for the options White Tone 32 37 Black level offset Diversity Colour Temp G B G B Not all sets with the same Commercial Number Normal 127 95 97 127 121 106 8 8 necessarily have the same option code Cool 127 100 112 124 127 119 8 8 Use of Alternative BOM gt an alternative BOM number usually Warm 17 89 52 qp er 8 8 indicates the use an alternative display or power supply This results in another display code thus in another Option code For White Tone 56 Black level the power supply there is no difference Refer to Chapter 2 offset Technical Specifications and Connections Colour Temp R G B R G EN LAS 6 4 5 Option Code Overview Cool 124 124 125 8 8 Warm 127 95 65 8 8 Table 6 3 Option and display code overview Option Settings CTN Options Group 1 Options Group 2 Disp code 32PFL9604H 12 08211 35971 18431 45288 30645 47282 00184 00000 181 Intr
25. CHN SETNAME CLASS NO 2 2008 11 21 DISPLAY INTERF PNX5100 TV543 R2 LDIPNX 8204 000 8928 2008 10 10 8 1 NAME Maelegheer Ingrid SUPERS 9 130 8 A2 CHECK DATE ROYAL PHILIPS ELECTRONICS 2008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310 525 090302 5 090302 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA E ZEHN SSB PNX5100 Debug All rights reserved Reproduction in whole or in parts 1 gt PHILIPS is prohibited without the written consent of the copyright owner 3CJ1C3 6CJ0C3 7CJ0D3 FCJOD3 B JEN 100 DEBUG RESERVED SML 310 SETNAME DEBUG SHEET PNX5100 TV543 R2 LDIPNX 2008 11 21 SUPERS CHECK DATE ROYAL PHILIPS ELECTRONICS N V 2008 1 2 3 4 5 6 18310 526 090302 eps 090302 2009 May 08 Personal Notes 10000 012 090121 eps 090121 Ali rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner 1 2 Circuit Diagrams and PWB Layouts Q549 2E LA 10 GHIA _ SSB FPGA Backlight LVDS
26. AUDIO IN3 L AA BTE ADAC 1 3HT8 4 33 ADAC 2 1 ADAC2 N mr 2HRS 3n3 2HRT 3n3 3 3 6 2HRE ones THRV RES 4 5 ALG p 2 2 SHRO2 2HRC 1 SARC TARY RES aap 2 ANG Vvs R 33K BHPS 1 SR ADAC3 5 2 33RV ADAC4 2HRG L 4 BHRI2 n p 7 UDIO INS L 1 THRU VaskT RES 335 i ABS 5 ADACSN 6 2HRJ RAIN 4 SHRU 4 I TART V Vask RES SHRI 3He2 5 ud A VDDA AUDIO ANA 1 33K 5 10 BPOIF IN ADACE N SPDIE IN1 5 T 15 4 las iN SCK ADAC7BUF ADAC8BUF AKI 5 1 1 52 128 IN ADAC 7 5 4 33R NAA 3HP1 AN9 AE AA T d 3HT8 2 F9 9 A A 3 8 2 ADAC 7 ALS 33R ADAC 8 iR 5 2 C10 SHRW D6 f 5HRZ D6 J 7H00 7 D7 7 C10 9H11 C4 G 9H12 4 FHPE C10 IH11 C10 IH13 C14 IHPD F9 IHRH C4 K IHRJ D4 G5 IHRL G6 L IHRM G6 IHRU F3 H IHRV E3 IHRW E3 L IHRY D3 IHRZ 50 D3 IHS1 03 IHSU C6 IHSV 0
27. _ 1 3Ve FPGA 3FN3 10K grag TE IO E2ILOPIFLASH CSO E NEE gt IO RS VREFB2N3 IO R2lLASP IO T4 VREFB3N3 IO UTIB26P 7 10 V12 VREFBANS IO UITIBATP AT TXBS2As T m ETILTONL S ATR ET 10_T3 L52P 1 T IO VTIB26N 07 XE T 10_V17 B47N IO 621 202 c NER S K2 L26P IO RaILS2NL rs TXFAE IFNA IO UBIB27P vs RoE TX852E P Vii 0 Uttie2eP IO RI3JB48N BS Msg __ 5 G1IL20N 8 XP IOLK1L26N I0 MS ha IFNS amp VAIBIN IO Ve B2TN v5 TX852E 012 10 111828 I0 H5 B io 2 2 5128 _ are US P lBeP 10_U2JPLL1_CLKOUTP v2 4 IFNG 012 110 0121829 1o_T13 RUP2 2 IO HSIDATAO 0 10_T RUP1 12 4 IFN2 UE V3 IO U3IBIP 1 CLKOUTN 2 e orm Vi3 0138322 He IO FaIVREFBIN1 TXPTBt L2 L2 La2P ___ IFN at Ud ValBt6N E gt wig 10 18 4 0 12 IFNA Hi 10_H6 VREFB1N2 GNDA1 TXF2B lt Va 10_U4 B17P IFN8 p O P10B33P IO 18 14 IFNB 10_H1 VREFB1N3 V4 B17N IFN9 4 P11 B33N GNDAS a 8 1V2 PLL 2V5 PLL 1V2 PLL 2V5 PLL DS CLK OUT2 PNX5
28. 1 2 3 4 5 6 7 8 2HF5 D7 2HF6 D7 2HF7 D7 3HES 1 C5 3HES 2 B5 8543 CONTROL miden 3HES 4 C5 3HEU B3 3HF2 E2 3HF4 E2 3HF5 C3 3HFD 1 A6 PCI DEVSEL 4 5 A AA A 3HFD 2 A5 PCI FRAME 3HFD 31 8 1 3HFD 3 A6 7H00 3 PCIHIRDY 2 2 7 2 4 3 3HFD 4 5 85439 2 24182 PCI TRDY 3HFD 3 6 3 3HFE 1 AG PCI 5 2 7 2 2 4 7 PCI ADO A29 221 PCI PERR 2 _ 76 3 1 3HFE 2 A6 PCI AD1 B29 4 4 C21 PCLCBE4 PCI SERR 18 1 3HFE 3 A6 PCI AD2 C29 2 PCI CBE 2 B21 PCI CBE2 E VAKT 3HFG D2 PCI AD3 D29 3 A21 PCI CBE3 3HFH E2 PCI AD4 228 4 m 3HFK E7 PCI ADS 5 lt PCI CLK PNX8535 E7 PCI AD6 C28 25 PCI DEVSEL 6 DEVSEL 7 PCI AD7 028 7 FRAME C26 PCI FRAME PCI AD8 E28 5 IDSEL B20 SA BHEU lt PCI AD24 3HFP E7 PCLAD9 8 NTA our 230 1008 Y 0 5 PCI AD10 B27 22 PCLIRDY 7H00 3 2 PCI AD11 C27 14 PAR 225 PCI PAR 7HF1 D6 PCI AD12 D27 TRDY C25 PCI PERR 9HF6 PCI REQ ETH PCI AD13 E27 12 PERR D25 PCI SERR 2 7 3HES 2 gt 9 4 6 5 13 SERR 7 PCI AD14 26 4 B25 PCI STOP AKT Y 9HF5 C6 PCI AD15 B26 E26 PCI TRDY _9 7_ PCI GNT ETH 9HF6 B6 E24 PCI AD TRDY SHES3 PCI AD16 16
29. H H US PANEL zi J 9 LEDS 2K9 3104 313 6344 i N gt J B 2009 May 08 090508 Circuit Diagrams and PWB Layouts Q549 2E LA E ELA Layout guide panel 3104 313 63441 Position leon 18009 P me 7 3 1 043 1 36344 1 1831 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA GLE Wi Fi Antenna Layout Wi Fi Antenna E i 2 2 6 E 3104 313 63282 A A S 1 N PHILIPS UJ 1000 B1 a 3104 313 6328 2 is prohibited without the written consent of the copyright All rights reserved Reproduction in whole or in parts owner 41 1000 NJ U FL R SMT 1 10 3 n ee SETNAME e WIFI antenna EU 3104 303 5212 T CLASS_NO 08 07 07 08 10 20 Maelegheer Ingrid SUPERS 1 DATE tme ROYAL PHILIPS ELECTRONICS 2008 1 2 3 4 5 6 18310 640 090306 eps 090306 2009 May 08
30. 7 i 15502 5201 O 14 1 0 G D 5201 gt 5 1 85 2203 6201 2209 835 6201 95 E deco e 9104 7200 221 2 EEL 8 2301 SIS T 2302 3306 155 O gt 1 a AT 3 Ql 2218 LR 8 AR 2319 N 1 gt 8324 1 9201 18 3326 9202 2312 6200 s gt 2 2206 RIBER Q 1 ilc O Ec 4 N E 58 85200 2 2207 5200 TM84 Pi Pos Rao ONU 2108 m Gn 2 3109 8110 AU Ne 5106 5103 8 5105 5104 UN IS 75205 3300 1j S m 215 213
31. 51 19 ANALOGUE EXTERNALS NCC En GE 8 42 cvBs BRX2 lt 41 SIDE FRONT C BR 39 1V8 PNX85XX yo 4 gt BR al 36 a SVHSIN 5 BR 35 15 21 34 40 64 70 85 88 H A eor ad EA Hom swircH HDMIB RXC HDMIB RXO N HDMIB RX0 N HDMIB RX1 16 HDMIB RXI gt HDMIB RX2 HDMIB RX2 RREF PNX85XX HDMI SWITCH 1 06 HDMIA PX2 HDMIA RX2 HDMIA RX1 HDMIA RX1 HDMIA RX0 S HDMIA RX0 _ 2 HDMIA RXC S Hou HDMIA RXG S CONNECTOR AP18 TO DISPLAY LLL gt 1080 50 60Hz N C pee wis QUADLVDS 1651 d 1920x1080 100 120HZ LOUT2_B_N AES a C N AN28 TX882C 2 vo PF Lour 22 20 lt N gt 81 IOU DN TODSPLAY CULA 1080p 100 120H2 Dana 114 10 8 7FNO EP3C25F324C7N 1 24__ 852 AK19 LVDS VDDA 3V3 AADC VDDA 3V3 ADAC VDD 3V3 LVDS VDDA HDMI 3V3 BIAS VDD 3V3 SBPER VDD 1 2 CORE VDD 1 2 SBCORE VDD 3V3 PER VDD 1V8 DDR USB FAULT LOUT2 CLK P VDDA LVDS 7FLO EDD1216AJTA FPGA LOCAL CONTRAST LVDS IN OUT i JUMPERS IN CASE O
32. D2 94 HDMIB RX2 5 DDC SCL J DAT 6 DDC SDA PD 48 FP44 R12K 74 IP17 4 L 2656 12K 1 4 10 Toon AIN 5V 5V 32 RX DDC SCL DAT ARX DDC SDA HPD ARX HOTPLUG 772 57 29 100 BIN 5V BRX DDC SCL BRX DDC SDA DAT BRX HOTPLUG HPD CIN 5V CRX DDC SCL CRX DDC SDA CRX HOTPLUG DIN 5V DRX DDC SCL DRX DDC SDA HPD DRX HOTPLUG DDC BAT54 COL STBY TEST NC 5 15 100 c PCEC HDMI 3P47 30R ART 5V EDID 1X07 EMC HOLE 10 11 12 13 14 2 48 5 2 49 6 2 50 012 2 51 012 2 52 013 2 53 013 2 54 013 2 55 013 2 56 12 2 57 12 2 58 G12 2 59 G12 3P14 F13 3P34 E14 3P36 F14 3P38 H6 3P43 E9 3P47 H14 3P53 H5 3P58 B4 3P61 B4 3P63 D4 3P64 D4 3P65 14 3P66 14 67 3P68 G3 3P75 G5 3P76 9 3P77 9 5 08 C12 5 11 B10 5P12 C10 5P13 C10 5 14 10 5 15 H13 6P03 G13 7 01 7 02 010 7 12 5 7P32 G6 9P0J G7 9P33 E9 BP1A F2 BP1B F1 BP1C F2 BP1D F1 BP1EF2 BP1F F1 BP1G F2 BP1HF2 BP1JA2 BP1K A2 BP1LA2 BP1M A2 BP1N A2 BP1P
33. 4 3 60 9 IT88 F6 ANTENNA SUPPLY x m 68R T 3T61 C4 IT89 F3 5V TUN 5 me 77 4 3T62 C9 IT90 F3 G 9 ele V 813 78 96 pis 3163 ITO1 F4 BAS KTS 15 97 1 3 64 9 IT93 G2 80 98 4 pie SA 7753 4 8 8 na 58 ome Bal ESS 3T65 C9 1194 G3 sis 82 5 8 100 5 19 BC857BS COL 3T66 1D4 1195 G3 8 5 5 5 2 2 2 161 3175 s cot 3T66 2D4 IT96E11 E Ye BC847BPN COL 3 Apc 3T66 3 D3 IT97 E11 4 8 90 Q 09 vssH vss 5 mes ed 5V TUN CVBS E 3166 4 04 IT98 5 SERB eme 8 A me CVBS TER OUT 3T67 D4 sme UM eum PRE ison 1808 peel 3 68 2 Hav m 3 95 1797 ma 3 69 2 3 lt Sa 5 RES 558 3170 09 gle asf 45 1 528 100R BC857BS COL 3174 D9 8 STR 3784 2918 ft 31729 M AA 1 3173 E11 BAS316 22 1V2 PNXB5XX e 3174 E12 TIN RESERVED 1 3 75 9 S28 BON 3176 9 7155 1 333 OUT p 2 3T77 E9 ET n mit ue nes 3780 A9 amp 8 3781 A9 BS Bog 3 82 9 9 8 i 3783 pi um 3186 F3 J 1 L L HV2 e gt et elacissis 3788 F5 E 872 amp 8h 8658 3789 F3 Y tly 3 G IT
34. T m 7116 1 1 ll 2125 F120 A1 l 1 1 EE ae 72 2126 F10 F121 A1 i 3141 2127 1 F122 At E FUB 2 1 2128 1 F123 A1 E 7 343 ava gt lt 30 RES 2129 B2 F124 B1 2 SDA g 2130 F2 F125 B1 3 ese H CONTROL 1 454 8 8 2131 F10 F126 B1 CONTROL 2 5 PESCE g 3101 2 D7 F127 B1 5965 252538 3101 3 D9 F128 1 n 3101 4 9 129 1 TEMP SENSOR 3102 1 D9 F130 B1 9 e 10 gt PROG ius SoS LER 8 3102 2D9 1 1 1 n pue 3102 3 E9 1 2 B1 12 4 3102 4 D9 F133 E1 a pe 1 o 2 F108 e LL le 3103 1E9 F1 514 e 3103 2 010 1 5 1 228228 amp 3 B E Bs 3103 3 611 F136 F1 5 gt s 3B 5 s 8 3103 4 610 F137 F1 3104 1 08 F138 1 ls e a 2 E 3104 2 EB F139 F1 5 3104 3 E8 1110 G8 5 x 86 25155 88 S LS 31044D9 1111098 G g78 8 22 gt 2 gt 3105 1 9 1113 610 4 3105 2 1114 610 fo Joo x 3105 3 EB 1115 610 1 L E 5 3105 4 1124 E11 7102 5 1 210 048 2 5 gt 8 5 8 3106 1E8 1125 E11 Vash gt S Ss 5 5 5 3106 2 08 1126 F11 5 3106 3 MicRO
35. is 5 3107 C7 m See 20607 515 PO2ISCLOICAPOO 2 3128 1008 PWM CLOCK BUF 310907 OUT 2 POASDADIMATO O 25 3129 A 100R lt e SPI CLOCK BUF 007 zd 1 775 3124 1 1AA 8 1008 SPI DATA RETURN 2 lt 4 F133 SPI CLOCK BUF POSIMOSIDIGAPO 2 _24 31242 2 7 100R i SPI DATA IN 3111 B10 E F135 SPI DATA OUT PO TISSELOMAT2 0 28 31243 8 6 1008 SPI LATCH 3112 09 F136 SPI DATA RETURN iQ 29 31251 1 8 1008 1125 SPI LATCH 2 3113 D8 3 S RTCK POBITXDIMAT2 1 22 US on 4 F139 e SPI LATCH PO SIRXDTIMAT2 2 gt 31253 1008 3114 1 5 F137 e 4 PWM CLOCK BUF gt 1 1 00 3 55 3125 4 4 V V V 5 100R lt 5 4 3 3115 ef e aM P0 1 1ICTS1ICAP1 11AD0 4 2 1262 2 E EEPROM CS 3116 7 F138 e BLANK BUF PO ZIDSRTIMATI OIADO S 7 S264 4 51008 6 22 TETTE DBGSEL PO ISIDTRIIMATI 1 41 5 PROG Sis ES 9 B PO 14IDCD1ISCKTIEINTI 10 2 3918 m F104 2 912811 s 126 y CONTROL 2 F 3119 F4 n a I RST PO T6IEINTOIMATO 2 77 31274 1 8 3120 5 5 12 h PO 17ICAP1 2ISCL1 4 0802 PO TBICAP1 3ISDA1 48 z a 3 374 An 51008 gt SDA Eos ru 88 14 sis 225 aco PO 19IMAT1 2IMISO1 8 EE J 51
36. 1D33 GND AUDIO 2002 70102 RIGHT SPEAKER _ gt TPA3120D2PWP 100K 10u L 26 VIA a GND AUDIO VIA 35 LEFT SPEAKER 4 E GND AUDIO VIA E 3D03 emm ac 5 EP AP 5 3 100R 2801 1038 6 3006 3 4 GND AUDIO V NOM 1D50 gt LEFT SPEAKER 10n GND AUDIO 1 RIGHT SPEAKER 1 GND A 1 eles GND AUDIO 1735446 3 220R GND AUDIO H GND AUDIO E e GND AUDIO amp s 1 5 3 N gt N 10 1051 gt 1735446 4 4 V NOM gl 2 9 gt 1053 gt gt V NOM V NOM lt 1054 2 NOM gt 1D52 CHN SETNAME i CLASS NO 2008 11 21 CLASS D TV543 R2 LDIPNX 8204 000 8931 2008 10 10 NAME Randal De Keyzer SUPERS 1 CHECK DATE 2007 10 12 ROYAL PHILIPS ELECTRONICS N V 2007 1 2 3 4 5 6 7 8 9 10 11 12 13 18310 548 090303 eps 090303 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA GIJ SSB SRP List Explanation Example Personal Notes Introduction Net Name Diagram 12 15 12 15 1245V SRP Service Reference Protocol is a software tool
37. CONVERSION Bota 1 Y 12VD 12VD Bis 1V2 PNX5100 7HPO lc BOs EN WADO 7 1 VDISP 4 d lI VDISP VDDA DAC VDDA DAC VDISP1 7CG2 4 gt z co i CEE tenen m L i BO9b TV FRONT END um m S eee PNX8543 AUDIO 5 RES Bola 3V3A Bota pee agvo Boit AUDIO POWER AUDIO POWER B051 5100 DEBUG AUDIO VDD ADIO VDD 5711 45V TUN PIN H 33VTUN 33VTUN 1 L gt 3110 2 as PNX8543 VIDEO STREAMS TIT FPGA BACKLIGHT LVDS amp I2C MUX ar 12 4VTUN 1M59 ANTENNA SUPPLY ANTENNA SUPPLY 8V3 PER 8V3 PER Sros Bo4p iis We 3V3 3V3 Bota 43V3 43V3 al Bota gt 43V3M 207 DEMODULATOR Tu 7 8543 DIGITAL VIDEO OUT LVDS 7 06 1 1V2 PNX85XX 1V2 PNX85XX VDDA LVDS VDDA LVDS 9T64 BO4p 9T62 i rns 1V2A RE E 1V2 PNX85XX 1 PNX8543 POWER Bota pal 14245 809 gt 1V2 PNX85XX 1V2 PNX85XX 45V 3 gt gt RES gt BUE 1V2 STANDBY 1V2 STANDBY gt gt 5 54 gt 1V8 PNX85XX 1V8 PNX85XX 5153 3V3D WANE 8074 a 43V3 STANDBY 3V3 STANDBY 21722 U WAND 5752
38. VA7R 3 SP83 3 CA MOSTRT 47R RESERVED 5 AAA 3P84 4 CA MDO3 YARBA A 478 CA MDO5 8 3 84 1 4787 3 84 2 CA MDO6 3P88 V V 478 CA MDO7 ART 85 2 CA MDO1 6 3 85 3 47R CA MDO2 47R5 gt 85 4 8 3 85 1 __47 CA MOVAL 86 CA MOSTRT wow NCC NEN __ 472 87 CA MOCLK_VS2 9 10 CHN SETNAME CLASS_NO 2008 10 10 UFD2K8 DIGI i O TV543 R2 LDIPNX 8204 000 8934 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS 2007 2009 May 08 8 9 1 57 B 18310 534 090303 eps 090303 SSB Audio In All rights reserved Reproduction in whole or in parts 1 Circuit Diagrams and PWB Layouts Q549 2E LA E GEJ 2 3 4 5 6 10 11 12 13 gt PHILIPS UJ is prohibited without the written consent of the copyright 12V 9 8 78 8 NA a FP02 3P05 IP06 YKB11 3004 Vy INA uaa a 0 gt AUDIO
39. 240945 2 50 7 1 _ 1 i 1 2 51 7 E E 2 52 8 263 NES 00 9 01 4 3A02 9 3A03 D9 1 29 3A04 D9 IROB mPCI a _9 00_ IRQ PCI 4 5 127 3A05 D9 19 2 4 3 RESE A gt g 9401 IRQ PCI 3A06 E9 E IRQA mPCI 5A00 A2 23 4 1426 25 PCI CLK MINI x RESET mPCL IMRESET mPCL _9A02_ _ lt B Ja 3V3 mPCI 2 PCI REQ MINI en PCI GNT MINI 9A01 B7 31 6 3 3 02 9 02 9 33 PCI AD31 lt x PME AA 44 3V3 mPCI FA30 E1 35 gt PCEAD29 10K FA31 E2 3 51 PCLAD30 FA32 E1 E PCLAD27 44 3 3 M PCLAD25 PCLAD28 FA33 E1 PE Em PCLAD26 FA34 E6 45 PCI CBE3 PCLAD24 FA35 E6 AT PCLAD23 IDSEL FA36 E6 48 5 PCLAD 1 PCLAD22 FA37 A8 53 PCI AD19 PCI AD20 1A20 9 d PCLPAR 1210 pa PCI AD17 PCLAD48 1A22 D9 59 5 PCI CBE2 PCI AD16 1A23 D9 415 1 24 9 63 6 3 3 1430 3 01 PCI FRAME 65 PCECLKRUN NPCKCLKRUN PCI TRDY 1 25 E9 67 Zu PCI SERR 8 1426 B7 69 4 3 3 1 27 B7 7 PCI PERR PCI DEVSEL 1 28 73 PCI CBE1 1429 B2 75 5 PCI AD14 PCI AD15 dios IDSEL 30 Ci PCLAD43 340 79 5 lt PCI AD12 PCLAD41 4006 7 81 2 PCI AD10 1008 RES 8 PCLAD9 D gt 2 S PCI AD7 lt 6 3 3 PCLADG 3V3 mPCI ADG a
40. 44 VLED2 3555 3584 F 3569 3585 1 i 3570 3586 5608 1 5 3571 3587 3572 3588 Se T G 3573 3589 Se 15 3574 3590 45 3591 1K5 1 2 3 5 8 10 CHN SETNAME CLASS NO 2008 05 23 2008 05 23 1 2008 08 08 2 2008 10 31 3 2LED CONNECTOR 2 9 8204 000 8874 2008 08 08 Peter Van Hove SUPERS 1 CHECK DATE 2008 04 20 ROYAL PHILIPS ELECTRONICS 2008 2009 08 11 12 13 14 15 16 17 18 19 20 18310 653 090508 eps 090508 Q549 2E LA Circuit Diagrams and PWB Layouts Layout 8 LED Low Pow 090326 18490_550_090326 eps 31043136314 3 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA 10 10 LED Low Pow Microcontroller Block Liteon 1 2 3 4 5 6 7 8 9 10 AS 11 12 13 14 15 16 17 18 19 20
41. UR 3025 2 612 5 1 E 762 1 8 0 205 512160 25_ 2 amp s 2 o o J VDD VDD J 55 PNX5100 DDR2 ODT K9 opr PNX5100 DDR2 ODT a 3C26 1 G12 55 100 0062 lt o A2 PNXS100 DDR2 CKE lt 2 Joke 2 3 26 2 611 55 PNX5100 DDR2 WE 2 PNXS100 DDR2 WE gt 2 3 26 3 611 SDRAM 2 SDRAM PNX5100 DDR2 CS 18 les PNXSI0LDDR2CS 4 18 lcs Lu 326 4 H12 58 J PNX5100 DDR2 RAS KT 695 NC PNX5100 DDR2 RAS lt KT 3C27 1 H11 55 PNX5100 DDR2 CAS E PNX5100 DDR2CAS 5 LT 5 3 27 2 11 Be G PNXS100 DDR2 BAO 2 PNX5100 DDR2 BAO 12 3 27 3 9 22 PNX5100 DDR2 BA1 3 13 BA 88 8 a 1 3005 1 gt PNX5100 DDR2 DO N PNX5100 DDR2 BA1 lt 13 BA o 98 8 AAA 36254 PNX5100 DDR2 D16 3 27 4 18 55 K gt 30073 8 6 lt PNX5100 DDR2 D1 i 11 92 3C263 3 6 SR PNX5100 DDR2 D17 3 28 1 H12 K PNXS100 DDR2 A0 5 338 7 2 3005 2 25 PNX5100 DDR2 D2 N PNX5100 DDR2 A0 2197 7 2 30252 PNXS100 DDR2 D18 30202 Hi 2 i PNX5100 DDR2 A1 3L e 3C072 2 x SR 25 PNX5100 DDR2 D3 PNX5100 DDR2 A1 5 M3 3 30262 2 7 338 PNX5100 DDR2 D19 i PNXS100 DDR2 A2 HT 338 1 anat 36071 25 5100 00 2 04
42. 2008 10 10 3 ANA SIDE TV543 R2 LDIPNX 8204 000 8930 NAME Maelegheer Ingrid SUPERS 4 130 4 A2 CHECK DATE 2008 01 18 ROYAL PHILIPS ELECTRONICS N V 2007 T ep 2009 May 08 12 13 14 15 16 17 18 19 20 18310 545 090303 5 090303 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright PHILIPS 1 Circuit Diagrams and PWB Layouts Q549 2E LA SSB Mini PCI Connector 2 10 11 12 13 gt owner 1 2 3 4 5 6 7 8 9 1A01 A A1 1A01 B A6 2A00 A3 2A01 A3 MINI PCI CONNECTOR 2A02 A3 HR NEM 2 03 5 00 1 28 2 04 4 3V3 gt 2222 p gt 3V3 mPCI 5A01 FA37 2 05 4 30R ew V vovv e gt 5 2 06 4 si 30R 241 2 07 4 98813 STSSTERSTERSTERSTESTERTERTE gle 415415 2 08 5 z 8 ST
43. 3538 3536 3537 9 3538 7 3539 E9 3540 7 3541 GREEN 2 3541 RED 2 3536 BLUE 2 560R 1 5 390R 3540 3544 mr 50 15 390R 3543 3547 Dr 560R 1K5 390R 3546 3550 560R 1K5 390R 3549 3553 560R 3559 3556 560R 3555 3584 560R LM 3569 3585 560R 15 3570 3586 560R 1K5 3571 3587 560R 15 3572 3588 560R 3573 3589 5608 3574 3590 5668 3591 1 5 3542 9 3543 7 3544 3546 7 3547 3549 F7 3550 3552 F7 3553 F8 3555 F7 3556 F8 3569 F7 3570 F7 3571 G7 3572 G7 3573 G7 3574 G7 B 3584 F8 3585 F8 3586 F8 3587 G8 3588 G8 3589 G8 3590 G8 3591 G8 7006 2 7007 4 7008 5 7009 1X04 REF EMC HOLE pg 10 CHN SETNAME CLASS NO 2008 08 14 2 2008 10 31 3 4 LED CONNECTOR LITEON 2K9 8204 000 8897 2008 08 14 2008 10 24 2008 10 31 NAME Peter Van Hove SUPERS 1 CHECK DATE 2008 07 29 ROYAL PHILIPS ELECTRONICS N V 2008 10 2009 May 08 12 13 14 45 16 17 18 19 20 18310_633_090306 eps 090306 Circuit Diagrams and PWB Layouts Q549 2E LA LEN Layout 10 LED Low Pow 090309 18310 553 090309 3104 313 6315 2 2009 08 SSB
44. 3H83 4 IHSD 3 3H84 5 IHSE E1 3H85 B4 IHSG E1 55 5 2HUB 56 me 3H88 C5 IHSH G3 228 7 lt 3H89 C4 IHSR A12 Eno Sg zm H 3H90 C5 IHSS B12 Bos 3H91 D4 IHST B12 2Huc il 3H93 D5 IHV3 G3 L 1 3 95 4 6 G3 L 0 3H96 4 IHVE D1 3HS3 3 97 4 3H98 B4 820R 100 3H99 C4 2 8 3HRP 8 8 54 2HSS 3HRR B9 3HRS 12 820R 100n 3HRT A10 M l 1 3HRU B9 3HRV B8 3HRW C12 _ 3HRY 010 3HRZ 012 3 50 E10 3HS1 D9 CHN SETNAME CLASS NO 2008 11 21 2008 10 10 3 NAME Maelegheer Ingrid SUPERS 16 CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS N V 2005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NY 18310_512_090302 eps 090302 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA EN 98 SSB PNX8543 Audio 2 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 Specs 2 5 09 A 2HP6 D9 2HP7 D9 2HP8 D9 2 11 EITM AUDIO 2 D10 2HRO C4 2HR1 D5 2HR2 C4 B A 2HR3 C5 2HR4 D4 2HR5 D4 2HR6 D4 2HR7 D4 m 2HR8 E4 2HR9 E4 2HRA D4 2HRB D4 2HRC E4 2HRD E4 2HRE E4 B 2HRF E4 nm 2HRG E3 2HRH F4 2HRJ F3 2HRK F4 D 2HRM D6 2HRN D6 2HRP C6 VDDA AUDIO 2HRS E11 VOBA DAE 2HRT 11 2HRU C6 LD2985BM33R 2HRV C6 m 2HRW G6 E 1 2HRY G6 lt 3H62 F6 ilz 3H63 F6 ze 011 011 IP L
45. 525 a lt ay 3V3 3V3 3V3 3V3 N S 2CD1 2 3 40 1 B2 3CD1 1 C2 3CD1 2 C2 3CD1 3 C2 3CD1 4 C1 3CD2 C2 3CD3 B2 3CD7 B5 3CD8 B5 A 3CD9 B5 3CDA 85 3CDB D7 3CDC D6 3CDD D6 7C00 1 A3 9 07 0 B3 FCD1 B3 FCD2 B3 FCD3 B3 B FCD4 FCD6 D5 FCD8 B3 FCD9 D5 ICD8 B3 7CDO M24C16 WDW6 08 16 2Kx8 1 WC EEPROM PNX5100 5100 lt 43V3 EEPROM oe 6 Are 501 558 3 5 3D 91 for DEBUG V V V lt 1 1008 d FCD9 _ 1 2 3 4 5 6 7 CHN SETNAME CLASS_NO 2008 11 21 CONTROL PNX5100 J 8204 000 8928 TV543 R2 LDIPNX 2008 10 10 NAME Maelegheer Ingrid SUPERS CHECK DATE ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310_523_090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA SSB 5100 PCI All rights reserved Reproduction in whole or in parts 4 13 gt PHILIPS UJ is prohibited without the written consent of the copyright 7 00 2 PNX5100E
46. 2x CVBS OUT SC1 BO4A 2x EJTAG DETECT 2x IRQ PCI BO4F 3V3 PER BO8B 1x AUDIO OUT L BOAN 1x CA CD1 2 1x CVBS TER OUT BO6B 1 EJTAG DETECT BO1B 1x KEYBOARD BO4N 3V3 PER 804 1x AUDIO OUT R 2x CA CD1 1x CVBS TER OUT 1x EJTAG PNX5100 TCK BO4A 2x KEYBOARD 04 3V3 PER BO8B 1x AUDIO OUT R BOAN 1x CA CD2 BO8D 1 CVBS TER OUT BO5F 1 EJTAG PNX5100 TDI 09 1x KEYBOARD 05 3V3 PNX5100 CLOCK 804 1x AUDIO R 2x CA CD2 BO6E 1x DATAO BO5F 1x EJTAG PNX5100 TDO 3x LAMP ON 05 3V3 PNX5100 DDR PLLO B10 1x AUDIO R BO7A 1x CA CE1 BO6G 1x DATAO 1 EJTAG PNX5100 TMS BO1B 1x LAMP ON OUT 05 3V3 PNX5100 LVDS IN 804 7x AUDIO VDD BO7H 1x CA CE1 BO6E 1x DCLK 1 EJTAG PNX5100 TRSTn 1x LAMP ON OUT 05 3V3 PNX5100 LVDS PLL BO4M 2 AUDIO VDD 1x CA CE2 BO6G 1x DCLK BO4E 2x EJTAG TCK BOSE 1x LAMP ON OUT 01 3V3 STANDBY 1x AV1 AUDIO L BO7H 1x CA CE2 BO4H 1x DDCA SCL BO6B 1x EJTAG TCK BOSH 2 LCD PWR ON B04A 3V3 STANDBY BO8D AV1 AUDIO L 4 1x CA DATADIR BO7E 1x DDCA SCL BO4E 2x EJTAG TDI BO1B 2x LED1 4 3V3 STANDBY 1x AV1 AUDIO R BO7H 1x CA DATADIR BO4H 1x DDCA SDA 06 1 EJTAG TDI BO4A 2x LED1 B07D 5 AV1 AUDIO R BON 1x CA DATAEN BO7E 1x DDCA SDA BO4E 2x EJTAG TDO BO1B 2x L
47. 2 42 AUDIO IN5 L d 2E45 D5 B 25 C gt AUDIO IN5 R 2 54 7 2 55 7 CVBS AUDIO HDPH L AP EOS 1M36 2 56 B8 AUDIO HDPH R AP e 5a 2E80 D5 2E97 C4 TO SIDE es D BE23 FE22 3E81 EN E e e 1 0 10 3E26 4 F5 ees 11 3E74 A4 LEFT 11 u o 1ETT24 e ES m WHITE a IR 3E78 D4 3E79 F3 3E80 F4 RIGHT 3E81 C4 v3 H 91 1 N FE20 GTA NOM 1006 gt 6 41 12V RES 3E75 75R Y MDC 013V1 B BE22 1814 L 9 epsact BE21 V NOM 1005 1 58 100K 9 0 6 21 CDS4C12GTA 12V o V NOM 1004 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner 100 ala R D 5 0 8 8 5E01 D8 6E20 A3 6 21 L 6E41 B3 6E43 D3 6E44 F4 6E45 F3 9 13 8 9 14 8 9E32 2 9E34 F3 BE20 A3 21 B2 G BE22 B2 66 BE23 C3 BE24 D2 8 BE25 D2 26 1 1 26 238262 27 F4 3 T e e lt MA E67
48. 2x PNX5100 DDR2 DQS3_N 1 SCL SSB BOSE 3x TX2E BO6D 1x 1 2x NAND AD 6 BO7F 1x PCI AD28 BO4F 2x PCI STOP 2x PNX5100 DDR2 DQS3_P 1x SCL SSB BOSE 3x TX2E BO6G 1x 1 2x NAND AD 7 BO7G 1x PCI AD28 8056 1x PCI STOP PNX5100 DDR2 ODT BO7D 1x SCL SSB BOSE 3x BO6D 1x TXF1CLK 2x NAND ALE BO7H 1x PCI AD28 BO7G 1x PCI STOP PNX5100 DDR2 RAS BO8D 1x SCL SSB BOSE 3x BO6G 1x TXF1CLK 2x NAND CLE 1 28 1 PCI STOP 2x PNX5100 DDR2 VREF CTRL 3 SCL UP MIPS BOSE 3x TX3B BO6D 1x TXFICLK 2x NAND REn 1x PCI AD29 BO4F 2x PCI TRDY PNX5100 DDR2 VREF DDR 3 SCL UP MIPS BOSE 3x TX3B BO6G 1x TXFICLK 2x NAND WEn 8056 1x PCI AD29 8056 1x PCI TRDY PNX5100 DDR2 WE 2x SDA1 BOSE 3x TX83C BO6D 1x TXF1D BO6G 2x nCE BO7F 1x PCI AD29 8076 1x PCI TRDY 1x PNX5100 RST OUT 3 SDA2 BOSE 3x TX3C BO6G 1x TXF1D BO6G 2x nCONFIG BO7G 1x PCI AD29 1x PCI TRDY 805 1x PNX5100 RST OUT BOE 2x SDA3 BOSE 3x TX3CLK BO6D 1x TXF1D 1 nCSO BO7H 1x PCI AD29 BO1B 1 BOSF 1x SDA AMBI 3V3 BOSE 3x TX3CLK BO6G 1x TXF1D BO6G 1x nCSO BO9A 1
49. F9 7 3HAG 1 F10 3HP5 1 E10 5 2 E9 F 3HP5 3 F10 D 5 4 F9 13HRP lg mST Yaak RES 2488 SHAW SOR Hz AUDIO 3HPN G9 VA 140 VDDA AUDIO B gt AADC 3HRO 1 C3 33K 5 VDDA 3V3 DAC 3HRO 2 C4 3 PARES 6 2HRA zig AMB 3HRO 3 C3 33K AMS 3HR0 4 D3 Tak tuo 3HR3 1 D3 G 23HR8 2 2HR8 VRNEG 3HR3 2 D4 1 SHR8 1 Vaan RESI 33 2HR9 AADC 3HR3 3 D3 pos 3HR3 4 D3 33K 1 0 3HR8 1 8 2 l 1 E 3HR8 3 D3 3HR8 4 D3 3HRC 1 H 3HRC 2 3HRC 3 3HRC 4 E2 N 3HRJ 1 F2 3HRJ 2 E3 3HRJ 3 F3 4 F2 3HRK H6 F 3HRM G5 3HRN 65 3HT8 1 F9 _ 12_ IHSW 2 2 IHSU 8 2HR2 RES Md 140 SHRO 3 6 3 2HRO 5 ae AUDIO IN1 R Ta BRI RES 3 QURE AUDIO IN2 L gt 3HR3 4 5 Sos RES 100 5HRZ 30R 2 2 7 2HR4 VDDA AUDIO FHPE 2HRU 2HP8 100 2 7 100 2HP5 100n 2HP4 104 10n 2 SHAH 22K 7H00 7 PNX85439EH M2 24182
50. T T 9T10 B5 d 74 TUN P6 1 9T11 B7 D TUN P1 2 _9718_ ATH e D 9T12 B5 p a 2723 m284 ee i 9 13 B7 1 lt 9T14 C10 5V TUN PIN 8T28 g 2 9118 05 __ _9 20_ E 9722 _ 4 9T20 05 G TUMPS RES 9121 07 7 1714 3115 2T26 4n7 9T22 010 TUN SCL A amp 7 478 ae 21 TUN PS 9123 D7 V I 9 24 9 arte 2728 9 25 F5 TUN SDA 2 TUN P4 L 9127 G5 E SUME 478 d8p o 407 7 572967 2 3T17 RES 9T30 G5 IF AGC 5 H IF 1T11 IS USED THEN 2125 AND 9T11 ARE ALSO STUFFED gt 9731 C13 H HD1816AF BHXP acy acy 9132013 1816 ALS 2S RTA ESN BOS 9794 611 I 9740B7 REN g 5 eet 1 9 41 E7 we 9 43 10 1 5 95099956 4 3 9 44 010 lt TER 2719 9 45 G7 EN L B IF _N IF PDP 2 5 ris t AT10 B7 F TUN P11 1 11 07 2 4 gt TUN P10 gu FT17 C2 TUN P3 2 2 TUN P9 mm eit FT18 G5 eet ie aT Fret He gt 7 mis 2 TUN P6 1 2285 88 BEAGC FT23 B2 2 s PDN 1 BS 58 9129 7 TUN P8 NB IF N IF zm 4 5 PDN 1704 B5 J 3 t IUNPS y 8T27 __q ANTENNA SUPPLY i 10n 1736 ITO5 B1 ec 3
51. c 1G F1 gt 2 20 12 0 5 3ECL T z AVI G E 2 25 G2 1 D5 5 13 2E38 G2 BEB2 E5 2 AV1 R SEAS gt AV1 PR 2E60 D3 BEB3 E5 7192 2 61 D4 4 010 74HC4066 AV1 CVBS 9EA7 5 1 5 e iir t gt t 2E62 D2 5 D10 3ECN Romes FOR MHP BOLT ON 2E63 D2 BEB6 C10 C NUART SWITCHn 7 5 su M 2EA1 7 ae 2EA2 C8 BEB8 3 5 8 2 C8 9 C 2 6 D8 FE10 G2 B 1 L B 2EA9 B11 FE11 G1 dya LUN 2 11 12 1 2 9 2 11 FE14 G2 MS 2 9 FE15 G1 D 95 100 D UART SWITCHn T kal 11 ADG734BRU T 2EAD 9 2712 e 14 3V3 STANDBY 1 2EAE F9 FE28 FE47 3E08 0 MHP SWITCH 2EAF G9 FE29 12 C T PRENNE 44 2EAK FE30 G2 3V3 STANDBY gt lt BSk lt 2EAL 110 FE31 G2 USE ECR P 2 A _ 12 2 111 2 1 ili 2EAN 111 FE33 H1 BO R 2 1 4u7 IEA2 3 13 AVLY 2EAP C8 FE34 H2 cC olf D1 D3 RES 82 8 8 E C mS gins 89 me m ad ias BEBE d rk 2EAQ D8 FE35 H2 E 9E08 D ale gt e se 538 2EB6 D12 FE36 H1 5 RXD M
52. 53 58 cu25 gle 8 aye 828 22 K 5 8 8 4 war 22 GND SIG1 555 G GND SIG1 GND SIG1 GND SIG1 G as alk n 8 3 H GND SIG1 GNDSIG 5 8161 H CHN SETNAME CLASS NO 2 2008 11 21 2008 10 10 71 NAME Maelegheer Ingrid SUPERS 3 130 3 A2 DATE 2007 11 20 ROYAL PHILIPS ELECTRONICS 2008 1 2 3 T 4 5 6 H 8 9 0 L 41 12 13 14 15 16 17 18 19 20 18310_502_090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA ES GE SSB Front End 1 2 3 4 wl 5 6 7 AA E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 21 5 Tu 1125 C10 FRONT END u 2T10 1 2711 L 18 1 2T12 C2 RF IN 2T13 C12 2T14 C2 2T15 C10 B A 216613 1 2T17 C10 TUN P1 TUN P11 TUN P2 lt TUN P1O 2119 pus L TUN P3 gt
53. AMPLIFIER HW 1H48 100n2HVE 1 1 AUDIO HDPH L AP 22 3H18 2 VV 400 1H25 22K 2H25 3n3 2H26 3n3 RESET AUDIO AUDIO HDPH R AP E 11 GND GND HS IHW8 FH RESET AUDIO v 3 445 22K 3HV4 3 3H35 IHW7 AUDIO POWER 1H31 SHV4 1 1 BC847BPN COL 5 2 22 IHVA lt A PLOP J6 7HVA 1 BC847BPN COL 1 1HV9 B3 2H02 D4 2H04 A2 2H05 B2 2H25 D1 2H26 D1 2HVA A5 2HVB B5 2HVC C5 2HVD C1 2HVE C2 2HVG 2HYC B3 2HYD C3 3H18 1 B5 3H18 2 C2 3H18 3 C2 3H18 4 B5 3H35 C7 3H71 A1 3H74 B1 3H75 A3 3H76 B2 3H77 B2 3H94 C2 3HV3 D2 3HV4 1 D7 3HV4 2 C8 3HV4 3 E6 3HV4 4 E6 7H01 1 A2 7H01 2 B2 7 0 C4 1 2 D8 50 E6 4 5 24 2 25 2 27 D4 29 D8 1H31 C8 47 C1 48 C1 51 2 52 2 53 B1 54 C2 55 B2 IHV1 C5 IHVA D8 IHW7 D7 IHW8 E7 IHWE C2 IHWJ C5 IHWL C2 CHN SETNAME CLASS NO 2008 10 10 AUDIO PNX8543 TV543 R2 LDIPNX 8204 000 8927 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS 2005 2009 May 08 8 9 10 11 12 13 18310 5
54. Stand by or st by resets Initialise 1 pins of the st by uP If the protection state was left by short circuiting the Switch reset AVC LOW reset state SDM pins detection of a protection condition during Switch WP NandFlash LOW protected startup will stall the startup Protection conditions in a Switch reset system LOW reset state playing set will be ignored The protection mode will Switch reset 5100 LOW reset state not be entered Switch reset Ethernet LOW reset state Switch reset ST7100 LOW reset state keep reset NVM high Audio reset and Audio Mute Up HIGH Switch Audio Reset high start keyboard scanning RC detection Wake up reasons are Itis low in the standby mode if the standby off mode lasted longer than 10s Important remark the appearance of the 12V will start the 1V2 DCDC converter automatically gt Switch ON Platform and display supply by switching le LOW the Standby line 12V 12Vs AL and Bolt on power is switched on followed by the 1V2 DCDC converter Detect2 should b
55. v Final check of all menus in CSM Special attention for HDMI Keys Q52xE SSB Board swap v5 1 VDS JA Updated 18 03 2009 changes are indicated in red H 16771 007 eps 090318 Figure 5 14 SSB replacement flowchart 2009 May 08 EMI 549 2 Service Modes Error Codes and Fault Finding 5 9 5 9 1 5 9 2 Software Upgrading Introduction The set software and security keys are stored in a NAND Flash which is connected to the PNX8543 via the PCI bus It is possible for the user to upgrade the main software via the USB port This allows replacement of a software image in a stand alone set without the need of an E JTAG debugger A description on how to upgrade the main software can be found in the DFU Important When the NAND Flash must be replaced a new SSB must be ordered due to the presence of the security keys copy protection keys MAC address Perform the following actions after SSB replacement 1 Setthe correct option codes see sticker inside the TV 5 9 3 2 Update the TV software gt see the eUM electronic User Manual for instructions 3 Perform the alignments as described in chapter 6 section 6 5 Reset of Repaired SSB 4 Check in CSM if the HDMI key MAC address are valid For the correct order number of a new SSB always refer to the Spare Parts list Main Software Upgrade e The UpgradeAll upg file is only used in the factory The
56. 08 Block Diagrams Q549 2E LA EB LI Block Diagram 2 00 000 0 LVDS amp izc MUx 41 ANALOGUE EXTERNALS D ET B024 ER wro 7HOO 3V3 PER PNX85439EH SSB BUS pS SS SS SS __ ___ __ ___ 032 SDAS SHPJ SpA ssB 1 SDA lt SCL3 SCL SSB V 5V DDC E E 5 5 5 r 7FHO 7 01 49 50 1 04 s M25P16 25 20 11 ARX DDC SDA TUNER BUS 1 12 ARX DDC SCL CONNECTOR 3 eo 5V DDC gt TUN SDA 316 TUN P7 B EDE1116AEBG E T d lt gt ME lt gt E TUN SCL TUN P6 mca 8 1 gt AW gt FPGA wow DDR 97 BRX DDC SDA s 7FLO EDD1216AJTA BRXDDCSCL CONNECTOR 2 1 avoe 74204 5 oa 2 NP 9h RESERVED 8
57. 2 3 4 5 6 7 13 14 15 16 177 18 19 20 Ew j 3 4 j 3 uq 10 11 12 B uj 1F00 E12 2FHO BS 2FH1 BS EIJ wow POWER CONTROL 5 gt 1V2 PLL 30R 407 2 100 2 2 100n 2FH3 100 2FH4 100n 2FH5 FFHT 1V2 PNX85XX gt ge 1 2 100 RES 2FJJ 100n 8 M25P16 4u7 2FJP 10n 2FHC 10n 2FHD 10n 2FHE 10n 2FHF 10n 2FHG 10n 2FHH 10n 2FHJ 10n 2FHK 10n 2FH0 10n 2 1 447 2 100 4 RES 2 5 1 e 30R gt 3V3 FPGA 2 100 2FHP 100n 2FHV 100n 2FHR 100n 100n vv gt 2VSout FPGA 30R 447 2FJ9 100n 2FJA 100n 2FJB 100n 2FJC 100n 2V5in FPGA D ae 30R 2FJ2 407 2 1 100n 2FJO 100n 2FHZ 100n 2FHW 100n 1V8 PNXB5XX 1 8 100 2 5 i 30R ge 2V5 PLL 2FH6 100n 2FH7 100n 2FH8 100n 2FH9 100n FOR DEBUG F CON26 CON23 gt gt CON22 5 21 sS CON20 H
58. 2F25 B3 9F19 B6 amp SPARTAN 3 FPGA SN 1F20 sab 1 71 2 26 11 9 20 6 BS i i 2F27 11 9F21 A12 5F02 ari 22 2F28 E13 9F22 A12 MU REA FF09 j i 5 221 1 2 5 Y ge 1 2 8 lio toe lo 1 24 RES SDASET Ln e 3 2 29 13 9FA1 A6 E 120R e iss 83 IO LOIN IO LO1NIINIT B 26 3V3M ob ACKLIGHT CONTROL FPGACIN 1 100R 4 2 30 2 9FA2 6 c l 3 ct E LO2P GCLK4 10 LO2P DOUT BUSY 8 5 82 52 4 52 5 84 27 12 A A MOSI 1735446 4 2F31A2 00 12 ramt gt 10_LO2N GCLKS 10_LO2N MOSI CSI_B c STU TE 81 05 85 32 Gor 12518 els 2F32 A2 FF01 BLMISO 86 IO LO3P GCLKG IO LO3P D7 GCLK12 33 g x 10_LO3N GCLK7 10_LO3N D8 GCLK13 3e m 28 gt o aa 2759 us dii HN 10 LO4P D4JGCLK14 35 8 1 4 1 l1 l 41 CE 9 Jio Lospiecikto 10 LoNiD3jGCLKts 59 4 IFo9 TEMPERATURE 2 35 B3 FF04 18 lt 1 6 gt oum SENSOR 2F36 A3 FF05 18 LD1117DT12 BLHS 5 106 1O_LOBN D1 En gu CLK OUT PNX5100 3F17 2F37 A3 FF06 G4 F 2 FOE ia 9 l L07P 10 LO7PIMO 44 4 23 3 V 2F38 A3 FF07 G4 3V3 IN OUT m RE LO7N HSWAP IO LO7
59. 9 1 210 8 5 gt 8 8 81 8 8 5 B 5 3106 1 1125 11 vs d VSSA 5 5 5 e 5 3106 2 08 1126 11 13 3106 3 Mico j 14 E wc H 8 12 xo CTRL poazisctoicaro o 1 4 31244 12 y CONTROL 1 3108 C7 OUT gt 310907 1M84 99 ossia MES 1 pt 3124 1 1 8 1008 SPI DATA RETURN 311007 LO 4 F133 E SPI CLOCK BUF 9101 25 I Co 31242 2 77 7 1008 SPLDATA IN 3111 B10 2 F135 b SPI DATA OUT 2448 P0 7ISSELOIMAT2 0 28 3124 3 3 6 100R SPI LATCH 3112 09 F136 X SPHDATA RETURN 28 POSITXDIMAT2 31254 8 1008 SPI LATCH 2 I 3113 D8 3 1 9 SPI LATCH 10K RES PO SIRXD1IMAT2 2 20 i EL NES V 1008 R 3114 E8 F137 PWM CLOCK BUF 91022 pay 28 31253 2 7 1008 TEMP SENSOR TEMP SENSOR TIADO 4 i 3125 4 4 5 1008 EEPROM CS 3115 7 F138 e BLANK BUF RES 9103 PO 12IDSR4IMAT4 0IADO 5 37 i x 3126 2 2 77 1008 BLANK BUF 3116 E8 8 P e EEPROM CS DBGSEL PO I3IDTRIIMATI 1 41 i 31284 51008 PROG 3117 E7 F 9 TEMP SENSOR 43V3 PO MIDCDTISCKIIEINT 3126 1 1 CONTROL 2 F 21185 10 PO 18IRHIEINT2 4 B 3119 F4 n LL a RST PO 16IEINTOIMATO 2 2 100 12 PO 17ICAP1 21SCL1 2 3127 1 1 ALB lt SCL 12065 13 4
60. DDR2 D2 A 2HGA E7 DDR2 A4 DDR2 D6 2HGB E7 DDR2 A5 2 032 fess DDR2 D5 2HGC E7 DDR2 A6 s w33 MA K34 DDR2 D4 8 2HGD E7 DDR2 A7 5 DDR2 D7 555 fus 355 2HGE E7 STE lt waa DDR2 D8 528 ays org 2HGF E8 D lt Yat DDR2 D9 8 DDR2 A10 2 52 DDR2 D10 L pai 2HGG E8 DDR2 A11 V33 114 np 25 DDR2 D11 DDR2 VREF CTRL lt DDR2 VREF DDR lt 4 DDR2 A12 2 32 12 xc DDR2 D12 2HGJ E9 DDR2 D13 2HGK E9 DDR2 BAO Acad 2 DDR2 D14 2HGM E9 DDR2 BAT e 16 AF32 DDR2 D15 595 ase DDR2 BA 18 P34 DDR2 D16 5 8 558 2HGN E10 1724 DDR2 D17 2HGP E10 ppr2 cas W32 casB 18 R33 DDR2 D19 B 2HGR E10 DDR2 D18 2HGS E10 DDR2 CKE E AESI 20 V34 DDR2 D22 2HGT E10 24 vas DDR2 D23 DDR2 CLK N AB33 22 DDR2 D20 2HGU E12 DDR2 CLK_P i AB34 p M_CLK 23 M34 DDR2 D21 2HGV E13 24 31 DDR2 D24 2HGW E13 DDR2 CS W31 25 E mE 2HGY E13 26 gt DDR2 CLK_P N DDR2 DOMO DDR2 D25 2HGZE1S 3HJO DDR2 CLK DDR2 DOM1 AJ31 1 28 032 0082 028 2 0 E13 220R DDR2 DOM2 R34 M 2g M31 DDR2 D31 2HH1 E14 DDR2 DOM3 R31 30 R32 DDR2 D27 2HH2 E14 M82 DDR2 D29 2HH3 H13 DDR2 DQSO Acad T 0082 2050 P G34 M_paso 2HH4 C8 E Rer i 2HH5 C8 DDR2 DQS1 vat
61. SETNAME CLASS NO 2008 10 10 MINI PCI TV543 R2 LDIPNX 8204 000 8935 2008 11 21 NAME Maelegheer Ingrid SUPERS 2 CHECK DATE 2008 01 18 ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310 547 090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA GHIAJ SSB Audio AS 8 9 10 11 2 _ 348 1 2 3 4 5 6 7 8 9 1735 9 1010 C7 1038 1011 4 1050 9 1012 4 1051 F8 1016 C4 1052 9 1018 1053 5 1019 5 1054 6 1027 6 2001 2 1028 6 2002 D2 1029 2005 4 1030 5 200645 103166 2007 5 1032 6 2008 7 1033 D2 2009 C7 1036 4 2010 C7 1037 2011 8 1038 4 2012 2013 F9 2014 9 2015 2016 2017 2019 7 2020 5 2021 D8 2022 B8 2023 4 2024 4 2025 F8 2026 B8 D 2D27 D8 2030 5 203156 3003 2 3006 1 D2 3D06 2 D2 3D06 3 D2 3D06 4 D2 3D09 A3 3D10 1 D8 3010 2 08 3010 3 D7 3010 4 07 _ IN 3D11 1 F7 D 11 2 3D11 3 E8 3011 4 E7 3014 1 B8 F 3D14 2 B8 3D14 3 B8 3D14 4 B7 3D16 A4 3D17 C4 5D01 C7 5D02 C7 E 5D04 C9 5D05 C9 5D07 A6 G 5D08 A6 5D09 F8 7D03 1 A4 7D03 2 C2 7D10 1 B6 7D10 2 D3 CD10 D5 FD02 F9 H 005 E9 F 006 F9 FD07 D2 FD14 A5 1005 1006 1007 1008 C8 1009 C7 gt 7003 1 AUDIO POWER 3D09 BC847BS COL ED14 ANA
62. ST PCI AD23 76 IDSEL RXOE 1 x x 100R 2 PCI DEVSEL 2 95 IDEVSEL TXE 30 j 64 Nice 129 y 62 RST MRD 130 2NOM FNOC 131 3V3 ET ANA p gt 48 REGE m 1u0 EESEL 128 111 100 POLGBEZ 89 M gt 132 INOK PCI CBES 75 3 138 9s gt PCLADO 121 135 x PCI AD1 120 138 PCI AD2 119 EEDO 138 PCI AD3 118 146 PCI AD4 116 ii FNOA PCI ADS 115 M 3N0J PCI ADS 113 270R aren 12 LEDACT 19 600 aca POLADS 308 7 1 BAS316 198 EED 7 INOZ 6N01 3NOK FNOB PCLADI2 305 AU Mio 220R E 3 BAS316 PCLAD13 104 0 7 1 14 102 ME E Eh PCLAD15 101 RXD 3 11 PCI AD16 88 A DATA 27 4 17 87 4 PCI AD18 86 5 19 83 Y 2 82 23 PCLAD21 81 To 24 PCI AD22 79 PCI AD23 78 INOL PCI AD24 74 3V3 a we gt gt 3V3 ET DIG PCI AD25 73 s Js 220R ls s s 5 5 PCI AD26 72 41 5 5 8 8 8 5 8 8 8 8 8 PCI AD27 71 91 5 8 8 8 8 188 8 8 PCI AD28 70 50 ay rays e E Ts 29 68 oro F ER 2 67 427 8 PCI AD31 66 31 gt 5 vss 5 7
63. because the FLASH needs to initialization this is not issue in this setup the delay is automatically be in Write Protect as long as the covered by the architectural setup supplies are not available Switch HIGH the WP NandFlash to allow access to NAND Flash Release Reset PNX5100 PNX5100 will start booting Before PNX8541 boots the PNX5100 should have Wait 10ms minimum to allow the bootscript set its PCI arbiter bootscript command To allow of the PNX5100 to configure the PCI arbiter this approx 1ms is needed This 1ms is extended to 10ms to also give some relaxation to the supplies Detect EJTAG debug probe pulling pin of the probe interface to ground by inserting EJTAG probe EJTAG probe e g WindPower ICE probe be connected for Linux Kernel debugging EM purposes Ye No N Cold boot Yes Y Y Y Release AVC system reset Release AVC system reset Release AVC system reset Feed warm boot script Feed cold boot script Feed initializing boot script disable alive mechanism 4 17660 125 5 17660 125b eps To 17660 125b eps 140308 Figure 5 4 to Stand by flowchart part 1 2009 May 08 Q549 2E L Service Modes Error Codes and Fault Finding From 17660 125a eps Y From 17660 125 5
64. 1 AUDIO CL R 11 36 44 AUDIO VDD IHNB DAC 5 10K 2HMT FHM2 4 e AUDIO OUT L AUDIO VDD 7HM1 4 ADAC 6 12 LM324 44 FHM3 4 Pa 1 g3HMM 1 10K 2HMZ 33 e AUDIO OUT R 2HM3 G4 I 2HM4 G5 2HM5 H5 2 2HMG 2 10 2HMP C10 A 2HMT E10 2HMW G10 2HMY H9 2HMZ 110 2HN1 F9 3HM0 1 3HM0 2 B4 3HM0 3 C4 4 05 3HM1 D4 3HMA G6 B 3HMB H6 3HMC G5 3HMD 15 3HME 1 B10 3HME 2 B9 3HME 3 E9 L 3HME 4 E10 3HMF B3 3HML G6 3HMM 1 3HMM 2 19 3HMM 3 G9 3HMM 4 G10 3HMU H6 3HMV H5 3HMW H5 3HMY F5 3HMZ F5 I 6HMO B4 7HM1 1 B10 7HM1 2 010 7 1 3 F10 7HM1 4 H10 THM2 1 F5 D 7HM2 2 H5 7HM3 F7 7HM4 H7 5 BS 7HM6 9HMO B5 11 1 011 FHM2 F11 FHM3 H11 FHR3 A10 E 1H22 F4 1H23 H4 IHM1 F7 IHM2 C4 4 C4 L IHM5 D5 IHM6 B3 IHM7 C5 IHM8 C5 IHMG H7 IHMV B9 F IHMW B9 IHNO F5 IHN3 D9 IHN4 H5 IHN6 D10 IHN8 F6 I IHNA F10 IHNB F9 IHND H9 IHNE H10 IHNF H6 IHNG F6 G IHNH H6 IHNJ G5 IHNK 15 11 12 13 SETNAME CLASS NO 2008 10 10 3 AUDIO PNX8543 TV543 R2 LDIPNX 8204 000 8927 2 2008 11 21 NAME Maelegheer Ingrid SUPERS 130 9 CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS 2005 8 9 10221 71
65. 1x CA MDI3 DDR2 A6 06 2x FAN1 DRV 2x MHP SWITCH 01 12VF BO7H 5V5 TUN BO8D 2x AV1 PR BON 1x CA MDI4 DDR2 A7 06 2x FAN1 OUT 8 MHP SWITCH B01A 12 1 7 45V DDC 1x AVI R 1x CA MDI4 DDR2 A8 06 2x FAN2 DRV 5 1 12VF2 B07D 5V EDID BO8D 1 4 1x CA MDI5 DDR2 A9 BOSH 1 FAN CTRL 1 BO6F 1 1 1V2 BO7E 5V EDID BO4A 1x AV1 STATUS 1x CA MDI5 DDR2 BAO 06 1x FAN CTRL 1 BO6G 1x 1 1V2A B09A 45V mPCI 1x AV1 STATUS BON 1x CA MDI6 DDR2 BA1 BOSH 1x FAN CTRL 2 BO6F 1 1 1 1V2 FPGA 2 5V TUN BO4K 1x AVI Y 1x CA MDI6 2x DDR2 BA2 FE CLK BO6G 1 1 1 1V2 FPGA 5V TUN BO8D 2x AVI Y BOAN 1x CA MDI7 DDR2 CAS 04 FE CLK BO6F 1 MM1 A10 BO6A 1V2M B07H 5V TUN BO4K 1x AV1 Y CVBS 1x CA MDI7 DDR2 CKE FE DATAO BO6G 1x 1 10 1V2 PLL 5V TUN CVBS 1x AV1 Y CVBS BON 1x CA MDOO 4x DDR2 CLK N BOAN FE DATAO BO6F 1 1 11 1V2 PLL 2 5V TUN PIN BO8D 2x AV1 Y CVBS 2x CA MDOO 4x DDR2 CLK P FE DATA1 BO6G 1x 1 1
66. 3 4 2 13 14 15 16 17 18 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 d L 1F05 H1 6F82 EG 1F29 16 6 83 E6 I 1F50 B14 6F84 E6 RESERVED LL e RES 3636 SCLDISP 6 85 6 FPGA Backlight LVDS amp 2
67. DSP Physical Layer NC 144 MA2 LED100N vss 143 MATILED10N IAUXVDD 39 142 VREF 40 141 RESERVED 41 Pint 4 140 42 Identification 139 S NC 43 138 5 44 25 MHz Clk 5 Am 45 136 TPRDP 46 135 IAUXVDD 47 134 REGEN 48 133 vss 49 132 MII RX RESERVED 50 mE VSS 51 RXFilter Interface MII Mgt 53 128 5 KB Logic L 1 TPTDP 54 Oogic vss 55 126 9 9 BIOS aces a 125 BIOS ROM Data vss 57 T EEPROM LEDs AUXVDD 58 123 PWRGOOD PMEN CLKRUNN 59 422 3VAUX PCICLK 60 121 ADO 61 120 01 5 3 5 2121 RSTN 62 Abe 5 2 Stel sspe E SER x i 2 lt 1245 2 5 vss 65 116 5 8 zi AD31 66 115 05 AD30 67 114 VSS AD20 68 PCI CLK L ichs 111 AD27 71 110 208 026 l 109 ui MAC BIU 72 PCIAD P 8558858 25550 0 5505 055955555 lt lt 087 lt lt 2 lt lt lt lt 4 lt lt 7299200005 4 lt lt 7 lt lt lt 5
68. INPUT BUFFER 2201 3219 2202 7201 4 T4HCT125PW y 12 gt 11 100R 3220 2 100p T _ 9212 RES 33 L5 27R 3223 2218 100p 9214 RES 100R 2219 m 100p 7201 3 yavs 74HCT125PW K 9 3121 8 2220 RES 100p 100R 3212 F210 itt 10 211 11 12 212 13 14 F213 15 16 17 li 18 19 20 2 100R 22 858 6216 t SML 310 3222 470R 3V3 2209 B2 2210 G6 2211 16 2214 A6 2215 7 2216 F7 2217 12 2218 C12 B 2219 D12 2220 9 3121 D9 3203 B5 3204 B7 3205 5 3207 B9 3209 9 3210 B3 C B 3211 3212 D11 3213 B3 3214 H6 3215 H6 3216 H6 3217 H6 3218 H6 D 3219 B11 3220 C11 3221 H11 3222 18 3223 11 3224 H11 621618 7201 1 10 7201 2 C10 7201 3 010 7201 4 B10 7209 B2 L 7210 C2 7212 83 D 7214 B6 7215 G7 9208 A10 F 9209 9 9210 B10 9211 9212 C10 9213 09 9214 010 F202 F203 G F204 H6 F205 B10 E F206 C10 F207 C10 F208 210 F209 H11 F210 G9 F211 G9 H F212 G9 F213 H9 F214 H9 F215 H9 11 12 13 2008 08 08 2 2008 10 27 3 DRIVER 6LED LITEON 2 9 8
69. slg z 8 LPC2103FBD48 nile 5 B 3 8 5 5 9105155 Has E11 ws VESA 5 5 3106 2 D8 1126 11 H 13 3106 3 H E 2 MICRO 2 15 Y E 3107 C7 e 12 CTRL 18 31244 4 5 1124 2 CONTROL 1 3108 C7 PO 2ISCLOICAPO 0 27 3128 2 PWM CLOCK BUE 3109 D7 OUT PO AISCKOICAPO 1 22 e Es SPLCLOCICBYF 3110 D7 L 1M84 28 31241 1 1008 7 SPH DATA RETURN US 1 F133 SPI CLOCK BUF PORMIGO 31242 2 100R SPI DATA IN 3111B10 7 2 F135 SPI DATA OUT ide PO 7ISSELOIMAT2 0 28 31243 3 1008 gt SPI LATCH 3112 09 E 3 F136 SPI DATA RETURN 26 3125 3 1 Toor Has SPI LATCH 2 I 3113 D8 1 F139 SPI LATCH 10K RES PO 9IRXD1IMAT2 2 30 SMS TOR 3114 E8 l M F137 e 7 PWM CLOCK BUF gt _9102_ POAOIRTSTICAPT DIADO 85 31252 2 7 100R ___ 3115 M eg PO TIICTSTICAPT TIADO A 22 3116 E8 7 BLANK BUF PO T2IDSRTIMATI OIADO 5 27 5 gt F134 EEPROM CS 41 31264 4 5 100 PROG 3117 E7 8 DBGSEL PO TSIDTRTIMATI 1 100 9 D TEMP SENSOR 433 PO 14IDCDIISCKIIEINTI 72 NACH 8 3118 5 10 PROG PO tSIRIIEINT2 e V CONTROL F 3119 F4 n aE 7 L RST PO 1GIEINTOIMATO 2 4 gt sera 8 3120
70. sorser 1 or oun gt Ww 5 5 o o gt 4 AW 5 g 5 9F18 9F16 3V3 PER 5 5 5 L_o o STANDBY BUS 1 2 7 6 2 1 9F17 9F14 DISPLAY BUS 25 gf on 8 2 4 5 15 SDA DISP H33 _ 5 1 5 5 5 lt gt 0 lt gt A TO 5 _ SCL SETO 9F13 SCL DISP DISPLAY ___5 1 SCL UP MIPS POWER gt 4 gt 5 SUPPLY 7 SDASETi 1 lt gt x 0271 PNX8543 STANDBY CONTROLLER SENSOR 8 SCL SET1 gt 1 1 43V3 STANDBY UPC DRE EIC ER pt e p mo RN RESERVED 3666 sDA UP MIPS 1875 i G mma 1 MC_SDA AW lt 1 ees LVDS APMPS 1 1 aa AW scLuPMPS i 48V3 PER 8 L____ RES STANDBY 5 e 1 1 9 7HC4 1 1 d 3HC2 1 AC gt gt 8 UARTSWITCH 1 1 1650 UART SWITCHn 1 1 M 1 TO 1 AMA DISPLAY 1 3ECK AW 1 1 1 1651 3V3 STANDBY i MIPS 5 me eee eel OPERUM RASEN CIR AW 1 1 1 53 eem 1 4 3V3 PER 1 E RXD MIPS 5 1 TXD MIPS t 1 1 LEV
71. 3205 c 2222 5 Ho 6100 43208 217 207 223204 sen ZOA 5 8206 H 2204 2221 5107 oy 5 5108 214 211 5 7300 I Qu 5100 a i e 5 ere Br 55 1 00 188 p 730 3317 910 SI 3319 2101 um 31 00 5100 31043136325 5 18310 550 090309 5 090309 2009 08 Personal Notes 10000_012_090121 eps 090121 Circuit Diagrams and PWB Layouts Q549 2E LA EN 71 6 LED Low Pow Microcontroller Block Liteon H 1 2 3 4 5 6 7 8 9 10 AL 11 12 13 14 15 16 17 18 19 20
72. M11 2 69 4 D2 3V3 gt et 2C70 1 D3 x M M14 2C70 2 D3 48 lagla 12151315231 zls iiet 5000 gt 2670 3 D3 _ lt 8 88 8 8 8 8 8 8 8 8 8 8 8 8 8 VDD_3V3_PER M15 1V2 PNX5100 pe c ge 1V2 PNX5100 CLOCK 2070 4 03 9 RINI RIRI SOR a 2 71 2 D 5 6 915 6 ISVS TS 5 CS TS 5 8 8 8 5 66 86 1V2 PNX5100 DLL D IN PFEEPPP PEPE EEC 2 1 NI 1V2 PNX5100 gs OO e go 2072 E2 clele 4 30R 515 16 2 73 2 N14 8 8 55 VSS 5061 leet 86 8 2 74 2 F N15 1V2 PNX5100 pe yyy PES p gt 1V2 PNX5100 TRI PLL1 3228418 s 2 75 2 F 43 30R 88 R 8 VDD 3V3 LVDSIN P12 als 2C76 E3 55545 5067 2 77 9 lt 3V3 Y 4 We 3V3 PNX5100 LVDS IN 2C78 1 B1 __ 5C62 82 1 87 2 78 2 1 VDD_3V3_LVDSOUT P23 1V2 PNX5100 pe 5 ge 1V2 PNX5100 TRI PLL2 8 5 2 78 3 T NORRIS ils IT 2 78 4 D3 es R13 oT Ic88 2C79 D6 cole R14 5 68 5 5 5 5 5 5 5 5 a 3V3 Be 4 p 3V3 PNX5100 CLOCK E 2 80 D6 G vss 5 5C63 2 81 B3 R23 1V2 PNX5100 v p gt 1V2
73. SHv2 2 vy RIS vbD 1 2 SBCORE 331 IHK3 T 2HU1 B3 IHSN D11 33 v 30R AGE utac_vsst1 AMS vovv d 2HU2 A12 IHSP A13 SOR gt gls Ace 5HY3 1V2 PNX85XX slesls 3 2HU3 C12 0 5 213 ET ADS VOD_aV3_SBPER VODA IV2 USB PLL 4 2722 8 2HU4 F9 IHY1 H3 Xs 925 ava VDDA USB 30R ay Taye 2HUG Fa sivapnxexx F 22 GNDA Usa f elt 8 2 R 3V3 VID 1 1 mm gif slr L 1 2HU7 F3 IHY3 F11 E H5 VDDA_3V3_VID_1_2 VDDA_1V2_LVDS_PLL 520 2HU9 B2 4 A12 VDDA 3V3 VID 4 nee 2HUA A2 IHY5 11 F RES SS LVDS 2HV0 IHY6 C10 le DOS svo 2HV1 C3 IHY7 4 S 8 avene o lt NE VDDA 1V2 VDDA_3V3_LVDS 4 1 2 5 ame 04 SS 5HVS mar 30R aya an 8T ay vss cL VDDA 1V2 AADC a xlesleelegls 5HY5 D 2HV4 IHYA E2 amp D16 VODA AVS AADO 78278 78278 gt 2 4 2HV5 D4 IHYC D4 5HV6 E17 YODA_1V2_HDMI_EQ VDDA 3V3 VDDA ADC p fat 30R 2HV6 D4 IHYF C3 1V2 PNX85XX vvv VDD 3V3 HDMI TERM 2 VDDA 3V3 ADAC AK12 VDDA DAC cle ele 08 5 E16 VDDA_HDMI_3V3_BIAS 8 5 B s 2 7 E2 D2 8 8 28 VDDA 3V3 HDMI
74. Switch off the dimming backlight feature set Initialize audio and video Y processing IC s and functions according needed use case the BOOST control to nominal and make sure PWM output is set to 10096 Switch LCD backlight Lamp ON output is delivered by AVC AND Wait until valid and stable audio and video corresponding to the requested the backlight PWM has been on for 1s internal inverter LPL displays OR the backlight PWM has been on for 2s external inverter LPL displays The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted Switch Audio Reset low and wait 5ms maximum 1s before or at the same time as the unblanking of the video _ handling is done e g volume change Release audio mute and wait 100ms before any other audio v and unblank the video Restore dimming backlight feature PWM and BOOST output The higher level requirement is that the ambilight functionality may not be switched on Switch on the Ambilight functionality according the last status before the backlight is turned on in case the settings Set contains a CE IPB inverter supply Active 17660 127 eps 140308 Figure 5 7 Semi Stand by to Active flowchart LCD with preheat 2009 May 08 Service M
75. TUN P9 TUN P4 4 5 TUN P8 2721 E11 TUN P5 25 5 TUN P7 2722 B7 5 TUN P6 2723 DS RESERVED 78 i 2125 B7 C me 272707 amo Tunes e era 2728 ES 100R 1104 2735 2729 E7 B FT23 2 FT22 B 273585 33vTUN AN p gt 47R d8p f 2136 B5 mos 1008 g g 100R 220n 2137 C7 el Sele 14 mO 2736 5 T ma D 27 21582165 TUN SDA 2 T13 2T39 H9 D 585 dm cb 3T10 B2 8 18 SIUN P5S 5 _9T40_ TUN P10 3T11 B2 ar22 7116 ia 3T12 B2 _ 1 c 1 4 USES 3T13 B5 2137 2113 3114 B5 TUN PG 45V TUN 3T15 E5 srt 4n7 10n 3T16 E5 E BTN TUNER eig 3117 E11 E EB 2112 1 5V TUN PIN RF IN 5 7T10 19 E11 nis ME g 8 pe d UPC3221GV E1 1 3T22 G9 E 2714 88 1T25 215 1 5 outputi 7 IF Srog EMI ks doin 2202400 T B IF _N IF dn ton gir EE 2 2n 123 724 2 3 __ oUTPUT2 6 1125 IF 5T12 F11 s 3 Jano m ib t 7 6T10 B2 TUN P2 lt lt TUN P10 Vie 6T11 B2 F IUN P3 lt 5 TUN P9 6966 4 CONTROL 2 a 2 TUN PB 36 125 5 7110 C11 STUN P5 2 20
76. 4 4 3 3 1240 A5 16 111 E 1241 A6 7 18 12 5 2 2 1242 5 9 00 G5 1226 028 155 02 7 RAL i L L 1 1246 H3 9 01 5 iets 75 8 5 1250 13 9 02 5 4 8 8 8 Bos 59 125513 9 04 F5 3 FESS is ele 59550 A 1E03 1 13 9 06 H9 H 9 4 8 8 1E03 2G3 9 07 8 2 4 9 1E03 3H3 9 11 65 5 yw SEM2EM 9E2818 VGA FTH off gece oft z 1E04 3E3 9E29C14 CONNECTOR 7 54 ale tt vue Sh gace 1 05 2 9E37 C14 5 gt 98528 1 07 14 FE13 B4 1E1013 FE16 B6 6 gt 2E05 G8 FE19 B9 2E07 G8 26 10 ally EDID NVM VGA 2E08 11 FE38 C4 8115 B 238145 FE39 C12 LT la L 1 L ds 4 8 5865 1E10 2E21 D8 FE40 E11 cr vt 2 22 612 41 614 re 1208 18 2 26 10 FE42 G3 875 M24C02 WDW6 2 27 4 FE43 I3 FEI6 505 BSS 9 2E28 F9 FE48 G4 e VV 2 PRESS 256x8 1E32 FEB2 2 34 F8 49 13 400R 2 8 5 888 2829 WRITEPROT 2E46 C5 50 13 NTS STF BY 58 EEPROM 1 L 2E49 E9 FE51 G4 0 SCL lt 2 pon p 2 52 GB 52 6 4 3 ADR 5 RES 2 64 C6 53 F10 EM 9525 S acc 825 T buat 1008 2 65 54 3 E Box Si SES 5 8 45 Sh Se gt 1 FEN 55 5 6 3 CLK SCL 3E65 2 68 G5 FE58 4 8 2
77. 5 L R 6 AUDIO OUTR m 12 ADAC 6 22 3V3 NAND ARXO A gt A PLOP eae ARXC 1E03 AUDIO IN3 L 4 AUDIO IN 8543 SDRAM LR AUDIOING R gt 1 8 1E07 7E03 DDR2 VREF CTRL DIGITAL 2 SPDIF OUT 7HGO AUDIO lt SPDIF OUT EDE1116AEBG Nemo ANALOGUE EXTERNALS gt JEN EN 2 4 AUDIO IN ae DDR2 VREF DDR Vo bn 8 AUDIO IN5 R 41V8 PNX85XX EDE1116AEBG Ss 3e 3V3 7 Y eee gt NE HDMIB AXC 1V8 PNX85XX Arae HDMIB RXC DDR2 VREF DDR Ace HOME xO B N hee 9 HOMIB AX1 HDMI_RX0_B_P gt HDMI_RX1_B_N VDDA 3V3 AADC 1 4 VDDA DAC Weer ES VDDA 3V3 ADAC VDDA ADC m HDMIB RX2 HDMI_RX2_B_N MS DE HDMIB RX2 HDMI B P 3V3 LVDS VDDA LVDS 3HKO RREF PNX85XX RREF VDDA 3V3 BIAS RREF PNX85XX 1 06 VDD_3V3_SBPER 1 3V3 STANDBY VDD_1V2_CORE 1V2 PNX85XX HDMIA RX2 HDMI_RX2_A_P VDD_1V2_SBCORE ja 1V2 STANDBY HDMIA RYE HDMI_RX1_A_N HDMIA RX1 VDD 3V3 PER 3V3 PER eme gt VDD 1V8 DDR 1V8 PMNXB5XX A P HDMIA RXC S A N HDMI 4 HDMIA RXG HDMI CONNECTOR 18310_403_090305 eps 090313 H 2009 May 08 Block Diagrams
78. AUDIO POWER p gt ART GND AUDIO GND AUDIO 2D30 4 PHILIPS 1011 GND AUDIO UJ S g 2D19 25V 220u 25V 220u 5D08 1028 1 7 220 220 2022 220 2026 15 A 3D14 4 15K VV 3D14 3 15K 3D14 2 15K 3D14 1 ID36 2D24 1019 4 los E 7010 1 47n TPA3120D2PWP AUDIO R 161032 2010 25V 220 2021 1010 5002 2012 5005 RIGHT SPEAKER 15 jer 220u 1008 AUDIOL 2023 IN AUDIO AMP R 22u 1006 25V 220 220R gt L OUT 22 47n 18 L 009 5001 2011 25004 1 GND AUDIO 1 17 9 IE D 2009 7 5057 2016 1029 220 2015 10 VCLAMP Em BYPASS 25V 220u A STBY sy 3D17 Tuo MUTE 7003 2 AUDIO MUTE LAA 2 4997 BCBA7BS COL A STBY D 1016 1018 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner FDO7 LEFT SPEAKER 30064 30062 VA 5 2 100K 7 N D 1 3006 1 8 100K F GND AUDIO 8 9 23 24 13 14 25 1 6 9 15 N V 2D21 220n 2D27 3D10 4 3010 3 15 3010 2 15 3010 1 220
79. Audio Post Processing APP block Digital Audio decoder 7 5 3 Connectivity and Compute Subsystem Refer to Figure 7 10 for the connectivity and compute subsystem 2009 May 08 Circuit Descriptions Q549 2E LA EN 49 DDR2 SDRAM PNX8543x MCU_DDR DCS NETWORK DMA BUS SYSTEM CONTROLLER JTAG_MMIO 18440_205_090226 eps 090226 Figure 7 10 PNX8543 connectivity and compute subsystem The Connectivity Subsystem consists of keys in the components unauthorised exchange of these interface components will always result defective board USB2 0 interface Three 2 wire UARTs Four Master Slave interfaces Common Interface Conditional Access Interface The Computing Subsystem consists of 32 bit MIPS RISC core Enhanced JTAG EJTAG block inside the MIPS JTAG_MMIO blocks TV controller Audio Video DSP AV DSP Memory Control Unit MCU 7 5 4 Service Notice FLASH RAM PNX8543 exchange The FLASH RAM item 7P10 and or PNX8543 item 7 00 can only be exchanged by an authorised central workshop with dedicated programming tools Due to the presence Cl 2009 May 08 Q549 2E LA Circuit Descriptions 7 6 Common Interface Cl Together with this platform an extention to the Common Interface Cl Conditional Access system is added called Cl or Common Interface Plus is a specification that extends the Commo
80. NCP303LSN30 3H78 1 E6 N 1H92 FHD1 2 gt DETECT2 MP ou e n 7 t Cnc 3H78 4 H4 43 86 4 5 3 86 3 4 23 86 2 1 19 H i ROTCHAEU 3H86 1 F4 F gt V VV t BCBA7BS COL al ale F 3H86 2 F4 10K 10K 52 4 amp 2 2 8 3H86 3 8 8 3H86 4 F2 EE ela 3 87 1 12 5 4 ais 3 87 213 518 m H 2 3H87 3 100 3H87 4 14 3H92 1 G4 1V2 PNX85XX 3H92 3 fa 3H92 2 G4 J gt 254 S 5 7H16 2 3H92 3 G3 at 5 3H92 4 H3 8 8 3V3 STANDBY 3HC2 1 H12 G 5 Y G 3HC2 2 612 3HC2 3 12 RSE 3HC2 4 H13 Rcx 52 E a ass 6HW2 F5 K S Res 7 00 6 5 M RESET NVM FHC amp 3Hc24 FH09 3 7 02 D10 1V2 PNX5100 5 3H92 4 4 i 1H26 5316 1H36 e BAKA 1 e 7H03 C13 gt ot DETECT 12v INP 10K 7H11 T COL 1 10k o 10K 6H10 1H35 OUTP 7H14 F6 2 5 5 H cu eae 0 omes EE y 7H93 1 H5 L als woe cm e a ii 7H93 2 15 Sor E 12 804 ace ocx 258 8Kx8 7 7HC4 H12 2 FHCi 7HDO E12 7H832 i soL z 9 05 D13 1 100 FHC2 BOBATBSICR 3 SDA e SDA UP MIPS HHA E EL AD 1 10K 7 9H15 F11 7 7 2
81. PNX5100 DDR2 A2 gt VVSR T 118 3C26 1 PNX5100 DDR2 D20 3C28 3 H11 PNXS100 DDR2 A3 lt N2 MJ 30061 8 1 VV PNX5100 DDR2 D5 N PNX5100 DDR2 A3 lt 5 H9 30271 8 1 BR PNXS100 DDR2 D21 p 3C28 4 H12 Pee PNX5100 DDR2 A4 5 N8 eL 1 338 4 5 3 07 4 lt PNX5100 DDR2 D6 PNX5100 DDR2 A4 N8 eft 338 4 5 3C26 4 PNX5100 DDR2 D22 3C30 1 H11 348 PNX5100 DDR2 A5 30062 7 2 lt PNX5100 DDR2 D7 JS PNX5100 DDR2 A5 N3 5 7 ES 30272 7 2 V33R PNXS100 DDR2 D23 3030 2 H11 PNX5100 DDR2 A6 6 VYVSSR 8 30083 x PNX5100 DDR2 D8 PNX5100 DDR2 AG Nr 6 D CB 3631 PNXS100 DDR2 D24 3 30 318 PNX5100 DDR2 A7 2 3 093 3 lt PNX5100 DDR2 D9 PNX5100 DDR2 A7 2 3C282 7 33R PNX5100 DDR2 D25 PNX5100 DDR2 A8 40257 338 ana 3Cf x PNX5100 DDR2 D10 PNX5100 DDR2 A8 10 27 3632 PNX5100 DDR2 D26 3 30 4 19 L PNXS100 DDR2 A9 9 36092 2 T V83R __ 5100 2 11 5100 2 9 lt 9 n 30283 8 PNX5100 DDR2 D27 3 31 H12 L H PNX5100 DDR2 A10 21 42 21 1 8 3 09 1 PNX5100 DDR2 D12 PNXS100 DDR2 A10 M2 12 L P1 5p p4 3 28 4 PNX5100 DDR2 028 H 3 32 H12 PNXS100 DDR2 A11 Lam 13 09 36081 8 1 SBR PNX5100 DDR2 D13 IN 5100 2 11 lt 1309 36301 8 38R
82. _9308_ 8 2 93092 7 9908 1 4 93094 5 1 7003 LTW E500T PH1 lo 6 93183 3 9310 1 8 1 7004 LTW E500T PH1 3 1 7005 LTW E500T PH1 2 931 8 o 8 1 52 7 4 93134 5 F341 GREEN gt RED 2 GREEN 3 4 gt 2 5 GREEN yi RED 4__ GREEN 3 5 Reo 2 gt lo 8 93181 1 GREEN 3 RED 2 54 5 F342 3338 3336 gt gt gt BLUE gt 5 93184 4 gt 2 4 931 gt m 51 8 F343 560H 3340 3908 3337 560R 3343 390R 3339 560A 3346 390R 3342 560R 3349 5604 3352 5604 3355 560R 3369 560R 3370 560R 3371 560R 3372 560R 3373 SeA 3374 3388 3389 3390 1K5 1 5 15 560R 1K5 3391 1K5 390R BLUE gt GND HS BLUE 5 1 GND_HS x PWM B1 VLED1 F x 3331 3334 3332 x 1 GND_HS T 7307 BC847BW F308 GREEN6 RED6 BLUES F307 PWM R1 VLED1 F x 3325 8 8 3328 x 7305 BC84 F303 4 F302 e PWM G1 925 Sz g lt 8 l 5 7306 BC847BW 3833 F305 pu L e 4 BLUE 1 GND_HS 5 93064
83. 1 PCMCIA DO PCMCIA D1 PCMCIA D2 WPIIOIS16 m 7 3 20 9 PCMCIA VCC VPP GND2 1 06 EMC HOLE NI IP18 10K 70 2 1X05 REF EMC HOLE K IP08 3P26 2 E6 3P27 1 E6 3P27 4 E6 3P26 3 E6 3P27 2 E6 3P80 1 B9 3P26 4 E6 3P27 3 E6 3P80 2 B9 CABLE CARD INTERFACE 3P80 3 B9 3P82 1 D9 3P82 4 D9 3P84 1 E8 3P84 4 E8 3P80 4 B9 3P82 2 D9 3P83 3 D9 3P84 2 E8 3P85 1 E8 3P81 B9 3P82 3 D9 3P83 4 D9 3P84 3 E8 3P85 2 E8 3V3 PCMCIA VCC VPP Y CA INPACK CA WAIT 3P85 3 E8 3P87 7P16 8 00 6 3P85 4 E8 3P88 E8 FP04 A2 IP01 A6 3P86 E8 7P15 A8 05 D6 IP02 A6 7P15 74LVC245A IP03 6 1 08 D2 04 6 09 C9 05 6 18 D2 CA MDO3 ATR 3 3 80 3 CA MDO4 3 80 2 V47R CA MDO6 VATR 1 3 80 1 5 x PCMCIA VCC VPP 3P81 478 CA MDO7 7 16 74LVC245A BVD2 SPKR BVD1 STSCHG 4 3 82 4 09 ATR 3 3 82 3 4 CA MOCLK VS2 CA MDOO 82 2 DOR CA MDO2 RY 1 3P82 1 CA MDO1 3P83 4 47 CA MOVAL
84. 2 In 30 UIN i 2HV8 D2 IHYM F5 3 3 5HV9 IHY8 VDD 1V2 HDMI 1 VDDA 1V2 DLL F535 2 9 2 2 Y 1V2 HDMI 2 L 5HYB IHYO gu VDDA 1V2 HDMI EQ 7 YE ES 5HV7 m z 8 f 8 T E14 VDD 3V3 TERM 1 3 3 DDRPLLO 230 TA 30R cir VDDA 3V3 HDMI PLL 1 VSSA DDRPLLO 030 1 _5HGO 2HVJ F4 sls IV2 PNXBRIOK 28 2 1 2 DDRPLLO AB30 RC 4 1V2 PNXB5XX 2HVK D10 2 5 6 L ID 8542 VSS DDRPLL 830 2HVL C12 STA STA pp ip assa of wn 2 10 512512 Kg VDDA 3V3 VIDOUT VSSA DLL 2HVN 11 H RES H05 VDDA_1V2_ADC4A AST 3V3 PER 1V8 DDR 7 2 13 RREF PNX85XX B gt 1V2 PNXB5XX Be ES anio TERT Exp ib 2HVR B10 43V3 PER We 952 2HVS B3 N IHY7 svzpnxasxx pe 9 21_ _ 2HVT B4 3v3 oR slests 5 5515515055156 158 15 2HW A10 5 IHYN al ay Tay aye 2HVW 9 gt gt Bil i 2HVY G3 E 6 1V8 PNX85XX glo els RREF PNX85XX 7 5 E 8 1 2 DOC 513 278 7 a ul F 2HY3 E3 2 4 11 2
85. 2008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310_650_090508 eps 090507 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA GIG 8 LED Low Pow Microcontroller Block Liteon 1 2 3 4 6 7 12 14 15 17 18 19 20 10 11 12 13 2 3218 7209 B PDTC144EU 5 58 7210 PDTC144EU 8 EEPROM CS LOCAL 1 3V3 10K 7212 PDTC144EU MICROCONTROLLER BLOCK LITEON 1 x 3210 3V3 2214 fi PWM CLOCK INPUT BUFFER _9208_RES yev 72011 125 2 SPLDATAIN 7 3 F202 EEPROM CS A seios fenas 5 10K 7214 8 9 64K 8 HOLD F203 3205 10 RES PWM CLOCK BUF M95010 WDW6 GND 2 SPI DATA RETURN 7 7 Ft ES T serctock vA 5 3207 F205 3219 PWM CLOCK BUF 219209 7201 4 T4HCTI25PW 3 3 _9210_RES 10K SPI CLOCK BUE 7 eranc 2 n 3 11 1008 3220 8 8 ATE SPI CLOCK BUF 7201 2 AHCT125PW 5 SPI DATA RETURN 3121 F207 3211 4 27R 2218 100p BLANK BUF 17 _9214_RES 100R SPL DATA OUT FIL 7201 3 74HCT12
86. 2009 May 08 Q549 2E LA Digital Noise Reduction noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool special remote control designed for service technicians Digital Transmission Content Protection A protocol for protecting digital audio video content that is traversing a high speed serial bus such as IEEE 1394 Digital Video Broadcast Cable Digital Video Broadcast Terrestrial Digital Versatile Disc Digital Visual Interface d digital only Enhanced Display Data Channel VESA standard for communication channel and display Using E DDC the video source can read the EDID information form the display Extended Display Identification Data VESA standard Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Erasable Programmable Logic Device Europe EXTernal source entering the set by SCART or by cinches jacks Full Dual Screen same as FDW Full Dual Window same as FDS FLASH memory Field Memory or Frequency Modulation Field Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High bandwidth Digital Content Protection A key encoded into the HDMI DVI signal that prevents video data piracy If a source is HDCP coded and connected via HDMI DVI without the proper HDCP decoding the picture is put into a snow visio
87. 264 VIDEO DECODER gt SCALER DE INTERLACE AND NOISE REDUCTION AUDIO DSP 300 MHz AV DSP DRAWING ENGINE CPU lt DMA BLOCK AUDIO DEMOD AND DECODE AUDIO IN HDMI RECEIVER SYSTEM CONTROLLER 8051 300 MHz MIPS32 4KEc ADC SPI UART x22 x10 Figure 7 7 PNX8543 functional diagram Refer to Figure 7 8 for the main video interfaces for the PNX8543 and the video signal flow between blocks and memory 2009 May 08 LVDS VIDEO ENCODER AUDIO DACS AUDIO OUT GPIO Flash USB2 0 2 2 LVDS for flat panel display single or dual channel analog CVBS analog audio 125 SPDIF 18440 202 090226 eps 090226 7 5 2 Circuit Descriptions Q549 2E LA EN 47 DDR2 SDRAM MCU DDR 2D_DE GFX1 GFX2 PIP PNX8543x e 2 lt a MBVP_ L2QTV Dual HDMI DV including MBVP_ L2VO1 LVDS BUF LVDS TX ITU 656 TS PCMCIA TSDO TSDI CMD Figure 7 8 PNX8543 video flow diagram The Video Subsystem consist of the following blocks e Analogue Front End AFE block e Video and PC Capture VPC PC pipe e HDMI Receiver interface e Memory Based Video Processor MBVP e Video Composition Pipe e Memory Based Video Processor MBVP VO 1 e Memory Based Video Processor MBVP VO 2 e Video Composition Pipe CPIPE
88. 30R 3CH2 w 6662 7CG0 SI4835DDY D res Ad 7061 12VD SI34418DV yv 3661 C2 ICHA B8 _ 2 uresrceeekr 1 3CG5 D4 ICHB B8 9 8 3CG6 5 3V3 12 3CG7 E5 LA C 15 3CG8 E5 zi 3CG9 5 1 2663 530004 3CGA V E 10 47K 7CG2 3CGG E3 BC847BW 3CGH E3 tt 3CGJ E BZX384 C5V6 3 ICG4 scc0 2 CC6 3660 3 3CGN H11 z Cpe 3300036 313 3CGP H12 47K s 2 RE 3CGR H13 3CGS G12 3CGT G11 D 3CGV G13 F 3CGZ B12 1 B12 3CH1 B12 3CH2 C4 3CH3 G11 p 3CH4 H11 3CH5 G11 3CH7 C2 G FCG 3CH8 D11 7 3CH9 D11 E 3CHA D13 3CHB D12 3CHA 2 1 1 STS gt 8s BC847BPN COL m VDISP SWITCH ca 3065 4 33 313 4 7 ICHS Icot LCD PWR ON 3CGA PHILIPS O 100R BCGO CTRL1 PNX5100 iar CTRL DISP1 47R RES E 8061 RES e e 3CG6 47R RES 3067 478 RES 3CG8 47R RES 3CG9 10K RES 470p RES CTRL2 PNX5100 CTRL DISP2 x 3CHF 15K RES 3CHG 47R RES a 3CHC D11 3CGH 4 BCG2 3CHD D11 CTRL3 PNX5100 PR A CIRL DISP3 11 RES 3CHF E12 ICGA BCG3 H CTRL4 PNX5100 yy RGO e gt CTRLDISPS 3CHG E13 H 47R RES seco 4 5CG1 4 RESERVED 5CG2 B4
89. 5 64 1V2 PNX5100 DDR PLL1 3V9 PER FPGA WOW DDR 5 65 1V2 PNX5100 LVDS PLL 5 66 1V2 PNX5100 DLL ix ES Bota tgi 1 8 5100 4 T Bole PNX8543 CONTROL 5FLO 2 5 00 1 df gh E E B08a b d Bota VREF DDR1 43V3 PER 3V3 PER 5067 3V3 PNX5100 LVDS IN VREF FPGAt 5 68 3 3 5100 1 is 5069 3V3 PNX5100 DDR PLLO 8543 SDRAM 5C70 43VS PNXS100 VDS PLL FPGA Wow 10 BANKS B02b B04a p 1V8 PNX85XX 1V8 PNX85XX L a PEN 1V2 PLL 3 DDR2 VREF CTRL 5 E PNX5100 LVDS 1V2 FPGA 41V2 FPGA DDR2 VREF DDR m 33 Bia 3509 2VSPLL VDISP2 avpisP2 2V50ut FPGA 2V50ut FPGA 1 gt 1050 Bota 42V5in FPFA 42VSin FPFA 5 gt TY TT PNX8543 DIGITAL VIDEO IN 8 1 4VDISP1 42V5 DDR1 2V5 DDR1 Bele gt 1651 RREF PNX85XX RREF PNX85XX es OA m VREF FPGA1 VREF FPGAt gt 2009 08 Ty CONNECTOR MINI CONNECTOR
90. 502382 0570 2923034 921 _9 22_ 9 CHN SETNAME CLASS_NO 2008 10 10 DIGI UFD2K8 TV 543 R2 LDIPNX 8204 000 8934 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS N V 2007 2 3 4 5 6 10000 012 090121 eps 090121 18310 536 090303 eps 090303 2009 May 08 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS Circuit Diagrams and PWB Layouts Q549 2E LA EN SSB HDMI 13 14 15 16 20 10 11 12 4 1 04 HDMI CONNECTOR 3 BP1J gt gt 1 e BP gt bd gt 1 eN bd e 15 11 12 FP15 Paar p gt 2322 be DC1ROT9WBER220 HDMI CONNECTOR 2 1 03 e ARX DDC SCL lt lt ARX DDC SDA ARX HOTPLUG BRX2 e BP5B BRX2 BPT 2 BRX1 e BPSD BRX1 5 BRXO e 5 BRXO BP5G BRXC BRXC PCEC HDMI BRX DDC SCL BRX
91. CAPACITOR OR ecco c3 6CG0 C3 1 WIRE BRIDGE RES F 6CG2 C5 EN 7 00 3 9 7 03 G4 7CG0 B2 3V3 7CG1 7CG2 C4 3V3 22x 7CG4 H12 2004 8 5 7CG5 G12 7CG6 1 G13 q 5 2 9 2065 100 2CG6 100p 2667 100p 2 100 5 470K 3642 10K 7C03 BACKLIGHT CTRL we TALVC1G1256W BRUT J 2 4 CTRL DISP4 acis 1 7 BACKLIGHT CTRL E m m ICGR RES 7CG6 1 7CG6 2 613 4 BC847BPN COL 7 8 B12 J 7CG62 7CHO 012 BC847BPN COL G 7CH1 1 013 7CH1 2 013 9CG0 B3 9CG1 B3 9064 H13 9CG7 G10 9CG8 G10 K RES 9CG9 H10 3258 8 lt 7 BCG1 E6 H BCG2 E6 BCG3 E6 5 A5 BCG6 B5 FCG0 A5 L FCG1 B5 FCG2 E6 FCG3 6 L FCG4 E6 5 E6 6 H13 BACKLIGHT OUT FCG7 E13 FCG8 B4 M 1 01 02 G3 1C03 G3 ICG1 4 ICG2 C2 470K RES CTRL4 PNX5100 A BACKLIGHT CONTROL FPGA IN lt es 2CGD 470p RES 10K 3 39 K 9cco _ 3V3 e is prohibited without the written consent of the copyright All rights reserved Reproduction in whole or in parts owner 3CGN 10K 2CGB 1u0 WN 2603 n 220 25V BACKLIGHT PWM ANA SSB _
92. M 1M99 EU S AAA KEYBOARD 10R FU1H S D FU19 L 8 8 FU14 u 4 Sg FU16 LAMP ON OUT 3 Toor 3055 8 C E E 7 FU18 e AAA 22 BACKLIGHT OUT LD3985M122 5 H 100R V3U56 TKO 9 AAA BACKLIGHT BOOST 3V3 STANDBY p gt 5 1 2 55 55 10 3064 FU15 NT BACKLIGHT PWM ANA DISP LE ab E 818 9 8 100R 73058 12 2 25 gt gt 5 1 1735446 2 878 gigs RES 91 9 2448 2 RES NJ D FU25 100R RES D 3066 7 5 AA RES F 3U67 cuni e dep s ecce Rec 1 7 6U0B FUIG zi gt 33VTUN 27 GND AUDIO s STANDBY BAS316 ox 7040 2 alcol 9526 28 Sx BC847BPN COL Sca 815559859 2032 2585 9 9 8755 S ass 25 82 BON alg 82509 1 SW je jg m 10n 1003 12VF SW sy _ G 3V3 STANDBY gt 3 cl c E 1 3 0A T 32V FU1B BCX OD 12059 ENABLE 3V3 5V 2 e Ses V 1 e IU3B 6020 ase 22K gt pov FU23 amp 9 FUIC 2 So 1038 5 e a 1001 12V 5 3 1043 Sox ser TUOP e y o E elm 512 6 a 97v 2N7002 4 4
93. Q 7 2 3V3 STANDBY ___ J SDA SSB 1V8 PNXB5XX 1V8 HDMI 100 2 42 100 2P41 100n 2P38 100n 2P39 100n 2P37 100n FP25 1 51 52 2 36 7P02 lc TDA9996 9 5 24 20 Remark for service Replacing the TDA 9996 1 02 E1 1P03 C1 1 04 1 1P05 H1 2P03 C6 2P05 C10 2P28 H13 2 32 13 2P33112 2P34 D12 2P35 D12 2P36 D10 2P37 D10 2P38 D9 2P39 D9 2P41 D9 2P42 D9 2P43 D12 2P44 C10 2P45 C11 2P46 B10 2P47 C10 of its I2C address from 0 to OxCE Requires reprogramming 3V3 2 34 100n 2P35 100n 2P50 100n 2P51 100n 2P52 100n 2 53 100 2 54 100 2 55 100 15 21 xs 9338 88 50 49 3V3 gt 21 Do D1 D2 DO D1 2 TOO 01 02 DRXC DRXO DRX1 01 02 VDDH 75 _1 8 95 3 4 VDDH 3V3 vopo_svs 4 _ 2 HDMIB RXC 3 HDMIB RXC 99 HDMIB RXO 100 96 HDMIB RX1 OUT Di 97 HDMIB RXO I HDMIB RX1 93 HDMIB RX2
94. SSB Temp protection 3 12 MIPS E EB Display PNX 5100 2 21 MIPS E EB PNX5100 SSB HDMI mux 2 23 MIPS E EB TDA9996 SSB switch 2 24 MIPS E EB PCA9540 SSB Boot NVM PNX5100 2 25 MIPS E EB STM24C08 SSB Multi Standard demodulator 2 27 MIPS E EB DRX3616K SSB Micronas IF DRX3626K ARM ambilight 8 28 MIPS E EB NXP LPC2103 AL module or DC DC FPGA Local contrast 2 29 MIPS E EB Altera SSB Tuner 2 34 MIPS E EB UV1783S HD1816 SSB Fan 12 expander 7 41 5 PCA9533 FAN module T sensor 7 42 MIPS E EB LM 75 T sensor FAN 1 7 43 MIPS E EB FAN FAN 2 7 44 MIPS E EB FAN Main NVM 2 MIPS E X STM24C128 SSB PNX doesn t boot SW cause 2 53 Stby E BL PNX8543 SSB Display only 56PFL9954H 5 64 MIPS E BL EB Altera Display Extra Info Rebooting When a TV is constantly rebooting due to internal problems most of the time no errors will be logged or blinked This rebooting can be recognized via a ComPair interface and Hyperterminal for Hyperterminal settings see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging It s shown that the loggings which are generated by the main software keep continuing In this case diagnose has to be done via ComPair Error 13 bus 3 blocked At the time of release of this manual this error was not working as expected Current situation when this error occurs the TV will constantly reboot due to the blocked bus The best way for further diagnosis here is to use ComPair Er
95. 1x TSINO DATA3 1x TX852B BO7F 2x XIO ACK 8056 1 PCI AD19 BO7G 1x PCI CBE2 PNX5100 DDR2 A7 1x RX51002A BOAN 2x TSINO DATA4 B040 1x 852 1x XIO SEL NAND BO7G 1x PCI AD19 BO7H 1x 2 PNX5100 DDR2 A8 BO6D 3x RX51002A BO7F 1x TSINO DATA4 BO6D 1x 852 BO7F 2x XIO SEL NAND BO7H 1x PCI AD19 1 PCI CBE2 PNX5100 DDR2 A9 BOSB 1x RX51002A BOAN 2x TSINO DATAS BO6G 1x 852 BO4K 1 Y_CVBS MON OUT 1x PCI AD19 1x PNX5100 DDR2 BAO BO6D 3x RX51002A BO7F 1x TSINO DATAS B040 1x TX852C BOBB 1x Y CVBS MON OUT BO4F 1x PCI AD2 8056 1x PCI CBE3 PNX5100 DDR2 BA1 1x RX51002B BOAN 2x TSINO DATAG BO6D 1x TX852C 1x Y CVBS MON OUT SC BO5G 1 PCI AD2 1x PCI CBE3 PNX5100 DDR2 CAS BO6D 3x RX51002B BO7F 1x TSINO DATAG 1x TX852C BOBB 1x CVBS MON OUT SC BO7G 1x PCI AD2 1x PNX5100 DDR2 CKE BOSB 1x RX51002B BOAN 2x TSINO DATA7 B040 1x TX852C BO7H 1x PCI AD2 2x PCI CLK ETHERNET PNX5100 DDR2 CLK_N BO6D 3x RX51002B BO7F 1x TSINO DATA7 BO6D 1x TX852C 1x PCI AD2 BO7G 1x PCI CLK ETHERNET PNX5100 DDR2 CLK_P 1x RX51002C BOAN 2x TSO BIT CLK BO6G 1x TX852C BO4F
96. 2 AD21 1908 3 ws Feo BL WS 22 le 2 toon 7 7C00 7 PNX5100E 9 10 2010 ACTO AMBI e 7 11 DE 12 SYNC_H 3041 SYNC v 2 ace AMBI VS 3C41 D4 3 95 1 5 3 95 2 5 3 95 3 4 3 95 4 4 7 00 6 B3 7 00 7 CHN SETNAME CLASS_NO 2008 10 10 3 AUDIO PNX5100 TV543 R2 LDIPNX 8204 000 8928 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE ROYAL PHILIPS ELECTRONICS 2008 2009 May 08 8 9 10 11 12 13 18310 521 090302 5 090302 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS Circuit Diagrams PWB Layouts Q549 2E LA 10 SSB 5100 LVDS 1 2 3 4 5 6 AN 16775 12 13 14 15 16 17 18 19 20
97. 2203 5 2204 2205 6 2206 1 2207 2 2208 7 2209 7 2210 B8 2211 C3 2212 C4 2213 C6 2214 C3 2215 C6 2216 C2 2217 C7 2218 D1 2219 D2 2220 D7 2221 D3 2222 05 2223 D8 2224 D8 3200 A3 3201 6 3202 B3 3203 B6 3204 B3 3205 B6 3206 D3 3207 D2 3208 D7 3209 D5 3210 D3 3211 03 3212 D6 3213 D6 5200 B2 5201 B7 6200 B2 6201 B7 7200 B4 9201 BS 9202 C4 F200 B2 F201 C7 F202 D3 F203 B5 F204 B4 F207 C4 1200 A3 1201 A6 1204 B2 1205 B6 1206 B6 1208 B3 1209 B6 1210 C6 1211 1212 C3 1213 05 1214 04 1215 03 1216 5 1217 B4 CHN SETNAME CLASS_NO DC DC INTERFACE 3104 313 6325 08 06 19 08 08 06 08 09 18 08 10 23 r 08 12 06 08 06 19 08 08 06 BI 2 9 08 10 23 NAME Peter Van Hove SUPERS CHECK DATE 08 06 09 ROYAL PHILIPS ELECTRONICS N V 2008 6 7 8 2009 08 9 10 11 12 13 18310 601 090305 5 090305 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS 2 Circuit Diagrams and PWB Layouts Q549 2E LA 10 LI Interface Ambilight Microcontrollerblock 3 4 5 9 10 2 11 12 13 14 15 16 17 18 19 20 Zl 1300 E2 1301 H5 MICROCONTROLLER
98. 5 8 PO 29ITCKICAP2 2 12 eii 4 5 15 FSi2 33054 3 6 POROITDIMATS ag 3354 F313 2 7 33053 10K P0 31ITDO e N n 3 3 gt j i 10 VDD 3V3 RaR EI 9 3335 F314 1309 4 AAO 100R o els 57895 8 gis 9307 5 4 97 PES 83 1 33 F315 41V8 x 5 EN 5 er 8 8 8 8 8 8 8 8 STPSRTBRTS 812 1302 Ca 2300 2301 Ad 2302 A5 2303 A4 2304 BB 2305 10 A 2306 9 2307 B10 2308 D4 2309 D5 2310 F6 2311 F7 2312 F7 2318 F7 2314 F7 2315 F7 2316 2318 G2 B 2319 G6 2320 H5 2321 H4 2322 H4 2323 H4 2324 H4 I 3300 2 05 3300 3 D7 3300 4 D7 3301 1 D6 3301 2 5 3301 3 E6 3301 4 D7 3302 1 D7 3302 2 D6 3302 3 E6 3302 4 D6 3303 1 E6 3303 2 D6 3303 3 E6 3304 1 D6 3304 2 D7 3304 3 D7 D 3304 4 D7 3305 1 E7 3305 2 G8 3305 3 G9 3305 4 G8 3306 1 E8 3306 2 E8 3306 3 E8 3306 4 E8 3307 1 E8 3307 2 F8 3307 4 F8 E 3308 1 F8 3308 2 F8 3308 4 F8 3309 1 F8 3309 4 F8 3310 A10 I 3311 3312 A10 3313 BB 3314 BB 3315 B10 3316 B10 F 3317 B8 3318 C10 3319 3320 C5 3321 C5 3322 DS 3323 05 3324 D7 3325 06 3326 06 3327 06 3328 E5 3329 E5 3330 E8 3331 E8 3332 E3 3333 F2 3334 G5 3335 G5 3336 G6 3337 G6 3338 E8 3339 F1 H 7300 1 B9 7300 2 A10 7301 A4 7302 E3 7303 F2 9300 E3 I 9301 F3 9302 F3 11 9303 F3 9305 G1
99. 7306 H5 7307 F4 7315 G9 7316 H10 7317 F9 9301 C1 9302 C1 9303 1 C10 9303 3 C10 9303 4 C10 9304 1 E10 9304 2 E10 9304 4 E10 9305 1 C6 9305 2 C6 9305 4 C6 9306 1 D5 9306 3 D5 9306 4 D5 9307 A6 9308 A6 9309 1 B6 9309 2 B6 9309 4 B6 9310 1 B8 9310 2 B8 9310 4 B8 9311 1 H13 9311 3 H13 9311 4 H12 9312 1 B10 9312 3 B10 9312 4 B10 9313 1 B12 9313 2 B12 9313 4 B12 9314 G5 9315 1 C12 9315 2 C12 9315 4 C12 9316 H5 9317 F5 9318 1 C8 9318 3 C8 9318 4 C8 9319 1 09 9319 3 D9 9319 4 D9 9320 1 07 9320 2 D7 9320 4 D7 9325 F10 9326 G10 9327 H10 F302 G5 F303 G4 F304 H5 F305 5 F307 F5 F308 F4 F325 F10 F326 F9 F327 G10 F328 09 F329 H10 F330 H10 F340 D1 F341 01 F342 D1 F343 D2 F344 012 F345 D12 F346 D13 F347 G12 F348 G13 F349 G13 CHN SETNAME CLASS NO 2008 08 08 2008 10 27 NAME Peter Van 2 9 DRIVER 6LED LITEON 8204 000 8857 2008 06 10 2008 08 08 2008 10 SUPERS 130 3 DATE 2008 06 02 ROYAL PHILIPS ELECTRONICS N V 2008 10 2009 May 08 12 13 14 15 1 6 17 18 19 20 18310 612 090305 5 090305 Circuit Diagrams and PWB Layouts Q549 2E LA 10 EE Layout 6 LED Low Pow
100. 9 9FGA 4 RX51001E 1 1 Se RX51001E N RX51001E E gerea 02 228 E 4 4 1 8 RX51001E 3FF7 1C5 9FGB 4 D3 i RES 3FF7 2C5 9FGC 1F2 1X8 9FGBA4 3FF9 4 2F73 4 7 3FF7 3C5 9FGC 2 52A m 9 RX51002A TXF2A 3 vg 1 gt RX51002A 8510024 3FF7 4C5 9 3 E2 lt 1808 5 9265 lt 5 RES RX51002B 8 5 5 lt 3 558 2F74 4 7 RX51002B 3FF9 1 E5 9FGD 1 F2 2 _ 3 RX51002A TXF2A AP 1 RX51002A 3 9 2 05 9FGD 2 N 3 3 6 4 RX51002C sy 9 3 05 9FGD 3 22 RES RX51002C 2 3FF9 4D5 9 4 3FF9 2 2575 4 7 3FFA 1F5 FFL2E8 F IX852B _ 9FGB 2 RX51002B TXF2B gt RX51002B N RX51002CLK 7 2 2 igor 7 1 RXB1002CLK lt 3FFA 2E5 FFL3 8 z 180R 826 ESS RES RX51002D 5 3FFA 3E5 FFL4 B8 Bee 552 2F76 4 7 RX51002D 5 3FFA 4 5 TX852B 1 9FGB 1 RX51002B 2 AA 4 RX51002B RX51002E S 3FFB B5 e 7 1 8 1 8 7 5 igor 8 RES RX51002E 5 1 5 E 4 2817 eL 1 TX852C 9 66 4 SFGC4 y RX51002C IXF2C 1 S RX51002C dde ia 4 5 4 5 E jj 5 1808 VDISP 1 558 RES d di 3FFC 4 F5 E DT 55 2578 497 E E 3FFE B5 G IX852C 9FG6 3 9FGC 3 x RX51002C TXF2C NAA RX51002C 5 5 8 3 6 3 6 7 3 9 RES 9 3FFA 2 2F79 4 7 FFL
101. Dual Flat Panel Display LVDS FPD LVDS e Digital Encoder e Digital Video VIP e graphics block Audio Subsystem Refer to Figure 7 9 for the main audio interfaces for the PNX8543 and the audio signal flow between blocks and memory LCD panel FPD LVDS1 LCD panel FPD LVDS2 monitor CVBS1 Y monitor CVBS2 C 18440 203 090226 eps 090226 2009 May 08 HI 549 2 Circuit Descriptions DDR2 SDRAM PNX8543x EN TM2270 VMSP MPEG AC 3 MP3 DECODER SPDIF IN1 SPDIF IN gt SPDIF OUT SPDIF Out SPDIF IN2 fast SPDIF 125 5 1 I2S IN SD2 I2S IN SD3 I2S IN SD4 DMA BUS I2S IN WS I2S IN SCK 125 5 SPDIF HDMI_RX I2S OUT SD1 125 001 502 I2S OUT SD3 APP AUDIO DSP 125 5 4 POST PROCESSING 12S OUT WS 125 5 125 5 Main L R HPL R SCART2L R SCART1L R 18440 204 090226 eps 090226 Figure 7 9 PNX8543 audio flow diagram The Audio Subsystem consist of the following blocks Analogue Audio Front End AAFE used to capture Baseband Audio Inputs and to sample Secondary Sound IF SSIF directly or via Low IF input HDMI Receiver interface block e SPDIF input block e Audio Input Al block e Audio Output AO block e Demodulation amp Decoding ASDEC DSP for decoding all analogue terrestrial TV sound standards
102. FI RE21S HF R1500 2P12 5 2P23 E6 2P60 B1 3P15 C5 22 5 28 5 29 6 3P30 BS 3P31 BS B 3P32 C6 3P33 C4 3P35 C3 5 06 5 6 06 06 7P07 4 7 17 5 9 19 6 9 20 6 9 29 3 D2 9P29 4 D2 9P30 1 E2 9P30 2 E2 9 30 3 2 9 30 4 2 9P31 1 2 9 31 2 2 9 31 3 2 9 31 4 2 9 32 1 D1 9 32 2 1 9 32 4 1 50 1 51 2 52 1 53 2 54 1 55 1 56 2 57 1 BP5Z B1 FP00 B1 FPOB A4 FP30 B1 FP31 B1 FP32 B1 FP33 B1 FP34 B1 FP35 B5 FP36 D1 FP37 D2 FP38 D2 IP14 A6 IP15 A6 IP16 B5 20 C4 23 C5 IP28 B4 IP68 C6 CHN SETNAME CLASS NO UFD2K8 DIGI TV543 R2 LDIPNX 2008 10 10 8204 000 8934 2008 11 21 SUPERS 8 Maelegheer Ingrid CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS 2006 2009 May 08 8 9 10 11 12 13 18310 538 090303 5 090303 Circuit Diagrams and PWB Layouts Q549 2E LA SSB PNX8543 Flash 1 2 3 4 5 6 7 8 9 10 12 13 14 1 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 c12 4 2P14
103. FlashUtils upg file is only used by service centra which are allowed to do component level repair on the SSB 5 9 4 Automatic Software Upgrade In normal conditions so when there is no major problem with the TV the main software and the default software upgrade application can be upgraded with the AUTORUN UPG FUS part of the one zip file e g 3104 337 05661 FUS _Q5492_ 1 26 15 0 commercial zip This can also be done by the consumers themselves but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu see eUM The autorun upg file must be placed in the root of the USB stick How to upgrade 1 Copy to the root of the USB stick 2 Insert USB stick in the set while the set is in ON MODE The set will restart and the upgrading will start automatically As soon as the programming is finished a message is shown to remove the USB stick and restart the set Manual Software Upgrade In case that the software upgrade application does not start automatically it can also be started manually How to start the software upgrade application manually 1 Disconnect the TV from the Mains AC Power 2 Press the OK button on a Philips TV remote control or a Philips DVD RC 6 remote control it is also possible to use a TV remote in DVD mode Keep the button pressed while reconnecting the TV to the Mains AC Pow
104. MM1 D3 05 43V3 B07D ARX DDC SDA BOSD 1x BL OSCLK 1x CON22 BO1B 1x DETECT 12V BO4H 1x HDMIB RX1 BO6G 1 MM1 D3 BOSE 43V3 BO7D 2x ARX HOTPLUG BO6A 1 BL OSCLK BO6E 1x CON23 1x DETECT 12V 070 1x HDMIB RX1 BO6F 1 MM1 D4 05 43V3 BO6E 1x ASDO 8050 BL SCK 1x CON23 DETECT2 BO4H 1x HDMIB RX2 BO6G 1x MM1 D4 B05G 43V3 BO6G 1x ASDO BO6A 1x BL SCK BO6E 1x CON26 BO7D 4x DIN 5V BO7D 1x HDMIB RX2 BO6F 1 MM1 D5 BOSH 43V3 BO4M 1x A STBY BOSD 1 BL SDO 1x CON26 2x DONE BO4H 1x HDMIB RX2 BO6G 1x MM1 D5 05 43V3 B10 2x A STBY BO6A 1x BL SDO BO6E 1x CON27 BO6F 2x DQ1 0 BO7D 1x HDMIB RX2 BO6F 1x MM1 D6 BO6A 43V3 804 1x AUDIO CL L BO6A 2x BL VS BO6G 1x CON27 BO6F 2x DQ1 1 BO4H 1x HDMIB RXC 1 MM1 D6 BO6B 43V3 1x AUDIO CL L BOSD 1x BL WS BO6E 1x CONF DONE 2x DQ1 10 BO7D 1x HDMIB RXC BO6F 1x MM1 D7 06 43V3 B04I 1x AUDIO CL R BO6A 1x BL WS 1x CONF DONE BO6F 2x DQ1 11 BO4H 1x HDMIB RXC BO6G 1x MM1 D7 43V3 1x AUDIO CL R BO8D 2x BO AUDIO L BO7D 2x BO6F 2x DQ1 12 BO7D 1x HDMIB RXC BO6F 1x MM1 D8 BO7A 43V3 BO4M 1x AUDIO HDPH L AP BO8D 2x BO AUDIO R BO7D 2x CRX0 BO6F 2x DQ1 13 BO4H 1x HOT PLUG 1x MM1 D8 07 43V3 1x AUDIO HDPH L AP BO8D 2x BO B BO7D 2x CRX1 2x
105. PCR OB 06 PID Audio OB 07 Allpicture settings at 50 brightness colour contrast All sound settings at 50 except volume at 25 5 2 2 Allservice unfriendly modes if present are disabled like Sleep timer Child parental lock Picture mute blue mute or black mute Automatic volume levelling AVL Skip blank non favourite pre sets How to Activate SDM For this chassis there are two kinds of SDM an analog SDM and a digital SDM Tuning will happen according Table 5 1 e Analog SDM use the standard RC transmitter and key in the code 062596 directly followed by the MENU or HOME button Note It is possible that together with the SDM the main menu will appear To switch it off push the MENU or HOME button again Digital SDM use the standard RC transmitter and key in the code 062593 directly followed by the MENU or HOME button Note It is possible that together with the SDM the main menu will appear To switch it off push the MENU or HOME button again e Analog SDM can also be activated by grounding for a moment the solder pad on the SSB with the indication SDM see Service mode pad 25 sPi PROGH aw 4 GND 18310 219 090318 eps 090319 Figure 5 1 Service mode pad After activating this mode SDM will appear in the upper right corner of the screen when a pi
106. SPI CLK 1x TX851C BOBD 2x UART SWITCHn BO4F 1x PCI AD13 BO7H 1x PCI AD6 1 PCMCIA D1 2 1x RF AGC 2x SPI CSB B040 1x TX851C 2x USB20 DM 8056 1 PCI AD13 BO9A 1x PCI AD6 BO7H 1x PCMCIA D1 B10 3x RIGHT SPEAKER BO4A 2x SPI PROG BO6D 1x 851 7 1 USB20 DM BO7G 1x PCI AD13 1x PCI AD7 7 1x PCMCIA D2 BO4H 1x RREF PNX85XX BO4B 1x SPI PROG BO6G 1x 851 BO4E 2x USB20 DP BO7H 1x PCI AD13 8056 1x PCI AD7 BO7H 1x PCMCIA D2 BO4P 2x RREF PNX85XX 3 SPI SDI B040 1x TX851CLK 7 1x USB20 DP 2x PCI AD13 BO7G 1x PCI AD7 1 PCMCIA D3 4 1x R VGA 2x SPI SDO BO6D 1x TX851CLK 1x USB OC BO4F 1x PCI AD14 BO7H 1x PCI AD7 BO7H 1x PCMCIA D3 8 1x R VGA 3 SPI WP BO6G 1x TX851CLK 7 1x USB OC 8056 1 PCI AD14 BO9A 1x PCI AD7 1x PCMCIA D4 1x RX51001A BO1B 1x STANDBY B040 1x TX851CLK B04P 2x VDDA ADC 7 1x PCI AD14 1x PCI AD8 BO7H 1x PCMCIA D4 BO6D 3x RX51001A 2x STANDBY BO6D 1x TX851CLK BOAL 4x VDDA AUDIO BO7H 1x PCHAD14 8056 1x PCI AD8 1 PCMCIA D5 5 1x RX51001A BOBD 1 STANDBY BO6G 1x TX851CLK BO4P 2x VDDA AUDIO 1x PCI AD14 BO7G 1x PCI AD8 BO7H 1x PCMCIA D5 BO6D 3x RX51001A BO4A 2x SUPPLY FAULT B040 1x TX851D BOAL 1x VDD
107. an SSB is received where xxx is the 3 digit display panel code see sticker on the side bottom of the cabinet 6 6 1 When a picture is available 6 6 3 Use of repaired SSBs instead of new 1 Mount the Service SSB into the TV set After start up normally the download application will appear on the Repaired SSBs on stock will obviously already contain main TV Screen software This implies that only a main software upgrade is 2 Download the latest main software FUS from the required if you use a repaired SSB for board swap instead of www p4c philips com website a new SSB 6 7 Total Overview SAM modes Table 6 4 SAM mode overview Main Menu Sub menu 1 Sub menu 2 Sub menu 3 Description Hardware Info A SW VERSION e g 05492 1 26 15 0 Display TV amp Standby SW version and CTN serial B Standby processor version e g STDBY 88 68 0 0 number C Production code e g See type plate Operation hours Displays the accumulated total of operation hours TV switched on off amp every 0 5 hours is increase one Error Displayed the most recent errors Reset error buffer Clears all content in the error buffer Alignment Tuner AGC RF AGC Take over point adjustment AGC default value is 80 Whitepoint Colour temperature Normal 3 different modes of colour temperature can be se Warm lected Cool White point red LCD White Point Alignment For values White point green see Table 6 1 White D alignment values White point blue Red black level offs
108. and Fault Finding 5 8 7 5 8 8 5 8 9 5 8 10 5 8 11 5 8 12 5 8 13 look for DisplayRawNumber in the beginning of the logging Tip when there is no picture available during rebooting you are able to check for error devices in the logging LAYER 2 error which can be very helpful to determine the failure cause of the reboot For protection state there is no logging Loudspeakers Make sure that the volume is set to minimum during disconnecting the speakers in the ON state of the TV The audio amplifier can be damaged by disconnecting the speakers during ON state of the set IPB In case of no picture when CSM test pattern from PNX5100 is activated and backlight doesn t light up it s recommended first to check the inverter on the IPB wiring LAYER 2 error 17 is displayed in SDM Tuner Attention In case the tuner is replaced always check the tuner options PCI bus The splash screen image is not distributed via the regular YUV signal path from the PNX8543 to the PNX51XX but loaded time via the PCI bus Once the splash screen image is loaded into the PNX51XX it will be continuously generated by the PNX51XX until the first incoming video disables the splash screen So when teletext and or general UI is available but no splash screen option is visible during start up check the PCI bus as possible root cause Display option code Attention In case the SSB is replac
109. gt RX51001C RES 2F80 F6 9FG6 3 E2 gt V Vg gt lt 180R RES 2F81 F6 9FG6 4 2 5 9 2F67 4p 2F82 F6 7 1 22 IX851C 4 fi 9FG92 RX51001C 1 1 gt RX51001C L 2F83 F6 9FG7 2 F2 2 N Um 2F84 F6 9FG7 3 F2 p S E 3FF6 2 gt 2285 6 9FG7 4 F2 TX851CLK 69 3_ RX51001CLK IXFiCLK AAA __ RX51001CLK 49 3 AT a 100R 2FN8F8 9FG8 1 2 25 E 5 RES Lg RES 2FN9 B8 9FG8 2 A2 co 5 lt 3FF6 1 SSe 2F69 4 7 iz 1F51 2FNA B8 9FG8 3 A3 58 TX851CLK 4 REED RX51001CLK TXF1CLK s RX51001CLK 3FE0 E5 9FG8 4 A2 2 180R RES 32 Rewa gt SFEBFS 9FG9 2 B2 23 TX851D SFGA 1 RX51001D TXF1D AA RX51001D RX51001A 8 D 1 1 4 5 1 RX51001B S 3FF4 1 5 9FG9 3 5 5 5 ESS RES RX51001B 5 3FF4 2A5 9 9 4 B2 it E 3FF7 3 T 2 71 4 7 4 3 9 1 83 TX851D _ RX51001D TXF1D 1 gt RX51001D Rx51001C 3FF4 4A5 2 C2 5 1808 RES RX51001C lt 2 2F72 gt 5 5 9FGA 3 C3 3 E 77 851 S9FGA3 RX51001E A RX51001E NRX51001CLK 3FF6 1B5 4 C2 5 T dass 3 2 7 1 6 RX51001CLK lt 3FF6 2B5 9 1 E2 23 9 5 5 oraf S RX51001D a 3FF6 3B5 9 203 25 5 29 gt 5 407 RX51001D lt 955 IX851E
110. j PWM CLOCK BUF i SPLLATCH 3 SPLDATA RETURN 2 SPLDATA QUT 1 SP CLOCK BUF al gt 2B 2 e 58 Board Level Repair Component Level Repair Only For Authorized Workshop 1M20 8P 2009 May 08 18310 401 090305 eps 090420 Block Diagrams Q549 2E LA 9 Wiring Diagram 56 Elite Core WIRING DIAGRAM 56 ere core AMBI LIGHT MOD AMBI LIGHT MOD AMBI LIGHT MOD AMBI LIGHT MOD 3 3 1080 3 3 1076 3 3 1074 L 4 4 1072 een 1M83 L1 1 SCL 1 83 AL1 1M85 L4 14 GND 13 VLED2 1 83 AL1 AMBI LIGHT MOD L 4 4 1073 GND SDA CONTROL 1 CONTROL 2 1 84 14 GND 13 VLED2 1 85 AL4 Board Level Repair 1 SPLCLOCK BUF Component Level Repair Only For Authorized Workshop LCD DISPLAY 1004 TO BACKLIGHT TO BACKLIGHT 3 2 SCL DISP 1 SDA DISP AMBI LIGHT MODULE AMBI LIGHT MODULE 4 4 1070 4 4 1075 1651 8050 50 SDA DISP CN2 1319 14 PDIM Select 38 SUGDISP 13 PWM 1 83 L1 12 u 3 VDISP1 2 4VDISP1 10 GND3 1 VDISP1 2avinv 5 CONTROL 2 4 CONTROL 3 SDA 2 GND 1 SCL TEMP SENSOR 40 PROG 1 84 1 20 8018 14 GND VLED2 12 GND 1M84 9 7 5 4 2 1 1M95 B018 11 N C
111. 1 20 BO4F 2x PCI CLK MINI PNX5100 DDR2 CS BO6D 3x RX51002C BO7F 1x TSO BIT CLK B040 1x TX852CLK 1 PCI AD20 1 PCI CLK MINI 2x PNX5100 DDR2 DO BOSB 1x RX51002C BOAN 2x TSO BIT ERR BO6D 1x TX852CLK BO7G 1x 20 1 PCI CLK OUT 2x PNX5100 DDR2 D1 BO6D 3x RX51002C BOAN 2x TSO BIT VALID BO6G 1x TX852CLK 1x 20 3x PCI CLK OUT 2x PNX5100 DDR2 D10 1x RX51002CLK BO7F 1x TSO BIT VALID B040 1x TX852CLK BO4F 1x PCI AD21 2x PCI CLK PNX5100 2x PNX5100 DDR2 D11 BO6D 3x RX51002CLK BOAN 2x TSO SYNG BO6D 1x TXB52CLK 5 1 PCI AD21 8056 1x PCI CLK PNX5100 2x PNX5100 DDR2 D12 BOSB 1x RX51002CLK BO7F 1x TSO SYNC BO6G 1x TX852CLK BO7G 1x PCI AD21 3x PCI CLK PNX8535 2x PNX5100 DDR2 D13 BO6D 3x RX51002CLK BO2A 5x TUN P1 B040 1x TX852D 1x PCI AD21 2x PCI CLKRUN 2x PNX5100 DDR2 D14 5 1x RX51002D 2 5x TUN P10 BO6D 1x TX852D BO4F 1x 22 BO4F 2x PCI DEVSEL 2x PNX5100 DDR2 D15 BO6D 3x RX51002D BO2A 4x TUN P11 1x TX852D BO5G 1 22 BOSG 1 PCI DEVSEL 2x PNX5100 DDR2 D16 1x RX51002D BO2A 5x TUN P2 B040 1x TX852D BO7G 1x 22 BO7G 1x PCI DEVSEL 2x PNX5100 DDR
112. 1 llb lt CN 5 8 Ve 09 oz Y 3 L e D 3 amp E po M 55 E E Es 2 ES n m 98072 23 E lt 3 E 0002 s sg fao d 9 ES 1 r HIRE Bee y MES ce z lt lt Ban oond lt 2 82 9 6 n uU xot DE on fona E E Ieonis aH DB c 5 090309 18310 554 0900309 e 3104 313 6343 2 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA 138 Layout Small Signal Board Bottom Side 3104 313 6343 2 16310 556 090509 eps 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA HEJ Light guide 1 7 10 11 12 13 LIGHT GUIDE RES 2002 100u 16V LTW M670 LTW M670 6004 LTW M670 LTW M670 LTW M670 LTW M670 LTW M670 LTW M670 F 4 1735446 4 3016 RES 10K I z001 JBC817 25W a 1P09 C1 2001 B4 2002 B3 3000 B4 3001 B4 3002 B4 3003 B5 3004 B5 3005 B5 3007 B6 3008 B6 3009 B6 3015 C3 3016 C3 6001 B4 6002 B4 6003 B4 6004 B5 6005 B5 6006 B5 6007 B6 6008 B6 6009 B6 7001 C4 1000 C3 1001 C4 1002 B4 1003 B4 1004 B4 1005 B5 1006 B5 1007 B5 1008 B6 1009 B6 1010 B6
113. 1 59 14 8 2 8 RES 3 37 T 1 71 14 7F01H9 e 2 00 12 7205 E2 3238 SCL BOLT ON nc aroun 5F04 FF17 dL ava A alae 2 02110 7 07 02 e 9 G M RES 2 9 8 4 A 2F03 D11 7F08 A6 5 518 e zo cm gsishinalsslsslsslsalsels VOD 30 5 1M59 ETS ee Tsk Sk Sisk sis RES SCL AMBI 3V3 4558 _9 21 _ 5 1 2206 013 E14 E SCL SET sci 8 De Cb 2F07 D13 9F03 010 soo 4 S SDA AMBLSV3 DE e 3 2F08 E13 9F04D7 Lac x Hs lize ES 220R is 2F09 C2 9 05 1 F p FF10 2 HH sor 7 N B pon ps Doea F py e pe d 58 298 8 4 i 7 I 120R x 3F39 SDA BOLT ON lias 22 aca otal 2 4 1 2 3V3 gt E 2 8 0 86 81 ER 8 5 8 R78 Res 2714 E10 8 8 2215 9 09 5 E sava P 1 uo Lo 3 AMBILIGHT 2F16 C2 9F10 A5 e 5 B 278 9F11 5 A eg ae E m uM LD3985M25 SDA SET 9 8 effi SDA DISP 5558 2222 2F20 B2 9F14 SCL SET 2 gFig RES FFi8 SCL BOLT ON 9999 ECT 4 lu ou SDA SET 9F20 RES ets SDA BOLT ON 1F20 4 2F21C3 9F15 A8 2 3 5F06 2F22 B2 9F16 BP 4 _ 7 BAM 2F23 B2 9F17 B6 2 8 con a 2 3 XC3S100E 4vaG100c_A SIR S RES 308 2F24 B2 9F18 B6 x VGGAUX
114. 10 GND 9 AUDIO POWER 12 7 42 12 1M99 1 12 GND 11 SDA SET 6 BACKLIGHT OUT 5 LAMP ON OUT 4 RIGHT SPEAKER 1735 8104 AMBI LIGHT MODULE AMBI LIGHT MODULE 1 83 14 GND 13 VLED2 12 GND 11 VLEDI 10 PROG 9 TEMP SENSOR TEMP SENSOR 10 PROG 1 VLEDI 12 GND 13 VLED2 14 GND 18310 407 090420 eps 090508 2009 May 08 VIDEO FRONT END Ea PCMCIA CONNECTOR 7 15 7 16 8543 PNx5100 vipEo IN Ir Block Diagram Video Block Diagrams 549 2 LIN 1711 HD1816AF BHXP 11 TUN P11 10 TUN P10 9T18 1 TUNP1 o a ANTENNA SUPPLY 9T23 9 3T22 48V TUN 3 TUN P3 9120 gt N IF B IF _N IF 2719 2 20 7710 UPC3221GV 5V TUN p 41125 5 4 SAW 36 125 il 2T15 2 1 00 7ALVC245APW m PCMCIA VCC VPP CONDITIONAL ACCESS DEMODULATOR x 7150 DRX3926K 3758 47 3155 48 7 00 PNX85439EH M2 9T61 CVBS4 9163 CVBS TER OUT 8 18 26 53 2 16 27 56 37 42 52 ANALOGUE EXTERNALS
115. 11 12 13 14 15 16 17 18 19 20 3104 313 6314 3 1 2 3 5 8 10 1M3A E2 1 85 D2 3536 9 3537 9 3538 7 3539 9 LED DRIVE 4 F L 4 8541E8 3542 E9 3543 E7 3544 E8 3546 E7 3547 E8 354977 3550 E8 3552 F7 3553 F8 3555 F7 7006 7007 3556 F8 LTW E500T PH1 LTW E500T PH1 MEE oq d 3570 F7 GREEN 1 4 GREEN yj 4 SET Qf RED 1 5 RED 5 RED 3572 G7 gt gt 3573 67 BLUE 1 e eue y e UE 5 3574 G7 GND_HS GND_HS sere 3585 8 3586 F8 3587 G8 3588 G8 3589 G8 3590 G8 3591 G8 7006 A5 7007 A7 1M85 LI 1 SPI DATA OUT 3 SPL DATA RETURN SPI LATCH 5 2 PWNM CLOCK BUF GREEN 2 lt RED 2 D EEPROM CS 9 TEMP SENSOR BLUE 2 10 PROG vet 12 VLED2 14 51 F 3538 3541 8590 560R DH 390R 3540 3544 9957 560 DN 390R i SPI CLOCK BUF 3543 3547 95 s gt SPI DATA OUT Wwe eh hoe SPI DATA RETURN 4 4 2 SPI LATCH 9546 3542 PWM CLOCK BUF 6 4 a 3 3 560R 1K5 390R 7 3549 3553 A EEPROM CS TEMP SENSOR Seon 10 PROG 3552 3556 4 Wwe 12 560R 1K5 13
116. 2009 08 12 13 14 15 16 17 18 19 20 18310 511 090302 5 090302 Circuit Diagrams and PWB Layouts Q549 2E LA 10 SSB PNX8543 Analogue AV 1 2 3 4 55 6 7 8 9 1045 mq 13 15 1 wv 902020000 1 2 3 4 5 6 7 8 9 10 11 12 13 2 82 5 3 54 19 3 3Ho5 2 83 5 3HS5 1 4 K 1H38 18 5H80 IH80 AV1 Y_CVBS 2H84 B6 3HS6 E1 N 3H79 8543 ANALOGUE AV AVEPR im ZR 2H85 B5 3HS7 E1 21 330 22n 2 86 03 3 8 8 L 518 548856 2 87 5 3HS9 F12 AT ayes 1 2 88 4 3HSA 69 ax IHPF SHRC ST 5 xm A 2H89 B4 3HSB G10 B 3H96 lt d
117. 2H07 RES D SDM c TSTPOINT 100p FOR DEBUG SDM CHN SETNAME CLASS NO 2008 11 21 DEBUG STBY CTRL PNX8543 TV543 R2 LDIPNX 8204 000 8927 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS N V 2005 2 3 4 5 6 10000 012 090121 090121 18310 506 090302 5 090302 2009 08 All rights reserved Reproduction in whole or in parts Circuit Diagrams and PWB Layouts Q549 2E LA 10 LIN SSB 8543 Control 13 gt PHILIPS UJ is prohibited without the written consent of the copyright owner AWN 5 CONTROL 3V3 PER 10K 3HF9 7 00 8 85439 2 24182 ABS CONTROL Pee BL_PWM SCL 1 33 gt SCL1 IHFB SDA1 lt gt SDA1 RESET SYSTEM RESET_SYS D32 A 3V3 PER SCL2 gt SCL2 10K EJTAG TCK EJTAG TCK AN4 B33 Zs SDA2 A gt SDA2 gt A lt EJTAG TDI EJTAG TDI 1 A 4 4 6 EJTAG TDO EJTAG TDO VV gt gt aV VV TDO iQ GHPA 7 EJTAG TMS N EJTAG T
118. 2H90 B5 3HSD G10 B 3301 PUERUM m ms en 2H91 C4 3HSE G11 Ravers e 8 18 gle 2H92 C5 3HSF B2 P WR S a ew 22h 5 2H93 C5 3HSH 9 NL gt Y CVBS MON OUT 8 8 8 88 5 2 94 4 3HSJ A8 J amp A TSS loc 1 L 2H95 C4 3HSK E1 18 2H96 D5 3HSM C12 28 18 55 3H97 ES 2 57 ne om 3HRU 2H97 D4 3HSN C10 1 40 188 3H83 5H82 1 2 84 22n gt T 278 2H98 D4 3HSQ No 2 8 2 8 2H99 03 3HSR G10 Re a 330 p ag Sy 22n 2 3HST F12 B 5 2 H SYNC VGA aye 48528 2 4 3HSU G8 ers V SYNC VG 2 5 5 3HSV F10 2 1 ds al IHRO 2HKL E1 3HSW E1 L A poe j lt 1 2HRZ A8 3HT3 H11 188 Heb ae a Sem 278 2 50 G4 3HT4 H11 AM TSTS 2 8 2 51 8 3HT9 E1 D n 22n 2HS2 B8 5H80 A5 D Rog B28 85 1 2HS3 9 5 81 5 ATE ayes vm d IHRC 5HRG 2HS4A10 5 82 5 BHSA 2HS7 B8 5H85 B4 3H99 330n 27R 2HS8 8 5 86 C4 2 2 186R __ _ 145 8 2HS9 B9 5H87 04 bans 5 2 aye 2HSAC10 5 Rs ag dy 2HSB 5HR2 B9 E 2 8 2 8 lt 8 i 2HSCC10 5 C11 E 2HSDD10 5HR5D9 Pee 2 2 011 5 69 G10 ge
119. 3205 C5 3207 9 3209 3210 B3 B 3211 3212 011 3213 B3 3214 H6 3215 H6 3216 H6 3217 H6 3218 H6 3219 B11 3220 C11 3221 H11 3222 18 3223 3224 H11 621618 7201 1 10 7201 2 10 7201 3 010 7201 4 10 7209 2 7210 C2 7212 B3 7214 B6 D 7215 G7 9208 A10 9209 B9 9210 10 9211 9212 C10 9213 D9 9214 010 F202 B3 F203 C5 F204 H6 F205 10 E F206 C10 F207 C10 F208 D10 F209 H11 F210 G9 F211 G9 F212 G9 F213 H9 F214 H9 F215 H9 10 11 12 13 CHN SETNAME CLASS NO 1 2008 06 10 DRIVER 6LED LITEON 2 20090908 3 m 1 9 8204 000 8857 3 NAME Peter Van Hove SUPERS 3 130 2 A2 CHECK DATE 2008 06 02 ROYAL PHILIPS ELECTRONICS 2008 9 2009 08 12 13 14 15 16 18 19 20 18310 631 090306 5 090306 rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS 2 Circuit Diagrams PWB Layouts Q549 2E LA 10 EIN 10 LED Low Pow LED Liteon 3 13 14 16 17 19 20 10 11 12 13 3301 F9 3302 F9 3303 F9 J LED LITEON VLEDi F VLED2 Y 9301 9302 _ 7000 LTW E500T PH1 7001 LTW ESOOT PH1 7002 LTW E500T PH1 VLEDi F VLED2 Y i
120. 4 93202 BLUE yj GND_HS 1 BLUE yj GND_HS F 8 1 9319 1_ 3335 3908 3345 3311 3908 3348 1 5 3312 3908 Place jumper 9314 9316 9317 if VLED 17V VLED1 F scx 8 9 x 8 7317 d BCB47BW F326 i Do 8 8 I A 7315 BC847BW S 2 F328 F329 7316 BC847BW 3308 F330 8 38 l _9327 _ Place jumper 9325 9326 9327 if VLED 17V F348 4 93114 5 931 1 981 12 13 3301 9 3302 F9 3303 F9 3304 G9 3305 G9 3306 H9 3307 H9 3308 H9 3309 I9 3310 D12 3311 D12 3312 E12 3313 E12 3314 E12 3315 E12 3316 E12 3317 F12 3318 F12 3319 F12 3320 F12 3321 G12 3322 G12 3323 G12 3325 G4 3326 H4 3327 H4 3328 G4 333014 3331 F4 3332 F4 3333 H4 3334 F4 3335 D12 3336 D2 3337 D2 3338 D1 3339 D2 3340 D1 3341 D1 3342 E2 3343 D1 3344 D1 3345 D12 3346 E1 3347 D1 3348 E12 3349 E1 3350 E1 3351 E12 3352 E1 3353 E1 3354 D13 3355 E1 3356 E1 3357 D13 3358 E13 3359 E13 3360 E13 3361 E13 3362 E13 3363 F13 3364 F13 3365 F13 3366 F13 3367 G13 3368 G13 3369 F1 3370 F1 3371 F1 3372 F1 3373 F1 3374 G1 3384 E1 3385 F1 3386 F1 3387 F1 3388 F1 3389 F1 3390 G1 3391 G1 7000 C2 7001 C3 7002 C4 7003 C6 7004 C8 7005 C11 7305 G4
121. 5 5 PCI CBEO AEA 0 PCI XIO __ PCLCBE1 1 j 5 PCI CBE2 2 AF4 PCI CBE3 PCLPAR AF2 02 PCI FRAME 5 FRAME 2 vi PCHRDY 6 IRDY 2 PCI TRDY 7 TRDY gt VA PCI STOP 8 STOP v3 PCI DEVSEL 9 DEVSEL 2 14 PCLAD25 10 IDSEL AM wi PCLPERR 11 gt D o SERR 2 PCLSERR 12 Abe RES 8 1008 2 pease ACT RES 3CFK 33 6 1008 Yi te RES 3 22 77 1546 AES _ RES 3 1 11 100R 15 ona RES 3CFL33 6 100R 7 RES 3CFL22 7 1008 T3 18 CNB 10K 19 INTA 33 2 L3 eX PCI CLK PNX5100 T2 2o CK PLL OUT H R3 R2 P4 P3 P2 1 N3 6 3 3 10K N2 3CF1 C5 3CFK 1 B5 3CFK 2 B5 3CFK 3 B5 3CFL 1 B5 3CFL 2 B5 3CFL 3 B5 3CFN B5 7 00 2 IC50 C5 51 C5 CHN SETNAME CLASS NO 2008 10 10 PCI PNX5100 TV543 R2 LDIPNX 8204 000 8928 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE ROYAL PHILIPS ELECTRONICS N V 2008 6 7 8 2009 08 9 10 11 12 13 18310 524 090302 5 090302 Circuit Diagrams and PWB Layouts Q549 2E LA SSB 5100 Display Interfacing B 1 3 4 12 13 14 15 17 18 19
122. 5 E 12 D PO 17ICAP1 2ISCL1 et 4 weve I PO I8ICAP1 3ISDA1 8 3127 4 4 5 100 SDA 3123611 8 14 gig PO 8IMATI 2IMISO 1 8 8 8 1998 2121 J 516 sepe 92 7110 4 5 PO 20IMAT1 3IMOSH P3 P 2 e x i oe J NCPSOSLSNIGT P0 21ISSEL1IMAT3 0 SP SNL Bk 848 8 8 3124 3 E11 32 2 i Po 221AD0 0 5 3124 4 E11 5 F109 3 Pozaiapo 1 39 3125 1 F11 55 GND PO 24lADO 2 E ES dE ea O 2 4 8 4 Po 251AD0 6 22 7 E 7 3126 2 Ft 5 2 NC Po 261AD0 7 22 3125 4 11 85 1 2 mds s Po 27ITRSTICAP2 0 8 4 3126 1 F11 8 1 d PO 28ITMSICAP2 1 410 3126 2 F11 2 SPIDATA OUT rig 10 31084 5 ii K G T SPLDATA RETURN 1578 pope pean MD 114 4 31033 8 3126 4 11 K E 3 SOT ef 3130 15 31032 A EC uova 3127 1 F11 3 5 lt PWM CLOCK BUF l VDD 3V3 vppa 22R 2 10K 3127 4 F11 ga 6 4 3 3 or W 3128 E11 22 BLANK BUF zs 3 3191 q 3129 11 Pee EEPROM CS L 26 9 TEMP SENSOR 100R 16 PROG 3131 G7 n av Sis 89 3132 H8 i E 3133 H8 L 13 1 3134 A13 L 516 1V8 3135 11 i 3136 12 55 ales 3137 B11 m ERTSETBR S EFS 3138 B13 3139 B12 3140 C11 3141 3142 F11 7101 7 7102 6 7
123. 5 366 1008 V SDA UP MIPS SDA UP MIPS 5 VV 3H03 RES 3His B1 10K RESET ETHERNET RESET ETHERNET AB2 LEDI RES 4 7 167 UART SWITCH UART SWITCH 3H67 100R 3H16 B2 1H35 H7 WP NANDFLASH WP NANDFLASH 5 3 68 1008 gt gt 02 EDZ 05 3H17 B1 1H36 H7 D 3 19 RESET AUDIO RESET AUDIO ADT 40K 3H19 B2 1H37 C10 gt 57 2 3H6o RES D 3H20 C1 1H91 H4 3V3 STANDBY gt ae 1 110 4 RC UP J RC UP gt e 3H54 100R T ALE bi 1H32 40K 3H07 302102 30K REGIMBEAU 5 REGIMBERU CVBS SWITCH AFI 3 lt ALE 43V3 PER 3V3 PER 3H22 C13 H12 10K 3H46 AGA 1 m i n e a 3H23 C1 2 G12 3H48 27K SUPPLY FAULT SUPPLY FAULT ea AF4 EA NEA Y 3H24 C2 0 F12 10 51 SDM 5 AG2 as 100R 3H25 C13 IHW1 B4 10k gt MHe swircH T MHP SWITCH gt y B4 lt EJTAG DETECT 4 EJTAG DETECT e WC 725 27 3V3 STANDBY 77 Tamp on 4 LAMP ON Rin 1 9V3 STANDBY 3H28 C1 IHW4 B4 10K STANDBY STANDBY ADS 81 a 02 IHW5 B5 RE
124. 5V 1x BACKLIGHT CONTROL FPGA IN 2x CA RST 2x DDR2 D8 BO4H 1x BO6G 1 1 50 2 5 1 BO4A 2x ALE BO6G 1x BACKLIGHT CONTROL FPGA IN 4 1x CA VS1 2x DDR2 D9 2x BO6F 1 MM1 DO 2V5in FPGA 8050 1 5 BOSH BACKLIGHT CTRL 2x CA VS1 2x DDR2 DQMO BO4H 1x HDMIA RX1 BO6G 1x MM1 DO 2V5in FPGA 2 2x ANTENNA CTRL BO1B 1x BACKLIGHT OUT 2x CA WAIT 2x DDR2 DQM1 2x HDMIA RX1 BO6F 1x 1 01 BO6A 2V5M 2 2x ANTENNA SUPPLY BOSE 1x BACKLIGHT OUT BO7H 1x CA WAIT 2x DDR2 DQM2 BO4H 1x HDMIA RX1 BO6G 1x 1 01 2 1x ANTENNA SUPPLY BOSH 1x BACKLIGHT OUT 1x CA WE 2x DDR2 DQM3 2x HDMIA RX1 BO6F 1x MM1 D10 2 BO4M 1x A PLOP BO6G 1x BACKLIGHT OUT BO7H 1x CA WE 2x DDR2 DQSO N BO4H 1x HDMIA RX2 BO6G 1x MM1 D10 2V5 PLL 1x A PLOP BOSH 1x BACKLIGHT OUT2 CCLK 2x DDR2 DQSO P 2x HDMIA RX2 BO6F 1x MM1 D11 2V5 PLL BO8B 2x A PLOP BO6G 1x BACKLIGHT OUT2 BO4A 2x CEC HDMI 2x DDR2 DQS1 N BO4H 1x HDMIA RX2 BO6G 1x MM1 D11 8098 2V5 REF 3x AP SCART OUT L BO1B 1x BACKLIGHT PWM ANA DISP B07D 1x CEC HDMI 2x
125. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NY 18310_518_090302 eps 090302 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA GIZ SSB 5100 Video In All rights reserved Reproduction in whole or in parts 12 13 gt PHILIPS UJ is prohibited without the written consent of the copyright 1 2 3 4 6 7 8 9 3C14 B2 3C15 B2 3C16 B2 3C17 C2 3C18 C2 EEE PNX5100 VIDEO IN 3 19 D2 3C24 D2 3C29 D2 3 33 E2 3 34 E2 3C35 E2 3C36 F2 RES 3 50 C6 rei J 3 51 C7 RX51002A a 1 7 00 5 4 toe 7 00 9 C7 5 8 54 C7 RX51002A gt 1 RX51002B 5 1 ocu 7C00 5 858 PNX5100E RX51002B RX51002CLK 17 LVDS_RX 5 8 58 RX51002CLK x 1 BN 7 00 9 RX51002C Clie 5100 CLKN 528 28 RX51002C 5450 x A E2 3 CLK RX51002D MAL 30517 DN 1 c 8 8 G2 RX51002D 1 51002 a Fa 3 ocx F2 4 529 1 2 74 l 6 RX51002E 3 1 ub ee RX51001A 5 BN 1 Et lt 9 45 5 CLKP 4 CLKN i RX51001A gt LIN2 3 RX5
126. 8 3 3 2216 2215 100n 7215 TiC5e46PWP 8 LED DRIVER PWM CONTROL 25 BLANK BUF PROG 12210 2 GSCLK BLANK 3217 6 SPI LATCH Drs 1008 3218 RES 27 me 1K2 3 MODE IREF SPI CLOCK BUF 4 XLAT SPLDATA IN 5 ISCLK SPI DATA OUT 3216 24 SIN SPEDATA OUT FIL 7 1008 3V3 26 SOUT XHALF 10K 2211 3 GND GND HS 100p 2220 RES 100R F210 EN 10 F208 3212 lt __DATA RETURN SWITCH PWM R1 10 bd F211 PWM G1 11 12 e F212 PWM B1 13 14 e F213 PWM R2 15 16 17 e F214 PWM G2 18 19 e F215 PWM B2 20 21 22 XERR VIA amp 8598 3222 4708 x EEPROM CS LOCAL DATA RETURN SWITCH IN 43V8 ip g 3224 F209 1008 43V3 9 5 3221 EEPROM CSLOCAL V e DATA RETURN SWITCH 3104 313 6314 3 10 11 12 13 2201 B8 2202 C8 2203 D8 2209 B2 2210 G6 221116 2214 6 2215 7 2216 7 2217 12 2218 12 2219 012 2220 9 312109 3203 5 3204 B7 3205 C5 3207 B9 3209 C9 3210 B3 3211 3212 D11 3213 B3 3214 H6 3215 H6 3216 H6 3217 H6 3218 H6 321
127. 9307 H4 C300 B8 F300 A5 F301 A8 F302 A10 F303 B11 F304 C4 F305 C4 F306 D4 F307 F3 F308 F3 F309 G6 F310 G6 F311 G8 F312 G8 F313 G8 F314 G5 F315 F316 C9 F317 F1 F320 E9 1300 E9 1302 F9 1303 4 1304 1305 E6 1306 E7 1307 G6 1308 G2 1309 G5 1310 05 1311 E7 1312 E7 1313 E7 1314 F7 1315 F7 1316 F8 1317 F6 1318 F7 1319 F5 1320 F8 1321 F6 1322 G5 CHN SETNAME CLASS NO 1 08 06 19 DC DC INTERFACE 2 08 06 19 1 3 08 09 18 AMBI 2 9 3104 313 6325 ws 5 Peter Van Hove SUPERS 3 130 3 A2 CHECK DATE 08 06 09 ROYAL PHILIPS ELECTRONICS 2008 9 10 rz 11 2009 May 08 12 13 14 1 45 16 17 18 19 20 18310 602 090305 eps 090410 Circuit Diagrams and PWB Layouts Q549 2E LA ES Layout DC DC Interface Ambilight
128. 9EM _ 61808 AUDIO IN1 R 3ECQ 1 1 4 G10 aye K AV1 AUDIO L _ _ 61809 AUDIO INA L m 4 K _ 3ECQ 4E9 IEC5 E9 5 5 1 G8 1 6 9 J 3ECS 2G9 G9 L 5 1208 3ECS 3F8 1 8 612 FOR MHP BOLT ON 8 1 l 3E09 400R 8 4 9 9 G12 3 e 5 TXD UP 1 155 100R BOLT ON IO H 3ED1 D12 IEDO H12 E03 3E23 E FEAS 3ECG A 100R 7 RXD UP 3ED2 C8 IED1 H11 L 4 Aerea n VN SCL BOLT ON 3 TOOR 5 TXD UP 5E03 H1 IED2 H11 L 8 3V3 STANDBY 10086 SDA BOLT ON 4 _9 30 _ EDO AV1 BLK 5EA1 B10 7 1008 100R 57 KZ lt BOLT DAO 68R d SEI 3 1008 STANDBY vs L ere 3EAY 1 BO AUDIO L 6 25 L 10 CVBS TER OUT 8 2 1 0 502 BO AUDIO R 6E27 F4 1 2L 4 I 6E50 C3 B10P PH K S sl 10 BO CVBS 17 D2 8 Ms 19 1 NIST aye NTS 12 595 19 2 4 13 c Sled zlezla 20 _ 1 280 80 94 6 4 _82 8 1 10 85 ATESTE SCL 1 e AAA SCL SSB 9 o o a E11 2 Pu ie y u 9E03 D2 Sos 2 7 SDA SSB MU EI E1 N 3 9 9E08 C3 N 9 09 4 9E30 H11 CHN SETNAME CLASS NO 2 2008 11 21
129. A2 BP1R B2 BP1S B2 BP1U E1 BP1V G1 1 11 5 2 5 2 5 2 BP5D C2 5 02 5 D2 BP5G 02 5 02 BP5J H2 BP5K H2 BP5L H2 BP5M H2 BP5N I2 BP5P I2 BP5R 12 55 2 0 14 06 1 07 1 FP08 G1 09 G1 G1 FPOC G1 FPOE D1 FPOF D1 D2 FPOH D2 FP0J E1 FPOP D1 FPOR I1 05 FPOT I2 FPOU 12 FP10 B1 FP11 B1 FP12 B1 FP13 B1 FP14 B2 FP15 B1 FP16 G1 17 20 11 21 9 22 12 23 110 FP25 D8 FP26 D12 FP39 C12 FP40 C11 FP41 C10 42 6 FP43 12 FP44 F13 10 612 11 12 17 F13 26 5 IP5U G6 5 G7 IP5Y G6 IP5Z H6 IP60 H13 8204 000 8934 2008 11 21 CHN SETNAME CLASS NO UFD2K8 DIGI IO TV543 R2 LDIPNX 2008 10 10 3 NAME Maelegheer Ingrid SUPERS 8 CHECK DATE 2007 10 18 e ROYAL PHILIPS ELECTRONICS N V 2005 0 7 2009 08 11 14 15 16 17 18 19 20 18310 537 090303 5 090303 Circuit Diagrams and PWB Layouts Q549 2E LA SSB HDMI Switch 11 12 13 gt PHILIPS UJ All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner AN 1 2 9 1 96 D1 1 06 1 2 04 5 ERAS 5
130. ACTUNPI ANTENNA SUPPLY a 52 9T23 S TUNES 45V TUN PIN 7HVO x TPA6111A2DGN 45V TUN 3 TUN P3 ore RESET AUDIO 5 1 gt gt 1 15 e 7 AUDIO HDPH L AP AUDIO IN AMI2 ADAC 3 2 1 05 AUDIO HDPH R AP 1 DRX2 Headphone gt 2 AUDIO INA L 11 ADAC 4 m 4 gt 6 8 Out 3 5mm DANI AUDIO IN gt VGA 1 DVI gt HDMI 2 AUDIO IN4 R omo gt USB CONNECTOR baxe 2 ANALOGUE EXTERNALS A PNX8543 AUDIO CONNECTOR gt 1E01 5 1 2 lt _AP SCARTOUFL lt _AUDIO CLL CRX24 2 Oo AP SCARFOUT R bie AUDIO CL R 7 5 ADAC 8 5 m T lt AL16 USB OC S 1 un USB FAULT USB 2 0 AV1 AUDIO L 4 AUDIO IN1 L 7 16 USB20 DM CONNECTOR SIDE gt gt t USB_DM SW UPLOAD eme gt use pp AP USB20 DP une AUDIO SEAS F Y AVI AUDIO R EM AUDIO INI R_ AP7 gt 17 3 37 HDMI 1 CRXC SCARTI USB_RPU lt 3V3 PER CONNECTOR gt es T 3909 AP SCARTOUTL USB VBUS 3V3 PER 1P03 BRX2 gt lt _AP SCARFOUTR inr EXT2 PNX8543 FLASH AUDIO IN2 L 1 _ S gt mou AUDIO IN2 R S 27 a BRXC SCART2 7P10 BRXC gt NAND01GW3B2BN6F ANALOGUE EXTERNALS B 1 1E04 2 2 5 Q 4 AUDIO OUTL 7 lt lt ADAC S 4 1 _ AUDIO OUT 1
131. AL2 81 84 10 LED Low Pow LED Liteon 82 84 10 LED Low Pow LED Drive Liteon AL4 83 84 SSB 01 10 85 133 137 138 SSB SRP List Explanation 134 SSB SRP List Part 1 135 Copyright 2009 Koninklijke Philips Electronics N V All rights reserved No part of this publication may be reproduced stored retrieval system or transmitted in any form or by any means electronic mechanical photocopying or otherwise without the prior permission of Philips Published by ER EL 0965 BU TV Consumer Care the Netherlands Subject to modification EN 3122 785 18311 2009 May 08 PHILIPS Revision List 1 2 1 2 2 Revision List Manual xxxx xxx xxxx 0 e First release Manual 1 All Chapters the following sets to the manual see Table 2 1 Described Model numbers e Chapter 5 paragraph 5 8 10 PCI bus added Chapter 6 paragraph 6 6 Service SSB delivered without main software loaded added Technical Specifications and Connections Index of this chapter 2 1 Technical Specifications 2 2 Directions for Use 2 3 Connections 2 4 Chassis Overview Notes figures can deviate due to the different set executions e Specifications are indicative subject to change Technical Specifications For on line product support please use the links in Table 2 1 Here is product information available as well as getting started user manuals frequently
132. All references to normal grounds Ground symbols without additional text are not listed in the reference list this to keep it concise S28229922 p9 Signals that are not used in multiple schematics but only once or several times in the same schematic are included in the SRP reference list but only with one reference Additional Tip When using the PDF service manual file you can very easily search for signal names and follow the signal over all the schematics In Adobe PDF reader Select the signal name you want to search for with the Select text tool Copy and paste the signal name in the Search PDF tool Search for all occurrences of the signal name Now you can quickly jump between the different occurrences and follow the signal over all schematics It is advised to zoom in to e g 150 to see clearly which text is selected Then you can zoom out to get an overview of the complete schematic PS It is recommended to use at least Adobe PDF reader version 6 x due to better search possibilities in this version 10000 031 090121 eps 090121 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA HA SSB SRP List Part 1 Netname Schemat BosD 3V3 STANDBY 1x 1 BO7H 1 CA DATAEN BO4H 1x DDC SCL BO6B 1 EJTAG TDO 2x LED2 9 3V3 STANDBY 8 3 1 2 BO7D 1x DDC SCL BO4E 2x EJTAG TMS B10 3x LE
133. Ambi Light architecture in this platform has been entirely renewed The characteristics are e Additional DC DC board generating 12 16 24 V optional processor on DC DC panel or AL board e Low power LEDs interface from ARM to LED drivers lC upgradeable via USB e Each AL module has a temperature sensor 2009 May 08 called Net TV is introduced A separate Wi Fi module enables wireless communication with a local network The use of the DC DC board is optional In case no DC DC board is implemented the ARM processor is located on one of the AL boards Refer to Figure 7 12 for the Ambi Light architecture Circuit Descriptions Q549 2E LA EN 51 SSB 12C ARM In case of Y cable AL board AL board d AL board AL board Interface board for DC DC amp ARM 1M85 needed in case of MP Elite 21 9 7 8 4 controller 18310 203 090317 eps 090317 Figure 7 12 Interface between Ambi Light and SSB Referto Figure 7 13 below for signal interfacing to and from the ARM controller The ARM controller is located on the DC DC board item no 7302 or AL panel item no 7102 SPICLOCK SPI LATCH SPILATCH 2 only on dc dc for aurea SPI DATA OUT PWM CLOCK SPI DATA RETURN CS EEPROM 7 8 2 18310 204 090318 eps 090318 Figure 7 13 ARM controller interface Data transfer between ARM processor and LED drivers is ex
134. B01A TPS53124PW IC 7003 Block Diagram vrecs V5OK ae 4 H TSD VSFILT 0 4 Ovo O 3 Q vesT2 7 4 Ref BGR Ref Switcher Controller Switcher Controller Fault Fault Ouz 9 4 Sdn Sdn DRV 2 N 8 Q P6ND2 EN SS Control T N Q N N s BR gt gt 30 vsriLr B 15 Ref 7 55 PWM VFBx 10 VREGS Control logic TRIPx 9 VBSTx oce gt DRVHx 1 shot LLx PGNDx gt gt VREGS 0 DRVLx ux vox On Off time Minimun On Off gt OVP UVP Fault Discharge Control Sdn PGNDx ENx gt 2164541 1 2 3 4 5 6 74 8 9 18250 300 090319 eps 090319 Figure 8 1 Internal block diagram and pin configuration 2009 May 08 EEJ Data Sheets 8 2 Diagram SSB Front End 02 DRX3926K IC 7T50 Block Diagram
135. C2 2FJA C3 2FJB C3 2FJC C3 2FJD F12 D 2FJJ B8 2FJK B7 2FJP B3 3FHO H2 3FH1H2 2 H2 3FH3 H3 3FH6 H3 3FH7 H3 3FH8 D9 3FH9 1 D9 E 3FH9 2 D9 3FH9 3 E9 3FHB 1 E10 3FHB 2 E10 3FHB 3 E10 3FHB 4 E10 3FHG C9 3FHJ C12 3FHK C12 3FHL B11 3FHM B12 A2 F 5FH1 B2 5FH2 C2 5FH3 D2 E2 6FHO 12 6FH1 12 2 12 6FH3 13 6 6FH7 6FH8 B12 7FHO B8 G 2 C12 D11 B2 D6 B3 FFH2 B3 FFH3 C3 FFH4 D3 5 E10 FFH6 E10 H FFH7 E10 FFH8 E10 FFH9 E10 FFHA E3 FFHM B9 FFHN B9 FFHP B9 FFHR C9 FFHS C9 FFHT C11 IFH4 10 11 12 13 CHN SETNAME CLASS NO Maelegheer Ingrid PGA WOW POWER amp CONTRO TV543 R2 LDIPNX 8204 000 8933 2 2008 11 21 SUPERS 130 5 DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS 2007 10 1 12 13 14 2009 08 15 16 17 18 19 20 18310 531 090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA ERE _ SSB FPGA WOW DDR f gp 2 3 4 5 6 1 2 3 4 5 6 7 8 9 2FL1 1 2FL2B3 2FL3 B4 2215 B5 2 16 1 zu B 2FL9 B6 2FLA B8 2FLB B8 A 2FLCB8 2FLD C6 2FLE C6 2FLF D7 2FLH C7 2FLK C8 2FLL C8 2FLM C8 2FLNC9 2FLP A1 B 2FLR B4 2FLS B4 3FLO B4 D 3FL2 C4 3FL3 C4
136. D 3HWV 1 B10 3HWV 2 C10 3HWV 3 C10 3HWV 4 B10 7 00 12 9 G33 2 73HWR 2 631 1 BAW gt THUS ES 630 V VATR2 73HWN 2 2 CA MDI2 HP 1182 E H34 3HWR4 4 5 478 E 9 06 2 2 F34 47R 1 8 3HWR 1 CA MDI4 9H06 3 B2 EE 3HWV 4 EY 5 5 CA MDI5 9H06 4 B2 634 EG 6 47R rene gt ee 331 2 7 3HWV 2 CA MISTRT 9H07 3 B2 47R 9 07 4 82 2 3HWVS 9 08 1 C2 nu nas MS B31 CA ADDEN 4 B2 9HWO0 D6 2 CA CD1 9HW1 D10 2 CA CD2 9HW2 C8 50 F2 AS IHWO 06 cat G 234 IRQ CA C34 CA RST caa D LASS J32 c CA VS1 H A34 Dw 22 VS2 J F K G L M 10 11 N CHN SETNAME CLASS NO 2 200 1121 CONDITIONAL ACCESS 71 8204 000 8927 PNX8543 TV543 R2 LDIPNX 2008 10 10 Maelegheer Ingrid SUPERS 16 130 14 2 DATE 2008 06 05 ROYAL PHILIPS ELECTRONICS 2008 9 2009 08 12 13 14 15 16 17 18 19 20 18310 515 090302 5 090302 Circuit Diagrams PWB Layouts 10 101 SSB 8543 Digital Video Out LVDS i 1 2 oq 4 4 5 6 8 9 10 11 i 15 1 2 3 4 5 6 7 8 9 58 7H00 5 6 FEVER Fe 543 DIGITAL VIDEO OUT LVDS EZ gt IHPG A7 PHILIPS UJ UJ 7H00 5 PNX85439EH M
137. DC DC Circuit Diagrams and PWB Layouts Q549 2E LA 10 LI AAN 2009 08 NY 2006 10 2U0F A5 2UOR 610 2U0VE12 2U10C14 2015813 201 14 2U55D4 2U59 E2 2U63 6 3U09 H9 3U0J 9 3U16 C5 3U1D 6 3020 05 3U24 F7 3074 9 5001 B9 5033 1 3 7003 03 7009 1 FUO06 F5 FUOB E14 1007 E9 B6 1011 B6 1U1D 610 IU1TA13 105603 1060 2007 E11 2U0H 2008 F1 200 5 2U11C14 2016 E13 2U39 B6 2U56 D4 2U60 6 2U64 G9 3U0A H10 9 3017 D3 3U1J 614 3021 E2 3025 F8 3075 610 5002 13 6002 2 7005 C8 CU77 G2 FU07 B9 FUOC B14 1008 B9 1005 65 1U12 D7 F9 1030 6 1057 D3 1061 05 2U0B 9 200 E9 2UOTE11 200 12 2U12C9 2017 E13 205007 2057 D2 2061 4 2065 G8 3U0F H5 3U13 C7 3018 05 3U1MB9 3022 3030 6 3076 E11 5003 C13 6003 05 7006 D8 FU04 2 FU08 614 FUOEC14 D7 G9 1019 H9 6 1031 69 1058 1062 6 2000 H6 2U0K F9 2000 E12 2U0ZB10 2U14A12 2019 13 2054 2 2058 03 2062 2 3006 B6 3U0G 6 3015 5 3019
138. DDC SCL 3 58 3P61 AIN 5V BIN 5V 47K 3 63 BRX DDC SDA BRX DDC SDA p gt BIN 5V BRX HOTPLUG 2322 25 24 be DCTROTSWBER220 HDMI CONNECTOR 1 BP1A PCEC HDMI CRX DDC SCL FI CIN 5V gt CRX HOTPLUG 2 FPOA 7 bs 22 5 24 pe DC1RO19WBER220 HDMI CONNECTOR SIDE 1 05 BP5J e BP5K CIN 5V CRX DDC SDA CRX DDC SCL CRX DDC SDA 47K 47K 3P67 3P68 CIN 5V DRX2 DRX2 e BPEL DRX1 5 DRX1 e gt BPSN lt e gt DRXO BP5P DRXO e DRXC 55 DRXC PCEC HDMI FPOR gt DRX DDC SCL DRX DDC SCL 3P64 47K BIN 5V DIN 5V 3P65 AK bd e Pos S DRX DDC SDA DRX DDC SDA 3P66 7 01 1011170118 FPA2 4V amp HDMI IN COM 4 313 i 220 16V 2 03 PSU errs e Pu 1 5 100R WC EEPROM PNX5100 BC847BW 7 12 WRITE PROT 28 3P53 22K 3 3 DIN 5V FPOT FPOU 0 p gt DIN 5V DRX HOTPLUG 20 e BPW dciRoTeIB1E40p 47K
139. DDR2 DQS1 P 2x HDMIA RX2 BO6F 1x MM1 D12 01 33VTUN 3x AP SCART OUT R BOSH 1 BACKLIGHT PWM ANA DISP BO7D 4 CIN 5V 2x DDR2 DQS2 N BO4H 1x HDMIA RXC BO6G 1x MM1 D12 B02A 33VTUN B07D 2 ARXO BOSH 2x BACKLIGHT PWM ANA SSB 2x CLK OUT2 PNX5100 2x DDR2 DQS2 P 2x HDMIA RXC BO6F 1x 1 013 1 43V3 BO7D 2x 2 B IF N IF 1 CLK OUT PNX5100 2x DDR2 DQS3 N BO4H 1x HDMIA RXC BO6G 1x 1 013 01 43V3 BO7D 2x 1 2 3 B IF _N IF BO6A 1x CLK OUT PNX5100 2x DDR2 DQS3 P 2x HDMIA RXC BO6F 1x 1 014 43V3 BO7D 2x 1 BO7D 4 BIN 5V 1x CLK OUT PNX5100 DDR2 ODT BO4H 1x HDMIB RXO BO6G 1x 1 014 BO4A 43V3 BO7D 2x ARX2 2x BL CLK BO6E 1x CON20 DDR2 RAS BO7D 1x HDMIB RXO BO6F 1 1 015 BO4L 43V3 B07D 2 ARX2 2x BL CS BO6G 1x CON20 2x DDR2 VREF CTRL BO4H 1x HDMIB RX0 BO6G 1x 1 015 B04M 43V3 BO7D 2x ARXC 2x BL HS BO6E 1x CON21 DDR2 VREF DDR 070 1x HDMIB RX0 BO6F 1 MM1 D2 BO4N 43V3 BO7D 2x ARXC 2x BL MISO BO6G 1x CON21 DDR2 WE BO4H 1x HDMIB RX1 BO6G 1x MM1 D2 4 43V3 B07D ARX DDC SCL 2x BL MOSI BO6E 1x CON22 DETECT1 BO7D 1x HDMIB RX1 BO6F 1
140. DDR2 VREF DDR a 8 B 2039 12 PNX5100 DDR2 A7 2 7 7 PNXS100 DDR2 D7 2C40 16 B PNX amp 100 DDR2 A8 2 126 1 8 PNX5100 DDR2 D8 2C41 1 F1 PNXS100 DDR2 A9 2 9 PNX5100 DDR2 D9 E 2 41 2 F1 PNX5100 DDR2 A10 2 726 jio 10 PNX5100 DDR2 D10 82 8 gt D DDR2 5 PNX5100 DDR2 D11 Sot T PNX5100 DDR2 A11 11 41 2041 3 N PNX5100 DDR2 A12 __ MA 12 23 PNX5100 DDR2 D12 2041 4 F2 6 13 23 42 PNXS100 DDR2 D13 2042 1 F2 PNX5100 DDR2 BA0 R26 24 72 PNX5100 DDR2 D14 I 2C42 2 F2 PNX5100 DDR2 BA1 125 V24 S PNX5100 DDR2 D15 le nag 1 F26 PNXS100 DDR2 D16 2042 3 F2 BA2 16 d 2 42 4 17 a PNX5100 DDR2 D17 18 625 72 PNX5100 DDR2 D18 2 43 1 PNX5S100 DDR2 RAS 24 lease 2 26 22 C PNX5100 DDR2 D19 2043 2 E E PNX5100 DDR2 CAS gt 124 sn 20 K26 2 PNX5100 DDR2 D20 2C43 3 F8 PNX5100 DDR2 WE 0 pi 025 gt PNXS100 DDR2 D21 2043 4 F8 PNX5100 DDR2 CS 2 1 22 S PNXS100 DDR2 D22 2C44 1 F9 2302 PNX5100 DDR2 D23 PNXS100 DDRZ ODT 24 PNX5100 DDR2 D24 2 44 2 F9 PNX5100 DDR2 CKE 23 25 __ 24 __________ 100 0082 025 2C44 3 F9 5 6 1 IREF 27 C2 1 PNX5100 DDR2 VREF CTRL p gt 224 REF 28 PNX5100 DDR2 D28 A 1 4 pes T 29 D23 PNX5100 DDR2 D29 3C01 D2 F PNX5100 DDR2 CLK_P 820R 1 100 P26 Pim PNXS100 DDR2 D30 3C02
141. DQ1 14 BO4H 1x HOT PLUG A BO6F 1x MM1 D9 B07D 43V3 BO4M 1x AUDIO HDPH R AP BO8D 2x BO CVBS BO7D 2x CRX1 BO6F 2x DQ1 15 BOTE 1x HOT PLUG A 1x MM1 D9 BO7F 43V3 BO8C 1x AUDIO HDPH R AP 8 2x BO G BO7D 2x CRX2 BO6F 2x DQ1 2 BO4K 1x H SYNC VGA BO6F 1x MM1 DQSO 43V3 8041 1x AUDIO IN1 L BO4A 2x BOLT ON IO BO7D 2x CRX2 BO6F 2x DQ1 3 BO8B 1x H SYNC VGA 1x MM1 DQSO B07H 43V3 BO8D 2x AUDIO IN1 L BO4N 1 BOLT ON IO BO7D 2x CRXC 2x DQ1 4 BOAN 1x 12C SCL BO6F 1x MM1 DQS1 43V3 BO4L 1x AUDIO IN1 R 8 BOLT ON IO BO7D 2x CRXC BO6F 2x DQ1 5 BO7F 1x 12C SCL BO6G 1x MM1 DQS1 B08B 3V3 BO8D 2x AUDIO IN1 R BO4A 2x BOLT ON TS ENn BO7D CRX DDC SCL BO6F 2x DQ1 6 BOAN 1x I2C SDA BO6F 1x 1 43V3 8041 1x AUDIO IN2 L 4 1x BOLT ON TS ENn BO7D CRX DDC SDA BO6F 2x DQ1 7 BO7F 1x I2C SDA BO6G 1x 1 BO9A 43V3 1x AUDIO IN2 L BOSH BOOST CTRL BO7D 2x CRX HOTPLUG BO6F 2x DQ1 8 2x IDSEL B02A 3V3A BO4L 1x AUDIO IN2 R BO4E 2x BOOTMODE 4x CSO B BO6F 2x DQ1 9 2 1x IF 2 1 AUDIO IN2 R BO8D 2x BO R BOSH 2x CTRL1 PNX5100 BO6F 2x DQS10 2 1x IF 2 3V3D 8041 1x AUDIO IN3 L BO7D 2x BRXO BOSH 2x CTRL2 PNX5100 BO6F 2x DQS11 2 1x IF 43V3E BO8B 1x AUDIO IN3 L BO7D 2x BRX0 BO
142. Diagrams and PWB Layouts Q549 2E LA ELE SSB U Wand All rights reserved Reproduction whole or in parts PHILIPS gt UJ 1 10 5FC5A3 5FC7 C 1R20 5FC6A2 5FC8 5FC9A3 FFC3A3 FFC5A3 FFHCB3 FFHEB3 FFHGC3 FFHJC3 A2 FFC2A3 FFC4A3 FFHBB3 FFHDB3 FFHFC3 FFHKC3 FFHL C3 IFCO 2 1 2 3 4 IFC1 A3 IFC5 A2 5 8 8 5 D ow 8 RES U WAND 5 E IFCO 5FC5 FFC2 A 55 IXD MIPS2 8 1 5FC6 30R 2 E 92 308 5 e FCA v 30R 3R ynn FFCS 30R JZ 1735446 5 F B 1 10 5 _ 2 EJTAG DETECT EJTAG TDI 2 21 EJTAG TDO _ _ FOR FACTORY EJTAG TMS FFHFe 2 E E EJTAGTCK ye FFHGe USE ONLY G FFHJ pire 5 147279 3 H 1 2 3 4 CHN SETNAME CLASS NO 2008 11 21 U WAND 2008 10 10 TV543 R2 LDIPNX 8204 000 8933 NAME Maelegheer Ingrid SUPERS DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS N V 2007 1 2 3 4 5 18310 528 090302 5 090302 2009 08 Personal Notes
143. E 10n RES 2121H6 F112 G8 8 8 T vem gt MLEDIE sls 845857 3138 2122 F9 F116 A10 ATPase 2123 F10 F117 B13 57 L 7116 1 5 2124 F10 F118 C11 zl I 2125 B3 F120 A1 c 3 2126 10 F121 1 1 3141 2127 B1 F122 A1 4 F118 2128 1 F123 A1 2 i rag gt lt 10K RES 2129 B2 F124 B1 A lt 2 77 42 2130 2 F125 B1 E 8 4 conmo Y CER 2131 F10 F126 1 5 m 3101 2 D7 F127 1 SIE 55758 3101 3 09 F128 B1 Sop _ Fio 3101 4 9 129 Bi 9 TEMP SENSOR 3102 1 D9 F130 B1 10 PROG Ss s S S 5 5 5 3102 2 09 F131 B1 LL FEET ue cm ee E I 5102 3 E9 F132 B1 F 42 3102 4 D9 F133 E1 e ia F108 M fe fe le fe 3103 1 9 F134 1 T x e 3103 2010 F135 E1 MS 2 x 3 Ia l 255255 75 5 5 El 5 3103 3G11 F136 F1 lt e 3103 4010 F137 F1 NN 3104 1 08 F138 F1 d 5 3104 2 F139 F1 sx 3104 3 1110 G8 G gle o 5 2 3104 4 09 1111 G8 RS ETE gt lt 2 3105 1 E9 1113 G10 5 _ 3105 2 08 1114 610 ilo j fo te fo 3105 3 1115 010 ae L ME 5 5 3105 4 08 1124 E11 7102
144. H6 F108 D7 F132 11 4 2120 H6 F109 G3 D 13 ER 5 14 3 8 1105 1 101 RES 2121 H6 F112 G8 68 Bal B Md eee 33 slg 81585 2122 F9 116 10 Do YQ T Tod 7 zi I 2125 F120 A1 L c 2126 10 F121 A1 1M1A 1 3141 2127 B1 F122 A1 E gt yy 2128 B1 F123 A1 E gt fee 1 m p lt 2129 2 124 1 SDA 2130 F2 F125 B1 3 gon 4 CONTROL 1 1 A S L 2131 F10 F126 B1 5 CONTROL PESE 3101 2 D7 F127 B1 J pave 82882 an 3101 3 D9 F128 1 8 gt Pior 3101 4 9 F129 1 5 2 TEMP SENSOR _ EUER 5 3102 1 09 F130 1 ia gt PROG NENNEN 3102 2 D9 F131 B1 RM VEDI ele E lt lt lt E 3102 3E9 F132B1 F 12 lt lt 383 lt lt lt 3102 4 D9 F133 E1 a 2 e gt Sen i s F108 3103 1 9 F134 F1 i 516 x 3103 2 G10 F135 E1 255255 p 8 3 8 massis 3103 3611 F136F1 5 2112 5 3103 4G10 F137 F1 3104 1 D8 F138 F1 al e a B E 3104 2 F139 F1 G Gee lel lel lel vex x z 3104 3 1110 G8 G 52 7 zz e ee 310819 118010 S ee lt 212 3105208 1114610 e fo Jo le lef Jo 3105 3 E8 1115 610 us a els 5 3105 4 1124 E11 7102
145. HIV2 FPGA ge b 1V2FPGA ge Uu 41V2 FPGA ge cine 013 vs port V2 FPGA 1V2 FPGA ge N AV2 FPGA gt N9 4205008 1 vecios B8 4250081 H 42N5 DDR H M CHN SETNAME CLASS NO 2008 11 21 2008 10 10 Maelegheer Ingrid SUPERS 130 7 CHECK DATE 2007 12 06 ROYAL PHILIPS ELECTRONICS N V 2007 10 2009 08 NY 11 12 13 14 15 16 17 18 19 20 _ 18310_533_090303 eps 090303 All rights reserved Reproduction in whole or in parts Circuit Diagrams and PWB Layouts Q549 2E LA ZEILE SSB Cl PCMCIA Connector 2 3 4 5 s 12 3 2 1 Gi is prohibited without the written consent of the copyright owner 1 00 1 2P16 C8 1 00 B5 2 40 2 2P15 A8 3P09 A2 3P10 1 A6 3P11 C7 3P10 2 A6 3P12 A6 3P10 4 A6 3P13 1 A6 3P13 2 A6 3P24 D6 3P13 3 A6 3P25 E6 3P20 D2 3P26 1 6 gt PCMCIA VCC VPP PCMCIA D3 PCMCIA D4 PCMCIA D5 RDY BSY VCC1 16 y 1 PCMCIA VCC VPP CA MIVAL A15 12 AT PCMCIA A7 A6 PCMCIA A6 A5 PCMCIA AS 4 4 RIOR AA 2
146. INA L 1 ele lt o9 og RTE 8558 HES f 9 alt ofc 8 8 a a 1 YKB11 3004 vl gt AUDIO IN4 R 2 Fpo4 TPOB 1 RT ER 98 8 1 B2 1 02 1 9 1P9B D3 2P06 B2 2P07 B3 2P08 B4 2P09 D2 2P10 D3 2P11 D4 3P05 B3 3P06 B4 3P07 D3 3P08 D4 6P01 B3 6P02 D3 01 D2 02 B2 FP24 D2 06 B4 IP07 D4 CHN SETNAME CLASS_NO UFD2K8 DIGI TV543 R2 LDIPNX 8204 000 8934 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS N V 2005 8 2009 08 9 10 12 13 18310 535 090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA SSB USB Connector T 71 Personal Notes gt 1P07 C4 1P10 C2 2P17 A1 PHILIPS UJ 2P24B2 2P31A1 3P18A2 3 23 4 2 27 1 3 16 2 19 3 55 4 2 30 1 3P17A2 3P21A3 3 56 4 3 59 2 5 07 2 FP27C3 FP2AC3 IP13C2 3P60 B2 9 21 FP28C3 45 1 19 2 3P62B2 9P22C3 FP29C3 IP12A2 220u 16V 330u 10V 2P17 220 16V 2P31 is prohibited without the written consent of the copyright All rights reserved Reproduction in whole or in parts 47u 6 3V USB CONNECTOR 1 07
147. IPOJ 3V3 ET DIG INOLA 5 3 3NONS 22R 33R a 3NOL 3 6 5 L FNOS INOP NU A 7340522 22R 33R 33R 22R ele 278 BNOA we 5 08 8 5 2 amp RS 8 5 BNOC 2 gt T FNOS 7NO4 1 e e DP83816AVNG anor 5 ETHERNET CONNECTOR EN AUXVDD PCIVDD MacPhyter AUXVDD 100n IPOH ICLKRUN 10 100 Mb s TPTDP 54 123 PwRGooD TPTDM 5s gt 122__ TPRDP B IRQ PCI 81 TPRDM n mm FNoo PCI CLK ETHERNET 60 PCICLK x 17 PCI PAR 99 PAR x 18 3NOF INOT i 470R gt 92 IRDY VREF 40 d PCLTRDY 5 23 coL 28 PCLPERR 97 do 5 5 gt tI PERR CRS 5 PCLSERR 98 5 91 bio 4 50 2 T 25M PCI GNT ETH gt 83 RXCLK PCLSTOP 9 8t
148. Mains 198 265 Vac 47 the Integrated Power Board IPB incl inverter is used For sets of 52 and 56 a conventional PSU with additional inverters is used In this manual no detailed information is available because of design protection issues The output voltages to the chassis are e 3V3 STANDBY standby mode only 12 on mode e Vsnd 24V audio power e 24 bolt on power e IPB High voltage to the LCD panel for sets up to and including 47 2009 May 08 7 3 7 4 Front End The Front End consist of the following key components e Tuner HD1816AF e SAW filter 36M125 IF demodulator DRX3926K amplifier UPC3221GV Below find a block diagram of the front end application 12C SSB CVBS Hybrid Tuner DRX3926K PNX8543 Filter Figure 7 4 Front End block diagram I2C TUNER 18440 211 090227 eps 090227 The DRX3926K is a multi standard demodulator supporting DVB C DVB T and analogue standards The demodulated digital stream is fed into the parallel transport stream data ports of the PNX8543 The demodulated analogue signal in the form of CVBS is connected to the analogue video CVBS Y input channel while the SIF is connected via the SSIF2 positive input port HDMI In this platform the TDA9996 HDMI multiplexer is implemented Only for one HDMI input a separate EEPROM is implemented to store the EDID values For the
149. N V 2005 10 11 12 13 18310 516 090302 eps 090302 2009 May 08 rights reserved Reproduction in whole or in parts Circuit Diagrams and PWB Layouts 549 2 10 102 SSB 8543 Power is prohibited without the written consent of the copyright owner 2 12 13 14 15 16 17 18 19 20 1 2 3 4 6 7 8 9 10 11 12 13 14 ata Ba 2H14 D2 5HVC C13 2H15 A3 5HVD C13 2H16 A3 5HVE B12 4 PNX 8543 POWER 2H17 A3 5HVF B13 IHY4 5HVH 2H18 A3 5HVG B10 43V3 PER lt 4 q
150. PNX5100 TRI PLL3 8 15 2082 F6 TH SOR 315 SIUS 2C83 F6 rn e rom 5 E vss 712 974 5C69 ices 2C84 D8 3 3 Be M gt 3V3 PNX5100 DDR PLLO 2 85 09 5C64 84 30R p 2 86 D9 pe vv p gt 1V2 PNX5100 DDR PLL1 gis 818 2 87 09 25 4 W23 Sis 3165 2 88 9 AE26 RTE 2C89 E9 AE26 L 1 a 5C70 1c90 2C90 F9 H ne 5C65 1 85 33 pen RM 4 e 3V3 PNX5100 LVDS PLL 2091 F8 F 1V2PNX5100 pe o 5 gt 1V2 PNX5100 LVDS PLL lu cores gis STR 2 94 F7 SIS 5 2C95 A1 S 18 2 96 2 uu 2C97 A2 5C60 D6 5C61 06 CHN SETNAME CLASS_NO 2008 11 21 i TV543 R2 LDIPNX 8204 000 8928 2008 10 10 NAME Maelegheer Ingrid SUPERS 9 DATE ROYAL PHILIPS ELECTRONICS 2008 5 6 7 8 9 10 11 12 13 18310 520 090302 eps 090302 2009 08 SSB 5100 Audio Circuit Diagrams and PWB Layouts Q549 2E LA HIA 13 gt gt All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright PHILIPS Cy 79 2 amp E PNX5100E 395 4 4022 AUDIO NAY BL OSCLK AD22 AC21 4 5 SCK SCK 100R 3C95 1 AAA BL SCK AF22 1 toon 8 AD23 0 BUT AE21 30993 BL SD0 AE23 sp 550 3 y 6 AF23
151. PO TBICAP1 3ISDA1 8 31274 4 5 1008 SDA 3128 14 T 8 2 5 PO 19IMAT1 2IMISO 8 1008 3124 1 11 51 17 527 PO 20MAT1 2IMOSH oath x 3124 2 E11 J 2 Po 211SSEL1IMATS 0 3 ELSECSETSERCSSLSSOSRISS SB S 3124 3 E11 T P0 221AD0 0 55 o 3124 4 E11 I L F109 Po 231AD0 1 32 3125 1 F11 0 241 00 2 dee Po2slApo c 38 3125 2 F11 5 4 739 UD MD 1M2A NC 26 7 iti 3125 4 F11 SPI CLOCK BUF EE PO2TITRSTIGAPAD t 3126 1 F11 4 SPLDATA RETURN 16 114 4 51033 6 3126 4 F11 K 2 SPI LATCH Se POO 16 1773130 fis 31032 2117 3127 1 F11 5 2 PWN CLOCK BUF AL VOD3V3 vona 2 10K 3127 4 F11 7 BLANICBUF E S y sh EE 52 3128 E11 H EEPROM CS AAA u Sievert 9 TEMP SENSOR 3130 G8 10 PROG ass 3131 G7 44 me aE is sis 88 7527527 3132 8 SIS He L a F103 p e 1V8 gt 3136 12 53 58 els 3137 B11 28878558 P48 3198 B13 3139 12 3140 C11 3141 3142 F11 7101 7 7102 6 7110 F4 7116 1 11 1X03 REF EMC HOLE E CHN SETNAME 7 CLASS NO 2008 06 10 DRIVER 6LED LITEON 2008 08 08 2008 08 08 2 2 9 3104 313 6314 3 NAME Peter Van Hove SUPERS 3 CHECK DATE 2008 06 02 5 ROYAL PHILIPS ELECTRONICS
152. SCL DISP BOSE 3x TX2A BO6D 1x BO6G 1x MSELO BO7H 1x PCI AD26 BO4F 2x PCI REQ 2x PNX5100 DDR2 DQM1 BO1B 1x SCL SET BOSE 3x 2 BO6G 1x TXF1A BO6G 1x MSEL1 BO9A 1x PCI AD26 BO4F 2x PCI REQ B 2x PNX5100 DDR2 DQM2 BOE 2x SCL SET BOSE 3x TX2B BO6D 1x BO6G 1x MSEL2 1x PCI AD27 1x PCI REQ ETH 2x PNX5100 DDR2 DQM3 BOGA 5x SCL SET BOSE 3x TX2B BO6G 1x BO6G 1x MSEL3 8056 1x PCI AD27 BO7G 1x PCI REQ ETH 2x PNX5100 DDR2 DQS0_N BOGC 2x SCL SET BOSE 3x TX2C BO6D 1x 1 2x NAND AD 0 BO7F 1x PCI AD27 1 PCI REQ MINI 2x PNX5100 DDR2 DQS0_P BOGA 2x SCL SETO BOSE 3x 2 BO6G 1 1 2x NAND AD 1 BO7G 1x PCI AD27 BO9A 1x PCI REQ MINI 2x PNX5100 DDR2 DQS1_N BOGA 2x SCL SET1 BOSE 3x TX2CLK BO6D 1x 1 2x NAND AD 2 BO7H 1x PCI AD27 BO4F 2x PCI SERR 2x PNX5100 DDR2 DQS1_P 2 2x SCL SSB BOSE 3x TX2CLK BO6G 1x 1 2x NAND AD 3 BO9A 1x PCI AD27 8056 1x PCI SERR 2x PNX5100 DDR2 DQS2_N 2x SCL SSB BOSE 3x BO6D 1x TXF1C 2x NAND AD 4 1x PCI AD28 8076 1x PCI SERR 2x PNX5100 DDR2 DQS2_P BOSF 2x SCL SSB BOSE 3x TX2D BO6G 1x 1 2x NAND AD 5 8056 1x PCI AD28 1 PCI SERR
153. WE K3 E2 DDR2 WE 5 K3 22 DDR2 CS 18 DDR2 CS Ed SDRAM no 3HHH G14 DDR2 RAS SDRAM DDR2 RAS 27 3HHJ G13 DDR2 CAS 17 R8 DDR2 CAS LT R8 3HHK G14 3HHM G13 DDR2 BAO L2 DDR2 BAO gt 12 0 3HHB 3HHN G14 DDR2 BAt 68 AOT DDR2 DO DDR2 BA1 68 DDR2 D16 3HHP G13 ge DDR2 BA2 L1 EDE1116AEBG 8E 3HGR 33R DDR2 D1 DDR2 BA2 L1 3HHC 33R DDR2 D17 28 2 DDR2 D3 ENARE 9 V 3HHR G14 DDR2 A0 M8 DDR2 D2 DDR2 A0 33R_33R DDR2 D18 613 5E DDRZ A1 M3 BR 3HGU DDR2 D4 N DDR2 A1 d DDR2 D20 3HHT G14 5 DDR2 A2 M7 MNT 3HGV 33R DDR2 D5 IN DDR2 A2 41 9 3HHG SHHE 7 Ssh DDR2 D21 3HHU G13 DORAE 2 33R 3HGW DDR2 D6 4 DDR2 A3 13 39R SHH DDR2 D22 3HHV H10 55 DDR2 A4 N8 29 3HGY 33R 25 DDR2 D7 N DDR2 A4 7 29 3HHJ 33R DDR2 D23 58 DDR2 A5 N3 IR 3HGZ x DDR2 D8 7 DDR2 A5 NS cs 33R 3HHK DDR2 D24 3HHW H10 5 DDR2 A6 7 3HHO DDR2 D9 N DDR2 A6 6 3HHM DDR2 D30 3HHY H9 DDR2 A7 P2 10 27 33R 3HH1 DDR2 D10 J DDR2 A7 2 10 27 33R SHHN DDR2 D26 G 3HHZ H10 52 DDR2 A8 P8 411 03 3HH2 33R DDR2 D11 DDR2 A8 P8 1 111 03 33R DDR2 D25 3HJ0 C1 88 DDR2 A9 P3 Pm
154. Warnings Route the wire trees correctly and fix them with the mounted cable clamps Check the insulation of the Mains AC Power lead for external damage Check the strain relief of the Mains AC Power cord for proper function Check the electrical DC resistance between the Mains AC Power plug and the secondary side only for sets that have a Mains AC Power isolated power supply 1 Unplug the Mains AC Power cord and connect a wire between the two pins of the Mains AC Power plug 2 Set the Mains AC Power switch to the position keep the Mains AC Power cord unplugged 3 Measure the resistance value between the pins of the Mains AC Power plug and the metal shielding of the tuner or the aerial connection on the set The reading should be between 4 5 MQ and 12 MQ 4 Switch off the set and remove the wire between the two pins of the Mains AC Power plug Check the cabinet for defects to prevent touching of any inner parts by the customer 3 3 3 3 3 4 3 3 5 All ICs and many other semiconductors are susceptible to electrostatic discharges ESD 4 Careless handling during repair can reduce life drastically Make sure that during repair you are connected with the same potential as the mass of the set by a wristband with resistance Keep components and tools also at this same potential Be careful during measurements in the high voltage section Never replace modules or other components while the unit is swit
155. ale 6E40 F4 Ee BTE te 2 18 xoe ale zi 6 46 1 1 9 8 8 RES CVBS MON OUT CINCH _9 07 _ 6E47 E10 FE43 8 6E48 F10 Y CVBS MON OUT 6E51 H4 l c 1 L c L 6 52 G4 CHN SETNAME CLASS NO 2008 11 21 ANA SIDE 2008 10 10 3 NAME Maelegheer Ingrid SUPERS 4 DATE 2008 01 18 ROYAL PHILIPS ELECTRONICS N V 2005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NY 2009 May 08 18310 543 090303 090303 Circuit Diagrams and PWB Layouts Q549 2E LA GEJ _ SSB Analogue Externals C Ge ap 3 4 6 8 9 10 HM x 13 1 2 3 4 5 6 7 8 9 1000 FE87 B7 1002 E2 FE88 B7 1003 D3 FE89 B8 1004 C2 90 ANALOGUE EXTERNALS C 1005B2 FE91D7 1006 B3 FE98 B8 T T 1 1007 1 58 C4 1010 4 66 5 _ 1E11 1 C1 1 67 F5 RESERVED 1511202 187205 1 11 3 02 FRONT C 1E14 B1 1E15 E2 B 5 1 36 8 Were REM 1 1008 AUDIO INS L 2E35 A3 T 8 VY gt 2 36 B3 gt 0 Nd RES 3E74 V 75R 53 4 Op 4 m A 1 1 gt PHILIPS V NOM 1007 35 6 20 12V UJ FRONT Y CVBS SVHS IN 5 AUDIO INS R 2E37 D3 ps gt FRONT Y CVBS ATS 100R 2E39 F4 A 8 8 2 40 F5 FRONT C
156. blocked and the set reboots CSM and SAM are not selectable From consumer mode LAYER 1 From SDM mode LAYER 2 Important remark 2009 May 08 Q549 2E LA Service Modes Error Codes and Fault Finding 5 5 2 5 5 3 5 5 4 For all errors detected by MIPS which are fatal gt rebooting of the TV set reboot starts after LAYER 1 error blinking one should short the solder paths SDM at start up from the power OFF state by mains interruption and not via the power button to trigger the SDM via the hardware pins n CSM mode When entering CSM error LAYER 1 will be displayed by blinking LED Only the latest error is shown n SDM mode When SDM is entered via Remote Control code or the hardware pins LAYER 2 is displayed via blinking LED e Inthe ON state n Display error mode set with the RC commands mute 06250 _OK LAYER 2 errors are displayed blinking LED e Error display on screen n CSM no error codes are displayed on screen n SAM the complete error list is shown Basically there are three kinds of errors e Errors detected by the Stand by software which lead to protection These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error see section 5 6 The Blinking LED Procedure Errors detected by the Stand by software which not lead to protection In this case the front LED should blink the involved error See also sectio
157. channel decoder Initialize source selection Initialize video processing IC s initialize Initialize Ambilight with Lights off Semi Standby Figure 5 5 Off to Semi Stand by flowchart part 2 2009 May 08 1 17660 125b eps 140308 Service Modes Error Codes and Fault Finding Q549 2E LA ES Constraints taken into account Display may only be started when valid LVDS output clock can be delivered by the AVC Between 5 and 50 ms after power is supplied display should receive valid 4 clock action holder AVC minimum wait time to switch on the lamp after power up is 200ms action holder St by autonomous action Semi Standby The assumption here is that a fast toggle lt 2s can only happen during ON gt SEMI gt ON In these states the AVC is still active and can provide the 2s delay If the transition ON gt SEMI y gt STBY gt SEMI gt ON can be made in less than 2s the semi gt stby transition has to be delayed until the requirement is met Wait until previous on state is left more than 2 seconds ago to prevent LCD display problems Assert RGB video blanking and audio mute CPipe already generates a valid output clock in the semi standby state display startup can start immediately when leaving the se
158. ia 5 2 1306 1300 12 x CTRL po 2iscLoicaPo o 1 33068 Sp S CONTROLI 21 RES 3330 100R PO 3ISDAOIMATO O L PO AISCKOICAPO 1 22 yeas 3331 T 1812 33063 2 7 1008 SPL DATA RETURN RTXC1 PO SIMISOOIMATO 1 V 24 3806 1 1 8 100R SPLDATA OUT RTXC2 PO IMOSIOICAPO 2 Y PO 7ISSELOIMAT2 0 22 T 3306 4 4 5 100R SPLLATCH RTCK PO BITXD1IMAT2 1 22 4 33073 1 8 100R 1 SPI LATCH2 33 90 1313 3338 300R PWM CLOCK BUF gt 9301 4 lear n 33074 4 100R TEMP SENSOR 36 1314 3307 2 2 7 100R EEPROM CS PO 11ICTSTICAP1 11AD0 4 37 3308 4 4 5 100R 5 BLANK BUF P0 12IDSR1IMAT1 01AD0 5 4r 30822 V DBGSEL PO T8IDTRTIMATI 1 y gt PROG PO 14IDCD1ISCKTIEINTI 116 is F308 PO ISIHIIEINT2 39091 1 Soe CONTROL RST PO 16IEINTOIMATO 2 4 1317 1318 1302 47 1319 33094 5 4 ScL PO 17ICAP1 2ISCL1 5 3309 1 8 1 100R 5 P0 18ICAP1 31SDA1 48 m acy 2 7 g 1320 8 20 4 21 8 o ar gu 20 Po 211SSEL1iMATS 0 2 8 85 82 82 8 8 8 m 32 P0 231AD0 1 3 0 241 00 2 5 Lo x dL st x 1308 0 251 0 6 1307 Po 261AD0 7 92 UDMD 4 fava Po 27ITRSTICAP2 0 8 P0 28ITMSICAP2 1 els
159. memory test is shown now This is also visible on the TV screen n BOARDTESTLOGGER an option Send extra UART command can be found where you can select AUD1 This command generates hear test tones of 200 400 1000 2000 3000 5000 8000 and 12500Hz Error Codes Introduction The error code buffer contains all detected errors since the last time the buffer was erased The buffer is written from left to right new errors are logged at the left side and all other errors shift one position to the right When an error occurs it is added to the list of errors provided the list is not full When an error occurs and the error buffer is full then the new error is not added and the error buffer stays intact history is maintained To prevent that an occasional error stays in the list forever the error is removed from the list after more than 50 hrs of operation When multiple errors occur errors occurred within a short time span there is a high probability that there is some relation between them New in this chassis is the way errors can be displayed There is a simple blinking LED procedure for board level repair home repair so called LAYER 1 errors next to the existing errors which are LAYER 2 errors see Table 5 2 LAYER 1 errors are one digit errors LAYER 2 errors are 2 digit errors e n protection mode From consumer mode LAYER 1 From SDM mode LAYER 2 Fatal errors if I2C bus is
160. other HDMI inputs the EDID contents are no longer stored in a separate EEPROM but directly in the multiplexer Each input has its own physical subaddress the first 253 bytes are common where the last 3 bytes define the specific input The EDID contents are at 5V power up downloaded to RAM The following figures show the HDMI input configuration and EDID control WDMIB RX 8 HDMIA RX HDMI Side optional 9996 9 8 E 1P04 1P03 1P02 HDMI3 optional HDMI 1 18440 213 090227 eps 090227 Figure 7 5 HDMI input configuration Circuit Descriptions Q549 2E LA HI Platform with embedded EDID 253commorBytes 1B suladdres of Source hyscal Address 3B forinputA forinputB 3B forinputC 3B forinputD 4xHDMI inputs 18440 214 090227 eps 090227 Figure 7 6 EDID control embedded EDID The delta s with respect to the use of the TDA9996 as HDMI multiplexer compared with earlier chassis platforms are e 5V detection mechanism Stable clock detection mechanism e Integrated EDID control control e TMDS output control control e hotplug control for PNX8543 for 5th HDMI input e New EDID structure EDID stored in TDA9996 therefore there are no EDID pins on the SSB Only in the event of a 5th HDMI input an
161. to ensure that old error codes are no longer present If possible check the entire contents of the error buffer In some situations an error code is only the result of another error code and not the actual cause e g a fault in the protection detection circuitry can also lead to a protection There are several mechanisms of error detection e Via error bits in the status registers of ICs 2009 May 08 e Via polling on I O pins going to the stand by processor e Via sensing of analog values on the stand by processor or the PNX8543 e Via a not acknowledge of an communication Take notice that some errors need several minutes before they start blinking or before they will be logged So in case of problems wait 2 minutes from start up onwards and then check if the front LED is blinking or if an error is logged Service Modes Error Codes and Fault Finding Q549 2E LA ES Table 5 2 Error code overview Monitored Error Buffer Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board lt 2 13 5 BL 55 55 2 2 14 5 SSB Display SSB display PNX doesn t boot HW cause 2 15 Stby uP P BL PNX8543 PNX51XX 55 PNX 5100 doesn t boot blocked 12V 3 16 Stby uP P BL Supply Inverter or display supply 3 17 MIPS E EB 1V2 3V3 5V to low 2 18 Stby uP P BL
162. via an isolation transformer with low internal resistance Allow the set to warm up for approximately 15 minutes Measure voltages and waveforms in relation to correct ground e g measure audio signals in relation to AUDIO GND Caution It is not allowed to use heat sinks as ground Test probe Ri 10 MO Ci 20 pF Use an isolated trimmer screwdriver to perform alignments 6 3 2 Alignment Sequence First set the correct options n SAM select Options and then Option numbers Fill in the option settings for Group 1 and Group 2 according to the set sticker see also paragraph 6 4 Option Settings Press OK on the remote control before the cursor is moved to the left submenu Option numbers select Store and press OK on the RC OR n main menu select Store again and press OK on the RC Switch the set to Stand by Warming up 215 minutes Hardware Alignments Not applicable Software Alignments Put the set in SAM mode see Chapter 5 Service Modes Error Codes and Fault Finding The SAM menu will now appear on the screen Select ALIGNMENTS and go to one of the sub menus The alignments are explained below The following items can be aligned Tuner AGC White point To store the data Press OK on the RC before the cursor is moved to the left In main menu select Store and press OK on the RC Press MENU on the RC to switch back to the m
163. 0 FCBP E8 B19 Naxie 0 lt ES ros I ZCBAFIO UN A bi gt mS Cm 2CBB F10 B7 2 IX1D 2 4 4 7 2 F10 FCJ5C7 _ 2 019 2CAB 407 Pu 2085 47 TX3D lt Pe x 2CBD F10 ICA1 B8 TX2A EN RES MIXIE FCAS Em Ph SIKE RES 2 2 610 2 8 pags B18 18 Deer gt e 27 2 610 ICA9B1 18 26 D 2089010 lt AN DOA 45 TXAA FCB8 o 2 610 ICAE B14 TX1D 18 TX2A FCAD 15 5 Pus 23 2CBJ B13 TX2B FCAE 5 2CBK B13 gt C8 PN EN TX2B 5 FCAF H TX4B 5 hd pus z 2CBL B13 TXICLK lop GLKR DOC 5 e 12 FOBT 2 S lt 10072 LOUT S IX3CLK TX2C 5 11 5 Pe 19 2 VQ C7 cpl TIC RES TX2CLK at i dee RES IX4cLk gt ee 18 2CBP B13 e B7 B10 Z DIC 2 TX2CLK FCAK 2 6 TX4CLK ca FCBF 2CBR B13 e E z 2CB7 Pr 1 18 2 5 14 H ae DP DP 59 s XB neat RES TX2D 5 e cM RES 5 14 2 F8 TXIB 2 DN DN Qe 2 FCAN e 5 e
164. 0000 PNX8543xEH 000000 L T W AD 000000 AE 000000 AF AJ AL Transparent top view 18440_301_090303 eps 090303 Figure 8 3 Internal block diagram and pin configuration 2009 May 08 0549 2 Data Sheets 8 4 Diagram SSB Ethernet B05A PNX5120 7 2009 May 08 Block Diagram PNX51xx MEMORY CONTROLLER TM327x 1 Video UIP L3K7 gt x TM327x 2 lt gt TM327x 3 GIC 3 LVDS RX 2 r LVDS TX 1 2 lt gt I2C DMA T LVDSTX2 lt L3K7 LVDSTX3 LVDS TX 4 UART UART 16 X G
165. 000000000 0000000000 21 10000 001 090121 eps 090121 Figure 2 4 SCART connector 1 Audio R 0 5 Vams 1 kohm 2 Audio 0 5 5 10 kohm 3 AudioL 0 5 1 4 Ground Audio Gnd 5 Ground Blue Gnd 6 Audio L 0 5 10 kohm 7 Video Blue 0 7 Vpp 75 ohm 8 Function Select 0 2 V INT 4 5 7 V EXT 16 9 9 5 12 V EXT 4 8 9 Ground Green Gnd 10 n c 11 Video Green 0 7 Vpp 75 ohm 12 n c 13 Ground Red Gnd 14 Ground P50 Gnd 15 Video Red 0 7 Vpp 75 ohm 16 Status FBL 0 0 4 V INT 1 3V EXT 75 ohm 17 Ground Video Gnd 18 Ground FBL Gnd 19 Video CVBS Y 1 Vpp 75 ohm 20 Video CVBS 1 75 ohm 21 Shield Gnd Aerial In EC type EU Coax 75 ohm RJ45 Ethernet if present 12345678 E 06532 025 eps 210905 Figure 2 5 Ethernet connector 1 TD Transmit signal 2 TD Transmit signal 3 RD Receive signal 4 CT Centre Tap DC level fixation 5 CT Centre Tap DC level fixation 6 RD Receive signal 7 GND Gnd 8 GND Gnd D 4L DPO 2 4 Technical Specifications and Connections Q549 2E LA 5 Cinch Audio In VGA DVI Rd Audio 0 5 10 o Wh Audio L 0 5 10 kohm QO HDMI 1 2 3 amp 4 Digital Video Digital Audio In 19 1 18 2 _06532_017 25050
166. 008 11 21 2008 10 03 PNX8543 TV543 R2 LDIPNX ROYAL PHILIPS ELECTRONICS N V 2005 2009 08 9 10 11 12 13 18310 508 090302 5 090302 Circuit Diagrams and PWB Layouts Q549 2E LA 10 LIN _ SSB PNX8543 SDRAM 1 2 3 13 14 19 20 1 2 3 6 7 8 9 10 11 12 13 14 2Ho1 Es 2 1 2HG2 2HG3 8543 SDRAM 2HG4 E3 Tua 2HG5 E4 PNX85439EH M2 24182 2HG6 4 MEMORY 2HG7 E4 DDR2 A0 DDR2 DO 1V8 PNX85XX 1V8 PNX85XX 2HG8 E4 DDR2 A1 1 DDR2 D1 2HG9 DDR2 A2 gt DDR2 D3 DDR2 A3
167. 01 E_06532_038 eps 240108 Figure 5 2 Location of Display Option Code sticker Store go right All options and alignments are stored when pressing cursor right or the OK button and then the SW Maintenance SW Events Not useful for Service purposes In case of specific software problems the development department can ask for this info HW Events Not useful for Service purposes In case of specific software problems the development department can ask for this info Operation hours display Displays the accumulated total of display operation hours So this one keeps up the lifetime of the display itself mainly to compensate the degeneration behaviour e Test settings For development purposes only e Development file versions Not useful for Service purposes this information is only used by the development department Upload to USB To upload several settings from the TV to an USB stick which is connected to the SSB The items are Channel list Personal settings Option codes Display related alignments and History list First a directory repairV has to be created the root of the USB stick To upload the settings select each item separately press cursor right or the OK button confirm with OK and wait until Done appears In case the download to the USB stick was not successful Failure will appear In this case check if the USB stick is c
168. 05 3U1V F1 3U23 F2 3U31 G8 5000 E9 5U32A13 7U02B6 7008 A6 05 1006 G9 C7 1000 E1 IU1B C9 IU1R F1 1055 C4 1059 1063 05 gt 12VF1 FUOS 5U02 RES 6 12 5 10u ELSE a zlazla 5U32 RES ele jue i 67 Som L cia SI48008DY 5 598 _ t 12V 3V3 CONVERSION 1 9 8 5 3 9 2039 5001 Fuoc 1 0 e pe 23 3 10u E 2 2 8 5 2d 8 lt ars SI4800BDY 1008 D gle 5 aye 5003 FUOE uB 10u gt gt runs IM NE PS C T 3U15 T 5 2 Eng a mH 51480080 3016 Ls 5 4 10R 2 8 ays 558 2050 m 1056 2055 1061 1 w12 1 0 a if GND SIG 52 100 8 5285 8 815 8 lt 9 pS 1057 SFe 2565 B2 D TPSS3124PW BI ET Lu D VR 58 25 1063 da 83 6 1 vesri i 12V 1V2 CONVERSION DRVH2 5 H DRVL2 3U21 1058 44 5000 FUOB GND SIG ANA TRIP L 5 e ge 1V2 PNX85XX 20K BATS4COL 159 14 LL2 FUOA 10u 8 8 8 px vBsT2 x 5 5 8 ofS np 49 L tds 2 3U22 1060 18 M 88 1 19 voa 17 3 3 1030 N N R A La GND SIG 20 21 2 22 uou _ vsFiLt VREGS AKT 2
169. 1 2417 9 12 5 RES 2 gi RES 5 2 8 RES 8 B FEM AP SCART OUT R 838 Res axo uss 8 8 B 1 25 1 9 15 D5 aepo 1603 8 al 8 lt 1 26 7 9 16 5 2 2 1 27 17 9 17 5 eke l 1 1 l 1E31 B12 9 18 5 F 4 AP SCART OUT L BC847BS COL AP SCART OUT L 364 rd B 28141 9E19 F5 prs gle lt 2 04 C11 9E20 G10 lt ele 2 06 11 9 22 010 E a s u 8 quocp 8 gt 6 2 28 res 2 10 11 9E23 010 D RESHCS 8 RES P i 5 2 12 G12 9 24 10 8 2E13 G6 9E25 F10 A PLOP L 9 IE23 2 14 F12 9 26 610 1 gt gt SCART1 2 15 D12 9 27 G10 AUDIO IN2 L 2 16 05 9E33 F2 EU 2 AV1 2 17 E6 FE60 A7 SCART2 NSE SLE pes Ele at 1E01 2E18 E12 FE61 A7 Hes 1 8 t BOSE FE70 2E19 F6 FE62 B7 E acs glg 8 2 8 ___ _ FE63 D7 mar 1268 3 2E29 A5 FE64 D7 8 8 8 2E30 BS 65 E7 1 2 31 C5 FE66 E7 S E 2 32 85 FE67 E7 REGIMBEAU_CVBS SWITCH AV3 PB 9 12 FEG8 2 4 2E33 E5 FE68 C7 if pU 2 41 16 FE70 C13 1E97 gc ele zt amp yew 2 44 112 FE71 C13 AVEPB 20000 965 5558 B 4 9 22_ res 2 50 7 FE72 C13 F a sle lt De 8 a a 2 51 FE73 013 TN gt 45 e d 2E70 B7
170. 1 BOIC 1V2 PNX5100 B041 AUDIO L 4 1x AV2 BLK 4 1x CA MDO1 DDR2 CS 04 3x FE DATA1 BO6F 1 1 12 BO4A 1V2 PNX5100 B10 AUDIO L 1x AV2 BLK 2x CA MDO1 2x DDR2 DO 1 FE DATA2 BO6G 1x MM1 A12 05 1V2 PNX5100 BO1B AUDIO POWER BO4A 1x AV2 STATUS BON 1x CA MDO2 2x DDR2 D1 BOAN FE DATA2 BO6F 1 1 2 05 1V2 PNX5100 CLOCK B041 AUDIO POWER 1x AV2 STATUS 2x CA MDO2 B04G 2x DDR2 D10 FE DATA3 BO6G 1x MM1 A2 05 1V2 PNX5100 DDR PLL1 B04M AUDIO POWER BO4K 1x AV2 Y CVBS BOAN 1x CA MDO3 2x DDR2 D11 04 FE DATA3 BO6F 1 1 05 1V2 PNX5100 DLL B10 AUDIO POWER 1x 2 5 2 CA MDO3 2x DDR2 D12 1 FE DATA4 BO6G 1x 1 05 1V2 PNX5100 LVDS PLL B05H VDISP BO8B 1x AV2 Y CVBS BOAN 1x CA MDO4 2x DDR2 D13 04 FE DATA4 BO6F 1 1 4 05 1V2 PNX5100 TRI PLL1 B06D VDISP BO4K 1x AV3 PB 2x CA MDO4 2x DDR2 D14 FE DATAS BO6G 1 1 4 05 1V2 PNX5100 TRI PLL2 BOSE VDISP1 1x AV3 PB BOAN 1x CA MDO5 2x DDR2 D15 04 FE DATAS BO6F 1 1 5 05 1V2 PNX5100 TRI PLL3 BOSH VDISP1 BO4K 1x AV3 PR 2x CA MDO5 2x DDR2 D16 8028 1 FE DATA6 BO6G 1x MM1 A5 1 1V
171. 10 9FNO 04 9FN6 4 9FN9 07 9FNC E7 FF19 B1 IFN1A4 IFN4 B9 IFN7 B11 IFNA B15 IFND E11 IFNH D3 IFNL D4 1V2 PLL 2V5 PLL 1V2 PLL 2V5 PLL 7FNO 1 EP3C40F324C7N Mi TFNO 2 TFNO 3 C VGCD EP3C40F324C7N 2 EP3C40F324C7N 7FNO 4 A A BANK1 VGCD EP3C40F324C7N BANK2 BANK3 jd N2 L 09 u TXF2C BANKA ni E 1 TXF1B 5 FNO 10_B2 L1P CLI2JCLK 1 IO L1IL22N 7 iA ToS CLK15 CLK_6P 02 9 2 ing ia MEC eukticuk IO BI LIN m 10_LajL33P 18 IO 1 55 IO SENT 1 18 m IO C1 LN CLK3 CLK_1N aes CLK14 CLK_6N IO R8j21P 55 D ia e 10 C3 LAP RESET 18 gt IO TB B2IN gt i13 CLKI2ICLK 7N IO U1S B35P vis Le 5 n s Hy coNrie 10 Mg IO L6IVREFB2NO IO p 5 TPI p PBIVREFB3NO IO PoJB23N 016 VI5 B35N 25 gt TX852B D 3V3 FPGA jok FAB nstaTus A 1 D2ILBP 9 10 2 IO P2ILA4P _P7IVREFBSN1 10_u6 B24P ve 5 GE 119 10_UisIvREFBANt IO RTIB3EN Be c GP STATUS IO D ILENIDATATJASDO P 75 RS RIIVREFB2N2 IO PAILAANL t FID 18 IO vezan e o
172. 10 LO2N VREF 2 5 68 9 ly 3F03 H10 FF40 E14 SML 310 3F25 DONE GF84 LTST C190KGKT 70 10_LO6N RHCLK7 LO3P LHCLKO 10 FF43 LN NN Le DONE 1 10_L07P LOSN LHCLK1 3 0618 FF41E14__ 7 00 IO LO7N 10 LO4P LHCLK2 3F21 FF23 3F07 011 FF42 E14 5 LTST C190KGKT 12 RSS ee IO LOANILHCLK3 I 15 gF05 4 gt 3F08 011 FF43 E14 5 8 Y 3275 IPIVREF essa L 1 TXDAT als NE 9 011 FF44 E14 5 17 9F05 2 777 oo le 10 11 FF54 F6 FOR 9 5 LOGPILHCLKG FEM d _____73 T 18 9F05 1 ___ YET e 11 D7 FFA7 A1 986 1 3 i 1 emo Mb F 2 5 10 LOIN t t 3F29 3F13 C10 FFAS A1 gt TXCLK BL CS AAA BONE 51 __ iF01 9855 2 502382 1470_L 3F14 F7 IFOO 8 8 BRETT gis 3 15 1 64 F10 PROG B 1 4 2V5M 4 5 PROG_B 4 l 5 3F15 2G4 2010 s 44 vsM 3F15 3 G5 IF07 C10 FF G E I 3F16 1 H4 IF08D9 76 m BLVS 3F16 2 H4 IF09 C10 J 75 ior _ 3F16 3H4 IF12B3 GND 218 3F16 4 5 C10 Em 17 013 IF14 07 eval TEES 3F18D13 IF15 010 IF16 D10 le Caes abe 1 BL HS 3F20
173. 100 9FND 3 z 7FNO 6 E RES 7FNO 8 VCCD PLA VOCA EP3C40F324C7N i i EP3C40F324C7N 5 _ 12 3V3 FPGA BANK6 BANK7 BANK8 G queue 7 loikecuk 10_L16 R33P IFNG paz B10 MM1 D4 c5 1 Wig IO MIT RS9N asia m e7 2 10_B18 R4N PADD20 818 CLK9 CLK 10 B 4 T36P PADDG 818 lt 1 04_ E eonek 10_C5T11PIDATAS ES lt w MM1 D9_ L14 R36P g Des 8 5100 10_C17 RSP PADD21 C17 10_A14 T36N PADDs MMT D3 IO BSITTGPIDATA13 29 lt __MM1 A9_ 115 5 851 Yid CLI OUT PNX5100 SFNS F18 C18 SFNS A10 Y 1 5 A9 F A5 MM1 DQst D 10_L15 R36N 7 Ar CLKS CLK_2N IO CT8IRSN PADD22 RES CLKB CLK 5N 10 B1S T37P PADD4 819 1 _ 2 CLKIOJCLK_4N 10_ 16 14 Eo s MM1 DAS1 D TX8518 US 10_L18 VREFBSNO L13JR38P 1 TXB51D 10 G14JR7N PADD23 G14 amp amp oa 10_A15 T38N PADD3 A S lt p MM1 D5 7 SIR REI IO B6 TABPIDATA15 pe 35 7_ Fig O NIGIVREFBSN1 IO MI4 RSBN pr lt CONF DONE IO H1S VREF FPGA1 O15 IO ATTIVREFBTNO IO BITA1P PADD2 nte A VREF FPGA1 p c7 0_E9IVREFBENO IO AGITIBNIPADD19 57 Rig lO RI7IVREFBSN2 10_P17
174. 1001B S E Gb gcc CN 858 nid DP L 51001 gt 1 DN RX51001CLK E 8 8 589 RX51001CLK RX51001C 5 e RX51001C TN 1 RX51001D 21 52 e RX51001D S RX51001E S lt 88 8 51001 i 6 7 8 CHN SETNAME CLASS NO 2008 10 10 VIDEO PNX5100 TV543 R2 LDIPNX 8204 000 8928 2008 11 21 NAME Maelegheer Ingrid SUPERS 9 CHECK DATE ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310 519 090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA HIH SSB PNX5100 Power 25 8 9 10 11 12 43 1 2 3 4 5 6 7 8 9 2C45 D1 5 62 6 2C55 D1 5C63 6 2 56 D1 5 64 6 2 57 D9 5C65 F6 PNX5100 POWER 2 59 1 5 67 E8 2C60 1 B1 5C68 E8 7C00 11 2 60 2 1 5 69 8 T PNXS100E SUPPLY_2 2C60 3 B1 5C70 F8 A 3V3 PNX5100 LVDS IN 18_ ava LvpsIN VD
175. 110 F4 4 7116 1 B11 n 1X03 REF EMC HOLE CHN SETNAME 8 i CLASS NO P 2008 08 08 2 2K9 3 NAME Peter Van Hove SUPERS 3 2008 06 02 ROYAL PHILIPS ELECTRONICS 2008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310 630 090306 5 090306 2009 08 All rights reserved Reproduction in whole or in parts 10 LED Low Pow Microcontroller Block Liteon PHILIPS is prohibited without the written consent of the copyright owner 2 Circuit Diagrams and PWB Layouts Q549 2E LA EN 81 3 4 12 14 15 16 19 20 10 11 12 2201 8 2202 C8 2 MICROCONTROLLER BLOCK LITEON INPUT BUFFER 19208 RES 3V3 3 3 yev ATE PWM CDLOCK 3219 2 lt e lt 8 PWM CLOCK BUF 5 gt 5 8 ace ale EN 1008 xs 7212 8 8 ATS 7209 PDTGIAEM SPI CS Ass SPL DATA N 7 9209 _ M PDTC144EU L L 33 I 5 2 SPL DATA RETURN _9210_ i 6 64K 7201 4 74 125 W 3V3 8 8 i lt 5 320
176. 12 13 1 2 3 4 5 6 7 8 9 1 0 2N30 D3 2N31 B5 2N32 D5 2N3383 BUFFERING 7 2P19 E9 2P20 D7 2P21C8 A A 2P22 C8 2P25 D8 2 26 9 2 61 C7 2P62 C8 B 3N30 D1 3N31 B4 3N32 D4 3N33E4 3N34 D2 3P46 C7 B B 3P49 D6 3P50 D8 3P51 D8 3 52 8 5 m 3P54 E8 t 5 10 9 28 741 245 7 10 02 58 TT 7N11 B5 5 gt CA ADDEN 5V5 TUN 7412 05 2 PCMCIA D1 3 17 z PCI AD25 228 D PCMGCIA D3 25 4 16 25 PCI AD27 PCLAD7 2 7 11 D9 D ge PCMCIA DA 5 15 PCI AD28 7P13 07 58 PCMCIA D5 6 14 PCI AD29 PCI AD6 _ 3 a 5 PCMCIA D6 7 13 PCI AD30 PCLADS lt 4 pla 899 gig dle die Bt 3 PCMCIA D7 8 12 PCI AD31 PCI AD4 5 Y NTT PCMCIA DO 9 11 PCLAD24 gt 6 PCMCIA A3 amp amp 8 2 lt PCLAD2 lt 7 4 PCMCIA A2 IN21 D4 5 CADIS 8 lt PCMCIA A1 T IN22 D2 i PCIADO gt
177. 14 090302 eps 090302 rights reserved Reproduction in whole or in parts SSB PNX8543 Video Streams Circuit Diagrams and PWB Layouts Q549 2E LA 2 3 AN 9 10 12 13 14 15 16 17 18 19 20 PHILIPS is prohibited without the written consent of the copyright owner 1 2 3 FE ERR 04 9 064 5 5 TSO BIT ERR 7H00 12 PNX85439EH M2 24182 FE CLK TSO BIT CLK FE VALID 5 TSO BIT VALID CA MDOO 33 TUN_CA a FE SOP 5 TSO SYNC CA MDO1 C32 1 FE DATAO 5 TSINO DATAO CA MDO2 B32 2 FE DATA1 5 TSINO DATA1 CA MDO3 130 3 FE DATA2 5 TSINO DATA2 CA MDO4 K34 CA CA FE DATA3 2 TSINO DATA3 CA MDOS 5 5 FE DATA4 5 TSINO DATA4 CA MDOG H30 6 6 5 TSINO DATAS CA MDO7 433 7 MEE DATAG gt TSINO DATAG FE DATA7 TSINO DATAT CA MOSTRT gt E34 MOSTRT MISTRT SCL BOLT ON I2C SCL CA MOVAL 034 cA CA MAL SDA BOLT ON 3HB2 12C SDA 100R CA MOCLK VS2 gt tahi Hit BOLT ON IO R
178. 18 C1 IEAGC L 5 8 E TUN P9 2 ITO9 B5 5 ITOD B7 G IF 1721 IS USED THEN 2T23 2T25 3T14 3115 9113 9T11 9T21 ARE ALSO STUFFED G mex H 2 l 1111 B7 1112 B7 E K IT13 B7 K 85 IT14 E5 559 IT15 F5 35 _ IT16 B9 REAC 9 1717 B11 IT19 C10 8 IT20 C11 1721 C12 L H T2013 L C11 1124 C12 IT25 1726 010 IT28 D7 mem IT30D9 IT32 011 IT34 F11 M IT36 611 M CHN SETNAME CLASS NO 2008 11 21 2008 10 10 Randal Keyzer SUPERS 3 CHECK DATE 2008 06 03 ROYAL PHILIPS ELECTRONICS N V 2008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310 503 090302 5 090302 2009 08 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS O Circuit Diagrams and PWB Layouts Q549 2E LA 10 GEJ SSB Demodulator 2 3 4 10 12 13 14 15 16 17 19 20
179. 1x SDA SSB BO6D 1x BO6D 1x TXF2D PCI AD11 BO7H 1x PCI AD4 7 1x PCMCIA A6 2x RESET mPCI BO4A 3x SDA UP MIPS 1x 851 1x TXF2D BO5G 1 PCI AD11 BO9A 1x PCI AD4 BO7H 1x PCMCIA AG 4 3x RESET NVM 3x SDA UP MIPS B040 TX851B BO6D 1x TXF2D BO7G PCI AD11 1x PCI ADS PCMCIA A7 2x RESET PNX5100 2x SDM BO6D 1x TX851B BO6G 1x TXF2D BO7H 1x PCI AD11 8056 1x PCI ADS BO7H 1x PCMCIA A7 BOSF 1x RESET PNX5100 BO4B 1x SDM BO6G 1x 851 BO6D 1x TXF2E 2x PCI AD11 B07G 1x PCI AD5 1x PCMCIA A8 4 2x RESET STBY BO4P 2x SENSE 1V2 PNX85XX B040 1x TX851B BO6G 1x TXF2E BO4F 1x PCI AD12 BO7H 1x PCI ADS BO7H 1x PCMCIA A8 2 1x RESET SYSTEM BOAL 1x SPDIF IN1 BO6D 1x 851 BO6D 1x TXF2E 5 1 PCI AD12 BO9A 1x PCI ADS 1 PCMCIA A9 4 2x RESET SYSTEM BO8D 1 SPDIF IN1 2x 851 BO6G 1x 2 BO7G 1x PCI AD12 1x PCI AD6 BO7H 1x PCMCIA A9 4 1 RESET SYSTEM BOAL 1x SPDIF OUT B040 TX851C 2x UART SWITCH 7 1x PCI AD12 8056 1x PCI AD6 1x PCMCIA DO 1 RESET SYSTEM BO8B 1 SPDIF OUT BO6D 1x TX851C BOBD 2x UART SWITCH 2x PCI AD12 BO7G 1x PCI AD6 BO7H 1x PCMCIA DO 2 4x RF AGC 4 2x
180. 2 24182 LVDS IREF_LVDS VV 4 VDDA LVDS 12 1 LL ANI x TX851A 85439 2 24182 gt 5 lt lt lt lt lt lt lt lt lt lt lt lt 2 18 G TX851A MA AK18 gt 851 gm AL18 851 C4 m AN19 IX851C B AP19 TX851C gt 8 R5 AN20 Ss TX851D 58 24 ws D p 20 lt TX851D 2 F11 2 12 120 ET TX851E E p 20 S TX851E 28 F14 7 5 F15 AL19 TX851CLK 55 D famo TX851CLK D 85 EE 1 AL12 85 22 852 88 15 LOUT2_A 22 2 852 o 9 4 5 5 nf 22 TX852B 85 2 p AL22 a TX852B 25 4 55 5 N AN23 x TX852C 2 AP23 lt TX852C E N AN24 TX852D LOUT2 0 24 TX852D lt 852 _ 10072 E p AM24 TX852E NLAL23 TX852CLK D LOUT2 CLK p AM23 lt TX852CLK 1 2 3 4 5 6 7 8 9 CHN SETNAME CLASS NO 2008 11 21 LVDS PNX8543 TV543 R2 LDIPNX 8204 000 8927 2008 10 10 NAME Maelegheer Ingrid SUPERS 16 DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS
181. 2 3 36 5 3 7 44 9 25 9 26 is mmm MAIN NVM 09 12 me FHC1 H13 FHC2 114 _ FHC3 C5 FHC6 H11 N 1X03 EMC HOLE CHN CLASS NO 2 2008 11 21 CLER 2008 10 10 3 STANDBY CONTROLLER PNX8543 TV543 R2 LDIPNX 8204 000 8927 NAME Randal De Keyzer SUPERS CHECK DATE 2007 11 29 5 130 1 ROYAL PHILIPS ELECTRONICS 2005 10 2009 May 08 12 13 14 15 16 17 18 19 20 a 18310 505 090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA 10 SSB PNX8543 Debug 1 A Personal Notes gt PHILIPS 1H11 C2 UJ 2H06 C3 2H07 D3 3HF3 A3 6HF0 7 2 00 2 FH01 D2 D3 IH93 C2 94 95 D2 O is prohibited without the written consent of the copyright owner m All rights reserved Reproduction in whole or in parts ET PNX8543 DEBUG 3V3 PER 3HF3 330R SML 310 2 PDTC114EU FHOO 1H93 2H06 RES C SPI PROG 5 TSTPOINT 100p FOR DEBUG g SPPROG gt 27 94 5 GND TSTPOINT FOR DEBUG G SEI 7 IH95
182. 2 5 3FFL C5 TX852CLK 9FG6 2 9FGC 2 RX51002CLK JIXF2CLK AR 2 s RX51002CLK 3FFP D5 e 1 2 7 2 77 GET 82 3FFT D5 4 526 ass RES 3FFW E5 L 028 aay S 2F80 467 4 2 1 2 TX852CLK y 9FG6 1 QFGC 1 RX51002CLK IXF2CLK NA 1 sa RX51002CLK Y RTI 1 8 1 8 8 RES s 2 81 4 7 50 51 TX852D J9FG7 4 9FGD4 RX51002D IXF2D Pe 1 I RX51002D els FI RE41S HF 3FG4 B2 H gt 1 477 427775 lt lt VS A 3FG5 C2 H 825 2 5 RES 1 258 58 2F82 4 7 266062 dod m RX51002D F 3FG8 D2 TX852D J9FG7 3 9FGD 3 RX51002D TXF2D _ d 1 F dm i X pr RES i TO DISPLAY 369 D2 3FFC 2 2F83 4 7 2 TX852E 1 _ 7 2_ 9FGD 2 RX51002E IXF2E 2 4 RX51002E 3FGB F2 diem 2 7 2 7 180R 7 eck 3FGC F2 025 RES 559 2F84 4 7 2 TX852E gt RX51002E 2 AUR RX51002E 3FH4 A8 d 7 0 7 3FH5 B8 5FG1 E8 SETNAME CLASS_NO 2008 11 21 2008 10 10 NAME Maelegheer Ingrid SUPERS 8 CHECK DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS N V 2007 5 6 7 8 9 10 11 12 13 18310 530 090303 5 090303 2009 08 All rights reserved Reproduction in whole orin parts Circuit Diagrams and PWB Layouts Q549 2E LA GHA SSB FPGA Power Control is prohibited without the written consent of the copyright owner
183. 2 B6 Bonos 8 37 6 14 UPC 8 6 22 12 8 i I 6E23 011 4 L _ 6E24 D6 j CHN SETNAME EMC HOLE CLASS NO 2 2008 11 21 ANA SIDE 8204 000 8930 TV543 R2 LDIPNX E 2008 10 10 3 Maelegheer Ingrid SUPERS 4 2008 01 18 ROYAL PHILIPS ELECTRONICS N V 2005 2 3 5 6 T 8 9 11 12 13 14 15 16 17 18 19 20 18310 542 090303 5 090303 Circuit Diagrams and PWB Layouts Q549 2E LA GEJ _ SSB Analogue Externals 1 2 4 0393 6 7 gS 16 17 18 19 20 1011 612 6E53 A5 1 2 3 4 5 6 7 8 9 10 n 7 B 14 1013 7E03 H9 1014 F11 7 06 1 113 1016 A4 7 06 2 113 ANALOGUE EXTERNALS B 5 3 3 3 dM 1235 63 7 10 2 F9
184. 2 D17 BO6D 3x RX51002D 2 6x TUN P3 BO6D 1x TX852D 7 1x 22 BO9A 1x PCI DEVSEL 2x PNX5100 DDR2 D18 1x RX51002E 2 5x TUN P4 1x TX852D 1x 22 2x PCI FRAME 2x PNX5100 DDR2 D19 BO6D 3x RX51002E BO2A 5x TUN P5 B040 1x TX852E BO4F 1x 23 BOSG 1 PCI FRAME 2x PNX5100 DDR2 D2 1x 51002 BO2A 5 TUN P6 BO6D 1x TX852E 8056 1 23 BO7G 1x PCI FRAME 2x PNX5100 DDR2 D20 BO6D 3x RX51002E BO2A 5x TUN P7 BO6G 1x 852 BO7G 2x PCI AD23 BO9A 1x PCI FRAME 2x PNX5100 DDR2 D21 8080 3x RXD BO2A 5x TUN P8 B040 1 TX852E BO7H 1x 23 BO4F 2x PCI GNT 2x PNX5100 DDR2 D22 BOE 2x RXD MIPS 2 6x TUN P9 BO6D 1x TX852E 1x 23 2x 2x PNX5100 DDR2 D23 BO8D RXD MIPS BO2A 2x TUN SCL 1x TX852E 2x 24 1x PCI GNT ETH 2x PNX5100 DDR2 D24 2x RXD MIPS2 2 2x TUN SCL BOSE 1x TXCLK 8056 1 24 BO7G 1x PCI GNT ETH 2x PNX5100 DDR2 D25 BO6B 1 RXD MIPS2 2 2x TUN SDA 1x TXCLK BO7F 24 1x PCI GNT MINI 2x PNX5100 DDR2 D26 4 2x RXD UP 2 2x TUN SDA BOSE 1x TXCLK BO7G 1 24 BO9A 1x PC
185. 2 H bridge positive output for left channel PGNDL 23 24 P Power ground for left channel H bridge VCLAMP 11 Internally generated voltage supply for bootstrap capacitors BSR 16 y o Bootstrap I O for right channel ROUT 15 Class D 1 2 H bridge negative output for right channel PGNDR 13 14 P Power ground for right channel H bridge PVCCR 10 12 P Power supply for right channel H bridge not connected to PVCCL or AVCC AGND 9 P Analog ground for digital analog cells in core AGND 8 P Analog ground for analog cells in core BYPASS 7 pei eed inputs Nominally equal to AVCC 8 Also controls start up time via AVCC 19 20 P High voltage analog power supply Not internally connected to PVCCR or PVCCL Thermal pad Die pad us be soldered down on all applications to properly 18440_302_090303 eps 090303 Figure 8 6 Internal block diagram and pin configuration 2009 May 08 9 Block Diagrams Wiring Diagram 32 Elite Core WIRING DIAGRAM 32 Block Diagrams Q549 2E LA 1 83 SCL SPLDATA IN SDA CONTROL 1 CONTROL 2 43V3 BLANK EEPROM CS 9 TEMP SENSOR 10 PROG 11 VLEDI 8316 12 GND 13 VLED2 14 GND AMBI LIGHT MODULE 5 5 1074 AL LCD DISPLAY 1004 8684 BACKLIGHT SP CLOCK BUF 1650 41 NC 40 TXDAT 39 TXDAT 2 SCL DISP 1 SDA DISP 1651
186. 2 PNX85XX BOSE VDISP2 1x AV3 PR BON 1x CA MDO6 2x DDR2 D17 BOAN BO6F 1x 1 6 1V2 PNX85XX BOSH VDISP2 BO4K 1x AV3 Y 2x CA MDO6 2x DDR2 D18 2 1x FE DATA7 BO6G 1x 1 6 BO4A 1V2 PNX85XX 9 V LM833 1x AV3 Y BOAN 1x CA MDO7 2x DDR2 D19 04 FE DATA7 BO6F 1 MM1 A7 4 1V2 PNX85XX 2 VTUN BO4K 1x 4 2 CA MDO7 2x DDR2 D2 04 4x FE ERR BO6G 1x MM1 A7 BO6A 1V2 PNX85XX Bo7D 1V8 HDMI 1x AV4 PB BOAN 1x CA MICLK 2x DDR2 D20 2 1x FE SOP BO6F 1 MM1 A8 1V2 PNX85XX 804 1x ADAC 1 BO8B 1x AV4 PB 1x CA MICLK 2x DDR2 D21 BOAN FE SOP BO6G 1 MM1 A8 B01A 1V2 STANDBY 8041 1x ADAC 1 BO4K 1x AV4 PR BOAN 1x CA MISTRT 2x DDR2 D22 2 1x FE VALID BO6F 1 1 9 01 1V2 STANDBY 804 1x ADAC 2 1x AV4 PR 1x CA MISTRT 2x DDR2 D23 04 FE VALID BO6G 1x 1 9 4 1V2 STANDBY BO4L 1x ADAC 2 BO8B 1x AV4 PR BOAN 1x CA MIVAL 2x DDR2 D24 BO4K 1x FRONT C BO6F 1 MM1 BAO 1V8 PNX5100 BO4L 1x ADAC 3 BO4K 2x AV4 Y 1x CA MIVAL 2x DDR2 D25 BO8C 2x FRONT C BO6G 1x MM1 BAO 05 1V8 PNX5100 BO4M 1x ADAC 3 1x AV4 Y BO4N 2x CA MOCLK_VS2 2x DDR2 D26 BO4K 1
187. 2 x Q529 x Q54x x T P Set is still Set is going into protection after operating replacing the SSB blinking LED error 2 Create repair directory on USB stick and Take care that speakers are connected connect USB stick to TV set In some sets the speakers are in the rear Go to SAM mode 062596 i and cover and when the set is switched on save the TV settings via Upload to USB without speakers it is possible that the Audio protection is triggered Replace SSB board by a Service SSB Advise remount rear cover before switching Make the SSB fit mechanically to the set on see also SCC_71772 Start up set Set behaviour y Set is starting but no display Set is starting up amp display is OK Set is starting up in Factory mode Update main software in this step by using autorun upg file v Press 5 5 the Volume minus button the local Program Display Option code via 062598 cntrl until the red LED switches off and then MENU HOME followed by 3 digits code this press 5 s the MENU button of the local code can be found on a sticker inside the set in some chassis this button is named SOURCE The picture noise is replaced by blue mute v Noisy picture with bands lines is visible and the red LED is continuous on sometimes also the letter F is visi
188. 20 1 01 5 ICG3 C2 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1C02 B5 ICG4 D4 A 2C03 H5 ICG5 D4 2C04 G4 ICG6 D5 2CG0 5 ICG7 E2 2061 85 IcG8 2 2062 C4 ICG9 E2 2063 C2 ICGA E2 BACKLIGHT OUT2 A 266208 2CG5F5 ICGK G13 B 2CG6 F5 ICGM G12 700 3 2CG7 F5 ICGN G11 5100 3V3 2CG8 F5 ICGP G11 2CGBH12 610 VDISP PNX5100 DISPLAY INTERFACING 1 01 cco BCG5 B vv lt gt VDISP2 30R 3 0A T 32V 8 100R 8 9 25 GPIO 2CGCH12 ICGVB8 2CGDG11 ICGW C3 2CH0 E11 ICGY B12 2CH1E12 ICGZB8 4 3C37 G3 ICH1 G9 BACKLIGHT BOOST 1 3 38 G3 2 G9 3 39 G3 ICH3 H9 CHA AF26 CTRL4 PNX5100 227 2 lt lt C26 088 26 B25 5 6 7 3CH1 40K RES BACKLIGHT PWM ANA SSB LCD PWR ON i 100R 7CG8 B26 PDTA114EU 26 A25 BOOST CTRL lt lt 224 3C42 G9 ICH4 FAN CTRL 1 1262 S B24 FAN CTRL 2 gt Mm A23 3C43 5 D10 BACKLIGHT CTRL s 825 ui 3C44 B8 ICH6 D11 ICGY 3CHO lt GPIO sme RES 5092 1 02 FCG1 BCG6 1008 e gt 4 m 30R 30A T 32V 3662 40K RES 5 VDISP1 2081 i FCG8 mE 1 CTRL3 PNX5100 3CG0 2 D5 ICH7 D11 CTRL2 PNX5100 B22 3CG0 3 05 ICH8 D12 CTRL1 PNX5100 C22 5 BOOST CTRL gt E 3CG0 4 ICH9 D13 D
189. 2009 May 08 14 E 549 2 Mechanical Instructions 18310 217 090318 090320 Figure 4 10 LCD Panel 1 18310 218 090318 eps 090319 Figure 4 11 LCD Panel 2 4 3 9 Wi Fi antenna Follow the instructions for LCD Panel until remove plastic rim After removal of this rim you gain access to the Wi Fi antennas 44 Set Re assembly To re assemble the whole set execute all processes in reverse order Notes While re assembling make sure that all cables are placed and connected in their original position e special attention not to damage the EMC foams in the set Ensure that EMC foams are mounted correctly 2009 May 08 5 1 5 2 5 2 1 Service Modes Error Codes and Fault Finding Q549 2E LA 5 Service Modes Error Codes and Fault Finding Index of this chapter 5 1 Test Points 5 2 Service Modes 5 3 Stepwise Start up 5 4 Service Tools 5 5 Error Codes 5 6 The Blinking LED Procedure 5 7 Protections 5 8 Fault Finding and Repair Tips 5 9 Software Upgrading Test Points As most signals are digital it will be difficult to measure waveforms with a standard oscilloscope However several key ICs are capable of generating test patterns which can be controlled via ComPair In this way it is possible to determine which part is defective Perform measurements under the following conditions Service Default Mode e Video Colour
190. 204 000 8857 SUPERS CHECK DATE 2 10 NY 2009 May 08 12 13 14 145 16 17 18 19 20 18310 611 090305 eps 090410 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS D 6 LED Low Pow LED Liteon 2 Circuit Diagrams and PWB Layouts Q549 2E LA 10 3 i 14 15 1 17 18 19 20 1 1 13 VLEDi F VLED2 D 9301 LED LITEON 7000 LTW ESOOT PH1 7001 LTW E500T PH1 GREEN GREEN y 7002 LTW E500T PH1 GREEN gt VLEDi F VLED2 2 93092 7 7004 LTW ESOOT PH1 1 12 GREEN y 3 3 93033 6 9313 1 8 mi 2 m RED wt RED RED RED GREEN yj 3341 3336 gt BUE y gt gt 5 93184 4 gt 5 GND_HS BLUE y GND_HS 3340 1 5 3344 3908 5608 1 5 3339 3346 3908 3342 560H E 3349 5608 3353 1 5 3384 1 5 3385 1 5 3387 1K5 3388 3389 3390 1K5 3391 1 5 390R L3 VLED1 F BLUE yj GND_HS F307 F302 4 i 8 306 1 9320 1 8 9320
191. 23 Wig IO HISIVREFBONt 10 618 27 DONE 618 oe VV E 12__ 11 29 11 IO DI4IPLL2 CLKOUTP IFND AS i 3 IO ETITSNIDATAO 10 CLKOUTP MM1 CLK 2 i CON20 _ 18 6 2 Hi7 R28P 17 lt MIDI Ars IO BI2IT31P PADD10 C 4 PLL2 CLKOUTN MM SG A4 lO PAITSPIDATAB 10 _AtJPLL3_CLKOUTN MM1 CLK 10_J13 VREFB6N3 NCBI Sig ATZIT3NIPADDO ee a 25 0 7 Lt anes Ara 10 gt 10_E8 T8P DATAG E L 1 _ 1 35 7 i 7FNO 9 EP3C40F324C7N 7FNO 10 EP3CAOF324C7N VCC GND 3V3 FPGA HIV2 FPGA pe IO S4 q 3V3 FPGA J F HIV2 FPGA pe 2 L3 F IV2 FPGA pe 86 IV2 FPGA pe Ke 2N amp out FPGA ge 0 cine vccioz M av sour FPGA 1V2 FPGA gt 6 GND GND 1V2 FPGA Eo Bi 52 _ _ _ T V2 FPGA ge e vccios ooo atin ge veo UR 42 FPGA ge oo Ko tin FPGA HV2 EPGA 2vsin pca GND GND G 1V2 FPGA Be 1 vccios a 2V5in FPGA ___ ORS IV2 FPGA HIV2 FPGA pe 2 Ee L 1V2 FPGA ge vecios S18 GND GND 1V2 FPGA i
192. 25 08 06 19 08 08 06 08 09 18 08 10 23 NAME Peter Van Hove SUPERS CHECK DATE 08 06 06 ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310_600_090305 eps 090305 Circuit Diagrams and PWB Layouts Q549 2E LA LI Interface Ambilight Dual DC DC 1 2 3 4 5 6 11 12 13 gt DUAL DC DC PHILIPS UJ 100u 35V 2201 320 1200 VSW 688 xx 7 3202 5 0 7200 TPSS4283PWP PVDDT BOOT 1 VLED2 16V lt wes 100u 35V 2207 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PVDD2 BOOT2 sw2 EN2 FB2 100u 35V VLED1 12 AN RES 3206 2218 RES RES 2221 aL G 7200 TPS54383 in case of 16V or dual dc dc converter The components marked with one star belong to the 12V versions 3104 328 58351 3104 328 58371 The components marked with two stars belong to the 16V versions 3104 328 58331 3104 328 58341 3104 328 58361 3104 328 58371 220u 25V AN 3K3 3209 RES 5 2222 RES 2200 4 2201 4 2202 5
193. 27 3V3 PER 9HF7 6 PCI AD17 D24 47 REQ 230 PCI REQ PCI REQ 9HG3 C3 PCI AD18 C24 8 cnr 230 PCI GNT PCI GNT PCI REQ MINI 1H30 B4 PCLAD19 B24 id ot ANB SHES 3 3 PCI AD20 A24 19 1 D PCI REQ B PCI REQ B 4K7 YY 0 E2 20 REQ_B lt lt PCI AD21 E23 121 ont B 29 5 PCI GNT B PCI GNT B _ 5_ PCI GNT MINI IHF1 C3 PCI AD22 D23 7 4 5 3HES 4 22 IHS7 29 3V3 PER 2 23 C23 28 HOS 54 PCI CLK OUT 523 123 PLL_OUT gt D3 PCI AD24 24 IHF5 E2 PCI AD25 A23 A20 P XIO ACK E22 25 819 lt lt IHS7 C3 26 26 AD25 PCI AD27 D22 27 28 22 28 0 20 A gt gt __ XIO SEL NAND PCI AD29 B22 29 1 C20 IHF1 100R PCI AD30 22 127 XIO_SEL 520 PCI AD31 E21 E20 IHF3 31 1 RESERVED 3V3 PER 2HF5 10n D 2HF6 1 23055 1900 VDD 3HFG gt AAA 5 PC CLK ETHERNET ZERO IHFO 3HFH PCI CLK PNX5100 3HFR Uy 5 PCI CLK PNX8535 SES PCI CLK MINI gt VN REF CLK DELAY BUFFER 2 TODS sez PCI CLK PNX8535 3 PCI CLK ETHERNET 4 5100 CHN SETNAME CLASS_NO CONTROL 8204 000 8927 2
194. 2HHA H7 NC 2 1 2 11 2 2 N N34 M RASB 820R 100n 2HHK E6 N33 _ 2 vrer 832 1 ae 2HHM E6 2 11 N DDR2 DQS3_N Ju wes E22 y 2HHP E12 DDR2 DQS3 P N32 p pass DDR2 ODT 3HGP F7 F7 DDR2 RAS 3HGS 3HGT G7 5 D 3HGU G8 3HGV G7 3HGW G8 a 3HGY G7 1V8 PNX85XX 3HGZ G8 1V8 PNX85XX G7 3HH1 G8 gt gt 3HH2 G7 Zd 3HH3 G8 amp 3HH4 G7 8 3HH5 GB el L 3HH6 G7 7 7 H3 3HH8 H4 m gt 3155159153155153153155153165 9185618581581581581551531 51531551531561585515515315515 8158155155155 569 55 4 gles 4 9 898 8 8 8 8 8 8 8 8 9 8 829 8 8 8 8 89 8 Q 892 892 89 89 892 89 89 89 8 89 89 89 89 8rf 8 2 8 Eg EN aAlralral ral ral FN rn trate F13 3HHC F13 xa mns s 3585885858 zals 2585885858 3HHD G14 E en 13 VOD a DDR2 ODT DDR2 ODT K9 lopr G13 DDR2 CKE 2 DDR2 CKE 5 Joke 3HHG G13 DDR2
195. 3 F1 3374 G1 3384 E1 3385 F1 3386 F1 3387 F1 3388 F1 3389 F1 3390 G1 3391 G1 7000 C2 7001 C3 7002 C4 7003 C6 7004 C8 7005 C11 7305 G4 7306 5 7307 7315 69 7316 H10 7317 F9 9301 C1 9302 C1 9303 1 C10 9303 3 C10 9303 4 C10 9304 1 E10 9304 2 E10 9304 4 E10 9305 1 C6 9305 2 C6 9305 4 C6 9306 1 05 9306 3 D5 9306 4 05 9307 6 9308 9309 1 B6 9309 2 B6 9309 4 B6 9310 1 B8 9310 2 B8 9310 4 B8 9311 1 H13 9311 3 H13 9311 4 H12 9312 1 B10 9312 3 B10 9312 4 B10 9313 1 B12 9313 2 B12 9313 4 B12 9314 G5 9315 1 C12 9315 2 C12 9315 4 C12 9316 H5 9317 F5 9318 1 9318 3 C8 9318 4 C8 9319 1 D9 9319 3 D9 9319 4 D9 9320 1 D7 9320 2 D7 9320 4 D7 9325 F10 9326 G10 9327 H10 F302 G5 F303 G4 F304 H5 F305 5 F307 F5 F308 F4 F325 F10 F326 F9 F327 G10 F328 G9 F329 H10 F330 H10 F340 D1 F341 01 F342 D1 F343 D2 F344 012 F345 D12 F346 D13 F347 G12 F348 G13 F349 G13 CHN SETNAME CLASS NO 2008 08 08 2 3 DRIVER 6LED LITEON 2 9 8204 000 8857 2008 06 10 2008 08 08 Peter Van Hove SUPERS CHECK DATE 2008 06 02 130 3 ROYAL PHILIPS ELECTRONICS N V 2008 04 2009 08 11 12 13 14 15 16 17 18 19 20 18310 652 090508 eps 090508 1 2 Circuit Diagrams and PWB Layouts Q549 2E LA ES 8 LED Low Pow LED Drive Liteon 3 4 v dl
196. 3 PER 100R FH12 2 V SDASEL MSDASET x gt o FU 100R AKT 3H09 C6 3H11 C1 3H33 C6 3H37 D4 3H38 D5 3H45 D4 3H49 E4 3H50 E4 3HF9 A3 3HFY C1 3HP2 C4 3HP3 1 B 3HP4 B1 3HP6 B1 3HP8 C1 3HPA C1 3HPB C1 3HPC C1 3HPD E2 3HPE E2 3HPF E2 3HPG E2 3HPH E2 3HPJ F2 3HPK E4 3HPL C1 3HPM F4 3HPP D1 3HPR D1 3HPS F2 3HPT F4 3HPU F2 3HPV F4 3HPW B3 7H00 8 9H17 D3 FH03 C5 04 4 05 4 11 4 12 4 12 C1 IHF4 B3 6 1 8 1 9 1 F IHS8 C1 CHN SETNAME CLASS_NO 2008 10 10 MIPS I2C 8 EJTAG PNX8543 TV543 R2 LDIPNX 8204 000 8927 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS N V 2005 2009 May 08 8 9 10 11 12 13 18310 507 090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA LI SSB PNX8543 Control All rights reserved Reproduction in whole or in parts 2 3 4 5 6 10 11 12 13 gt PHILIPS UJ is prohibited without the written consent of the copyright owner AN
197. 302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA LIN SSB PNX8543 Digital Video In i 1 2 4 8 4 5 6 8 9 10 11 12 13 3HKO B2 7 00 4 9HKO 02 a IHSM B2 01 C2 4 2 2 8543 DIGITAL VIDEO IN THO3 C2 d 04 C2 TH05 C2 06 2 THO7 D2 B THO8 D2 THOS B2 TH10 B2 7H00 4 PNX85439EH M2 24182 TH11 B2 TH12 B2 DDCA SCL TH13 B2 DDCA SDA lt SDA TH14 C2 TH15 C2 DDC SCL DDC SDA 74 TH16 C2 C RREF PNX85XX em HDMI_RREF 4 12K HDMIA RX0 THO9 e B E 8 e e y HDML A _ ss 25 HDMIA RX1 VQ THIt HDMIA RX1 5 e HDMIA RX2 TH13 5 D DMARD gt HDMI_RX2_A DV_UVIN D 5 E 2 HDMIA RKXC 15 e 8 HDMIA RXC S e HDMI RXC A 3 B HDMIB RXO THO1 HDMIB RXO a e HDMI_RX0_B o 2 HDMIB RXi e 2 5 5 HDMIB RX1 HDMI RX1 B E zi HDMIB RX2 THOS e HDMIB RX2 e RX2 B gt THO7 e 4 HDMIB RXC gt e HDMI RXC B HOT PLUG A lt lt HOT_PLUG_A N HOT PLUG 2 HOT_PLUG_B WA CHN SETNAME p CLASS_NO 2008 11 21 VIDEO IN PNX8543 TV543 R2 LDIPNX 8204 000 8927 2008 10 10 NA
198. 326 8 1 x x 7317 BC847BW VLED1 F F302 Place jumper 9314 9316 9317 if VLED 17V 3325 3328 F303 4 PWM R1 9314 5 PWM R2 VLED1 F 5 5 3305 F328 T F304 3333 F305 1 1 9316 _ PWM G1 PWM G2 LEDI F a F327 RED 2 9826 _ F329 GREEN 2 3308 nd 38 l 9327 A 3908 9325 9326 9327 if VLED 17V 1 5 3314 1 5 3315 1 5 3316 1 5 3317 3318 1k5 3319 1 5 3320 3321 3368 3323 era F348 F349 8 4 93114 5 9911 3 6 EIS 1 3104 313 6314 3 10 11 12 13 3301 F9 3302 F9 3303 F9 3304 G9 3305 69 3306 H9 3307 H9 3308 H9 3309 19 3310 D12 3311 012 3312 12 3313 E12 3314 E12 3315 12 3316 12 3317 F12 3318 12 3319 F12 3320 F12 3321 G12 3322 G12 3323 G12 3325 G4 3326 4 3327 H4 3328 G4 3330 4 3331 F4 3332 F4 3333 H4 3334 F4 3335 D12 3336 D2 3337 D2 3338 D1 3339 D2 3340 D1 3341 D1 3342 2 3343 D1 3344 D1 3345 012 3346 1 3347 D1 3348 12 3349 1 3350 1 3351 12 3352 1 3353 E1 3354 D13 3355 E1 3356 E1 3357 D13 3358 E13 3359 E13 3360 E13 3361 E13 3362 E13 3363 F13 3364 F13 3365 F13 3366 F13 3367 G13 3368 G13 3369 F1 3370 F1 3371 F1 3372 F1 337
199. 3FL4 C4 3FLBCA 3FL6 C4 3FL7 C4 3FL8 C4 3FL9 C4 C E 3FLB C4 3FLC C4 3FLD C4 3FLEC4 N 3FLF C4 3FLG D4 WA 3FLH D4 3FLJ D1 aikee F 3FLL B6 D 3FLM B9 3FLN B9 5FLOC7 5FL1 C7 7FLO B2 FFLO B8 FFL1 B7 IFL1 C7 G 2V5 DDR1 2V5 DDR1 2V5 DDR1 2V5 DDR1 7FLO EDD1216AJTA 5B E 1 29 30 e gt gt VREF DDR1 T gt VREF FPGA1 SDRAM NC NC NC All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright p gt 2V5 DDR1 2FLJ 100n 2FLK 100n 2FLL 100n 2FLM 100n 2FLN 100n 2V5 p Q T N 22u 16V 330u 6 3V SFLG 228 2 CHN SETNAME CLASS_NO 2008 11 21 FPGA WOW DDR TV543 R2 LDIPNX 8204 000 8933 2008 10 10 Maelegheer Ingrid SUPERS 8 CHECK DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS N V 2007 1 2 3 4 5 6 7 8 9 10 11 12 13 18310_532_090303 eps 090303 2009 May 08 All rights res
200. 3V3E Boy di 3V3 45V TUN 45V TUN Bota T gt gt afd 5155 I TUN T SEM 5 4V3 PER B04a bof 5HV8 RREF PNX85xx ae eee gt Bosh i e TEMPERATURE amp FAN CONTROL VDDA LVDS B040 43V3 3V3 VDDA AUDIO VDDA AUDIO Bota up ds 412V 412V gt 12 12V SHY4 VDDA DAC gt 5HY7 AUDIO ADC L Eaa FPGA WOW LVDS IN OUT Bota i TIT PNX5100 SDRAM Bosh ere agi 5FG1 PNX8543 STANDBY CONTROLLER 3 20 PNX5100 DDR2 VREF CTRL 1 1V2 PNX85XX 1V2 PNX85XX 322 PNX5100 DDR2 VREF DDR 1 1 2 100 1V2 PNX5100 FPGA WOW POWER amp CONTROL z L 3V3 STANDBY 8V8 STANDBY 1V2 PNXBEXX 1V2 BNXB5XX 5100 VIDEO IN CFHO 1V2 FPGA Tum jet abis E 5FHO 1V2 PLL x 1V8 PNX85XX 1V8 PNX85XX B09b gt Bos 1V8 PNX5100 POW Bote Te PNX5100 POWER BUS 225 PNX8543 DEBUG 809 MUR Fd 5FH2 2V50ut FPGA Boi 1V2 PNX5100 1V2PNX5100 PR TRUE 1 3V3 PER 3V3 PER gt 5060 1V2 PNX5100 CLOCK 2V5 PLL 5061 1V2 PNX5100 TRI PLL1 gt i pue 5062 1V2 PNX5100 TRLPLL2 gt Bota T T T2 PNX8543 CONTROL SNA 5063 1V2 PNX5100 TRI PLL3
201. 4 9306 7932 79320 79320 4 BLUE gt 1 GND HS 8 1 9319 1 4 9894 5 93193 6 GREEN6 9 lo 8 is 19 gt 1 1 981 ers F345 F346 G RED 1 GREEN t BLUE 1 3335 3310 3354 390R 3345 3311 560R 3357 RED6 3908 71 5 8312 5eoR BLUEG 3908 3351 3313 3359 PWM B2 VLED1 F 3302 x 1 F326 3303 7317 BC847BW Place jumper 9314 9316 9317 if VLED 17V _9314_ PWM R2 VLED1 F H gt 1 3305 F328 __ RED 2 7315 i BC847BW F304 e _9316_ PWM G2 LEDi F i 825 8 8 3308 1 2 825 l 7316 F330 F329 GREEN 2 BC847BW 9327 Place jumper 9325 9326 9327 if VLED 17V 3908 1 5 F347 1K5 3314 1 5 3315 ks 3316 1 5 3317 1K5 3318 3319 1 5 3320 71 5 3321 1 5 3322 TKS 3323 560R F348 F349 4 9311 4 5 GREEN 2 RED 2 BLUE 2 BUE 3304 69 3305 69 3306 9 3307 H9 3308 H9 3309 19 3310 012 3311 D12 3312 E12 3313 E12 3314 E12 3315 E12 3316 E12 3317 F12 3318 F12 3319 F12 3320 F12 3321 G12 3322 G12 883612 3825 G4 3326 H4 3327 H4 3328 G4 3330 4 3331 F4 3332 F4 3333 3334 F4 333
202. 4 N 7 12 gt 3 m 4 3V3 11 18220 SPI CLOCK BUF F203 W Mm95010 WDW6 ia 3209 13 7210 GND Ale RES ele 4 8 8 8 PDTC144EU g 4 3 9211 got eS 8 BN EEPROM CS LOCAL 1 8 58 x SPI CLOCK BUE Sie 43V3 1 3 3223 BLANK BUF ale EN 100R ole 5 8 ATE SL 2 _9213_ B 8214 RES SPL DATA OUT FIL 7 201 Wtsv3 74 125 3121 SPI DATA RETUBN A 8 F208 3212 m 100R e AA DATA RETURN SWITCH 1008 3 3 2216 2215 10 100 7215 Ticse4gPWP 8 LED DRIVER PWM CONTROL F210 7 PWM R1 PWM CLOCK BUF 25 ra BLANK BUF 10 PWM G1 Pe 2 BLANK F212 PWM B1 5 PROG EL 6 a8 cs F204 7 e PWM R2 RES 3218 RE 27 mer our aE 49 8 3215 7 16 F214 SPI LATCH 1 2 417 e PWM G2 SPI CLOCK BUF 4 UE rus PWM B2 559 sg gt SCLK 12 e SPI DATA IN 5 JSN 120 7 ro 827 9855 SPLDATA QUT 3216 a 24 Sour 3 EEPROM CS LOCAL J EEPROM CS LOCAL SPI DATA OUT FIL 1008 18 22 2 DATA RETURN SWITCH DATA RETURN SWITCH 3214 33 3 AA 26 xERR 28 Us GND HS ex qc 5 8 Ses 8 8 a ES 9 l5 SUL 5 3 3 2203 08 2209 2 2210 06 221116 2214 A6 2215 F7 2216 F7 2217 12 2218 12 2219 012 2220 9 312109 3203 5 3204 B7
203. 427 e BER T A CSRS ES C 7201 8 seal O bo 370145 TH N 355 _ 33414335 8 m N ete E 888 N N 3141 N N n N 1 8 D Nf G a Ende 7214 a 2 x 812115 EIN 8 EIE ar 5 ng e 28 at E 3 04 ZRKG Z OH 6229 es EE 3 5 Su 51 w S 815 5 i amp 8 8 124 E 1126 3104 313 6313 3 18310 551 090309 090309 2009 08 Circuit Diagrams and PWB Layouts Q549 2E LA 10 8 LED Low Pow Microcontroller Block Liteon 1 2 3 4 5 6 7 8 9 10 2 11 12 13 14 15 16 17 18 19 20
204. 470R 3FH1 470R 3FH2 470R 3FH3 470R 3FH6 470R 3FH7 470R y LTST C190KGKT 6FH1 LTST C190KGKT 6FH2 y LTST C190KGKT 6FH3 y LTST C190KGKT 6FH6 LTST C190KGKT LTST C190KGKT vec FFHP 5DO _16 FLASH c FFHN DCLK 9 FFHM 1 50 HOLD vss FFHR 3FHG 47R 25 205 RES 3FH8 3FH9 3 1 4285 9 1 1 5 8 CONF DONE 2V5in FPGA 10K 6FH8 3FHK e FFHT 100 RES 100K 2 5 25 _ _ RES 1 00 1 e 4 DR FFG e V 2 FFH7 100R 6 FFH8 5 100R 3FH9 4 5 147279 2 100 100 2FJ5 RES 100p 2FJ6 RES 10n 2FJD RES 100p 3FHM BIS6E 2 jBCBA78W FOR DEBUG 2FH2 A3 2FH3 A3 2FH4 A3 2 5 4 2FH6 E2 2FH7 E2 2FH8 E3 A 2FH9 E3 2FHA A3 2FHB C3 2FHC B3 2FHD B4 2FHE B4 2FHF B4 2FHG B4 2FHH B4 2FHJ B5 2FHK B5 B 2FHL B2 2FHM B2 2FHN C2 2FHP C3 2FHR C3 2FHS C3 2FHT B3 2FHV C3 2FHW D3 2FHZ 03 2 0 D3 2FJ1 D2 2FJ2 D2 2FJ3 F11 2FJA F11 2FJ5 F11 2FJ6 F11 2FJ7 D12 2FJ8 C2 2FJ9
205. 5 Figure 2 6 HDMI type connector 1 D2 Data channel 2 Shield Gnd 3 D2 Data channel 4 01 Data channel Chassis Overview Refer to chapter Block Diagrams for PWB CBA locations 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Shield D1 00 Shield 00 CLK Shield CLK Easylink CEC n C DDC SCL DDC SDA Ground 5V HPD Ground Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel DDC clock DDC data Gnd Hot Plug Detect Gnd 66 96 2009 08 Q549 2E LA Precautions Notes and Abbreviation List 3 Precautions Notes and Abbreviation List Index of this chapter 3 1 Safety Instructions 3 2 Warnings 3 3 Notes 3 4 Abbreviation List 3 1 Safety Instructions 3 3 2 Safety regulations require the following during a repair Connect the set to the Mains AC Power via an isolation transformer gt 800 VA Replace safety components indicated by the symbol A only by components identical to the original ones Any other component substitution other than original type may increase risk of fire or electrical shock hazard Of de set ontploft Safety regulations require that after a repair the set must be returned in its original condition Pay in particular attention to the following points 3 2 3 3 3 3 1 2009 May 08
206. 5 12 2 6 10 S 2HY7 C11 7H00 10 eel tele e S so 2HY8 D11 p p 4 T segetes iere M 2 24182 __ 8 5 155 5 5 SISE E 2HY9 D12 zi vss 2HYA A13 2 13 amp 2 4 M 2HYF F5 L 2HZB F10 G 2HZC 1 F11 2HZC 2 F11 1V8 PNX85XX gt 2 2 4 F10 ze 2HZD F11 8 2HZE F10 2HZF F9 2HZG F9 2HZH H4 VSS 2HZK A5 vss 2HZL 4 L 5HY4 2 2 VDDA AUDIO VDDA DAC 2HZV alts 2HZY 1 B3 STE 2HZY 2 B2 2 2 3 2 2 2 4 2 3H55 D2 L 3H57 C2 5 50 M 5HG0 E12 VDDA AUDIO Y VDDA ADC L gt on gt 1 5HV2 C1 5HV3 F4 8 5HV4 C3 vss 5HV5 D3 N 5HV6 D1 5HV7 E1 1 5HV8 F2 5HV9 E3 5HVA E3 CHN SETNAME CLASS NO 2 2008 11 21 ums NAME Maelegheer Ingrid SUPERS 16 130 16 CHECK DATE 2007 11 29 B ROYAL PHILIPS ELECTRONICS 2005 10 2009 May 08 12 13 14 15 16 17 18 19 20 18310 517 090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA SSB 5100 SDRAM 1 2 3 4 5 6 77 8 9 10 A 11 12 13 14 15 16 17 18 19 20 d
207. 5 5 1Po2 CRX DDC SDA conte CRXDDCSQL CONNECTOR 1 1 58 45V DDC SDAAMBISVS 12 3CD9 i SCL AMBI 3V3 9 21 5 ei ish AW gt dina TO A AMBI LIGHT DDC SDA lt y DRXDDC SDA lt gt HDMI MODULE SIDE ANALOGUE EXTERNALS B PNxs100 s0Ram streams f PNxesas FLASH HDMI DV 45V DDC i 7 01 4 amp 1 06 SVDCOUT EDES116AJBG 19 DDCA SDA 19 91 91 ERX DDC SDA 2 lt gt lt gt lt 6AJBG eis a ie a IRS 1 C18 DDCASCL ERX DDC SCL CONNECTOR 4 ses 215 1 PU ee e DATA SDA 5 1M97 PNX5100 SDRAM lt gt 2 I2C SDA D z lt gt CLK SCL 6 7P10 gt 1 1 96 NANDOIGWSB2BNI 9P29 4 CONNECTOR 9 29 3 1 7 0 0 1 RESI li 4 DC DC EM TEMPERATURE amp FAN CONTROL FPGA BACKLIGHT LVDS amp I2C MUX FPGA LOCAL CONTRAST te oe ee NORTE ICH ORS re ONE PCN EN LO RUDE LVDS IN OUT 3V3 PER 100 kHz 8 1808 833 4 SDA2 SDA SET gt 515 E SDABOLEON 2 oF 5 i 3E83 lt
208. 5 D12 3336 D2 3337 D2 3338 D1 3339 D2 3340 D1 3341 D1 3342 E2 3343 D1 3344 D1 3345 D12 3346 1 3347 D1 3348 E12 3349 1 3350 1 3351 E12 3952 E1 3353 E1 3354 D13 3355 E1 3356 E1 3357 D13 3358 E13 3359 E13 E 3360 E13 3361 E13 3362 E13 3363 F13 3364 F13 3365 F13 3366 F13 3367 G13 3368 G13 3369 F1 3370 F1 3371 F1 3373 F1 3374 G1 3384 E1 3385 F1 3386 F1 3387 F1 3388 F1 3389 F1 3390 G1 3391 G1 7000 C2 7001 7002 C4 7003 C6 7004 7005 C11 7305 G4 7306 5 7307 F4 7315 G9 7316 H10 7317 F9 9301 C1 9302 C1 9303 1 C10 9303 3 C10 9303 4 C10 9304 1 E10 9304 2 E10 9304 4 E10 9305 1 C6 9305 2 C6 9305 4 C6 9306 1 D5 9306 3 D5 9306 4 05 9307 6 9308 6 9309 1 B6 9309 2 B6 9309 4 B6 9310 1 B8 10 11 12 13 9310 2 B8 9310 4 B8 9311 1 H13 9311 3 H13 9311 4 H12 9312 1 B10 9312 3 B10 9312 4 B10 9313 1 B12 9313 2 B12 9313 4 B12 B 9314 G5 9315 1 C12 9315 2 C12 9315 4 C12 9316 H5 9317 F5 9318 1 C8 9318 3 C8 9318 4 C8 9319 1 D9 9319 3 D9 9319 4 D9 9320 1 D7 9320 2 D7 9320 4 D7 9325 F10 9326 G10 9327 H10 F302 G5 F303 G4 F304 H5 F305 HS F307 F5 F308 F4 F325 F10 E F326 9 F327 G10 F328 G9 F329 H10 F330 H10 F340 D1 F341 01 F342 D1 F343 D2 F344 012 F345 D12 F346 D13 F347 G12 F348 G13 F349 G13 CHN SETNAME CLASS NO 2008 08 08 2 3 2 9 DRIVER 6LED LITEON 8204 000
209. 5 vm gt PCI ADS PCI AD4 1008 93 5 PCLAD2 55 gt PCI AD3 PCLADO S 5V mPCI A 4 PCI AD1 101 1 24 00 103 M66EN wn 105 FA30 FA34 10K 107 FA35 109 FA32 111 113 115 E 117 119 5 6 06 119 MPCIACL MMPCIACT AAA d 3 123 5 1 25 10K FA33 1734065 3 17340653 1X09 REF EMC HOLE CHN SETNAME H CLASS_NO 2008 11 21 2008 10 10 MINI PCI TV543 R2 LDIPNX 8204 000 8935 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 10 16 ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310_546_090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA 10 ZEE SSB DDR Supply PHILIPS 1 i 10 12 13 gt UJ 1 1M01 E3 2A10 E3 2V5 REF All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner m 12 p gt V LM833 2V5 REF b lt 3A09 3A11 1 01 10 RES 4708 VVV 10K lt lAC2 1 08 SACO V FACO 3V3 STANDBY gt lAC3 2ACO 100p 3A21 V LM833 v 1405 A 3V3F 7A01
210. 51 50 SDA DISP 49 SCL DISP 3 VDISP1 TELLE 2 1 1 20 8 5V 7 KEYBOARD 6 LEDI 5 3V3 STANDBY 1M95 B018 10 GND AUDIO POWER 20 GND GND GND STANDBY 3V3 STANDBY AMBI LIGHT MODULE 5 5 1076 1M99 6018 12 GND 11 SDA SET 10 SCL SET POWER OK BACKLIGHT PWM BACKLIGHT BOOST BACKLIGHT OUT 1 83 4 RIGHT SPEAKER GND AUDIO 2 GND AUDIO 1 LEFT SPEAKER 1735 1 9 TEMP SENSOR EEPROM CS EN Board Level Repair Component Level Repair Only For Authorized Workshop 8101 1M01 1M20 8P 18310 400 090305 eps 090421 2009 May 08 Block Diagrams Q549 2E LA 9 LIN Wiring Diagram 37 Elite Core WIRING DIAGRAM 37 eure B 1 83 1 SCL GND SDA CONTROL CONTROL 2 343 GND 8684 EEPROM CS TEMP SENSOR 10 PROG 14 VLED1 12 GND 13 VLED2 14 GND TO 8319 BACKLIGHT AMBI LIGHT MODULE 3 3 1074 AL 1 84 AL1 SP CLOCK BUF SPLDATA QUT SPI DATA RETURN SPLLATCH PWM CLOCK BUF 43V3 BLANK BU EEPROM CS TEMP SENSOR 10 PROG 14 VLED1 12 GND 13 VLED2 14 GND 11 NC 1M84 10 GND_SND 14 GND 5 GND1 4 GND1 3 GND1 2 STANDBY 1 3 3 ST 2 1 TEMP SENSOR 10 PROG 41 VLED1 12 GND 43 VLED2 14 G
211. 6 IHSW C9 IHSY 011 M IHSZ D6 3H63 47K 503 504 SPDIF_OUT AMT 25 IN Ws B 125 OUT 1 NEOMLADG 125 OUT SD AOUT IHRM 03 3HRM 758 3HRK 3HRN 2HRW 100n 2HRY 104 is prohibited without the written consent of the copyright All rights reserved Reproduction in whole or in parts owner 1 2 3 4 5 6 7 8 9 10 11 12 CHN CLASS NO 2008 11 21 AUDIO PNX8543 TV543 R2 LDIPNX 8204 000 8927 2008 10 10 3 NAME Maelegheer Ingrid SUPERS 16 CHECK DATE 2007 11 29 41 2 3 5 6 8 1 5022 11 12 T 13 14 15 I 16 17 18 19 I 20 18310 513 090302 eps 090302 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA GEJ SSB PNX8543 Audio All rights reserved Reproduction in whole or in parts PHILIPS is prohibited without the written consent of the copyright 2 3 4 10 11 12 13 gt UJ TEN PNX 8543 AUDIO AUDIO VDD 1 51 2 04 52 75 100R IH53 S 7H01 2 ANTA 5 BC847BS COL 5 6 J 2H05 55 3 76 4 47 2HVD 1 24 IHWL INADAC 3 4 82653 1HV9 Ons 1735446 439184 5 22K
212. 7 Sos 552 5958 1 90 i 1 p gt 24V 2 3 4 8 92Y9 8 5 ANTZE S gt OATS 6 1735446 6 L 12V 001 lt 02 VL ED STUFFING DIVERSITIES FOR DC DC INTERFACE 2 9 DC DC INTERFACE 1101 1M85 5103 5104 5105 5106 VLED1 VLED2 3104 328 58341 in in in out 24V 16V 3104 328 58351 out out out in 12V 12V 3104 328 58361 out out out in 16V 16V 3104 328 58371 out out out out 12V 16V See the stuffing diversities table in the case of components marked with one star 1100 A6 1101 A7 1M59 C2 1M84 A2 1M85 A2 1M90 D2 2100 A6 2101 B5 2102 C6 2103 D6 2104 D5 2105 D9 2106 D9 2107 E9 2108 D3 2109 E3 3100 B5 3101 C5 3102 D6 3103 D9 3104 D6 3105 D5 3106 D5 3107 D5 3108 E9 3109 D2 3110 D3 3111 E8 3112 B6 5100 A8 5101 A8 5102 A7 5103 B8 5104 B8 5105 B8 5106 B8 5107 A6 5108 A6 6100 C8 7100 B7 9101 C3 9102 C3 9103 C3 9104 C3 F101 B3 F102 B3 F103 B3 F104 B3 F105 B3 F106 B3 F107 A7 F108 B3 F109 B3 F110 B3 F111 B3 112 F113 114 5 115 2 F116 D2 F117 D2 F118 D2 F119 D2 F120 D2 F121 E2 F122 E2 F123 E2 F124 E2 F125 B3 F126 A2 1100 6 1101 6 1102 6 1103 6 1104 D9 1105 DS 1106 D7 1108 D6 1109 A8 001 2 002 2 CHN SETNAME CLASS_NO 08 06 19 08 08 06 DC DC INTERFACE AMBI 2 9 3104 313 63
213. 8 EU gle z 3E70 B13 5 8 MSP 305H BBB 523 03 NI AVA PR aud Ei CES 3E71 B13 2 4 8 3E72 C13 Se ge g 3 a 19 l l l 3E82 B7 TRED 8 52888 78 3689 c7 88 9E11 5 3V3 5 i FE42 8 8 EOM aviy in 52 oF A 2E52 3E95 15 22 3E96 14 8 10 3E97 14 3 EU 3E98 15 58 MSP 305H BBB 523 03 NI S _9 02_ Pi Av4 PB 7S SPDIF ouT b Fi 36942 E2 4 7E03 5V 3EA1 H14 555 x 100 3E20 2E08 EAS is x 5 Ji ee E 8 Bob 8 li 08 4 82 47R 100 5 02 1E90 3EA5 114 3 g 8 22g HO 3EA6 113 8 g PESE 8 8 1 1 L L L _ 01_ cues 918 sla 23 228 825 Poe sis H 3EB2 113 TTE 8 TB 298 poy 4 111 5 12 dE 3ED3 H14 5 02 H12 9E06 _ cd 1E70 2E78 5E05 B10 1 29 4 MSP 305H BBB 523 03 i AAA d s AUDIO IN3 L 4 COS 110 lt 8 x v 8 BC847BPN COL 1 1 03 1 5 2 uz a CLE waite ce gorges 28 8 gh 1 6 11 C6 1 07 5 1E38 3EB1 6E13 C10 iets BC847BW 4 1 61 100 6 15 11 3 zi Y CVBS MON OUT SC _9E28_ 2 470R 6E16 C13 _9 21_ 2A 52 1 6 17 14 3E97 228 8 8 Ney 6 18 4 YELO e AUDIO IN3 R A 6E38 14
214. 8857 2008 06 10 2008 08 08 NAME Peter Van Hove SUPERS CHECK DATE 2008 06 02 e ROYAL PHILIPS ELECTRONICS N V 2008 9 2009 May 08 11 12 13 14 15 16 17 18 19 20 18310 632 090306 5 090306 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner PHILIPS Circuit Diagrams PWB Layouts Q549 2E LA 10 LIE 10 LED Low Pow LED Drive Liteon 2 4 10 12 13 16 17 18 19 20 1 1 2 1 85 D2 LED DRIVE 7006 2 7007 7008 7009 LTW E500T PH1 LTW E500T PH1 LTW E500T PH1 LTW E500T PH1 S 4 4 4 GREEN 1 GREEN yj 3 GREEN yj GREEN yj GREEN 3 mE s s JR g s s gt BLUE 1 6 BLUE 1 6 yj 6 BLUE e BLUE 1 gt gt gt GND HS GND HS HS GND HS SPI CLOCK BUF E SPI DATA OUT SPI DATA RETURN 4 SPI LATCH 5 a gt PWM CLOCK BUF 6 7 8 omm BLANK BUF EEPROM CS TEMP SENSOR 40 gt PROG lt q VLEDI 13 q VLED2 14 SPI CLOCK BUF SP CLOCK BUF i aE 12 13 l 4 14
215. 9 ub g IN30 D2 5 g i PHDSBNO2LT IN34 B2 228 M et e E i ale IP31 D8 gates 32 D8 2 2 815 18 B N D 27827 18 D 741 245 82 225 pan 7N10 N IN22 o e 7P43 TS2431 FP19 7N12 IP32 F IN3049 74LVC245A 4 Z 2 2log m 3252 AT gt _ 19 10 i lt gt gt 10K RES PCI CBE1 17 m CA WE 6 16 PCI AD14 __2 55 15 a CA CE2 4 lt 14 CA CE1 PCLAD13 28 13 CA REG PCI AD12 12 CA IORD PCLAD11 lt 11 gt CA IOWR PCLAD10 PCI AD9 s PCI AD8 1 2 33 4 CHN SETNAME CLASS_NO 2008 11 21 UFD 2K8 DIGI TV543 R2 LDIPNX 8204 000 8934 2008 10 10 NAME Maelegheer Ingrid SUPERS 8 CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS 2007 1 2 3 4 5 6 7 8 9 10 11 12 13 18310_541_090303 eps 090303 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA 10 SSB Analogue Externals A
216. 9 B11 3220 C11 3221H11 3222 18 3223 C11 3224 H11 6216 18 7201 1 A10 7201 2 C10 7201 3 D10 7201 4 B10 7209 B2 7210 C2 7212 B3 7214 B6 7215 G7 9208 A10 9209 B9 9210 B10 9211 9212 9213 09 9214 010 202 203 5 204 6 205 10 206 207 208 010 209 11 F210 G9 211 69 212 69 F213 H9 214 9 F215 H9 CHN SETNAME CLASS NO 2008 08 08 NAME Peter Van Hove 2 3 DRIVER 6LED LITEON 2 9 8204 000 8857 1 2008 06 10 2 2008 08 08 3 7 SUPERS 130 2 CHECK DATE 2008 06 02 ROYAL PHILIPS ELECTRONICS 2008 10 rz 11 2009 May 08 12 13 14 15 16 17 18 19 20 18310 651 090508 eps 090508 Circuit Diagrams and PWB Layouts Q549 2E LA 10 8 LED Low Pow LED Liteon 2 3 4 10 11 14 1 6 17 12219 20 10 11 12 M 7 VLEDi F VLED2 9301 9992 EC LED LITEON VLEDi F VLED2 Y i 5 8 i _9308_ 8 7 2 93062 7 9309 1 4 93094 5 2 9310 2 1 7003 7000 7001 7002 LTW ESOOT PH1 LTW E500T PH1 LTW E500T PH1 LTW ESOOT PH1 6 93183 3 5 4 9810 4 9310 1 8 1 7004 LTW E500T PH1 3 93033 6 123 6 93121 8 1 7005 LTW E500T PH1 2 93152 7 8 7 981931 13 4 93134 5 2 GREEN
217. 93 3T92 1194 om SIS ANTENNA CTRL 5 Ps 20 L L me ES AL 3T92 G3 1 1795 1 mue E E 5 3 93 G3 aava 19 5 52 3T94 H3 K lt E 3 95 9 BSE ae 5150 RESERVED wet 518197 NT SAT 5152 G6 L E 3 5T53 H6 1 5154 17 ui me 515516 5153 58 3130 6T50 H 6T51 F2 L elaels 7T50 A6 RETRETE 7T51 1 7751 2 je 7752 1 E9 1 7752 2 E10 7789 EN 7153 1 E11 2 gt 7753 2 E11 M Eo 7154 F7 plyelyelsels 514815 7755 1 F4 RTSETSETBETE NTSNTS 7155 2 G4 56 9115 C1 i id 4 9716 C1 5T55 FT63 9T62 F6 5V TUN 5V TUN CVBS 9T63 E11 9T64 F6 9117062 9T71 C2 SETNAME CLASS NO 2008 11 21 2008 10 10 3 NAME Randal De Keyzer SUPERS 3 130 2 A2 CHECK DATE 2008 06 03 ROYAL PHILIPS ELECTRONICS N V 2008 10 12 2009 08 13 14 15 16 17 18 19 20 18310 504 090302 5 090302 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner Circuit Diagrams and PWB Layouts Q549 2E LA 10 EEJ SSB PNX8543 Stand by Controller PHILIPS O 2 3 4 10 AN 12 13 14 15 16 17 19 20
218. A DAC BO4F 1x PCI AD15 BO7H 1x PCI AD8 1x PCMCIA D6 1x RX51001B 6 2x 1 BO6D 1x TX851D 2x VDDA DAC 8056 1 PCI AD15 1 BO7H 1x PCMCIA D6 BO6D 3x RX51001B 6 2x TACHO1 INV 1 TX851D B040 VDDA LVDS BO7G 1x PCI AD15 1x PCI AD9 PCMCIA D7 BOSB 1x RX51001B 6 2x TACHO2 B040 1x TX851D BO4P 1x VDDA LVDS BOSA 1x PCI AD15 8056 1x PCI AD9 BO7H 1x PCMCIA D7 BO6D 3x RX51001B 6 2x TACHO2 INV BO6D 1x TX851D 2x VREF DDR1 BO4F 1x PCI AD16 BO7G 1x PCI AD9 5x PCMCIA VCC VPP 1x RX51001C BOGE 1x TCK 1x TX851D 1 VREF FPGA1 BO5G PCI AD16 BO7H 1x PCI AD9 BO2A 2x PDN BO6D 3x RX51001C 1 TCK B040 1 TX851E BO6G 16x VREF FPGA1 BO7G 1x PCI AD16 BO9A 1x PCI AD9 2 1 BOSB 1 RX51001C BOGE 1x TDI BO6D 1x TX851E 1 1x vsw BO7H 1x PCI AD16 1x PCI CBEO BO2A 1x PDP BO6D 3x RX51001C 1 TDI 1x TX851E BO1B vsw 1x PCI AD16 8056 1x PCI CBEO BO2B 1 PDP 1x RX51001CLK BOGE 1x TDO B040 1x TX851E BO4K 1 V SYNC VGA BO4F 1x PCI AD17 BO7G 1x PCI CBEO 2x PME BO6D 3x RX51001CLK 1x TDO BO6D 1x TX851E 8 1x V SYNC VGA 5 1 PCI AD17 BO9A 1x PN
219. AME CLASS NO 2 2008 11 21 2008 10 10 3 Maelegheer Ingrid SUPERS 9 130 5 CHECK DATE ROYAL PHILIPS ELECTRONICS 2008 eee 11 2009 May 08 12 13 14 15 16 17 18 19 20 18310 522 090302 eps 090302 Circuit Diagrams and PWB Layouts Q549 2E LA SSB 5100 Control i 1 2 3 4 5 6 10 11 12 13 gt PHILIPS 1 00 A2 2 00 2 UJ 1 0 7 00 1 5100 9 E gle xs 58 CONTROL 5 IN 55 AF13 n 55 OUT XTAL Ace AL 55 CLK OUT PNX5100 E 3000 AF14 our2 ua2 5 D 3003 5 cL K2 3CD7 100R y SCL SSB 7 3g EJTAG PNX5100 TCK _ FCDO 4 1 K1 3CD8 a 100R ae SDA SSB gt e TCK SDA VVV gt 23 EJTAG PNX5100 TDI 5 FCD1 H2 os EJTAG PNX5100 TDO 4 FCD2 H3 TDO 12 3CD9 100R SCL AMBI 3V3 3 B EJTAG PNX5100 TMS Ji TMS SDA Li 1008 2 SDA AMBI3V3 9 5 EJTAG PNXS100 TRSTn lt 2 TEST RES B is RESET svs P PNX5100 RST OUT 5 RESET PNX5100 228 24 RESET IN 7 5 2 G22 St ICD8 RI OBSERVE zo 8 wu b y Tey AB21 NC os 8328 825 926 ASS ASS 3V3 VPP ID TSE OSF gt
220. Avec M moire Color system mainly used in France and East Europe Color carriers 4 406250 MHz and 4 250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus a 4 wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board STand BY 800 x 600 4 3 Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 x 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 x 1200 4 3 V sync to the module Video Electronics Standards Association 640 x 480 4 3 Variable Level out processed audio output toward external amplifier Vestigial Side Band modulation method What You See Is What You Record record selection that follows main picture and sound 1280 x 768 15 9 Quartz crystal 1024 x 768 4 3 CS Luminance signal Luminance Y and Chrominance C signal Component video Luminance and scaled color difference signals B Y and R Y Component video 2009 May 08 Mechanical Instructions 4 Mechanical Instructions Index of this chapter Notes 4 1 Cable Dressing and Taping Figures below can deviate slightly from the actual situation 4 2 Service
221. B O M number 1 If the third digit is a 2 example AG2B0335000001 then the set has been produced according to B O M no 2 This is important for ordering the correct spare parts For the third digit the numbers 1 9 and the characters A Z can be used so in total 9 plus 26 35 different B O M s can be indicated by the third digit of the serial number Identification The bottom line of a type plate gives a 14 digit serial number Digits 1 and 2 referto the production centre e g AG is Bruges digit 3 refers to the B O M code digit 4 refers to the Service version change code digits 5 and 6 refer to the production year and digits 7 and 8 refer to production week in example below it is 2006 week 17 The 6 last digits contain the serial number 32PF9968 1 MADE IN BELGIUM MODEL 0 PHILS PHILIPS 128W VHF S H UHF 10000 024 090121 eps 090121 PROD NO AG 1A0617 000001 Figure 3 1 Serial number example Board Level Repair BLR or Component Level Repair CLR If a board is defective consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level If your repair procedure says the board should be exchanged completely do not solder on the defective board Otherwise it cannot be returned to the O E M supplier for back charging Practical Service Precautions e t makes sense to avoid exposure to electrical shock While some sources are exp
222. B9 FU1G E9 FU1H C4 FU20 E1 FU21 E1 FU22 E1 FU23 E1 FU24 C1 FU25 D1 FU26 D1 FU30 A1 FU31 A1 FU32 A1 FU33 A1 FU34 A1 FU35 A1 FU36 B1 FU38 B1 FU39 E5 FU40 F4 1020 B4 1021 B4 1034 A8 1035 B8 136 F7 1U37 F8 1038 E7 1U39 F9 1U3B E8 IU3C B8 IU3T C8 1040 1041 1042 4 1043 1044 1045 F4 1U47 1048 4 1049 4 1050 5 1051 1052 B3 1053 B4 1054 5 2008 11 21 F4 IB DC DC Bio 1B 100 3U90 1048 39 mm 2042 100R 100K RESERVED TO 100 1049 T A LED PANEL 4 3V3 STANDBY ance 5U07 1998 33 3V3 STANDBY FU32 1 oo 5010 100 1951 Y ac B 2 2R ANA 82 S 3 FUSS _ 308 5012 1008 gt xo 1 3V3 STANDBY RES 9 4 _ 9006 _ 45V 3V3 STANDBY 8 gt 2 529 1034 BC847BW Fuss 30R 2044 2 e p 1 2 5 1052 1 4 2025 FU1F 8 e gU E 100 54 58 VV 11 1 5V A 525 855 RES 22 oue 2045 100R lt a lt a 8 8 1053 3 4 S a E 100 SUNT 7UON d RTT 2U21 RES RES TS431AILT 5 BC847BW 221 4 1035 100 3V3 4 8 ee arg 3U3V 818 7011 88 S72 BC847BW 58 5 2 25 12VD gt auos 5
223. BE28 F2 H i 1 28 e 18 9 4_ _ RIGHT FE25 3 26 3 6 FOR ITV e t 1 n saa FE20 B2 F MSJ 035 10A B AG PPO 43264 F Fene Le AM FE22 C3 mE FE23 D3 100 4V 0 2 80 D TELLS 25 24 2 78 IE72 gt 100 4V V NOM 1003 a SRES 100K 2E45 cpsac 2E 1n0 3E77 1002 4 V NOM 1 15 5 1 36264 HEADPHONE 12V 3E80 1K0 _ 2E40 VINAM amp gt 6 44 1 24 FE25 F5 56 A2 FE86 B7 9E32 1 2 3 4 5 6 7 CHN SETNAME CLASS NO 2008 11 21 ANA SIDE TV543 R2 LDIPNX 8204 000 8930 2008 10 10 NAME Maelegheer Ingrid SUPERS 4 CHECK DATE 2008 01 18 ROYAL PHILIPS ELECTRONICS N V 2007 1 2 3 4 5 6 7 8 9 10 11 12 13 18310 544 090303 eps 090303 2009 May 08 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright Circuit Diagrams and PWB Layouts Q549 2E LA 130 SSB Analogue Externals 1 2 3 12 13 14 15 16 17 18 19 20
224. C UP 5 SDA SET BOSE 3x TXACLK BO6D 1x TXF2B 5 1 PCI AD1 1 PCI AD30 1 PCMCIA A14 8070 2x REF 3V3 BOGC 2x SDA SET BOSE 3x TXACLK BO6G 1x 2 7 PCI AD1 1x PCI AD31 BO7H 1x PCMCIA A14 2x REGIMBEAU_CVBS SWITCH BOGA 2x SDA SETO BOSE 3x BO6D 1x TXF2C BO7G 1x PCI AD1 8056 1x PCI AD31 1x PCMCIA A2 BOBA 1x REGIMBEAU_CVBS SWITCH BOGA 2x SDA SET1 BOSE 3x TX4D BO6G 1x TXF2C BO7H 2x PCI AD1 BO7F 1x PCI AD31 BO7H 1x PCMCIA A2 BO4A 2x RESET AUDIO 2 2x SDA SSB BOSE 3x TX4E BO6D 1x 2 1 PCI AD1 BO7G 1x PCI AD31 1 PCMCIA A3 BO4M 2x RESET AUDIO 2x SDA SSB BOSE 3x TX4E BO6G 1x 2 BO4F 1x PCI AD10 BO7H 1x PCI AD31 BO7H 1x PCMCIA A3 BOAN 1x RESET BOLT ON BOSF 2x SDA SSB B040 1x TX851A BO6D 1x TXF2CLK 8056 1 PCI AD10 1x PCI AD31 1x PCMCIA A4 BO7F 1x RESET BOLT ON 1x SDA SSB BO6D 1x TX851A BO6G 1x TXF2CLK BO7G 1x PCI AD10 1x PCI AD4 BO7H 1x PCMCIA A4 2x RESET ETHERNET 1x SDA SSB 1 851 BO6D 1x 2 BO7H 1x PCI AD10 8056 1x PCI AD4 1 PCMCIA A5 BO7G 2x RESET ETHERNET BO7D 1x SDA SSB B040 1x 851 BO6G 1x TXF2CLK 1x PCI AD10 BO7G 1x PCI AD4 BO7H 1x PCMCIA A5 1x RESET ETHERNET BO8D
225. C7 3P37 C1 3P39 1 C3 PNX 8543 FLASH 3P39 2 C3 B 3P39 3 C3 B 3P39 4 D3 3P40 1 D3 A A 3P40 2 D3 3P40 3 D3 3P40 4 D3 3P42 E3 3P44 03 3P48 1 C 3P48 2 3P48 3 F3 3P48 4 F3 3P57 C11 5 09 1 I 7P10 C5 B B 24 5 27 D5 D 29 BS D 0 4 3V3 NAND gt Fa 5P09 24 3313 3V3 NAND ale als oor NANDOIGWSB2ENGF 5 vec i im 43V3 NAND gt 54 XIO SEL NAND 3 TSO BIT CLK c Vd gt 2 40K 4 TSO BIT VALID 10k H TSO SYNC PCI AD24 2 3P39 1 1 8 es NAND AD 0 NAND AD O 29 6 TSINO DATAO 5 PCI AD25 5 3 39 2 2 71008 gt lt NAND AD 1 NAND AD 1 25 30 10 TSINO DATA1 6 12 26 3 39 3 3 61008 NAND AD 2 NAND AD 2 5 31 2 11 TSINO DATA2 7 27 3 39 4 4 7 7 51008 3 NAND AD 3 25 32 15 14 TSINO DATA3 8 PCI AD28 3P40 1 1 id 8100R NAND AD 4 NAND AD 4 41 410 15 TSINO DATA4 2 29 3P402 2 7 71008 NAND AD 5 NAND AD 5 42 5 20 ISINO DATA5 0 a PCI AD30 3 40 3 3 6100R NAND AD 6 NAND AD 6 43 6 21 TSINO DATAG 2 PCI AD31 3 40 4 4 7 51008 NAND AD 7 7 44 7 22 TSINO DATA7 12 E 25 I2C SDA za gt jis D m NAND CLE 16 Jas 27 MRESET BOLT ON pu 22 NAND ALE __ __
226. Colour Television Chassis Q549 2E LA Service Service Service 8310 000 090317 eps 090317 Service Manual Contents Page Contents Page 1 Revision List 2 SSB SRP List Part 2 136 2 Technical Specifications and Connections 2 Light guide 139 140 3 Precautions Notes and Abbreviation List 6 Wi Fi Antenna 141 141 4 Mechanical Instructions 10 5 Service Modes Error Codes and Fault Finding 15 6 Alignments 36 7 Circuit Descriptions 42 8 IC Data Sheets 53 9 Block Diagrams Wiring Diagram 32 Elite Core 59 Wiring Diagram 37 Elite Core 60 Block Diagram Video 62 Block Diagram Audio 63 Block Diagram Control amp Clock Signals 64 Block Diagram I2C 65 Supply Lines Overview 66 10 Circuit Diagrams and PWB Layouts Drawing PWB Interface Ambilight Interface Single DC DC AB1 67 70 Interface Ambilight Dual DC DC AB2 68 70 Interface Ambilight Microcontrollerblock AB3 69 70 6 LED Low Pow Microcontroller Block Liteon AL1 71 74 6 LED Low Pow Microcontroller Block Liteon AL2 72 74 6 LED Low Pow LED Liteon 73 74 8 LED Low Pow Microcontroller Block Liteon AL1 75 79 8 LED Low Pow Microcontroller Block Liteon AL2 76 79 8 LED Low Pow LED Liteon 77 79 8 LED Low Pow LED Drive Liteon AL4 78 79 10 LED Low Pow Microcontroller Block Liteon AL1 80 84 10 LED Low Pow Microcontroller Block Liteon
227. D3 F PNX5100 DDR2 CLK N 25 gt lt PNX5100 DDR2 D31 3C03 H2 a n 0 PNX5100 DDR2 DQMo aeo 1 23 Z PNX5100 DDR2 DQM1 D 100R DOM gt 926 PNX5100 DDR2 DQM2 D 3 05 2 G6 L 3 623 22 PNXS100 DDR2 DQM3 3 05 3 15 Ws 3C05 4 H5 PNXS100 DDR2 DQSO P 1 00 3 06 1 5 paso was PNX5100 DDR2 DQS0_N a EM aso HOOK 3C06 2 H5 G G 24 PNX5100 DDR2 DOS1 P 3C06 3 H2 past Y23 PNXS100 DDR2 DQS1 I 3 06 4 12 3C07 1 G6 E25 PNX5100 DDR2 DQS2 3 07 2 65 I Sadh E26 PNX5100 DDR2 DQS2_N 3 07 3 G5 PNX5100 DDR2 DQS3 P 3 07 4 6 bass E23 PNXS100 DDR2 DQS3 3C08 1 H5 H E 1V8 PNX5100 1V8 PNX5100 E 30082 H 3C09 1 H6 3 09 2 5 legis 3C09 3 H5 8 8 28 83 88 282 amp 3 09 4 6 8 88 3 10 C4 7 c cum 3C11 H6 3612 12 EN 3c1312 of o of of 5 29 9 5 5 51 5 e 3ls2ls l1sils3lsilsilsils 9 58 158 158 15815 gia scat Be a ls gt 59 5 La 5150150150 5 e 2 2 F 872887 287287887 S87 es pears RTSRTERTERTERTER TB 8 4 S TESTER TER TER TS 5 8 F MCA EI 3 23 12 _ q 3 25 1 G12 WE MEL M LL gt C F ww
228. DA 1V2 722 1V2 PNX5100 DLL 2660 481 7 00 10 4 a FCO7 A VSSA_LVDSIN VSSA DLL7 2C61 1 B2 7C00 11 A7 B 1V2 PNX5100 ge 1 gt GOOD S gt p 6 mu 2C61 2 B2 CC60 A3 B el 5 1V2 PNX5100 VDDD_1V2_TRI_PLL1 VDD_1V2_DDRPLLO 26 1V2 PNX5100 2C61 3 B2 07 2 T 878 5 8 8 8 i VSSD TRI PLL1 VSS DDRPLLO 4 2 61 4 2 IC80 D7 8 6700040 1V2 PNX5100 TRI PLL1 5 VDDA 1V2 TRI PLL1 VDDA 1V2 DDRPLL1 1V2 PNX5100 DDR PLL1 2C62 1 B2 IC81 D7 1 VSSA TRI PLL1 VSSA DDRPLL1 2 62 2 06 82 AL E 2 62 3 2 1 83 7 SUPPLY 1 1V2 PNX5100 VDDD 1V2 TRI PLL2 VDDA 3V3 DDRPLLO T9VSEDNXSTOO DDR REEO 2 62 4 6 IC84 E7 Pee o gt p gt A53 VSSD TRI PLL2 2C63 1 B3 IC85 F7 wo wo 19 x 2 1V2 PNX5100 TRI PLL2 5 VDDA_1V2_TRI_PLL2 VDD 1V2 DDRPLL1 1V2 PNX5100 2063 2 IC86 09 E 5 5 5 4 8 5 VSSA TRI PLL2 VSS DDRPLL1 2C63 3 6 87 E9 OTOTOTO TOTTE AF1 A Ep ek B 2 63 4 B3 1 88 E9 B tle ale mle ele mle le wie mle wie wle mle le 5 5 B1 _ 15 E15 1V2 PNX5100 LVDS PLL 7 5 ols 25 75 els 5 5 05 595 5 8 S B1 4 V2 PNX5100 TRI PLL3
229. DISP an 5 ap een EET 2CAT A10 FCB8 D12 XQ RES a 9610 _ m RES SCL DISP 1008 FCAT 2CAV B10 9 012 ICAA cag RES LAMP ON OUT 100R 9 2CAWB10 012 Los TTE 2686 pa BACKLIGHT OUT TOR FOTS 2CAYB10 FCBB D12 m r E TX3CLK oR 2CAZ B10 FCBC D12 RM RES 5 10 1 RES a RES CTRL DISP4 M 2CB0C10 012 2 6 4 7 e ae 2 0 4 7 CTRL DISP3 RES 100R 04 AN AN 2CAT 4p7 RES Scar _ pad 2CB1 4p7 CTRL DISP2 100R 3CAD Puit 2CB1 C10 FCBE E12 T Noack RES J FCJ5 RES 9632 L TX3CLK RES CTRL DISP1 SOME RES 1008 2 2 C10 FCBF E13 pepe Uo dae 10 al FCAB 100 2CB3 C10 FCBG E12 _ gt 2 4 010 E12 E Ne n FD T E gt C 2cB5D10 2 TX2CLK y 5 TX1B gt e 30 RES n TX3B gt FCAY o Dock OUTS EN 2 e 2 2 4 7 7 2 6 10 FCBK E12 2 9 oq C e 2083 1407 FOROS 2CB7 E10 FCBM E14 2 E 5 Txic FCA4 27 IX3D RES eC 2CB8 E10 FCBN B8 F TX2C 20 26 4 2 9 1
230. DRIVER 6LED LITEON 2008 08 08 8204 000 8857 HE P 2008 08 08 2 2K9 2008 10 27 3 NAME Peter Van Hove SUPERS CHECK DATE 20080602 ROYAL PHILIPS ELECTRONICS 2008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310 610 090305 5 090410 2009 08 rights reserved Reproduction in whole or in parts Circuit Diagrams and PWB Layouts Q549 2E LA ES LE 6 LED Low Pow Microcontroller Block Liteon 12 14 9 20 PHILIPS c is prohibited without the written consent of the copyright owner 11 12 13 220188 2202 C8 2203 D8 A 2 7209 PDTC144EU MICROCONTROLLER LITEON 48V3 i 1 3218 10K 7212 PDTC144EU osy acs ase 3 1 Y A A 4 10K 7214 8 D o 64K GND Hone 33 W 95010 6 4 7215 TLC5946PWP 25 1 tu amp vec LED DRIVER PWM CONTROL 3217 RECO F204 A 27 T mne meV 3 pols 3216 100R 3V3 3214 26 10K 2211 GSCLK BLANK MODE IREF ISCLK SIN XHALF GND GND HS OUT XERR
231. E 1 06 HDMI SIDE CONNECTOR OPTIONAL AB2 DUAL DC DC 424VF dmi al i 7200 TPS54283PWP PNX8543 FLASH 14 12 5201 VLEDI 412v ABI 1 3 43V3 gt LED2 5 09 3V3 NAND 3 520 WUDA Hev AB1 LO t OPTIONAL ETHERNET MICROCONTROLLER BLOCK 43V3 avs avs 5 6 48V3 ET DIG BO1b gt 5 7 1V8 s Boag ee OPTIONAL 1 43V8 z B05a c 45V5 TUN 45V5 TUN T 45V TUN B02a b 8069 7 13 064 I 8055 m B06g TY ANALOGUE EXTERNALS 3V3 3V3 me 45V 45V 064 B06g Tz ANALOGUE EXTERNALS 3V3 3V3 gt E 45V 12V 12V las 5 ANALOGUE EXTERNALS D 313 33 3V3 STANDBY 43V3 STANDBY gt 45V 45V L 18310 406 090305 eps 090306 Circuit Diagrams PWB Layouts 10 10 Circuit Diagrams and Layouts Interface Ambilight Interface Single DC DC All rights reserved Reproduction in whole or in parts 1 2 3 10 11 12 13 gt PHILIPS UJ is prohibited without the written consent of the copyright owner AK
232. E DATA3 Rida a JE 2158 RES T 19 e FE DATA4 2173 H6 1788 B10 RESET SYSTEM 3 100n 32 RSTN 5 20 ma gt FE DATAS 2T74H7 IT59 B9 FE DATAG 2T75 H6 IT60 B4 31 ISAW_SW 7 22 5 FE DATAT I 21767 IT61 B3 Ires 3 57 2177 16 1762 B9 SCL SSB SCL SSB x 23 33 5 L 2 SDA SSB N SDA SSB prd TOOR 29 gt 217816 IT63 B9 31597 LN 2179 16 1165 _9T15RES TUN SCL TUN SCL _9T70_ AKT M oe sr 44 2760 1770 07607 278017 1766 C4 29116 RES TUN SDA TUN SDA Nii 61 5012 19K Ve 2 8117 67 4 F5 ae BSE eu IT68 JTAG TCK DRXK 2783 4 IT69 C8 7151 2 JTAG TDO DRXI 57 28 3763 5 BC847BPN COL 2784 IT70 C9 JTAG TMS DRXK TMS ws 7751 1 2785 2 IT73 C9 e 4 2 RES NOD P 3 50 2 1175 09 Roy teu 30 erior VSYNC 3T64 5 60 3T51 A10 IT76 08 3 8 8 5 8 5 3 5 672 AA ER 315282 1177 09 Bog AT 84 3 53 2 1 79 03 87 85 3T54 B3 IT80 E9 68 86 RESERVED 3155 B2 1T81 E10 F 3V3 3V3 3V3 3V3 69 87 ANTENNA CTRL 70 88 3T56 011 1783 E9 4 D e 1784 E2 3767 72 90 3758 C4 1185 5 91 do au FT61 3T59 C4 1 86 F6 m v 8
233. E13 IF17 D10 825 255 228 3F21 F13 IF18 D9 K 5 8 158 528 gis 22 E7 IF19 E9 E 5 3F23 E7 20 C13 3F24 1 IF21 ava x 3F25 E2 1229 B14 1 1 3F26 F6 IF32E7 3F27 F2 IF33 E7 FOR FACTORY USE ONLY F 1 3F29 F13 IF35 F7 be dot 100 H IF36 E10 2 5 oo Sack 2 5 RES me 3F31 G13 IF37 E10 558 552559 158 5 8 3F36 A8 IF38 F10 3F37 IF39 F10 1 05 25 20 3F38 A8 IFA8 A11 i 4 5 050 8 1F03 Ver 3F39 B8 IFA9 A10 2 100R 3 6 3 00 3 MOSI 1 MOSI e 5 D MISO 3F40 C13 3 202 D IOR 5 MISO 2 1 29 FFO4 2 2 3F41 C13 Toor FLASH 3F79 F10 M 80 F10 D imi weet Fam 5 5 84 E7 917 2 8 L FOR 5 12 6 12 Ant PROG B DEBUG 3FAA A10 10 5F02 C1 E 5F03 A2 5F04 A2 5F05 B14 5 06 B14 1 2 3 4 5 6 nd 7 8 9 10 11 12 13 14 EMC HOLE CHN SETNAME CLASS NO 2008 11 21 1 FPGA Backlight LVDS 4 I2C MUX BENE TV543 R2 LDIPNX 8204 000 8933 2008 10 10 3 P NAME Maelegheer Ingrid SUPERS 8 DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS 2005 8 9 10 NY 2009 May 08 1 2 13 14 45 16 17 18 19 20 18310 527 090302 eps 090302 Circuit
234. E7115 FE59 F13 23 3 eng 2E7215 FE69 D10 ers 84 2 76 111 FEB2 C13 FE26 i i 1 1 1 i i i 1 2E78 14 FEB3 D13 2 79 114 IEO1 H10 2 81 12 1 02 H9 2 92 13 1 03 65 a DATA SDA 2E93 IEO7 112 2E95 F10 1 08 F5 D 229810 IE10 B12 2 99 C9 1 13 19 2 1 H12 1E15 F11 2EB3 14 1 19 A2 2 4 4 1 24 GB 2ECF B3 1 25 GB 2 21 1 57 1 68 AUDIO OUT I m 25 a e MSP 305H BBB 732 03 NI 3E01 B6 IE26 G5 10 150 4708 4 3E03 7 1E27 5 3 04 1 G8 1E2915 5 3E04 2G8 1E3115 aese 1862 a 17 8 3E04 3 H8 1E32 C13 gt gt ee 8 4 82888 05 4 1E33 F9 10 1 1 E 1 4 F8 BC8478S COL 9 xp 3E13 H9 1 35 F9 Pct loc 3E20 H10 1E38 112 MSP 305H BBB 732 03 NI 3 3229 CVBS MON OUT CINCH 1 3E25 D9 1 57 08 v2 zd 3E29 5 60 114 3E33 D10 1 61 114 E EDEN RSS 8 8 EU 3E35 C6 1 62 E9 91 ae 108 Wis 4 3E36 G4 IE68 09 8 2094 8 AUDIO QUT R dap ips MSP 305H BBB 732 03 NI 3E42 B7 1E70 H13 gt L 1b pot 6 3E46 C5 IE89 H13 d 0 3E47 C11 1 90 H13 res Sle lt 1801 3E48 F10 UFE RI _ aese 1835 s et 8 32 gt 8 8 1 RES 12682 3E53 F10 7E102 4 2 56 BC847BS COL bu 5E06 59 CON JACK E 5 Y 5 30R 3E65 C12 2
235. ED2 18310 700 090309 eps 3104 313 6343 2 090309 2009 May 08 Circuit Diagrams and PWB Layouts Q549 2E LA HEJ SSB SRP List Part 2 Netname Schemati 8056 2x 25 PCI IRDY 2x PNX5100 DDR2 D30 BOSF 1x SCL AMBI 3V3 BOSE 3x TX1C BOSE 1x TXDAT BO7F 1x 25 4 1x PCI PAR 5 2x PNX5100 DDR2 D31 1x SCL AMBI 3V3 BOSE 3x TX1C TXDAT 1 1 BO7G 1x PCI AD25 BO5G 1x 2x PNX5100 DDR2 D4 1 SCL AMBI 3V3 BOSE 3x TX1CLK BO4E 2x TXD MIPS BO6G 1x 1 BO7H 1x 25 BO7G 1x 2x PNX5100 DDR2 D5 BOAN 1x SCL BOLT ON BOSE 3x TXICLK BOBD TXD MIPS 4x MOCLK VS2 1 PCI AD25 1 PCI PAR 5 2x PNX5100 DDR2 D6 3 SCL BOLT ON BOSE 3x TX1D BOE 2x TXD MIPS2 3x MOSI 1x PCI AD26 BO4F 2x PCI PERR 2x PNX5100 DDR2 D7 BO8D 1 SCL BOLT ON BOSE 3x TX1D BO6B 1 TXD MIPS2 4x MOSTRT 8056 1x PCI AD26 8056 1x PCI PERR 2x PNX5100 DDR2 D8 BOSE 2x SCL DISP BOSE 3x 1 2x TXD UP 4x MOVAL BO7F 1x PCI AD26 BO7G 1x PCI PERR 2x PNX5100 DDR2 D9 SCL DISP BOSE 3x 1 BOBD 4x TXD UP 2x MPCIACT BO7G 1x PCI AD26 PCI PERR 2x PNX5100 DDR2 DQMO BO6D 1
236. EL SHIFTER FOR 1 43V3 PER LED PANEL CONTROL d DEBNGIONEY RESERVED e eee ee 4 qme 1 1E06 RXD MIPS2 5155 1 UART TXD MPPS2 lt 5 SERVICE CONNECTOR RES A 18310_405_090305 eps 090316 2009 08 Block Diagrams Q549 2E LA EB Supply Lines Overview SUPPLY LINES OVERVIEW serv 1 5 1M99 12VD 12 Bosh 12V Q GND1 35 amp BGNLOEF LAMP ON OUT CONTROL BM BACKLIGHT OUT CONTROL iier BACKLIGHT BOOST EZ CONTROL EID BACKLIGHTPWM ANADISP_ pem CONTROL POWER OK OK Eu MAIN CONTROL 3V3 STANDBY 3 3V_ST gt 4 1 2 gt B01a B04p B07h STANDBY CONTROL GND1 Bod GND1 GND1 12 2 n B06c B07b h dev BO8b BO9b tov gt 3042 suog 6008 12 01 Bota AUDIO POWER Bota AVSND B04i m B10a i GND_SND 2K9 SUPPLIES O 28 SUPPLIES Sa on 2 5 GND1 TO 1 gt 24Vb DC DC INTERFAC 45V GNDI OPTIONAL 1M20 ad 3V3 STANDBY
237. ER 1 error 2 Disconnect the mains cord now and start up the TV set with the solder path SDM short to ground during start up to activate the LAYER 2 error blinking Error 21 will be logged and displayed via the blinking LED procedure after a few moments from start up Remark the rebooting can be recognized via a ComPair interface and Hyperterminal for Hyperterminal settings see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging It is shown that the loggings which are generated by the main software keep continuing Check in the logging for keywords like e g Device error 21 Error 23 HDMI When there is no IC communication towards the after start up LAYER 2 error 23 will be logged and displayed via the blinking LED procedure if SDM is switched on It should be noted that in case a new spare EDID MUX device is used for repair the initial default address must be changed from CO to CE to be done via ComPair Error 24 12 switch When there is no communication towards the 2 switch LAYER 2 error 24 will be logged and displayed via the blinking LED procedure when SDM is switched on Remark this only works for TV sets with an 2 controlled screen included Error 25 Boot NVM PNX5100 Same behaviour as described in Error 21 PNX5100 Error 27 Micronas IF When there is no 2 communication towards the multi standard demodulator LAYER 2 error 27 will be logged and display
238. ESET BOLT ON i CA ADD EN FE DATAO gt 010 0 0 9 2 FE DATAZ 2 8 11 3 FE DATAG 5 C11 TNR CA DATA EN FE DATAS 3 D11 5 10 CA RDY savs 3ws FE ERR C12 ERROR CA RST 2H08 B10 TNR CA_VCCEN 2 85 T 100n 3V3 PER 1 4 gt ITNR MISTRT CA VPPEN kc 3HB5 FE VALID C10 TNR ven 1 Ll 10K ab 2 9i 193 d FE DATAT gt 2 gt sa TSINO DATAZ l FE DATAG gt 3 17 sa FE DATAS lt 4 16 23 TSINO DATAS FE DATA4 2 5 15 23 4 FE DATA3 gt 6 14 lt TSINO DATA3 FE DATA2 2 7 13 24 TSINO DATA2 FE DATAI 2 8 12 2 ISINO DATA1 TSINO DATAO smn 313 33 2H09 100 7H5 o 2 1 1 2 BOLT ON TS ENn zi 3HB6 3HB7 a 10K v 10K J 3 E 17 Ed 4 16 5 15 FE SOP 6 14 TSO SYNC FE VALID 7 13 TSO BIT VALID FE CLK 8 12 TSO BIT CLI FE ERR 9 11 TSO BIT ERI 2H08 03 10 11 2 09 B 3H73 2 3HB1 C2 EIEEXS 3HB3 C2 3HB4 D2 5 D2 3HB6 F2 3HB7 F4 3HWK D5 3HWN 1 B11 3HWN 2 B11 A 3HWP C10 3HWR 1 B11 3HWR 2 B11 3HWR 3 C10 3HWR 4 B10
239. Error Codes How to Activate CSM Key in the code 123654 via the standard RC transmitter Note Activation of the CSM is only possible if there is no user menu on the screen How to Navigate By means of the CURSOR DOWN UP knob on the RC transmitter can be navigated through the menus Contents of CSM The contents are reduced to 3 pages General Software versions and Quality items The group names itself are not shown anywhere in the CSM menu General e Set Type This information is very helpful for a helpdesk workshop as reference for further diagnosis In this way it is not necessary for the customer to look at the rear of the TV set Note that if an NVM is replaced or is initialized after corruption this set type has to be re written to NVM ComPair will foresee in a possibility to do this Production Code Displays the production code the serial number of the TV Note that if an NVM is replaced or is initialized after corruption this production code has to be re written to NVM ComPair will foresee a in possibility to do this e Installed date Indicates the date of the first installation of the TV This date is acquired via time extraction Options 1 Gives the option codes of option group 1 as set in SAM Service Alignment Mode Options 2 Gives the option codes of option group 2 as set in SAM Service Alignment Mode e 12NC SSB Gives an identification of the SSB as stored NVM Note th
240. F NO FPGA VDDA DAC 1 4 VDDA ADC VDDA LVDS RREF PNX85XX 3 3 5 a 1 2 85 1V2 STANDBY RX51001A 2V5 DDR1 VREF DDR1 AE20 BOSE PNX5100 LVDS 7 00 12C PNX5120EH M2 22 LVDS 1 05 BOSE 4VDISP1 SUPPLY 43V3 1V2 PNX5100 1V8 PNX5100 1V2 PNX5100 DDR PLL1 3V3 PNX5100 LVDS IN 1V2 PNX TREPLL1 1V2 PNX TRI PLL2 1V2 PNX TRI PLL3 1V2 PNX5100 DLL 3V3 PNX5100 DDR PLLO 1V2 PNX5100 LVDS PLL 3V3 PNX5100 LVDS PLL 1V2 PNX5100 CLOCK 3V3 PNX5100 CLOCK PNx5100 SDRAM PNX5100 DDR2 VREF CTRL 7 01 EDE5116AJBG 8E E 1V8 PNX5100 PNX5100 DDR2 VREF DDR 7 02 EDES116AJBG 8E E 1V8 PNX5100 PNX5100 DDR2 VREF DDR USB_DM USB DP USB RPU USB VBUS 3V3 PER 1V8 PMNX85XX 5117494 USB CONNECTOR 5V 8 S 1P07 lt lt 938 06 20 USB20 DM CONNECTOR SIDE USB20 DP gt SW UPLOAD JPEG 3H37 MP3 48V3 PER 3 45 La 3 3 PNX8543 FLASH 7P10 NANDO1GW3B2BN6F 3V3 NAND PNX8543 SDRAM 3HJ5 41V8 PNX85XX DDR2 VREF CTRL 7HGO EDE1116AEBG 41V8 PNX85XX DDR2 VREF DDR 7HG1 EDE1116AEBG 41V8 PNX85XX DDR2 VREF DDR 18310 402 090305 5 090324 2009 Ma
241. FE74 D13 7E02 98 5 5 218 FE75 2E7312 FE75 D13 7aHC4053PW _ 23_ ST e a D FE76 E7 L FE63 8 M X 6 7 5 9 2 75 D1 FE77 F7 EU 2E77 C2 FE78 F7 1 04 1 AV2 STATUS FE64 L ll L a es 14 1 8 to 2E82 C7 FET9 F7 212 amp 4 2E87 A13 FE80 D13 G EET al an 9 zl 9 1 2 2 88 12 FE81 E13 FE6S 10 ETT 5 els 12 2 90 12 FE82 E13 15 1 2 Y_EVBS MON OUT SC 8 EU 25 E epee NTS 2E91 C12 FE83 F13 2 1 96 i 2 e Hi 8 33 2 4 FE84 F13 L 0 2EA5 A3 FE85 F13 ica ica t LI 2 L is L 1 3E02 06 4 3 13 15 E 1 B3 X d E Vss FES7 36 P 3E12 A11 1 06 H6 e SAVE tle gS off 14 6 1 09 H11 L gece gees Pd 16 s 3E15 B11 1 14 4 lt I 3E16 D6 IE16 5 7 e 17 35 dE 18 17 5 IE17 F5 4 1 1 L 8308 8 18 5 IE18 010 _ 25_ 8 3E19 C11 1 20 5 9E33 Hd 19 9 3E21 5 1 21 5 Aoc 3E22 C11 1E22 A11 RES FE78 1E17 20 z S FEES e F 3E24 A5 1 23 C11 EN lt MT 505H 01 NI LF 3E27 B11 1E48 H11 FE79 __ 28 011 1 51 5 gece ele et 8 off 3E30 B11
242. FT SPEAKER 01 12 BO1B 45V 1x AV1 BLK 1x CA IORD BO4H 1x DDC SDA BO6B 1x EJTAG TMS BO1B 2x LIGHT SENSOR B01C 12V BO1C 45V 1x AV1 BLK BO7H 1x CA IORD BO7D 1x DDC SDA BO4E 2x EJTAG TRSTN BO4A 1x LIGHT SENSOR 12 B04A 45V BO8D 1 AV1 BLK 1x CA IOWR DDR2 A0 06 1x EJTAG TRSTN 2x M66EN 8068 12V 5V 1x AV1 BLK BO BO7H 1x CA IOWR DDR2 A1 BO1B 1 ENABLE 3V3 4x MDOO 06 12 BO6A 5V BO8D 1 AV1 BLK BO BOAN 1x CA MDIO DDR2 A10 2x ENABLE 3V3 4x MDO1 B07B 12V B07C 45V 1x AV1 CVBS 1x CA MDIO DDR2 A11 1 ENABLE 3V3 5V 4x MDO2 BO7H 12V B07D 45V BO8D AV1 CVBS BOAN 1x CA MDI1 DDR2 A12 BO1B 1x ENABLE 3V3 5V 4x MDO3 B08B 12V 5V 1x AVI G 1x CA MDI1 DDR2 A2 01 1 ENABLE 3V3 5V 4x MDO4 8098 12V 5V BO8D AV1 G BOAN 1x CA MDI2 DDR2 A3 ERX DDC SCL 4x MDO5 01 12VD BosD 5V BO4K 1x AV1 PB 1x CA MDI2 DDR2 A4 ERX DDC SDA 4x MDO6 BOSH 12VD B09A 45V BO8D 2x AV1 PB BOAN 1x CA MDI3 DDR2 A5 ERX HOTPLUG 4x MDO7 12VF BO1C 5V5 TUN BO4K 1x AV1 PR
243. FU21 S 7040 1 e 5 S lt g sx 3 0A T 32V FU40 L 8 lt o 326526 7U0Q en e UD Em BC847BPN COL 1 259 BS BC847BW pe AUDIO POWER 2 i g 325 4529 te Nel NM lt lt 11 o 2 8 1044 3L 1036 4 8 L 5 1039 1 1735446 1 1V2 STANDBY aTe 7U41 2 3062 ENABLE 3V3 ate e BC847BS COL ast 278 F 3088 3089 1047 1045 4 22K F VN IN CASE ONLY ANALOG TUNER 318 518815815 7 2KS 7041 1 aTe BC847BS COL M er 1 2K9 supplies L CHN SETNAME CLASS_NO 2008 10 10 NAME Maelegheer Ingrid SUPERS 3 CHECK DATE 2007 11 20 ROYAL PHILIPS ELECTRONICS N V 2008 2009 May 08 8 9 10 11 12 13 18310 501 090302 eps 090302 SSB DC DC Circuit Diagrams and PWB Layouts Q549 2E LA 10 AN
244. FUO4 218 1007 8 2 20 TEST 6 ls gle b 2098 GND SIG T NC EE 2U617 8 3 2 S 8 2U63 3U24 R RES ase aye L PGND 2 3V3 42 1 2 5 8 GND SIG STI GND SIG 1062 33K Ba 2006 x s 28 1 3K3 8 tg J GND sIG 35 2 3 88 7 Gnosis 8 5 55 4 Boy 35 acs LES 4 1005 1006 2064 5 H 5 K A 3n3 8 3 1V2 STANDBY gle 25 Ps 58 GND SIG dos aut SENSE 1V2 PNX85XX 348 1208 1 L m 8 1 ase 5 8 52 5 8 3 9 8 8 58 2 8 8 wis M GND SIG GND SIG GND SIG GND SIG GND sIG GND SIG 1 08 REF HOLE VLA CHN SETNAME CLASS NO 2008 11 21 2008 10 10 NAME Maelegheer Ingrid SUPERS 3 DATE 2007 11 20 ROYAL PHILIPS ELECTRONICS 2008 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 18310 500 090302 5 090302 __ SSB DC DC Circuit Diagrams and PWB Layouts Q549 2E LA 10 LI 10 12 13
245. GND1 I IR LED PANEL 1316 HVR HVR TO DISPLAY Bota HVR 1 1319 Bob HVL Bota HVL TO DISPLAY 04 Bote 1V2 STANDBY 1V2 STANDBY gt 12 Bate ave 12VF1 7003 TPS53124PW 4 12 3 3 COVERSION 5001 43V3 7002 17 5003 04 12 1 2 COVERSION 1V2 PNX85XX 4 ee DC DC TY T PNX8543 AUDIO E 5100 CONTROL ob 4AUDIO POWER AUDIO POWER asia 12V 3V3 Bota 1 AUDIO VDD 4 1 PNX5100 PCI 12V 5V CONVERSION 33 373 Bota gt 5V5 TUN L e 5536 45V B01b B04a PNX8543 AUDIO E BHI PNX5100 DISPLAY INTERFACING B06a B07a c B08a b d 3V3F B09a d 3V3 Bola ita 12 2
246. HKL THSET N 2314 2 G11 46 G10 REF 2 pls D oii um 2HTGG11 80 5 2HTH D3 IH81 B5 PC3 2HT8 IHR6 ip ys vy FRONT Y 2HTK G3 1 85 B5 m Zn g lt y 27R 2HTL B2 IH87 D5 sc 2385 55 2HTP A8 IHPF A8 pr rame Nl AB h 1 2HTR 9 IHRO B8 33 2 10 10 133 Em S5 2HSP FRONT C F 2HTV C11 IHR3 C11 an 27R 2HTZ G8 IHR4 010 AUN Gq 3H34 2HU0 69 IHR5 08 ace Ht 18R 55 2HU5 IHR6 F9 AM H2 i 2HUB IHR8 G11 H3 IHRE els 2HUBH11 F4 L 44 280 2HUC H9 IHRC C10 T isn Et 1200 NM 2HUK E1 2 gle 2HUN G4 IHRE F8 a 2HTB 23 J ABI ST 2285 8 2 2 G4 10 J 25 RES 1 zn 12n o g 1R 3H29 C4 IHS2 2 ii G 2HSY fee 92 8 2 8 3H34 F9 IHS3 E1 2 5 3H40 G10 54 58 02 2HUN i 3H47 G11 IHS5 F4 5 2HTK ll Ud EE B VGA 3H79 4 IHS6 H11 BE 1 2 1200 o a 188 3H80 5 IHSA E3 a2 1 2 SET i 95 8 Eg 3H81 4 IHSB E1 579 SOLES 3 82 5 5
247. I GNT MINI 2x PNX5100 DDR2 D27 8080 4x RXD UP BOSE 3x TX1A 1x TXCLK BO7H 1x PCI AD24 2x PCI IRDY 2x PNX5100 DDR2 D28 BO4E 2x SCL1 BOSE 3x 1 BOBD 3x TXD 1x 24 8056 1 PCI IRDY 2x PNX5100 DDR2 D29 3x SCL2 BOSE 3x TX1B BOSE 1x TXDAT BO4F 1x PCI AD25 BO7G 1x PCI IRDY 2x PNX5100 DDR2 D3 BOE 2x SCL3 BOSE 3x TX1B 1x TXDAT 18310 701 090309 eps 3104 313 6343 2 090309 2009 May 08 KN PEN 137 Q549 2E LA Circuit Diagrams and PWB Layouts Layout Small Signal Board Top Side gent Es Ez Bs fp 51P101 RU
248. I HDCP key Indicates if the HDMI keys HDCP keys are valid or not In case these keys are not valid and the customer wants to make use of the HDMI functionality the SSB has to be replaced Ethernet MAC address Displays the MAC address present in the SSB Wireless MAC address Displays the wireless MAC address to support the Wi Fi functionality BDS key Indicates if the BDS level 1 key is valid or not e CI slot present If the common interface module is detected the result will be YES or NO HDMI input format The detected input format of the HDMI HDMI audio input stream The HDMI audio input stream is displayed present not present e HDMI video input stream The HDMI video input stream is displayed present not present How to Exit CSM Press MENU or HOME Back key the RC transmitter 2009 May 08 5 549 2 Service Modes Error Codes and Fault Finding 5 3 Stepwise Start up When the TV is in a protection state due to an error detected by stand by software error blinking is displayed and SDM is activated via shortcutting the pins on the SSB the TV starts up until it reaches the situation just before protection So this is a kind of automatic stepwise start up In combination with the start up diagrams below you can see which supplies are present at a certain moment Important to know is that if e g mode with a faulty FET 7U08 is done you can destro
249. IE91 H1 2 AVEPR V _9 19_ 85 99 E 3E31 D11 1 92 2 88 8 5 gt 3E32 E11 1E93 12 5 3E34 C5 1E94 J 55 3E37 11 1 96 2 45 it 9E27 ale 3E38 F11 1 97 D3 z3 ay ATE 3E43 H12 1 98 C2 58 8 3 44 H11 IECO RES sno 2 E 51 5 IEC2 AV1 BLK BO 22 9 20 i l 88 gt lt ae 3E52 15 IEC3 B2 7 abi um zm K 5 8 SR 218 EU 59 111 28 als _ 3E61 H6 955 x 8 wos ure 3E62 16 Js 548 58686 3E63 1068 NAV2 BLK 3 1 ice 3E64 Be 9 151 7 cl 3E68 7E05 Y 1 AV1 BLK lt 3 BC847BW 4 4 CVBS OUT SCt BCedyBW 3E69 6 L 2 5 H 2E7365 sce gl S gt gf BC8478W 3E99 C2 8 8 l PESOS al 2 5 7 3 else 8 Felip 7 3EA9 A2 8 1 0 2 6 1 AV1 CVBS zl 3EB7 H2 y 8 12 S8 2 3EB9 ag zl E ie 85 ease 8 3 8 ils sls sts sf Bice 6 01 12 273 8 8 mE 2578 Hoos 8 7 6 02 6 5 8 8 Biz L 1 1 l l 45 6E08 B6 x CVBS OUT SC1 Sa ee 68R E 218 6 10 6 8 E 218 4 ER 6E1
250. INOU 3V3 ge 3V3 ET ANA INON 2 8 8 3 8 4 5 5 2 2 7 04 2 220R n DP83816AVNG 5 5 n Snot 3e 27 278 a NC2 zls 37 124 8 8 55 SX ee 23 NC4 NC9 56 NC5 10 Le xL 10 11 12 13 1 00 A11 1N02 C8 2 D8 2NOL D8 2NOM D3 2NON H4 2NOP G10 2N0Q G10 2NOR AQ 2 05 C8 2NOT B10 2NOU B9 2NOV H10 2NOW H10 2NOY G12 2 02 G13 2N10 G12 2N11 G12 2N12 G12 2N13 G11 2N14 G12 2N15 G11 2N16 G11 2N17 G11 2N1C H3 3NOF C7 3N0G D3 3NOH C7 3N0J 3NOK F8 3NOL 1 8 3NOL 2 A9 3NOL 3 A8 3NOL 4 8 3NON 1 AQ 3NON 2 AQ 3NON 3 AQ 3NON 4 AQ 3NOT 1 B9 3NOT 2 B9 3NOT 3 C9 3NOT 4 C9 3NOV C8 3NOW 3NOY D1 5 06 G10 5N07 H10 6 00 F8 6N01 F8 7 04 1 B3 7 04 2 H7 A10 BNOB B10 BNOC B10 BNOD B10 05 A10 A10 FN07 B10 B11 FNO9 C11 FNOA 9 FNOB F9 FNOC D3 FN15 B10 INOK E7 INOL G10 INOM C7 INON H3 9 INOT C8 INOU H10 INOV C8 INOW E7 INOY F7 INOZ F7 IN10 F8 IPOH B10 IPOJ D1 CHN SETNAME UFD 2 8 2 DIGI TV543 R2 LDIPNX 8204 000 8934 9 10 gt 11 2009 May 08 12 13 14 15 16 17 18 19 20 18310 540 090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA GEJ SSB Buffering i 4 gt 8 9 10 11
251. IPS 9E35 2 RXD BEB7 SEAT 1 78 2 a BO B 2EA3 407 1 4 1 10 IN2 INA 20 5 2 9 lt 2 9 FE44 E5 _ gt PT um ais 8686 9 lon 19 aS 2ECD 19 FE45 E5 L DEBUG RS232 INTERFACE PMEGIO20EA TXD MIPS _9 6_ 3 nm a a 383 2 12 47 C1 E BO G 8 18 S AV1 Y CVBS LL ST3232C 16 02 04 gt 2 5 FE57 F5 3E00 G3 FE92 D5 F 2 E AV1 G 2 6 407 1 7 T 17 SEE CZ pases F 2E60 Boy Roy Rox Soy 5 15 189 2 6 3E09 2 FE94 5 00n v ac AVI 1 a AV CVBS 3E23 H2 FE95 B1 3 5 5 GND VSS ie 100 2 61 mot met BOY OOF 9 15 FE96 F4 D 2E63 2 29 A D 4 10 1 1 1 40 2 FE97 F4 12 lrg SESTMS FEAS H10 c2 LEVEL BEB4 AV1 PB 3E67 G2 6 10 1 50 FEBO 92 1 3E83 H3 FEA7 H10 TXD UP 9 03 11 14 5 e 1 G 7 FE93 BEB2 FE94 t 2 UP SHIFTED AV1 PR nH G 3 E82 13 4 3E86 FEBO 10 TXD MIPS 8 RN L ES FOR as 3E87 H5 FEB1 H9 3E88 G14 FEBAH2 RXD MIPS o 1 51 s DEBUG 3 M 3E91 F2 FEBS 110 E 45 BEBO 2 MIPS uo IEAB E 2 1E84 3 U
252. IR 3HH3 DDR2 D12 7 DDR2 A9 9 Pm IR 7 DDR2 D28 3HJ1 11 38 DDR2 A10 2 12 D9 SHAS 0082 013 DDR2 A10 4 0 13 09 ELA Ed DDR2 D29 3HJ2 B11 2 DDR2 A11 P7 1481 33R 5 DDR2 D14 DDR2 A11 5 P7 n 1481 33R SHHT DDR2 D27 8 DDR2 A12 R2 Pm 3HH6 DDR2 D15 DDR2 A12 R25 Pm 3HHU DDR2 D31 3HJ3 A13 3HKM RES RES 3HJ4 B13 82 DDR2 CLK P 2208 2 2 S 2208 DDR2 DQM3 3HJ5 C8 258 N UDM ES DDR2 CLK_N 5 LOM 83 2 DDR2 DQM0 s DDR2 CLK i K8 CK LDM LIS DDR2 DQM2 3HJY C8 0082 0050 P F7 J2 T T DDR2 DQS2 P F7 J2 4 T 3HKM G3 NES N 1 2 REF DOR DDR2 DQS2 33R 4 1 9 DOR 3HKN G10 33R 100 100 7H00 2 A7 1 B7 0082 0053 P 3HHV B7 7HGO F5 H SR 3HHE A8 d DDR2 DQS3 N 33R SHAW 8 5 7HG1 F11 2 9 2 vssa vss vssa 06 A12 S SEES CHN SETNAME 8204 000 8927 2008 11 21 E DDR2 INTERFACE PNX8543 TV543 R2 LDIPNX E DATE ROYAL PHILIPS ELECTRONICS N V 2005 agre 2009 May 08 12 13 14 15 16 17 18 20 18310 509 090
253. ME Maelegheer Ingrid SUPERS 16 CHECK DATE 2007 11 29 ROYAL PHILIPS ELECTRONICS N V 2005 1 2 3 4 5 6 7 8 9 10 11 12 13 18310 510 090302 5 090302 2009 08 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner Circuit Diagrams and PWB Layouts Q549 2E LA LII SSB PNX8543 Audio 1 2 3 12 13 14 15 16 17 18 19 20 11 12 13 2HM1 G5 2HM2 H5 EBEN PNX 8543 AUDIO AUDIO POWER pe _9 _ 7HMS BC807 25W 2 3 487 BZX384 C6VB t4 2 3HM1 10K x 1 IHM8 x 23HM0 27 g3HM0 1 4 gu y Dried 7HM6 4 N 22K 5 53 0 4 22K 1H22 IHNO ADAC Aue 2 7HM2 1 X BCBABS COL IHNG gt AUDIO VDD AUDIO VDD 3HMY o AUDIO L 1H23 IHNA ADAC 2 puy 5 7HM2 2 X BC847BS COL AUDIO VDD 9 2 BC857BW 1 7 4 IHNF 3HMW 3 IHNH IHMG 3HMU AUDIO R 3HMB 470R AUDIO VDD 2HMJ FHR3 100n 7HM1 1 IHMW ADAC s m LM324 4 AUDIO CL L IHMV 2 23HME 27 g3HME 1 33p AUDIO VDD 4 ADAC 5 v IHNG 6 7HM1 2 LM324 7 L i 40K B 2HMP
254. MS 338 sci 233 x 4 il AA SHPB lt EJTAG TRSTN EJTAG TRSTN S RSTN SpA 3 992 lt gt SDA3 58 10K SHEY BOOTMODE x 92 cpio o USB20 DDM x i H42 WC EEPROM PNX5100 U3 GPIO_1 IRO PCL IRQ PCI gt mrri 2 43V3 PER 10 SHPB HET L34 10K 2 RXD MIPS RXD MIPS 132 N16 USB20 DM USB20 DP gt tag VV GPIO_4 DM 7 TXD MIPS TXD MIPS L31 5 pp AP16 USB20 DP JL he 2 6 usB FAULT AEE USB OC 1 iNES CPIO7 PWR_ENT nite 3HP2 FH03 8 RREF 22 GPIO_9 12K 1 3V3 PER gu 10K A3HPP TXD MIPS2 N TXD MIPS2 lt 27 TX 10 A ASHER 5 RXD MIPS2 RXD MIPS2 127 UA2 RX USB_RPU AM17 3H37 AAS 1 5 lt q 3V3 PER E USB ip AP17 3H38 PCI CLK OUT AP29 LK 27 our 3H45 4 3V3 PER n Ss SCL UP MIPS SCL UP MIPS mite 6 3 3 1008 PE 2s SDA UP MIPS NAA vv A SHPF RES 100R Nesa 2 dcs gs 22 SDA UP MIPS 100R 3HPH FH04 3HPK gt AAN SCLSSB MSCLSSB _ e 3 100R FHOS 1 5 Nespas 2 VN SDA SSB MSDA SSB gt e MM 100R IKS 3HPS 3HPT SscL2 y ANA SCL SEL MSCL SET e 44 3V
255. NA RESET SYSTEM A26 BACKLIGHFPWNANADISP gt gt KEYBOARD AV1 BLK 7CG8 gt gt RESET AUDIO 45V BOOST CTRL BACKLIGHT BOOST AV2 BLK s gt gt Hl gt gt gt gt AUDIO MUTE AVI STATUS gt gt gt 1 99 BACKLIGHT CTRL opaa LAMPON SS ee eee 86 gt gt ENABLE 3V3 BACKLIGHT OUT TO FPGA WOW 10 d 43V3 STANDBY 7HDO SYS E ANDEV gt gt gt gt POWER 7FNO NCP303LSN30G REGIMBEAU_CVBS SWITCH Ez BACKLIGHEBOOST SUPPLY EP3C25F324C7N 8 POWEROK ETE BACKLIGHT CONTROL EPGA IN RESET PNX5100 a BACKLIGHT PWM ANA DISP F18 7 CLK OUT PNX5100 gt gt Bi EH eee 1 95 Ed FPGA Wow DDR STANDBY 7HC3 SUPPLY EDD1216AJTA 1 M24C64 WDW6P dz 7HC4 7P32 3 CEC HDMI RESETNVM 8 conTROL gt i 7P02 A TO PIN 1 04 13 DASS 1P03 13 __ 57 1P02 13 4 MM1 CLK 4 45 1 46 1 05 13 7H02 igs pu IE M25P05 AVMNGP 3 FPGA WOW POWER amp COTROL 1Po4 15 ABXDDC SCL 7P10 15 BRX DDC SCL NANDO1GW3B2BN6F CRX DDC SCL SPLWP ASDO 4x HDMI 1P02 15 1 7 gt CONNECTOR 1 05 15 DRX DDC SCL SPI CSB DCLK SPLSDO gt gt gt HOTPLUG A gt 5 lt lt SPI SDI lt DAM lt 18310 404 090305 eps 090327 2009
256. ND 8735 INLET AMBI LIGHT MODULE 3 3 1073 1M84 SPI CLOCK BUF SPI DATA OUT j SPLDATA RETURN SPLLATCH PWM CLOCK BUF 43V3 BLANK BU EEPROM CS 8101 LCD DISPLAY 9 4VSND 13 VLED2 12 12 GND 11 VLED1 6 12V 10 PROG TEMP SENSOR j EEPROM CS BLANK BUF 3V3 PWM CLOCK BUF SPI LATCHICONN SPI DATA RETURN SPI CLOCK BUF SPI LATCH2CONN 1650 5 40 TXDAT 39 TXDAT 3 TX2E 2 SCL DISP 1 SDA DISP 1G51 5 51 N C 50 SDA DISP 49 SCL DISP 3 2 1 4VDISP1 1 20 8018 KEYBOARD j LED1 1M95 B018 11 N C 10 GND AUDIO POWER 12V 12V GND GND GND STANDBY 3V3 STANDBY 1 99 12 GND 11 SDA SET 10 SCL SET POWER OK BACKLIGHT PWM BACKLIGHT BOOST BACKLIGHT OUT LAMP ON OUT 8802 1 59 06A SCL AMBI 3V3 1 GND AUDIO 4 RIGHT SPEAKER 2 GND AUDIO 1 LEFT SPEAKER 1735 8104 PWM CLOCK BUF i SPHDATA RETURN SPI DATA OUT SPI CLOCK BUF TO AMBI LIGHT MODULE 3 3 1075 AL 1M83 14 GND 13 VLED2 12 GND 11 VLED1 10 PROG TEMP SENSOR EEPROM CS GND 343 CONTROL 2 1 84 14 GND 13 VLED2 12 GND 41 VLED1 10 PROG TEMP SENSOR EEPROM CS BLANK BU 33
257. NIDINIDO 7 F5 WR 2 9 FF08 B6 ps m REM 10_Lospivs2 45 2F40 F13 FF09 89 LO4P GCLK8B 10 LOBN VS1 49 IF17 D 2F41 G13 FF10 A3 ele IP_LO4NIGCLK9 10_LogP vso 50 3F09 2 42 G13 11 6 is 1 L 8 22 _ FOS 3F18 5 lo CC TNNT SCL SET 2F46 C13 FF12 F7 82 IP_LOSP RDWR_B GCLKO 5 EE 9F03 J 9F00 WOR 2F47 C13 FF13 G5 105 2 9 eme TR 4 7 5 8 2248 C14 14 64 G gt KO RES 2 49 FF15 6 5 4 LUC Ll 2 16 6 SCL SSB x 1008 3 4 5 3 BL CLK A 2 FF17 SDA SSB em E 56 oma ATE NN WR 2FNDF11 20 14 eo 1F32 at AM ELS F11 FF21 C14 BL SCK 133 60 IC LOSP RHCLKO veco 45 3F00 1 13 FF22 14 BLWS 610 1038 2 1253 3F00 2 12 FF23 F14 LO3N RHCLK1 3F20 Eee 10_LO4P RHCLK2 A BL MOSI _ 5n E 3F00 3 H2 FF24 F14 SERLDUITSTCHSUKGKT 82 65 10 104 _1 1 _ 36 1008 3 00 4 2 25 14 p E IO LOSP RHCLK4 I0 LOIN 9 137 0 6 0112 FF30 G5 3F24 LIST E 67 10 LOSNIRHCLKS 10 102 ___ 3F02 H8 FF31 F14 3V3M IO LOGP RHCLKG
258. NY 2009 May 08 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2000 A12 2004 03 2013 2066 6 2083 G7 2U8E 10 2U8K 010 2U8T H6 2090 12 3U03 5 3008 03 3014 B6 3U2C 6 3U2H D9 3U3F E11 5U04 09 5U19 C11 6U01 D2 TUOD 2 C7 FU00 E2 FU87 D8 FU90 E5 1003 1010 D3 1016 C7 1U2A B6 lu2v C9 1U33 F8 A 2001 4 2005 02 2118 6 2067 C7 208 5 2U8F B12 208 D10 2U8U C8 3U00 C5 3U04 C3 3U10 E2 3U26 G9 3U2D H6 3U32 E6 3U3G F11 5U05 B9 5U30 A11 6U09 B11 TUOH 1 A6 FUOD F13 FU8B A14 1000 C4 1004 05 1013 03 1025 06 1U2C E5 1U2Y F9 1U82 C9 2U02 C4 2U08 6 2020 2080 C4 2U8C B10 2U8G D10 2080 9 2U8V C8 3U01 C5 3U05 C5 3U11E7 3U27 G10 3U2F F10 3U33 F8 3U3J B9 5U09 A11 5U31 A11 7U01 C3 TUOH 2 B6 FU80 B14 FU8C B8 1001 C3 1005 D3 1014 B6 1U28 C7 1U2D D5 1022 E9 1085 E9 _ 2003 02 2009 4 2U38 F8 2U81 C2 2U8D B10 2U8H 010 2U8R E9 2U8Y 3U02 C6 3U07 D2 3U12 3U28 C6 3U2G B8 3U3A B12 3U3N D9 5U18 B11 6U00 C5 7000 1 B7 CU25 G2 FU85 D14 FU8D B14 1002 C5 1009 1015 E6 1029 6 1U2T G7 1U32 D6 DC DC ird gt xar 5009 RES C A e n A 10u 5U30 RES D gle amid 3 2 51 1 ara A 4 1 ni 541 D 12V 5V CONVERSION all D 3 FU8D ge e ope 2066 Fusc 5005 5536 B 1014 1n0 e FR rH gt 5V ne P 2 10 2 6009 AJCI 2 3 5 8 5 5 48 4 Sut
259. O1 INV TACHO2 INV D 6 I 0 3F69 3F71 IF58 27K IF60 PDTA114EU 6 7 0 EU 3 IF61 TACHO1 TACHO2 1F01 A1 1F02 B1 2F50 B2 2F51 B2 2F52 B2 2F53 C2 2F54 C2 2F55 C2 2F56 E4 2F57 E4 2F58 B8 2F59 C8 2F60 E8 2F61 F8 3F50 E3 3F51 E2 3F52 E5 3F53 3F54 E4 3F55 E5 3F56 E2 3F57 F2 3F58 3F59 D2 3F60 A7 3F61 B7 3F62 B7 3F63 C8 3F64 C9 3F65 B9 3F66 D7 3F67 D7 3F68 E8 3F69 E8 3F70 6 F8 3F72 F8 3F73 F8 6F50 B7 6F51 D2 7F50 B7 7F51 C8 7F52 D3 7F53 4 7F54 D9 7F55 7F56 F9 7F57 F6 9F07 F6 9F50 B8 9F51 B9 9F52 C9 FF49 A2 FF50 A3 FF51 B3 FF52 C3 FF53 C3 IF50 D2 IF51 IF52 E3 IF53 4 1254 E5 IF55 F2 56 IF57 E8 IF58 E8 IF59 6 IF60 F8 IF61 F8 62 B8 IF63 B7 64 B9 IF65 B7 66 B9 67 E4 IF68 D7 IF69 D7 CHN SETNAME CLASS NO TEMPERATURE amp FAN CONTROL TV543 R2 LDIPNX 2008 10 10 8204 000 8933 2008 11 21 NAME Maelegheer Ingrid SUPERS CHECK DATE 2007 12 04 ROYAL PHILIPS ELECTRONICS 2007 2009 May 08 8 9 10 11 12 13 18310 529 090303 eps 090303 Circuit Diagrams and PWB Layouts Q549 2E LA SSB FPGA WOW LVDS In Out i 1 3 1224 5 6 4 5 19 1F51 B9 l 5FG2E8
260. PHD38NO2LT N 4 330p e 2A25 100 2 26 1u0 p 2 5 1406 15 22K 1u0 2A13 2A14 1u0 2A27 RES 22u 6 3V 20 AKT RES 7A03 TS431AI Res 5 Q RES 3A23 4 FA06 3422 eV 1 07 4 24 22K 3A25 1K01 RES RES 100n 7A02 PHD38NO2LT E 3V3F 0 2 28 1u0 2A29 1u0 330p 16 VV 3A18 AA FA03 FA02 22R IA13 1V8 PNX85XX 1 11 1 0 100 2 23 2 24 100 RES 2A30 22u 6 3V 2 11 5 2 12 5 2 13 6 2 14 6 2 15 4 2 16 4 2 19 5 2 20 4 2 21 5 2A22 C1 2A23 E6 2A24 E6 2A25 AT 2A26 A7 2A27 B7 2A28 D7 2A29 D7 2A30 E7 2 0 E1 3A07 C1 3A08 A3 3A09 A3 3A10 B3 3A11 A3 3A12 A4 3A13 A6 3A14 B5 3A15 B5 3A16 E5 3A17 B5 3A18 E6 3A19 D6 3A20 C3 3A21 C3 3A22 C4 3A23 C5 3A24 D4 3A25 D4 3A26 A1 3A27 A1 3ACO E1 5AC1E2 5AC2 E2 4 6A01 E7 7A00 1 A5 7A00 2 D5 7A01 A6 7A02 D7 7A03 D3 7A07 A1 01 6 02 6 E6 04 1 06 4 1A01 B3 1 02 4 1 03 5 1A04 5 1 05 1 06 B5 1 07 04 1 08 03 1 09 E5 1A10 C1 1A11 E5 1A12 E7 1A13 6 1 2 1 1 4 1 CHN
261. PIO EJTAG LOOK AUDIO IN gt AUDIO OUT Pin Configuration ball A1 indexarea 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 1113 15 17 19 21 23 25 00000000000000000000000000 D 00000000000000000000000000 E 00000000000000000000000000 F 00000 00000 00000 H 00000 51 J 00000 00000 K 00000 00000 L p 00000 000000 00000 00000 00000 T 00000 000000 00000 V 00000 00000 W 00000 00000 Y 00000 00000 00000 00000 AB 00000000000000000000000000 AC 00000000000000000000000000 AD 00000000000000000000000000 00000000000000000000000000 Transparent top view 18560_300_090403 eps 090403 Figure 8 4 Internal block diagram and pin configuration Data Sheets Q549 2E LA EM 8 5 Diagram SSB Ethernet B07G DP83816 IC7N04 Block Diagram Pin Configuration e X lt lt lt lt 55 lt lt lt lt 8 X8 32328 22 2228 PEET EEEE EET 88098 4888 8999 233 9 99885582955882 5 9228002280090253 TPRDP M gt gt
262. PNX8543 Stand by Controller B04A PNX8543 IC7H00 Block Diagram PNX8543x MEMORY CONTROLLER TS in from channel decoder MPEG SYSTEM LVDS for TS out in for E PROCESSOR PRIMARY flat panel display PCMCIA LVDS single or dual channel DV ITU 656 gt DV INPUT AV PIP SUB PICTURE CVBS Y C DECODER 3D COMB RGB SECONDARY VIDEO ENDE analog CVBS OUTPUT Low IF DIGITAL IF MPEG H 264 VIDEO SCALER DECODER DE INTERLACE AND NOISE REDUCTION AUDIO DEMOD i AND DECODE AUDIO DACS analog audio AUDIO DSP Dual SPDIF 25 AUDIO OUT Ps SPDIF 300 MHz AV DSP DRAWING ENGINE DMA BLOCK D GPIO Flash USB2 0 PCI2 2 x 10 Dual HDMI RECEIVER SYSTEM CONTROLLER 8051 300 MHz MIPS32 4KEc CPU EI ADC SPI PWM GPIO UART x 22 Pin Configuration ball 1 index area 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 13 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 A B G H 000000 J 00
263. PNXS100 DDR2 D29 7 00 8 A6 PNXS100 DDR2 A12 lt 12 14181 338 4 5 3009 4 PNXS100 DDR2 D14 N PNXS100 DDR2 A12 lt RZ 1481 8 AA PNXS100 DDR2 D30 TCO B9 3C082 7 2 33R PNX5100 DDR2 D15 3004 B9 30302 7 2 33 PNXS100 DDR2 D31 21 PNXS100 DDR2 CLK P J8 15 4338 PNXS100 DDR2 CLK 180R J8 16 7 02 F9 PNXS100 DDRZ CLK 83 5 4 5100 2 1 PNX5100 DDR2 CLK_N_ lt 83 PNX5100 DDR2 DQM3 05 B11 3603 3 8 Kans BR gt _PNX5100 DDR2 DQMO 7 F 30252 6 43 IR 2 PNX5100 DDR2 DQM2 FC06 B9 V E 7 3 3627 36 m 5100 0082 0080 iR 3 F7 aan 3005 3 5100 0082 0052 33R 1 04 C2 M PNXS100 DDR2 DQSO N 3C064 4 5 vnEr 2 14 PNX5100 DDR2 VREF DDR PNX5100 DDR2 DQS2 N 25 4 5 E8 LDQs VREF 22 4 PNX5100 DDR2 VREF DDR M 33R 3ci2 2C40 3 27 4 4 2039 DDR2 DDR2 4505946 B7 ENXS100 DDR2 DOS1 P acu Br M 3 8 VVV A8 ubas ENXS100 DDR2 DQS1 N KA BR AB _ UDQS Ae PNX5100 DDR2 DQS3 A 8 100 vss vssa 3030 3 33R vss 2 vssa REF EMG HOLE CHN SETNAME CLASS NO 2 2008 11 21 DDR2 5100 2008 00 00 Maelegheer Ingrid SUPERS 9 130 1 A2 CHECK DATE ROYAL PHILIPS ELECTRONICS 2008 1 2 3 4 5 6
264. Positions due to the different set executions 4 3 Assy Panel Removal 4 4 Set Re assembly 41 Cable Dressing and Taping 18310_210_090318 eps 090318 Figure 4 1 Cable dressing 32 2009 May 08 Mechanical Instructions Q549 2E LA EN 11 18310_211_090318 eps 090318 Figure 4 2 Cable dressing 37 18311_200_090506 eps 090506 Figure 4 3 Cable dressing 56 21 9 2009 May 08 4 2 4 2 1 4 3 4 3 1 4 3 2 Q549 2E LA Service Positions For easy servicing of this set there are a few possibilities created e The buffers from the packaging e Foam bars created for Service Foam Bars 06532 018 eps Figure 4 4 Foam bars The foam bars order code 3122 785 90580 for two pieces can be used for all types and sizes of Flat TVs See Figure 4 4 for details Sets with a display of 42 and larger require four foam bars 1 Ensure that the foam bars are always supporting the cabinet and never only the display Caution Failure to follow these guidelines can seriously damage the display By laying the TV face down on the ESD protective foam bars a stable situation is created to perform measurements and alignments By placing a mirror under the TV you can monitor the screen Assy Panel Removal Rear Cover Warning Disconnect the mains power cord before you remove the rear cover Note it is not necessary to remove the stand while removing the rear cover Removi
265. Q549 2E LA ES LIN Block Diagram Control amp Clock Signals CONTROL CLOCK SIGNALS 4 ETHERNET Eres FRONT END 7HOO PNX85439EH M2 7303 IBO4N DRX3926K XK A3_ 7 04 Lo 1N00 DP83816AVNGNOPB 1 00 lt CA MICLK lt 50 2 FE CLK 7 15 7 16 RD ETHERNET VS2 lt RESET SYSTEM CONNECTOR gt gt RESET ETHERNET 555 gt TX852CLK gt BUFFERING 5 TX851CLK PCMCIA gt CA DATADIR 031 TX851CLK gt 61 IRO PCI CA DATAEN A31 CONDITIONAL PNX8543 SDRAM ACCESS MINI PCI CONNECTOR pues CA ADDEN a DDR2 CLK P RESET mPCI IRO PCI 7 lt DDR2 CLK N Mili PE CONNECTOR 8543 FLASH FOR WIFI PANEL lt lt _PC1 GNTMIN lt lt PCHONTB PNx8543 CONTROL PNX5100 CONTROL 3HFG PCI CLK OUT 9 g
266. R42P A MSELO IFNK 10_H14 R8NJAVD_ H57 COND VREF FPGA1 12_ 12 7 1 10_AM6 T41NIPADD1 gt 1O_B7 T19P DATA4 10_R18 VREFB5N3 10_P18 R42N 7 sf Jig 5 10 DIZIRIZPIOE RES lt TIARN VREF FPGA1 11 0_C12 VREFB7N2 10 E12 TA5PIPADDO lt MMI DT VREF FPGA1 ES 10_D7 VREFB8N2 10_A7 T19N PADD18 10_T17 R54N gt FRM i7 10_D18 R12N WE_ lt VREF FPGA1 pp a 10 E11 VREFB7N3 10_Ata T4gp gt sa MT VREF FPGA1 pe 34 10_E6 VREFB8N3 10_B8 T20P DATA3 1 lo 17 829 1O_N15 R55P MSEL2 H16 R23N HIS DU IO D16 T49P 1O ABIT20NIDATA2 lt H MIXO518 lO K18 R29N 10 Tte 118 55 1 214 _ 17_ _SENB_RES BACKLIGHT OUT A MMI A2 510 DIOITZTPIPADD14 1O CTG T49N DE DSIT3PIDATA12 2 17 MMtDOSO I L17 R32P DEV IO TI6 RUP3 8 10 E18 R24N CEO _ Em NC E CONT 210 0 10 27 1 10_E14 RUP4 eee IW E 58 JIO 10 C9 T24N PADD16 lO 18 832 OE 10_R16 RDN3 IGHT OUT2 Fig O B7IVREFBGNO I0_G17 R27P CRC_ERROR apne 6 MMIAT EST 0 11 29 12 IO E13 RDN4 E19 AS 10 E10 T25PIPADD15 CON
267. Refer to figure Figure 7 3 for the power architecture of this platform 12VDisp AS V display SSB LCD Power on 3V3 stby 1V2 STANDBY M Inverter DODC Enable3V3 Undervoltage Switches off detect 3V3and r 5 8 1V8 PNX85XX gt Detect2 gt 8 12V sense voltage ref 8 1V8 PNX5100 Boost cony opt TUS present in inverterless displays present in displays with internal inverte V inverter 4kV V backlight 24 V 18310 202 090317 eps 090317 Figure 7 3 Power Architecture 543 92 platform 7 2 1 Power Supply Unit 7 2 2 Diversity All power supplies are a black box for Service When defective Below find an overview of the different PSUs that are used a new board must be ordered and the defective one must be returned unless the main fuse of the board is broken Always Table 7 1 Supply diversity replace a defective fuse with one with the correct specifications This part is available in the regular market Supplier PSU Model Input Voltage Range Consult the Service website for the order codes of the boards TET Tigh Mains 106 265 Vac Delta DPS 298CP A 37 High Mains 198 265 Vac In the TV543 Elite Core platform for sets up to and including Delta DPS 411AP 3A 56 High
268. Res E 98 5 30R 8 28 amp a 1028 ue in AA 5 5 SM RES 3U01 P 3 5 4 _ 2 8 8 3 10R 929 2067 1001 1002 2 0 2002 2 5 2 WF 325 12 3 aie F a GND SIG1 82 1008 8 8 5 3 5 4 Le 1U03 S8 575 37 8 a 5 1 2 2 8 L VIN g 8 104 8 5 8 prvi 28 ee 12V 1V2 CONVERSION DRVL1 a 1 9 1 15 3 DRVH2 gt G DRVL2 3u07 1005 5004 GND SIG1 AN 2 Y FUSS o We 1V2 PNX5100 D 20K BATSACOL 1010 i 2 10u P pos 4 4V2 PNX5100 4 gg ENABLE3VESV lt lt 6001 RES 12 leno vest 5 41020 BSN 328 3u08 1013 5 PERS 88 4 AMR oc 3U32 1 a 8 RIR 18 I H S GND SIG1 18 21 2 22 Sg VSFILT VREGS AKT 5 9 8 2 8 EE 8 1 2 2 9 ou 2 GND SIG1 2 resr NC 5 5 3 tit ele 15 555 5 3 2018 vey E zh PGND 5 E 5V5 TUN ge 528 zio 9 GND SIG1 GND SIG1 Ll 1460 22K 9 5 2 4 290 GND SIG1 2 c 1009 GND SIG1 m HE es FP 2 SENSE 1V2 PNX5100 3 2 J F 1033 1208 1 J 25 ir SA 825 82 8 Sc T 8
269. S 3H27 DETECT1 DETECT IHWG AD4 P2 ELI 3H31 D1 IHW6 4 RES 10K 2 mz AA S DETECT2 DETECT2 AD3 2 5 7HO3 3H32 B11 IHW9 B4 10K _ 0 2 AES gt BOBEZBW p gt x ENABLE 3V3 ENABLE 3V3 9 3H36 D2 IHWA C5 3H39 C2 IHWB C4 RXD UP RXD UP 1 3H41 H6 IHWC C4 8V3 STANDBY 3H80 _ TXD UP i 0 1 UA TX 3H42 C1 IHWD C4 10 RES BOLT ONIO 2 BS LAMP ON 3H43 H7 IHWF C5 4 BOLT ON40 2 M25PO5 AVMNG RES D 10k eros AH2 4 1H00 1 4 LAMP ON OUT D 3H44 14 IHWG C4 5 SPI SDO_ 3H46 C2 IHWH C4 3H amp 4 RES 1H03 512K 3H48 C1 IHWM D4 BEBETSNSTEM RESET SYSTEM gt ANS lo SPI CLK FLASH 3 51 C2 IHWN 05 10K V2 BLK 55 AN2 3 52 113 VI BLK 2 SPLCSB talg auro KEYBOARD lt 3 1H07 3 H 2 SPLWP 3 lw 3H54 C7 G 1 2 1 AVI STATUS AQ 4 3 56 C7 STATUS AK4 7 3H58 D2 3H00 100 3H60 D1 AAA eros SPLPROG 3V3 STANDBY vss HOT 10K SPLWP S SPLWP 22 3H64 D2 10K m 3H65 7 3V3 STANDBY 3V3 STANDBY E 3H66 B7 3V3 STANDBY d BT lt 3H68 B7 H N 4 3H69 C7 gt 1 ASX HOTEL TV lt icx zi 225 3 70 2 557 227 5 3H72 G7 1
270. SB is mounted To exit this mode push the VOLUME minus button on the TV s local keyboard for 10 seconds this disables the continuous mode Then push the SOURCE button for 10 seconds until the F disappears from the screen Logging When something is wrong with the TV set f i the set is rebooting you can check for more information via the logging in Hyperterminal The Hyperterminal is available in every Windows application via Programs Accessories Communications Hyperterminal Connect a ComPair cable 3138 188 75051 from the service connector in the TV to the multi function jack at the front of ComPair box Required settings in ComPair before starting to log Start up the ComPair application Select the correct database open file Q549 2E LA this will set the ComPair interface in the appropriate mode Close ComPair After start up of the Hyperterminal fill in a name f i logging in the Connection Description box then apply the following settings 1 COMx 2 Bits per second 115200 3 Data bits 8 4 Parity none 5 Stop bits 1 6 Flow control none During the start up of the TV set the logging will be displayed This is also the case during rebooting of the TV set the same logging appears time after time Also available in the logging is the Display Option Code useful when there is no picture 2009 May 08 BE EMI Q549 2E LA Service Modes Error Codes
271. SE ONLY 09 7 110 4 neue eet 2 IECA 2 3EAB D9 FEBS H B3B PH SM4 TBT LF ds L 3EAC D9 D1 _9 41_ L 3ECQ 1 _ 3EAT C12 E1 AV1 AUDIO R BAN 2EAD E80 PR 3EAV C8 1 11 H1 1E75 _ 40_ 4 6 3EAYH10 1 12 1 FE96 2 33K J cla 7 D u A 3EAZ H10 1E75 F4 ne 100R 5 ATA 85 2 1 12 IE76 F1 41 828 nal 3EC2 C9 1 78 C12 z 1 1 im pe 3EC3 C9 1 79 4 els 18 xs Tes 3EC4 C9 1 81 C2 F 5 ans 8 8 UART i e AUDIO INT L F 3EC5 C9 IE82 E2 713 913 SERVICE je F 10 21 6 D8 1 84 2 a 9 8 3EC7 D8 1 95 C12 BOLT ON MODULE 8 11 an 1807 4 9 012 IEA1 B10 FE12 AVL BO AUDIO L 3 99K 158 2 1 0 IEBS 5 H11 IEA2 C10 11 AVI G 9 z 3 u AV1 AUDIO L 1 8 2EAF 1u0_ IEB4 10 1 10 J eft AV1 BLK BO ok VEE VSS 3ECG 10 1 4 s e rex 3E67 3ECS1 wy I 1 5 10 AV1 AUDIO L 1 1 d e MOOR 3E00 AV1 AUDIO R 3 d MHP SWITCH MHP SWITCH V 3ECL A2 1 7 010 1008 10K 3ECM B3 IEA8 E11 FE15 E G G 3ECN B1 IEBO E10 3ECP B1 1 1 E10 818 8 8 V1 AUDIO R
272. SH 2x CTRL3 PNX5100 BO7D 2x DRXO 17 B07G 3V3 ET ANA BO4L 1x AUDIO IN3 R BO7D 2x BRX1 BOSH CTRL4 PNX5100 BO7D 2x DRX0 B02A 2x IF AGC B07G 3V3 ET DIG 8 1x AUDIO IN3 R B07D 2x BRX1 1x CTRL DISP1 B07D 2x DRX1 2 1x IF AGC 1 3V3F BO4L 1x AUDIO IN4 L BO7D 2x BRX2 BOSH 1x CTRL DISP1 BO7D 2x DRX14 BO4K 1x IF N 05 3V3F BO7B 1x AUDIO IN4 L BO7D 2x BRX2 BOSE 1x CTRL DISP2 BO7D 2x DRX2 8098 3V3F 8041 1x AUDIO IN4 R BO7D 2x BRXC BOSH 1x CTRL DISP2 BO7D 2x DRX2 BO4K 1x IF P 3V3 FPGA BO7B 1x AUDIO IN4 R BO7D 2x BRXC 1x CTRL DISP3 BO7D 2x DRXC 1x IRQA mPCI 3V3 FPGA 8041 1x AUDIO IN5 L BO7D 3x BRX DDC SCL BOSH 1x CTRL DISP3 BO7D 2x DRXC 1x IRQB mPCI B06A 3V3M BO8C 2x AUDIO IN5 L BO7D 3x BRX DDC SDA BOSE 1x CTRL DISP4 BO7D DRX DDC SCL BO4E 2x IRQ CA 3V3 mPCl BO4L 1 AUDIO IN5 R BO7D 2x BRX HOTPLUG BOSH 2x CTRL DISP4 8070 DRX DDC SDA BOAN 1x IRQ CA BO7F 3V3 NAND BO8C 2x AUDIO IN5 R BO4K 1x B VGA 2 1x 54 BO7D 2x DRX HOTPLUG 2x IRQ CA BO4A 3V3 PER BO4A 2x AUDIO MUTE BO8B 1x B VGA BO4K 1x CVBS4 BO4A 2x EA BO4E 2x IRQ PCI 8048 3V3 PER B10 1x AUDIO MUTE BO4N 1 CA ADDEN BO8B 2x CVBS MON OUT CINCH BO7E 4x EIN 5V BO7G 1x IRQ PCI BO4E 3V3 PER 804 1x AUDIO OUT L BO7H 3x CA ADDEN
273. SU 5 Service SSB NVM no picture be available at start up and 5 gt 3 thus download application will be visible you can 5 proceed and finalize step by step to load the main TV software 8 via the UART logging on the PC for visual feedback i um aum 1 Start up the TV set equipped with the Service SSB and a Ss 5 enable the UART logging on the PC see for settings 5 8 EE H i 1 lt Fault Finding and Repair Tips 5 8 6 Logging 2 The TV set will start up automatically in the download application if main TV software is not loaded 3 Plug the prepared USB stick into the TV set press cursor Right to enter the list and navigate to the autorun file in A the UART logging printout via the cursor keys on the Figure 6 1 SSB identification remote control When the correct file is selected press OK 6 6 Service SSB delivered without main software 4 Press cursor Down and OK to start the flashing of the loaded main TV software Printouts like L 1 100 V 1 100 and P 1 100956 should be visible now in the UART logging 5 Wait until the message Operation successful is Due to a changed manufacturing process new Service SSB s displayed and remove all inserted media Restart the TV can be delivered to the warehouse without main TV set software loaded Below you find the steps to follow when such 6 Setthe correct display code via 062598
274. SW event Y be updated if more STi7100AliveFailedError gt Flash to Ram mature infos Generate f st cold reboot PoolSTITIO0PorFallure N image transfer succeeded avaiable aantay folowed by a cold og HW error within 3052 a reboot Layert 2 and generate cold boot Layer2 15 Yes Timing needs to be i updated if more Code _ mature into is Switch AVC PNX8541 SW initialization in reset active low lt np succeeded avallable Layer2 53 within 2052 Wait 10ms Yes Enable Alive check mechanism Switch the NVM reset line HIGH i MIPS reads the wake up reason Wait until AVC starts to Disable all supply related protections and from standby HP communicate switch off the 3V3 5V DC DC converter Initialize audio Wait 5ms i In case of a LED backlight display a LED DIM panel is Switch on the display in case of a LED backlight present which is fed by the Vdisplay To power the LED DIM the remaining display by sending the TurnOnDisplay 1 FC Panel the Vdisplay swilch driven by the PNX 5100 must be command to the PNX5100 closed The display startup sequence is taken care of by the LED DIM panel Switch Standby shty VO line high Yes t Download firmware into the channel decoder Blink Code error code Downloaded 2 Enter protection Yes decoder error initialize tuner Master IF and
275. T e 52 PO 20IMATI 3IMOSH 2 E Lees esee ies 3124 2 E11 J 5 5 gt P0 21ISSEL1IMAT3 0 Bre ape ap eae ape ETE 3124 3 E11 Be IN 221400 0 T gt ad m 3124 4 11 55 at 1 F109 rst pozaiapo 1 33 3125 1 11 5 GND PO 241AD0 2 Le xe xh xL oe 2 iL 58 4 u 4 PO 28IADO 6 55 3125 2 211 PO 26AD0 7 2 m 3125 4 F11 ii 1 2 5 PO 27ITRSTICAP2 0 5 4 3126 1 F11 2 4 22 1 PO 28ITMSICAP2 1 e 3126 2 F11 tu 2 SPI DATA OUT PO 29ITCKICAP2 2 4 4 G 5 ii G 2 5 SPLDATA RETURN pais 2 4114 4 WK 90992 6 3126 4 11 K 4 e SPI LATCH 1 16 3130 1115 3103 2 7 3 10K 43V3 3127 1 F11 85 5 2 L voae 2 10K 3127 4 F11 88 iva VDD VODA 45 33 3128 11 858 7 BLANK BUF EI 3 3131 2 3129 E11 55 Fee E EEPROM CS a 548 TEMP SENSOR e 3130 G8 10 PROG 2188 5805 3131 G7 11 lt q Sis 88 AT FBST 3132 H8 12919 aT ae 3133 H8 L 13 lt q VLED2 3134 A13 L 14 3 3 F103 3135 11 H S 2 58 55 8 228 3138 B13 3139 12 3140 C11 3141 I 3142 F11 M 7101 7 7102 6 7110 F4 7116 1 B11 Es 1X03 REF EMC HOLE EA SETNAME i em CLASS NO 2008 06 10
276. TECT 12V signal becomes high and 12V 3V3 and 12V 5V DC DC converter can be started up if it rises above 10V5 typical and doesn t drop below 10V typical Debugging The best way to find a failure in the DC DC converters is to check their start up sequence at power on via the mains cord presuming that the standby microprocessor and the external supply are operational Take STANDBY signal high to low transition as time reference When 12V becomes available maximum 1 second after STANDBY signal goes low then 1V2 PNX85XX and 1V2 PNX5100 are started immediately Then after ENABLE 3V3 goes low all the other supply voltages should rise within 2ms Tips e When an output supply voltage is short circuited to GND the corresponding DC DC converter is not making any audible noise the converter switches off immediately and will attempt a re start only after 12V drops and rises again Check the integrity at least no short circuit between drain and source of power MOS FETs especially the high side ones 7005 7008 7000 1 and 7UOH 1 before starting the platform in SDM mode otherwise it can be easily damaged e Switching frequency of DC DC converters should be around 290KHz for 12V to 1V2 DC DC converters and around 370KHz for 12V to 3V3 and 12V to 5V DC DC converters Exit Factory Mode When is displayed in the screen s right corner this means the set is in Factory mode and it normally happens after a new S
277. VDDA 1V2 TRI PLL3 VDDA 1V2 LVDS PLL 1V2 PNX5100 LVDS 2C64 B3 IC89 E9 2 U4 VSSA TRI VDDA 3V3 LVDS1 515 3V3 PNX5100 LVDS PLL 2C65 B3 IC90 F9 BR S e LVDS o AB e ae VDDA_3V3_Lvps2 P15 t ar ae Se a S Se a ae Se Sax Sear See St See VDD_1V2_CORE vss 1V2 PNX5100 55 __ _1 2 TRI VSSA 2 66 1 C1 8 set VSSD TRI PLL3 VSSA LVDS2 L 2 66 2 C2 m 58 4 2 66 3 2 5 24 1V2 PNX5100 DLL 2 VDDA_1V2_DLLO VDD_1V2_MCAB1 au 1V2 PNX5100 2 66 4 2 55 I a VSSA DLLO VDD 1V2 MCAB2 2 67 1 C2 5 Lo AA VDDA 1V2 1 7 MCAB A 1V2 PNX5100 CLOCK c c 9 VDDA_1V2_DLL1 VDDA_1V2_UIP_PLL 572 2067 2 C2 D 5 VSSA DLL1 3V3 SYS 02 3V3 PNX5100 CLOCK 2C67 3 C2 3 Es T VSS_MCAB1 A 573 2C67 4 C2 55 et E22 1V2 VSS MCAB2 2C68 1 D1 ge 1V8 PNX5100 p gt 23 1 VSSA_DLL4 AD13 2C68 2 D2 5 ol ls 2 A213 1V2 PNX5100 CLOCK A CG8 3 DZ gt 22 5 121 12174 VDD_1V8_DDR VSSA_XTAL RIS 5 5 5 5 5 1 8 vss H11 4 8 2C68 4 D2 58 SISISISISISISIS 4 2 69 1 D2 5 mle 555 8 8 8 8 8 8 t1 2C69 2 D2 Pee 2C69 3 D2
278. X5100 DDR2 AO BOSB 1x RX51001CLK BOGE 1x TMS 1x TX851E 1 WC EEPROM PNX5100 BO7G 1x PCI AD17 1x PCI CBE1 PNX5100 DDR2 A1 BO6D 3x RX51001CLK 1 TMS B040 1x TX852A 2x WC EEPROM PNX5100 7 1x PCI AD17 8056 1x PCI CBE1 PNX5100 DDR2 A10 1x RX51001D BO4N 2x TSINO DATAO BO6D 1x TX852A BO7D 1x WC EEPROM PNX5100 1x PCI AD17 BO7F 1x PCI CBE1 PNX5100 DDR2 A11 BO6D 3x RX51001D BO7F 1x TSINO DATAO 1x TX852A 2x WP NANDFLASH BO4F 1x PCHAD18 BO7G 1x PCI CBE1 PNX5100 DDR2 A12 BOSB 1x RX51001D BOAN 2x TSINO DATA1 B040 1x 852 BO7F 2x WP NANDFLASH 8056 1 PCI AD18 BO7H 1x PCI CBE1 PNX5100 DDR2 A2 BO6D 3x RX51001D BO7F 1x TSINO DATA1 BO6D 1x 852 8070 1x WRITE PROT BO7G 1x PCI AD18 1 PCI CBE1 PNX5100 DDR2 A3 1x RX51001E BOAN 2x TSINO DATA2 BO6G 1x 852 BO7E 1x WRITE PROT BO7H 1x PCI AD18 1x PCI CBE2 PNX5100 DDR2 A4 BO6D 3x RX51001E BO7F 1x TSINO DATA2 B040 1 TX852B BOBB 1 WRITE PROT 1x PCHAD18 8056 1x PCI CBE2 PNX5100 DDR2 A5 1x RX51001E BOAN 2x TSINO DATA3 BO6D 1x TX852B 1x XIO ACK 1 PCI AD19 BO7F 1x PCI CBE2 PNX5100 DDR2 A6 BO6D 3x RX51001E BO7F
279. _17 28 XO SELNAND 9 33 rs NAND REn 8 RE 34 __ NAND WEn 18 WE 35 MEN WP NANDFLASH 19 2 WP NANDFLASH e E 428 3V3 NAND ae 24 45 aod 46 47 1 215 1300 vss H E 5 H 4 1 PCI ADO 3PA8 1 1 8 Ss NAND CLE Sc PCI AD1 3P48 2 2 7 100R NAND ALE PCI CBE1 3 48 3 3 6 1008 NAND WEn 2 3 48 4 4 7 5 1008 NAND REn 100R is prohibited without the written consent of the copyright All rights reserved Reproduction in whole orin parts owner 1 1 2 3 4 5 6 7 8 9 10 11 12 13 CHN SETNAME CLASS NO 2 2008 11 21 4 UFD 2K8 DIGI 1 0 TV543 R2 LDIPNX 8204 000 8934 _ ___ NAME Ingrid SUPERS 8 130 6 A2 CHECK DATE 2007 10 18 ROYAL PHILIPS ELECTRONICS 2007 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IE NY 18310_539_090303 eps 090303 2009 May 08 All rights reserved Reproduction in whole or in parts is prohibited without the written consent of the copyright owner 5 SSB Ethernet Circuit Diagrams and PWB Layouts Q549 2E LA 12 13 14 15 16 17 18 19 20 10 11 12 BIS 7G ETHERNET 3V3 ET DIG 3NOY 10K
280. additional EEPROM is foreseen as was implemented in previous platforms After replacement of the TDA9996 HDMI mux the default IC address should be reprogrammed from CO to CE and the HDMI EDIDs should be reprogrammed as well Both actions should be executed via ComPair 7 5 Video and Audio Processing PNX8543 The PNX8543 is the main audio and video processor or System on Chip for this platform It is a member of the PNX85xx SoC family described in earlier chassis with the addition of the MPEG4 functionality the separate STi710x decoder is no longer implemented in this platform Some more delta s compared to the previous PNX85xx are 2HDMI inputs A amp B e HDMI deep colour RGB YCbCr 4 4 1 10 12 bit detection The PNX8543 handles the digital and analogue audio and video decoding and processing The processor is a MIPS32 general purpose CPU and a 8051 based TV controller for power management and user event handling e Fora functional diagram of the PNX8543 refer to Figure 7 7 2009 May 08 46 549 2 Circuit Descriptions TS in from channel decoder TS out in for PCMCIA DV ITU 656 CVBS Y C RGB SSIF LR Dual SPDIF 125 Dual 7 5 1 Video Subsystem PNX8543x MEMORY CONTROLLER MPEG SYSTEM PROCESSOR PRIMARY VIDEO OUTPUT PWM GPIO DV INPUT VIDEO DECODER SD COMB DIGITAL IF AV PIP SUB PICTURE SECONDARY VIDEO OUTPUT
281. ain Menu Sub menu 1 Sub menu 2 Sub menu 3 Description Development ver Development 1 file version Display parameters DISPT 3 26 8 7 Display information is for development purposes sions Acoustics parameters ACSTS 3 6 6 5 PQ PRFPP 1 26 10 4 Ambilight parameters PRFAM 2 6 1 3 Development 2 file version 12NC one zip software Display information is for development purposes nitial main software NVM version Q5492 0 4 0 0 Flash units SW Q5492 0 26 15 0 Upload to USB Channel list To upload several settings from the TV to an USB Stick Personal settings Option codes Display related alignment History list Download from USB Channel list To download several settings from the USB stick to the TV Personal settings Option codes Display related alignment 2009 May 08 HI 549 2 Circuit Descriptions 7 Circuit Descriptions Index of this chapter Main difference with the previous platform is the introduction of 7 1 Introduction Net and 7 2 Power Architecture 7 3 Front End 7 1 1 Implementation 7 4 HDMI 7 5 Video and Audio Processing PNX8543 Key components of this chassis are 7 6 Common Interface e 8543 Digital Colour Decoder cia EP3C25F324C7N FPGA Local Contrast 28 Ambi Light HD1816AF Hybrid Tuner e DRX3926K Demodulator Notes e TDA9996 HDMI Switch e Only new circuits circuits tha
282. ain menu Switch the set to stand by mode For the next alignments supply the following test signals via a video generator to the RF input e EU AP PAL models PAL B G TV signal with a signal strength of at least 1 mV and a frequency of 475 25 MHz e US AP NTSC models an NTSC M N TV signal with a signal strength of at least 1 mV and a frequency of 61 25 MHz channel 3 models an NTSC M TV signal with a signal strength of at least 1 mV and a frequency of 61 25 MHz channel 3 Tuner AGC RF AGC Take Over Point Adjustment Purpose To keep the tuner output signal constant as the input signal amplitude varies No alignment is necessary for the AGC alignment you can use the default value 80 Store settings and exit SAM White Point e Set Active control to Off Choose TV menu TV Settings and then Picture and set picture settings as follows Picture Setting Dynamic backlight Off Dynamic Contrast Off Colour Enhancement Off Picture Format Unscaled Light Sensor Off Brightness 50 Colour 0 Contrast 100 e Go to the SAM and select Alignments gt White point White point alignment LCD screens e Use 100 white screen as input signal and set the following values Colour temperature Normal All White point values to 127 Red BL offset values to 8 Green BL offset values to 8 In case you have a col
283. asked questions and software amp drivers Table 2 1 Described Model numbers CTN Styling Published in 32PFL9604H 12 Core 1312278518310 32PFL9604H 60 3122 785 18310 37PFL9604H 12 3122 785 18310 37PFL9604H 60 3122 785 18311 56PFL9954H 12 3122 785 18311 Directions for Use You can download this information from the following websites http www philips com support http www p4c philips com 2009 May 08 2 3 Connections Technical Specifications and Connections Q549 2E LA EEH Rear connectors SERVICE VGA S VIDEO USB lt gt HDMI SIDE COMMON INTERFACE pH 10 DIGITAL AUDIO OUT AUDIO 750 NETWORK AUDIO IN VGA HDMI 3 HDMI 2 HDMI 1 Figure 2 1 Connection overview 18310_001_090317 eps 090317 2009 May 08 2 Q549 2E LA Technical Specifications and Connections Note The following connector colour abbreviations are used acc to DIN IEC 757 Bk Black Bu Blue Gn Green Gy Grey Rd Red Wh White Ye Yellow 2 3 4 Side Connections Head phone Output Head phone 32 600 ohm 10 mw Cinch Video CVBS Audio In Rd Audio R 0 5 10 DO Wh Audio L 0 5 10 kohm DO Ye Video CVBS 1 75 ohm DO S Video Hosiden Vide
284. at if an NVM is replaced or is initialized after corruption this identification number has to be re written to NVM ComPair will foresee in a possibility to do this This identification number is the 12nc number of the SSB e 12NC display Shows the 12NC of the display e 12NC supply Shows the 12NC of the supply e 12NC fan board Shows the 12NC of the fan board module for sets with LED backlight e 12NC LED Dimming Panel Shows the 12NC of the LED dimming Panel for sets with LED backlight Software versions e Current main SW Displays the built in main software version In case of field problems related to software software can be upgraded As this software is consumer upgradeable it will also be published on the Internet Example Q5492 1 2 3 4 e Standby SW Displays the built in stand by processor software version Upgrading this software will be possible via ComPair or via USB see section 5 9 Software Upgrading Example 88 68 1 2 ambient light SW Displays the MOP ambient light EPLD SW LED Dimming SW Displays the LED Dimming EPLD SW version for sets with LED backlight e Local contrast SW Displays the local contrast SW version Quality items Signal quality Poor average good Child lock Not active active This is a combined item for locks If any lock Preset lock child lock lock after or parental lock is active the item shall show active HDM
285. ated the front LED will show blink the contents of the error buffer Error codes greater then 10 are shown as follows 1 long blinks where 1 to 9 indicating decimal digit 2 Apause of 1 5s 3 n short blinks where 1 to 9 4 A pause of approximately 3 s 5 When all the error codes are displayed the sequence finishes with a LED blink of 3 s 6 The sequence starts again Example Error 128600 After activation of the SDM the front LED will show 1 One long blink of 750 ms which is an indication of the decimal digit followed by a pause of 1 5 s Two short blinks of 250 ms followed by a pause of 3 s Eight short blinks followed by a pause of 3 s Six short blinks followed by a pause of 3 s One long blink of 3 s to finish the sequence The sequence starts again How to Activate Use one of the following methods 2009 May 08 5 7 5 7 1 5 7 2 e Activate the CSM The blinking front LED will show only the latest layer 1 error this works in normal operation mode or automatically when the error protection is monitored by the standby processor In case no picture is shown and there is no LED blinking read the logging to detect whether error devices are mentioned see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging e Activate the SDM The blinking front LED will show the entire content of the LAYER 2 error buffer this works in normal ope
286. bar signal e Audio 3 kHz left 1 kHz right Service Modes Service Default mode SDM and Service Alignment Mode SAM offers several features for the service technician while the Customer Service Mode CSM is used for communication between the call centre and the customer This chassis also offers the option of using ComPair a hardware interface between a computer and the TV chassis It offers the abilities of structured troubleshooting error code reading and software version read out for all chassis see also section 5 4 1 Note For the new model range a new remote control RC is used with some renamed buttons This has an impact on the activation of the Service modes For instance the old MENU button is now called HOME or is indicated by a house icon Service Default Mode SDM Purpose e To create a pre defined setting to get the same measurement results as given in this manual To override SW protections detected by stand by processor and make the TV start up to the step just before protection a sort of automatic stepwise start up See section 5 3 Stepwise Start up start the blinking LED procedure where only LAYER 2 errors are displayed see also section 5 5 Error Codes Specifications Table 5 1 SDM default settings Default Region Freq MHz system Europe AP PAL Multi 475 25 PAL B G Europe AP DVB T 546 00 PID DVB T Video OB 06 PID
287. ble v After entering Display Option code set is Unplug the mainscord to verify the correct going to Standby validation of code disabling of the factory mode v Program Display Option code via 062598 MENU Resi ino sci HOME followed by 3 digits code this code can be found on a sticker inside the set Saved settings v on USB stick After entering Display Option code set is going to Standby validation of code Connect via ComPair interface to Service connector v Restart the set Start TV in Jett mode DVD i OSD Open ComPair browser Q52x v In case of settings reloaded from USB the set type Go to SAM mode and reload settings serial number Display 12NC are automatically stored 3 h tering displ tions Y via Download from USB Apay dr Program set type number serial number and display 12 not already done gt Check latest software on Service website Update Main and Standby software via USB Check if correct Display Option code is programmed Verify Option Codes according sticker inside the set Default settings for White drive see Service Manual Check and perform alignments in SAM according to the Service Manual E g option codes colour temperature
288. ched on When you align the set use plastic rather than metal tools This will prevent any short circuits and the danger of a circuit becoming unstable Notes General Measure the voltages and waveforms with regard to the chassis tuner ground 4 or hot ground depending on the tested area of circuitry The voltages and waveforms shown in the diagrams are indicative Measure them in the Service Default Mode with a colour bar signal and stereo sound L 3 kHz R 1 kHz unless stated otherwise and picture carrier at 475 25 MHz for PAL or 61 25 MHz for NTSC channel 3 e Where necessary measure the waveforms and voltages with and without aerial signal Measure the voltages in the power supply section both in normal operation and in stand by 5 These values indicated by means of the appropriate symbols Schematic Notes e All resistor values are in ohms and the value multiplier is often used to indicate the decimal point location e g 2K2 indicates 2 2 kQ Resistor values with no multiplier may be indicated with either an or an R e g 220E or 220R indicates 220 All capacitor values are given in micro farads x 10 nano farads n x 109 or pico farads p x 10712 e Capacitor values may also use the value multiplier as the decimal point indication e g 2p2 indicates 2 2 pF asterisk indicates component usage varies Refer to the diversi
289. cture is available How to Navigate When the MENU or HOME button is pressed on the RC transmitter the TV set will toggle between the SDM and the normal user menu How to Exit SDM Use one of the following methods e Switch the set to STAND BY via the RC transmitter e Via a standard customer RC transmitter key in 00 sequence Service Alignment Mode SAM Purpose e To perform software alignments e To change option settings Toeasily identify the used software version 2009 May 08 view operation hours To display or clear the error code buffer How to Activate SAM Via a standard RC transmitter Key in the code 062596 directly followed by the INFO button After activating SAM with this method a service warning will appear on the screen continue by pressing the OK button on the RC Contents of SAM see also Table 6 4 Hardware Info A SW Version Displays the software version of the main software example Q5492 1 2 3 4 AAAAB X Y W Z e AAAA the chassis name e B the SW branch version This is a sequential number this is no longer the region indication as the software is now multi region e X Y W Z the software version where X is the main version number different numbers are not compatible with one another and Y W Z is the sub version number a higher number is always compatible with a lower number B STBY PROC Version Displays the software version o
290. e A a 2 010 5 11 3Ho1 8R 5 87 1 2H96 278 2HSJ 08 5 9 cle A 2 5 8 4 4 25 2 8 2HSK 08 5HRG C11 IR ple Se 7 SERE 2HSMD9 7H00 1 18 2 8 2782 8 2HSN G8 7H00 1 D2 ES IHRS 1 1 1 182 Oy 2HSPF10 9 50 04 ANALOG VIDEO 1 21 28 2HSRH10 9 51 05 a SYNC IN 1 55 5282 8 278 2 55 110 9 52 4 SYNCIN 2 7 _ 2HST G3 9 53 5 T 2HSU I9 9H54 4 2HSV G4 9 55 5 PC1 2 2HSF IHR4 3HRZ A r T2 P4 AV2 Y 5 IN PC1 AI 2HSW D1 FHR1 B8 2HSW IHVE U ta P 2HTH uf IK FB Jour PCI AID fe e MA juam ir ZR I 2HSY G3 FHR5 B2 a SES Aus 5 5 2 1 5 FHR6 B2 V gk N3 2HT5 F3 1 38 4 A13 G ECCO E 2 1 2HT6 1H39 4 22 _ 9652 _ _9 53_ 2HSB 2 7 5 40 4 c2 1 m zm 1 AGC PC2 2HT8 F8 IH41 B4 E m 25 2HTB G9 1H42 C4 3H88 nlevesty 2 AI 2HUS 54 j 77 2HTC G10 1H43 D4 4 Ir Tag N ar 22 1 2HTD 610 4 Vises 2 2 610 1 45 5 seg 2
291. e 7 14 SPI communication between ARM controller and LED drivers The ARM controller communicates with the LED drivers on each AL module via an SPI bus For debugging purposes the working principle is given below Data from the ARM controller is linked through the drivers which are connected in cascade e SPI CLK SPI LATCH PROG BLANK and PWM CLOCK are going directly from the controller to each driver SPI DATA RETURN is linked from the last driver to the controller controller decides which driver returns data 7 8 3 Temperature Control Refer to Figure 7 15 for signal interfacing between the ARM controller and the temperature sensor on the AL boards Ambilight module 1 Ambilight module 2 Ambilight module N Vcc Vcc t t TEMP Ines TEMP 0 sENSOR SENSOR SENSOR 18310 206 090318 eps 090318 Figure 7 15 Communication between ARM controller and temperature sensor Each AL board is equipped with a temperature sensor If one of the sensors detects a temperature over the threshold the TEMP line is pulled LOW which results in brightness reduction 2009 May 08 IC Data Sheets EN LEN 8 IC Data Sheets This chapter shows the internal block diagrams and pin electrical diagrams with the exception of memory and logic configurations of ICs that are drawn as black boxes in the ICs 81 Diagram SSB DC DC
292. e polled on the standard 40ms Power OK error interval and startup should be continued when Layer1 3 detect2 becomes high Layer2 16 The supply fault line is Supply fault O T a D emor combination of the DCDC High D gt P converters and audio yere protection line Yes This enables the 3V3 and Enable the DCDC converter for 3V3 and Comente 8541 1 8 5100 become available Du Delay of 50ms needed because of the latency of the detect 1 circuit Wait 50m delay is also needed for the PNX5100 The reset of the 5100 should only be released 10ms after powering the 3V3 5V DCDC or class D error Supay ont No Layer1 2 igh Layer2 11 yes Detect 1 line Disable 3V3 switch standby High line high and wait 4 seconds Yes Yes Added to make the system more robust to 4 Y power dips during startup At this point the Voltage output error regular supply fault detection algorithm which Enable the supply fault detection Layer1 2 normally detects power dips is not up and algorithm Layer2 18 running yet Enter protection Set slave address te ote t o of Standby pP to i This will allow access to NVM and Switch LOW the RESET NVM line to allow access to NVM Add a NAND FLASH and can not be done 2 delay before trying to address the NVM to allow correct NVM
293. e used by Service Technicians ProcessNVM Q5492 x x x x zip Default NVM content Must be programmed via ComPair or can be loaded via USB be aware that all alignments stored in NVM are overwritten here Content of the MOP Ambilight ARM SW File MOP AMBILIGHT V1 2 UPG jettsigned zip Contains the MOP ambientlight software ARM processor on the DC DC AL interface board and is upgradeable via USB UPG This SW is not part of the FUS autorun upg and is not available in the One Zip software file but provided separately via the commercial Philips website software for servicers only Instructions for upgrading are included in the zip file 5 9 6 UART logging 2K9 see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging 2009 May 08 es Alignments 6 6 1 6 1 1 6 2 6 3 2009 May 08 Alignments Index of this chapter 6 1 General Alignment Conditions 6 2 Hardware Alignments 6 3 Software Alignments 6 4 Option Settings 6 5 Reset of Repaired SSB 6 7 Total Overview SAM modes General Alignment Conditions 6 3 1 Perform all electrical adjustments under the following conditions Power supply voltage depends on region AP NTSC 120 230 Vac 50 Hz 10 AP PAL multi 120 230 Vac 50 Hz 10 EU 230 Vac 50 Hz 10 LATAM NTSC 120 230 Vac 50 Hz 10 US 120 Vac 60 Hz 10 Connect the set to the mains
294. ected to have a possible dangerous impact others of quite high potential are of limited current and are sometimes held in less regard e Always respect voltages While some may not be dangerous in themselves they can cause unexpected reactions that are best avoided Before reaching into a powered TV set itis bestto testthe high voltage insulation It is easy to do and is a good service precaution 3 4 Abbreviation List 0 6 12 AARA ACI ADC AFC AGC AM AP AR ASF ATSC ATV Auto TV AV AVC AVIP B G BLR BTSC B TXT CEC CL CLR ComPair CSM CVBS DAC DBE DDC D K DFI DFU DMR DMSD DNM SCART switch control signal on A V board 0 loop through AUX to TV 6 play 16 9 format 12 play 4 format Automatic Aspect Ratio Adaptation algorithm that adapts aspect ratio to remove horizontal black bars keeps the original aspect ratio Automatic Channel Installation algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control control signal used to tune to the correct frequency Automatic Gain Control algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio 4 by 3 or 16 by 9 Auto Screen Fit algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Televisi
295. ective replace the whole unit Piezo Touch Control Panel The flexfoil between Piezo Flexfoil Assy mounted on the plastic rim of the set and the PWB as described below is extremely vulnerable Do not pull hard at the PWB or flexfoil Once the flexfoil has been damaged the entire plastic rim of the set with the touch control pads has to be swapped The Piezo Touch Control Panel PWB contains ESD sensitive components implying that necessary industrial ESD precautions must be taken during removing or remounting Refer to Figure 4 7 Figure 4 8 and Figure 4 9 for details 2 5 b 18310 214 090318 eps 090319 Figure 4 7 Piezo Touch Control Panel 1 1 Gently pull the bottom side of the PWB out of the cabinet until you can unplug the connector 1 18310 216 090318 eps 090319 Figure 4 8 Piezo Touch Control Panel 2 1 Now gently pull the top side of the PWB out of the cabinet without damaging the flexfoil until you can unplug the connector 2 4 3 7 4 3 8 18310 215 090318 eps 090319 Figure 4 9 Piezo Touch Control Panel 3 1 Tounplug the flexfoil connector first the outer part of the connector has to be moved upwards 3 before this part can be turned sidewards 4 as shown in the picture Now the flexfoil can be removed from the connector and the PWB can be taken out of the set When defective replace the whole unit Small Signal Board SSB Caution It is mandatory to remount sc
296. ecuted by a Serial Peripheral Interface SPI bus interface Ambilight module 1 Ambilight module 2 5 w SPI bus is a synchronous serial data link standard that operates in full duplex mode For debugging purposes the working principle is given below e At startup the controller will read out matrix data from the EEPROM devices via SP DATA RETURN Before operation the driver current is set via SPI with driver in DC mode During normal operation the controller receives RGB configuration operation mode and topology data via I C controller converts the RGB data via the matrixes to SPI LED data e Via data return the controller receives error data if applicable Also PWM clock and BLANK signals are generated by the controller The controller can be reprogrammed via via USB The controller can receive matrix values via which will be stored in the EEPROM of each AL module via the SPI bus The temperature sensor in each AL module controls the TEMP line in case of a too high temperature the controller will reduce the overall brightness LED driver communication via SPI bus Refer to Figure 7 14 below for signal interfacing between the ARM controller and the LED drivers on the AL boards and the LED drivers and the EEPROMs on the AL boards Ambilight module N 18310 205 090318 eps 090318 2009 May 08 LEN 549 2 Circuit Descriptions Figur
297. ed always check the display option code in SAM even when picture is available Performance with the incorrect display option code can lead to unwanted side effects for certain conditions Upgrade HDMI EDID NVM The EDID MUX device including all HDMI NVM except the 4th is upgradeable via USB see ComPair for further instructions It should be noted that in case a new spare EDID MUX device is used for repair the initial default address must be changed from CO to CE to be done via ComPair Upgrade VGA 4th HDMI EDID NVM The EDID for VGA connector or the 4th HDMI can only be upgraded via external 2 To upgrade the EDID for the VGA connector or 4th HDMI pin 7 of the EDID NVM has to be short circuited to ground Therefore a test point is foreseen see Figure 5 13 For the VGA EDID NVM it s most suitable to connect pin 7 to ground on the NVM device itself See ComPair for further instructions 2009 May 08 18310 220 090318 eps 090319 Figure 5 13 4th HDMI EDID NVM pin 5 8 14 Wi Fi module To prevent damage on the coax wires especially the female core of the coax wires can be bend over during dis and reconnecting this should be carried out by use of pliers Service Modes Error Codes and Fault Finding Q549 2E LA 5 8 15 SSB Replacement Follow the instructions in the flowchart in case a SSB has to be exchanged See figure SSB replacement flowchart Instruction note SSB replacement Q528 x Q52
298. ed via the blinking LED procedure if SDM is switched on Error 28 ARM ambilight When there is communication towards the ARM processor LAYER 2 error 28 will be logged and displayed via the blinking LED procedure if SDM is switched on Error 29 FPGA local contrast When there is no communication towards this FPGA LAYER 2 error 29 will be logged and displayed via the blinking LED procedure if SDM is activated Error 34 Tuner When there is no 2 communication towards the tuner after start up LAYER 2 error 34 will be 2009 May 08 5 549 2 Service Modes Error Codes and Fault Finding 5 6 5 6 1 5 6 2 logged and displayed via the blinking LED procedure when SDM is switched on e Error 42 Temp sensor Only applicable for TV sets with I C controlled screen Main NVM When there is no communication towards the main NVM LAYER 1 error 2 will be displayed via the blinking LED procedure In SDM LAYER 2 error will be blinked as 15 Errors here can not be logged due to inaccessibility of the NVM device e Error 53 This error will indicate that the PNX8543 has read his bootscript when this would have failed error 15 would blink but initialization was never completed because of hardware problems NAND flash or software initialization problems Possible cause could be that there is no valid software loaded try to upgrade to the latest main software vers
299. een 5 and 50 ms after power is supplied display should receive valid Ivds clock action holder AVC minimum wait time to switch on the lamp after power up is 200ms To have a reliable operation of the backlight the backlight should be driven with a PWM duty cycle of 10096 during the first second Only after this first one or two seconds the PWM may be set to the required output level action holder St by Note that the PWM output should be present before the backlight is switched on To minimize the artefacts the picture should only be unblanked after these first seconds autonomous action Semi Standby The assumption here is that a fast toggle lt 2s can only happen during ONPSEMI gt ON In these states the AVC is still active and can provide the 2s delay If the transition ON SEMI gt STBY SEMI gt ON can be made in less than 2s Wait until previous on state is left more than 2 the semi gt stby transition has to be delayed seconds ago to prevent LCD display problems until the requirement is met I Assert RGB video blanking CPipe already generates a valid output and audio mute clock in the semi standby state display startup can start immediately when leaving the semi standby state Switch on the display by sending the TurnOnDisplay 1 command to the PNX5100 wait 250ms min 200ms
300. er 3 The software upgrade application will start Attention In case the download application has been started manually the autorun upg will maybe not be recognized What to do in this case 1 Create a directory UPGRADES on the USB stick 2 Rename the autorun upg to something else e g to software upg Do not use long or complicated names keep it simple Make sure that AUTORUN UPG is no longer present in the root of the USB stick 3 Copy the renamed file into this directory 4 Insert USB stick into the TV 2009 May 08 5 The renamed upg file will be visible and selectable in the upgrade application Back up Software Upgrade Application If the default software upgrade application does not start could be due to a corrupted boot 2 sector via the above described method try activating the back up software upgrade application How to start the back up software upgrade application manually 1 Disconnect the TV from the Mains AC Power 2 Press the INFO button on a Philips remote control or CURSOR DOWN button on a Philips DVD RC 6 remote control it is also possible to use a TV remote in DVD mode Keep the INFO button or cursor down button pressed while reconnecting the TV to the Mains AC Power 3 The software upgrade application will start Stand by Software Upgrade via USB In this chassis it is possible to upgrade the Stand by software via a USB stick The method is
301. erved Reproduction whole or in paris Circuit Diagrams and PWB Layouts Q549 2E LA SSB FPGA WOW I O Banks is prohibited without the written consent of the copyright owner 1 2 3 10 AN 11 12 13 14 15 16 17 18 19 20 2 43 E7 2 2 09 2 6 013 3F74 3 2 2 B1 3FNG E7 2 A6 7FNO 5 C1 7FNO 8 C13 9FN1 D4 9FN7 E4 07 9FND C9 FF48 B1 IFN2 B8 IFN5 B9 IFN8 B13 IFNB B15 IFNF D7 IFNJ D3 IFNM D5 2 0 D9 2FN3 D9 2FN7 D13 3F74 4 B5 3FN3 B1 1 0 3 A10 0 6 C5 7FNO 9 E4 9FN4 E4 9FN8 05 9FNB D7 FF18 A1 IFNO A2 IFN3 B8 IFN6 B11 IFN9 B13 IFNC D13 IFNG D5 IFNK D4 IFNN D5 2FN1 D9 2FN5 D12 3F74 2 B4 3FN1 1 7 0 10 11 4 A13 7FNO 7
302. et Green black level offset 2009 May 08 Alignments Q549 2E LA LEN Sub menu 1 Sub menu 2 Sub menu 3 Description Dealer options Picture mute Off On Select Picture mute On Off Picture is muted not muted in case no input signal is detected at input connectors Virgin mode Off On Select Virgin mode On Off TV starts up does not start up once with a language selection menu after the mains switch is turned for the first time virgin mode E sticker Off On Select E sticker On Off USP s on screen Auto store mode None PDC VPS TXT page PDC VPS TXT Options Digital broadcast DVB Off On Select DVB On Off DVB T installation Off On or Country dependent Select DVB T installation On Off or by country DVB T light Off On Select DVB T light On Off DVB C Off On Select DVB C On Off DVB C installation Off On or Country dependent Select DVB C installation On Off or by country Over the air download Off On or Country dependent Select Over the air download On Off or by country 8 days EPG Off On Select 8 day EPG On Off Digital features USB Off On Select USB On Off Ethernet Off On Select Ethernet On Off Wi Fi Off On Select Wi Fi On Off DLNA Off On Select DLNA On Off Online service Off Online service is Off PTP Picture Transfer Protocol Off On Select PTP On Off Update assistant Off On Select Update assistant On Off Inter
303. f the stand by processor C Production Code Displays the production code of the TV this is the serial number as printed on the back of the TV set Note that if an NVM is replaced or is initialized after corruption this production code has to be re written to NVM ComPair will foresee in a possibility to do this Operation Hours Displays the accumulated total of operation hours not the stand by hours Every time the TV is switched on off 0 5 hours is added to this number e Errors followed by maximum 10 errors The most recent error is displayed at the upper left for an error explanation see section 5 5 Error Codes Reset Error Buffer When cursor right or the button is pressed and then the OK button is pressed the error buffer is reset e Alignments This will activate the ALIGNMENTS sub menu See Chapter 6 Alignments Dealer Options Extra features for the dealers Options Extra features for Service For more info regarding option codes 6 Alignments Note that if the option code numbers are changed these have to be confirmed with pressing the OK button before the options are stored Otherwise changes will be lost initialize NVM The moment the processor recognizes corrupted NVM the initialize NVM line will be highlighted Now two things can be done dependent of the service instructions at that moment Save the content of the NVM via ComPair for developmen
304. g of the CTN can be done via ComPair Model number programming The reset item Clear NET TV memory can be selected via MENU or HOME gt Setup gt Installation gt Clear NET TV memory customer preferences stored at provider side will be reset now 2009 May 08 5492 Alignments 6 5 4 SSB identification Whenever ordering a new SSB it should be noted that the correct ordering number 12nc of a SSB is located on a sticker on the SSB The format is lt 12nc SSB gt lt serial number gt The ordering number of a Service SSB is the same as the ordering number of an initial factory SSB 3 Create a folder upgrades in the root of a USB stick size gt 50 and save the file in this upgrades folder Note it is possible to rename this file e g Q549 SW version upg this in case there are more than one autorun upg files on your USB stick 4 Plugthe prepared USB stick into the TV set and select the autorun file in the displayed browser on the screen 5 Now the main TV software will be loaded automatically supported by a progress bar 6 Setthe correct display code via 062598 HOME xxx where is the 3 digit display panel code see sticker on the side bottom of the cabinet 6 6 2 When no picture is available 28 E E a tw Due to a possible wrong display option code in the received E
305. he file Csm txt will be saved in the root of the USB stick If this mechanism works it can be concluded that a large part of the operating system is already working MIPS USB DC DC Converter Description The onboard supply consists of 5 DC DC converters and 4 linear stabilizers All DC DC converters have 12V input voltage and deliver e 41V2 PNX85XX supply voltage 1 24V nominal stabilized close to PNX8543 chip e 1 2 5120 supply voltage 1 26V nominal stabilized close to PNX5120 chip 3V3 3 34V nominal overall 3 3 V for onboard IC s e 5V 5 15V nominal for USB and Conditional Access Interface and 5V5 TUN for 5V TUN tuner stabilizer 4 33VTUN 34V nominal for analog only tuners The linear stabilizers are providing e 1V2 STANDBY out of 3V3 STANDBY 1 24V nominal e 1 8 85 and 1V8PNX5100 connected via CFH1 1 84V nominal e 2V5 WOW FPGA diversity only 2 5V nominal e 5 out of 5V5 TUN 5V nominal 3V3 STANDY and 1V2 STANDBY are permanent voltages Supply voltages 1V2 PNX85XX and 1V2 PNX5100 are 5 8 5 5 8 6 started immediately when 12 incoming voltage is available 12 is enabled by STANDBY signal active low Supply voltages 3V3 2V5 1V8 PNX5100 1 8 85 5V and 5V TUN are switched on directly by signal ENABLE 3V3 active low provided that 12V detected via 7U40 amp 7U41 is available 12V is considered OK gt DE
306. ight functionality is turned off in case the set contains a CE IPB inverter supply switch off LCD backlight Mute all video outputs Wait 250ms min 200 5 v Switch off the display by sending the TurnOnDisplay 0 C command to the PNX5100 1 17660 129 140308 Semi Standby Figure 5 9 Active to Stand by flowchart LCD non DFI 2009 May 08 Service Modes Error Codes and Fault Finding Q549 2E LA 5 Semi Stand by action holder MIPS d autonomous action If ambientlight functionality was used in semi standby lampadaire mode switch off ambient light Delay transition until ramping down of ambient light 5 If this is not performed and the set is finished switched to standby when the switch off of the ambilights is still ongoing the lights will H Switch off abruptly when the supply is cut transfer Wake up reasons to the Stand by Switch Memories to self refresh this creates a more stable condition when switching off the power 17660 130 eps Stand by 140308 Figure 5 10 Semi Stand by to Stand by flowchart 2009 May 08 HZI Service Modes Error Codes and Fault Finding action holder MIPS autonomous action Log the appropriate error and set stand by flag in NVM Redefine wake up
307. ignals a schematic reference e g B14b is placed next to the signals BOOST CPROT CPROT CPROT SW CPROT SW 14 signal_name DC F DC F DC PROT DC PROT DIM CONTROL FEEDBACK SW FEEDBACK L Grounds FEEDBACK R For normal and special grounds e g GNDHOT or GND3V3 etc nothing is indicated SRP Schematics SRP is a tool which automatically creates a list with signal references indicating on which schematic the signals are used A reference is created for all signals indicated with an SRP symbol these symbols are op Power supply line GND SA GNDscrew GNDscrew Stand alone signal or switching line used as less as possible GND SSB GND SSP GND SSP IN SW IN L IN R Signal line into a wire tree IN SW INV MUTE INV MUTE name 7 4 INV MUTE LEFT SPEAKER Switching line into a wire tree LEFT SPEAKER UTE name 4 Bi directional line e g SDA into a wire tree name 4 POWER GOOD AP1 POWER OK PLATFORM RIGHT SPEAKER P4 Signal line into a wire tree its direction depends on the circuit e g ingoing for PDP outgoing for LCD sets RIGHT SPEAKER SOUND ENABLE STANDBY STANDBY SUB SPEAKER SUB SPEAKER Remarks When there is a black dot on the signal direction arrow it is an SRP symbol so there will be a reference to the signal name in the SRP list V CLAMP oe
308. io and video corresponding to the requested output is delivered by the AVC The higher level requirement is that audio and 1 video should be demuted without transient effects and that the audio should be demuted Switch Audio Reset low and wait 5ms maximum 1s before or at the same time as the unblanking of the video Release audio mute and wait 100ms before any other audio handling is done e g volume change i unblank the video The higher level requirement is thatthe ambilight functionality may not be switched on __ Switch on the Ambilight functionality according the last status before the backlight is turned on in case the settings set contains a CE IPB inverter supply Active 17660 128 eps 140308 Figure 5 8 Semi Stand by to Active flowchart LED backlight 2009 May 08 EEJ 5 Q549 2E LA Service Modes Error Codes and Fault Finding Active action holder AVC action holder St by autonomous action Mute sound outputs softmute Wait 100ms Set main amplifier mute I O audio mute Force ext audio outputs to ground I O audio reset And wait 5ms switch off Ambilight v The higher level requirement is that the Wait until Ambilight has faded out backlight may not be switched off before the fixed wait time of x s ambil
309. ion Note that it can take a few minutes before the TV starts blinking LAYER 1 error 2 or in SDM LAYER 2 error 53 e Error 64 Only applicable for TV sets with an I C controlled screen The Blinking LED Procedure Introduction The blinking LED procedure can be split up into two situations Blinking LED procedure LAYER 1 error In this case the error is automatically blinked when the TV is put in CSM This will be only one digit error namely the one that is referring to the defective board see table 5 2 Error code overview which causes the failure of the TV This approach will especially be used for home repair and call centres The aim here is to have service diagnosis from a distance e Blinking LED procedure LAYER 2 error Via this procedure the contents of the error buffer can be made visible via the front LED In this case the error contains 2 digits see table 5 2 Error code overview and will be displayed when SDM hardware pins is activated This is especially useful for fault finding and gives more details regarding the failure of the defective board Important remark For all errors detected by MIPS which are fatal gt rebooting of the TV set reboot starts after LAYER 1 error blinking one should short the solder paths at start up from the power OFF state by mains interruption and not via the power button to trigger the SDM via the hardware pins When one of the blinking LED procedures is activ
310. is TX2E FCAP e la TXE FCBJ e 12 2CBZ F8 E fep ep 2 Kaa 2 gt FCR e e EN EN S gt 2 10 2 RES RES 7 cn f 9 2 a Fes 255 MESS fie B pe pi SDADISP 7 100R 1650 2089 407 qu RES FCBR TX4B RES 5 3CA2 E7 RES 8 8 VDISP1 _9 _ 5 4 3CA4 B12 n 5 12 h Le 2 3CA6 B1 2 4 7 2 4 7 2CAH 4p7 AJE 2CBB 4p7 3CA7 1 RES RES 1651 9 12 DISPLAY CA CI 12 RES RES 3CAC C12 J 2 2086 3CAD 12 2 4p 2CBDj4p 3CAE C12 RES RES 7 00 4 1 9C10 B7 Noe D 9C11C7 RES 9631 2 4 7 9C32 C8 2 4 7 2CBF 407 9CA0 E14 Doe PER ND4De T 9 1 14 9 TX4E 9CA3 B8 RES 5 n 9 4 2 2CBG le 2CAR 407 i 2CBH 47 n 5 RES RES Ker SE FC10 B7 FC12 C12 FC13 C13 L FC14 C13 FC15 C13 FC16 C13 FC17 E14 _ 2 C7 FCA1 C7 FCA2 C8 FCA3 C7 M FCA4 C8 5 C7 08 FCA7 07 FCA8 08 FCA9 D7 FCAA D8 N CHN SETN
311. istance is 6 5 MHz L is Band 1 Lis all bands except for Band LG Philips LCD supplier Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system Sound carrier distance is 4 5 MHz Microprocessor without Interlocked Pipeline Stages A RISC based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Not Connected Near Instantaneous Compounded Audio Multiplexing This is a digital sound system mainly used in Europe Negative Temperature Coefficient non linear resistor National Television Standard Committee Color system mainly used in North America and Japan Color carrier NTSC M N 3 579545 MHz NTSC 4 43 4 433619 MHz this is a VCR norm it is not transmitted off air Non Volatile Memory IC containing TV related data such as alignments Open Circuit On Screen Display On screen display Teletext and Control also called Artistic SAA5800 Project 50 communication protocol between TV and peripherals Phase Alternating Line Color system mainly used in West Europe color carrier 4 433619 MHz and South America color carrier PAL M 3 575612 MHz and PAL N 3 582056 MHz Printed Circuit Board same as PWB Pulse Code Modulation Plasma Display Panel Power Factor Corrector or Pre conditioner Picture In Picture Phase Locked Loop Used for e g FST tuning syste
312. lt DP83816 9 o 2 15710 167 5 230905 Figure 8 5 Internal block diagram and pin configuration 2009 May 08 Data Sheets 8 6 Diagram SSB Audio B10A TPA3123D 7010 Block Diagram 1 pF Left Channel Right Channel 1 22 pH 470 pF 55 22 pH 470 AGND 10 V to 10 V to 30 V VCLAMP Shutdown Control Mute Control 4 Step Gain Control Pin Configuration PVCCL 10 PGNDL SD 2 PGNDL PVCCL 3 LOUT MUTE 4 BSL LIN 5 6 BYPASS 7 GAINO AGND 8 GAIN1 AGND BSR PVCCR ROUT VCLAMP PGNDR PVCCR PGNDR TERMINAL NAME an VO P DESCRIPTION SD 2 signal for low disabled high operational TTL logic levels with compliance to RIN 6 Audio input for right channel LIN 5 Audio input for left channel GAINO 18 Gain select least significant bit TTL logic levels with compliance to GAIN1 17 Gain select most significant bit TTL logic levels with compliance to MUTE 4 Mute signal for quick disable enable of outputs high outputs switch at 50 duty cycle low outputs enabled TTL logic levels with compliance to AVCC BSL 21 y o Bootstrap for left channel PVCCL 1 3 P Power supply for left channel H bridge not internally connected to PVCCR or AVCC LOUT 22 Class D 1
313. mi standby state v The timings to be used in 5 orbi i Pane command for this specific display play 1 FC v wait 250ms min 200ms Initialize audio and video processing IC s and functions according needed use case Switch on LCD backlight Lamp ON Wait until valid and stable audio and video corresponding to the requested output is delivered by the AVC The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video 3 Release audio mute and wait 100ms before any other audio handling is done e g volume change Switch Audio Reset low and wait 5ms unblank the video The higher level requirement is that the v ambilight functionality may not be switched on Switch on the Ambilight functionality according the last status before the backlight is turned on in case the settings Set contains a CE IPB inverter supply Active 17660 126 eps 140308 Figure 5 6 Semi Stand by to Active flowchart 2009 May 08 EA EMI Q549 2E LA Service Modes Error Codes and Fault Finding Constraints taken into account Display may only be started when valid LVDS output clock can be delivered by the AVC Betw
314. ms The customer can give directly the desired frequency Point Of Deployment a removable CAM module implementing the CA system for a host e g a TV set Power On Reset signal to reset the uP Positive Temperature Coefficient non linear resistor Printed Wiring Board same as PWM QRC QTNR RGB RC 5 RC6 RESET ROM RSDS R TXT SAM S C SCART SCL SCL F SD SDA SDA F SDI SDRAM SECAM SIF SMPS SoC SOG SOPS SPI S PDIF SRAM SRP SSB STBY SVGA SVHS SW SWAN SXGA TFT THD TMDS TXT TXT DW UI uP UXGA V VESA VGA VL VSB WYSIWYR WXGA XTAL XGA Precautions Notes and Abbreviation List Pulse Width Modulation Y Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor YPbPr Random Access Memory Red Green and Blue The primary color signals for TV By mixing levels YUV of R G and B all colors Y C are reproduced Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d Appareils Radior cepteurs et T l viseurs Serial Clock 2 CLock Signal on Fast 2 bus Standard Definition Serial Data DAta Signal Fast 12 bus Serial Digital Interface see ITU 656 Synchronous DRAM SEequence Couleur
315. n 5 5 Error Codes 5 5 4 Error Buffer Extra Info Note that it can take up several minutes before the TV starts blinking the error e g LAYER 1 error 2 LAYER 2 error 15 or 53 Errors detected by main software MIPS In this case the error will be logged into the error buffer and can be read out via ComPair via blinking LED method LAYER 1 2 error or in case picture is visible via SAM How to Read the Error Buffer Use one of the following methods screen via the SAM only when picture is visible E g 0000 00 00 00 No errors detected 23 00 00 00 00 Error code 23 is the last and only detected error 37 23 00 00 00 Error code 23 was first detected and error code 37 is the last detected error Note that no protection errors can be logged in the error buffer e Via the blinking LED procedure See section 5 5 3 How to Clear the Error Buffer e Via ComPair How to Clear the Error Buffer Use one of the following methods e By activation of the RESET ERROR BUFFER command in the SAM menu 4 With anormal RC key in sequence MUTE followed by 062599 and e Ifthe content of the error buffer has not changed for 50 hours it resets automatically Error Buffer In case of non intermittent faults clear the error buffer before starting to repair before clearing the buffer write down the content as this history can give significant information This
316. n mode or changed to a low resolution For normal content distribution the source and the display device must be enabled for HDCP software key decoding High Definition Multimedia Interface HeadPhone Monochrome TV system Sound carrier distance is 6 0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector ITU R is a standards body subcommittee of the International Telecommunication Union relating to radio communication ITU 656 a k a 01 is a digitized video format used for broadcast grade video Uncompressed digital component or digital composite signals can be used The SDI signal is self synchronizing Precautions Notes and Abbreviation List ITV LS LATAM LCD LED LS LVDS Mbps M N MIPS MOP MOSFET MPEG MPIF MUTE NC NICAM NTC NTSC NVM O C OSD OTC P50 PAL PCB PCM PDP PFC PIP PLL POD POR PTC PWB uses 8 bit or 10 bit data words and has a maximum data rate of 270 Mbit s with a minimum bandwidth of 135 MHz Institutional TeleVision TV sets for hotels hospitals etc Last Status The settings last chosen by the customer and read and stored in RAM or in the NVM They are called at start up of the set to configure it according to the customer s preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system Sound carrier d
317. n Interface DVB Cl as described the digital broadcasting standard DVB The weakness of the conventional CI module as Conditional Access system was the absence of a Copy Protection mechanism as decrypted content could be sent over the PCMCIA interface unscrambled With the Cl extension a form of copy protection is established between the Conditional channel decoder Transport stream 1 interface 1_ 2 G conax irdela viaccess France Telecom company DES AES scrambler Access Module CAM and the Integrated Digital Television IDTV The security mechanisms in Cl are derived copied from POD with the exception of Out Of Band OOB used in US CA systems For more information about conventional CA systems using a Cl module refer to the L PA or BL2 xU Service Manual The Cl standard is downwards compatible with the existing CI standard The following figure shows the implementation of the Cl Conditional Access system in the TV543 platform DES AES descrambler 1 4 u interface Transport Streams CA Control Proprietary CA scrambling CI Standardised CCS scrambling mmm o 18440_221_090227 eps 090227 Figure 7 11 Cl Conditional Access implementation 7 7 Net TV In this chassis a feature that enables access to dedicated internet pages from a limited group of information suppliers 78 Ambi Light The
318. net software update Internet software update is Display Screen 180 LCD Sharp Z3LA13 56 Displayed the panel code amp type model LightGuide Off On Select LightGuide On Off Display fans Not present Present Select Display fans Present Not present Temperature sensor Sensor present in display only for 21 9 N A Temperature LUT 0 amp monitor Off On Select E box amp monitor On Off Video reproduction Picture processing None PNX5100 Select Picture processing None PNX5100 Q549 xE chassis MOP local contrast Off On Select MOP local contrast On Off Light sensor Off On Select Light sensor On Off Light sensor type 0 1 2 3 Select Light sensor type form 0 to 3 for difference styling Pixel Plus type Pixel Plus HD Select type of picture improvement Perfect Pixel HD Pixel Precise HD Ambilight None Select type of Ambilight modules use 2 sided 2 2 For 8400 series only 2 sided 4 4 3 sided 2 3 2 3 sided 4 3 4 3 sided 4 5 4 4 sided 4 3 4 3 Ambilight technology LED Future use Ambilight technology LED is in use MOP ambilight Off On Select MOP ambilight On Off 2009 May 08 HZI Alignments Main Menu Sub menu 1 Audio reproduction Sub menu 2 Acoustic system Sub menu 3 Description Cabinet design used for setting dynamic audio pa rameters So
319. ng the Piezo Touch Control Panel PWB requires special attention Refer to Piezo Touch Control Panel for details 1 Remove all screws of the rear cover 2 Lift the rear cover from the TV Make sure that wires and flat coils are not damaged while lifting the rear cover from the set Speakers Each speaker unit is mounted with two screws A sticker on the the unit indicates if it is the right or left L box seen from the front side of the set When defective replace the whole unit 2009 May 08 Mechanical Instructions 4 3 3 4 3 4 4 3 5 Ambi Light Each Ambi Light unit is mounted on a subframe Refer to Figure 4 5 for details 18310 212 090318 eps 090319 Figure 4 5 Ambi Light unit 1 Remove the Ambi Light cover 1 2 Unplug the connector s 3 The PWB can now be taken from the subframe When defective replace the whole unit Note the screws that secure the AmbiLight units are longer than the other screws Main Supply Panel 1 Unplug all connectors 2 Remove the fixation screws 3 Take the board out When defective replace the whole unit IR amp LED Board Refer to Figure 4 6 for details 18310 213 090318 eps 090319 Figure 4 6 IR amp LED Board 4 3 6 Mechanical Instructions Q549 2E LA 1 Remove the Main Supply Panel as earlier described 2 Remove the stand 1 and its subframe 2 3 Now you gain access the IR amp LED board When def
320. nitial failure shuts the amplifier down this cyclus starts over and over again Important remark regarding the blinking LED indication As for the blinking LED indication the blinking led of LAYER 1 error displaying can be switched off by pushing the power button on the keyboard This condition is not valid after the set was unpowered via mains interruption The blinking LED starts again and can only be switched off by unplugging the mains connection This can be explained by the fact that the MIPS can not load the keyboard functionality from software during the start up and doesn t recognizes the keyboard commands at this time Fault Finding and Repair Tips Read also section 5 5 Error Codes 5 5 4 Error Buffer Extra Info Ambilight Due to degeneration process of the AmbiLights there can be a difference in the colour and or light output of the spare ambilight module in comparison with the originals ones contained in the TV set Via ComPair the light output can be adjusted Audio Amplifier The Class D IC 7D10 has a powerpad for cooling When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid This is needed to insure that the cooling is guaranteed otherwise the Class D IC could break down in short time CSM When CSM is activated and there is a USB stick connected to the TV the software will dump the complete CSM content to the USB stick T
321. no 2H19 A4 5HVH A12 x 2H20 A4 5HY2 A12 lt lt gt 221 4 5 11 TSR ERTES TSE TSA 7 S87 Se 195 95 TEETE TE 2 22 4 5HY4 H3 B 1V2 PNX85XX gt 2 23 5 5 5 012 2 24 11 5 6 13 1138 88 8 8 8 28 28 6 E amason SHYBEA ae ae ae ae 5 T amp amp amp qe 2H29 011 7H00 10 F6 B ado che b Qd eS ade 5HY2 NP 2H30 A9 7H00 9 A6 NEC MD 50 75 3 2H31 AQ 7 06 C2 PNX85439EH M2 24182 1H28 5 n 2832 A10 9H18 5 1V2 STANDBY D gt Fo gig ele 2H33 A10 9H19 E5 3V3 STANDBY AJ12 gls 2H34 A10 9H20 E5 2 2 8 8 R SR 85 gt 2H35 A10 9H21 5 AT RTA 2 36 11 CH53 I 2 8 8 2 8 m c 2H37 A11 FHK1 D4 L 1 1 1 4 5 6 3v3 2H38 11 05 5 3 3 2H39 C10 10 ES 813 BE 2H40 C11 1H28 B10 STi VDD_1V2_CORE A 6 1V2 PNX85XX 2H41 C11 49 C4 D Zle 2H42 C2 60 C2 E 2 8 2H43 D2 1H61 D2 2H44 D2 B12 L 2H50 C4 IHK2 D11 72 3 VDD zlealeslesls B 2H51 C4 IHK3 C12 ST a 5 82 8 8 8 ps RES 2H52 C3 IHK4 C12 N 4 det va cse co DEC E 5H50 E 3 3
322. o Y C In 1 Ground Y Gnd 2 Ground C Gnd 3 Video 1 Vpp 75 ohm 4 0 3 Vpp 75 ohm USB2 0 3 7 mm 10000 022 090121 eps 090121 Figure 2 2 USB type 1 5V 2 Data QC 3 Data QC 4 Ground Gnd 1 HDMI Digital Video Digital Audio In see HDMI 1 2 3 amp 4 Rear Connections Common Interface 68p See diagram 7 SSB PCMCIA Connector X 2 3 2 Rear Connections Service Connector UART 1 Ground Gnd 1 2 UART TX Transmit gt 3 UART RX Receive VGA Video RGB In 00000 HOO OO Ot o 10000 002 090121 eps 090127 Figure 2 3 VGA Connector 1 Video Red 0 7 Vpp 75 ohm 2 Video Green 0 7 Vpp 75 ohm 3 Video Blue 0 7 75 ohm 4 5 Ground Gnd 6 Ground Red Gnd 7 Ground Green Gnd 8 Ground Blue Gnd 9 45Vpc 5V 10 Ground Sync Gnd 11 n c 12 DDC SDA DDC data 13 0 5V 14 V sync 0 5V 15 DDC_SCL DDC clock 2009 May 08 Cinch S PDIF Out Bk Coaxial 0 4 0 6Vpp 75 ohm Cinch Audio Out Rd Audio R 0 5 5 10 kohm Wh Audio L 0 5 10 kohm EXT3 Cinch Video YPbPr In Audio In Gn Video Y 1 75 ohm Bu Video Pb 0 7 75 ohm Rd Video Pr 0 7 Vpp 75 ohm Rd Audio 0 5 10 kohm Wh Audio L 0 5 10 kohm amp 2 Video RGB In CVBS In Out Audio In Out 20 2 0
323. odes Error Codes and Fault Finding Q549 2E LA action holder AVC Constraints taken into account Display may only be started when valid LVDS output clock can be delivered by the Between 5 and 50 ms after power is supplied display should receive valid Ivds clock action holder St by minimum wait time to switch on the lamp after power up is 200ms Semi Standby The assumption here is that a fast toggle lt 2s autonomous action can only happen during ON gt SEMI gt ON In these states the AVC is still active and can provide the 2s delay If the transition ON gt SEMI v gt STBY gt SEMI gt ON be made in less than 2s N Wait until previous on state is left more than 2 the semi gt stby transition has to be delayed seconds ago to prevent LCD display problems until the requirement is met v Assert RGB video blanking CPipe already generates a valid output and audio mute clock the semi standby state display startup can start immediately when leaving v the semi standby state v Switch on the display by sending the OUTPUT ENABLE FC command to the LED DIM panel v wait 250ms min 200ms TBC in def spec Initialize audio and video processing IC s and functions according needed use case Switch on LCD backlight Lamp ON Wait until valid and stable aud
324. oduction 32PFL9604H 60 08211 35971 18431 45288 30645 47282 00184 00000 181 37PFL9604H 12 08227 35972 18431 45288 30625 47282 00176 00000 161 The microprocessor communicates with a large number of 2 37PFL9604H 60 08227 35972 18431 45288 30625 47282 00176 00000 161 ICs in the set To ensure good communication and to make 56PFL9954H 12 08275 33925 18431 45288 30644 47282 00161 00000 180 digital diagnosis possible the microprocessor has to know which ICs to address The presence absence of these 5100 ICs back end advanced video picture improvement Important after having edited the option numbers as IC which offers motion estimation and compensation features described above you must press OK on the remote control commercially called HDNM plus integrated Ambilight control before the cursor is moved to the left is made known by the option codes 6 5 Reset of Repaired SSB Notes After changing the option s save them by pressing the button on the RC before the cursor is moved to the left select STORE in the SAM root menu and press OK on the RC new option setting is only active after the TV is switched off stand by and again with the mains Switch the NVM is then read again Dealer Options For dealer options in SAM select Dealer options See Table 6 4 SAM mode overview Service Options Select the sub menu s to set the initialisation codes options
325. of the model number via text menus See Table 6 4 SAM mode overview Opt No Option numbers Select this sub menu to set all options at once expressed in two long strings of numbers An option number or option byte represents a number of different options When you change these numbers directly you can set all options very quickly All options are controlled via eight option numbers When the NVM is replaced all options will require resetting To be certain that the factory settings are reproduced exactly you must set both option number lines You can find the correct option numbers on a sticker inside the TV set and in Table 6 3 Option and display code overview Example The options sticker gives the following option numbers 08192 00133 01387 45160 12232 04256 00164 00000 A very important issue towards a repaired SSB from a service repair shop implies the reset of the NVM on the SSB A repaired SSB in service should get the service Set type 00 0000000000 and Production code 00000000000000 Also the virgin bit is to be set To set all this you can use the ComPair tool In case of a display replacement reset the Operation hours display to 0 or to the operation hours of the replacement display New here in this chassis is the Net TV functionality Therefore the CTN set type item in CSM1 must be filled into the spare SSB to ensure access to the Net TV portals The loadin
326. on Systems Committee the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system Sound carrier distance is 5 5 MHz Board Level Repair Broadcast Television Standard Committee Multiplex FM stereo sound system originating from the USA and used e g in LATAM and AP NTSC countries Blue TeleteXT Centre channel audio Consumer Electronics Control bus remote control bus on HDMI connections Constant Level audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet Copy Protection Customer Service Mode Color Transient Improvement manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement extra low frequency amplification See E DDC Monochrome TV system Sound carrier distance is 6 5 MHz Dynamic Frame Insertion Directions For Use owner s manual Digital Media Reader card reader Digital Multi Standard Decoding Digital Natural Motion 2009 May 08 DNR DRAM DRM DSP DST DTCP DVB C DVB T DVD DVI d E DDC EDID EEPROM EMI EPLD EU EXT FDS FDW FLASH FM FPGA FTV Gb s G TXT H HD HDD HDCP HDMI HP 2 25 IF IR IRQ ITU 656
327. onnected properly and if the directory repair is present in the root of the USB stick Now the settings are stored onto the USB stick and can be used to download onto another TV or other SSB Uploading is of course only possible if the software is running and if a picture is available This method is created to be able to save the customer s TV settings and to store them into another SSB e Download to USB To download several settings from the USB stick to the TV same way of working needs to be followed as with uploading To make sure that the download of the channel list from USB to the TV is executed properly it is necessary to restart the TV and tune to a valid preset if necessary Note The History list item can not be downloaded from USB to the TV This is a read only item In case of specific problems the development department can ask for this info How to Navigate e n SAM the menu items can be selected with the CURSOR UP DOWN key on the RC transmitter The selected item will be highlighted When not all menu items fit on the screen move the CURSOR UP DOWN key to display the next previous menu items e With the CURSOR LEFT RIGHT keys it is possible to De activate the selected menu item De activate the selected sub menu 5 2 3 Service Modes Error Codes and Fault Finding Q549 2E LA ESI e With the OK key it is possible to activate the selected action How to Exit SAM U
328. oup 1 indicates hardware options 1 to 4 Group 2 e g 10185 12448 00164 00000 The second line group 2 indicates software options 5 to 8 Store Store after changing Initialise NVM N A Store Select Store in the SAM root menu after making any changes Software maintenance Software events Display Clear Test reboot Display information is for development purposes Hardware events Display Display information is for development purposes Clear Operation hours display 0003 In case the display must be swapped for repair you can reset the Display operation hours to 0 So this one does keeps up the lifetime of the display it self mainly to compensate the degeneration behav iour Test setting Digital info QAM modulation 64 QAM Symbol rate 23 29 Original network ID 12817 Network 10 12817 Transportstream ID 2 Service ID 3 Hierarchical modulation 0 Selected video PID 35 Selected main audio PID 99 Selected 2nd audio PID 1 Display information is for development purposes Install start frequency 000 Install start frequency from 0 MHz Install end frequency 999 Install end frequency as 999 MHz Default install frequency Installation Digital only Select Digital only or Digital Analogue before instal Digital Analogue lation 2009 May 08 Alignments Q549 2E LA 6 LM M
329. our analyser e Measure with a calibrated contactless colour analyser in the centre of the screen Consequently the measurement needs to be done in a dark environment e Adjust the correct x y coordinates while holding one of the White point registers R G or B on 127 by means of decreasing the value of one or two other white points to the correct coordinates see Table 6 1 White D alignment values Tolerance dx 0 004 dy 0 004 Repeat this step for the other colour temperatures that need to be aligned e When finished press OK on the RC and then press STORE in the SAM root menu to store the aligned values to the NVM Restore the initial picture settings after the alignments Table 6 1 White D alignment values Value Cool 11000K Normal 9000K Warm 6500K x 0 270 0 279 0 309 y 0 279 0 287 0 328 If you do not have a colour analyser you can use the default values This is the next best solution The default values are average values coming from production e Selecta COLOUR TEMPERATURE e g COOL NORMAL or WARM 6 4 6 4 1 6 4 2 6 4 3 6 4 4 e Set the RED GREEN and BLUE default values according to the values in Table 6 2 e When finished press OK on the RC then press STORE the SAM root menu to store the aligned values to the NVM e Restore the initial picture settings after the alignments Table 6 2 White tone default setting
330. ration mode or when SDM via hardware pins is activated when the tv set is in protection Important remark For all errors detected by MIPS which are fatal gt rebooting of the TV set reboot starts after LAYER 1 error blinking one should short the solder paths at start up from the power OFF state by mains interruption and not via the power button to trigger the SDM via the hardware pins Transmit the commands MUTE 062500 OK with a normal RC The complete error buffer is shown Take notice that it takes some seconds before the blinking LED starts e Transmit the commands MUTE 06250x OK with a normal RC where x is a number between 1 and 5 When x 1 the last detected error is shown x 2 the second last error etc Take notice that it takes some seconds before the blinking LED starts Protections Software Protections Most of the protections and errors use either the stand by microprocessor or the MIPS controller as detection device Since in these cases checking of observers polling of ADCs and filtering of input values are all heavily software based these protections are referred to as software protections There are several types of software related protections solving a variety of fault conditions e Protections related to supplies check of the 12V 5V 3V3 and 1V2 e Protections related to breakdown of the safety check mechanism E g since the protection de
331. reasons for protection state and transfer to stand by pP v Switch off LCD lamp supply If needed to speed up this transition this block could be omitted This is depending on the outcome of the safety investigations Wait 250ms min 200ms v Switch off LVDS signal v Switch off 12V LCD supply within a time frame of min 0 5ms to max 50ms after LVDS switch off v Ask stand by uP to enter protection state This can be the standby LED or the ON LED depending on the availability in the set 1 17660 131 eps 140308 Protection Figure 5 11 To Protection State flowchart 2009 May 08 5 4 5 4 1 Service Modes Error Codes and Fault Finding Q549 2E LA 5 LIE Service Tools 5 4 2 ComPair Introduction ComPair Computer Aided Repair is a Service tool for Philips Consumer Electronics products and offers the following 1 ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way 2 ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas No knowledge on 2 UART commands is necessary because ComPair takes care of this 3 ComPair speeds up the repair time since it can automatically communicate with the chassis when the uP is working and all repair information is directly available 4 ComPair features TV sof
332. rews at their original position during re assembly Failure to do so may result in damaging the SSB 1 Remove the Wi Fi module that is mounted on the SSB 2 Unplug all connectors 3 Remove the screws that secure the board 4 The SSB can now be taken out of the set LCD Panel Refer to Figure 4 10 and Figure 4 11 for details 1 Remove the Piezo Touch Control Panel PWB as earlier described 2 Remove the AL covers as earlier described 3 Remove both Main Supply Panel and SSB as earlier described 4 Remove the subframes of Main Power Supply and SSB 1 5 Remove both AL subframes with the AL unit still mounted on it by unplugging the connector 2 and removing the screws 3 6 Remove all remaining adhesive tapes and remove all cables from their clamps 7 Carefully remove the conducting tape 4 it must be re used during re assembly 8 Remove the remaining screws indicated with an arrow that hold the plastic rim and remove the rim 9 Now the LCD Panel can be lifted from the front cabinet The panel has to be slided downwards once it has been lifted because the brackets on the top cannot be removed from the cabinet You will see a conducting foam between metal front and panel near the location of the Piezo Touch Control Panel When mounting a new LCD Panel 1 Check if this conducting foam between panel and metal front is in place 2 Re attach the conducting tape between LCD Panel and metal rim 4
333. ror 15 PNX8543 PNX5100 doesn t boot Indicates that the main processor PNX5100 was not able to read his bootscript This error will point to a hardware problem around the PNX8543 supplies not OK PNX 8543 completely dead I C link between PNX and Stand by Processor broken etc When error 15 occurs it is also possible that 1 bus is blocked NVM 12 1 can be indicated in the schematics as follows SCL UP MIPS SDA UP MIPS SCL 1 SDA 1 SCL 2 or SDA 2 Other root causes for this error can be due to hardware problems from the NVM PNX5100 DDR s and the bootscript reading from the PNX5100 Error 16 12V This voltage is made in the power supply and results in protection LAYER 1 error 3 in case of absence When SDM is activated we see blinking LED LAYER 2 error 16 Error 17 Invertor or Display Supply Here the status of the Power OK is checked by software no protection will occur during failure of the invertor or display supply no picture only error logging LED blinking of LAYER 1 error 8 in CSM SDM this gives LAYER 2 error 17 Error 18 1V2 3V3 5V too low All these supplies are generated by the DC DC supply on the SSB If one of these supplies is too low protection occurs and blinking LED LAYER 1 error 2 will be displayed automatically In SDM this gives LAYER 2 error 18 Error 21 5100 When there is no communication towards the PNX5100 the TV set will start rebooting and display LAY
334. se one of the following methods e Switch the TV set to STAND BY via the RC transmitter e Via a standard RC transmitter key in 00 sequence select the BACK key Customer Service Mode CSM Purpose When a customer is having problems with his TV set he can call his dealer or the Customer Helpdesk The service technician can then ask the customer to activate the CSM in order to identify the status of the set Now the service technician can judge the severity of the complaint In many cases he can advise the customer how to solve the problem or he can decide if it is necessary to visit the customer The CSM is a read only mode therefore modifications in this mode are not possible When in this chassis CSM is activated a testpattern will be displayed during 5 seconds 1 second Blue 1 second Green and 1 second Red then again 1 second Blue and 1 second Green This test pattern is generated by the PNX5100 So if this test pattern is shown it could be determined that the back end video chain PNX5100 LVDS and display of the SSB is working When CSM is activated and there is a USB stick connected to the TV the software will dump the complete CSM content to the USB stick The file Csm txt will be saved in the root of the USB stick This info can be handy if no information is displayed Also when CSM is activated the LAYER 1 error is displayed via blinking LED Only the latest error is displayed see also section 5 5
335. similar to upgrading the main software via USB Use the following steps 1 Create a directory UPGRADES on the USB stick 2 Copy the Stand by software part of the one zip file e g StandbySW CFT72 88 0 0 0 upg into this directory 3 Insert the USB stick into the TV 4 Start the download application manually see section _ Manual Software Upgrade 5 Select the appropriate file and press the OK button to upgrade Content and Usage of the One Zip Software File Below the content of the One Zip file is explained and instructions on how and when to use it e BootProm 5120 05492 x x x x zip A programmed device can be ordered via the regional Service organization e Ceisp2padll P2PAD x x x x zip Not to be used by Service technicians For ComPair development only DDC Q5492 x x x x zip Contains the content of the VGA NVM See ComPair for further instruction e 05492 x x x x zip Contains the EDID content of the different EDID NVM s See ComPair for further instructions e EJTAGDownload_Q5492_x x x x zip Only used by service centra which are allowed to do component level repair e FUS_Q5492_x x x x_commercial zip Contains the autorun upg which is needed to upgrade the TV main software and the software download application e Factory_Q5492_x x x x_commercial zip Only for production purposes not to be used by Service technicians e FlashUtils Q5492 commercial zip No
336. t gt 7 1 PCI CLK PNX5100 NANDO1GWSB2BNGF MEM vfs PCI CLK PNX8535_ TTE 5100 WP NANDFLASH 19 n gt Mabe WOWEP PNX5120EH M2 F4 XO SELNAND gt gt LeldkPNXGIO0 Doi IU PCI CLK PNX5100 u3 WC EEPROM PNXSI00 7 134 v2 PNX8543 LCD PWR ON_SPI DI IRQ PCI gt U4 gt gt PN RESET SYSTEM 5100 SDRAM 056 coNNECTOR gt gt ETT ANALOGUE EXTERNAL D 7001 1 07 EDE5116AJBG USBOC 1 06 5 002 USB 2 0 USB20 M i EDES CONNECTOR USB20 DP_ lt s CONNECTOR esq 07 PNX5100 DDR2 CLK_P RXD UP LL ag Rm eR LB EV UP PNX5100 DDR2 CLK 5117121 PNX8543 DEBUG TXD UP 9 40 1 STANDBY gt 2H07 SDM gt Lo 0 0 gt gt RES RES smm ee E a E 17 74 PNX8543 STANDBY CONTROLLER 24 DC DC RESET PNX5100 90 serene gt gt LIGHT SENSOR m lt lt SPI PROG lt lt 2 EH PNX8543 STANDBY CONTROLLER Rc up 9H25 ac ue E lt AF13 LED2 gt gt AF14 CLK OUT PNX5100 DETECT 12V 2 IR LED PANEL PEE gt gt gt 0 RESET ETHERNET gt gt quit 3V3 STANDBY AND B26 CDPWRON _ mm DETECT gt wo D KEYBOARD CONTROL PWM A
337. t analysis before initializing This will give the Service department an extra possibility for diagnosis e g when Development asks for this Initialize the NVM Note When the NVM is corrupted or replaced there is a high possibility that no picture appears because the display code is not correct So before initializing the NVM via the SAM a picture is necessary and therefore the correct display option has to be entered Refer to Chapter 6 Alignments for details To adapt this option it s advised to use ComPair the correct HEX values for the options can be found in Chapter 6 _ Alignments or a method via a standard RC described below Changing the display option via a standard RC Key in the code 062598 directly followed by the MENU or HOME button and XXX where XXX is the 3 digit decimal display code as mentioned in Table 6 3 Make sure to key in all three digits also the leading zero s If the above action is successful the front LED will go out as an indication that the RC sequence was correct After the display option is changed in the NVM the 2009 May 08 5 Q549 2E LA Service Modes Error Codes and Fault Finding TV will go to the Stand by mode If the NVM was corrupted or empty before this action it will be initialized first loaded with default values This initializing can take up to 20 seconds Display Option Code PHILIPS ODEL 32PF9968 10 PROD SERIAL NO AG 1A0620 0000
338. t are not published recently TPA3123D2PWP Class D Power Amplifier are described DP83816AVNG PCI ethernet media access controller and Figures can deviate slightly from the actual situation due physical layer MacPhyter Il to different set executions e For a good understanding of the following circuit 7 1 2 TV543 Architecture Overview descriptions please use the wiring block see chapter 9 Block Diagrams and circuit diagrams see chapter 10 Circuit Diagrams and PWB Layouts Where necessary you will find a separate drawing for clarification e For details about the chassis block diagrams refer to chapter 9 Block Diagrams An overview of the TV543 architecture can be found in Figure 7 1 7 1 Introduction The Q549 2E LA chassis platform name TV543 92 is the successor of the Q529 1E LA chassis platform TV522 92 PNX5120 PNX8543 Contrast Halo Reduced HD NM Hybrid Tuner MICRONAS FHD 120Hz Saw DRX39xyK H264 USB 2 0 Ethernet Spartan 5250 Led Dimming 9996 MUX 4 LLL 18310 200 090317 5 090317 Figure 7 1 Architecture of TV543 92 Elite Core platform 2009 May 08 Circuit Descriptions Q549 2E LA HI 7 1 3 SSB Cell Layout Id ddA ueos Position UL logo 18310 201 090317 eps 090317 Figure 7 2 SSB layout cells top view 2009 May 08 44 Q549 2E LA Circuit Descriptions 7 2 Power Architecture
339. t to be used by Service technicians e x x x x zip Contains the local contrast software and is upgradeable via USB UPG This SW is not part of the FUS autorun upg e 05492 x x x x zip Not to be used by Service Technicians e OpenSourceFile 05492 x x x x zip Not to be used by Service technicians e PQGPrivate 05492 x x x x zip Not to be used by Service technicians e StandbySW CFTxx x x x x commercial zip Contains the Stand by software in upg and hex format The StandbySW_xxxxx_prod upg file can be used to upgrade the Stand by software via USB StandbySW_xxxxx hex file can be used to upgrade the Stand by software via ComPair 5 9 5 Service Modes Error Codes and Fault Finding Q549 2E LA The files StandbySW_xxxxx_exhex hex and StandbySW_xxxxx_dev upg may not be used by Service technicians only for development purposes UpgradeAll_Q5492_x x x x_commercial zip Only for production purposes not to be used by Service technicians Caution Never try to use this file because it will overwrite the HDCP keys UpgradeExe Q5492X x x x x zip Not to be used by Service Technicians Ambilight Q5492 x x x x zip Not to be used by Service technicians Cabinet Q5492 x x x x zip Not to be used by Service technicians Display Q5492 x x x x zip Not to be used by Service technicians LightGuide TV522 x x x x zip Not to b
340. tections are done by means of software failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more Remark on the Supply Errors The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection but to a cold reboot of the set If the supply is still missing after the reboot the TV will go to protection Protections during Start up During TV start up some voltages and IC observers are actively monitored to be able to optimise the start up speed and to assure good operation of all components If these monitors do not respond in a defined way this indicates a malfunction of the system and leads to a protection As the observers are only used during start up they are described in the start up flow in detail see section 5 3 Stepwise Start up Hardware Protections The only real hardware protection in this chassis appears in case of an audio problem e g DC voltage on the speakers This protection will only affect the Class D 7D10 and puts the amplifier in a continuous burst mode cyclus approximately 2 seconds Repair Tip e There will be still picture available but no sound While the Class D amplifier tries to start up again the cone of the 5 7 3 5 8 5 8 1 5 8 2 5 8 3 5 8 4 Service Modes Error Codes and Fault Finding Q549 2E LA 5 loudspeakers will move slowly in one or the other direction until the i
341. that creates a list with all references to signal lines The list contains 12 15 12 15 12V references to the signals within all schematics of a PWB It replaces the text references currently printed next to the signal names in the schematics These printed references are created manually and are therefore not guaranteed to be 100 12V_NF 12VAL 25VLP correct In addition in the current crowded schematics there is often none or very little place for these references Some of the PWB schematics will use SRP while others will still use the manual references Either there will be an SRP 25VLP 3V3 STANDBY 400V F reference list for a schematic or there will be printed references in the schematic 400V F 400V F 5V2 Non SRP Schematics 5V2 5V2 NF 5V2 NF There are several different signals available in a schematic 5V SW 5V SW 8 Power Supply Lines All power supply lines are available in the supply line overview see chapter 6 In the schematics see chapter 7 is not SUB SPEAKER indicated where supplies are coming from or going to It is however indicated if a supply is incoming created elsewhere or outgoing created or adapted in the current schematic SUB SPEAKER 12 15V 12 15V 12 15V 12 15V 12 15V Be 45V 45V gt AL OFF AUDIO L AUDIO L Outgoing Incoming AUDIO PROT AUDIO R Normal Signals AUDIO R AUDIO SW ADDIOSSWI For normal s
342. time of the solder joint should not exceed 4 sec Avoid temperatures above 400 C otherwise wear out of tips will increase drastically and flux fluid will be destroyed To avoid wear out of tips switch off unused equipment or reduce heat e Mix of lead free soldering tin parts with leaded soldering tin parts is possible but PHILIPS recommends strongly to avoid mixed regimes If this cannot be avoided carefully clear the solder joint from old tin and re solder with new tin 3 3 6 3 3 7 3 3 8 Precautions Notes and Abbreviation List Q549 2E LA EM Alternative BOM identification It should be noted that on the European Service website Alternative is referred to as Design variant The third digit in the serial number example AG2B0335000001 indicates the number of the alternative B O M Bill Of Materials that has been used for producing the specific TV set In general it is possible that the same TV model on the market is produced with e g two different types of displays coming from two different suppliers This will then result in sets which have the same CTN Commercial Type Number e g 28PW9515 12 but which have a different B O M number By looking at the third digit of the serial number one can identify which B O M is used for the TV set he is working with If the third digit of the serial number contains the number 1 example AG1B033500001 then the TV set has been manufactured according to
343. tware is available via the Philips Service web portal e ComPair UART interface cable for Q54x x using 3 5 mm Mini Jack connector 3138 188 75051 Note While encounting problems contact the local support desk Memory and Audio Test With this tool you can test the memory of the PNX8543 as well if the PNX5100 is enabled and audio testing What is needed USB stick TESTSCRIPT 0549 Downloadable from the Philips Service website from the section Software for Service only ComPair service cable 3138 188 75051 Procedure Create a directory JETTFILES under the root of the USB stick MemTestTV543 bin and autojett bin available TESTSCRIPT Q549 under the directory JETTFILES Install the computer program BOARDTESTLOGGER available in TESTSCRIPT Q549 on the PC Connect a ComPair service cable from the service connector in the set into the multi function jack at the front of the ComPair II box Required settings in ComPair start up the ComPair application Select the correct database open file 0549 2 LA this will set the ComPair interface in the appropriate mode Close ComPair Start up the program BOARDTESTLOGGER and select COMx Putthe USB stick into the TV and start up the TV while pressing the i button on a Philips DVD RC6 remote control it s also possible to use TV remote in DVD mode PC the
344. tware up possibilities Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the defective product The ComPair interface box is connected to the PC via an USB cable For the TV chassis the ComPair interface box and the TV communicate via a bi directional cable via the service connector s The ComPair fault finding program is able to determine the problem of the defective television by a combination of automatic diagnostics and an interactive question answer procedure How to Connect This is described in the chassis fault finding database in ComPair TOTV To To UART SERVICE SERVICE UART SERVICE CONNECTOR CONNECTOR CONNECTOR ComPair It non RC out 99999 Optional Power Link Mode witch Activity 5 5 85232 UART 5 5 1 ComPair Developed ui lips Brugge Optional power CE 5V DC SS 06532 036 eps 160208 Figure 5 12 ComPair interface connection Caution It is compulsory to connect the TV to the PC as shown in the picture above with the ComPair interface in between as the ComPair interface acts as a level shifter If one connects the TV directly to the PC via UART ICs will be blown How to Order ComPair order codes e CombPair Il interface 3122 785 91020 Sof
345. ty tables for the correct values correct component values are listed on the Philips Spare Parts Web Portal Spare Parts For the latest spare part overview consult your Philips Spare Part web portal BGA Ball Grid Array ICs Introduction For more information on how to handle BGA devices visit this URL http www atyourservice magazine com Select Magazine then go to Repair downloads Here you will find Information on how to deal with BGA ICs BGA Temperature Profiles For BGA ICs you must use the correct temperature profile Where applicable and available this profile is added to the IC Data Sheet information section in this manual Lead free Soldering Due to lead free technology some rules have to be respected by the workshop during a repair e Use only lead free soldering tin If lead free solder paste is required please contact the manufacturer of your soldering equipment In general use of solder paste within workshops should be avoided because paste is not easy to store and to handle e Use only adequate solder tools applicable for lead free soldering tin The solder tool must be able reach solder tip temperature of at least 400 C stabilize the adjusted temperature at the solder tip exchange solder tips for different applications e Adjust your solder tool so that a temperature of around 360 C 380 C is reached and stabilized at the solder joint Heating
346. urce selection EXT1 AV1 type SCART CVBS RGB LR Select input source when connected with external equipment CVBS YPbPr LR CVBS Y C YPbPr HV LR CVBS YPbPr LR EXT2 AV2 type SCART CVBS RGB LR Select input source when connected with external equipment CVBS Y C LR CVBS YPbPr LR CVBS Y C LR EXT3 AV3 type None Select input source when connected with external equipment CVBS CVBS LR YPbPr YPbPr LR YPbPr HV LR VGA Off On Select VGA On Off SIDE Off On Select SIDE On Off HDMI 1 Off On Select HDMI 1 On Off HDMI 2 Off On Select HDMI 2 On Off HDMI Off On Select HDMI 3 On Off HDMI 4 Off On Select HDMI 4 On Off HDMI side Off On Select HDMI side On Off HDMI CEC Off On Select HDMI CEC On Off HDMI CEC RC passthrough Off On Select HDMI CEC RC passthrough On Off HDMI CEC Pixel Plus link Off On Select Pixel Plus link On Off Miscellaneous Region Europe AP PAL MULTI Australia Select Region country Tuner type HD1816 MK1 TD1716 MK4 Select type of Tuner used TD1716 MK3 HD1816 MK2 System RC support Off On Select System RC support On Off Embedded user manual Off On Select Embedded user manual On Off Start up screen Off On Select Start up screen On Off Wallpaper Off On Select Wallpaper On Off Hotel mode Hotel mode is Option number Group 1 e g 08192 02181 01387 45160 The first line gr
347. x FRONT Y CVBS BO6F 1 1 1 06 1 8 5100 8041 1x ADAC 4 BO8B 1x AV4 Y 2x CA MOCLK_VS2 2x DDR2 D27 BO8C 2x FRONT Y CVBS BO6G 1x 1 1 B04G 1V8 PNX85XX BO4M 1x ADAC 4 BO4K 1x AV5 PB BON 1x CA MOSTRT 2x DDR2 D28 B10 2x GND A BO6F 1 1 5 4 1V8 PNX85XX 804 1x ADAC 5 1x AV5 PB 2x CA MOSTRT 2x DDR2 D29 BO1B 1x GND AUDIO BO6G 1x 1 5 1V8 PNX85XX 8041 1x ADAC 5 BO4K 1x AV5 PR BOAN 1x CA MOVAL 2x DDR2 D3 B10 16x GND AUDIO BO6F 1 1 B07D 1V8 PNX85XX 804 1x ADAC 6 1x AV5 PR 2x CA MOVAL 2x DDR2 D30 15x GND SIG BO6G 1x 1 8098 1V8 PNX85XX BO4L 1x ADAC 6 BO4K 2x AV5 Y 1x CA OE 2x DDR2 D31 01 15x GND SIG1 BO6F 1x MM1 CLK BO6A 2 5 804 1x ADAC 7 1x AV5 Y BO7H 1x CA OE 2x DDR2 D4 BO4K 1x G VGA BO6G 1x 1 2 5 8041 3 ADAC 7 BO1B 1x BACKLIGHT BOOST 1x CA REG 2x DDR2 D5 08 1 G VGA BO6F 1 MM1 CLK BO6F 2V5 804 1x ADAC 8 BOSH 1 BACKLIGHT BOOST BO7H 1x CA REG 2x DDR2 D6 BO4H 1x HDMIA RXO BO6G 1x MM1 CLK 8098 2 5 8041 3 ADAC 8 BOSH 1 BACKLIGHT CONTROL FPGA IN BON 1x CA RST 2x DDR2 D7 2x HDMIA RXO BO6F 1x 1 50 06 2V5 DDR1 BO7D 4x AIN
348. x PCI AD29 BO7H 1x 2x 1 SDA AMBI 3V3 BOSE 3x TX3D BO6D 1x BO6G 2x nSTATUS 1x PCI AD3 1x PCMCIA A1 2x PROG B BO6G 1x SDA AMBI 3V3 BOSE 3x TX3D BO6G 1x BO7D 6x PCEC HDMI 8056 1x PCI AD3 BO7H 1x PCMCIA A1 4 2x PSEN BOAN 1x SDA BOLT ON BOSE 3x BO6D 1x 2 BO7G 1x PCI AD3 1 PCMCIA A10 BO1B 1 RC SDA BOLT ON BOSE 3x BO6G 1x 1 PCI ADO BO7H 1x PCI AD3 BO7H 1x PCMCIA A10 2x RC BO8D 1x SDA BOLT ON BOSE 3x 4 BO6D 1x TXF2A 8056 1 PCI ADO BO9A 1x PCI AD3 1x 11 1x RC IN BOSE 2x SDA DISP BOSE 3x 4 BO6G 1 BO7F PCI ADO 1x PCI AD30 BO7H 1x PCMCIA A11 BO8C 1 RC IN BOGA 3x SDA DISP BOSE 3x TX4B BO6D 1x TXF2A BO7G 1x PCI ADO 8056 1x PCI AD30 PCMCIA A12 1x RC OUT BO6D 1 SDA DISP BOSE 3x TX4B BO6G 1x 2 7 1 PCI ADO BO7F 1x PCI AD30 BO7H 1x PCMCIA A12 BO8C 1 RC OUT BO1B 1 SDA SET BOSE 3x TX4C BO6D 1x TXF2B 1x PCI ADO BO7G 1x PCI AD30 7 1x PCMCIA A13 4 4x RC UP 2x SDA SET BOSE 3x 4 BO6G 1 TXF2B BO4F 1x PCI AD1 BO7H 1x PCI AD30 BO7H 1x PCMCIA A13 BO8D 1x R
349. y 08 Block Diagrams Q549 2E LA 9 Block Diagram Audio FRONT END PCMCIA CONNECTOR 7P15 7P16 54 8543 0 4506 7ALVC245APW 20 3 3 PNX85439EH M2 V ANB SHRW 1 VDDA AUDIO D VREE POS amo SHEZ TPA3123D2PWP AK9 VDDA_3V3_DAC VDDA DAC GONDIONAL PCMCIA VCC VPP VAUDIOHFONER 1735 ACCESS LEFT SPEAKER 5 SPEAKER L DEMODULATOR 8028 AUDIO R DRX3926K RIGHT SPEAKER HD1816AF BHXP 11 3153 47 M STANDBY ESTEE lt SPEAKER R 1 L 0 CONTROLLER 10 TUN P10 B IF _N IF 3T55 7 AUDIO MUTE 5V TUN 7152 1 3T70 gt gt 1725 _ 25 T I 1 5 2 PNX8543 AUDIO ANALOGUE EXTERNALS T 8 18 26 53 E THVA 1 SAW 36 125 pL 16 27 56 RESETAUDIO n i gt A PLOP 37 9118
350. y all IC s supplied by the 3V3 due to overvoltage 12V on 3V3 line It is recommended to measure first the FET 7U08 or others FET s on shortcircuit before activating SDM via the service pads The abbreviations SP and MP in the figures stand for e protection or error detected by the Stand by Processor the 3V3 detection fails and thus error layer 2 18 is blinking while the TV is restarted via SDM the Stand by Processor will protection error detected by the MIPS Main enable the 3V3 but the TV set will not go to protection now TOE Ol The TV will stay in this situation until it is reset Mains AC Power supply interrupted Caution in case the start up in this Mains off Mains on WakeUp requested WakeUp Acquisition needed No data Acquisition required tact SW pushed last status is hibernate after mains ON Stby Tact switch Pushed last status is hibernate after mains ON Tact switch pushed Hibernate On Semi St by GoToProtection Active St by requested tact SW pushed WakeUp requested SDM GoToProtection Protection i 1 17660 124 eps 140308 Figure 5 3 Transition diagram 2009 May 08 Service Modes Error Codes and Fault Finding Q549 2E 5 Mains is applied Protection Standby Supply starts running All standby supply voltages become available
351. yj 3 4 GREEN Mp a 5 s A 8 93181 1 GREEN yy RED gt 2 4 93034 5 4 GREEN gt 3 5 RED gt 2e 4 93154 5 6 RUE BLUE y 1 5 93184 4 BUE 1 1 93031 8 6 yj 1 1 93151 8 GND_HS GND_HS x e F340 F341 F342 3338 3341 3336 F343 560R 3340 3344 390R 3337 19 1 560 3343 3347 3908 3339 18 19 1 5 93064 4 8 93061 6 930603 3 932 9 560R 3346 1 5 3350 3908 3342 GREEN6 GND_HS 4 99194 5 93193 6 1 GREEN6 GND_HS M G R RED6 RED6 1 3349 3852 3355 3369 3370 3371 3372 3373 3374 T T T T m T T 560R 3353 1 5 3356 1 5 3384 1 5 3385 1 5 3386 1K5 3387 1K5 3388 1K5 3389 1K5 3390 560R 1 5 3391 1 5 390R BLUES BLUES 3335 4 F345 F346 B R G RED 1 GREEN 1 BLUE 1 3310 3508 3345 71 5 3311 3908 3348 3312 390R 3351 3313 VLED1 F F307 gS 7307 825 3334 F308 x 1 i PWM B2 9317 3332 PWM B1 VLED1 F 8 3302 F

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