NEC PD75P308 User's Manual
Contents
1. TWO LINE AND THREE LINE SERIAL I O MODES SCK internal clock output Parameter SCK Cycle Time tkcy1 Conditions Output 1600 SCK High Low Level Widths tkH1 tKL1 Output It cv1 2 50 SI Set Up Time vs SCKT tsik1 150 SI Hold Time vs SCKT tks 400 SCK gt SO Output Delay Time tkso1 1 CI 100pF and CL are load resistance and load capacitance of the SO output line TWO LINE AND THREE LINE SERIAL I O MODES SCK external clock input 20 Parameter SCK Cycle Time tkcv2 Conditions SCK High Low Level Widths tku2 tKL2 SI Set Up Time vs SCKT tsik2 SI Hold Time vs SCKT tksi2 SCK gt so Output Delay Time tkso2 1kQ C 100pF and CL are load resistance and load capacitance of the SO output line uPD75P308 SBI MODE SCK internal clock output master Parameter SCK Cycle Time Conditions 1600 SCK High Low Level Widths tkcv 2 50 580 1 Set Up Time vs SCK T 150 SB0 1 Hold Time vs SCKT tkcv 2 5 SBO 1 Output Delay Time R 1 C 100pF 0 SCKT gt SBO 1 SBO 14 gt SCKL SBO 1 Low Level Width SBO 1 High Level Width and CL are load resistance and load capacitance of the SO outpu2. No part of this document may be copied or reproduced any form or by means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others The devices listed in this document are not suitable for uses in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for the applications not intended by NEC please contact our sales people in advance Application examples recommended by NEC Corporation Standard Computer Office equipment Communication equipment Testand Measurement equipment Machine tools Industrial robots Audio and Visual equipment Other consumer products etc Special Automotive and Transportation equipment Traffic control systems Antidisaster systems Anticrime system etc M4 92 6 MS DOS is a trademark of Microsoft Corporation PC DOS and PC AT are trademarks of IB
3. Output Timer event counter output Input Output Clock output Input Output Fixed frequency output for buzzer or for trimming the system clock SCK Input Output Serial clock input output SO SBO Input Output Serial data output Serial bus input output SI SB1 Input Output Input P00 Serial data input Serial bus input output Edge detection vector interrupt input either rising or falling edge detection is effective INT1 Input P10 P11 Edge detection vector interrupt input detection edge can be selected INT2 Input P12 Edge detection testable input rising edge detection KR0 KR3 Input Output P60 P63 Testable input output parallel falling edge detection KR4 KR7 Input Output P70 P73 Testable input output parallel falling edge detection S0 S23 Output Segment signal output 3 S24 S31 Output BP0 7 Segment signal output 3 COM0 COM3 Output Common signal output 13 Vico Vic2 LCD drive power BIAS External dividing resistor disconnect output High impedance LCDCL Input Output Externally expanded driver clock output Input SYNC Input Output Externally expanded driver sync clock output Input X1 X2 Input To connect the crystal ceramic oscillator to the main system clock generator When inputting the external clock input the ex
4. Operating Mode Specification Operating Mode Program memory address 0 clear mode Write mode Verify mode Program inhibit mode x Lor 11 NEC 75 308 3 2 PROGRAMI MEMORY WRITE PROCEDURE The program memory write procedure is as follows High speed program memory write is possible 1 Ground the unused pins through pull down resistors The X1 pin must be low 2 Supply 5 V to the and VP pins 3 Wait for 10 microseconds 4 Set program memory address 0 clear mode 5 Supply 6 V to the pin and 12 5 V to the VPP pin 6 Set program inhibit mode 7 Write data in 1 millisecond write mode 8 Set program inhibit mode 9 Set verify mode If data has been written connectly proceed to step 10 If data has not yet been written repeat steps 7 to 9 10 Write additional data for the number of times data was written X in steps 7 to 9 times 1 milliseconds 11 Set program inhibit mode 12 Supply a pulse to the X1 pin four times to update the program memory address by 1 13 Repeat steps 7 to 12 to the last address 14 Set program memory address 0 clear mode 15 Change the voltages of Voo and VPP pins to 5 V 16 Turn off the power supply Steps 2 to 12 are illustrated below X time repetition Write Verify Additional Address T T data write increment VPP n4 n VpP x1 _ x E L _ deg x E pete input
5. This specified input output in bit units Internal pull up resistors can be specified in 4 bit units by software P40 43 Input Output N ch open drain 4 bit input output port PORTA Data input output pin for writing and verifying of program memory PROM lower 4 bits High impedance P50 P53 Input Output N ch open drain 4 bit input output port PORT5 Data input output pin for writing and verifying of program memory PROM upper 4 bits High impedance P60 P61 P62 P63 Input Output Programmable 4 bit input output port PORT6 This port can be specified for input output in bit units Internal pull up resistors can be specified in 4 bit units by software P70 P71 P72 P73 Input Output 4 bit input output port PORT7 Internal pull up resistors can be specified in 4 bit units by software BPO BP1 BP2 BP4 BP5 BP6 BP7 1 bit output port BIT PORT Shared with a segment output pin 1 Circles indicate schmitt trigger inputs Can directly drive LED For 7 Vici indicated below are selected as the input source However the output level is changed depending on 7 and the Vic external circuits uPD75P308 1 2 NON PORT PINS Input Output Input Also Served As Function Timer event counter external event pulse input When Reset Input Output Circuit TYPE
6. D P50 P53 Data input AD ata input MDO N N N P30 12 uPD75P308 3 3 PROGRAM MEMORY READ PROCEDURE The contents of the program memory can be read in the following procedure 1 2 3 4 5 6 7 Ground the unused pins through pull down resistors The X1 pin must be low Supply 5 to the Vpp and VP pins Wait for 10 microseconds Set program memory address 0 clear mode Supply 6 V to the Vpp pin and 12 5 to the VPP pin Set program inhibit mode Set verify mode Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times 8 9 10 11 Set program inhibit mode Set program memory address 0 clear mode Change the voltages of and VPP pins to 5 V Turn off the power supply Steps 2 to 9 are illustrated below Vee EP V DD Voo 1 RU I Vop a Gre P50 P53 oo Y ERE P30 Dl aaao 1 D2 P32 P33 13 NEC uPD75P308 3 4 ERASURE uPD75P308K ONLY The contents of the data programmed to the uPD75P308 can be erased by exposing the window of the program memory to ultraviolet rays The wavelength of the ultraviolet rays used to erase the contents is about 250 nm and the quantity of the ultraviolet rays necessary for complete erasure is 15 W s cm ultraviolet ray intensity x erasure time When a comme
7. XT1 High Level Output Voltage Ports 0 2 3 6 7 BIAS 1 7 1004A Low Level Output Voltage Ports 0 2 3 6 7 Ports 3 4 5 lo 15mA lo 1 6mA SBO 1 Open drain Pull up gt 1kQ BP0 7 lo 100uA High Level Input Leakage Current Vin Other than below X1 X2 XT1 Vin 10V Ports 4 5 Low Level Input Leakage Current Vin OV Other than below X1 X2 XT1 High Level Output Leakage Current Vout Other than below Vout 10V Ports 4 5 Low Level Output Leakage Current Vout OV Internal Pull Up Resistor Ports 0 1 2 3 6 7 except POO Vin OV LCD Drive Voltage LCD Output Voltage Deviation Common lo 5 uA LCD Output Voltage Deviation Segment lo 1 HA Vicpo Vucpi Vicp Vicp2 x 3 2 7 V Vico lt 18 Supply Current When using two of and two of BP4 BP7 for output at the same time Voltage deviation means the difference between the ideal segment or common output value Vicon 0 1 2 and output voltage 4 19MHz crystal 4 6 oscillator C12 2 22 HALT mode 32 kHz 5 crystal oscillator HALT mode XT1 20V STOP mode Currents for the built in pull up resistor are not included Including when
8. 1 8 0 2 0 07179 bos L 0 8 0 2 0 031 0 908 0 154942 0 006 0 004 0 15 0 006 P 2 7 0 106 Q 0 1 0 1 0 004 0 004 5 3 0 MAX 0 119 MAX uPD75P308 80 PIN CERAMIC WOFN NOTE Each lead centerline is located within 0 08 mm 0 003 inch of its true position T P at maximum material condition X80KW 80A 1 ITEM MILLIMETERS INCHES A 20 0 0 4 0 787 0 917 B 19 0 0 748 C 13 2 0 520 D 14 2 0 4 0 559 0 016 1 64 0 065 F 2 14 0 084 G 4 064 MAX 0 160 MAX H 0 51 0 10 0 020 0 004 0 08 0 003 J 0 8 T P 0 031 T P K 1 0 0 2 0 039 0 008 Q C 0 5 C 0 020 R 0 8 0 031 S 0 043 T R3 0 R 0 118 U 12 0 0 472 W 0 75 0 2 0 030 0 009 29 NEC 75 308 6 RECOMMENDED SOLDERING CONDITIONS It is recommended that uPD75P308 be soldered under the following conditions For details on the recommended soldering conditions refer to Information Document Semiconductor Devices Mounting Manual 1 616 The soldering methods and conditions are not listed here consult NEC Table 6 1 Soldering Conditions uPD75P308GF 3B9 80 pin plastic QFP 14 x 20 mm Symbol for Recommended Condition Wave Soldering Soldering bath temperature 260 C max WS60 162 1 time 10 seconds max number of times 1 pre heating temperature 120 C max packag
9. P70 KR7 P73 BASIC INTERVAL TIMER O TIMER EVENT COUNTER 0 INTTO WATCH TIMER INTW flep SERIAL INTERFACE INTCSI INTERRUPT CONTROL SEO BUFFER 16 PROGRAM MEMORY PROM 8064 x 8 BITS DECODE AND CONTROL GENERAL REG MEMORY RAM 512 x 4 BITS CLOCK OUTPUT CLOCK CONTROL DIVIDER O PCL P22 SYSTEM CLOCK GENERATOR XI1 XT2 X1 2 STAND BY CONTROL PORT1 PORT2 CONTROLLER DRIVER P00 P03 P10 P13 P20 P23 P30 P33 MD0 MD3 P40 P43 P50 P53 P60 P63 P70 P73 S0 S23 S24 BP0 S31 BP7 COM0 COM3 Vico 5 OLCDCL P30 OSYNC P30 INVHOVIG JAN 80 dSLdd NEC 75 308 T PIN FONGTIONS 5 EIC INI 5 1 2 NON PORT PINS u 6 1 3 CIRCUITS 7 1 4 NOTES ON USING POO INT4 AND RESET a 9 2 DIFFERENCES BETWEEN uPD75P308 AND UPD75308 10 3 WRITING AND VERIFYING PROM PROGRAM MEMORY 11 3 1 OPERATION MODES FOR WRITING VERIFYING PROGRAM MEMORY 11 3 2 PROGRAM M
10. Ta 10 to 70 C Parameter Symbol Conditions Data Retention Supply Voltage Data Retention Supply 2 0V Current Release Signal Set Time Oscillation Stabilization Released by RESET Wait Time Released by interrupt 1 Does not include current folowing through internal pull up resistor 2 The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started 3 Depends on the setting of the basic interval timer mode register BTM as follows WAIT time fx 4 19 MHz 27 fx approx 250 ms 2 fx approx 31 3 ms 2 5 fx approx 7 82 ms 2 3 fx approx 1 95 ms DATA RETENTION TIMING releasing STOP mode by RESET Internal reset operation HALT mode 0 STOP mode e a Operation mode Data retention mode Vpp 4 STOP instruction execution RESET tWAIT R DATA RETENTION TIMING standby release signal releasing STOP mode by interrupt HALT mode STOP mode gt Operation mode Data retention mode STOP instruction execution Standby release signal interrupt request I 25 uPD75P308 DC PROGRAMMING CHARACTERISTICS 25 5 6 0 0 25V VPP 12 5 0 3V Vss OV Parameter Conditions Other than X1 or X2 Hi
11. below are used Note that no address input pins are provided because the address is updated by the clock input through the X1 pin Pin Name Function VPP Applies voltage when program memory is written verified normally at potential X1 X2 These pins input clock that updates address when program memory is written verified To X2 pin input signal 180 out of phase in respect to signal to X1 pin MD0 MD3 These pins select operation mode when program memory is written verified P40 P43 Lower 4 P50 P53 Upper 4 These pins input output 8 bit data when program memory is written verified Power supply voltage application pin Apply 5V 5 to this pin during normal operation and 6V when program memory is written verified Note 1 Always cover the erasure window of the uPD75P308K with a light opaque film except when the contents of the program memory are erased 2 The one time PROM model uPD75P308GF is not equipped with a window and therefore the contents ofthe program memory ofthis model cannot be erased by exposing itto ultraviolet rays 3 1 OPERATION MODES FOR WRITING VERIFYING PROGRAM MEMORY When 6V is applied to the pin of the uPD75P308 with 12 5V applied to the VPP pin the uPD75P308 is set in the program memory write verify mode In this mode the following operation modes can be set by using the MDO MD3 pins At this time pull down the levels of all the other pins to Vss
12. grade on the devices and its recommended applications The function common to the one time PROM and EPROM types of product is referred to as PROM throughout this document The information in this document is subject to change without notice Document No 1 2472 D IC 7208C mark shows major revised points Date Published November 1993 P Printed in Japan NEC Corporation 1989 uPD75P308 PIN CONFIGURATION 0 o 400 C 511 80 79 78 77 76 75 74 73 7271 O gt N gt O gt N O N N N o 25 26 27 28 29 BIAS O 10 59 58 S7 O S6 55 OS4 53 052 O O O P40 O P41 O P42 O v 9 e e eo P43 O 6 4580C 5 0 7 Vss 70 69 68 34 35 36 37 P50 O P51 O 52 P53 O P73 KR7 P72 KR6 71 5 POO INT4 O P01 SCK O P02 SO SB0 O n n n n Bn n n B On gt N O P70 P63 P62 P61 P60 2 P31 P30 P23 P22 P21 P20 12 11 P10 KR4 KR3 KR2 KR1 KR0 MD3 MD2 SYNC MD1 LCDCL MD0 BUS PCL PTO0 P13 TI0 NT2 NT1 NTO SI SBI TIO P13 PTOO P20 BUZ P23 SI SBI PO3 SO SBO P02 SCK P01 INTO P10 INT1 P11 INT2 P12 INT4 POO KRO P60 KR3 P63 KR4
13. in dotted line in the figures as follows to avoid adverse influences on the wiring capacity Keep the wiring length as short as possible Do notcross the wiring over the other signal lines Do not route the wiring in the vicinity of lines through which a high alternating current flows Always keep the ground point of the capacitor of the oscillator circuit at the same potential as Do not connect the power source pattern through which a high current flows Do not extract signals from the oscillation circuit RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK CERAMIC OSCILLATOR 10 to 70 C 16 Oscillation Voltage Range V C1 C2 MIN MAX Manufac External Capacitance pF turer Product Name CSA 2 00MG 30 30 CSA 4 19MG 30 30 CSA 4 19MGU 30 30 CST 4 19MG 30 pF internal 30 pF internal uPD75P308 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS 10 to 70 C 5 V 5 Recommended Oscillator Constants Crystal Oscillation frequency Conditions Oscillation stabilization time External Clock XT1 input frequency fx XT1 input high low level widths txt Time required for oscillation to stabilize after reaches the minimum value of the oscillation voltage range Caution When using the oscillation circuit of the subsystem clock wire
14. 001 R EP 75308GF R EV 9200G 80 Emulation prove for uPD75P308GF provided with 80 pin conversion socket EV 9200G 80 PG 1500 PROM programmer PA 75P308GF programmer adapter solely used for uPD75P308GF It is connected to PG 1500 PA 75P308K IE Control Program PG 1500 Controller RA75X Relocatable Assembler 1 Maintenance product 2 Not provided with IE 75001 R 3 Ver 5 00 5 00A has a task swap function but this function cannot be used with this software programmer adapter solely used for uPD75P308K It is connected to PG 1500 Host machine e 9800 series MS DOS Ver 3 30 to 5 00 3 IBM PC AT PC DOS Ver 3 1 Remarks For development tools from other companies refer to 75X Series Selection Guide IF 151 31 NEC LPD75P308 APPENDIX B RELATED DOCUMENTS 32 uPD75P308 GENERAL NOTES ON CMOS DEVICES 1 ELECTRICITY ALL DEVICES Exercise care so that MOS devices are not adversely influenced by static electricity while being handled The insulation of the gates of the MOS device may be destroyed by a strong static charge Therefore when transporting or storing the MOS device use a conductive tray magazine case or conductive buffer materials or the metal case NEC uses for packaging and shipment and use grounding when assembling the MOS device system Do not leave the MOS device
15. 08 User s Manual IEM 5016 Table 2 1 Differences between uPD75P308 and uPD75308 Item 75 08 uPD75P308GF uPD75308GF Program Memory EPROM PROM one time model Mask ROM 0000H 1F7FH 0000H 1F7FH 0000H 1F7FH 8064 x 8 bits 8064 x 8 bits 8064 x 8 bits Pull up Resistor Ports 4 5 Not provided Mask option Dividing Resistor for LCD Driving Power Supply Not provided Mask option Pins 50 53 P30 MD0 P33 MD3 P30 P33 Pin Connection Pin 57 VPP NC Electrical Specifications Current dissipations and operating temperature ranges differ between uPD75P308 and 75308 For detail refer to the specification documents of each mode Operating Voltage Range 5V 5 2 7 6 0V Package 80 pin ceramic WOFN 80 pin plastic OFP 14 x 20 mm LCC w window Note 10 Others Noise immunity and noise radiation differ because circuit scale and mask layout are different The noise immunity and noise radiation differ between the PROM and mask ROM models To replace the PROM model with the mask ROM model in the course of experimental production to mass production evaluate your system by using the CS mode not ES model of the mask ROM model uPD75P308 3 WRITING AND VERIFYING PROM PROGRAM MEMORY The program memory of the uPD75P308 is a PROM of 8064 x 8 bits To write data to or verify the contents of this PROM the pins listed in the table
16. 5 to 4150 1 impedance of the power source pull up resistor must be 50 KO minimum when a voltage higher than 10V is applied to ports 4 and 5 2 Effective value Peak value x NDuty 15 NEC uPD75P308 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS Ta Ceramic Oscillation 10 to 70 C 5 to 5 V Recommended Oscillator Conditions Constants frequency fo Oscillation stabilization After Voo came to MIN time of oscillation voltage range Crystal Oscilaltion frequency Oscillation stabilization time External Clock X1 input frequency XT X1 input high low level PD74HCU04 widths tx tx The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit For instruction execution time refer to AC Characteristics Time required for oscillation to stabilize after Voo reaches the minimum value of the oscillation voltage range or the STOP mode has been released 3 The oscillators below are recommended 4 When the oscillation frequency is 4 19 MHz lt fx lt 5 0 MHz do not select PCC 0011 as the instruction Ca execution time otherwise one machine cycle is set to less than 0 95 us falling short of the rated minimum value of 0 95 us ution When using the oscillation circuit of the main system clock wire the portion enclosed
17. DATA SHEET MOS INTEGRATED CIRCUIT uPD75P308 4 BIT SINGLE CHIP MICROCOMPUTER DESCRIPTION The uPD75P308 is a model of the uPD75308 equipped with a one time PROM or EPROM instead of an internal mask ROM Two types are available as the uPD75P308 The one time PROM type is ideal for production of a small quantity of many different types of application systems as data can only be written once to the one time PROM of this type Programs can be written and rewritten to the built in EPROM type making it ideal for system evaluation Detailed functions are described in the followig user s manual Be sure to read it for designing 75308 User s Manual IEM 5016 FEATURES uPD75308 compatible Memory capacity Program memory PROM 8064 x 8 bits Data memory RAM 512 x 4 bits Can be connected to a pull up resistor through software Ports 0 3 6 7 Open drain input output Ports 4 and 5 Single power source 5V 596 ORDERING INFORMATION Part Number Package Internal ROM UPD75P308GF 3B9 80 pin plastic OFP 14 x 20 mm One time PROM UPD75P308K 80 pin ceramic WOFN LCC w window EPROM QUALITY GRADE Part Number Package Quality Grade UPD75P308GF 001 3B9 80 pin plastic OFP 14 x 20 mm Standard UPD75P308K 80 pin Ceramic WOFN LCC w window Standard Please refer to Quality Grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality
18. EMORY WRITE PROCEDURE essent ennt then tnn 12 3 8 PROGRAM MEMORY READ PROCEDURE L 13 3 4 ERASURE uPD75P308K ONLY uuu u anun sqa as 14 4 ELECTRICAL SPECIFICATIONS iacet ie came teen E t ues 15 5z PACKAGE DRAMIN 28 RECOMMENDED SOLDERING CONDITIONS 30 APPENDIX DEVELOPMENT TOOLS asua nen nnns 31 APPENDIX B RELATED DOCUMENTS 32 uPD75P308 1 PIN FUNCTIONS 1 1 PORT PINS P01 Input Output Input Input Output Also Served As INT4 SCK P02 Input Output 50 580 P03 Input Output SI SBI Function 4 bit input port PORT0 Pull up resistors can be specified in 3 bit units for the P01 to P03 pins by software 8 Bit When Reset Input Output Circuit P10 P11 P12 P13 Input INTO INT1 INT2 TIO With noise elimination function 4 bit input port PORT1 Internal pull up resistors can be specified in 4 bit units by software P20 P21 P22 P23 Input Output PTOO 4 bit input output port PORT2 Internal pull up resistors can be specified in 4 bit units by software P30 P31 P32 P33 2 Input Output Programmable 4 bit input output port
19. M Corporation
20. e surface temperature maximum number of days 2 days beyond this period 16 hours of pre baking is required at 125 Infrared Reflow Package peak temperature 230 C IR30 162 1 time 30 seconds max 210 C min number of times 1 maximum number of days 2 days beyond this period 16 hours of pre baking is required at 125 Package peak temperature 215 C VP15 162 1 time 40 seconds max 200 C min number of times 1 maximum number of days 2 days beyond this period 16 hours of pre baking is required at 125 Soldering Method Soldering Conditions Pin Partial Heating Pin temperature 300 max time 3 seconds max per side Number of days after unpacking the dry pack Storage conditions are 25 C and 6596RH max Caution Do not use two or more soldering methods in combination except the pin partial heating method Notice A model that can be soldered under the more stringent conditions infrared reflow peak temperature 235 C number of times 2 and an extended number of days is also available For details consult NEC 30 uPD75P308 APPENDIX A DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using uPD75P308 PROM writing tools Hardare Software E 75000 R IE 75001 R In circuit emulator for 75K series 1 75000 Emulation board for IE 75000 R and IE 75
21. gh Level Input Voltage X1 and X2 Other than X1 or X2 Low Level Input Voltage X1 and X2 Input Leakage Current ViN Vit or High Level Output Voltage 2 1 mA Low Level Output Voltage lo 1 6 mA Voo Supply Current Vee Supply Current MDO Vii MD1 Vin Notes 1 VPP must not exceed 13 5 V including the overshoot 2 Apply Voo before VPP and disconnect it after VPP AC PROGRAMMING CHARACTERISTICS 25 5 Vpp 6 040 25V VPP 12 5 0 3V Vss 0 26 Parameter Address Set Up Time vs Conditions Set Up Time vs MDOL Data Set Up Time MDOJ Address Hold Time vs MD0T Data Hold Time vs MDOT MDO T5 Data Output Float Delay Time VPP Set Up Time vs Voo Set Up Time vs Initial Program Pulse Width Additional Program Pulse Width MDO Set Up Time vs MD1T MDO Data Output Delay Time tov Vi MD1 Hold Time vs MDOT twiH MD1 Recovery Time vs twin 2 50 us tuir Program Counter Reset Time tPCR X1 Input High Low Level Width txH txL X1 Input Frequency fx Initial Mode Set Time ti MD3 Set Up Time vs MD1T Hold Time vs MD1J MD3 Set Up Time vs MDOL When data is read from program memory Address Data Outpu
22. h are off Schmitt trigger input with hysteresis characteristics TYPE E B P U R IN OUT O P U R enable gt data output disable P U R Pull Up Resistor TYPE B C P U R lt P U R Pull Up Resistor Schmitt trigger input with hysteresis characteristics P U R enable TYPE E E P U R P U R enable o F data IN OUT Type D output disable lt lt P U R Pull Up Resistor uPD75P308 Do data output disable P U R Pull Up Resistor IN OUT O P U R P U R output enable De disable gt o ve P output disable 77 N ES IL out data disable P n P U R Pull Up Resistor Vici SEG data Bit Port data Vic2 TYPE M A Middle voltage input buffer IN OUT NEC uPD75P308 P U R 2 4 IN OUT data L output disable q Ze P U R Pull Up Resistor 1 4 NOTES ON USING P00 INT4 AND RESET PINS In addition to the functions shown in sections 1 1 and 1 2 the 4 and RESET pin
23. on a plastic plate and do not touch the pins of the device Handle boards on which MOS devices are mounted similarly 2 PROCESSING OF UNUSED PINS CMOS DEVICES ONLY Fix the input level of CMOS devices Unlike bipolar or NMOS devices if a CMOS device is operated with nothing connected to its input pin intermediate level input may be generated due to noise and an inrush current may flow through the device causing the device to malfunction Therefore fix the input level of the device by using a pull down or pull up resistor If there is a possibility that an unused pin serves as an output pin whose timing is not specified each pin should be connected to Voo or GND through a resistor Refer to Processing of Unused Pins in the documents of each devices STATUS BEFORE INITIALIZATION ALL MOS DEVICES The initial status of MOS devices is undefined upon power application Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level the initial status of the device is notcontrolled during the production process The output status of pins I O setting and register contents upon power application are not guaranteed However the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed When using a device with a reset function be sure to reset the device after power application 33 NEC uPD75P308
24. rcially available ultraviolet ray lamp wavelength 254 nm intensity 12 mW cm is used about 15 to 20 minutes is required Note 1 contents of the program memory may be erased when the uPD75P308 is exposed for a long time to direct sunlight or the light of fluorescent lamps To protect the contents from being erased mask the window of the program memory with the light opaque film supplied as an accessory with the UV EPROM products 2 Toerasethe memory contents the distance between the ultraviolet ray lamp and the uPD75P308 should be 2 5 cm or less Remarks The time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the surface condition dirt of the window of the program memory 14 uPD75P308 4 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 25 Parameter Supply Voltage Conditions 0 3 to 7 0 Supply Voltage Input Voltage Other than ports 4 or 5 0 3 to 413 5 0 3 to Ports 4 and 5 Open drain 0 3 to 11 Output Voltage 0 3 to High Level Output Current 1 Pin 15 pins 30 Low Level Output Current Operating Temperature Peak value 30 One pin Effective value 15 Peak value Total of ports 0 2 3 5 Effective value Peak value Total of ports 4 6 7 Effective value 10 to 70 Storage Temperature 6
25. s also have a function to set a test mode for IC testing in which the internal operations of the uPD75P308 are tested When a voltage higher than Vpp is applied to either of these pins the test mode is set This means that even during ordinary operation the uPD75P308 may be set in the test mode if a noise exceeding Von is applied For example if the wiring length of the 4 or RESET pin is too long noise superimposed on the wiring line of the pin may cause the above problem Therefore keep the wiring length of these pins as short as possible to suppress the noise otherwise take noise preventive measures as shown below by using external components Connect diode with low Vr between Vpp e Connect capacitor between and POO INT4 RESET pin and POO INT4 RESET pin V Diode with V bp low Vr POO INT4 RESET POO INT4 RESET uPD75P308 2 DIFFERENCES BETWEEN 4PD75P308 AND 4PD75308 The uPD75P308 is model of the wPD75308 and is equipped with a PROM instead of a mask ROM Programs can be rewritten to the PROM of the uPD75P308 Table 2 1 shows the differences between the LPD75P308 and uPD75308 You should fully consider these differences when you debug or produce your application system on an experimental basis by using the PROM model and then proceed to mass produce the system by using the mask ROM model For the details of the CPU and the internal hardware refer to uPD753
26. t Delay Time When data is read from program memory Address Data Output Hold Time When data is read from program memory MD3 Hold Time MDOT When data is read from program memory MD3 Data Output Float Delay Time When data is read from program memory 1 These symbols are the corresponding uPD27C256 symbols 2 The internal address signal is incremented by 1 at the fourth rising edge of X1 input The internal address is not connected to any pin uPD75P308 PROGRAM MEMORY WRITE TIMING x1 P40 P43 P50 P53 DO D1 D2 D3 PROGRAM MEMORY READ TIMING Vep Vpp 1 Vpp V X1 P40 P43 P50 P53 D0 D1 D2 D3 lt LV0 lt 05 bu lt 27 uPD75P308 5 PACKAGE DRAWINGS 80 PIN PLASTIC OFP 14x20 1 Each lead centerline is located within 0 15 mm 0 006 inch of its true position T P at maximum material condition 28 detail of lead end P80GF 80 3B9 2 MILLIMETERS 5 23 6 0 4 0 929 0 016 20 0 0 2 0 79510 008 C 14 0 0 2 0 551 0 008 D 17 6 0 4 0 693 0 016 1 0 0 039 0 8 0 031 0 35 0 10 0 014 0 006 0 15 0 006 J 0 8 T P 0 031 T P K
27. t line SBI MODE SCK external clock output master Parameter SCK Cycle Time Conditions SCK High Low Level Widths SBO 1 Set Up Time vs SCKT 580 1 Hold Time SCKT 5 SBO 1 Output Delay Time 1kQ C 100pF 5 580 W SBO 14 SCK SBO 1 Low Level Width SBO 1 High Level Width and CL are load resistance and load capacitance of the SO output line 21 NEC LPD75P308 AC TIMING TEST POINT excluding X1 and XT1 inputs 0 8 Voo 0 8 Voo Test points 0 2 Voo 0 2 CLOCK TIMING X1 input 0 5V 049 XT1 input 0 5V 0 4V TIO TIMING 22 NEC uPD75P308 SERIAL TRANSFER TIMING THREE LINE SERIAL I O MODE TWO LINE SERIAL I O MODE lt tkcy gt n SB0 1 23 NEC uPD75P308 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER lt TKCY3 4 gt Yn 151 3 4 1 513 4 5 0 1 503 4 COMMAND SIGNAL TRANSFER lt tkcy3 4 gt n 151 3 4 gt lt 10513 4 SB0 1 KSO3 4 INTERRUPT INPUT TIMING TINTL gt tiNTH INTO 1 2 4 KRO 7 RESET INPUT TIMING TRSL gt 24 NEC uPD75P308 LOW VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
28. ternal clock to pin X1 and the reverse phase of the external clock to pin X2 To connect the crystal oscillator to the subsystem clock generator When the external clock is used in XT1 inputs the external clock In this case pin XT2 must be left open Pin XT1 can be used as 1 bit input test pin Input System reset input low level active Input Output P30 P33 To select mode when writing verifying of program memory PROM Program voltage application when writing and verifying of program memory PROM Connect during the normal operation Apply 12 5V when writing verifying EPROM Positive power supply GND Circles indicate schmitt trigger inputs These pins are provided for future system expansion At present these pins are used only as pins P30 and P31 3 For these display output Vicx indicated below are selected as the input source 50 to S31 Vici COMO to COM2 Vic COM3 Vico However display output level varies depending on the particular display output and Vicx external circuit uPD75P308 1 3 PIN INPUT OUTPUT CIRCUITS The following shows a simplified input output circuit diagram for each pin of the uPD75P308 for TYPE E B 2 Input buffer of CMOS standard TYPE D for TYPE E B F A output disable Push pull output that can be set in a output high impedance state both P ch and N c
29. the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity Keep the wiring length as short as possible Do cross the wiring over the other signal lines Do not route the wiring in the vicinity of lines through which a high alternating current flows Always keep the ground point of the capacitor of the oscillator circuit at the same potential as Do not connect the power source pattern through which a high current flows Do not extract signals from the oscillation circuit The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit When using the subsystem clock therefore exercise utmost care in wiring the circuit CAPACITANCE Ta 25 C Von 0 V Parameter Input Capacitance Conditions f21MHz Output Capacitance Input Output Capacitance Pins other than thosemeasured are at 0 V 17 uPD75P308 DC CHARACTERISTICS Ta 10 to 70 C 5V 5 Parameter High Level Input Voltage Conditions Ports 2 3 Ports 0 1 6 7 RESET Ports 4 5 Open drain X1 XT1 Low Level Input Voltage Ports 2 3 4 5 Ports 0 1 6 7 RESET X1
30. the subsystem clock is operated When operated with the subsystem clock by setting the system clock control register SCC to 1001 to stop the main system clock operation When operand in the high speed mode with the processor clock control register PCC set to 0011 uPD75P308 AC CHARACTERISTICS Ta 10 to 70 VDD 5V 5 Operation Other Than Serial Transfer Parameter Conditions CPU Clock Cycle Time oc w main system clock Minimum Instruction Execution Time w subsystem clock 1 Machine Cycle TIO Input Frequency fn TIO Input High Low Level Widths trip trit InterruptinputHigh Low Level tintn INTO Widths tiNTL KRO 7 INT1 2 4 T 2 2tcv or 128 fxx depending on the setting of RESET Low Level Width tRSL tey vs with main system clock The CPU clock cycle time is determined A 64r bythe oscillation frequency ofthe connected 60 gt oscillator system clock control register SCC and processor clock control register PCC 5 The figure on the right is cycle time vs 4 supply voltage Vpp characteristics at the main system clock the interrupt mode register IM0 Cycle time tcy us 0 5 3 4 Supply voltage Voo V 5 19 uPD75P308 SERIAL TRANSFER
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