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National Instruments HPC167064 User's Manual

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1. Functional Modes of Operation Continued Security Level 2 This security level prevents programming of the on chip EPROM or the ECON registers thereby providing WRITE protection Read accesses to the on chip EPROM or ECON registers may be accomplished without constraint EPROM Read accesses to the on chip EPROM may be accomplished without constraint in NORMAL RUNNING mode Security Level 1 This security level prevents programming of the on chip EPROM or ECON registers thereby providing registers write protection Read accesses to the on chip ECON regis ters may be accomplished without constraint in EPROM mode Read accesses to the on chip EPROM will produce ENCRYPTED data in EPROM READ accesses to the on chip EPROM during NORMAL RUNNING mode are sub ject to Runtime Memory Protection Under Runtime Mem ory Protection only instruction opcodes stored within the on chip EPROM are allowed to access the EPROM as oper and If any other instruction opcode attempts to use the contents of EPROM as an operand it will receive the hex value FF The Runtime Memory Protection feature is de signed to prevent hostile software running from external memory or on chip RAM from reading secured EPROM data Transfers of control into or out of the on chip EPROM such as jump or branch are not affected by Runtime Mem ory Protection Interrupt vector fetches from EPROM pro ceed normally and are not affected by Runtime Memory P
2. WS 65 Data Input Valid after RD Falling Edge 85 ns E ipw etc WS 10 RD Pulse Width 140 ns tor tc 15 Hold of Data Input Valid after RD Rising Edge 0 60 ns tropa tc 15 Bus Enable after RD Rising Edge 85 ns 8 tanw Yate 5 ALE Falling Edge to WR Falling Edge 45 ns mm 6 tww 34 WS 15 WR Pulse Width 160 ns 2 ty sic WS 5 Data Output Valid before WR Rising Edge 145 ns tuw 5 Hold of Data Valid after WR Rising Edge 20 ns tpAR 14 WS 50 Falling Edge of ALE to Falling Edge of 75 ns 5 8 2 tRwR tc RDY Pulse Width 100 ns 30 MHz AC Electrical Characteristics See Notes 1 and 4 and Figures 7 thru 5 5V 10 TA 0 C to 70 C for HPC467064 Symbol and Formula Parameter Min Max Units Notes fc Operating Frequency 2 30 MHz 1 fc CKI Clock Period 33 500 ns CKI High Time 22 5 ns tckiL CKI Low Time 22 5 ns 5 tc 2 fc CPU Timing Cycle 66 ns 2 twAIT tc CPU Wait State Period 66 ns 9 tpc1coR Delay of CK2 Rising Edge after CKI Falling Edge 0 55 ns Note 2 tpc1C2F Delay of CK2 Falling Edge after Falling Edge 0 55 ns Note 2 fu fc 8 External UART Clock Input Frequency 3 75 MHz fuw External MICROWIRE PLUS Clock Input Frequency 1 875 MHz fxiN fc 22 External Timer Input Frequency 1 364 MHz txiN tc Pulse Width for Timer Inputs 66 ns o tu
3. Note 4 10 pA Ci Input Capacitance Note 2 10 pF Cio Capacitance Note 2 20 pF OUTPUT VOLTAGE LEVELS Logic High CMOS 10 pA Note 2 Voc 0 1 01 V Logic Low CMOS 10 pA Note 2 Port Drive CK2 7 2 4 04 Y Voi2 0 15 B10 B11 B12 B15 lo 3 mA Other Port Pin Drive WO open drain 1 6 mA except WO 2 4 04 v 0 9 B13 B14 lo 0 5 mA ST1 ST2 Drive lou 6 2 4 0 4 V lo 1 6 Vous Port Drive 0 15 B10 B11 B12 B15 1mA 2 4 04 V Vols when used as External Address Data Bus lo 3 VRAM RAM Keep Alive Voltage Note 3 2 5 Voc V loz TRI STATE Leakage Current Vin Vin Voc 5 pA Note 1 Icc4 measured with no external drive and 0 0 and EXM Vcc 1 is measured with RESET GND is measured with NMI driven to and Vj 4 with rise and fall times Note 2 This is guaranteed by design and not tested Note 3 Test duration is 100 ms less than 10 ns Note 4 The EPROM mode of operation for this device requires high voltage input on pins EXM Vpp 13 14 15 16 and 17 This will increase the input leakage current above the normal specification when driven to voltages greater than Vcc 0 3V See NORMAL RUNNING MODE 20 MHz AC
4. PRELIMINARY National Semiconductor August 1992 HPC167064 HPC467064 High Performance microController with a 16k UV Erasable CMOS EPROM General Description The HPC167064 is a member of the HPC family of High further current savings The HPC 167064 is available only in Performance microControllers Each member of the family 68 LDCC package has the same core CPU with a unique memory and configuration to suit specific applications The 167064 Features has 16 kbyte high speed UV erasable electrically pro HPC family core features grammable CMOS EPROM This is ideally suited for appli 16 bit architecture both byte and word operations cations where fast turnaround pattern experimentation and 16 bit data bus ALU and registers code confidentiality are important requirements The 64 kbytes of direct memory addressing HPC167064 can serve as a stand alone emulator for either FAST 200 ns for fastest instruction when using the HPC16064 or the HPC16083 Two configuration regis 20 0 MHz clock 134 ns at 30 0 MHz ters have been added for emulation of the different chips High code efficiency most instructions are single The on chip EPROM replaces the presently available user byte ROM space The on chip EPROM can be programmed via a 16 x 16 multiply and 32 x 16 divide DATA I O UNISITE There are security features added to Eight vectored interrupt sources the chip to implement READ E
5. FIGURE 2 Input and Output for AC Tests Timing Waveforms JoctALER TL DD 11046 5 FIGURE 3 CK1 CK2 ALE Timing Diagram tarw wo TL DD 11046 6 FIGURE 4 Write Cycle Timing Waveforms Continued ALE PORTA ADDR OUT TL DD 11046 7 FIGURE 5 Read Cycle ALE 1 0 ADDR TRI STATE RD or WR N RDY r toar TL DD 11046 8 FIGURE 6 Ready Mode Timing TL DD 11046 9 FIGURE 7 Hold Mode Timing Timing Waveforms Continued SK tuwH I tony gt 0 X TL DD 11046 10 FIGURE 8 MICROWIRE Setup Hold Timing SI TRE TRI STATE TRI STATE DATA OUT VALID prov TL DD 11046 11 FIGURE 9 UPI Read Timing gt TRI STATE DATA IN PORT A VALID WRRDY HPC RD INT TL DD 11046 12 FIGURE 10 UPI Write Timing Functional Modes of Operation There are two primary functional modes of operation for the HPC167064 EPROM Mode Normal Running Mode EPROM MODE In the EPROM mode the HPC167064 is configured to proximately emulate a standard NMC27C256 EPROM Some dissimilarities do exist The most significant one is that HPC167064 contains only 16 kbytes of programmable memory rather than the 32 kbytes in 27C256 An HPC167064 in the EPROM mode can be programmed with a Data machine Given below is the list of f
6. W SP SP 2 SP POP Pop Stack to Memory SP 2 SP W SP gt W LDS Load A incr decr B A B 1 or 2 gt Skip on condition Skip next if B greater less than K XS Exchange incr decr B Mem B lt A B 1 or 2 B Skip on condition Skip next if B greater less than K REGISTER LOAD IMMEDIATE INSTRUCTIONS LDB Load B immediate imm B LDK Load K immediate imm LD X Load X immediate X LD BK Load B and K immediate imm B imm ACCUMULATOR AND C INSTRUCTIONS CLR A Clear A 0 5 1 gt DEC Decrement A 1 A COMP A Complement A 1 s complement of A SWAPA Swap nibbles of A A 15 12 lt A 11 8 lt A 7 4 lt 3 0 RRCA Rotate A right thru C A15 gt 0 RLCA Rotate A left thru C lt 15 lt lt 0 lt SHR Shift A right 0 A15 gt A0 C SHLA Shift A left lt A15 lt lt A0 lt 0 SC Set 1C RC Reset C 0 C IFC IF C Do next if C 1 IFNC IF not C Do next if C 0 TRANSFER OF CONTROL INSTRUCTIONS JSRP Jump subroutine from table PC W SP SP 2 SP W table PC JSR Jump subroutine relative PC W SP SP 2 SP PC 4 15 1025 to 1023 JSRL Jump subroutine long PC W SP SP 2 SP PC 4 JP Jump relative short PC is 32 to 31 JMP Jump relative PC PC is 257 to 255 JMPL Jump relative long PC PC JID J
7. WO This is an active low open drain output that sig nals an illegal situation has been detected by the WATCHDOG logic ST1 Bus Cycle Status Output indicates first opcode fetch ST2 Bus Cycle Status Output indicates machine states skip interrupt and first instruction cycle RESET is an active low input that forces the chip to re start and sets the ports in a TRI STATE mode RDY HLD has two uses selected by a software bit It s ei ther an input to extend the bus cycle for slower memories or a HOLD request input to put the bus in a high impedance state for DMA purpos es no connection do not connect anything to this pin EXM Has two uses External memory enable active high which disables internal EPROM and maps it to external memory and is Vpp during EPROM mode El External interrupt with vector address FFF1 FFFO Rising falling edge or high low lev el sensitive Alternately can be configured as 4th input capture External interrupt which is internally OR ed with the UART interrupt with vector address FFF3 FFF2 Active Low Connection Diagram 15 4 12 2 EXUI B1 987654 52 B2 B3 1 GND B4 B5 B6 B7 wo 68 67 66 65 64 63 17 16 10 1 01 11 02 572 D3 RESET El 0 D4 A 05 167064 A2 06 07 4 5 AB P1 A7 P2 RDY HLD P3 NC DGND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 4
8. Register 0141 0140 T4 Timer 0128 ENUR Register 0126 TBUF Register 0124 RBUF Register UART 0122 ENUI Register 0120 ENU Register 0104 Port D Input Register 00 5 00 4 BFUN Register 00 3 00 2 DIR Register abdo RB 00 1 00 0 DIR A Register IBUF 00 6 Register UPI Control 00E3 00E2 Port B 00 1 00 0 Port A OBUF For ASB 00DE Reserved 00DD 00DC HALT Enable Register 00D8 Port I Input Register 0006 SIO Register 0004 IRCD Register 0002 IRPD Register gISters 00DO ENIR Register 00 00 X Register 00CD 00CC B Register 00 00 K Register 00C9 00C8 A Register HPC Core 00C7 00C6 PC Register Registers 00 5 00 4 SP Register 00C3 00C2 Reserved 00 0 PSW Register 00 00 Doo EID User RAM 0001 0000 26 Design Considerations Continue Designs using the HPC family of 16 bit high speed CMOS microcontrollers need to follow some general guidelines on usage and board layout Floating inputs are a frequently overlooked problem CMOS inputs have extremely high impedance and if left open can float to any voltage You should thus tie unused inputs to Vcc or ground either through a resistor or directly Unlike the inputs unused output should be left floating to allow the output to switch without drawing any DC current To reduce voltage transients keep the supply line s parasit ic inductances as low as possible by reducing trace
9. capture registers sive peripheral chips 52 general purpose lines memory mapped microCMOS process results in very low current drain Commercial 0 C to 70 C and military 55 C to and enables the user to select the optimum speed power 125 temperature ranges for 20 0 MHz commercial product for his system The IDLE and HALT modes provide 0 to 70 for 30 0 MHz Block Diagram HPc167064 with 16k EPROM shown m me Dn TL DD 11046 1 Series 320009 and TRI STATE are registered trademarks of National Semiconductor Corporation MICROWIRE PLUS and WATCHDOG are trademarks of National Semiconductor Corporation UNIX is a registered trademark of AT amp T Bell Laboratories IBM and PC AT are registered trademarks of International Business Machines Corp SunOS is a trademark of Sun Microsystems 1995 National Semiconductor Corporation TL DD11046 RRD B30M105 Printed S INOHd3 SONO 1 14 AN A94 19 043u020421U1 90 9 90 91 OdH Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Total Allowable Source or Sink Current 100 mA Vcc with Respect to GND 0 5V to 7 0V All Other Pins Vcc 0 5V to GND 0 5V Note Absolute maximum rating
10. it s more effective to distribute them among the ICs If the design has a fair amount of synchronous logic with outputs that tend to switch simultaneously additional de coupling might be advisable Octal flip flop and buffers in bus oriented circuits might also require more decoupling Note that wire wrapped circuits can require more decou pling than ground plane or multilayer PC boards A recommended crystal oscillator circuit to be used with the HPC is shown in Figure 29 See table for recommended component values The recommended values given in Table V have yielded consistent results and are made to match a crystal with a 20 pF load capacitance with some small allowance for layout capacitance A recommended layout for the oscillator network should be as close to the processor as physically possible entirely within 1 distance This is to reduce lead inductance from long PC traces as well as interference from other compo nents and reduce trace capacitance The layout contains a large ground plane either on the top or bottom surface of the board to provide signal shielding and a convenient loca tion to ground both the HPC and the case of the crystal It is very critical to have an extremely clean power supply for the HPC crystal oscillator Ideally one would like a Vcc and ground plane that provide low inductance power lines to the chip The power planes in the PC board should be decou pled with three decoupling capacitors
11. or 2 critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform can into the body or b support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 Email cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax 81 043 299 2408 Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Kowloon Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Hong Kong Fran ais Tel 49 0 180 532 93 58 Tel 852 2737 1600 Italiano Tel 49 0 180 534 16 80 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
12. the external inter rupt input on the slave HPC167064 MASTER SYSTEM 1 0 0 8 BIT 50 REGISTER si SHIFT CLOCK T N CLOCK A SELECT L 0 SK T A UNDERFLOW TL DD 11046 32 FIGURE 24 MICROWIRE PLUS HPC167064 SYSTEM 1 0 SK Dt 0 474 STATUS DISPLAY 602494 cs E PROM TL DD 11046 33 FIGURE 25 MICROWIRE PLUS Application 22 167064 UART HPC167064 contains software programmable UART The UART see Figure 26 consists of a transmit shift regis ter a receiver shift register and five addressable registers as follows a transmit buffer register a receiver buff er register RBUF a UART control and status register ENU a UART receive control and status register ENUR and a UART interrupt and clock source register ENUI The ENU register contains flags for transmit and receive func tions this register also determines the length of the data frame 8 or 9 bits and the value of the ninth bit in transmis sion The ENUR register flags framing and data overrun er rors while the UART is receiving Other functions of the ENUR register include saving the ninth bit received in the data frame and enabling or disabling the UART s Attention Mode of operation The determination of an internal or ex ternal clock source is done by the ENUI register as well as selecting the number of stop bits
13. 064 provides an additional 16 bit free running timer T8 with associated input capture register EICR Ex ternal Interrupt Capture Register and Configuration Regis ter EICON EICON is used to select the mode and edge of the El pin EICR is a 16 bit capture register which records the value of T8 which is identical to TO when a specific event occurs on the EI pin The timers T2 and T3 have selectable clock rates The clock input to these two timers may be selected from the following two sources an external pin or derived internally by TO WATCHDOG 16 16 SOFTWARE 15122 CONFIGURED SOFTWARE CONFIGURED CKI 16 TL DD 11046 27 FIGURE 19 Timers TO T1 and T8 with Four Input Capture Registers dividing the clock input Timer T2 has additional capability of being clocked by the timer T3 underflow This allows the user to cascade timers and T2 into a 32 bit timer coun ter The control register DIVBY programs the clock input to timers T2 and T3 see Figure 20 The timers T1 through T7 in conjunction with their registers form Timer Register pairs The registers hold the pulse du ration values All the Timer Register pairs can be read from or written to Each timer can be started or stopped under software control Once enabled the timers count down and upon underflow the contents of its associated register are automatically loaded into the timer SYNCHRONOUS OUTPUTS The flexible timer struct
14. 2 43 TL DD 11046 17 Top View Order Number HPC 167064 EL See NS Package Number EL68C Ports amp The highly flexible ports are similarly structured The Port A see Figure 11 consists of a data register and a direction register Port B see Figures 12 thru Figure 14 has an alternate function register in addition to the data and direction registers All the control registers are read write registers The associated direction registers allow the port pins to be individually programmed as inputs or outputs Port pins se lected as inputs are placed in a TRI STATE mode by reset ting corresponding bits in the direction register PORT A bit DATA REGISTER WRITE PORT READ DIR A DIRECTION REGISTER WRITE REGISTER Hro r zmmaz READ PORT A write operation to a port pin configured as an input causes the value to be written into the data register a read opera tion returns the value of the pin Writing to port pins config ured as outputs causes the pins to have the same value reading the pins returns the value of the data register Primary and secondary functions are multiplexed onto Port B through the alternate function register BFUN The sec ondary functions are enabled by setting the corresponding bits in the BFUN register TRISTATE BUFFER EIN TL DD 11046 19 FIGURE 11 Port I O Structure 13 Ports amp B continued ALTERNAT
15. 29 FIGURE 21 Timers T4 T7 Block Timer Applications The use of Pulse Width Timers for the generation of various waveforms is easily accomplished by the HPC167064 Frequencies can be generated by using the timer register pairs A square wave is generated when the register value is a constant The duty cycle can be controlled simply by changing the register value Synchronous outputs based on Timer T2 can be generated on the 4 outputs 0 3 Each output can be individually programmed to toggle on T2 underflow Register R2 con tains the time delay between events Figure 23 is an exam ple of synchronous pulse train generation T20UT TL DD 11046 31 FIGURE 22 Square Wave Frequency Generation WATCHDOG Logic The WATCHDOG Logic monitors the operations taking place and signals upon the occurrence of any illegal activity Ep 51 ITem TS2 9 4 TL DD 11046 30 FIGURE 23 Synchronous Pulse Generation The illegal conditions that trigger the WATCHDOG logic are potentially infinite loops and illegal addresses Should the WATCHDOG register not be written to before Timer TO overflows twice or more often than once every 4096 counts an infinite loop condition is assumed to have oc curred An illegal condition also occurs when the processor generates an illegal address when in the Single Chip modes Any illegal condition forces the WATCHDOG Out p
16. Bus Enable after HLDA Rising Edge 116 ns Note 5 tuas Address Setup Time to Falling Edge of URD 10 ns tUAH Address Hold Time from Rising Edge of UR 10 ns tRPw URD Pulse Width 100 ns toe URD Falling Edge to Output Data Valid 0 60 ns top Rising Edge of URD to Output Data Invalid 5 45 ns Note 6 tpRDY RDRDY Delay from Rising Edge of URD 70 ns twow UWR Pulse Width 40 ns 5 tups Input Data Valid before Rising Edge of UWR 10 ns HPC467064 Input Data Hold after Rising Edge of UWR 20 ns 167064 25 ns ta WRRDY Delay from Rising Edge of UWR 70 ns See NORMAL RUNNING MODE This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two 2 falling edges of the CK2 clock Note 40 pF Note 1 These AC Characteristics are guaranteed with external clock drive having 50 duty cycle and with less than 15 pF load on with rise and fall times and input less than 2 5 ns Note 2 Do not design with this parameter unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 is spec d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed If HLD falli
17. C Compiler HPC C Compiler User s Manual 424410883 001 Assembler Linker Librarian HPC Assembler Linker Librarian 424410836 001 Package for IBM PC AT User s Manual DIAL A HELPER Dial A Helper is a service provided by the Microcontroller Applications group Dial A Helper is an Electronic Bulletin Board Information system and additionally provides the ca pability of remotely accessing the development system at a customer site INFORMATION SYSTEM The Dial A Helper system provides access to an automated information storage and retrieval system that may be ac cessed over standard dial up telephone lines 24 hours a day The system capabilities include a MESSAGE SECTION electronic mail for communications to and from the Micro controller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities can be found The minimum require ment for accessing Dial A Helper is a Hayes compatible mo dem Voice If the user has a PC with a communications package then files from the FILE SECTION can be downloaded to disk for later use Order P N MDS DIAL A HLP Information System Package Contains Dial A Helper Users Manual Public Domain Communications Software FACTORY APPLICATIONS SUPPORT Dial A Helper also provides immediate factory applications support If a user is having difficulty in operating a MDS messages can be left on our electronic bulletin boar
18. E FUNCTION INPUT ALTERNATE PORT B BIT FUNCTION OUTPUT DATA REGISTER SELECT WRITE PORT B READ DIR B DIR B BIT DIRECTION REGISTER WRITE DIR B SELECT READ PORT B BFUN BIT ALTERNATE FUNCTION WRITE BFUN READ BFUN TL DD 11046 20 FIGURE 12 Structure of Port B Pins BO B1 B2 B5 B6 and B7 Typical Pins ALTERNATE FUNCTION INPUT PIN TOGGLE BFUN BIT ALT FUNCTION REGISTER READ BFUN READ PORT B DIR B BIT DIRECTION REGISTER WRITE DIR B READ DIR B TL DD 11046 21 FIGURE 13 Structure of Port B Pins B3 B4 B8 B9 B13 and B14 Timer Synchronous Pins 14 Ports A amp B continued WRITE PORT B READ DIR B DIR B BIT DIRECTION REGISTER WRITE DIR B READ PORT B BFUN BIT ALTERNATE FUNCTION WRITE BFUN READ BFUN FIGURE 14 Structure of Port B Pins B10 B11 B12 and B15 Pins with Bus Control Roles Operating Modes To offer the user a variety of and expanded memory options the HPC167064 has four operating modes The various modes of operation are determined by the state of both the EXM pin and the EA bit in the PSW register The state of the EXM pin determines whether on chip EPROM will be accessed or external memory will be accessed within he address range of the on chip EPROM The on chip EPROM range of the HPC167064 is C000 to FFFF 16 kbytes A logic 0 state on the pin will cause the HPC device o address on chi
19. Electrical Characteristics See Notes 1 and 4 and Figures 1 thru 5 5V 5 55 C to 125 C for HPC167064 and 5V 10 Ta 0 C to 70 C for HPC467064 Symbol and Formula Parameter Min Max Units Notes fc CKI Operating Frequency 2 20 MHz 1 fc CKI Clock Period 50 500 ns tckiH CKI High Time 22 5 ns Low Time 22 5 ns 5 2 fc CPU Timing Cycle 100 ns 4 lWAIT tc CPU Wait State Period 100 ns tpc1C2R Delay of CK2 Rising Edge after Falling Edge 0 55 ns Note 2 tpc1C2F Delay of CK2 Falling Edge after CKI Falling Edge 0 55 ns Note 2 fu fc 8 External UART Clock Input Frequency 2 fw External MICROWIRE PLUS Clock Input Frequency 1 25 MHz 5 fxiN fc 22 External Timer Input Frequency 0 91 MHz txin tc Pulse Width for Timer Inputs 100 ns 2 tuws MICROWIRE Setup Time Master 100 MICROWIRE Setup Time Slave 20 2 tuWH MICROWIRE Hold Time Master 20 ae MICROWIRE Hold Time Slave 50 tuwv MICROWIRE Output Valid Time Master 50 m MICROWIRE Output Valid Time Slave 150 9 tsALE 3 4 40 Falling Edge before ALE Rising Edge 115 ns 2 tuwP tc 10 HLD Pulse Width 110 ns thae tc 100 HLDA Falling Edge after HLD Falling Edge 200 ns Note 3 tHap 34 85 HLDA Rising Edge after Rising Edge 160 ns tgr 10 lt 66 Bus Float after HLDA Falling Edge 116 ns Note 5 Vatc 66
20. HPC167064 are single byte There are two especially code saving instructions JP is a 1 byte jump True it can only jump within a range of plus or minus 32 but many loops and decisions are often within a small range of program memory Most other micros need 2 byte instructions for any short jumps JSRP is a 1 byte subroutine call The user makes a table of the 16 most frequently called subroutines and these calls will only take one byte Most other micros require two and even three bytes to call a subroutine The user does not have to decide which subroutine addresses to put into the table the assembler can give this information EFFICIENT SUBROUTINE CALLS The 2 byte JSR instructions can call any subroutine within plus or minus 1k of program memory MULTIFUNCTION INSTRUCTIONS FOR DATA MOVE MENT AND PROGRAM LOOPING The HPC167064 has single byte instructions that perform multiple tasks For example the XS instruction will do the following 1 Exchange A and memory pointed to by the B register 2 Increment or decrement the B register 3 Compare the B register to the K register 4 Generate a conditional skip if B has passed K The value of this multipurpose instruction becomes evident when looping through sequential areas of memory and exit ing when the loop is finished BIT MANIPULATION INSTRUCTIONS Any bit of memory I O or registers can be set reset or tested by the single byte bit instructions The bits can be addressed di
21. LE Pulse Width 24 ns 5 tst 14 7 Setup of Address Valid before ALE Falling Edge 9 ns D typ ato 5 Hold of Address Valid after ALE Falling Edge 11 ns 30 MHz AC Electrical Characteristics Continue See Notes 1 and 4 and Figures 1 thru 5 Vcc 5V 10 Ta 0 C to 70 for HPC467064 Continued Symbol and Formula Parameter Min Max Units Notes 5 ALE Falling Edge to RD Falling Edge 12 ns 8 tacc tc WS 32 Data Input Valid after Address Output Valid 100 ns 5 trap 10 WS 39 Data Input Valid after RD Falling Edge 60 ns E taw etc WS 14 RD Pulse Width 85 ns tpn 34tc 15 Hold of Data Input Valid after RD Rising Edge 0 35 ns trpa tc 15 Bus Enable after RD Rising Edge 51 ns 9 tanw stc 5 ALE Falling Edge to WR Falling Edge 28 ns tww 34 lt WS 15 WR Pulse Width 101 ns ty 10 1 5 Data Output Valid before WR Rising Edge 94 ns thw tc 10 Hold of Data Valid after WR Rising Edge 7 ns tpaR Yatc WS 50 Falling Edge of ALE to Falling Edge of RDY 33 ns tawr tc RDY Pulse Width 66 ns This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two 2 falling edges of the CK2 clock Note 40 pF Note 1 These AC Characteristics are guaranteed with external clock drive on having 50 dut
22. NCRYPTED READ and Four 16 bit timer counters with 4 synchronous out WRITE privileges for the on chip EPROM These defined puts and WATCHDOG logic privileges are intended to deter theft alteration or uninten MICROWIRE PLUS serial 1 0 interface tional destruction of user code Each part is fabricated in CMOS very low power with two power save modes National s advanced microCMOS technology This process IDLE and HALT combined with an advanced architecture provides fast flex 16 kbytes high speed UV erasable electrically program ible 1 O control efficient data manipulation and high speed mable CMOS EPROM ee Stand alone emulation of HPC16083 and HPC16064 The HPC devices are complete microcomputers on a single family chip All system timing internal logic EPROM RAM and EPROM fi ti byt ble b are provided on the chip to produce a cost effective D AB Four selectable levels of security to protect on chip tions such as UART up to eight 16 bit timers with 4 input EPROM contents capture registers vectored interrupts WATCHDOG logic and MICROWIRE PLUS provide a high level of system 8 UART full duplex programmable baud rate integration The ability to address up to 64k bytes of exter Four additional 16 bit timer counters with pulse width nal memory enables the HPC to be used in powerful appli modulated outputs cations typically performed by microprocessors and expen Four input
23. ONS ADD Add MA MA carry C ADC Add with carry MA carry C ADDS Add short imm8 A imm8 carry gt C DADC Decimal add with carry MA MA Decimal SUBC Subtract with carry MA Meml MA carry DSUBC Decimal subtract w carry MA Meml MA Decimal carry MULT Multiply unsigned MA Meml MA amp X 0 K 0 C DIV Divide unsigned MA Meml rem X 0 K 0 C DIVD Divide Double Word unsigned X amp MA Meml rem X 0 carry gt C IFEQ If equal Compare MA amp Meml Do next if equal IFGT If greater than Compare MA amp Meml Do next if MA gt AND Logical AND MA and OR Logical OR or MA XOR Logical Exclusive OR MA xor MEMORY MODIFY INSTRUCTIONS INC Increment Mem 1 Mem DECSZ Decrement skip if 0 Mem 1 Men Skip next if Mem 0 28 HPC Instruction Set Description Continued Mnemonic Description Action BIT INSTRUCTIONS SBIT Set bit 1 gt Mem bit Reset bit 0 Mem bit If bit If Mem bit is true do next instr MEMORY TRANSFER INSTRUCTIONS LD Load Load incr decr X Mem X A X 1 or 2 gt X ST Store to Memory Mem X Exchange lt Mem Exchange incr decr lt Mem X X 1 or 2 gt X PUSH Push Memory to Stack W
24. OTE HPC167064 SERIES 32000 HOST SYSTEM CONTROLLER DP7304B SHARED MEMORY TL DD 11046 36 FIGURE 28 Shared Memory Application HPC 167064 Interface to Series 32000 System Design Considerations TABLE Memory Map of HPC167064 Emulating an HPC 16064 FFFF FFFO Interrupt Vectors 0128 ENUR Register FFEF FFDO JSRP Vectors 0126 TBUF Register FFCF FFCE 0124 RBUF Register UART po On Chip ROM 0122 ENUI Register 001 000 User 0120 ENU Register External Expansion 0104 Port D Input Register 04 03 Memory 00 5 00 4 BFUN Register 0301 0300 9 00 3 00 2 DIR Register RB des On Chip RAM EUN 00 1 00 0 DIR Register IBUF 01 1 01 0 00 6 Register UPI Control 00E3 00E2 PortB 0195 0194 WATCHDOG Register WATCHDOG Logic SOE ONES Port A OBUF Ports amp B 0192 TOCON Register 0191 0190 TMMODE Register 00DE Reserved 018F 018 DIVBY Register 00DD 00DC HALT Enable Register Port Control 018D 018C T3 Timer 0008 Port Input Register 018 018 Register 0006 SIO Register 0189 0188 T2 Timer Timer Block 0 73 0004 IRCD Register 0187 0186 R2 Register 0002 IRPD Register 0185 0184 12 Register R1 0000 Register 0183 0182 Register 1 OOCF 00CE X Register 0181 0180 Register 00CD 00CC Re
25. address condition The Expanded Nor mal mode is entered with the EXM pin pulled low logic 0 and setting the EA bit in the PSW register to 1 TABLE 1 HPC167064 Operating Modes Pin Bit Configuration Single Chip Normal 0 0 C000 FFFF On Chip Expanded Normal 0 1 C000 FFFF On Chip 0300 Off Chip Single Chip ROMless 1 0 C000 FFFF Off Chip Expanded ROMless 1 1 0300 FFFF Off Chip SINGLE CHIP ROMless MODE In this mode the on chip EPROM of the HPC167064 is not used The address space corresponding to the on chip EPROM is mapped into external memory so 16k of external memory may be used with the HPC167064 see Table The WATCHDOG circuitry detects illegal addresses ad dresses not within the on chip EPROM and RAM range The Single Chip ROMless mode is entered when the EXM pin is pulled high logic 1 and the EA bit is logic 0 EXPANDED ROM MODE This mode of operation is similar to Single Chip ROMless mode in that no on chip ROM is used however a full 64 kbytes of external memory may be used The illegal address detection feature of WATCHDOG is disabled The EXM pin must be pulled high logic 1 and the EA bit in the PSW register set to 1 to enter this mode Wait States The internal EPROM can be accessed at the maximum op erating frequency with one wait state With 0 wait states inter
26. and enabling or disabling transmit and receive interrupts The baud rate clock for the Receiver and Transmitter can be selected for either an internal or external source using two bits in the ENUI register The internal baud rate is pro grammed by the DIVBY register The baud rate may be se lected from a range of 8 Hz to 128 kHz in binary steps or T3 underflow By selecting a 9 83 MHz crystal all standard baud rates from 75 baud to 38 4 kBaud can be generated The external baud clock source comes from the pin The Transmitter and Receiver can be run at different rates by selecting one to operate from the internal clock and the other from an external source The HPC167064 UART supports two data formats The first format for data transmission consists of one start bit eight data bits and one or two stop bits The second data format for transmission consists of one start bit nine data bits and one or two stop bits Receiving formats differ from transmis sion only in that the Receiver always requires only one stop bit in a data frame UART Wake Up Mode The HPC167064 UART features a Wake Up Mode of opera tion This mode of operation enables the HPC167064 to be networked with other processors Typically in such environ ments the messages consist of addresses and actual data Addresses are specified by having the ninth bit in the data frame set to 1 Data in the message is specified by having the ninth bit in the data frame reset t
27. as close to the chip as possible A 1 0 uF and 0 001F dipped mica or ceramic cap should be mounted as close to the HPC as is physically possible on the board using the shortest leads or surface mount components This should provide a stable power supply and noiseless ground plane which will vastly improve the performance of the crystal oscillator network TABLE V HPC Oscillator XTAL Frequency MHz 2 1500 4 1200 6 910 8 750 600 470 390 300 220 180 150 120 100 75 62 Ry 0 3 3 Cy 27 pF 33 pF XTAL Specifications The crystal used was an M TRON Industries MP 1 Se ries XTAL cut parallel resonant CL 20 pF Series Resistance is 250 25 MHz 400 10 MHz 6000 e 2 MHz TL DD 11046 37 FIGURE 29 Recommended Crystal Circuit 27 167064 The HPC167064 CPU has a 16 bit ALU and six 16 bit regis ters Arithmetic Logic Unit ALU The ALU is 16 bits wide and can do 16 bit add subtract and shift or logic AND OR and exclusive OR in one timing cycle The ALU can also output the carry bit to a 1 bit C register Accumulator A Register The 16 bit A register is the source and destination register for most I O arithmetic logic and data memory access op erations Address B and X Registers The 16 bit B and X registers can be used for indirect ad dressing They can automatically count up or d
28. bit mode is selected by pulling HBE high at reset If HBE is left floating or connected to a memory device chip select at reset the 16 bit mode is entered The following sections describe the operating modes of the HPC167064 Note The HPC devices use 16 bit words for stack memory Therefore when using the 8 bit mode User s Stack must be in internal RAM 15 167064 Operating Modes SINGLE CHIP NORMAL MODE In this mode the HPC167064 functions as a self contained microcomputer see Figure 15 with all memory RAM and EPROM on chip It can address internal memory only con sisting of 16 kbytes of EPROM C000 to FFFF and 512 bytes of on chip RAM and Registers 0000 to O2FF The illegal address detection feature of the WATCHDOG is enabled in the Single Chip Normal mode and a WATCH DOG Output WO will occur if an attempt is made to access addresses that are outside of the on chip EPROM and RAM range of the device Ports and B are used for I O func tions and not for addressing external memory The EXM pin and the EA bit of the PSW register must both be logic 0 to enter the Single Chip Normal mode EXPANDED NORMAL MODE The Expanded Normal mode of operation enables the HPC167064 to address external memory in addition to the on chip ROM and RAM see Table 1 WATCHDOG illegal address detection is disabled and memory accesses may be made anywhere in the 64 kbyte address range without triggering an illegal
29. bitration Address P Ranking FFFF FFFE RESET 0 FFFD FFFC Nonmaskable external on rising edge of I1 pin 1 FFFB FFFA External interrupt on I2 pin 2 FFF9 FFF8 External interrupt pin 3 FFF7 FFF6 External interrupt on 14 pin 4 FFF5 FFF4 Overflow on internal timers 5 FFFS FFF2 Internal on the UART transmit receive complete or external on EXUI 6 FFF1 FFFO External interrupt on El pin 7 Interrupt Arbitration For the interrupts from the on board peripherals the user The HPC167064 contains arbitration logic to determine which interrupt will be serviced first if two or more interrupts occur simultaneously The arbitration ranking is given in Ta ble The interrupt on RESET has the highest rank and is serviced first Interrupt Processing Interrupts are serviced after the current instruction is com pleted except for the RESET which is serviced immediately RESET and EXUI are level LOW sensitive interrupts and El is programmable for edge RISING or FALLING or level HIGH or LOW sensitivity All other interrupts are edge sen sitive NMI is positive edge sensitive The external interrupts on 12 13 and 14 can be software selected to be rising or falling edge External interrupt EXUI is shared with UART interrupt This interrupt is level low sensitive To select this interrupt disable the ERI and ETI UART interrupt bits in the ENUI register To select the UART interrupt leave this pin floating or tie it high Interru
30. cts For details of the shim and how to obtain it contact factory applications group at 408 721 5582 32 33 with 16k UV Erasable CMOS EPROM HPC 167064 HPC467064 High Performance microController Physical Dimensions inches millimeters i m Oni 10 26 9 109 0 135 0 016 0 02 vette ae LX 6 020 0 51 59 6 011 0 28 a TTTTTTTTTTTTT 0 004 0 10 0 005 9 015 5 0 15 0 33 ET DETAIL TYPICAL ROTATED 90 0 942 0 958 23 93 24 33 0 345 0 355 A 8 75 9 02 WINDOW A 0 809 ryp 5 20 32 0 049 SEE DETAIL A 124 50 pa nee 0 626 0 640 15 90 16 26 m DN 9 980 1 000 530070349 24 89 25 40 22 86 25 88 TYP CONTACT POINT eo P Zo eo se LS Bo zl REV Leaded EPROM Chip Carrier EL Order Number HPC167064EL or HPC467064EL NS Package Number EL68C LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices
31. d dress must be between C000 and FFFF when emulating the HPC16064 and between E000 and FFFF when emulating the HPC16003 Timer Overview The HPC167064 contains a powerful set of flexible timers enabling the HPC167064 to perform extensive timer func tions not usually associated with microcontrollers The HPC167064 contains nine 16 bit timers Timer TO is a free running timer counting up at a fixed CKI 16 18 91607 jo 81 380514 9c 9v0LL QQ 11 1 1 a e l e 14 ANI ANI EMEN 851 854 3IN3 934 19 Timer Overview Continued Clock Input 16 rate It is used for WATCHDOG logic high speed event capture and to exit from the IDLE mode Con sequently it cannot be stopped or written to under software control Timer TO permits precise measurements by means of the capture registers 2 I3CR and I4CR A control bit in the register TMMODE configures timer T1 and its associ ated register R1 as capture registers I3CR and I2CR The capture registers I2CR and I4CR respectively record the value of timer TO when specific events occur on the interrupt pins I2 I3 and I4 The control register IRCD pro grams the capture registers to trigger on either a rising edge or a falling edge of its respective input The specified edge can also be programmed to generate an interrupt see Fig ure 19 The HPC167
32. d which we will respond to 408 721 5582 Modem 408 739 1162 Baud 300 or 1200 baud Set Up Length 8 bit Parity Stop Bit 1 None Operation 24 hrs 7 Days HOST COMPUTER USER SITE DIAL A HELPER HOST COMPUTER NATIONAL SEMICONDUCTOR SITE TL DD 11046 38 31 Part Selection The HPC family includes devices with many different options and configurations to meet various application needs The number HPC167064 has been generically used throughout this datasheet to represent the whole family of parts The following chart explains how to order various options available when ordering HPC family members Note All options may not currently be available HPCX67064 EL E 20 NEN Speed in MHz 20 20 MHz Package Type EL Leaded Ceramic Chip Carrier LDCC Temperature 4 Commercial 0 C to 70 C 1 Military 55 C to 125 C TL DD 11046 39 Examples HPC467064 EL20 16k EPROM Commercial temperature 0 C to 70 LDCC HPC167064 EL20 16k EPROM Military temperature 55 C to 125 C LDCC to be used for automotive temperature range also Socket Selection Suggested sockets and extractor tool Socket Amp PLCC 821574 1 6141749 YAMAICHI 1C51 0684 390 1C120 0684 204 ENPLAS PLCC 68 1 27 02 Extractors Tool Amp 821566 1 A shim must be used in conjunction with this socket to ensure proper conta
33. full 16 kbytes of ROM and 512 bytes of RAM are enabled Programming a 0 to these bits disables the lower 8k for the EPROM and upper 256 bytes for the RAM The ECON registers are only acces sible to the user during EPROM mode Address In Address In Other EPROM Mode HPC Modes 7FFF Operation 4000 FFFF 3FFF 2000 E000 1FFF DFFF Enabled or Disabled by config logic 0000 C000 11 Pin Descriptions The HPC167064 is available only in 68 pin LDCC package 1 0 PORTS Port A is a 16 bit bidirectional I O port with a data direction register to enable each separate pin to be individually de fined as an input or output When accessing external memo ry port A is used as the multiplexed address data bus Port is a 16 bit port with 12 bits of bidirectional 1 similar in structure to Port A Pins B10 B11 B12 and B15 are gen eral purpose outputs only in this mode Port B may also be configured via a 16 bit function register BFUN to individually allow each pin to have an alternate function TDX UART Data Output B1 B2 CKX UART Clock Input or Output 2 Timer2 1 Pin B4 Timer3 1 Pin 5 SO MICROWIRE PLUS Output SK MICROWIRE PLUS Clock Input or Output B7 Hold Acknowledge Output B8 TSO Timer Synchronous Output B9 TS1 Timer Synchronous Output B10 UAO Address 0 Input for UPI Mode B11 WRRDY Write Ready Output for UPI Mode B12 B13 TS2 Timer Synchr
34. gister 015E 015F EICR 00 00 Register 015 00C9 00C8 A Register HPC Core 0153 0152 Port P Register 00 7 00 6 Registers 0151 0150 PWMODE Register 00 5 00 4 SP Register 014F 014E R7 Register 0003 0002 Reserved 014D 014C T7 Timer 0000 PSW Register 014B 014A R6 Register Timer Block T4 T7 OOBF 00BE 0149 0148 T6 Timer Do User RAM 0147 0146 R5 Register 0001 0000 0145 0144 T5 Timer 0143 0142 R4 Register 0141 0140 T4 Timer 25 Design Considerations Continued TABLE IV Memory of HPC 167064 Emulating an HPC 16083 FFFF FFFO Interrupt Vectors FFEF FFDO JSRP Vectors FFCF FFCE On Chip EPROM E001 E000 User Memory DFFF DFFE External Expansion 0201 0200 01FF 01FE 01 1 01 0 0195 0194 WATCHDOG Register WATCHDOG Logic 0192 TOCON Register 0191 0190 TMMODE Register 018F 018E DIVBY Register 018D 018C T3 Timer 018B 018A R3 Register 01890188 T2 Timer Timer BIGOS EST 0187 0186 R2 Register 0185 0184 12 Register R1 0183 0182 I3CR Register T1 0181 0180 14 Register 015E 015F EICR 015 0153 0152 Port P Register 0151 0150 PWMODE Register 014F 014E R7 Register 014D 014C T7 Timer 014B 014A R6 Register Timer Plon Poele 0149 0148 Timer 0147 0146 R5 Register 0145 0144 T5 Timer 0143 0142 R4
35. gister can be modified only once IDLE MODE The HPC167064 is placed in the IDLE mode through the PSW In this mode all processor activity except the on board oscillator and Timer TO is stopped As with the HALT mode the processor is returned to full operation by the RESET or NMI inputs but without waiting for oscillator stabi lization A timer TO overflow will also cause the HPC167064 to resume normal operation Note If an NMI interrupt is received during the instruction which puts the device in Halt or Idle Mode the device will enter that power saving mode The interrupt will be held pending until the device exits that power saving mode When exiting Idle mode via the TO overflow the NMI interrupt will be serviced when the device exits Idle If another NMI interrupt is received during either Halt of Idle the processor will exit the power saving mode and vector to the interrupt address HPC167064 Interrupts Complex interrupt handling is easily accomplished by the HPC167064 s vectored interrupt scheme There are eight possible interrupt sources as shown in Table II 16 167064 Interrupts Continued ROMLESS ROM MEMORY HPC187064 TL DD 11046 24 ROMLESS ROM MEMORY npcie7064 MEMORY TL DD 11046 25 FIGURE 17 16 Bit External Memory 17 167064 Interrupts continued TABLE Il Interrupts Vector interrupt Source Ar
36. is the Absolute Maximum Rat ings of 0 5V and GND 0 5V respectively The D C Electrical Characteristics and Electrical Characteristics for the HPC167064 where Ta 55 C to 125 are guaranteed over a reduced operating voltage range of Vcc 5 This is different from the masked ROM devices that it simulates which is Vcc 1096 These characteristics for the HPC467064 where TA 0 to 70 C are guaranteed over the masked ROM operating voltage range which is 10 addition to the reduced operating voltage range for the HPC167064 the A C timing parameter tupp is required to be a mimimum value of 25 ns The masked ROM de vices require a mimimum typH Of 20 ns This A C timing parameter for the HPC467064 is required to be the same as the masked ROM devices HPC167064 EPROM SECURITY The HPC167064 includes security logic to provide READ and WRITE protection of the on chip EPROM These de fined privileges are intended to deter theft alteration or un intentional destruction of user code Two bits are used to define four levels of security on the HPC167064 to control access to on chip EPROM Security Level 3 This is the default configuration of an erased HPC167064 READ and WRITE accesses to the on chip EPROM or ECON registers may be accomplished without constraint in EPROM mode READ accesses to the on chip EPROM may be accomplished without constraint in NORMAL RUNNING mode 10
37. lengths using wide traces ground planes and by decoupling the supply with bypass capacitors In order to prevent additional voltage spiking this local bypass capacitor must exhibit low inductive reactance You should therefore use high frequen cy ceramic capacitors and place them very near the IC to minimize wiring inductance m Keep Vcc bus routing short When using double sided or multilayer circuit boards use ground plane techniques Keep ground lines short and on PC boards make them as wide as possible even if trace width varies Use separate ground traces to supply high current devices such as re lay and transmission line drivers n systems mixing linear and logic functions and where supply noise is critical to the analog components per formance provide separate supply buses or even sepa rate supplies If you use local regulators bypass their inputs with a tan talum capacitor of at least 1 uF and bypass their outputs with a 10 uF to 50 uF tantalum or aluminum electrolytic capacitor If the system uses a centralized regulated power supply use 10 uF to 20F tantalum electrolytic capacitor or 50 uF to 100 uF aluminum electrolytic capacitor to de couple the Vcc bus connected to the circuit board Provide localized decoupling For random logic a rule of thumb dictates approximately 10 nF spaced within 12 cm per every two to five packages and 100 nF for every 10 packages You can group these capacitances but
38. ly as for the HPC16083 The WATCHDOG function monitors ad dresses accordingly Thus the HPC167064 can be used as a stand alone emulator for both HPC16064 and HPC16083 Within this mode the on chip EPROM cell acts as read only memory Each memory fetch is 16 bits wide The HPC167064 operates to 20 MHz with 1 wait state for the on chip memory The HPC167064 emulates the HPC16064 and HPC16083 except as described here The value of EXM is latched on the rising edge of RESET Thus the user may not switch from ROMed to ROMless operation or vice versa without another RESET pulse The security logic can be used to control access to the on chip EPROM This feature is unique to the HPC167064 There is no corresponding mode of opera tion on the HPC16064 or the HPC16083 Specific inputs are allowed to be driven at high voltage 13V to configure the device for programming These high voltage inputs are unique to the HPC167064 The same inputs cannot be driven to high voltage on the HPC16064 and HPC16083 without damage to the part The Port D input structure on this device is slightly differ ent from the masked ROM HPC16083 and HPC16064 Vin2 and Vi_2 max are the same as for the masked ROM HPC16083 and HPC16064 There is a 2 max requirement for this device equal to 0 05V There is also Vi_2 requirement for this device equal to GND 0 05V The ViH2 max and gt min requirement for the masked ROM devices
39. memory access instructions Data waiting to be transmitted in the SIO register is clocked out on the falling edge of the SK clock Serial data on the SI pin is clocked in on the rising edge of the SK clock 21 MICROWIRE PLUS Application Figure 25 illustrates MICROWIRE PLUS arrangement for an automotive application The microcontroller based sys tem could be used to interface to an instrument cluster and various parts of the automobile The diagram shows two HPC167064 microcontrollers interconnected to other MICROWIRE peripherals HPC167064 1 is set up as the master and initiates all data transfers HPC167064 2 is set up as a slave answering to the master The master microcontroller interfaces the operator with the system and could also manage the instrument cluster in an automotive application Information is visually presented to the operator by means of a LCD display controlled by the COP472 display driver The data to be displayed is sent serially to the COP472 over the MICROWIRE PLUS link Data such as accumulated mileage could be stored and re trieved from the EEPROM COP494 The slave HPC167064 could be used as a fuel injection processor and generate timing signals required to operate the fuel valves The mas ter processor could be used to periodically send updated values to the slave via the MICROWIRE PLUS link To speed up the response chip select logic is implemented by connecting an output from the master to
40. mp tubes during erasure Some lamps have a filter on their tubes which should be removed before erasure The era sure time table shows the minimum HPC167064 erasure time for various light intensities An erasure system should be calibrated periodically The distance from lamp to unit should be maintained at one inch The erasure time increases as the square of the distance If distance is doubled the erasure time increases by a factor of 4 Lamps lose intensity as they age When a lamp is changed the distance has changed or the lamp has aged the system should be checked to make certain full erasure is occurring Incomplete erasure will cause symptoms that can be mis leading Programmers components and even system de signs have been erroneously suspected when incomplete erasure was the problem Minimum HPC 167064 Erasure Time Erasure Time Minutes 15 000 36 10 000 50 Light Intensity Micro Watts cm Memory Map of the HPC167064 The HPC167064 has 256 bytes of on chip user RAM and chip registers located at address 0000 01FF that is always enabled and 256 bytes of on chip RAM located at 0200 O2FF that can be enabled or disabled It has 8 kbytes of on chip EPROM located at address 0 000 that is al ways enabled and 8 kbytes of EPROM located at address 0C000 0DFFF that be enabled or disabled The 6 contains two bits ROMO and RAMO When these bits are 1 erased default
41. nal ROM accesses are limited to 24 max The HPC167064 provides four software selectable Wait States that allow access to slower memories The Wait States are selected by the state of two bits in the PSW register Addi tionally the RDY input may be used to extend the instruc tion cycle allowing the user to interface with slow memories and peripherals HPC167064 TL DD 11046 23 FIGURE 15 Single Chip Mode Power Save Modes Two power saving modes are available on the HPC167064 HALT and IDLE In the HALT mode all processor activities are stopped In the IDLE mode the on board oscillator and timer TO are active but all other processor activities are stopped In either mode all on board RAM registers and I O are unaffected HALT MODE The HPC167064 is placed in the HALT mode under soft ware control by setting bits in the PSW All processor activi ties including the clock and timers are stopped In the HALT mode power requirements for the HPC167064 are minimal and the applied voltage Vcc may be decreased without altering the state of the machine There are two ways of exiting the HALT mode via the RESET or the NMI The RESET input reinitializes the processor Use of the NMI input will generate a vectored interrupt and resume opera tion from that point with no initialization The HALT mode can be enabled or disabled by means of a control register HALT enable To prevent accidental use of the HALT mode the HALT enable re
42. ng edge occurs later may be as long as 4 WS 72tc 100 depending on the following CPU instruction cycles its wait states and ready input Note 4 WS twait X number of pre programmed wait states Minimum and maximum values are calculated at maximum operating frequency 20 00 MHz with one wait state programmed Note 5 Due to emulation restrictions actual limits will be better Note 6 Due to tester limitations actual limits will be better 20 MHz AC Electrical Characteristics Continued See Notes 1 and 4 and Figures 7 thru Voc 5V 5 Ta 55 C to 125 C for HPC167064 Voc 5V 10 0 C to 70 C for HPC467064 Continued Symbol and Formula Parameter Min Max Units Notes M tpc1ALER Delay from Rising Edge to ALE Rising Edge 0 35 ns Notes 1 2 5 tpC1ALEF Delay from Rising Edge to ALE Falling Edge 0 35 ns Notes 1 2 5 tpc2aLeR 4 20 Delay from CK2 Rising Edge to ALE Rising Edge 45 ns 2 tpceALEF 1 20 Delay from CK2 Falling Edge to ALE Falling Edge 45 ns 1 9 ALE Pulse Width 41 ns 5 tst Alo 7 Setup of Address Valid before ALE Falling Edge 18 ns s typ 14 5 Hold of Address Valid after ALE Falling Edge 20 ns tanR Vato 5 ALE Falling Edge to RD Falling Edge 20 ns 8 tacc tc WS 55 Data Input Valid after Address Output Valid 145 ns 8 trp
43. o 0 The UART monitors the communication stream looking for addresses When the data word with the ninth bit set is received the UART signals the HPC167064 with an inter rupt The processor then examines the content of the re ceiver buffer to decide whether it has been addressed and whether to accept subsequent data ro 2 0 RECEIVE SHIFT REGISTER TRANSMIT SHIFT REGISTER CLOCK SELECT UNFL CKX TL DD 11046 34 FIGURE 26 UART Block Diagram 23 Universal Peripheral Interface The Universal Peripheral Interface UPI allows the HPC167064 to be used as an intelligent peripheral to anoth er processor The UPI could thus be used to tightly link two HPC167064 s and set up systems with very high data ex change rates Another area of application could be where a HPC167064 is programmed as an intelligent peripheral to a host system such as the Series 320009 microprocessor Figure 27 illustrates how a HPC167064 could be used as an intelligent peripheral for a Series 32000 based application The interface consists of a Data Bus port A a Read Strobe URD a Write Strobe UWR a Read Ready Line RDRDY a Write Ready Line WRRDY and one Address Input UAO The data bus can be either eight or sixteen bits wide The URD and UWR inputs may be used to interrupt the HPC167064 The RDRDY and WRRDY outputs may be used to interrupt the host processor The UPI contains an In
44. onous Output B14 TS3 Timer Synchronous Output B15 RDRDY Read Ready Output for UPI Mode When accessing external memory four bits of port B are used as follows B10 ALE Address Latch Enable Output B11 WR Write Output B12 HBE High Byte Enable Output Input sampled at reset B15 RD Read Output Port is an 8 bit input port that can be read as general purpose inputs and is also used for the following functions 11 NMI Nonmaskable Interrupt Input I2 INT2 Maskable Interrupt Input Capture URD 13 Maskable Interrupt Input Capture UWR l4 INT4 Maskable Interrupt Input Capture 15 Sl MICROWIRE PLUS Data Input 16 RDX UART Data Input 17 Port D is an 8 bit input port that can be used as general purpose digital inputs Port P is a 4 bit output port that can be used as general purpose data or selected to be controlled by timers 4 through 7 in order to generate frequency duty cycle and pulse width modulated outputs POWER SUPPLY PINS Voci and Vcc2 Positive Power Supply GND Ground for On Chip Logic DGND Ground for Output Buffers Note There are two electrically connected Vcc pins on the chip GND and DGND are electrically isolated Both Vcc pins and both ground pins must be used CLOCK PINS The Chip System Clock Input CKO The Chip System Clock Output inversion of Pins and are usually connected across an external crystal CK2 Clock Output CKI divided by 2 OTHER PINS
45. operand is the memory addressed by the X register This mode automatically increments or decrements the X register by 1 for bytes and by 2 for words Register Indirect Auto Increment and Decrement with Conditional Skip The operand is the memory addressed by the B register This mode automatically increments or decrements the B register by 1 for bytes and by 2 for words The B register is then compared with the K register A skip condition is gener ated if B goes past K ADDRESSING MODES DIRECT MEMORY AS DESTINATION Direct Memory to Direct Memory The instruction contains two 8 or 16 bit address fields One field directly points to the source operand and the other field directly points to the destination operand Immediate to Direct Memory The instruction contains an 8 or 16 bit address field and an 8 or 16 bit immediate field The immediate field is the oper and and the direct field is the destination Double Register Indirect Using the B and X Registers Used only with Reset Set and IF bit instructions a specific bit within the 64 kbyte address range is addressed using the B and X registers The address of a byte of memory is formed by adding the contents of the B register to the most significant 18 bits of the X register The specific bit to be modified or tested within the byte of memory is selected using the least significant 3 bits of register X Mnemonic Description Action ARITHMETIC INSTRUCTI
46. own to se quence through data memory Boundary K Register The 16 bit K register is used to set limits in repetitive loops of code as register B sequences through data memory Stack Pointer SP Register The 16 bit SP register is the pointer that addresses the stack The SP register is incremented by two for each push or call and decremented by two for each pop or return The stack can be placed anywhere in user memory and be as deep as the available memory permits Program PC Register The 16 bit PC register addresses program memory Addressing Modes ADDRESSING MODES ACCUMULATOR AS DESTINATION Register Indirect This is the normal mode of addressing for the HPC167064 instructions are single byte The operand is the memory addressed by the B register or X register for some instructions Direct The instruction contains an 8 bit or 16 bit address field that directly points to the memory for the operand HPC Instruction Set Description Indirect The instruction contains an 8 bit address field The contents of the WORD addressed points to the memory for the oper and Indexed The instruction contains an 8 bit address field and an 8 or 16 bit displacement field The contents of the WORD ad dressed is added to the displacement to get the address of the operand Immediate The instruction contains an 8 bit or 16 bit immediate field that is used as the operand Register Indirect Auto Increment and Decrement The
47. p EPROM when the Program Counter PC contains addresses within the on chip EPROM address range A logic 1 state on the EXM pin will cause the HPC device to address memory that is external to the HPC when he PC contains on chip EPROM addresses The function of he EA bit is to determine the legal addressing range of the HPC device A logic 0 state in the EA bit of the PSW register does two things addresses are limited to the on chip EPROM range and on chip RAM and Register range and the illegal address detection feature of the WATCH ALTERNATE FUNCTION INPUT ALTERNATE FUNCTION OUTPUT BUS FUNCTION B12 HBE ONLY MODE 16 BIT MODE EXPANDED OR ROMLESS TL DD 11046 22 DOG logic is engaged A logic 1 in the EA bit enables accesses to be made anywhere within the 64 kbytes ad dress range and the illegal address detection feature of the WATCHDOG logic is disabled All HPC devices can be used with external memory Exter nal memory may be any combination of RAM and EPROM Both 8 bit and 16 bit external data bus modes are available Upon entering an operating mode in which external memory is used Port A becomes the Address Data bus Four pins of Port B become the control lines ALE RD WR and HBE The High Byte Enable pin HBE is used in 16 bit mode to select high order memory bytes The RD and WR signals are only generated if the selected address is off chip The 8
48. pt Control Registers The HPC167064 allows the various interrupt sources and conditions to be programmed This is done through the vari ous control registers A brief description of the different con trol registers is given below INTERRUPT ENABLE REGISTER ENIR RESET and the External Interrupt 11 are non maskable interrupts The other interrupts can be individually enabled or disabled Additionally a Global Interrupt Enable Bit in the ENIR Register allows the Maskable interrupts to be collec tively enabled or disabled Thus in order for a particular interrupt to request service both the individual enable bit and the Global Interrupt bit GIE have to be set INTERRUPT PENDING REGISTER IRPD The IRPD register contains a bit allocated for each interrupt vector The occurrence of specified interrupt trigger condi tions causes the appropriate bit to be set There is no indi cation of the order in which the interrupts have been re ceived The bits are set independently of the fact that the interrupts may be disabled IRPD is a Read Write register The bits corresponding to the maskable external interrupts are normally cleared by the HPC167064 after servicing the interrupts has the responsibility of resetting the interrupt pending flags through software The NMI bit is read only and 12 14 are designed as to only allow a zero to be written to the pending bit writing one has no affect A LOAD IMMEDIATE instr
49. put Buffer IBUF an Output Buffer OBUF and a Control Register UPIC In the UPI mode Port A on the HPC167064 is the data bus UPI can only be used if the HPC167064 is in the Single Chip mode Shared Memory Support Shared memory access provides a rapid technique to ex change data It is effective when data is moved from a pe ripheral to memory or when data is moved between blocks of memory A related area where shared memory access proves effective is in multiprocessing applications where two CPUs share a common memory block The HPC167064 supports shared memory access with two pins The pins are the RDY HLD input pin and the HLDA output pin The user can software select either the Hold or Ready function by the state of a control bit The HLDA output is multiplexed onto Port B SERIES 32000 SYSTEM WA CPU TCU e icu MEMORY ADDRESS DECODER SYSTEM MASTER ADORESS BUS A23 The host uses DMA to interface with the HPC167064 The host initiates a data transfer by activating the HLD input of the HPC167064 In response the HPC167064 places its system bus in a TRI STATE Mode freeing it for use by the host The host waits for the acknowledge signal HLDA from the HPC167064 indicating that the sytem bus is free On receiving the acknowledge the host can rapidly transfer data into or out of the shared memory by using a conven tional DMA controller Upon completion of the message transfe
50. r the host removes the HOLD request and the HPC167064 resumes normal operations To insure proper operation the interface logic shown is rec ommended as the means for enabling and disabling the us er s bus Figure 28 illustrates an application of the shared memory interface between the HPC167064 and a Series 32000 system Memory The HPC167064 has been designed to offer flexibility in memory usage A total address space of 64 kbytes can be addressed with 8 kbytes of EPROM and 512 bytes of RAM available on the chip itself The EPROM may contain pro gram instructions constants or data The EPROM and RAM share the same address space allowing instructions to be executed out of RAM Program memory addressing is accomplished by the 16 bit program counter on a byte basis Memory can be addressed directly by instructions or indirectly through the B X and SP registers Memory can be addressed as words or bytes Words are always addressed on even byte boundaries The HPC167064 uses memory mapped organization to support registers 1 and on chip peripheral functions The HPC167064 memory address space extends to 64 kbytes and registers and I O are mapped as shown Table and Table IV RORDY WRRDY SYSTEM HPC167064 DATA BUS TL DD 11046 35 FIGURE 27 HPC 167064 a Peripheral UPI Interface to Series 32000 Application Shared Memory Support Continued BUS GRANT REM
51. rammed in the on chip EPROM and the HPC167064 can then be plugged in the target system to run the application like a regular masked ROM device The HPC167064 can be pro grammed using DATA I O UNISITE with pinsite module To support the security feature of the HPC167064 a soft ware switch is provided with the linker under PROMHPC which will generate an encrypted hex file for the user The purpose is to be able to compare this software generated encrypted data with the encrypted data produced by the actual chip to provide a way to verify on chip EPROM code after security has been enabled For details of how to gener ate encrypted data and all other HPC167064 features refer to the Appendix K of the HPC Family User s Manual 30 Development Support Continued PROGRAMMING SUPPORT The HPC167064 EPROM array can be programmed using a DATA I O Unisite model with a pinsite module No adaptor board is required with the DATA I O programmer Program ming of the configuration bytes and security bits is de scribed in the HPC Family User s Manual HOW TO ORDER To order a complete development package select the sec tion for the microcontroller to be developed and order the parts listed Development Tools Selection Table Order Description Includes Manual Number P Number HPC DEV IBMA Assembler Linker Librarian HPC Assembler Linker Librarian 424410836 001 Package for IBM PC AT User s Manual HPC DEV IBMC
52. rectly or indirectly Since all registers I O are mapped into the memory it is very easy to manipulate specific bits to do efficient control DECIMAL ADD AND SUBTRACT This instruction is needed to interface with the decimal user world It can handle both 16 bit words and 8 bit bytes The 16 bit capability saves code since many variables can be stored as one piece of data and the programmer does not have to break his data into two bytes Many applications store most data in 4 digit variables The HPC167064 sup plies 8 bit byte capability for 2 digit variables and literal vari ables MULTIPLY AND DIVIDE INSTRUCTIONS The HPC167064 has 16 bit multiply 16 bit by 16 bit divide and 32 bit by 16 bit divide instructions This saves both code and time Multiply and divide can use immediate data or data from memory The ability to multiply and divide by immediate data saves code since this function is often needed for scaling base conversion computing indexes of arrays etc Development Support The HPC167064 acts as a stand alone emulator for either the HPC16083 or the HPC16064 No separate development tool is thus provided to support this emulator device The user will use either the HPC16083 or the HPC16064 de pending on which device is in use development tools to develop and debug the application hardware and software in their target as normally done for the non emulator HPC devices The application software can then be prog
53. rotection Security Level 0 This security level prevents programming of the on chip EPROM or ECON registers thereby providing write protec tion Read accesses to the on chip ECON registers may be accomplished without constraint in EPROM mode READ accesses to the on chip EPROM are NOT ALLOWED in EPROM mode Such accesses will return data value hex Runtime Memory Protection is enforced as in security level 1 These four levels of security help ensure that the user EPROM code is not tampered with in a test fixture and that code executing from RAM or external memory does not dump the user algorithm Erasure Characteristics The erasure characteristics of the HPC167064 are such that erasure begins to occur when exposed to light with wave lengths shorter than approximately 4000 Angstroms A It should be noted that sunlight and certain types of fluores cent lamps have wavelengths in the 3000A 4000A range After programming opaque labels should be placed over the HPC167064 s window to prevent unintentional erasure Covering the window will also prevent temporary functional failure due to the generation of photo currents The recommended erasure procedure for the HPC167064 is exposure to short wave ultraviolet light which has a wave length of 2537 Angstroms A The integrated dose i e UV intensity exposure time for erasure should be a minimum of 30W sec cm The HPC167064 should be placed within 1 inch of the la
54. s indicate limits beyond which damage to the device may occur DC and AC electri Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 sec 300 C vice at absolute maximum ratings DC Electrical Characteristics Vcc 5 0V 5 unless otherwise specified Ta 55 C to otherwise specified Ta 0 C to 70 C for HPC467064 cal specifications are not ensured when operating the de 125 C for HPC167064 and Vcc 5 0V 10 unless Symbol Parameter Test Conditions Min Max Units Icc4 Supply Current Voc max 30 0 MHz Note 1 85 mA Voc max 20 0 MHz Note 1 70 mA Voc max 2 0 MHz Note 1 40 mA IDLE Mode Current Voc max 30 0 MHz Note 1 6 0 mA Voc max fi 20 0 MHz Note 1 4 5 mA Voc max fin 2 0 MHz Note 1 1 mA HALT Mode Current Voc max fin 0 KHz Note 1 400 pA Voc 2 5V fin 0 kHz Note 1 100 pA INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET NMI AND WO AND ALSO CKI Logic High 0 9 Voc Logic Low 0 1 Voc ALL OTHER INPUTS Logic High 0 7 Vcc 2 Logic Low T 0 2 Vcc liit Input Leakage Current Vin 0 and Vin Note 4 2 pA 2 Input Leakage Current RDY HLD EXUI Vin 0 3 50 pA liis Input Leakage Current B12 RESET 0 Vin Voc 0 5 7 pA Input Leakage Current Vin 0 and Vin
55. uction is to be the only instruction used to clear a bit or bits in the IRPD register This allows a mask to be used thus ensuring that the other pending bits are not affected INTERRUPT CONDITION REGISTER IRCD Three bits of the register select the input polarity of the external interrupt on 12 and 14 Servicing the Interrupts The Interrupt once acknowledged pushes the program counter PC onto the stack thus incrementing the stack pointer SP twice The Global Interrupt Enable bit GIE is copied into the CGIE bit of the PSW register it is then reset thus disabling further interrupts The program counter is loaded with the contents of the memory at the vector ad dress and the processor resumes operation at this point At the end of the interrupt service routine the user does a RETI instruction to pop the stack and re enable interrupts if the CGIE bit is set or RET to just pop the stack if the CGIE bit is clear and then returns to the main program The GIE bit can be set in the interrupt service routine to nest inter rupts if desired Figure 18 shows the Interrupt Enable Logic RESET The RESET input initializes the processor and sets Ports A and B in the TRI STATE condition and Port P in the LOW state RESET is an active low Schmitt trigger input The processor vectors to FFFF FFFE and resumes operation at the address contained at that memory location which must correspond to an on board location The Reset vector a
56. ump indirect at PC A 1 JIDW then Mem PC PC NOP No Operation PC 1 PC RET Return SP 2 SP W SP PC RETSK Return then skip next SP 2 SP W SP amp skip RETI Return from interrupt SP 2 SP W SP interrupt re enabled Note W is 16 bit word of memory MA is Accumulator A or direct memory 8 bit or 16 bit Mem is 8 bit byte or 16 bit word of memory is 8 bit or 16 bit memory or 8 bit or 16 bit immediate data imm is 8 bit or 16 bit immediate data imm 8 is 8 bit immediate data only For details of memory usage by each instruction see The HPC User s Manual 29 Code Efficiency One of the most important criteria of a single chip microcon troller is code efficiency The more efficient the code the more features that can be put on a chip The memory size on a chip is fixed so if code is not efficient features may have to be sacrificed or the programmer may have to buy a larger more expensive version of the chip The HPC family has been designed to be extremely code efficient The HPC looks very good in all the standard cod ing benchmarks however it is not realistic to rely only on benchmarks Many large jobs have been programmed onto the HPC and the code savings over other popular micro controllers has been considerable Reasons for this saving of code include the following SINGLE BYTE INSTRUCTIONS The majority of instructions on the
57. unctions that can be performed by the user in the EPROM mode Programming CAUTION Exceeding 14V on pin 1 Vpp will damage the HPC167064 Initially and after each erasure all bits of the HPC EPROM are in the 1 state Data is introduced by selec tively programming Os into the desired bit locations Although only Os will be programmed both 18 and Os can be presented in the data word The only way to change 0 to a 1 is by ultraviolet light erasure Program verify EPROM registers To read data verify during the programming process Vpp must be at 13V When reading data after the pro gramming process Vpp can be either 13V or at e Program verify ECON registers There are two configuration registers ECON6 and ECON7 to emulate different family members and also to enable disable different features in the chip These reg isters are not mapped in the EPROM user space These bytes must be programmed through a pointer register ECONA To prevent unintentional programming the ECON6 7 registers must be programmed with the assistance of this pointer register ECONA and externally presented ad dress both identify the same ECON register may be pro grammed NORMAL RUNNING MODE In this mode the HPC167064 executes user software in the normal manner By default its arcitecture imitates that of the HPC16064 It may be configured to emulate the HPC16083 The addressable memory map will be exact
58. ure of the HPC167064 simplifies pulse generation and measurement There are four syn chronous timer outputs TSO through TS3 that work in con junction with the timer T2 The synchronous timer outputs can be used either as regular outputs or individually pro grammed to toggle on timer T2 underflows see Figure 20 Timer register pairs 4 7 form four identical units which can generate synchronous outputs on Port P see Figure 21 T210 T310 TL DD 11046 28 FIGURE 20 Timers T2 T3 Block 20 Timer Overview Continued Maximum output frequency for any timer output can be ob tained by setting timer register pair to zero This then will produce an output frequency equal to 7 the frequency of the source used for clocking the timer Timer Registers There are four control registers that program the timers The divide by DIVBY register programs the clock input to tim ers T2 and T3 The timer mode register TMMODE contains control bits to start and stop timers T1 through T3 It also contains bits to latch acknowledge and enable interrupts from timers TO through T3 The control register PWMODE similarly programs the pulse width timers T4 through T7 by allowing them to be started stopped and to latch and en able interrupts on underflows The PORTP register contains bits to preset the outputs and enable the synchronous timer output functions rezamaz T4 T7 OUT gt gt TL DD 11046
59. ut WO pin low The WO pin is an open drain output and can be connected to the RESET or NMI inputs or to the users external logic Note See Operating Modes for details MICROWIRE PLUS MICROWIRE PLUS is used for synchronous serial data communications see Figure 24 MICROWIRE PLUS has an 8 bit parallel loaded serial shift register using SI as the input and SO as the output SK is the clock for the serial shift register SIO The SK clock signal can be provided by an internal or external source The internal clock rate is pro grammable by the DIVBY register A DONE flag indicates when the data shift is completed The MICROWIRE PLUS capability enables it to interface with any of National Semiconductor s MICROWIRE periph erals i e A D converters display drivers EEPROMs MICROWIRE PLUS Operation The HPC167064 can enter the MICROWIRE PLUS mode as the master or a slave A control bit in the IRCD register determines whether the HPC167064 is the master or slave The shift clock is generated when the HPC167064 is config ured as a master An externally generated shift clock on the SK pin is used when the HPC167064 is configured as a slave When the HPC167064 is a master the DIVBY regis ter programs the frequency of the SK clock The DIVBY register allows the SK clock frequency to be programmed in 15 selectable steps from 64 Hz to 1 MHz with at 16 0 MHz The contents of the SIO register may be accessed through any of the
60. ws MICROWIRE Setup Time Master 100 amp MICROWIRE Setup Time Slave 20 du lt g tuwH MICROWIRE Hold Time Master 20 MICROWIRE Hold Time Slave 50 id tuwv MICROWIRE Output Valid Time Master 50 Ag MICROWIRE Output Valid Time Slave 150 5 tsaLe 34 40 HLD Falling Edge before ALE Rising Edge 90 ns o tc 10 HLD Pulse Width 76 ns 1 tc 85 HLDA Falling Edge after HLD Falling Edge 151 ns Note 3 tuap 85 Rising Edge after Rising Edge 135 ns x tar 10 66 Bus Float after HLDA Falling Edge 99 ns Note 5 5 16 66 Bus Enable after HLDA Rising Edge 99 ns Note 5 tuas Address Setup Time to Falling Edge of URD 10 ns tUAH Address Hold Time from Rising Edge of URD 10 ns URD Pulse Width 100 ns B toe URD Falling Edge to Output Data Valid 0 60 ns top Rising Edge of URD to Output Data Invalid 5 45 ns Note 6 tpRDY RDRDY Delay from Rising Edge of URD 70 ns 2 twow UWR Pulse Width 40 ns tups Input Data Valid before Rising Edge of UWR 10 ns tupH Input Data Hold after Rising Edge of UWR 20 ns tA WRRDY Delay from Rising Edge of UWR 70 ns o DC4ALER Delay from CKI Rising Edge to ALE Rising Edge 0 35 ns Notes 1 2 tpc1ALEF Delay from Rising Edge to ALE Falling Edge 0 35 ns Notes 1 2 6 tpC2ALER A4tc 20 Delay from 2 Rising Edge to ALE Rising Edge 37 ns 8 tpceALEF 20 Delay from CK2 Falling Edge to ALE Falling Edge 37 ns 2 9 A
61. y cycle and with less than 15 pF load on CKO with rise and fall times and input less than 2 5 ns Note 2 Do not design with this parameter unless is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 is spec d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed If HLD falling edge occurs later may be as long as 4 WS 72 100 depending on the following CPU instruction cycles its wait states and ready input Note 4 WS twait X number of pre programmed wait states Minimum and maximum values are calculated at maximum operating frequency 30 00 MHz with one wait state programmed Note 5 Due to emulation restrictions actual limits will be better Note 6 Due to tester limitations actual limits will be better CKI Input Signal Characteristics Rise Fall Time 90 10 TL DD 11046 2 Duty Cycle TL DD 11046 3 FIGURE 1 CKI Input Signal CKI Input Signal Characteristics TEST POINTS ML TL DD 11046 4 Note AC testing inputs are driven at for logic 1 and Vj for a logic 0 Output timing measurements are made at 2 for both logic 1 and logic 0

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