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National Instruments 32100 User's Manual

1. Figure 4 3 1 0 Connector Pin Assignment for the AT MIO 16DE 10 AT MIO AI E Series User Manual 4 4 National Instruments Corporation 1 0 Connector Signal Descriptions Chapter 4 Signal Connections Signal Name Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your AT E Series board ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channel pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs ACH lt 16 63 gt AIGND Input Analog Input Channels 16 through 63 AT MIO 64E 3 only Each channel pair ACH lt i i 8 gt i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input Analog Input Sense AT MIO 64E 3 only This pin serves as the reference node for any of channels ACH lt 16 63 gt in NRSE configuration DACOOUT AOGND Output DACIOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output
2. Figure 4 38 Mode 1 Input Timing Name Description Minimum Maximum Tl STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 TS Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds National Instruments Corporation 4 55 AT MIO AI E Series User Manual Chapter 4 Signal Connections Mode 1 Output Timing The following are the timing specifications for an output transfer in Mode 1 Name T1 T2 T3 T4 T5 T6 Figure 4 39 Mode 1 Output Timing Description WR 0 to INTR 0 WR 1 to Output WR 1 to OBF 0 ACK 0 to OBF 1 ACK Pulse Width ACK 1 to INTR 1 All timing values are in nanoseconds AT MIO AI E Series User Manual 4 56 Minimum Maximum 250 200 150 150 100 150 National Instruments Corporation Mode 2 Bidirectional Timing The following are the timing specifications for bidirectional transfers in Mode 2 Chapter 4 Signal Connections Name T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Figure 4 40 Mode 2 Bidirectional Timing Description WR 1 to OBF 0 Data before STB 1 STB Pulse Width STB 0 to IBF 1 Data after STB 1 ACK 0 to OBF 1 ACK Pulse Width ACK 0 to Output ACK 1 to
3. Board Gain Board Range Software Software Selectable Selectable Bipolar Unipolar 1 10 0 V Oto 10V 2 5 0 V O0to5 V 5 2 0 V 0to2 V 10 1 0V Otol V 20 0 5 V 0 to 0 5 V 50 0 2 V 0to0 2V 100 0 1 V 0to0 1V Input coupling eee eee DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V Inputs protected powered off Ree reas ACH lt 0 15 gt AISENSE FIFO buffer size nnn 512 samples Data tramsters ecseri niee DMA interrupts programmed I O DMA M0d S 025 5 3scscchsetsesssssssesseseroess Single transfer demand transfer National Instruments Corporation A 19 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 AT MIO AI E Series User Manual Configuration memory Ssize 512 words Transfer Characteristics Relative accuracy cseeeeeeeeee eens 0 75 LSB typ 1 LSB max DNE eror et ee eiee 0 5 LSB typ 1 LSB max No missing codes 16 bits guaranteed Offset error Pregain error after calibration 3 uV max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 WV max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 0 0 2 150 ppm of reading max With
4. DAQ Click here to comment on this document via the National Instruments website at http www natinst com documentation daa AT MIO AI E Series User Manual Multifunction I O Boards for the PC AT May 1996 Edition Part Number 320517E 01 Copyright 1994 1996 National Instruments Corporation All Rights Reserved Internet Support GPIB gpib support natinst com DAQ daq support natinst com VXI vxi support natinst com LabVIEW lv support natinst com LabWindows lw support natinst com HiQ hiq support natinst com E mail info natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 or 800 327 3077 BBS United Kingdom 01635 551422 BBS France 1 48 65 15 59 FaxBack Support 512 418 1111 Telephone Support U S Tel 512 795 8248 Fax 512 794 5678 ae International Offices Australia 03 9 879 9422 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 National Instruments Corporate Headquarters 6504 Bridg
5. ccc eeecceeeceeeceeeeeseeeeees 12 bits 1 in 4 096 Max update rate oo eee 100 kS s Type of DAC isin chiiedionetns Double buffered multiplying FIFO buffer size sereins None National Instruments Corporation A 13 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 AT MIO AI E Series User Manual Data transfers cccccceeccceeceeeseeeeeees DMA interrupts programmed I O DMA mode eene Single transfer Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 2 0 00 cceeeeeeeeeeeeeeeee 4 LSB max DNL After calibration s s s 0 3 LSB typ 1 0 LSB max Before calibration eee 3 LSB max Monotonicity oe ceeeeeeeeeeceeeeeeeeeeeeeeees 12 bits guaranteed after calibration Offset error After calibration cccee ces 1 0 mV max Before calibration cc c088s 200 mV max Gain error relative to internal reference After calibration s s s 0 01 of output max Before calibration 0 0 5 of output max Gain error relative to external reference 0 to 0 5 of output max not adjustable Voltage Output Range Soinua eed retais gite 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling 0 0 eee DC Output impedance ee 0 1 Q max C rrent driverene en e aE 5 mA max ProtectON sscisi n ann
6. Slew rate Glitch energy at midscale transition Magnitude Reglitching disabled Reglitching enabled Duration eee ceeeeeeseseeeeees Stability Offset temperature coefficient Gain temperature coefficient Internal reference ee External reference 000008 National Instruments Corporation A 7 0 to 0 5 of output max not adjustable 10 V 0 to 10 V tEXTREF 0 to EXTREF software selectable DC 0 1 Q max 5 mA max Short circuit to ground OV 11V 25 V powered on 15 V powered off 200 mV 30 mV 1 5 us 50 uV C 25 ppm C 25 ppm C AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Onboard calibration reference Level vecicscceneietienuncenniias 5 000 V 42 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 0 15 ppm 1 000 h Digital 1 0 Number of channels 00 eee 8 input output Compatibility 00 00 e cece TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 320 uA Vin 0 V Input high current 10 pA Vin 5 V Output low voltage lot 24 mA 0 4 V Output high voltage oH 13 mA 4 35 V POWe ON State neern Input High Z Data transfers siriana Programmed I O Tim
7. ACH lt 0 15 gt rome So Ground co Instrumentation Referenced Amplifier Signal Source So Input Multiplexers Measured Common AISENSE J Voltage Mode __AIGND Noise and Ground is Potential IZ Selected Channel in NRSE Configuration I O Connector Figure 4 9 Single Ended Input Connections for Ground Referenced Signal Common Mode Signal Rejection Considerations Figures 4 6 and 4 9 show connections for signal sources that are already referenced to some ground point with respect to the AT E Series board In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as long as V and V are both within 11 V of AIGND The AT MIO 16XE 50 has the additional restriction that V j V jn added to the gain times Vt V in must be within 26 V of AIGND At gains of 10 and 100 this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND AT MIO AI E Series User Manual 4 26 National Instruments Corporation Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DACOOUT DACIOUT EXTREF and AOGND DACOOUT and DACIOUT are not available on
8. o N BR oO OD N oo Figure B 2 68 Pin DIO Connector Pin Assignments National Instruments Corporation B 3 AT MIO AI E Series User Manual Appendix B Optional Cable Connector Descriptions Figure B 3 shows the pin assignments for the 68 pin extended analog input connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 64E 3 wo A ACH 16 ACH 25 ACH 26 ACH 19 ACH 28 ACH 29 ACH 22 ACH 31 ACH 40 ACH 33 ACH 42 ACH 43 AISENSE2 ACH 36 ACH 45 ACH 46 ACH 39 ACH 56 ACH 57 ACH 50 ACH 59 ACH 60 ACH 53 ACH 62 ACH 63 N C N C N C N C N C N C N C N C N C wo oo wo PO wo brg amp Oo N o N N XN N oO N oa Po A N oo N Po N a N oO ik o 18 es N oO 4 oa A oo mti M k ai Oo o P v BR OH DM N co Figure B 3 68 Pin Extended Analog Input Connector Pin Assignments AT MIO AI E Series User Manual B 4 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 4 shows the pin assignments for the 50 pin MIO connector This connector is available when you use the SH6850 or R6850 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10
9. C 3 AT MIO AI E Series User Manual Appendix C Common Questions AT MIO AI E Series User Manual 15 16 17 Can I sample across a number of channels on an AT E Series board while each channel is being sampled at a different rate NI DAQ for PC compatibles version 4 5 1 or later features a new function called SCAN_Sequence_Setup which allows for multirate scanning of your analog input channels Refer to the NI DAQ Function Reference Manual for PC Compatibles for more details I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal The AT MIO 16E 1 AT MIO 16E 2 and the AT MIO 64E 3 boards have built in reglitchers which can be enabled through software on their analog output channels See the Analog Output Reglitch Selection section in Chapter 3 for more information about reglitching Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my AT E Series board Yes One way to accomplish this is to use the waveform generation timing pulses to cont
10. 5at0 4 1 5 50 kQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 kQ pu GPCTRO_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu FREQ_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ National Instruments Corporation 4 13 AT MIO AI E Series User Manual Chapter 4 Signal Connections Table 4 4 shows the I O signal summary for the AT MIO 16XE 50 Table 4 4 1 0 Signal Summary AT MIO 16XE 50 Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns ACH lt 0 15 gt AI 20 GQ in 25 15 3 nA parallel with 100 pF AISENSE AI 20 GQ in 25 15 3 nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 Sat 10 2 to ground V us DAC1OUT AO 0 1 Q Short circuit 5 at 10 Sat 10 2 to ground V us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24at0 4 1 1 50 KQ pu SCANCLK DO 3 5 at Voc 0 4 5at0 4 1 5 50 kQ p
11. AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 The AT E Series boards are high performance multifunction analog digital and timing I O boards for the PC AT series computers Supported functions include analog input analog output digital I O and timing I O Organization of This Manual The AT MIO AI E Series User Manual is organized as follows National Instruments Corporation Chapter 1 Introduction describes the AT E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your AT E Series board Chapter 2 Installation and Configuration explains how to install and configure your AT E Series board Chapter 3 Hardware Overview presents an overview of the hardware functions on your AT E Series board xi AT MIO AI E Series User Manual About This Manual e Chapter 4 Signal Connections describes how to make input and output signal connections to your AT E Series board via the board T O connector e Chapter 5 Calibration discusses the calibration procedures for your AT E Series board e Appendix A Specifications lists the specifications of each board in the AT E Series e Appendix B Optional Cable Connector Descriptions describes the connectors on the optional cables for the AT E Series boards e Appendix C Common Questions contains a list of commonly as
12. ty 50 100 ns Figure 4 24 CONVERT Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the AT E Series board normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in readiness for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate 4 40 National Instruments Corporation Chapter4 Signal Connections AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a data acquisition sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal
13. 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 8 PFIs programmable function inputs 4 31 to 4 32 common questions about C 7 C 7 to C 8 overview 4 30 signal routing 3 19 to 3 20 National Instruments Corporation Index PGIA programmable gain instrumentation amplifier common mode signal rejection 4 26 differential connections floating signal sources 4 22 to 4 23 ground referenced signal sources 4 21 physical specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 pin assignments See I O connectors Plug and Play systems configuring 2 3 polarity input polarity and range 3 7 to 3 10 output polarity selection 3 14 to 3 15 Port C signal assignments table 4 53 posttriggered data acquisition 4 32 power connections 4 30 power requirement specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 pretriggered data acquisition 4 32 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier AT MIO AI E Series User Manual Index Q questions about AT E series boards C 1 to C 8 analog input and analog output C
14. I O Connector AT E Series Board Figure 4 12 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the board I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin You must be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The National Instruments Corporation 4 31 AT MIO AI E Series User Manual Chapter 4 Signal Connections detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity se
15. 15 gt Al 100 GQ in 35 25 200 pA parallel with 50 pF AISENSE AI 100 GQ in 35 25 200 pA parallel with 50 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 15 to ground V us DAC1OUT AO 0 1 Q Short circuit 5 at 10 5 at 10 15 to ground V us EXTREF AI 10 kQ 35 25 AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24at0 4 1 1 50 KQ pu PA lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5at0 4 5 100 KQ pu PB lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5at0 4 5 100 KQ pu PC lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5at0 4 5 100 KQ pu SCANCLK DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu EXTSTROBE DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFIO TRIG1 DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI1 TRIG2 DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu AT MIO AI E Series User Manual 4 10 National Instruments Corporation Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 Continued Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at V Time Output On Off ns PFI3 GPCTRI_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI4 GPCTR1_GATE DI
16. 500 mV 244 14 uV 20 0 250 to 250 mV 122 07 uV 50 0 100 to 100 mV 48 83 uV 100 0 50 to 50 mV 24 41 uV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings 3 8 National Instruments Corporation Chapter 3 Hardware Overview AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V iefp Where Vef is a positive reference voltage Bipolar input means that the input voltage range is between Vef and V ef The AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely ce Note You can calibrate your AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 analog input circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in your scan list and you are using NI DAQ then NI DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured National Instruments Corporation The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges
17. AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 50 pin connectors available when you use the R1005050 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10UT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND 5V 5 V SCANCLK EXTSTROBE PFIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT Figure B 4 50 Pin MIO Connector Pin Assignments National Instruments Corporation B 5 AT MIO AI E Series User Manual Appendix B Optional Cable Connector Descriptions Figure B 5 shows the pin assignments for the 50 pin DIO connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MIO 16DE 10 Figure B 5 50 Pin DIO Connector Pin Assignments AT MIO AI E Series User Manual B 6 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 6 shows the pin assignments for the 50 pin extended analog input connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MI
18. AT MIO AI E Series User Manual 3 4 National Instruments Corporation Chapter 3 Hardware Overview Figure 3 5 shows a block diagram for the AT AI 16XE 10 Voltage Mux Mode Eine Selection Switches Calibration Mux Calibration Programmable Gain Amplifier Trigger Level 2 Analog DACs Trigger Circuitry Trigger Configuration Memory 16 Bit Sampling A D Converter Data Transceivers Al Control EEPROM PFI Trigger Trigger Counter A Timing I O Digital I O 8 I O Connector National Instruments Corporation j Digital VO Analog Input Timing Control DAQ STC DMA Interrupt Request Interface 1 Analog Output 1 RTSI Bus Timing Control_ Interface DMA ND vy Angee IEEPROMI DMA Control A Control 1 Intertace lt gt DAQ STC Pog Bus pagPnP an Interface Play 8255 Bus g Output DIO Control 1 contro 1 erfece ie AT I O Channel Data 16 Figure 3 5 AT Al 16XE 10 Block Diagram AT MIO AI E Series User Manual Chapter 3 Hardware Overview Figure 3 6 shows a block diagram for the AT MIO 16XE 50 Voltage REF Mux Mode 16 Bit Selection Samping me sence i Transceivers Converter Calibration EEPROM Configuration Memory Al Control IRQ rin DMA FAD DMA y 4 PFI Trigger bail Counter D
19. Data Acquisition Timing Connections 00 eee ee eeeeeeeeeeeeeseeceesneceeenseenees 4 32 SCANCEK Signal seset ao eE EE E E 4 33 EXTSTROBE Signal oo eee ceceeeceeceeeeeeeeeeeseeeseecseesaecaeenaeenees 4 33 PRIG TSI Stal ice E oc Sessgsess pees E sessgcusts sepa EEE 4 34 TRIC Signal a aie aes oy Se 4 36 SEARTSCAN Signal mean a hiss aae EE E e 4 37 CONVERT Signaleer eie a RE EEs 4 39 AIGA TE S18 tial AEE E E E E EE E EEE ES 4 41 SISOURCE Signal roor a E E E ERS 4 41 Waveform Generation Timing Connections s eeseeeeeeseeressereresrreesreersreereees 4 42 WETRIG Signal sn a e a AT E RE Neha 4 42 UPDATE Signal Teee ee coves eeen e E Nepero EE SERET EEE Epei EEEE ONET 4 43 UISOURCE Sigjal c cccc sscssceeseevacecceeicenste ssesceeviossdgceesunsbadeeebvasbedes 4 45 General Purpose Timing Signal Connections 00 eee eee eeesecseessecneeeseenees 4 46 GPCTRO_SOURCE Signal wo eee eeeeeeeeeceeaesseenaeenees 4 46 GPCTRO GATE Siena esse socdstacs space eenen aaae eae t STA REE EE SEEE EEE 4 47 GPCTRO_OUT Signal eestin iet area CE i 4 47 GPCTRO_UP_DOWN Signal easier eiee E E 4 48 GPCTR1_SOURCE Signal eseseesessesessseesrsrrersresrerrsseerrsreresresesrenreees 4 48 GPCTRI GATE Sisnal poves penpe se teepee sessgousepssees ov steeped SNS ETN 4 49 GPCTRI OUT Sigjali n arn keen Ene E a En 4 50 GPCTR1_UP_DOWN Signal 00 00 00 ee eeeenseseeenseenseneeneeceeeneessees 4 51 FREQ OUT Signal icc ci tees hie eedate aig ke
20. FIFO FREQ OUT ft National Instruments Corporation Glossary digital to analog D A converter analog channel 0 output signal analog channel output signal data acquisition direct current digital ground signal differential mode digital input output direct memory access differential nonlinearity electrically erasable programmable read only memory Extended Industry Standard Architecture external reference signal external strobe signal first in first out frequency output signal feet G 3 AT MIO AI E Series User Manual Glossary G GPCTRO_GATE GPCTR1_GATE GPCTRO_OUT GPCTR1_OUT GPCTRO_SOURCE GPCTR1_SOURCE 1 0 IOH IOL ISA L LASTCHAN LSB MB MIO AT MIO AI E Series User Manual general purpose counter 0 gate signal general purpose counter 1 gate signal general purpose counter 0 output signal general purpose counter 1 output signal general purpose counter 0 clock source signal general purpose counter 1 clock source signal hour hexadecimal hertz input output current output high current output low Industry Standard Architecture last channel bit least significant bit megabytes of memory multifunction I O G 4 National Instruments Corporation MSB NRSE OUT PC PFI PGIA ppm rms RSE RTD RTSI S s S SCANCLK SCXI SE SISOURCE National Instruments Corporation Glossary most significant bit nonreferenced single ended mode
21. selection 3 14 to 3 15 reference selection 3 14 reglitch selection 3 15 analog trigger 3 15 to 3 18 block diagram 3 16 AT AI 16XE 10 block diagram 3 5 AT MIO 16E 1 and AT MIO 16E 2 block diagram 3 1 AT MIO 16E 10 and AT MIO 16DE 10 block diagram 3 3 AT MIO 16XE 10 block diagram 3 4 AT MIO 16XE 50 block diagram 3 6 AT MIO 64E 3 block diagram 3 2 digital I O 3 19 timing signal routing 3 19 to 3 22 board and RTSI clocks 3 21 programmable function inputs 3 20 to 3 21 RTSI triggers 3 21 to 3 22 National Instruments Corporation T O connectors 4 1 to 4 15 exceeding maximum ratings warning 4 1 4 16 4 29 TO signal summary table AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 4 8 to 4 9 AT MIO 16E 10 and AT MIO 16DE 10 4 10 to 4 11 AT MIO 16XE 10 and AT AI 16XE 10 4 12 to 4 13 AT MIO 16XE 50 4 14 to 4 15 signal descriptions table 4 5 to 4 8 IBF signal table 4 54 input characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 1 to A 2 AT MIO 16E 10 and AT MIO 16DE 10 A 11 to A 12 AT MIO 16XE 10 and AT AI 16XE 10 A 19 to A 20 AT MIO 16XE 50 A 26 input configurations 4 18 to 4 26 available input modes 3 6 to 3 7 DIFF table 3 7 NRSE table 3 7 RSE table 3 7 common mode signal rejection 4 26 differential connections DIFF input configuration 4 20 floating signal sources 4 22 to 4 23 ground referenced signal sources 4 21 nonreferenced signal sources 4 22 to 4 23 single ended c
22. 18 Ground Referenced Signal Sources oo eee eeessecseceseceeceseeeeceeeseeeeeeeseeaeeees 4 18 Input Configurations ees 53 560 dep onre reer er Er Sree a Eene ee raie R dase EE Gash ete 4 18 Differential Connection Considerations DIFF Input Configuration 4 20 Differential Connections for Ground Referenced Signal Sources oeei toe shee sind E E E ett 4 21 Differential Connections for Nonreferenced or Floating Signal SOULCES es 4 ah casters ee enea eenn se ee ae ree E Epeen Iet 4 22 Single Ended Connection Considerations eesessesesssseeeserereerserersereresreersreee 4 24 Single Ended Connections for Floating Signal Sources RSE Configuration sasie nenio ae a S 4 25 Single Ended Connections for Grounded Signal Sources NRSE Configuration e sessesssscsessesssersessesssessesresosesdesstsseeedesseseeee 4 25 Common Mode Signal Rejection Considerations eseseeeeseereeseerersreesrereee 4 26 Analog Output Signal Connections 20 ec eeeeecscessecseeeseceecesecneceseeeeeseeseeeeeeeeeeaeeees 4 27 Digital I O Signal Connections eee eee eeeeeeecreesseceesaecaecaecseceseseeeseeeeeeeeeeeeeaeeees 4 28 AT MIO AI E Series User Manual vi National Instruments Corporation Table of Contents Power Connections nisni ernn a E E A EE AE EA ER eeaven N 4 30 Timing Connections seses a e tases aee ae eee E AE EEE sepia sed EEE pe OESE 4 30 Programmable Function Input Connections sssseeseseeeeseeeesesrereseeersreersresreees 4 31
23. 2 mV actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 0 15 ppm 1 000 h National Instruments Corporation A 29 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Digital 1 0 Number of channels 8 input output Compatibility 0 0 0 ee eens TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current n 320 uA Input high current 10 pA Output low voltage lot 24 mA 0 4 V Output high voltage oH 13 mA 4 35 V Power on State ececeeeeeeeeeceeeeeeeeeeeeee Input High Z Data transfers Programmed I O Timing 1 0 Number of channels 000 eee 2 up down counter timers 1 frequency scaler Resolution Counter timers 00 eee eeeee 24 bits Frequency scaler 4 bits Compatibility 0 000 eeeeeeeee TTL CMOS Base clocks available Counter timers cccccceeeeeeees 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy ceeceeeeeeeeeeee 0 01 20 MHz Min source pulse duration 10 ns edge detect mode Max source frequency AT MIO AI E Series User Manual A 30 National Instruments Corporation Min gate pulse duration Data transfers DMA modes Triggers Appendix A Specifications for AT MIO 16XE 50 Digital Trigger Compatibility Response Pulse widt
24. 3 to C 5 general information C 1 to C 2 installation and configuration C 2 to C 3 timing and digital I O C 5 to C 8 R RD signal table 4 54 reference selection analog output 3 14 referenced single ended input RSE See RSE referenced single ended input register level programming 1 5 reglitch selection 3 15 RSE referenced single ended input description table 3 7 single ended connections for floating signal sources 4 25 RTSI clocks 3 21 RTSI triggers 3 21 to 3 22 overview 3 21 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 S SCANCLK signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 AT MIO AI E Series User Manual 1 10 description table 4 6 timing connections 4 33 settling time 3 12 to 3 13 C 1 to C 2 signal connections analog input 4 16 to 4 17 analog output 4 27 to 4 28 digital I O 4 28 to 4 29 field wiring considerations 4 58 T O connector 4 1 to 4 15 exceeding maximum ratings warning 4 1 4 16 4 29 TO signal summary table AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 4 8 to 4 9 AT MIO 16E 10 and AT MIO 16DE 10 4 10 to 4 11 AT MIO 16XE 10 and AT AI 16XE 10 4 12 to 4 13 AT MIO 16XE 50 4 14 to 4 15 signal descriptio
25. 4 14 for the relationship of TRIG1 to the data acquisition sequence As an input the TRIG signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 64E 3 support analog triggering on the PFIO TRIGI pin See Chapter 3 for more information on analog triggering As an output the TRIGI signal reflects the action that initiates a data acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 17 and 4 18 show the input and output timing requirements for the TRIGI signal 4 34 National Instruments Corporation Chapter4 Signal Connections Rising edge polarity Falling edge polarity ty 10ns minimum tw 50 100 ns Figure 4 18 TRIG1 Output Signal Timing The board also uses the TRIG1 signal to initiate pretriggered data acquisition operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG and TRI
26. 7 gt DGND Input or Port C These pins are port C of the extra digital I O signals Output on the AT MIO 16DE 10 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input PFI0 Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section in Chapter 2 Analog trigger is available only on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 64E 3 Output As an output this is the TRIG1 signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input PFI1 Trigger 2 As an input this is one of the PFIs Output As an output this is the TRIG2 signal In pretrigger
27. ACHO ACH1 67 AIGND AIGND 66 ACH ACH10 65 ACH2 ACH3 64 AIGND AIGND 63 ACH11 ACH4 62 AISENSE AIGND 61 ACH12 ACH13 60 ACHS ACH6 59 AIGND AIGND 58 ACH14 ACH15 57 ACH7 DACOOUT 56 AIGND DACIOUT 55 AOGND EXTREF 54 AOGND DIO4 53 DGND DGND 52 DIOO DIO1 51 DIO5 DIO6 50 DGND DGND 49 DIO2 45V 48 DIO7 DGND 47 DIO3 DGND 46 SCANCLK PFIO TRIG1 45 EXTSTROBE PFI1 TRIG2 10 44 DGND DGND 43 PFI2 CONVERT 5 V 42 PFI3 GPCTR1_SOURCE DGND 41 PFI4 GPCTR1_GATE PFI5 UPDATE 40 GPCTR1_OUT PFI6 WFTRIG 39 DGND DGND 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 36 DGND FREQ_oUT 1135 DGND N ojo oe ar N i oO 4 oa a A 4 wo 4 N a o oj o P oO BR oO OD N oo Not available on AT Al 16XE 10 2 Not available on AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Figure 4 1 1 0 Connector Pin Assignment for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT Al 16XE 10 and AT MIO 16XE 50 AT MIO AI E Series User Manual 4 2 National Instruments Corporation Chapter 4 Signal Connections AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10OUT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 N A VN o
28. AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI4 GPCTR1_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI5 UPDATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 National Instruments Corporation AT MIO 16XE 50 table 4 15 description table 4 7 PFI6 WFTRIG signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 7 PFI7 STARTSCAN signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 7 PFI8 GPCTRO_SOURCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 7 PFI9 GPCTRO_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table
29. DIO 32F default 4 Cascade for DMA Controller 1 channels 0 through 3 i Note EISA computers also have channels 0 3 available as 16 bit DMA channels National Instruments Corporation 2 7 AT MIO AI E Series User Manual Hardware Overview Chapter This chapter presents an overview of the hardware functions on your ATE Series board Figure 3 1 shows the block diagram for the AT MIO 16E 1 and AT MIO 16E 2 Selection Switches Calibration Dither J Mux Circuitry Calibration 12 Bit Sampling A D Converter Data Transceivers Trigger Level J 2 Bacs Analog Trigger Trigger Circuitry Configuration Memory Al Control EEPROM PFI Trigger Trigger Analog Input Timing Control Counter Timing Timing I O DAQ STC Digital 1 0 I O Connector Digital O 8 1 Analog Output Timing Control DMA Interrupt Request Interface RTS Bus Interface Analog IEEPROM DMA aR Control Interface DAQ STC Bus DAQ PnP Interface Analog 8255 Output DIO Control 1 Control AT I O Channel National Instruments Corporation AO Control Calibration DACs Figure 3 1 AT MIO 16E 1 and AT MIO 16E 2 Block Diagram C AT MIO AI E Series User Manual Chapter 3 Hardware Overview Figure 3 2 shows the block diagram fo
30. GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 37 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your ATE Series board Source Clock Period minimum Source Pulse Width minimum Gate Setup Time minimum Gate Hold Time minimum Gate Pulse Width minimum Output Delay Time maximum Figure 4 37 GPCTR Timing Summary National Instruments Corporation 4 51 AT MIO AI E Series User Manual Chapter 4 Signal Connections The GATE and OUT signal transitions shown in Figure 4 37 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your ATE Series board Figure 4 37 shows the GATE signal referenced to the rising edge of a source signal The gate mu
31. Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ RTSI DAQCard DAQPad DAQ PnP DAQ STC NI PGIA and SCXI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified me
32. MIO 16XE 50 3 9 to 3 10 mixing bipolar and unipolar channels note 3 9 unipolar output 3 14 to 3 15 unpacking AT E series boards 1 7 UPDATE signal timing connections 4 43 to 4 44 V VCC signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE S50 table 4 14 voltage output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO AI E Series User Manual 1 14 AT MIO 16E 10 and AT MIO 16DE 10 A 14 to A 15 AT MIO 16XE 10 A 22 AT MIO 16XE 50 A 29 W waveform generation timing connections 4 42 to 4 45 UISOURCE signal 4 45 UPDATE signal 4 43 to 4 44 WFTRIG signal 4 42 to 4 43 WFTRIG signal timing connections 4 42 to 4 43 wiring considerations 4 58 WR signal table 4 54 National Instruments Corporation
33. MIO AI E Series User Manual A 4 National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 System noise LSBrms Gain Noise Noise not including quantization dither off dither on AT MIO 16E 1 0 5 to 10 0 25 0 5 20 0 4 0 6 50 0 5 0 7 100 0 8 0 9 AT MIO 16E 2 0 5 to 20 0 15 0 5 AT MIO 64E 3 50 0 3 0 6 100 0 5 0 7 Crosstalkci ssc caostesasiecd casetdesds sects E 80 dB DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient PREG AIN asiar aens ep e e 5 uV C Postga ee 240 uV C Gain temperature coefficient 20 ppm C Onboard calibration reference Levelscc ck whine 5 000 V 42 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 00 0 15 ppm 1 000 h National Instruments Corporation A 5 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MI0O 16E 2 and AT MIO 64E 3 Analog Output AT MIO AI E Series User Manual Output Characteristics Number of channels ceeeeeeeeeeeee 2 voltage ReSOlution ccecc cece ceeecceeceeeeeeeeeeees 12 bits 1 in 4 096 Max update rate FIFO mode waveform generation Internally timed 0 0 1 MS s per channel Externally timed 0 0 0 0 950 kS s per channel Non FIFO mode waveform generation Ischanneles icre 600 950 kS s system depend
34. Output Float RD 1 to IBF 0 All timing values are in nanoseconds National Instruments Corporation Minimum Maximum 150 20 100 150 50 150 100 150 20 250 150 AT MIO AI E Series User Manual Chapter 4 Signal Connections Field Wiring Considerations AT MIO AI E Series User Manual Environmental noise can seriously affect the accuracy of measurements made with your AT E Series board if you do not take proper care when running signal wires between signal sources and the board The following recommendations apply mainly to analog input signal routing to the board although they also apply to signal routing in general You can minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the board With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the board carefully Keep cabling away from noise sources The most common noise source in a PC data acquisition system is the video monitor Separate th
35. Series boards are fully compatible with the industry standard Plug and Play ISA specification A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the board base I O address DMA channels and interrupt channels Each AT E Series board is configured at the factory to request these resources from the Plug and Play Configuration Manager The Configuration Manager receives all of the resource requests at start up compares the available resources to those requested and assigns the available resources as efficiently as possible to the Plug and Play boards Application software can query the Configuration Manager to determine the resources assigned to each board without your involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS Switchless Data Acquisition You can use an AT E Series board in a non Plug and Play system as a switchless DAQ board A non Plug and Play system is a system in which the Configuration Manager has not been installed and which does not contain any non National Instruments Plug and Play products You use a configuration utility to enter the base address DMA and interrupt selections and the application software assigns them to the board i Note Avoid resource conflicts with non National Instruments boards For example do not configure two boards for the sam
36. Table 2 1 PC AT I O Address Map uu cece ceseececesecesceeeeeeceseeeeceseeeneeseesaecaeeneenaes 2 4 Table 2 2 PC AT Interrupt Assignment Map ooo eee ee eeeeeeeeeeeeseeenecneeeneenaes 2 6 Table 2 3 PC AT 16 bit DMA Channel Assignment Map eee eee eee ere eeees 2 7 Table 3 1 Available Input Configurations for the AT E Series 2 0 0 eee 3 7 Table 3 2 Actual Range and Measurement Precision eee eee eseseeseeeeeeneeeees 3 8 Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 oo eee cee eeeceeeeeeeeeeees 3 10 Table 4 1 I O Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AST MIO 64 E 3 5 accscbectsncestissscesesecisiis E E o Hage EEEE EE RER 4 8 Table 4 2 I O Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 4 10 Table 4 3 I O Signal Summary AT MIO 16XE 10 and AT AI 16XE 10 000 000 4 12 Table 4 4 I O Signal Summary AT MIO 16XE 50 ooo cseeseecneensecseenaes 4 14 Table 4 5 Port C Signal Assignment 20 0 0 eee eeceeeeeeeeceeeeeeceseeeneeseecaecneeeneenaes 4 53 AT MIO AI E Series User Manual X National Instruments Corporation About This Manual This manual describes the electrical and mechanical aspects of each board in the AT E Series product line and contains information concerning their operation and programming Unless otherwise noted text applies to all boards in the AT E Series The AT E Series includes the following boards
37. addresses What jumpers should I be aware of when configuring my AT E Series board The AT E Series boards do not contain any jumpers they are also switchless Which National Instruments manual should I read first to get started using DAQ software If you are using LabVIEW Chapter 1 of the LabVIEW Data Acquisition VI Reference Manual is the best place to get started If you are programming with NI DAQ function calls or using LabWindows CVI the NI DAQ User Manual for PC Compatibles is the best starting place What version of NI DAQ must I have to program my AT E Series board You must have version 4 9 0 or higher for the AT MIO 16XE 10 and AT AI 16XE 10 version 4 8 0 or higher for the AT MIO 16E 1 and version 4 6 1 or higher for all other AT E Series boards C 2 National Instruments Corporation Appendix C Common Questions 10 What special calls must be made in DOS or LabWindows to use 11 AT E Series boards To link in the AT E Series function calls you must call USE_E_Series or one of its subsets What is the best way to test my board without having to program the board If you are using Windows the WOAQCONF utility has a Test menu with some excellent tools for doing simple functional tests of the board such as analog input and output digital I O and counter timer tests Also the Test Configuration option will verify that the base address interrupt and DMA settings for the board are functio
38. applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications AT MIO AI E Series User Manual National Instruments Corporation Chapter 4 Signal Connections Signal Name Reference Direction Description Continued PFI2 CONVERT DGND Input PFI2 Convert As an input this is one of the PFIs Output As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output PFIS5 UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG signal In ti
39. connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the AT E Series board are greater than 10 ft 3 m e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA 4 20 National Instruments Corporation Chapter 4 Signal Connections Differential Connections for Ground Referenced Signal Sources Figure 4 6 shows how to connect a ground referenced signal source to an AT E Series board channel configured in DIFF input mode ACH lt 0 7 gt 0o Ground Co Referenced So Signal V Instrumentation Source Amplifier So ACH lt 8 15 gt Oo Common Mode co Noise and V So Ground Potential Measured Voltage Input Multiplexers oe AISENSE _ AIGND Selected Channel in DIFF Configuration 1 O Connector Figure 4 6 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT E Series board ground shown as Vo
40. differential and common mode input ranges distorts your s7 input signals Exceeding the maximum input voltage rating can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in Tables 4 1 through 4 4 in the Protection column AT MIO AI E Series User Manual In NRSE mode the AISENSE and AISENSE2 signals are connected internally to the negative input of the AT E Series board PGIA when their corresponding channels are selected In DIFF and RSE modes these signals are left unconnected AIGND is an analog input common signal that is routed directly to the ground tie point on the AT E Series boards You can use this signal for a general analog ground tie point to your AT E Series board if necessary Connection of analog input signals to your AT E Series board depends on the configuration of the analog input channels you are using and the type of input signal source With the different configurations you can 4 16 National Instruments Corporation Chapter 4 Signal Connections use the PGIA in different ways Figure 4 4 shows a diagram of your AT E Series board PGIA Instrumentation Amplifier Vin Measured Voltage Vin V Vin Gain in Figure 4 4 AT E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to you
41. is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation National Instruments Corporation 4 41 AT MIO AI E Series User Manual Chapter 4 Signal Connections Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 25 shows the timing requirements for the SISOURCE signal tp 50ns minimum ty 23 ns minimum Figure 4 25 SISOURCE Signal Timing Wav
42. of analog output channel 0 This pin is not available on the AT AI 16XE 10 Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 This pin is not available on the AT AI 16XE 10 EXTREF AOGND Input AOGND External Reference This is the external reference input for the analog output circuitry This pin is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your AT E Series board DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on your AT E Series board National Instruments Corporation AT MIO AI E Series User Manual Chapter 4 Signal Connections Signal Name Reference Direction Description Continued DIO lt 0 7 gt DGND Input or Digital I O signals DIO6 and 7 can control the up down Output signal of general purpose counters 0 and 1 respectively PA lt 0 7 gt DGND Input or Port A These pins are port A of the extra digital I O signals Output on the AT MIO 16DE 10 PB lt 0 7 gt DGND Input or Port B These pins are port B of the extra digital I O signals Output on the AT MIO 16DE 10 PC lt 0
43. output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 15 shows the timing for the SCANCLK signal CONVERT SCANCLK ta 50to 100 ns ty 400 to 500 ns Figure 4 15 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the National Instruments Corporation 4 33 AT MIO AI E Series User Manual Chapter 4 Signal Connections AT MIO AI E Series User Manual EXTSTROBE signal A 10 us and a 1 2 Us clock are available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 16 shows the timing for the hardware strobe mode EXTSTROBE signal 600 ns or 5 us Figure 4 16 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIGI signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 13 and
44. superasen ai spaveede 5 mA Protection iiris isss poe oiris Short circuit to ground Power on State cceeeceeeeeeeeeeeeeeeeee 0 V 420 mV A 22 National Instruments Corporation Digital 1 0 Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Dynamic Characteristics Settling time for full scale step 10 us to 1 LSB accuracy Slew Fate ss ni ceinie latins 5 V s NOISE fs scores seees gases goetonhsageoseretnetsnseresone 60 uVrms DC to 1 MHz Stability Offset temperature coefficient 50 uV C Gain temperature coefficient 7 5 ppm C Onboard calibration reference Level ve ccc cscs ect ariennir iive 5 000 V 40 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm 1 000 h Number of channels seeeeeeee 8 input output Compatibility eee eee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 320 pA Input high current 10 pA Output low voltage AOL 24 mA 0 4 V Output high voltage dou 13 mA 4 35 V Power on state eeseeeeeeeseeeseesreeereeee Input High Z Data transfers ccceeeeeecreeereeeeeeeeeeeee Programmed I O National Instruments Corporation A 23 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 Timing 1
45. table 2 4 to 2 5 AIGATE signal 4 41 AIGND signal analog input connections 4 16 to 4 17 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 National Instruments Corporation Index differential connections for floating signal sources 4 22 to 4 23 AISENSE signal analog input connections 4 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 AISENSE2 signal analog input connections 4 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 description table 4 5 amplifier characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 12 AT MIO 16XE 10 and AT AI 16XE 10 A 20 AT MIO 16XE 50 A 27 analog input 3 6 to 3 13 common questions about C 3 to C 5 considerations for selecting input ranges 3 10 dither 3 11 to 3 12 input modes 3 6 to 3 7 input polarity and range 3 7 to 3 10 multiple channel scanning considerations 3 12 to 3 13 signal connections 4 16 to 4 17 1 1 AT MIO AI E Series User Manual Index analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 1 to A 5 amplifier characteristics A 3 dynamic char
46. the AT AI 16XE 10 EXTREF is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 DACOOUT is the voltage output signal for analog output channel 0 DACIOUT is the voltage output signal for analog output channel 1 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference You cannot use an external analog output reference with the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input e Usable input voltage range 11 V peak with respect to AOGND e Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal National Instruments Corporation 4 27 AT MIO AI E Series User Manual Chapter 4 Signal Connections Figure 4 10 shows how to make analog output connections and the external reference input connection to your AT E Series board EXTREF DACOOUT External Channel 0 Reference ref Signal Optional Load A v E VOUTI DAC
47. types of triggering can be implemented in hardware on my AT E Series board Digital triggering is supported by hardware on every AT E Series MIO board In addition the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 support analog triggering in hardware What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement C 5 AT MIO AI E Series User Manual Appendix C Common Questions AT MIO AI E Series User Manual 20 21 22 23 24 What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO boards have a 20 MHz timebase The Am9513 based MIO boards have a 1 MHz or 5 MHz timebase The counter timer examples supplied with NI DAQ are not compatible with an AT E Series board Where can I find examples to illustrate the use of the DAQ STC as a general purpose counter timer If you are using the NI DAQ language interface and a C compiler under DOS a new subdirectory called GPCT
48. your AT E Series board for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources 4 18 National Instruments Corporation Chapter 4 Signal Connections Figure 4 5 summarizes the recommended input configuration for both types of signal sources NOT RECOMMENDED gt Ground loop losses Vg are added to measured signal Figure 4 5 Summary of Analog Input Connections National Instruments Corporation 4 19 AT MIO AI E Series User Manual Chapter 4 Signal Connections Differential Connection Considerations DIFF Input Configuration AT MIO AI E Series User Manual A differential connection is one in which the AT E Series board analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available up to 32 channels on the AT MIO 64E 3 You should use differential input
49. 0 Number of channels 0000008 2 up down counter timers 1 frequency scaler Resolution Counter timers ccceceeeeeeees 24 bits Frequency scaler 4 bits Compatibility onee inire TTL CMOS Base clocks available Counter timers seseeeeeeeeeesee eee Frequency scaler Base clock accuracy cceceeeceereeereeeee Max source frequency ceeeeeereeee Min source pulse duration 0 Min gate pulse duration eee Data transfers ccccceecccccsssceeeneeeees DMA Mmodes ccccccceeecccesneeceeeneeees Triggers Analog Trigger SOULCE S32 eee eaede sees a E eee Feye Cae ae ona e e aere aa ReSOLUtION ce eeeeeeeeeeeceeeeeeeeeeeeeeeee Hysteresis a a a eE amp Bandwidth 3 dB secese AT MIO AI E Series User Manual A 24 20 MHz 100 kHz 10 MHz 100 kHz 0 01 20 MHz 10 ns edge detect mode 10 ns edge detect mode DMA interrupts programmed I O Single transfer ACH lt 0 15 gt PFIO TRIG1 Full scale internal 10 V external Positive or negative software selectable 12 bits 1 in 4 096 Programmable 255 kHz internal 4 MHz external National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 External input PFIO TRIG1 Impedance Coupling esi irse ProteCtiONn cccccceccceesceeeseeeeees ACCULACY oriniai Digital Trigger Compatibility 0 eee RES POMS C
50. 14 ACH15 57 ACH7 DACOOUT 56 AIGND DAC1OUT 55 AOGND EXTREF 54 AOGND DIO4 53 DGND DGND 52 DIO0 DIO1 51 DIO5 DIO6 50 DGND DGND 49 DIO2 45V 48 DIO7 DGND 47 DIO3 DGND 46 SCANCLK PFIO TRIG1 45 EXTSTROBE PFI1 TRIG2 44 DGND DGND 43 PFI2 CONVERT 45V 42 PFI3 GPCTR1_SOURCE DGND 41 PFI4 GPCTR1_GATE PFI5 UPDATE 40 GPCTR1_OUT PFIG WFTRIG 39 DGND DGND 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 36 DGND FREQ_OUT 35 DGND 4 o a N e gt i oa A k wo N a oO o PP CO BR oO oa IN co Not available on AT AI 16XE 10 2 Not available on AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Figure B 1 68 Pin MIO Connector Pin Assignments AT MIO AI E Series User Manual B 2 National Instruments Corporation Appendix B Optional Cable Connector Descriptions Figure B 2 shows the pin assignments for the 68 pin DIO connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 oe R eo ao ao N oo a oo Oo N o DS N N DS o N oa N R N wo N N N N Oo o 18 are N ak e gt oa ER A wo N Oo
51. 15 1 nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 Sat 10 5 to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 Sat 10 5 to ground V us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24at0 4 1 1 50 KQ pu SCANCLK DO 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFIO TRIG1 DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 4 75 KQ pu PFI1 TRIG2 DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu AT MIO AI E Series User Manual 4 12 National Instruments Corporation Chapter 4 Signal Connections Table 4 3 1 0 Signal Summary AT MIO 16XE 10 and AT Al 16XE 10 Continued Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns PFI5 UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 kQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vcc 0 4
52. 1OUT Channel 1 Analog Output Channels AT E Series Board Figure 4 10 Analog Output Connections The external reference signal can be either a DC or an AC signal The board multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital 1 0 Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking capabilities AT MIO AI E Series User Manual 4 28 National Instruments Corporation Chapter 4 Signal Connections Warning Exceeding the maximum input voltage ratings which are listed in s7 Tables 4 1 through 4 4 can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting from such signal connections Figure 4 11 shows signal connections for three typical digital I O applications DIO lt 4 7 gt TTL Signal DIO lt 0 3 gt Vb 2 Switch I O Connector AT E Series Board Figure 4 11 Di
53. 1_GATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kQ pu PFIS5 UPDATE DIO Vec 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 KQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu GPCTRO_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 KQ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kQ pu DIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output ADIO Analog Digital Input Output 2 Also pulled down with a 10 kQ resistor Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ National Instruments Corporation 4 9 AT MIO AI E Series User Manual Chapter 4 Signal Connections Table 4 2 shows the I O signal summary for the AT MIO 16E 10 and AT MIO 16DE 10 Table 4 2 1 0 Signal Summary AT MIO 16E 10 and AT MIO 16DE 10 Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at V Time Output On Off ns ACH lt 0
54. 2 to 4 43 timing I O specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 to A 9 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 and AT AI 16XE 10 A 24 AT MIO 16XE 50 A 30 to A 31 timing signal routing 3 19 to 3 22 board and RTSI clocks 3 21 programmable function inputs 3 20 to 3 21 RTSI triggers 3 21 to 3 22 transfer characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 12 AT MIO 16XE 10 and AT AI 16XE 10 A 20 AT MIO 16XE 50 A 27 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 to A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16XE 10 A 22 AT MIO 16XE 50 A 28 to A 29 TRIGI signal timing connections 4 34 to 4 35 TRIG signal timing connections 4 36 triggers analog 3 15 to 3 18 block diagram 3 16 RTSI triggers 3 21 to 3 22 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog trigger A 9 digital trigger A 10 RTSI A 10 1 13 AT MIO AI E Series User Manual Index AT MIO 16E 10 and AT MIO 16DE 10 digital trigger A 17 RTSI A 17 AT MIO 16XE 10 and AT AI 16XE 10 analog trigger A 24 to A 25 digital trigger A 25 RTSI A 25 AT MIO 16XE 50 digital trigger A 31 RTSI A 31 troubleshooting See questions about AT E series boards U UISOURCE signal 4 45 unipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 to 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT
55. 3 7 differential connections 4 22 to 4 23 single ended connections NRSE configuration 4 25 0 OBF signal table 4 54 operation of AT E series boards See hardware overview optional equipment 1 5 output characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 AT MIO 16E 10 and AT MIO 16DE 10 A 13 to A 14 AT MIO 16XE 10 A 22 AT MIO 16XE 50 A 28 P PA lt 0 7 gt signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 PB lt 0 7 gt signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 PC lt 0 7 gt signal table 4 6 PFIO TRIG1 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 AT MIO AI E Series User Manual PFI1 TRIG2 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI2 CONVERT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI3 GPCTR1_SOURCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and
56. 4 National Instruments Corporation Chapter4 Signal Connections UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 30 shows the timing requirements for the UISOURCE signal tp 50 ns minimum tw 23 ns minimum Figure 4 30 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source National Instruments Corporation 4 45 AT MIO AI E Series User Manual Chapter 4 Signal Connections General Purpose Timing Signal Connections AT MIO AI E Series User Manual The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ _ OUT GPCTRO_SOURCE Signal Any PFI pin can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is con
57. 5 V Oto 10 V 2 42 5 V OtoS V 5 1V 0to2V 10 500 mV Otol V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Input COUPLING eee eeeeeeeeeeeeeeeeeeee DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection ee 35 V powered on 25 V powered off Inputs protected ee ACH lt 0 15 gt AISENSE FIFO buffer size eee eee 512 samples National Instruments Corporation A 11 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 AT MIO AI E Series User Manual Data transfers ccceeeeeereeereeceeeeeeeeee DMA interrupts programmed I O DMA modes nne Single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy seeeeeeeee cece 0 2 LSB typ dithered 1 0 LSB max undithered DN sna Sagat tea inset 0 2 LSB typ 0 5 LSB max NO missing codes ceeeeeeeeeereeeeeeeeeee 12 bits guaranteed Offset error Pregain error after calibration 2 uV max Pregain error before calibration 24 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration Gain 1 0 01 of reading max Before calibration 0 2 0 of reading max Gain 1 with gain error adjusted to 0 at ga
58. 50 A 31 description table 4 5 DIO lt 0 7 gt signal digital I O connections 4 28 to 4 29 AT MIO 16E 1 AT MIO 16E 2 and digital timing connections 4 30 AT MIO 64E 3 table 4 9 DIFF differential input mode AT MIO 16E 10 and AT MIO 16DE 10 definition table 3 7 table 4 10 description 4 20 AT MIO 16XE 10 and AT AI 16XE 10 ground referenced signal sources 4 21 table 4 12 nonreferenced or floating signal AT MIO 16XE 50 table 4 14 sources 4 22 to 4 23 description table 4 6 single ended connections 4 24 digital I O connections 4 28 to 4 29 floating signal sources RSE 4 25 AT MIO AI E Series User Manual l 4 National Instruments Corporation dither enabling 3 11 to 3 12 DMA channels configuring 2 3 to 2 4 PC AT 16 bit DMA channel assignment map table 2 7 documentation about the manual xi conventions used in manual xii to xiii National Instruments documentation xiii to xiv organization of manual xi to xii related documentation xiv dynamic characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 4 to A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 12 to A 13 AT MIO 16XE 10 and AT AI 16XE 10 A 21 AT MIO 16XE 50 A 27 to A 28 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 A 23 AT MIO 16XE 50 A 29 E EEPROM storage of calibration constants 5 1 e mail support D 2 environment specifications AT MIO 16E 1 AT M
59. AC AC AC AC AC AC AC AC AC AC AC AC AC ACH42 ACH35 ACH43 AISENSE2 AIGND ACH36 ACH44 ACH37 ACH45 ACH38 DIO7 ACH46 DGND ACH39 5 V ACH47 5V ACH48 SCANCLK AC EXTSTROBE AC PFIO TRIG1 AC PFI1 TRIG2 AC PFI2 CONVERT AC PFI3 GPCTR1_SOURCE AC PFI4 GPCTR1_GATE AC GPCTR1_OUT AC PFI5 UPDATE AC PFI6 WFTRIG AC PFI7 STARTSCAN AC PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE AC GPCTRO_OUT AC FREQ_OUT oO N wo A oa D lt i ala oj Ded Oo N ard N N N wo De A nm oa Dey D N lt I N N o wo oO 2 w W Figure 4 2 1 0 Connector Pin Assignment for the AT MIO 64E 3 National Instruments Corporation 4 3 AT MIO AI E Series User Manual Chapter 4 Signal Connections AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC1OUT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND 5V 5V SCANCLK EXTSTROBE PFIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT COIN OD oy A wp
60. AQ STC Pl ing i Timing io DAQ STC interface Bus DAQPnP ane Interface Play Analog Input Interrupt Trigger Timing Control R Guiest Analog TEEPROM DMA q CORUL 1 Control 1 Interface Digital 1 O 8 I O Connector 1 Analog Output 1 RTSI Bus Analog 8255 Bus Output DIO interface Digital VO 1 Timing Control_ Interface Control 1 Control L AT I O Channel Analog Input AO Control Data 16 Calibration DACs Figure 3 6 AT MIO 16XE 50 Block Diagram Input Mode AT MIO AI E Series User Manual 3 6 The analog input section of each AT E Series board is software configurable You can select different analog input configurations through application software designed to control the AT E Series boards The following sections describe in detail each of the analog input categories The AT E Series boards have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 16 channels 64 channels on the AT MIO 64E 3 The DIFF input configuration uses up to eight channels 32 channels on the AT MIO 64E 3 Input modes are National Instruments Corporation Chapter 3 Hardware Overview programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels fou
61. C Gain temperature coefficient 7 ppm C Onboard calibration reference Wevelscca arunt e ae 5 000 V 40 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm 1 000 h National Instruments Corporation A 21 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT Al 16XE 10 Analog Output AT AT MIO AI E Series User Manual MIO 16XE 10 only Output Characteristics Number of channels cceeeeeeeeeeeee 2 voltage Resolution ceccccceseeeceeeeeeeeeeaeeeees 16 bits 1 in 65 536 Max update rate 00 0 eee 100 kS s Type of DAC sc iscsetisscessehicheies Double buffered FIFO buffer size eee eee 2 048 samples Data transfers aneneen DMA interrupts programmed I O DMA M d So pprt opsapienes Single transfer demand transfer Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max DN a e A 1 LSB max Monotonicity seseeseeeeceeeseeeererersrrerereeee 16 bits guaranteed Offset error After calibration 0 0 0 305 uV max Before calibration 000 20 mV max Gain error relative to internal reference After calibration ee 30 5 ppm max Before calibration s s s 2 000 ppm max Voltage Output Range inostrana tied eek 10 V 0 to 10 V software selectable Output coupling 0 0 eee DC Output impedance ee 0 1 Q C rrent ATIVE
62. CLK Signal Timing 00 eee eee eeeceeeeeeeeeeeeecaeesaecaaesaecneenaeenees 4 33 Figure 4 16 EXTSTROBE Signal Timing 0 0 eee eee eee cneeeee cesses ceeeaecneesneenees 4 34 Figure 4 17 TRIG1 Input Signal Timing 200 eeeeceeeeeceeeseecaeenaecseesaeenees 4 35 Figure 4 18 TRIG1 Output Signal Timing 0 eee ceeceeeeecneeseecaeeaecaeenaeenees 4 35 Figure 4 19 TRIG2 Input Signal Timing 200 ee cee eeeeeeeeeeeceeeseecaeesaecneenaeenees 4 36 Figure 4 20 TRIG2 Output Signal Timing 000 eee eeeeceeeeeceeeseecaeesaecneeaeenees 4 37 Figure 4 21 STARTSCAN Input Signal Timing 0 eeeeeeceeeseecneenaeeseenaeenees 4 38 Figure 4 22 STARTSCAN Output Signal Timing 20 cece eeecneenaecseenneenees 4 38 Figure 4 23 CONVERT Input Signal Timing 0 ee ceeceeceeneeceesaecseenaeenees 4 40 Figure 4 24 CONVERT Output Signal Timing eee cseeseecneensecneenneenees 4 40 Figure 4 25 SISOURCE Signal Timing 0 eee eee ec eeceeeeeeeceeeeeecaeesaecseesaecnecsaeenees 4 42 Figure 4 26 WFTRIG Input Signal Timing 20 0 0 ee eee ceeeeeeceeeseecaeeaecneeaeenees 4 43 Figure 4 27 WFTRIG Output Signal Timing 00 eee eeeeeeceeseecaeensecneenaeenees 4 43 Figure 4 28 UPDATE Input Signal Timing ooo eee ceeeeeecseeseecseeaecneenaeenees 4 44 Figure 4 29 UPDATE Output Signal Timing oe cece cseeneecneenaeeneenaeenees 4 44 Figure 4 30 UISOURCE Signal Timing 000 eee eecceeeeeeeceeeeeeceeeseecaeesaecaeesaeenees 4 45 Figure 4 31 GPCTRO_SOURCE Signal Timing o e
63. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse ___ yes __no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem AT E Series Hardware and Software Click here to comment on this document Configuration Form via the National Instruments website at http www natinst com documentation daq Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical
64. DACs Some form of board calibration is required for all but the most forgiving applications If no board calibration were performed your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and these are described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your AT E Series board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the board is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Cor
65. DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals L Warning If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the board the computer and the connected equipment 26 What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the board circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Tables 4 1 to 4 4 I O Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 1 shows that there is National Instruments Corporation C 7 AT MIO AI E Series User Manual Appendix C Common Questions a 50 KQ pull up resistor This pull up resistor will set the DIO O pin to a logic high when the output is in a high impedance state AT MIO AI E Series User Manual C 8 National Instruments Corporation Click here to commen
66. G2 in a pretriggered data acquisition operation National Instruments Corporation 4 35 AT MIO AI E Series User Manual Chapter 4 Signal Connections TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the data acquisition sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the board will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttr
67. I E Series User Manual Input signal ranges Board Gain Board Range Software Software Selectable Selectable Bipolar Unipolar 0 5 10 V 1 5 V Oto10V 2 2 5 V 0to5 V 5 t1 V 0to2 V 10 500 mV Otol V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Input coupling cece DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ee ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size AT MIO 16E 1 eee 8 192 samples AT MIO 16E 2 AT MIO 64E 3 eeen 2 048 samples Data transfers wiccicicccsseedsseeesoscdocsactiases DMA interrupts programmed I O DMA modes eee Single transfer demand transfer Configuration memory size 512 words National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Transfer Characteristics Relative accuracy eeeeeeeeeeeeeees 0 5 LSB typ dithered 1 5 LSB max undithered DND reee n oe ees Ea 0 5 LSB typ 1 0 LSB max NO MISSING codes ceeeeeeeeeeeeeeeeeeeeee 12 bits guaranteed Offset error Pregain error after calibration 12 uV max Pregain error before calibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After cal
68. IO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 environmental noise avoiding 4 58 National Instruments Corporation Index equipment optional 1 5 EXTREF signal analog output reference connections 4 27 to 4 28 analog output reference selection 3 14 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 5 EXTSTROBE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 30 F fax support D 2 faxback support D 2 field wiring considerations 4 58 floating signal sources description 4 18 differential connections 4 22 to 4 23 single ended connections RSE configuration 4 25 FREQ_ OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 8 waveform generation timing connections 4 52 AT MIO AI E Series User Manual Index frequently asked questions See questions about AT E series boards FTP support D 1 fuse 4 6 G general purpose timing signal connections 4 46 to 4 57 FREQ OUT signal 4 52 GPCTRO_GA
69. Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your board at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your board An external calibration refers to calibrating your board with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your board by calling the NI DAQ calibration function 5 2 National Instruments Corporation Chapter 5 Calibration To externally calibrate your board be sure to use a very accurate external reference The reference should be several times more accurate than the board itself For example to calibrate a 12 bit board the external reference should be at least 0 005 50 ppm accurate To calibrate a 16 bit board the external reference should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the i
70. LabVIEW release notes After you have installed Lab VIEW refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabVIEW If you are using LabWindows CVI refer to your LabWindows CVI release notes After you have installed LabWindows CVI refer to your NI DAQ release notes and follow the instructions given there for your operating system and LabWindows CVI If you are a register level programmer refer to the AT MIO E Series Register Level Programmer Manual and the DAQ STC Technical Reference Manual for software configuration information Hardware Installation You can install an AT E Series board in any available expansion slot in your PC However to achieve best noise performance you should leave as much room as possible between the AT E Series board and other boards and hardware The following are general installation instructions but consult your PC user manual or technical reference manual for specific instructions and warnings National Instruments Corporation 2 1 AT MIO AI E Series User Manual Chapter 2 Installation and Configuration 1 Write down the AT E Series board serial number in the AT E Series Hardware and Software Configuration Form in Appendix D at the back of this manual You will need this serial number when you install and configure your software 2 Turn off and unplug your computer 3 Remove the top cover or access port to the I O channel 4 Remove the ex
71. O Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFIS UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu GPCTRO_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu FREQ_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu DIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ National Instruments Corporation 4 11 AT MIO AI E Series User Manual Chapter 4 Signal Connections Table 4 3 shows the I O signal summary for the AT MIO 16XE 10 and AT AI 16XE 10 Table 4 3 1 0 Signal Summary AT MIO 16XE 10 and AT Al 16XE 10 Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns ACH lt 0 15 gt AI 100 GQ in 25 15 1 nA parallel with 100 pF AISENSE AI 100 GQ in 25
72. O 64E 3 ACH16 ACH17 ACH18 ACH19 ACH20 ACH21 ACH22 ACH23 ACH32 ACH33 ACH34 ACH35 AISENSE2 ACH36 ACH37 ACH38 ACH39 ACH48 ACH49 ACH50 ACH51 ACH52 ACH53 ACH54 ACH55 Figure B 6 50 Pin Extended Analog Input Connector Pin Assignments National Instruments Corporation B 7 AT MIO AI E Series User Manual Common Questions Appendix This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your AT E Series board General Information 1 National Instruments Corporation What are the AT E Series boards The AT E Series boards are switchless and jumperless enhanced MIO boards that use the DAQ STC for timing What is the DAQ STC The DAQ STC is the new system timing control ASIC application specific integrated circuit designed by National Instruments and is the backbone of the AT E Series boards The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other in
73. R which lies beneath the examples directory contains 16 examples of the most common uses of the DAQ STC Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the AT E Series and other boards the counter numbers are different timebase selections are different the DAQ STC counters are 24 bit counters unlike the 16 bit counters on boards without the DAQ STC If you are using NI DAQ language interface LabWindows or LabWindows CVI the answer is no the counter time applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my AT E Series board but I do not see the counter timer output on the I O connector What am I doing wrong If you are using NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated How does NI DAQ treat bogus misse
74. T MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 C cables See also I O connectors field wiring considerations 4 58 optional equipment 1 5 National Instruments Corporation 1 3 Index calibration 5 1 to 5 3 adjusting for gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5 2 self calibration 5 2 charge injection 3 13 clocks board and RTSI 3 21 commonly asked questions See questions about AT E series boards common mode signal rejection 4 26 configuration See also input configurations base I O address selection 2 3 bus interface 2 2 to 2 7 common questions about C 2 to C 3 DMA channel selection 2 3 to 2 4 interrupt channel selection PC AT 16 bit DMA channel assignment map table 2 7 PC AT I O address map table 2 4 to 2 5 PC AT interrupt assignment map table 2 6 Plug and Play systems 2 3 switchless data acquisition 2 3 connectors See I O connectors CONVERT signal signal routing 3 19 to 3 20 timing connections 4 39 to 4 40 customer communication xiv D 1 to D 2 D DACOOUT signal analog output connections 4 27 to 4 28 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 AT MIO AI E Series User Manual In
75. TE signal 4 47 GPCTRO_OUT signal 4 47 to 4 48 GPCTRO_SOURCE signal 4 46 GPCTRO_UP_DOWN signal 4 48 GPCTR1_GATE signal 4 49 to 4 50 GPCTR1_OUT signal 4 50 GPCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 GPCTRO_GATE signal 4 47 GPCTRO_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 8 waveform generation timing connections 4 47 to 4 48 GPCTRO_SOURCE signal 4 46 GPCTRO_UP_DOWN signal 4 48 GPCTR1_GATE signal 4 49 to 4 50 GPCTR1_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 AT MIO AI E Series User Manual 1 6 waveform generation timing connections 4 50 GPCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 ground referenced signal sources description 4 18 differential connections 4 21 single ended connections NRSE configuration 4 25 H hardware installation 2 1 to 2 2 hardware overview analog input 3 6 to 3 13 considerations for selecting input ranges 3 10 dither 3 11 to 3 12 input modes 3 6 to 3 7 input polarity and range 3 7 to 3 10 multiple channel scanning considerations 3 12 to 3 13 analog output 3 14 to 3 15 output polarity
76. V 0 8 V Input high voltage 2V 5V Input low current 320 uA Vin 0 V Input high current 10 pA Vin 5 V Output low voltage Io 24 mA 0 4 V Output high voltage oH 13 mA 4 35 V PA lt 0 7 gt PB lt 0 7 gt Level Min Max PEO TS partant AT MIO 16DE 10 only Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 60 uA Vin 0 V Input high current 10 uA Vin 5 V Output low voltage lot 2 5 mA 0 4 V Output high voltage oH 2 5 mA 3 9 V Handshaking AT MIO 16DE 10 only 00 3 wire AT MIO AI E Series User Manual A 16 National Instruments Corporation Timing 1 0 Triggers Bus Interface Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 POWe ON St le aore ne Input High Z Data transfers AT MIO 16E 10 0 ee Programmed I O AT MIO 16DE 10 seeen Interrupts programmed I O Number of channels ee 2 up down counter timers 1 frequency scaler Resolutions isci c ctessceussosssetena taste oes Counter timers oe eee 24 bits Frequency Scalers cccccceerreeee 4 bits Compatibility oe eee TTL CMOS Base clocks available Counter timers ccccceeeeeeeees 20 MHz 100 kHz Frequency scaler oo eee 10 MHz 100 kHz Base clock accuracy eeeeeeeeeeeeee 0 01 Max source frequency n 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mo
77. XE 10 analog input A 19 to A 21 amplifier characteristics A 20 dynamic characteristics A 21 input characteristics A 19 to A 20 stability A 21 transfer characteristics A 20 analog output AT MIO 16XE 10 only A 22 to A 23 dynamic characteristics A 23 output characteristics A 22 stability A 23 transfer characteristics A 22 voltage output A 22 bus interface A 25 digital I O A 23 environment A 25 physical A 25 power requirements A 25 timing I O A 24 triggers A 24 to A 25 analog trigger A 24 to A 25 digital trigger A 25 dynamic characteristics A 27 to A 28 input characteristics A 26 stability A 28 transfer characteristics A 27 analog output A 28 to A 29 dynamic characteristics A 29 output characteristics A 28 stability A 29 transfer characteristics A 28 to A 29 voltage output A 29 bus interface A 31 digital I O A 30 environment A 31 physical A 31 power requirement A 31 timing I O A 30 to A 31 triggers digital trigger A 31 RTSI A 31 stability analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 13 AT MIO 16XE 10 and AT AI 16XE 10 A 21 AT MIO 16XE 50 A 28 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 to A 8 AT MIO 16E 10 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 and AT AI 16XE 10 A 23 AT MIO 16XE 50 A 29 RTSI A 25 AT MIO 16XE 50 analog input A 26 to A 28 amplif
78. a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 12 bit board to settle within 0 012 120 ppm or 1 2 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle to within 0 0003 3 ppm or 1 80 LSB of the 4 V step It may take as long as 100 us for the circuitry to settle this much For a 16 bit board to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 us for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason you should keep source impedances under 1 KQ to perform high speed scanning Due to problems with settling times multiple channel scannin
79. acteristics A 4 to A 5 input characteristics A 1 to A 2 stability A 5 transfer characteristics A 3 AT MIO 16E 10 and AT MIO 16DE 10 amplifier characteristics A 12 dynamic characteristics A 12 to A 13 input characteristics A 11 to A 12 stability A 13 transfer characteristics A 12 AT MIO 16XE 10 and AT AI 16XE 10 amplifier characteristics A 20 dynamic characteristics A 21 input characteristics A 19 to A 20 stability A 21 transfer characteristics A 20 AT MIO 16XE 50 amplifier characteristics A 27 dynamic characteristics A 27 to A 28 input characteristics A 26 stability A 28 transfer characteristics A 27 analog output 3 14 to 3 15 common questions about C 3 to C 5 output polarity selection 3 14 to 3 15 reference selection 3 14 reglitch selection 3 15 signal connections 4 27 to 4 28 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 to A 7 dynamic characteristics A 7 output characteristics A 6 stability A 7 to A 8 transfer characteristics A 6 to A 7 voltage output A 7 AT MIO AI E Series User Manual 1 2 AT MIO 16E 10 and AT MIO 16DE 10 dynamic characteristics A 15 output characteristics A 13 to A 14 stability A 15 transfer characteristics A 14 voltage output A 14 to A 15 AT MIO 16XE 10 dynamic characteristics A 23 output characteristics A 22 stability A 23 transfer characteristics A 22 voltage output A 22 AT MIO 16XE 50 dynamic characteristics A 29 output c
80. and the NI DAQ documentation After you set up your hardware system use either the application software LabVIEW or LabWindows CVI or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure your hardware e Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the National Instruments Corporation xiii AT MIO AI E Series User Manual About This Manual relevant pieces of the system Consult these guides when you are making your connections e SCXI chassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions Related Documentation The following National Instruments document contains information you may find helpful e Application Note 025 Field Wiring and Noise Considerations for Analog Signals Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of thi
81. bers separated by an ellipsis represent a range of values associated with a bit port or signal name for example ACH lt 0 7 gt stands for ACHO through ACH7 Abbreviations acronyms metric prefixes mnemonics symbols and terms are listed in the Glossary at the end of this manual National Instruments Documentation The AT MIO AI E Series User Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows e Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints e Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI documentation sets
82. ble dither on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 This is because the resolution of the ADC is so fine that the ADC and the PGIA inherently produce almost 0 5 LSB rms of noise This is equivalent to having a dither circuit that is always enabled Multiple Channel Scanning Considerations AT MIO AI E Series User Manual All of the AT E Series boards can scan multiple channels at the same maximum rate as their single channel rate however you should pay careful attention to the settling times for each of the boards The settling time for most of the AT E Series boards is independent of the selected gain even at the maximum sampling rate The settling time for the high channel count and very high speed boards is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is 3 12 National Instruments Corporation Chapter 3 Hardware Overview constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the ATE Series boards When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply
83. d data transfer errors that can arise during DMA driven GPCTR buffered input operations When doing buffered transfers using GPCTR function calls with DMA you can call GPCTR_Watch to indicate dataTransfer C 6 National Instruments Corporation Appendix C Common Questions errors NI DAQ takes a snapshot of transfers and counts how many points have been transferred If all the points have been transferred and the first instance of this error occurs NI DAQ returns a gpctrDataTransfer Warning indicating that the error could be bogus If all the points have not been transferred NI DAQ returns the genuine error The error continues to be returned until the acquisition completes The above error occurs because NI DAQ disarms the counter from generating any more requests in the interrupt service routine Due to interrupt latencies it is possible that the counter may have generated some spurious requests which the DMA controller may not satisfy because it has already transferred the required number of points 25 What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ language interface LabWindows or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI
84. de Data transfers 2 0 ceeeeeeeeeereeeeeeeeeeeee DMA interrupts programmed I O DMA MmodeS ssieei rrine Single transfer Digital Trigger Compatibility 00 eee TTL RESPONSE sinen in ee teeta eaten Rising or falling edge Pulse Width sessccsigoceonssaestseuethetersesesesss 10 ns min RTSI Prig Ser HNe S vice ninin in hesetia cts 7 Type eeen i thine eg a Ee ta Slave National Instruments Corporation A 17 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Power Requirement Physical Environment AT MIO AI E Series User Manual F9 VDC ES Janan n cies el eaa 0 7 A Power available at I O connector 4 65 VDC to 5 25 VDC atl A Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in T O connector AT MIO 16E 10 ee 68 pin male SCSI II type AT MIO 16DE 10 ee 100 pin female 0 050 D type Operating temperature 0 to 55 C Storage temperature oe 55 to 150 C Relative humidity eee 5 to 90 noncondensing A 18 National Instruments Corporation AT MIO 16XE 10 and AT Al 16XE 10 Analog Input Input Characteristics Number of channels ET EE E 16 single ended or 8 differential software selectable Type of ADC crespir resserre Successive approximation Resolution cccccecceeecceeeeeeceeeeeeeeeaes 16 bits 1 in 65 536 Maximum sampling rate 100 kS s guaranteed Input signal ranges
85. dex DACIOUT signal grounded signal sources analog output connections 4 27 to 4 28 NRSE 4 25 AT MIO 16E 1 AT MIO 16E 2 and when to use 4 20 AT MIO 64E 3 table 4 8 digital I O AT MIO 16E 10 and AT MIO 16DE 10 common questions about C 5 to C 8 table 4 10 operation 3 19 AT MIO 16XE 10 and AT AI 16XE 10 signal connections 4 28 to 4 29 table 4 12 specifications AT MIO 16XE 50 table 4 14 AT MIO 16E 1 AT MIO 16E 2 description table 4 5 and AT MIO 64E 3 A 8 DAQ STC C 1 AT MIO 16E 10 and data acquisition timing AT MIO 16DE 10 A 15 to A 17 connections 4 32 to 4 42 AT MIO 16XE 10 and AIGATE signal 4 41 AT AI 16XE 10 A 23 CONVERT signal 4 39 to 4 40 AT MIO 16XE 50 A 30 EXTSTROBE signal 4 33 to 4 34 digital ports A B and C timing specifications SCANCLK signal 4 33 4 53 to 4 57 SISOURCE signal 4 41 to 4 42 mode input timing 4 55 STARTSCAN signal 4 37 to 4 39 mode output timing 4 56 TRIGI signal 4 34 to 4 35 mode 2 bidirectional timing 4 57 TRIG signal 4 36 Port C signal assignments table 4 53 DATA signal table 4 54 timing signals table 4 54 DGND signal digital trigger specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 AT MIO 16E 10 and table 4 10 AT MIO 16DE 10 A 17 AT MIO 16XE 10 and AT AI 16XE 10 AT MIO 16XE 10 and table 4 12 AT AI 16XE 10 A 25 AT MIO 16XE 50 table 4 14 AT MIO 16XE
86. dical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Table of Contents About This Manual Organization of This Maniial s c ss ssctsecvsessceuss vestonveitvaneeeessnesneeees snes sceanee sd eateveueeneteeseey xi Conventions Used in This Manual cccccccsssscesessecesseceeeseeceseseeecseecesssneecseaaeesseeenes xii National Instruments Documentation cccccccessecessececececeseececesseceseaeeceseeeseaeeesneaeess xiii Related Documentation serseri erer iateko i ire e e eria es xiv Customer Communication 20 ce ceeecessecessececesceceseccecesaeceseceecesueceseaueceseeceessuseeseaeeeneeaeess xiv Chapter 1 Introduction About the AT E Series eieren reee eere eei aa nee Ee EE iai rani 1 1 What You Need to Get Started ssenooseeeeeeseseeseeseeeeseresseeesreesetesseressrressresseeesseesssreese 1 2 Software Programming Choices oo eee eeseeseceseesecescesecesceeeseeeeeeeseeseecsassaecsessaeenees 1 3 LabVIEW and LabWindows CVI Application Software 0 eee eee 1 3 NI DAQ Driver Software cccccccssccees
87. dither to reduce noise You enable and disable the dither circuitry through software Figure 3 7 illustrates the effect of dither on signal acquisition Figure 3 7a shows a small 4 LSB sine wave acquired with dither off The quantization of the ADC is clearly visible Figure 3 7b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 7c the sine wave is acquired with dither on There is a considerable amount of noise visible But averaging about 50 such acquisitions as shown in Figure 3 7d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal National Instruments Corporation 3 11 AT MIO AI E Series User Manual Chapter 3 Hardware Overview 4 0 6 0 i 100 200 300 400 0 100 200 300 400 500 a Dither disabled no averaging Dither disabled average of 50 acquisitions LSBs 6 0 LSBs 6 0 4 0 4 0 2 0 2 0 0 0 4 0 0 lf 2 0 4 0 Z 4 0 6 0 6 0 0 100 200 300 400 0 100 200 300 400 500 c Dither enabled no averaging Dither enabled average of 50 acquisitions Figure 3 7 Dither You cannot disa
88. e ACH lt 0 15 gt Floating Signal Vs Source So Instrumentation Amplifier co Input Multiplexers g AISENSE Measured Voltage es AIGND I O Conne ctor Selected Channel in RSE Configuration Figure 4 8 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your AT E Series board in the NRSE input configuration The signal is then connected to the positive input of the AT E Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the AT E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of an AT E Series board were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage National Instruments Corporation 4 25 AT MIO AI E Series User Manual Chapter 4 Signal Connections Figure 4 9 shows how to connect a grounded signal source to an AT E Series board channel configured for NRSE mode
89. e You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup National Instruments Corporation 4 49 AT MIO AI E Series User Manual Chapter 4 Signal Connections Figure 4 35 shows the timing requirements for the GPCTR1_GATE signal Rising edge polarity Falling edge polarity tw 10ns minimum Figure 4 35 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 36 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle output on TC Figure 4 36 GPCTR1_OUT Signal Timing AT MIO AI E Series User Manual 4 50 National Instruments Corporation Chapter4 Signal Connections
90. e point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to your AT E Series board analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT E Series board assuming that the PC is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations AT MIO AI E Series User Manual You can configure
91. e Point Parkway Austin TX 78730 5039 Tel 512 794 0100 mportant inrormation Warranty The AT MIO AI E Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In t
92. e Type Description STB input Strobe Input A low signal on this handshaking line loads data into the input latch IBF output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This is an input acknowledge signal ACK input Acknowledge Input A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16DE 10 OBF output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port INTR output Interrupt Request This signal becomes high to request service during a data transfer The appropriate interrupt enable bits must be set to generate this signal and to allow it to interrupt your computer RD internal Read Signal This signal is the read signal generated by the host computer WR internal Write Signal This signal is the write signal generated by the host computer DATA input or output Data Lines at the Selected Port PA or PB This signal indicates when the data on the data lines at a selected port is or should be available AT MIO AI E Series User Manual 4 54 National Instruments Corporation Chapter4 Signal Connections Mode 1 Input Timing The following are the timing specifications for an input transfer in Mode 1
93. e actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 32 shows the timing requirements for the GPCTRO_GATE signal Rising edge polarity Falling edge polarity ty 10ns minimum Figure 4 32 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 33 shows the timing of the GPCTRO_OUT signal National Instruments Corporation 4 47 AT MIO AI E Series User Manual Chapter 4 Signal Connections GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle output on TC Figure 4 33 GPCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free
94. e base address Base 1 0 Address Selection The AT E Series boards can be configured to use base addresses in the range of 20 to FFEO hex Each AT E Series board occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3C0 3E0 hex This selection is software configured and does not require you to manually change any settings on the board DMA Channel Selection The AT E Series boards can achieve high transfer rates by using up to three 16 bit DMA channels You can use these DMA channels for data transfers with the analog input analog output and general purpose counter sections of the board The AT E Series boards can use only National Instruments Corporation 2 3 AT MIO AI E Series User Manual Chapter 2 Installation and Configuration AT MIO AI E Series User Manual 16 bit DMA channels which correspond to channels 5 6 and 7 in an ISA computer and channels 0 1 2 3 5 6 and 7 in an EISA computer These selections are all software configured and do not require you to manually change any settings on the board Interrupt Channel Selection The AT E Series boards can increase bus efficiency by using an interrupt channel You can use an interrupt channel for event notification without the use of polling techniques AT E Series boards can use interrupt channels 3 4 5 7 10 11 12 and 15 These selections are all software configured and do not require you
95. e eee ese eeeee 3 10 Dither disc ssdae tvs aited ee BO ei asd Meh ee ay 3 11 Multiple Channel Scanning Considerations 00 0 sees eeeeeeeceseeeeeeeeeeeeeeeeees 3 12 Analog Output sie cise ste eee ae eeen oa E Nusdeabes Gachect es tas EEEE E E EENE RNa a E ade nets 3 14 Analog Output Reference Selection eseseeseseeesesseeersererrererrerssersserrrsreerrreeene 3 14 Analog Output Polarity Selection eee ceecesecneceeeeeceeeeeeeeeeeeeeaeeees 3 14 Analog Output Reglitch Selection oo ees ceeceseceeceseeeeceseeeeeeeeeeeeeaeeees 3 15 Analog Trigger ssccejgheiighdl saws aie Nujea E E lee E A eae Se heehee eek 3 15 Digital V O EEE A EEEE E Mask EE depot aude teed teeters each neitrcogth utes eee ade 3 19 Timing Signal Routing oo eee cee e E E E i a i a AE e EE E RE ER 3 19 Programmable Function Inputs ssssesesesseseeeesesrersseeersressrreerreserrsserresresrereeee 3 20 Board and RTSI Clocks esenessenesseerereesereeeresessesersreevseererererversrsrersrensierereesere 3 21 RUST TES SOLS eos ERRAN ESE EEEE ENE V OE ET EEEE 3 21 Chapter 4 Signal Connections VO Connector ani e a a eee E E E S ee 4 1 I O Connector Signal Descriptions sesseseeeesseressseeersreesrersrrersserrsseerrsreerereeene 4 5 Analog Input Signal Connections oo eee eeeeecseessecreeaeceecaeceecseeseeeseeeseseseeseaeeees 4 16 Types OF Signal SOULCES sosoroh es eorr eth peste Adee ed seca a en ek eee eae 4 18 Floating Signal SOULCES 0 eee eee e eeii oE is 4
96. e monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your AT E Series board e Separate AT E Series board signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the AT E Series board signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments 4 58 National Instruments Corporation Chapter Calibration This chapter discusses the calibration procedures for your AT E Series board If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the ATE Series boards these adjustments take the form of writing values to onboard calibration DACs Cal
97. ee eeeceeeeeecneensecseenneenees 4 46 Figure 4 32 GPCTRO_GATE Signal Timing in Edge Detection Mode 00 4 47 Figure 4 33 GPCTRO_OUT Signal Timing 00 cece eeeeceeeeeceeeaecseenaeenees 4 48 Figure 4 34 GPCTR1_SOURCE Signal Timing o ee eeeeeecseeseecneenseceesaeenees 4 49 Figure 4 35 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 50 Figure 4 36 GPCTR1_OUT Signal Timing 0 cece eeeecaeeeeceeaeceesaeenees 4 50 Figure 4 37 GPCTR Timing Summary 0 0 cece eeceeeeeeeceeeeeecaeesaecaeesaecaeesaeenees 4 51 Figure 4 38 Mode 1 Input Timing sssrin eneinio ian a E 4 55 Figure 4 39 Mode 1 Output Timing 000 eee ee cee eeeeeeeeeeeeneeseecaeesaecaecaecneesaeenees 4 56 Figure 4 40 Mode 2 Bidirectional Timing 0 000 000 eee eee ecceeeeeeceeeeeecaeeeaecoeesaeceeaeenees 4 57 National Instruments Corporation ix AT MIO AI E Series User Manual Table of Contents Figure B 1 68 Pin MIO Connector Pin Assignment 2 0 0 0 ceceseeeeseeeseeeeeeeeeseeees B 2 Figure B 2 68 Pin DIO Connector Pin Assignments 2 0 0 0 ce eeeeeeeeeeeceeeeeeeeseeees B 3 Figure B 3 68 Pin Extended Analog Input Connector Pin Assignments B 4 Figure B 4 50 Pin MIO Connector Pin Assignment 20 00 0000 ce ceseeceeseeeeceeeeeeeeeeeees B 5 Figure B 5 50 Pin DIO Connector Pin Assignments 2 0 0 0 ce eseeceseeeeeeeeeeeeeneeees B 6 Figure B 6 50 Pin Extended Analog Input Connector Pin Assignments B 7 Tables
98. eform Generation Timing Connections AT MIO AI E Series User Manual The analog group defined for your AT E Series board is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup 4 42 National Instruments Corporation Chapter 4 Signal Connections Figures 4 26 and 4 27 show the input and output timing requirements for the WFTRIG signal Rising edge polarity Falling edge polarity tw 50 100 ns Figure 4 27 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS5 UPDATE pin As an input the UPDATE signal is configured in the edge detecti
99. eini 820 Q min Input bias current 0 0 0 eee 10 nA Input offset current eee 20 nA CMRR DC to 60 Hz Gim E Gs ere er dont aeee i ees 80 dB Gain 2 arenie ese ses 86 dB Gain JO erisso luotaa 100 dB G m 100i u arets 120 dB Dynamic Characteristics Bandwidth Gam 15 2 aen fei hhc io eaan 63 kHz Gain LO zpena e E ae 57 kHz Gain J00 mecra 33 kHz National Instruments Corporation A 27 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Analog Output AT MIO AI E Series User Manual Settling time for full scale step 50 us max to 1 LSB all gains and ranges System noise including quantization noise Gain 1 2 10 cece eeee 0 5 LSB rms Gain 100 eee eens 0 8 LSB rms bipolar 1 4 LSB rms unipolar Crosstalk orenen ii 85 dB max DC to 20 kHz Stability Recommended warm up time 15 min Offset temperature coefficient PreS alte ieee ewe 1 uv C Postg AIT eneen ices anpe 12 uV C Gain temperature coefficient 5 ppm C Onboard calibration reference Ceyo i ea E 5 000 V 2 0 mV actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 2 0 0 0 15 ppm 1 000 h Output Characteristics Number of channels ce eeeeeeeeeeeee 2 voltage ReSOlution ccccc cece ceeeseeecseeeeseeceees 12 bits 1 in 4 096 Max update rate 000 0 eee cece eee 20 kS s Typeof DAC orner cies Do
100. el Printer Adapter 0 3C0 to 3CF Enhanced Graphics Adapter VGA 3D0 to 3DF Color Graphics Monitor Adapter VGA 3E0 to 3EF 3F0 to 3F7 Diskette Controller 3F8 to 3FF Serial Port 1 COM1 A79 Reserved for Plug and Play operation National Instruments Corporation 2 5 AT MIO AI E Series User Manual Chapter 2 Installation and Configuration Table 2 2 PC AT Interrupt Assignment Map IRQ Device 15 Available 14 Fixed Disk Controller 13 Coprocessor 12 AT DIO 32F default 11 AT DIO 32F default 10 AT MIO 16 default 9 PC Network default PC Network Alternate default 8 Real Time Clock 7 Parallel Port 1 LPT1 6 Diskette Drive Controller Fixed Disk and Diskette Drive Controller 5 Parallel Port 2 LPT2 PC DIO 24 default Lab PC PC default 4 Serial Port 1 COM1 BSC BSC Alternate 3 Serial Port 2 COM2 BSC BSC Alternate Cluster primary PC Network PC Network Alternate WD EtherCard default 3Com EtherLink default 2 IRQ 8 15 Chain from interrupt controller 2 1 Keyboard Controller Output Buffer Full 0 Timer Channel 0 Output AT MIO AI E Series User Manual 2 6 National Instruments Corporation Chapter 2 Installation and Configuration Table 2 3 PC AT 16 bit DMA Channel Assignment Map Channel Device 7 AT MIO 16 series default 6 AT MIO 16 series default AT DIO 32F default 5 AT
101. en 4 52 Timing Specifications for Digital I O Ports A B and C oo eeeeeeeee 4 53 Mode 1 Input Timing oe eee eeeeeeeeeceeeeeseeseecaecsaecaeenaeeaees 4 55 Mode 1 Output Timing ooo eere e e s S E RR E ES 4 56 Mode 2 Bidirectional Timing eseeseesesseeeeesseereereseersseerrsreresreserrrereees 4 57 Field Wiring Considerations 0 0 rones esee es aese OE on E Nenen eE ee Enotne AERP oee RESINE O RSE Nee 4 58 Chapter 5 Calibration Loading Calibration Constants 0 ccc ceeeseeesceseeeeceeceseceseeseecaeseaecaeesaecaaesaecaeesaeenees 5 1 Seli Cali brat On 312 eenn a E E E E SAE EA i 5 2 External Calibration espesie ae or eee eE O R ETE RE TEE Ee 5 2 Other Consideratons vistri r e e ee tesa E aeaee E Ea E EE E EEES SS 5 3 National Instruments Corporation vij AT MIO AI E Series User Manual Table of Contents Appendix A Specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 oo cceeceseneeeeeeeeneeseeeeaeens A 1 AT MIO 16E 10 and AT MIO 16DE 10 ssssesesseseesseisesssrsesreresrrerrersrsrersseseseereserreree A 11 AT MIO 16XE 10 and AT AI 16XE 10 esesseseeseeeeeseisrssrsesrersssrerrersrsreessesesrsteserrerse A 19 PET MIO TOXES E E EE AE copies E EEE E EE PAE E E A 26 Appendix B Optional Cable Connector Descriptions Appendix C Common Questions Appendix D Customer Communication Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware o cccccccccccss
102. en configured as an analog trigger signal or disabled 35 V powered off AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MI0 16E 2 and AT MIO 64E 3 Digital Trigger Compatibility sessies TTL RESPONSE sisciveecisleeek ioar Lec deck ocean Rising or falling edge Pulse width sesype repasses 10 ns min RTSI Trigger nessi aa aa 7 Bus Interface Ly Pe e an sai EEE Slave Power Requirement 5 VDCES J e ee 1 0 A Power available at I O connector 4 65 VDC to 5 25 VDC atl A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in T O connector AT MIO 16E 1 AT MIO 16E 2 000 eee 68 pin male SCSI II type AT MIO 64E 3 eeen 100 pin female 0 050 D type Environment Operating temperature 0 to 55 C Storage temperature oe 55 to 150 C Relative humidity ee 5 to 90 noncondensing AT MIO AI E Series User Manual A 10 National Instruments Corporation AT MIO 16E 10 and AT MIO 16DE 10 Analog Input Input Characteristics Number of channels ee 16 single ended or 8 differential software selectable Type OF ADE orps erens resene Successive approximation ReSOlUtION ccc cceecceeecceeeceeeseeeeeeenes 12 bits 1 in 4 096 Max sampling rate eee 100 kS s guaranteed Input signal ranges Board Gain Board Range Software Software Selectable Selectable 5 V 0 10 V 0 5 10 V 1
103. ends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results you should match the input range as closely as possible to the expected range of the input signal For example if you are certain the input signal will not be negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero inaccurate readings will occur if you use unipolar input polarity 3 10 National Instruments Corporation Dither Chapter 3 Hardware Overview When you enable dither you add approximately 0 5 LSB rms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your AT E Series board as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the board calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the
104. ent 2 Channe aiao 300 625 kS s system dependent Type of DAC 2cn eet line Double buffered multiplying FIFO buffer size eects 2 048 samples Data transfers ccccceeccecceeeseeeeeees DMA interrupts programmed I O DMA modes eee eeeeeeceeeeeeneneees Single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration 0 00 0 3 LSB typ 0 5 LSB max Before calibration ccceeeee 4 LSB max DNL After calibration 0 00 eee 0 3 LSB typ 1 0 LSB max Before calibration c ceeee 3 LSB max Monotonicity s es 12 bits guaranteed after calibration Offset error After calibration c cece 1 0 mV max Before calibration 008 200 mV max Gain error relative to internal reference After calibration 0 00 eee 0 01 of output max Before calibration s s s 0 5 of output max A 6 National Instruments Corporation Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Gain error relative to external reference Voltage Output Rane cissvess Meccnssts baton me ooass satan eds eheens Output coupling Output impedance eee Current driv cenh n a eels Protection Power on state eseeeserereererrrees External reference input Rin E narine t e Overvoltage protection Input impedance Bandwidth 3 dB Dynamic Characteristics Settling time for full scale step
105. es all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Australia Austria Belgium Canada Ontario Canada Quebec Denmark Finland France Germany Hong Kong Italy Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan U K Telephone 03 9 879 9422 0662 45 79 90 0 02 757 00 20 519 622 9310 514 694 8521 45 76 26 00 90 527 2321 1 48 14 24 24 089 741 31 30 2645 3186 02 413091 03 5472 2970 02 596 7456 95 800 010 0793 0348 433466 32 84 84 00 2265886 91 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 LabVIEW lv support natinst com HiQ hiq support natinst com VISA visa support natinst com i i 03 9 879 9179 0662 45 79 90 19 02 757 03 11 514 694 4399 45 76 26 02 90 502 2930 1 48 14 24 14 089 714 60 35 2686 8505 02 41309215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 730 43 70 056 200 51 55 02 737 4644 01635 523154 Click here to comment on this document via the National Instruments website at Technical Support Form http www natinst com documentation daq Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration
106. es the RTSI bus for interconnecting timing signals between boards and the Programmable Function Input PFI pins on the I O connector for connecting to external circuitry These connections are designed to enable the AT E Series board to both control and be controlled by other boards and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 14 National Instruments Corporation 3 19 AT MIO AI E Series User Manual Chapter 3 Hardware Overview Sample Interval Counter TC GPCTRO_OUT RTSI Trigger lt 0 6 gt gt CONVERT PFI lt 0 9 gt Figure 3 14 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs AT MIO AI E Series User Manual The 10 PFIs are connected to the signal routin
107. figured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup Figure 4 31 shows the timing requirements for the GPCTRO_SOURCE signal tp 50ns minimum ty 23 ns minimum Figure 4 31 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source 4 46 National Instruments Corporation Chapter4 Signal Connections GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects th
108. for general use GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is being externally generated by another PFI This output is set to tri state at startup AT MIO AI E Series User Manual 4 48 National Instruments Corporation Chapter 4 Signal Connections Figure 4 34 shows the timing requirements for the GPCTR1_SOURCE signal tp 50ns minimum ty 23 ns minimum Figure 4 34 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edg
109. g is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on National Instruments Corporation 3 13 AT MIO AI E Series User Manual Chapter 3 Hardware Overview Analog Output AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 The AT E Series boards supply two channels of analog output voltage at the I O connector You can select the reference and range for the analog output circuitry through software The reference can be either internal or external whereas the range can be either bipolar or unipolar AT MIO 16XE 50 The AT MIO 16XE 50 supplies two channels of analog output voltage at the I O connector The range is fixed at bipolar 10 V AT MIO 16XE 10 The AT MIO 16XE 10 supplies two channels of analog output voltage at the I O connector The range is software selectable between unipolar 0 to 10 V and bipolar 10 V Analog Output Reference Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 only You can connect each D A converter DAC to the AT E Series board internal reference of 10 V or to the external reference signal connected to the external refe
110. g multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications 3 20 National Instruments Corporation Chapter 3 Hardware Overview You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS5 UPDATE pin Board and RTSI Clocks Many functions performed by the AT E Series boards require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector An AT E Series board can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the board to use the internal timebase you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the board as the primary frequency source The default configuration at startup is to use
111. gain error adjusted to 0 at gain 1 Gan lesniho ti 200 ppm of reading Amplifier Characteristics Input impedance Normal powered on s es 100 GQ in parallel with 100 pF Powered off oeer 820 Q min Overload oy nN 820 Q min Input bias current 0 eee eeeeeee 1 nA Input offset current ee eeeeeeeeeeeeeee 2 nA CMRR DC to 60 Hz Gain S Jien ane 92 dB Gan S Zieda ee e e ERa 97 dB Gain S Sesle oa etek ies 101 dB Gall 10k aa 104 dB G nn 2O harana 105 dB Gall 50ra isiin nea 105 dB Gain 100i nnise hike 105 dB A 20 National Instruments Corporation Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Dynamic Characteristics Bandwidth ALP aINS cca neisse r 255 kHz Settling time for full scale step all gains and ranges To 40 5 LSB rieira 40 us typ To IL LSB einer 20 us typ To A LSB cciccctsuesseveddbassesesceacteeas 10 us typ System noise including quantization noise G m 12S 1O ara 0 6 LSB rms bipolar 0 8 LSB rms unipolar Gain 20 ieke 0 7 LSB rms bipolar 1 1 LSB rms unipolar Gain D0 seis ea 1 1 LSB rms bipolar 2 0 LSB rms unipolar Gain 100 ve cscs tees 2 0 LSB rms bipolar 3 8 LSB rms unipolar Dynamic range o0 eee eee eres 91 7 dB full scale input with gain to 10 Crosstalk eien e a ann 70 dB max DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient PLES AIMS ionaire raiot eis 5 uV C POSE AIM siri eesse eier 120 uV
112. gital I O Connections Figure 4 11 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure National Instruments Corporation 4 29 AT MIO AI E Series User Manual Chapter 4 Signal Connections Power Connections Two pins on the I 0 connector supply 5 V from the PC power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry e Powerrating 4 65 VDC to 5 25 VDC at 1 A combined total for both pins Warning Under no circumstances should you connect these 5 V power pins directly XJ to analog or digital ground or to any other voltage source on the AT E Series board or any other device Doing so can damage the AT E Series board and the PC National Instruments is NoT liable for damages resulting from such a connection Timing Connections Warning Exceeding the maximum input voltage ratings which are listed in J Tables 4 1 through 4 4 can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting from such signal connectio
113. h RTSI Trigger Lines Bus Interface Power Requirement 5 VDC 45 Power available at I O connector Physical Dimensions not including connectors I O connector Environment Operating temperature Storage temperature Relative humidity National Instruments Corporation 10 ns edge detect mode DMA interrupts programmed I O Single transfer TTL Rising or falling edge 10 ns min Slave 0 75 A 4 65 VDC to 5 25 VDC atl A 33 8 by 9 9 cm 13 3 by 3 9 in 68 pin male SCSI II type 0 to 55 C 55 to 150 C 5 to 90 noncondensing AT MIO AI E Series User Manual Appendix Optional Cable Connector Descriptions This appendix describes the connectors on the optional cables for the ATE Series boards Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 or R6868 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 68 pin connectors available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 National Instruments Corporation B 1 AT MIO AI E Series User Manual Appendix B Optional Cable Connector Descriptions ACH8 68 ACHO ACH1 67 AIGND AIGND 66 ACH9 ACH10 65 ACH2 ACH3 64 AIGND AIGND 63 ACH11 ACH4 62 AISENSE AIGND 61 ACH12 ACH13 60 ACH5 ACH6 59 AIGND AIGND 58 ACH
114. haracteristics A 28 stability A 29 transfer characteristics A 28 to A 29 voltage output A 29 analog trigger 3 15 to 3 18 block diagram 3 16 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 9 to A 10 specifications AT MIO 16XE IO and AT AI 16XE 10 A 24 to A 25 AOGND signal analog output connections 4 27 to 4 28 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 AT E series boards See also hardware overview common questions about C 1 to C 8 features 1 1 to 1 2 getting started 1 2 optional equipment 1 5 National Instruments Corporation software programming choices LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 5 register level programming 1 5 unpacking 1 7 base I O address selection 2 3 bipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 to 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 9 to 3 10 mixing bipolar and unipolar channels note 3 9 bipolar output 3 14 3 15 block diagrams AT AI 16XE 10 3 5 AT MIO 16E 1 and AT MIO 16E 2 3 1 AT MIO 16E 10 and AT MIO 16DE 10 3 3 AT MIO 16XE 10 3 4 AT MIO 16XE 50 3 6 AT MIO 64E 3 3 2 board configuration See configuration bulletin board support D 1 bus interface specifications AT MIO 16E 1 A
115. he PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source National Instruments Corporation 4 23 AT MIO AI E Series User Manual Chapter 4 Signal Connections Single Ended Connection Considerations A single ended connection is one in which the AT E Series board analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels are available up to 64 channels on the AT MIO 64E 3 You can use single ended input connections for any input signal that meets the following conditions e The input signal is high level greater than 1 V e The leads con
116. he event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National
117. ibbon cable With the SH6850 shielded cable or R6850 ribbon cable you can connect your board to 50 pin signal conditioning modules and terminal blocks The I O connector for the AT MIO 64E 3 and AT MIO 16DE 10 has 100 pins that you can connect to 100 pin accessories with the SH100100 shielded cable With the SH1006868 shielded cable you can connect your board to 68 pin accessories and with the R1005050 ribbon cable you can connect your board to 50 pin accessories 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Figure 4 2 shows the pin assignments for the 100 pin I O connector on the AT MIO 64E 3 Figure 4 3 shows the pin assignments for the 100 pin I O connector on the AT MIO 16DE 10 Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connectors A signal description follows the connector pinouts Warning Connections that exceed any of the maximum ratings of input or output J signals on the AT E Series boards can damage the AT E Series board and the PC Maximum input ratings for each signal are given in Tables 4 1 through 4 4 in the Protection column National Instruments is NoT liable for any damages resulting from such signal connections National Instruments Corporation 4 1 AT MIO AI E Series User Manual Chapter 4 Signal Connections ACH8 68
118. ibration gain 1 0 02 of reading max Before calibration ee 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 10 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GQ in parallel with 100 pF Powered off aeee 820 Q min Overload ieee ee ro siot tussss 820 Q min Input bias current 0 0 0 eee 200 pA Input offset current eee 100 pA CMRR DC to 60 Hz Gam O Soe sosie 95 dB Gam Tni hi 100 dB Galina 2o iene 106 dB National Instruments Corporation A 3 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MI0 16E 2 and AT MIO 64E 3 Dynamic Characteristics Bandwidth eee Small signal 3dB Large signal 1 THD AT MIO 16E 1 1 6 MHz 1 MHz AT MIO 16E 2 AT MIO 64E 3 1 MHz 300 kHz Settling time for Gain Accuracy full scale step 0 012 0 024 0 098 0 5 LSB 1 LSB 4 LSB AT MIO 16E 1 0 5 2 us typ 1 5 us typ 1 5 us typ 3 us max 2 Us max 2 Us max 1 1 5 us typ 1 3 us typ 1 1 us typ 2 us max 1 5 us max 1 3 us max 2 to 50 2 us typ 1 5 us typ 0 9 us typ 3 us max 2 us max 1 us max 100 2 us typ 1 5 us typ 1 us typ 3 us max 2 us max 1 5 us max AT MIO 16E 2 All 2 us typ 1 9 us typ 1 8 us typ 4 us max 2 us max 2 us max AT MIO 64E 3 All 3 us typ 2ustyp 1 8 ps typ 5 us max 3 us max 2 us max AT
119. ier characteristics A 27 STARTSCAN signal timing connections 4 37 to 4 39 STB signal table 4 54 switchless data acquisition 2 3 AT MIO AI E Series User Manual 1 12 National Instruments Corporation T technical support D 1 to D 2 theory of operation See hardware overview ACH lt 0 63 gt signal description table 4 5 timebases board and RTSI clocks 3 21 timing connections 4 30 to 4 57 common questions about C 5 to C 8 data acquisition timing connections 4 32 to 4 42 AIGATE signal 4 41 CONVERT signal 4 39 to 4 40 EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 SISOURCE signal 4 41 to 4 42 STARTSCAN signal 4 37 to 4 39 TRIGI signal 4 34 to 4 35 TRIG signal 4 36 digital ports A B and C 4 53 to 4 57 mode input timing 4 55 mode 1 output timing 4 56 mode 2 bidirectional timing 4 57 Port C signal assignments table 4 53 timing signals table 4 54 general purpose timing signal connections 4 46 to 4 57 FREQ_OUT signal 4 52 GPCTRO_GATE signal 4 47 GPCTRO_OUT signal 4 47 to 4 48 GPCTRO_SOURCE signal 4 46 GPCTRO_UP_DOWN signal 4 48 GPCTR1_GATE signal 4 49 to 4 50 GPCTR1_OUT signal 4 50 GPCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 programmable function input connections 4 31 to 4 32 waveform generation timing connections 4 42 to 4 45 UNISOURCE signal 4 45 National Instruments Corporation Index UPDATE signal 4 43 to 4 44 WFTRIG signal 4 4
120. iggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 19 and 4 20 show the input and output timing requirements for the TRIG2 signal Rising edge polarity Falling edge polarity ty 10ns minimum Figure 4 19 TRIG2 Input Signal Timing AT MIO AI E Series User Manual 4 36 National Instruments Corporation Chapter4 Signal Connections ty 50 100 ns Figure 4 20 TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 13 and 4 14 for the relationship of STARTSCAN to the data acquisition sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter is started if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse
121. in 1 0 05 of reading max Amplifier Characteristics Input impedance Normal powered on 0 100 GQ in parallel with 50 pF Powered off eccere 3 kQ min OVetlO ddl ics coves cescsssecseeerevereens seve 3 kQ min Input bias current 200 pA Input offset current ee 100 pA CMRR all input ranges 90 dB DC to 60 Hz Dynamic Characteristics Bandwidth Small signal 3 dB 0 200 kHz Large signal 1 THD 300 kHz Settling time for full scale step 10 us max to 0 5 LSB accuracy A 12 National Instruments Corporation Analog Output Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 System noise Gain Noise not including quantization 0 5 to 10 0 07 LSB rms 20 0 12 LSB rms 50 0 25 LSB rms 100 0 5 LSB rms dither on any gain 0 5 LSB rms Crosstalk ariyana ear 80 dB DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Preg alinei wa vensie se 15 pV C POStSAIN ccsiistsissracscsessiens Meson 240 uV C Gain temperature coefficient 20 ppm C Onboard calibration reference Level orriren 5 000 V 42 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 0 15 ppm 1 000 h Output Characteristics Number of channels eee 2 voltage ReSOlUution
122. ing 1 0 Number of channels 0 00 eee 2 up down counter timers 1 frequency scaler Resolution Counter timers 0 eee 24 bits Frequency Scalers ccceeeereeee 4 bits Compatibility 0 0 0 ee eee TTL CMOS AT MIO AI E Series User Manual A 8 National Instruments Corporation Triggers Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Base clocks available Counter timers 0 Frequency scalers 000 Base clock accuracy ceeeeeeees Max source frequency 66 Min source pulse duration Min gate pulse duration Data transfers c ccceccceeeeeeeees DMA modes ccecceeceeeeeeeeees Analog Trigger S r esinen era esa assed eee oes TOV secon toegs ose vote A E Resolution cesit reiki TIYStEPESIS ee pro eni aE Bandwidth 3 dB ee External input PFIO TRIG1 Tmpedance cceeeseeesereseeeeeee COUPLING roria une Protection mannanna National Instruments Corporation A 9 20 MHz 100 kHz 10 MHz 100 kHz as 0 01 20 MHz 10 ns in edge detect mode 10 ns in edge detect mode DMA interrupts programmed I O Single transfer ACH lt 0 63 gt PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 8 bits 1 in 256 Programmable 1 5 MHz internal 7 MHz external 10 KQ DC 0 5 to Vcc 0 5 V when configured as a digital signal 35 V wh
123. isse inae a anaa Pulse width 2 0322 sensei RTSI Trigger Line Sius inete itses Bus Interface Power Requirement tE VDE E5 yu enai Power available at I O connector Physical Dimensions not including connectors I O connector 0 c cece ceecceeeceeeceeeeeeees Environment Operating temperature Storage temperature ee Relative humidity cceeeeeeeeeereeee National Instruments Corporation A 25 0 5 to Vec 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off 1 of full scale range TTL Rising or falling edge 10 ns min Slave 1L2A 4 65 VDC to 5 25 VDC atl A 33 8 by 9 9 cm 13 3 by 3 9 in 68 pin male SCSI II type 0 to 55 C 55 to 150 C 5 to 90 noncondensing AT MIO AI E Series User Manual AT MIO 16XE 50 Analog Input Input Characteristics Number of channels e ee 16 single ended or 8 differential software selectable Type OF ADE ccceseetesiccyetseretereeeseeeegseess Successive approximation Resolution cccccceeeecceeeeeeceeeeeeeeeaes 16 bits 1 in 65 536 Maximum sampling rate 20 kS s guaranteed Input signal ranges Board Gain Board Range Software Software Selectable Selectable Bipolar Unipolar 1 10 V 0tol0V 2 5 V O0to5V 10 1V Otol V 100 0 1 V 0to0 1 V Input coupling eee eeees DC Maxim
124. ked questions and their answers relating to usage and special features of your AT E Series board e Appendix D Customer Communication contains forms you can use to request help from National Instruments or to comment on our products e The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations metric prefixes mnemonics and symbols e The Index alphabetically lists topics covered in this manual including the page where you can find the topic Conventions Used in This Manual bold bold italic italic NI DAQ PC SCXI AT MIO AI E Series User Manual The following conventions are used in this manual Bold text denotes parameters Bold italic text denotes a note caution or warning Italic text denotes emphasis on a specific board in the AT E Series or on other important information a cross reference or an introduction to a key concept NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted PC refers to the PC AT series computers SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards xii National Instruments Corporation About This Manual The indicates that the text following it applies only to specific AT E Series boards lt gt Angle brackets containing num
125. llup AO Analog Output DO Digital Output Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 kQ and 100 kQ National Instruments Corporation 4 15 AT MIO AI E Series User Manual Chapter 4 Signal Connections Analog Input Signal Connections e AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 The analog input signals are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are tied to the 16 analog input channels of your AT E Series board In single ended mode signals connected to ACH lt 0 15 gt are routed to the positive input of the board PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA AT MIO 64E 3 The analog input signals are ACH lt 0 63 gt AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 analog input channels of the AT MIO 64E 3 In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the AT MIO 64E 3 PGIA In differential mode signals connected to ACH lt 0 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 24 31 40 47 56 63 gt are routed to the negative input of the PGIA Warning Exceeding the
126. m in Figure 4 6 National Instruments Corporation 4 21 AT MIO AI E Series User Manual Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 7 shows how to connect a floating signal source to an AT E Series board channel configured in DIFF input mode ACH lt 0 7 gt OO Bias s resistors see text So Floatin Sicnal V Instrumentation Source Pe 2 Amplifier 7 lo ACH lt 8 15 gt Measured Voltage So So So Input Multiplexers Paths Bias Current Vv Return o eo AISENSE Pa L O Connector Selected Channel in DIFF Configuration Figure 4 7 Differential Input Connections for Nonreferenced Signals Figure 4 7 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without AT MIO AI E Series User Manual 4 22 National Instruments Corporation Chapter 4 Signal Connections a
127. med analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 National Instruments Corporation AT MIO AI E Series User Manual Chapter 4 Signal Connections Signal Name Reference Direction Description Continued PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output Table 4 1 shows the I O signal summary for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Table 4 1 1 0 Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Signal Name Drive I
128. mpedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns ACH lt 0 63 gt AI 100 GQ 25 15 200 pA in parallel with 00 pF AISENSE AISENSE2 AI 100 GQ 25 15 200 pA in parallel with 100 pF AIGND AO DACOOUT AO 0 1 0 Short circuit 5 at 10 5 at 10 20 to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 20 to ground V us EXTREF Al 10 KQ 25 15 AOGND AO DGND DO VCC DO 0 1Q Short circuit 1A to ground AT MIO AI E Series User Manual 4 8 National Instruments Corporation Chapter 4 Signal Connections Table 4 1 1 0 Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Continued Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24 at 1 1 50 KQ pu 0 4 SCANCLK DO 3 5 at Vec 0 4 5 at 0 4 15 50 kQ pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 KQ pu PFIO TRIG1 ADIO 10kQ Vec 0 5 435 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu PFI1 TRIG2 DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kQ pu PFI4 GPCTR
129. nal from the output of the PGIA as 3 15 AT MIO AI E Series User Manual Chapter 3 Hardware Overview shown in Figure 3 8 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and 10 V in 4 9 mV steps for the AT MIO 16XE 10 and AT AI 16XE 10 The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and divided by 4 096 for the AT MIO 16XE 10 and AT AI 16XE 10 Note The PFIO TRIGI pin is a high impedance input Therefore it is susceptible to cross talk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 10 kQ source impedance if you plan to enable this input via software Analog Input Channels PFIO TRIG1 AT MIO AI E Series User Manual Analog Trigger DAQ STC Circuit Figure 3 8 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 9 through 3 13 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused 3 16 National Instruments C
130. nd for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 or 800 327 3077 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 1 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FTP Support To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation D 1 AT MIO AI E Series User Manual FaxBack Support Click here to comment on this document via the National Instruments website at http Awww natinst com documentation daq FaxBack is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access FaxBack from a touch tone telephone at 512 418 1111 You can submit technical support questions to the appropriate applications engineering team through e mail at the Internet addresses listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions GPIB gpib support natinst com DAQ daq support natinst com VXI vxi support natinst com LabWindows lw support natinst com Fax and Telephone Support National Instruments has branch offic
131. necting the signal to the AT E Series board are less than 10 ft 3 m e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the AT E Series board channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT E Series board provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT E Series board should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors AT MIO AI E Series User Manual 4 24 National Instruments Corporation Chapter 4 Signal Connections Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 8 shows how to connect a floating signal source to an AT E Series board channel configured for RSE mod
132. ng CL One of the following boards AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 L AT MIOSAI E Series User Manual Li One of the following software packages and documentation NI DAQ for PC compatibles LabVIEW LabWindows CVI L Your computer AT MIO AI E Series User Manual 1 2 National Instruments Corporation Chapter 1 Introduction Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use LabVIEW LabWindows CVI NI DAQ or register level programming LabVIEW and LabWindows CVI Application Software LabVIEW and LabWindows CVI are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows CVI enhances traditional programming languages Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of
133. ng sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold AT MIO AI E Series User Manual 3 18 National Instruments Corporation Digital 1 0 Chapter 3 Hardware Overview Timing Signal The AT E Series boards contain eight lines of digital I O for general purpose use You can individually configure each line through software for either input or output The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking capabilities At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines Routing The DAQ STC provides a very flexible interface for connecting timing signals to other boards or external circuitry Your AT E Series board us
134. ning properly 12 have several DAQ boards that use more total interrupt and DMA 13 channels than I have available in my PC What should I do Using the proper configuration utility WOAQCONF or DAQCONF you can disable interrupt and DMA channels for the board you are using You may be more limited in the functionality of the board usually regarding high speed acquisition but you should at least be able to use basic functionality for all boards in the system How can I select an AT E Series board as my device type in DAQCONF or WDAQCONF First make sure your board is plugged into your computer The DAQCONF and WDAQCONE utilities scan your system for any ATE Series devices If no AT E Series boards are found the AT E Series device types are not given as choices Analog Input and Output 14 National Instruments Corporation Pm using my board in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the board reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections
135. ns AT MIO AI E Series User Manual All external control over the timing of your AT E Series board is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many data acquisition waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any data acquisition waveform generation and general purpose timing signals The data acquisition signals are explained in the Data Acquisition Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 12 which shows how to connect an 4 30 National Instruments Corporation Chapter 4 Signal Connections external TRIGI source and an external CONVERT source to two of the AT E Series board PFI pins PFIO TRIG1 _ _ PFI2 CONVERT CONVERT Source
136. ns table 4 5 to 4 8 input configurations 4 18 common mode signal rejection 4 26 differential connections DIFF input configuration 4 20 floating signal sources 4 22 to 4 23 ground referenced signal sources 4 21 nonreferenced signal sources 4 22 to 4 23 single ended connections 4 24 to 4 26 floating signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 power connections 4 30 timing connections 4 30 to 4 57 data acquisition timing connections 4 32 to 4 42 AIGATE signal 4 41 National Instruments Corporation Index CONVERT signal software 4 39 to 4 40 programming choices EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 5 SISOURCE signal 4 41 to 4 42 register level programming 1 5 STARTSCAN signal specifications 4 37 to 4 39 AT MIO 16E 1 AT MIO 16E 2 and TRIGI signal 4 34 to 4 35 AT MIO 64E 3 TRIG2 signal 4 36 general purpose timing signal connections 4 46 to 4 57 analog input A 1 to A 5 amplifier characteristics A 3 dynamic characteristics FREQ_OUT signal 4 52 GPCTRO_GATE signal 4 47 GPCTRO_OUT signal 4 47 to 4 48 GPCTRO_SOURCE signal 4 46 GPCTRO_UP_DOWN signal 4 48 GPCTR1_GATE signal 4 49 to 4 50 GPCTR1_OUT signal 4 50 GPCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 A 4 to A 5 input characteristics A 1 to A 2 stability A 5 transfe
137. nternal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation 5 3 AT MIO AI E Series User Manual Appendix Specifications This appendix lists the specifications of each board in the AT E Series These specifications are typical at 25 C unless otherwise noted AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Analog Input Input Characteristics Number of channels AT MIO 16E 1 AT MIO 16E 2 cc eeeeeereeeeeee 16 single ended or 8 differential software selectable AT MIO 64E 3 0 ec ceeeeeeeteeeeeee 64 single ended or 32 differential software selectable Ly pe Of ADCr cei eneke eri pes Successive approximation Resolution cccc cece ceeecceeceeeseeeeseees 12 bits 1 in 4 096 Max sampling rate AT MIO 16E 1 oo eeeeeeeeeee 1 25 MS s guaranteed AT MIO 16E 2 AT MIO 64E 3 neeesser 500 kS s guaranteed Throughput to system memory EISA machines cceeeeeeeeeeeees 1 0 1 25 MS s ISA PCI machines 600 900 kS s National Instruments Corporation A 1 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 AT MIO A
138. ny resistors at all This connection works well for DC coupled sources with low source impedance less than 100 Q However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 7 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 kQ and produce a 1 gain error Both inputs of t
139. olar input means that the input voltage range is between Vef 2 and V e 2 The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V 3 7 AT MIO AI E Series User Manual Chapter 3 Hardware Overview AT MIO AI E Series User Manual You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have gains of 0 5 1 2 5 10 20 50 and 100 and are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Precision Range Gain Actual Input Range Precision Configuration 0to l0V 1 0 0 to 10 V 2 44 mV 2 0 Oto 5 V 1 22 mV 5 0 0 to 2 V 488 28 uV 10 0 Oto 1 V 244 14 uV 20 0 0 to 500 mV 122 07 uV 50 0 0 to 200 mV 48 83 uV 100 0 0 to 100 mV 24 41 uV 5 to 5 V 0 5 10 to 10 V 4 88 mV 1 0 5 to 5 V 2 44 mV 2 0 2 5 to 2 5 V 1 22 mV 5 0 l to 1 V 488 28 uV 10 0 500 to
140. on mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to tri state at startup National Instruments Corporation 4 43 AT MIO AI E Series User Manual Chapter 4 Signal Connections Figures 4 28 and 4 29 show the input and output timing requirements for the UPDATE signal Rising edge polarity Falling edge polarity tw 300 350 ns Figure 4 29 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The AT E Series board UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate AT MIO AI E Series User Manual 4 4
141. on is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages LabVIEW or LabWindows CVI your application uses the NI DAQ driver software as illustrated in Figure 1 1 Conventional Programming LabVIEW LabWindows CVI Environment PC Macintosh or PC or PC Macintosh or Sun SPARCstation Sun SPARCstation Sun SPARCstation NI DAQ Driver Software Jo Personal DAQ or Computer SCXI Hardware or Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware AT MIO AI E Series User Manual 1 4 National Instruments Corporation Chapter 1 Introduction You can use your AT E Series board together with other PC AT EISA DAQCard and DAQPad Series DAQ and SCXI hardware with NI DAQ software for PC compatibles Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level
142. onal Instruments Corporation Chapter 1 Introduction Unpacking Your AT E Series board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer e Never touch the exposed pins of connectors National Instruments Corporation 1 7 AT MIO AI E Series User Manual Chapter Installation and Configuration This chapter explains how to install and configure your AT E Series board Software Installation You may need to install your software before you install your AT E Series board Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using NI DAQ refer to the NI DAQ User Manual for PC Compatibles Version 4 9 0 Release Notes Find the installation section for your operating system and follow the instructions given there If you are using Lab VIEW refer to your
143. onal Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source e You should route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended part numbers for connectors that mate to the I O connector on your AT E Series board Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments part number 776832 01 e AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 16XE 50 Honda 68 position solder cup female connector part number PCS E68FS Honda backshell part number PCS E68LKPA e AT MIO 64E 3 and AT MIO 16DE 10 AMP 100 position IDC male connector part number 1 7509 13 9 AMP backshell 50 max O D cable part number 749081 1 AMP backshell 55 max O D cable part number 749854 1 AT MIO AI E Series User Manual 1 6 Nati
144. onnections 4 24 floating signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 input polarity and range 3 7 to 3 10 AT MIO 16E 1 AT MIO 16E 2 AT MIO 643 3 AT MIO 16E 10 and National Instruments Corporation Index AT MIO 16DE 10 3 7 to 3 8 actual range and measurement precision table 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 9 to 3 10 AT MIO 16XE 10 AT MIO 16XE 50 actual range and measurement precision table 3 10 mixing bipolar and unipolar channels note 3 9 selection considerations 3 10 installation See also configuration common questions about C 2 to C 3 hardware installation 2 1 to 2 2 unpacking AT E series boards 1 7 interrupt channel selection overview 2 4 PC AT 16 bit DMA channel assignment map table 2 7 PC AT I O address map table 2 4 to 2 5 PC AT interrupt assignment map table 2 6 INTR signal table 4 54 L LabVIEW and LabWindows CVI 1 3 manual See documentation mode input Port C signal assignments table 4 53 timing specifications 4 55 mode output Port C signal assignments table 4 53 timing specifications 4 56 mode 2 bidirectional transfers Port C signal assignments table 4 53 timing specifications 4 57 multiple channel scanning 3 12 to 3 13 AT MIO AI E Series User Manual Index NI DAQ driver software 1 3 to 1 5 noise avoiding 4 58 NRSE nonreferenced single ended input description table
145. orporation National Instruments Corporation Chapter 3 Hardware Overview lowValue Trigger Figure 3 9 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue LowValue is unused highValue Trigger Figure 3 10 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the high Value highValue lowValue Trigger 2 Figure 3 11 Inside Region Analog Triggering Mode 3 17 AT MIO AI E Series User Manual Chapter 3 Hardware Overview In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue highValue feacNec ade aaNed x lowValue Trigger Figure 3 12 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue highValue lowValue ___ Trigger Figure 3 13 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timi
146. output personal computer Programmable Function Input Programmable Gain Instrumentation Amplifier parts per million root mean square referenced single ended mode resistive temperature device Real Time System Integration seconds samples scan clock signal Signal Conditioning eXtensions for Instrumentation single ended inputs SI counter clock signal G 5 AT MIO AI E Series User Manual Glossary STARTSCAN T TC THD TRIG TTL U UI UISOURCE UPDATE V V VDC VIH VIL VoH VOL Vref W WFTRIG AT MIO AI E Series User Manual start scan signal terminal count total harmonic distortion trigger signal transistor transistor logic update interval update interval counter clock signal update signal volts volts direct current volts input high volts input low volts in volts output high volts output low reference voltage waveform generation trigger signal G 6 National Instruments Corporation Symbols 5 V signal description 4 6 power connections 4 30 A ACH lt 0 15 gt signal analog input connections 4 16 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 ACH lt 0 63 gt signal analog input connections 4 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 ACK signal table 4 54 addresses base I O address selection 2 3 PC AT I O address map
147. pansion slot cover on the back panel of the computer 5 Insert the AT E Series board into an EISA or 16 bit ISA slot It may be a tight fit but do not force the board into place 6 Screw the mounting bracket of the AT E Series board to the back panel rail of the computer Check the installation Replace the cover Plug in and turn on your computer The AT E Series board is installed You are now ready to install and configure your software Board Configuration Bus Interface AT MIO AI E Series User Manual Due to the DAQ PnP features the AT E Series boards are completely software configurable Two types of configuration must be performed on the AT E Series boards bus related configuration and data acquisition related configuration Bus related configuration includes setting the base I O address DMA channels and interrupt channels Data acquisition related configuration explained in the next chapter includes such settings as analog input polarity and range analog output reference source and other settings For more information about data acquisition related configuration refer to your NI DAQ user manual The AT E Series boards work in either a Plug and Play mode or a switchless mode These modes dictate how the base I O address DMA channels and interrupt channels are determined and assigned to the board 2 2 National Instruments Corporation Chapter 2 Installation and Configuration Plug and Play The AT E
148. poration 5 1 AT MIO AI E Series User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the board is installed in the environment in which it will be used Self Calibration Your AT E Series board can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method you can use This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application You should initiate self calibration to ensure that the effects of any offset gain and linearity drifts particularly those due to warmup are minimized Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration AT MIO AI E Series User Manual Your AT E Series board has an onboard calibration reference to ensure the accuracy of self calibration
149. r differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines One line connects to the positive input of the board programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA connects to the analog input sense AISENSE input For more information about the three types of input configuration refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range National Instruments Corporation AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V ef Where Vef is a positive reference voltage Bip
150. r AT E Series board Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the board The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the board Your AT E Series board A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the board If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations National Instruments Corporation 4 17 AT MIO AI E Series User Manual Chapter 4 Signal Connections Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground referenc
151. r characteristics A 3 analog output A 6 to A 8 dynamic characteristics A 7 output characteristics A 6 stability A 7 to A 8 transfer characteristics A 7 voltage output A 7 bus interface A 10 digital I O A 8 environment A 10 physical A 10 programmable function input power requirements A 10 connections 4 31 to 4 32 timing I O A 8 to A 9 waveform generation timing triggers connections 4 42 to 4 45 analog trigger A 9 UISOURCE signal 4 45 digital trigger A 10 UPDATE signal 4 43 to 4 44 RTSI A 10 WFTRIG signal 4 42 to 4 43 AT MIO 16E 10 and AT MIO 16DE 10 types of signal sources 4 18 analog input A 11 to A 13 floating 4 18 amplifier characteristics A 12 ground referenced 4 18 dynamic characteristics single ended connections A 12 to A 13 description 4 24 input characteristics floating signal sources RSE 4 25 A 11 to A 12 grounded signal sources NRSE 4 25 when to use 4 24 SISOURCE signal 4 41 to 4 42 stability A 13 transfer characteristics A 12 analog output A 13 to A 15 dynamic characteristics A 15 National Instruments Corporation l 11 AT MIO AI E Series User Manual Index output characteristics A 13 to A 14 stability A 15 transfer characteristics A 14 voltage output A 14 to A 15 bus interface A 17 digital I O A 15 to A 17 environment A 18 physical A 18 power requirements A 18 timing I O A 17 triggers digital trigger A 17 RTSI A 17 AT MIO 16XE 10 and AT AI 16
152. r the AT MIO 64E 3 Voltage Calibration 12 Bit Selection i Sampling Data Switches A D Transceivers Converter EEPROM Configuration x Memory Ti Analog Input PFI Trigger nigger Timing Control Trigger Level 2 DACs Analog Trigger Trigger Circuitry 19g gt Interrupt Analog 1 1 EEPROM DMA Request Input Control Interface 1 1 Control Counter PERN Timing I O DAQ STC interface DAQ PnP 1 Analog Output 1 RTSI Bus Analog 8255 Digital 1 O Timing Control Interface ont I O Connector Digital 1 0 8 AT I O Channel AO Control Figure 3 2 AT MIO 64E 3 Block Diagram AT MIO AI E Series User Manual 3 2 National Instruments Corporation Chapter 3 Hardware Overview Figure 3 3 shows the block diagram for the AT MIO 16E 10 and AT MIO 16DE 10 Calibration 12 Bit Sampling Data ND Transceivers Mux Mode Selection Switches Converter Dither Circuitry Configuration Memory Analog Input PFI Trigger M Interrupt Trigger Timing Control P Analog EEPROM DMA Request Input EG i Control Control Interface Counter pra DAQ STC Timing I O DAQ STC interface Bus DAQ PnP Interface Bus fo 2 ta Cc Cc e O O x Analog Output RTSI Bus Analog 8255 Output Digital 1 O 8 Digital VO Timing Control Interface Con
153. ration Table of Contents Figure 4 1 I O Connector Pin Assignment for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 oo eee ceeeceeeeeeeeseeeneenee 4 2 Figure 4 2 I O Connector Pin Assignment for the AT MIO 64E 3 oo ee 4 3 Figure 4 3 I O Connector Pin Assignment for the AT MIO 16DE 10 oo 4 4 Figure 4 4 ATE Series POIA e eae e ia terie e EEE RE ea E 4 17 Figure 4 5 Summary of Analog Input Connections sesesessseeersseereerereererrerrseeeesesee 4 19 Figure 4 6 Differential Input Connections for Ground Referenced Signals 4 21 Figure 4 7 Differential Input Connections for Nonreferenced Signals 0 4 22 Figure 4 8 Single Ended Input Connections for Nonreferenced or Bloating Sipmals 4 2c iecesds fh loscpes pecesedes ee E ae r nE emetic rene 4 25 Figure 4 9 Single Ended Input Connections for Ground Referenced Signal 4 26 Figure 4 10 Analog Output Connections 2 0 0 eee ceeeeeeceeeeeeeeeeeeecaeesaecaeesaecaeeaeenees 4 28 Figure 4 11 Digital I O Connections 0 cece eeeececeeeceseeeeeeseeeeecaeesaecaeesaecneesaeenees 4 29 Figure 4 12 Timing I O Connections 2 0 0 cece eceeceeeeeceseeeeeeeeeeeecaeesaecseesaecseesaeenees 4 31 Figure 4 13 Typical Posttriggered Acquisition 0 eee eeeeeeeeeeceeeeecaeeaecseesaeenees 4 32 Figure 4 14 Typical Pretriggered Acquisition 00 0 cece eeeceseeeeecseeeeeceeeaeceeeaeenees 4 33 Figure 4 15 SCAN
154. rence EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for the same mode Analog Output Polarity Selection AT MIO AI E Series User Manual AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 only You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to V ref at the analog output A bipolar configuration has a range of Vref to V ef at the analog output V ef is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 10 and 10 V You do not need to configure both channels for the same range 3 14 National Instruments Corporation Chapter 3 Hardware Overview Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive AT MIO 16XE 10 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog outpu
155. ress Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin TX 78730 5039 Glossary Prefix Meaning Value p pico 10712 n nano 1079 u micro 1076 m milli 1073 k kilo 103 M mega 106 G giga 10 Symbols percent T plus or minus degrees per positive of or plus negative of or minus Q ohms T square root of 5V 5 VDC source signal National Instruments Corporation G 1 AT MIO AI E Series User Manual Glossary A A AC ACH A D ADC AIGATE AIGND AISENSE AISENSE2 ANSI AOGND ASIC BIOS C C CalDAC CMOS CMRR CONVERT AT MIO AI E Series User Manual amperes alternating current analog input channel signal analog to digital A D converter analog input gate signal analog input ground signal analog input sense signal analog input sense 2 signal American National Standards Institute analog output ground signal application specific integrated circuit basic input output system or built in operating system Celsius calibration DAC complementary metal oxide semiconductor common mode rejection ratio convert signal G 2 National Instruments Corporation D D A DAC DACOOUT DACIOUT DAQ DC DGND DIFF DIO DMA DNL E EEPROM EISA EXTREF EXTSTROBE F
156. rol the analog input data acquisition To do this follow steps a through d below in addition to the usual steps for data acquisition and waveform generation configuration a Enable the PFI5 line for output as follows e If you are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW e If you are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update C 4 National Instruments Corporation Timing and Digital 1 0 18 19 National Instruments Corporation AppendixC Common Questions b Set up data acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows e If you are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW e Ifyou are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 c Initiate analog input data acquisition which will start only when the analog output waveform generation starts e Ifyou are using NI DAQ call DAQ_St art with appropriate parameters e Ifyou are using LabVIEW invoke AI Control VI with control code set to O start d Initiate analog output waveform generation e If you are using NI DAQ call WRM_Group_Control with operation set to 1 start e Ifyou are using LabVIEW invoke AO Control VI with control code set to 0 start What
157. ruments Corporation Chapter 4 Signal Connections Timing Specifications for Digital 1 0 Ports A B and C AT MIO 16DE 10 only In addition to its function as a digital I O port digital port C PC lt 0 7 gt can also be used for handshaking when performing data transfers with ports A and B The signals assigned to port C depend on the mode in which it is programmed In mode 0 port C is considered two 4 bit I O ports In modes 1 and 2 port C is used for status and handshaking signals with two or three additional I O bits Table 4 5 summarizes the signal assignments of port C for each programmable mode Table 4 5 Port C Signal Assignments Programming Group A Group B Mode PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO Mode 0 T O T O T O T O T O T O T O T O Mode 1 Input vO vO IBFA STB INTRA STBg IBFBg INTRg Mode 1 Output OBFa ACKa TO vO INTRA ACKp OBFR INTRg Mode 2 OBFa ACKa IBFa STBA INTRA rO vO vO Indicates that the signal is active low National Instruments Corporation 4 53 AT MIO AI E Series User Manual Chapter 4 Signal Connections This section lists the timing specifications for handshaking with the AT MIO 16DE 10 port C circuitry The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers The following signals are used in the timing diagrams that follow Nam
158. s manual AT MIO AI E Series User Manual xiv National Instruments Corporation Chapter Introduction This chapter describes the AT E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your AT E Series board About the AT E Series Thank you for buying a National Instruments AT E Series board The AT E Series boards are the first completely Plug and Play compatible multifunction analog digital and timing I O boards for the PC AT and compatible computers This family of boards features 12 bit and 16 bit ADCs with 16 and 64 analog inputs 12 bit and 16 bit DACs with voltage outputs eight and 32 lines of TTL compatible digital I O and two 24 bit counter timers for timing I O Because the AT E Series boards have no DIP switches jumpers or potentiometers they are easily configured and calibrated using software The AT E Series boards are the first completely switchless and jumperless data acquisition boards This feature is made possible by the National Instruments DAQ PnP bus interface chip that connects the board to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you to easily change the AT E Series board configuration without having to remove the board from your computer The DAQ STC makes possible such applications as b
159. secesseceseeecesseceesaecessaeeeseseceseseeeneeaeess 1 3 Register Level Programming 0 cc eeceseeeecesceeeceseeseeeeeeeeeeaseseeenesaeecaeenaeeaees 1 5 Optional Equipment ar iosa oker rien re we eine E o Ee nude A SINIST oe 1 5 C stom Cablin gs na ser cceisiecseitibeeeseesheueeaneedinavane E ESEA E ES 1 6 Unpacking a a Relig ee huis en ea E E S 1 7 Chapter 2 Installation and Configuration Software Installation A REN EEEE PE EE E EE EE EE EN 2 1 Hardware Installation e Ere RE E A E EE E E EES 2 1 Boatd Configuration sestiere ee rresia Shaa Eear ES E EEEE 2 2 JARRA DIr n Ke Te A A E S EEL SE E E EE E EA EEEE EEA 2 2 Plug and Play s 5 5 scsccceecisesscesseasseszetasnss wpestass t Esos se EKE s RESER EE T 2 3 Switchless Data Acquisition eeeeseseessseesesestsresrrererrerrsreresrsserrreere 2 3 Base I O Address Selection 0 cccccccccessssssceceesesececesenenseceecesenseaeees 2 3 DMA Channel Selection soera aE R S Eae 2 3 Interrupt Channel Selection sseesesseesseeesesseeesresrrerssrerrsreresreresrenreees 2 4 National Instruments Corporation v AT MIO AI E Series User Manual Table of Contents Chapter 3 Hardware Overview Analog Input scecusataeeiin He en a i ei a E Eaa ae EE aa AEE ae es 3 6 Input Mode sinees a Gin ation dtsertechaniie nite ate ata 3 6 Input Polarity and Input Range 0 eee eeesee cee ceseceeceseeeeceseeeeeteeeeeeeaeeees 3 7 Considerations for Selecting Input Ranges eee ee
160. si Short circuit to ground Power on State seeeeeeeee eee OV A 14 National Instruments Corporation Digital 1 0 Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 External reference input Range ticcacccest nenene 11 V Overvoltage protection 35 V powered on 25 V powered off Input impedance 10 KQ Bandwidth 3 dB ee eeeeeee 300 kHz Dynamic Characteristics Settling time for full scale step 10 us to 0 5 LSB accuracy Slew Fate enes es a en eta as 15 V us INOISE fax rrer EE Ren E EE 200 uVrms DC to 1 MHz Glitch energy at midscale transition Magnitude 100 mV Durations cccissteissccsessieasestve sees heise 3 Us Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference eee 25 ppm C External reference ee 25 ppm C Onboard calibration reference A A E EE sddecdee theta bs 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 0 15 ppm 1 000 h Number of channels AT MIO 16E 10 0 eee 8 input output AT MIO 16DE 10 eee 32 input output Compatibility oreo TTL CMOS National Instruments Corporation A 15 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Digital logic levels Level Min Max Input low voltage O
161. software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program your National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as register level programming and can save weeks of development time Optional Equipment National Instruments offers a variety of products to use with your AT E Series board including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon e Connector blocks shielded and unshielded 50 68 and 100 pin screw terminals e Real Time System Integration RTSI bus cables e Signal condition eXtension for instrumentation SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3072 channels e Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you National Instruments Corporation 1 5 AT MIO AI E Series User Manual Chapter 1 Introduction Custom Cabling Nati
162. sscceceesessceceeesesssececesensaeeeeees 1 4 Figure 3 1 AT MIO 16E 1 and AT MIO 16E 2 Block Diagram eseeesesceeeeeeee 3 1 Figure 3 2 AT MIO 64E 3 Block Diagram eeesssesseeeeesssresssresesresesrrsrrrrssrerssreresre 3 2 Figure 3 3 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram ee 3 3 Figure 3 4 AT MIO 16XE 10 Block Diagram seseseeesseeesssresesresesrrsrrrrssreresreresee 3 4 Figure 3 5 AT AI 16XE 10 Block Diagram esseeeseseeeesseeesssresrsresrsrrererrssrerssreresre 3 5 Figure 3 6 AT MIO 16XE 50 Block Diagram sesssseeesseeesssresesresrsrrererrssrerssresesee 3 6 Bigure a A Di E e E E ET 3 12 Figure 3 8 Analog Trigger Block Diagram sessseessseeeesssrssssreresreresresrerrsrenrssreresee 3 16 Figure 3 9 Below Low Level Analog Triggering Mode sesseesseeeseeeeeersererereresee 3 17 Figure 3 10 Above High Level Analog Triggering Mode 0 00 eee eee eeeeeereereeeee 3 17 Figure 3 11 Inside Region Analog Triggering Mode 00 0 eee ee eeeeeseeeeceeeeeeeeeeeees 3 17 Figure 3 12 High Hysteresis Analog Triggering Mode 00 eee ee ceeeeeeeeeeeeeeeeeeeee 3 18 Figure 3 13 Low Hysteresis Analog Triggering Mode oo eee eee eeeeeeeeeeeeeeee 3 18 Figure 3 14 CONVERT Signal Routing oo eee ceeceecneceseeeeenseeeeeeeeeeeeeaeeees 3 20 Figure 3 15 RTSI Bus Signal Connection 20 eee ec cseeseceeceeceeceseeeeesseeeseeeeeeeseaeeees 3 22 AT MIO AI E Series User Manual viji National Instruments Corpo
163. st be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tgsu and ty in Figure 4 37 The gate signal is not required to be held after the active edge of the source signal If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the ATE Series boards Figure 4 37 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ OUT pin The FREQ_OUT signal is the output of the AT E Series board frequency generator The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri state at startup AT MIO AI E Series User Manual 4 52 National Inst
164. support helps our applications engineers answer your questions more efficiently National Instruments Products AT E Series Board AT E Series Board Serial Number Interrupt Level of AT E Series Board DMA Channels of AT E Series Board Base I O Address of AT E Series Board Programming Choice NI DAQ LabVIEW LabWindows CVI or other Software Version Other Products Computer Model Microprocessor Clock Frequency Type of Video Board Installed Operating System DOS or Windows Operating System Version Operating System Mode Programming Language Programming Language Version Other Boards in System Base I O Address of Other Boards DMA Channels of Other Boards Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title AT MIO AI E Series User Manual Click here to comment on this document via the National Instruments website at Editon Date Mey http www natinst com documentation daq Part Number 320517E 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Add
165. t A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range Analog Output Reglitch Selection Analog Trigger AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 only In normal operation a DAC output will glitch whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output of the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at startup and can be independently enabled for each channel through software National Instruments Corporation AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 only In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIG1 pin on the I O connector or a postgain sig
166. t on this document via the National Instruments website at http www natinst com documentation daq Appendix Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a FaxBack system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services a
167. ternal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible How fast is each AT E Series board The last numeral in the name of an AT E Series board specifies the settling time in microseconds for that particular board For example the AT MIO 16E 2 has a 2 us settling time which corresponds to a sampling rate of 500 kS s These sampling rates are aggregate one channel at 500 kS s or two channels at 250 kS s per channel illustrates the relationship Notice however C 1 AT MIO AI E Series User Manual Appendix C Common Questions that some AT E Series boards have settling times that vary with gain and accuracy See Appendix A for exact specifications What type of 5 V protection do the AT E Series boards have The AT E Series boards have 5 V lines equipped with a self resetting 1 A fuse Installation and Configuration 5 AT MIO AI E Series User Manual How do I configure an AT E Series board on an EISA computer You must configure the board with DAQCONF or WDAQCONF you cannot use an EISA configuration utility to configure the board How do you set the base address for an AT E Series board Under the AT E Series device option there is a field for base I O address type in the desired base I O address 0x180 200 220 240 280 and 300 are typical base
168. that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN will be deasserted t tp after the last conversion in the scan is initiated This output is set to tri state at startup National Instruments Corporation 4 37 AT MIO AI E Series User Manual Chapter 4 Signal Connections Figures 4 21 and 4 22 show the input and output timing requirements for the STARTSCAN signal Rising edge polarity Falling edge polarity tw 10ns minimum Figure 4 21 STARTSCAN Input Signal Timing STARTSCAN ty 50 100 ns a Start of Scan Start Pulse CONVERT STARTSCAN tof 10 ns minimum b Scan in Progress Two Conversions per Scan Figure 4 22 STARTSCAN Output Signal Timing AT MIO AI E Series User Manual 4 38 National Instruments Corporation Chapter4 Signal Connections The CONVERT pulses are masked off until the board generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT will appear when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN will generate a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on your AT E Series board internally generates the STARTSCAN signal unless you select some external source This counter is started by
169. the internal timebase without driving the RTSI bus timebase signal You select this timebase through software RTSI Triggers The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any AT E Series board sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 15 National Instruments Corporation 3 21 AT MIO AI E Series User Manual Chapter 3 Hardware Overview DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE lt __ _ switch RTSI_OSC 20 MHz Trigger lt c gt 7 RTSI Bus Connector RTSI Switch Figure 3 15 RTS Bus Signal Connection Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3 15 AT MIO AI E Series User Manual 3 22 National Instruments Corporation Chapter Signal Connections This chapter describes how to make input and output signal connections to your AT E Series board via the board I O connector The I O connector for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 has 68 pins that you can connect to 68 pin accessories with the SH6868 shielded cable or the R6868 r
170. the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 13 and 4 14 for the relationship of CONVERT to the data acquisition sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup National Instruments Corporation 4 39 AT MIO AI E Series User Manual Chapter 4 Signal Connections Rising edge polarity Falling edge polarity AT MIO AI E Series User Manual Figures 4 23 and 4 24 show the input and output timing requirements for the CONVERT signal
171. the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition library is functionally equivalent to the NI DAQ software Using LabVIEW or LabWindows CVI software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with signal conditioning or accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI calibration messaging and acquiring data to extended memory National Instruments Corporation 1 3 AT MIO AI E Series User Manual Chapter 1 Introduction NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level functi
172. to manually change any settings on the board The following tables provide information concerning possible conflicts when configuring your AT E Series board Table 2 1 PC AT I O Address Map I O Address Range Hex Device 100 to 1EF 1F0 to 1F8 IBM PC AT Fixed Disk 200 to 20F PC and PC AT Game Controller reserved 210 to 213 PC DIO 24 default 218 to 21F 220 to 23F Previous generation of AT MIO boards default 240 to 25F AT DIO 32F default 260 to 27F Lab PC PC default 278 to 28F AT Parallel Printer Port 2 LPT2 279 Reserved for Plug and Play operation 280 to 29F WD EtherCard default 2A0 to 2BF 2E2 to 2F7 2F8 to 2FF PC AT Serial Port 2 COM2 2 4 National Instruments Corporation Chapter 2 Installation and Configuration Table 2 1 PC AT I O Address Map Continued T O Address Range Hex Device 300 to 30F 3Com EtherLink default 310 to 31F 320 to 32F ICM PC XT Fixed Disk Controller 330 to 35F 360 to 363 PC Network low address 364 to 367 Reserved 368 to 36B PC Network high address 36C to 36F Reserved 370 to 366 PC AT Parallel Printer Port 1 LPT1 380 to 38C SDLC Communications 380 to 389 Bisynchronous BSC Communications alternate 390 to 393 Cluster Adapter 0 394 to 39F 3A0 to 3A9 BSC Communications primary 3AA to 3AF 3B0 to 3BF Monochrome Display Parall
173. to those that the ADC can accommodate The AT MIO 16XE 10 and AT AI 16XE 10 have gains of 1 2 5 10 20 50 and 100 and the AT MIO 16XE 50 has gains of 1 2 10 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows the overall input range and precision according to the input range configuration and gain used 3 9 AT MIO AI E Series User Manual Chapter 3 Hardware Overview AT MIO AI E Series User Manual Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Range Gain Actual Input Range Precision Configuration 0to 10V 1 0 0 to 10 V 152 59 uV 2 0 0 to 5 V 76 29 UV 5 07 0to 2V 30 52 uV 10 0 Oto 1 V 15 26 uV 20 07 0 to 500 mV 7 63UV 50 07 0 to 200 mV 3 05 uV 100 0 0 to 100 mV 1 53 uV 10 to 10 V 1 0 10 to 10 V 305 18 uV 2 0 5 to 5 V 152 59 uV 5 0 2 to 2 V 61 04 uV 10 0 1 to 1 V 30 52 uV 20 07 500 to 500 mV 15 26 uV 50 07 200 to 200 mV 6 10 uV 100 0 100 to 100 mV 3 05 uV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count 2 AT MIO 16XE 10 and AT AI 16XE 10 only Note See Appendix A Specifications for absolute maximum ratings Considerations for Selecting Input Ranges Which input polarity and range you select dep
174. trol AT I O Channel lt AT MIO 16DE 10 ONLY Data 16 Calibration DACs Figure 3 3 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram The primary differences between the AT MIO 16E 10 and the AT MIO 16DE 10 are in the 8255 DIO port which is not present on the AT MIO 16E 10 and the I O connector National Instruments Corporation 3 3 AT MIO AI E Series User Manual Chapter 3 Hardware Overview Figure 3 4 shows a block diagram for the AT MIO 16XE 10 gt REF Voltage Calibration Buffer 16 Bit iid Selection Programmable Sampling oe Switches mp Transceivers Amplifier Converter gt Calibration gt Mux EEPROM EEPROM Configuration Al Control Memory 7 2 Trigger Level Analog IRQ DMA DACs Trigger Trigger Circuitry TN 4 Analog Input Trigger Timing Contro nterrupt Analog IEEPROMI DMA PFI Trigger Request RL Control 1 Interface 1 Counter DAQ STC Plug Timing i o DAQ STC interface Bus paapnP and Interface Play 7 1 Analog Output 1 RTSI Bus Analog 8255 Bus Digital O 8 j Digital O i Timing Control i Interface Output t alos interface i gt AO Control 1 1 DAC T F gesta 2 Calibration 4 DACs Figure 3 4 AT MIO 16XE 10 Block Diagram I O Connector AT I O Channel
175. ttings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter Data Acquisition Timing Connections AT MIO AI E Series User Manual The data acquisition timing signals are SCANCLK EXTSTROBE TRIGI TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered data acquisition sequence is shown in Figure 4 13 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 14 shows a typical pretriggered data acquisition sequence The description for each signal shown in these figures is included later in this chapter TRIG1 STARTSCAN CONVERT Scan Counter Figure 4 13 Typical Posttriggered Acquisition 4 32 National Instruments Corporation Chapter 4 Signal Connections TRIG1 TRIG2 Don t Care STARTSCAN CONVERT Scan Counter Figure 4 14 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an
176. u EXTSTROBE DO 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFIO TRIG1 DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI1 TRIG2 DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 kQ pu PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu AT MIO AI E Series User Manual 4 14 National Instruments Corporation Chapter 4 Signal Connections Table 4 4 1 0 Signal Summary AT MIO 16XE 50 Continued Signal Name Drive Impedance Protection Source Sink Rise Bias Input Volts mA at V mA at Time Output On Off V ns PFI5S UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu GPCTRO_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu FREQ_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu IDIO lt 6 7 gt are also pulled down with a 50 kQ resistor AI Analog Input DIO Digital Input Output pu pu
177. uble buffered FIFO buffer size None Data transfers cccceeeeeceeereeeeeeeeeeeee DMA interrupts programmed I O DMA Modes icien Single transfer Transfer Characteristics Relative accuracy INL ceeeeee 0 5 LSB max DNE ccscletestie tis eias ans e 1 LSB max Monotonicity 2 0 eect ceeeeeeeeeeeeeeeee 12 bits guaranteed A 28 National Instruments Corporation Appendix A Specifications for AT MIO 16XE 50 Offset error After calibration ccceeeeeees 0 5 mV max Before calibration 008 85 mV max Gain error relative to calibration reference After calibration eee 0 01 of output max Before calibration 1 of output max Voltage Output RANGE a eae anes aE E E Eo 10 V Output coupling eee DC Output impedance eee 0 1 Q max Current dri Vein eisscc essiz soetat 5 mA Protection ois sseeccesieccessesstecccne eestene Short circuit to ground Power on State ccceeeceeeesseeeeeeeeeeee 0V 85 mV Dynamic Characteristics Settling time for full scale step 50 us to 0 5 LSB accuracy Slew Tate cgeSis wien eetnta cette Hee 2 V s INOISE fas O OA 40 uVrms DC to 1 MHz Glitch energy at midscale transition Magnitude eects 30 mV Duration sous tiers 10 us Stability Offset temperature coefficient 25 wV C Gain temperature coefficient 15 ppm C Onboard calibration reference Level nev 5 000 V
178. uffered pulse generation equivalent time sampling and seamlessly changing the sampling rate The AT E Series boards use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns A common problem with DAQ boards is that you cannot easily synchronize several measurement functions to a common trigger or National Instruments Corporation 1 1 AT MIO AI E Series User Manual Chapter 1 Introduction timing event The AT E Series boards have the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of our RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ boards in your PC The AT E Series boards can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Detailed specifications of the AT E Series boards are in Appendix A Specifications What You Need to Get Started To set up and use your AT E Series board you will need the followi
179. um working voltage signal common mode The average voltage of each differential pair should remain within 8 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected 0 ee ACH lt 0 15 gt AISENSE FIFO buffer size eee eee 512 samples Data transfers oseiro DMA interrupts programmed I O DMA modes Single transfer demand transfer Configuration memory size 512 words National Instruments Corporation A 26 AT MIO AI E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Transfer Characteristics Relative accuracy eeeeeeeeeeeeeees 0 5 LSB typ 1 LSB max DNs ce tusisnisiec aeons 0 5 LSB typ 1 LSB max No missing codes sesser 16 bits guaranteed Offset error Pregain error after calibration 3 uV max Pregain error before calibration 1 mV max Postgain error after calibration 76 WV max Postgain error before calibration 4 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2250 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 2 0n neno 100 ppm of reading Gain FOO isisisi esise issis 250 ppm of reading Amplifier Characteristics Input impedance Normal powered oN eeee 7 GQ in parallel with 100 pF Powered Off 5 0 sc csccsssesssssecsasenes 820 Q min Overload sise

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