Maxim MAX12557 User's Manual
Contents
1. DIFFCLK SECLK OVpp PD GND G T GND 65 2 50 duty cycle TA 25 C unless otherwise noted TWO TONE IMD PLOT TWO TONE IMD PLOT FFT PLOT 32 768 POINT DATA RECORD 16 384 POINT DATA RECORD 16 384 POINT DATA RECORD 0 2 65 00352MHz 65 00352MHz s 65 00352MHz 8 10 Fin 174 98857MHz 5 fini 68 49987MHz 8 1 1 172 49995MHz 3 20 0 476dBFS E 6 97dBFS 6 95dBFS 1 E 30 sNR fino 71 49930dB fino 177 49900688MHz SINAD 70 4808 6 99dBFS 2 6 97dBFS es 7 THD 75 62dBc es IM3 91 54dBc a IM3 87 61dBc 50 SFDR 76 37dBc us IMD 87 97dBc IMD 82 37dBc B9 amp 70 HD3 2fiNo a Z 80 HD3 5 90 100 K 110 120 0 5 10 15 20 2 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE vs DIGITAL OUTPUT CODE SNR SINAD vs ANALOG INPUT FREQUENCY 4 194 304 POINT DATA RECORD 4 194 304 POINT DATA RECORD 65 00352MHz Ajy 0 5dBFS 1 00 0 x fin 3 00123MHz E B 0 75 B 75 8 8 5 E 5 0 50 L LIE 70 a 055 ull l 65 N e 9 60 amp 52 025 amp 552. 0 75 45 1 00 40 0 2048 4096 6144 8192 1024012288 14336 16384 0 2048 4096 6144 8192 1024012288 14336 16384 0 50 100 150 200 250 300 350 400 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE fin MHz THD SFDR vs ANALOG INPUT FREQUENCY SNR SINAD vs ANALOG INPUT AMPLITUDE THD SFDR vs ANALOG INPUT AMPLITUDE 65 00352 2 Ai 0 5dBFS 65 00352MHz fiy 70MHz 65 00352MHz fiy 70MHz 80 95 8 SNR 5 E 70 85 5 3 60 S 75 2 50 5 65 n SINAD c T amp 40 0 30 45 20 35 0 50 100 150 200 250 300 350 400 55 50 45 40 35 30 25 20 15 10 5 0 55 50 45 40 35 30 25 20 15 10 5 0 fin MHz Ain dBFS Ain dBFS 8 Dual 65Msps 14 Bit IF Baseband ADC Typical Operating Characteristics continued Vpp 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference mode 5pF at digital outputs Vin 0 5dBFS DIFFCLK SECLK OVpp PD GND G T GND 65MHz 50 duty cycle TA 25 C unless otherwise noted SNR SINAD vs ANALOG INPUT AMPLITUDE THD SFDR vs ANALOG INPUT A
3. 12557 toc24 18 21 24 27 OVpp V 30 33 36 65 00352MHz fiy 175MHz MAX12557 toc27 MAX12557 10630 900 800 Ppiss ANALOG 700 600 E 500 2 40 2 300 200 100 0 Voo V THD SFDR vs CLOCK DUTY CYCLE fin 70MHz Ay 0 5dBFS GLE ENDED CLOCK DRIVE 25 35 45 55 65 75 CLOCK DUTY CYCLE 96 AVLAZCLAVI Dual 65Msps 14 Bit IF Baseband ADC Typical Operating Characteristics continued Vpp 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference mode 5pF at digital outputs Vin 0 5dBFS DIFFCLK SECLK OVpp PD GND G T GND 65 2 50 duty cycle TA 25 C unless otherwise noted SNR SINAD vs TEMPERATURE THD SFDR vs TEMPERATURE fin 175MHz Ai 0 5dBFS fin 175MHz 0 5dBFS 76 5 90 A SNR 8 5 74 8 8 w 3 72 amp p E t L g 8 Pa ELI 2 SINAD B m g 5 66 T an 64 65 60 60 40 15 10 35 60 85 40 15 10 85 60 85 TEMPERATURE C TEMPERATURE GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE 3 0 3 5 2 5 02 5 gt gt E 601 55 011 85 per z 0 0 ud m lu 72 5 4 5 01 2 0 2 3 0 3 4
4. 175MHz at 0 5dBFS 3MHz at 0 5dBFS 32 5MHz at 0 5dBFS 70MHz at 0 5dBFS 175MHz at 0 5dBFS 1 68 5MHz at 7dBFS Two Tone Intermodulation 2 71 5MHz at 7dBFS 1 172 5MHz at 7dBFS 2 177 5MHz at 7dBFS 1 68 5MHz at 7dBFS 3rd Order Intermodulation 2 71 5MHz at 7dBFS Distortion 1 172 5MHz at 7dBFS 2 177 5MHz at 7dBFS 1 68 5MHz at 7dBFS Two Tone Spurious Free 2 71 5MHz at 7dBFS Dynamic Range 1 172 5MHz at 7dBFS 2 177 5MHz at 7dBFS Full Power Bandwidth FPBW Input at 0 2dBFS 3dB rolloff Aperture Delay igure 5 Signal to Noise Plus Distortion SINAD Spurious Free Dynamic Range Total Harmonic Distortion Second Harmonic Third Harmonic Aperture Jitter INAP INAN Output Noise INBP INBN COMB AVLAZCLAVI 3 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC ELECTRICAL CHARACTERISTICS continued Vpop 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference CL 10pF at digital outputs Vin 0 5 differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND G T GND 65MHz TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS Overdrive Recovery Time 10 beyond full scale INTERCHANNEL CHARACTERISTI
5. _ ne LUATION AILABU General Description 12557 is dual 3 3V 14 bit analog to digital converter ADC featuring fully differential wideband track and hold T H inputs driving internal quantizers The MAX12557 is optimized for low power small size and high dynamic performance in intermediate frequen IF and baseband sampling applications This dual ADC operates from a single 3 3V supply consuming only 610mW while delivering a typical 72 5dB signal to noise ratio SNR performance at a 175MHz input fre quency The T H input stages accept single ended or differential inputs up to 400MHz In addition to low oper ating power the MAX12557 features 1660W power down mode to conserve power during idle periods A flexible reference structure allows the MAX12557 to use the internal 2 048V bandgap reference or accept an externally applied reference and allows the refer ence to be shared between the two ADCs The refer ence structure allows the full scale analog input range to be adjusted from 0 35V to 1 15V The 12557 provides a common mode reference to simplify design and reduce external component count in differential analog input circuits The MAX12557 supports either a single ended or differ ential input clock User selectable divide by two DIV2 and divide by four DIV4 modes allow for design flexibil ity and help eliminate the negative effects of clock jitter Wide variatio
6. is the decimal equivalent of the digital The MAX12557 provides two 14 bit parallel tri state output code as shown in Table 3 output buses DOA B D13A B and DORA B update on Table 3 Output Codes vs Input Voltage GRAY CODE OUTPUT CODE TWO S COMPLEMENT OUTPUT CODE G 1 G T 0 HEXADECIMAL DAE HEXADECIMAL VIN P VIN N BINARY EQUIVALENT OF BINARY EQUIVALENT OE VREF_P 2 418V zi VREF 0 882V D13A DOA OF DADOA D13A D0A OF DISA DOA 2 D13B DOB D13A DOA D13B DOB D13A DOA DisB pog 0138 008 213B D0B CODE10 CODE10 gt 1 023875V 10 0000 0000 0000 Ox2000 416 883 01 11111111 1111 1 DATA OUT OF RANGE 10 0000 0000 0000 0x2000 16 383 01111111111111 Ox1FFF 1 023875V 10 0000 0000 0001 1 416 382 01111111111110 Ox1FFE 1 023750V 11 0000 0000 0011 0x3003 00 0000 0000 0010 0x0002 0 000250V 11 0000 0000 0001 0 3001 00 0000 0000 0001 0 0001 0 000125V 11 0000 0000 0000 0 3000 00 0000 0000 0000 0x0000 0 000000V 01 0000 0000 0000 0x1000 111111 1111 1111 OxSFFF 1 0 000125V 01 0000 0000 0001 0x1001 111111 1111 1110 OxSFFE 0 000250V 00 0000 0000 0001 0x0001 10 0000 0000 0001 0x2001 1 023875V 00 0000 0000 0000 0 0 0000 10 0000 0000 0000 0 2000 1 024000V 1 024000V 00 0000 0000 0000 0 0000 10 0000 0000 0000 0 2000 DATA OUT OF RANGE MAXIM 19 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Ba
7. 4 THE FINAL GRAY CODE CONVERSION IS BIT POSITION BIT POSITION D13 5D11 BINARY GRAY CODE GRAY CODE BINARY EXCLUSIVE OR TRUTH TABLE FIGURE 8 SHOWS THE GRAY TO BINARY AND BINARY TO GRAY CODE CONVERSION IN OFFSET BINARY FORMAT THE OUTPUT FORMAT OF THE MAX12557 IS TWO S COMPLEMENT BINARY HENCE EACH MSB OF THE TWO S COMPLEMENT OUTPUT CODE MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT Figure 8 Binary to Gray and Gray to Binary Code Conversion AVLAZCLAVI 21 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC Applications Information Using Transformer Coupling In general the MAX12557 provides better SFDR and THD with fully differential input signals than single ended input drive especially for input frequencies above 125MHz In differential input mode even order harmonics are lower as both inputs are balanced and each of the ADC inputs only requires half the signal swing compared to single ended input mode An RF transformer Figure 9 provides an excellent solution to convert a single ended input source signal to a fully differential signal required by the MAX12557 for optimum performance Connecting the center tap of the transformer to COM provides a Vpp 2 DC level shift to the input Although a 1 1 transformer is shown a step up transformer can be selected to reduce the drive requirements A reduced signal swing from the input driver such as an op amp can also
8. IF Baseband ADC ELECTRICAL CHARACTERISTICS continued Vpop 3 3V OVpp 2 0V GND 0 REFIN R EFOUT internal reference CL 10pF at digital outputs Vin 0 5dBFS differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND G T GND 65 2 TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER CONDITIONS EF_P Sink Current EF_N Source Current VREF_P 2 418V VREF_N 0 882V COM Sink Current VCOM_ 1 65V REF_P REF_N Capacitance Capacitance CLOCK INPUTS CLKP CLKN Single Ended Input High Threshold FFCLK SECLK GND CLKN GND Single Ended Input Low Threshold Minimum Differential Clock Input Voltage Swing FFCLK SECLK GND CLKN GND DIFFCLK SECLK OV Differential Input Common Mode Voltage DIFFCLK SECLK OV CLK Input Resistance Each input Figure 4 CLK_ Input Capacitance DIGITAL INPUTS DIFFCLK SECLK G T PD DIV2 DIV4 nput Leakage Current High Threshold Low Threshold Input connected to ground Digital Input Capacitance CDIN DIGITAL OUTPUTS D0A D13A DOB D13B DORA DORB DAV Output Voltage Low DOA D13A DOB D13B DORA DORB ISINK 200A DOA D13A DOB D13B DORA DORB ISOURCE 200 Output Voltage High DAV ISOURCE 600 Tri State Leakage Current OVpp applied
9. PD GND G T GND 65MHz 50 duty cycle TA 25 C unless otherwise noted FFT PLOT 32 768 POINT DATA RECORD FFT PLOT 32 768 POINT DATA RECORD FFT PLOT 32 768 POINT DATA RECORD 0 z 0 fci 65MHz 8 65 00352MHz 8 65 00352MHz 8 710 fy 3 00125MHz 13 10 fin 32 40058MHz 18 fin 70 00852MHz 7 20 A 048dBFS 4 20 Aw 04p4dBFS 46 An 0 4980BFS 46 30 SNR 74 4508 30 SNR 74 7708 SNR 74 4108 SINAD 74 33dB Bu SINAD 74 6208 SINAD 74 00dB THD 90 06dBc Es THD 87 22dBc THD 84 50dBc a 50 SFDR 92 47dBc ur 50 SFDR 91 88dBc ui SFDR 86 25dBc ea p 60 p 60 2 zd 70 10 z Mni 60 0 90 90 100 100 110 110 120 120 0 5 10 15 20 25 30 0 5 10 1 20 25 30 0 5 0 15 20 25 30 ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY MHz ANALOG INPUT FREQUENCY AVLAZCLAVI 7 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC Vpp 3 3 OVpp 2 0V GND 0 REFIN R Typical Operating Characteristics continued EFOUT internal reference mode 5pF at digital outputs ViN 0 5dBFS
10. 3 x fiN1 fIN2 3 x fIN2 fiN1 2 X fIN1 2 X fIN2 2 x flN1 2 x fiN2 2xfiN2 2 x 5th Order Intermodulation Products IM5 3 x fIN1 2 X fIN2 3 X fIN2 2 X fIN1 3 x fiN1 2 x fIN2 3 x fIN2 2 X fIN1 4 X fiN1 fiN2 4 x fiN2 4 x fiN1 fiN2 4 x fiN2 3rd Order Intermodulation IM3 is the total power of the 3rd order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones and The individual input tone levels are at 7dBFS The 3rd order intermodulation products are 2 x fIN1 fIN2 2 x fiN2 fIN1 2 x fiN1 fIN2 2 x fiN2 fiN1 Aperture Jitter Figure 14 shows the aperture jitter tAJ which is the sample to sample variation in the aperture delay 26 ER VM RECTO PUT 3JM ii ta LED _ HOLD TRACK Figure 14 T H Aperture Timing Aperture Delay Aperture delay tap is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken Figure 14 Full Power Bandwidth A large 0 2aBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3aB This point is defined as the full power input bandwidth frequency Output Noise nouT The output noise nOUT parameter is similar
11. User Selectable DIV2 and DIV4 Clock Modes Power Down Mode CMOS Outputs in Two s Complement or Gray Code Out of Range and Data Valid Indicators Small 68 Pin Thin QFN Package 12 Bit Compatible Version Available MAX12527 Evaluation Kit Available Order MAX12557 EV Kit 9 9 9 9 9 9 9 9 Ordering Information PART TEMP RANGE PIN PACKAGE 68 Thin QFN EP Meteo 10mm x 10mm x 0 8mm 40 C to 85 C Exposed paddle Selector Guide SAMPLING RATE Msps RESOLUTION PART its MAX12557 65 14 Pin Configuration appears at end of data sheet Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC ABSOLUTE MAXIMUM RATINGS 0 3V to 3 6V DIFFCLK SECLK G T PD SHREF DIV2 OV 0 3V to the lower of Vpp 0 3V and 3 6V DIVA to GND 0 3V to the lower of Vpp 0 3V and 3 6V NAP INAN to GND 0 3V to the lower of Vpp 0 3V and 3 6V DOA D13A DOB D13B DAV INBN to GND 0 3V to the lower of Vpp 0 3V and 3 6V DORA DORB to 0 3V to OVpp 0 3V CLKP CLKN to Continuous Power Dissipation Ta 70 C GND nae 0 3V to the lower of Vpp 0 3V and 3 6V 68 Pin Thin QFN 10mm x 10mm x 0 8mm REFIN REF
12. improve the IN P MAXIM MAX12557 MINICIRCUITS TT1 6 OR TWAT Figure 9 Transformer Coupled Input Drive for Inout Frequencies Up to Nyquist ADT1 1WT overall distortion The configuration of Figure 9 is good for frequencies up to Nyquist fCLK 2 The circuit of Figure 10 converts a single ended input signal to fully differential just as Figure 9 However Figure 10 utilizes an additional transformer to improve the common mode rejection allowing high frequency signals beyond the Nyquist frequency A set of 75Q and 113Q termination resistors provide an equivalent 50Q termination to the signal source The second set of termination resistors connects to COM providing the correct input common mode voltage Two resistors in series with the analog inputs allow high IF input fre quencies These 0Q resistors can be replaced with low value resistors to limit the input bandwidth Single Ended AC Coupled Input Signal Figure 11 shows an AC coupled single ended input application The MAX4108 provides high speed high bandwidth low noise and low distortion to maintain the input signal integrity MAXIM MAX4108 AVLAXLAVIA MAX12557 Figure 11 Single Ended AC Coupled Input Drive MINICIRCUITS MINICIRCUITS ADT1 1WT IN P MAXIM MAX12557 00 RESISTORS CAN REPLACED WITH LOW VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH Figure 10 Transformer Coupled Inpu
13. output data format is either Gray code Data Out of Range Indicator or two s complement depending on the logic input G T The DORA and DORB digital outputs indicate when the With G T high the output data format is Gray code analog input voltage is out of range When DOR is high With G T low the output data format is set to two s com the analog input is out of range When DOR_ is low the plement See Figure 8 for a binary to Gray and Gray to analog input is within range The valid differential input binary code conversion example range is from VREF P VREF_N x 2 3 to VREF_N The following equations Table 3 Figure 6 and Figure 7 VREF P x 2 3 Signals outside of this valid differential define the relationship between the digital output and range cause DOR to assert high as shown in Table 1 the analog input DOR is synchronized with DAV and transitions along Gray Code G T 1 with the output data D13 DO There is an 8 clock cycle VIN P VIN N 2 3 x VREF P VREF_N X2x latency in the DOR function as is with the output data T A CODE10 8192 16 384 Figure 5 DOR is high impedance when the MAX12557 is in power down PD high DOR enters Two s Complement G T 0 a high impedance state within 10ns after the rising edge VIN P VIN N 2 3 x VREF VREF_N X2 of PD and becomes active 10ns after PD s falling edge CODE10 16 384 Digital Output Data and Output Format Selection where
14. scale transition occurs at 0 5 LSB above negative full scale The gain error is the difference of the measured transition points minus the difference of the ideal transition points Small Signal Noise Floor SSNF SSNF is the integrated noise and distortion power in the Nyquist band for small signal inputs The DC offset is excluded from this noise calculation For this converter a small signal is defined as a single tone with a 35dBFS amplitude This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise fig ure of a digital receiver signal path Signal to Noise Ratio SNR For a waveform perfectly reconstructed from digital samples the theoretical maximum SNR is the ratio of the full scale analog input RMS value to the RMS quantization error residual error The ideal theoretical minimum analog to digital noise is caused by quantiza tion error only and results directly from the ADC s reso lution N bits SNR max 6 02 1 76 In reality there are other noise sources besides quanti zation noise thermal noise reference noise clock jitter etc SNR is computed by taking the ratio of the RMS signal to the RMS noise RMS noise includes all spec tral components to the Nyquist frequency excluding the fundamental the first six harmonics HD2 through HD7 and the DC offset SNR 20 log SIGNAL NOISERMS Signal to Noi
15. 0 15 10 35 60 85 40 15 10 35 60 85 TEMPERATURE C TEMPERATURE C AVLAXLAO 11 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC PIN Pin Description FUNCTION 1 4 5 9 18 14 17 Converter Ground Connect all ground pins and the exposed paddle EP together Channel A Positive Analog Input Channel A Negative Analog Input Channel Common Mode Voltage I O Bypass COMA to GND with a 0 1uF capacitor Channel A Positive Reference I O Channel A conversion range is 2 3 x VREFAP VREFAN Bypass REFAP with a 0 1uF capacitor to GND Connect a 10uF and a 1uF bypass capacitor between REFAP and REFAN Place the 1 REFAP to REFAN capacitor as close to the device as possible on the same side of the PC board Channel A Negative Reference I O Channel A conversion range is 2 3 x VREFAP VREFAN Bypass REFAN with a 0 1uF capacitor to GND Connect a 10uF and a 1 bypass capacitor between REFAP and REFAN Place the 1 REFAP to REFAN capacitor as close to the device as possible on the same side of the PC board COMB Channel B Negative Reference I O Channel B conversion range is 2 3 x VREFBP VREFBN Bypass REFBN with a 0 1uF capacitor to GND Connect a 10uF and a 1 bypass capacitor between REFBP and REFBN Place the 1 REFBP to REFBN capacitor as close to the device as possible on the same side of the PC board Channel B Positive Reference I O Channel B convers
16. CS fina or fing 70MHz at 0 5dBFS fiNA or fiNB 175MHz at 0 5aBFS Crosstalk Rejection in Matching set Matching INTERNAL REFERENCE REFOUT FOUT Output Voltage Vacrour 2000 2048 2080 v FOUT Load Regulation 1mA lt IREFOUT lt 1 35 mV mA 50 Short to Vpp sinking 0 24 Short to GND sourcing 2 1 BUFFERED REFERENCE MODE REFIN is driven by REFOUT or an external 2 048V single ended reference source VnEFAP VnErFAN VcoMA and VngrBP VnErFBN VCONMB are generated internally EFIN Input Voltage VREFIN EFIN Input Resistance RREFIN FOUT Temperature Coefficient TCREF mA EFOUT Short Circuit Current VCOMA COM Output Voltage SUNT VCOMB 2 VREFAP V DD 2 VREFIN x 3 8 REFBP EF P Output Voltage t VREFAN EF N Output Voltage 2 V x 3 8 p g SEHEN DD VREFIN REFA VREFAP VREFAN 1536 1580 REFB VREFBP VREFBN ifferential Reference Voltage ifferential Reference Temperature Coefficient UNBUFFERED EXTERNAL REFERENCE REFIN GND VnErAP VnErFAN VcoMA and VngrBP VnErFBN VCONB are applied externally Vcoma 2 x25 VREFAP P Input Voltage SPP VREFBP VREF P VCOM VREFAN VREFBN COM Input Voltage VCOM Vpp 2 Differential Reference Voltage VREF_ VREF P VREF_N VREFIN X 3 4 1 536 EX 4 MAXIM EF_N Input Voltage VREF_N VCOM Dual 65Msps 14 Bit
17. DD 2 3 8 x VREFIN REF N Vpp 2 3 8 x VREFIN Buffered External Reference Mode An external 0 7 to 2 3V reference voltage is applied to REFIN _ 0 2 VnEr P VDD 2 3 8 x VREFIN VREF_N 2 3 8 x VREFIN 0 7V to 2 3V Unbuffered External Reference Mode REF P REF N and COM are driven by external reference sources The full scale analog input range is VREF_P VREF x 2 8 MAX12557 The power down logic input PD enables and disables the reference circuit REFOUT has approxi mately 17kO to GND when the MAX12557 is powered down The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12557 or when PD transitions from high to low The internal bandgap reference produces a buffered reference voltage of 2 048V 1 at the REFOUT with a 50 temperature coefficient Connect an external 20 1uF bypass capacitor from REFOUT to GND for stability REFOUT sources up to 1mA and sinks up to 0 1mA for external circuits with a 35mV mA load regulation Short circuit protection limits IREFOUT to a 2 1mA source current when shorted to GND and a 0 24mA sink current when shorted to Vpp Similar to REFOUT REFIN should be bypassed with a 4 7uF capacitor to GND Reference Configurations The MAX12557 full scale analog input range is 2 3 x VREF with a Vpp 2 0 5V common mode input range VREF is the voltage difference
18. FEATURE DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 25mm AND 0 30mm FROM TERMINAL TIP ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY 7 DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS DDALLAS 9 DRAWNG CONFORMS TO JEDEC MO 220 10 WARPAGE SHALL NOT EXCEED 0 10mm MLG PACKAGE OUTLINE 68L THIN QFN 10x10x0 8mm TOCUENT CONTROL Mi 21 0142 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 28 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products Printed USA MAXIM is registered trademark of Maxim Integrated Products Inc
19. IN to GND deactivates the on chip reference buffers for COM REF P and REF With their buffers deactivated COM REF P and REF become high impedance inputs and must be driven with separate external reference sources Drive Vcom_ to Vpp 2 596 and drive REF P and REF N so VCOM P VREF N 2 The analog input range is VREF P VREF_N x 2 3 Bypass REF P REF and COM each with a 0 1uF capacitor to GND Bypass REF P to REF N with a 1OuF capacitor For all reference modes bypass REFOUT with O 1uF and REFIN with a 4 7uF capacitor to GND The MAX12557 also features a shared reference mode in which the user can achieve better channel to chan nel matching When sharing the reference SHREF VDD externally connect REFAP and REFBP together to ensure that VREFAP VREFBP Similarly when sharing the reference externally connect REFAN to REFBN together to ensure that VREFAN VREFBN Connect SHREF to GND to disable the shared refer ence mode of the MAX12557 In this independent refer ence mode a better channel to channel isolation is achieved For detailed circuit suggestions and how to drive the ADC in buffered unbuffered external reference mode see the Applications Information section Clock Duty Cycle Equalizer The MAX12557 has an internal clock duty cycle equaliz er which makes the converter insensitive to the duty cycle of the signal applied to CLKP and CLKN The con vert
20. K30 2 MAXIM MAX4230 52 3kQ MAXIM MAX12557 1 52 3kQ 1 147kQ 4230 Figure 13 External Unbuffered Reference Driving Multiple ADCs ence allowing REF P REF N and COM to be driven directly by a set of external reference sources Figure 13 uses a MAX6029 precision 3 000V bandgap reference as a common reference for multiple convert ers A seven component resistive divider chain follows the MAX6029 voltage reference The 0 47uF capacitor along this chain creates a 10Hz LP filter Three MAX4230 amplifiers buffer taps along this resistor chain providing 2 413V 1 647V and 0 880V to the MAX12557 REF P REF N and COM reference inputs The feedback around the MAX4230 op amps provides additional 10Hz LP filtering Reference volt ages 2 413V and 0 880 set the full scale analog input 24 REFOUT MAXIM MAX12557 REF_N 10WF pF I iP range for the converter to 1 022V x VnEF P 1 x 2 3 Note that one single power supply for all active circuit components removes any concern regarding power supply sequencing when powering up or down Grounding Bypassing and Board Layout The MAX12557 requires high speed board layout design techniques Refer to the MAX12557 EV kit data sheet for a board layout reference Locate all bypass cap
21. MPLITUDE SNR SINAD vs CLOCK SPEED fck 65 00352MHz fiy 175MHz 65 00352MHz fiy 175MHz fin 70MHz 0 5dBFS 80 95 z i m E i 70 4 85 E E g 0 SINAD g 15 2 2 50 5 65 e 5 T 5 30 45 20 35 55 50 45 40 35 30 25 20 45 10 5 0 55 50 45 40 35 30 25 20 15 10 5 0 20 25 30 35 40 45 50 55 60 65 Ain dBFS dBFS MHz THD SFDR vs CLOCK SPEED SNR SINAD vs CLOCK SPEED THD SFDR vs CLOCK SPEED fin 70MHz Ajy 0 5dBFS fin 175MHz 0 5dBFS fin 175MHz 0 5dBFS 90 80 90 z 85 12 76 E 85 E 8 S 80 2 3 S 5 5 5 15 S 68 92 65 65 60 60 60 20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65 MHz MHz MHz SNR SINAD vs ANALOG SUPPLY VOLTAGE THD SFDR vs ANALOG SUPPLY VOLTAGE SNR SINAD vs ANALOG SUPPLY VOLTAGE 65 00352MHz fiy 70MHz 65 00352MHz fiy 70MHz 65 00352MHz fiy 175MHz 80 2 95 8 75 8 76 3 72 3 _ 85 2 72 a S 69 e a 68 S C 66 gt E gt 70 64 63 65 60 60 60 30 31 32 33 34 35 36 30 31 32 33 34 35 36 30 31 32 33 34 35 36 Voo V Vpp V Vpp V MAALM 9 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC 85 THD SFDR vs ANALOG SUPPLY VOLTAGE 65 00352MHz fin 175MHz MAX12557 toc22 Typical Op
22. OUT derate 7OmMW C above 70 4000mW to GND 2 0 3V to the lower of Vpp 0 3V and 3 6V Operating Temperature Range 740 C to 85 REFAP REFAN Junction Temperature 150 C COMA to GND 0 3V to the lower of Vpp 0 3V and 3 6V Storage Temperature Range 65 C to 150 REFBP REFBN Lead Temperature Soldering 105 300 C COMB to GND 0 3V to the lower of Vpp 0 3V and 3 6V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference 10pF at digital outputs Vin 0 5dBFS differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND G T GND 65MHz TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS DC ACCURACY Resolution Integral Nonlinearity fin 3MHz fin 3MHz no missing codes over Differential Nonlinearity t
23. TERISTICS continued Vpop 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference 10pF at digital outputs 0 5dBFS differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND GND 65MHz TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS MAX TIMING CHARACTERISTICS Figure 5 Clock Pulse Width High CH Clock Pulse Width Low CL Data Valid Delay tDAV Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake Up Time from Power Down tWAKE VREFIN 2 048V tsETUP Note 6 tHoLD Note 6 Note 1 Specifications gt 25 guaranteed by production test lt 25 C guaranteed by design and characterization Note 2 Guaranteed by design and characterization Device tested for performance during product test Note 3 Specification guaranteed by production test for gt 25 Note 4 Two tone intermodulation distortion measured with respect to a single carrier amplitude and not the peak to average input power of both input tones Note 5 During power down DOA D13A DOB D13B DORA DORB and DAV are high impedance Note 6 Guaranteed by design and characterization Typical Operating Characteristics Vpp 3 3V OVpp 2 0V GND 0 REFIN REFOUT internal reference mode 5pF at digital outputs ViN 0 5dBFS DIFFCLK SECLK OVpp
24. ach pipeline stage and through the pipeline stages every half clock cycle From input to output the total latency is 8 clock cycles 2 14 AVLAZCLAVI DIFFCLK SECLK CLKP CLKN Dual 65Msps 14 Bit IF Baseband ADC 14 BIT M gt PIPELINE ADC DIGITAL ERROR CORRECTION DATA FORMAT OUTPUT DRIVERS HANNEL A EFERENCE SYSTEM CHANNEL B REFERENCE SYSTEM MAXIM MAX12557 INTERNAL REFERENCE GENERATOR Y 14 BIT gt PIPELINE ADC DIGITAL ERROR CORRECTION DATA FORMAT OUTPUT DRIVERS CLOCK DIVIDER DUTY CYCLE EQUALIZER Figure 2 Functional Diagram AVLAZCLAVI POWER CONTROL AND BIAS CIRCUITS D0A TO D13A DORA D0B TO D13B DORB 15 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC BOND WIRE INDUCTANCE 1 5nH MAALWVI MAX12557 Cran x j 5r BOND WIRE INDUCTANCE Cpar L CSAMPLE 4 5pF SAMPLING CLOCK THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS Rin fci X SAMPLE Figure 3 Internal T H Circuit Analog Inputs and Input Track and Hold T H Amplifier Figure 3 displays a simplified functional diagram of the input T H circuit This input T H circuit allows for high analog input frequencies of 175MHz and beyond and supports a Vpp 2 common mode input voltag
25. acitors as close to the device as possible prefer ably on the same side as the ADC using surface AVLAZCLAVI Dual 65Msps 14 Bit IF Baseband ADC mount devices for minimum inductance Bypass Vpp to GND with a 220yF ceramic capacitor in parallel with at least one 10pF one 4 7uF and one 0 1uF ceramic capacitor Bypass OVpp to GND with a 220uF ceramic capacitor in parallel with at least one 10pF one 4 7yF and one 0 1uF ceramic capacitor High frequency bypassing decoupling capacitors should be located as close as possible to the converter supply pins Multilayer boards with ample ground and power planes produce the highest level of signal integrity All grounds and the exposed backside paddle of the MAX12557 must be connected to the same ground plane The MAX12557 relies on the exposed backside paddle con nection for a low inductance ground connection Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground Route high speed digital signal traces away from the sensitive analog traces Keep all signal lines short and free of 90 turns Ensure that the differential analog input network layout is symmetric and that all parasitic components are bal anced equally Refer to the MAX12557 EV kit data sheet for an example of symmetric input layout Parameter Definitions Integral Nonlinearity INL INL is the deviation of the values on an actual transfer function from a str
26. aight line For the MAX12557 this straight line is between the endpoints of the transfer function once offset and gain errors have been nullified INL deviations are measured at every step of the transfer function and the worst case deviation is reported in the Electrical Characteristics table Differential Nonlinearity DNL DNL is the difference between an actual step width and the ideal value of 1 LSB A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function For the MAX12557 DNL deviations are measured at every step of the transfer function and the worst case deviation is reported in the Electrical Characteristics table Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point Ideally the midscale MAX12557 transition occurs at 0 5 LSB above mid scale The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point MAXIM Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function The slope of the actual transfer function is measured between two data points positive full scale and negative full scale Ideally the positive full scale MAX12557 transition occurs at 1 5 LSBs below pos itive full scale and the negative full
27. between REFAP REFBP and REFAN REFBN The MAX12557 provides three modes of reference operation The voltage at REFIN VREFIN selects the reference operation mode Table 1 Connect REFOUT to REFIN either with a direct short or through a resistive divider to enter internal reference mode COM REF P and REF are low impedance outputs with VCOM VDD 2 VREFP VDD 2 3 8 x VREFIN and VREF_N VDD 2 3 8 x VREFIN Bypass REF P REF and COM each with a O 1uF capacitor MAXIM Dual 65Msps to GND Bypass REF P to REF N with a 10uF capacitor Bypass REFIN and REFOUT to GND with a O 1uF capac itor The REFIN input impedance is very large gt 50MQ When driving REFIN through a resistive divider use resistances gt 10 to avoid loading REFOUT Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12557 s internal bandgap reference In buffered external reference mode apply a stable reference volt age source between 0 7V to 2 3V at REFIN Pins COM REF P and REF N are low impedance outputs with VCOM 2 VREF P VDD 2 3 8 x VREFIN and VREF N VoD 2 3 8 x VREFIN Bypass REF P REF and COM each with a O 1uF capacitor to GND Bypass REF P to REF N with a 10uF capacitor Connect REFIN to GND to enter unbuffered external ref erence mode Connecting REF
28. e MAX12557 sampling clock controls the switched capacitor input T H architecture Figure 3 allowing th analog input signals to be stored as charge on th sampling capacitors These switches are closed trac mode when the sampling clock is high and open ho mode when the sampling clock is low Figure 4 Th analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors To avoid signal degradation these capacitors must be charged to one half LSB accuracy within one half of a clock cycle The analog input of the MAX12557 supports differential or single ended input drive For optimum performance with dif ferential inputs balance the input impedance of IN P and and set the common mode voltage to mid supply Vpp 2 The MAX12557 provides the optimum common mode voltage of Vpp 2 through the COM output when operating in internal reference mode and buffered external reference mode This COM output voltage can be used to bias the input network as shown in Figures 9 10 and 11 Reference Output An internal bandgap reference is the basis for all the internal voltages and bias currents used in the 16 Table 1 Reference Modes VREFIN REFERENCE MODE nternal Reference Mode REFIN is driven by REFOUT either through a direct short or a resistive divider Vcom_ VDD 2 V V 35 VREFOUT to 10096 V REFOUT P V
29. emperature Note 2 Gain Error ANALOG INPUT INAP INAN INBP INBN Differential Input Voltage Range VDIFF Differential or single ended inputs Common Mode Input Voltage Analog Input Resistance RIN Each input Figure 3 Analog Input Capacitance Switched capacitance CSAMPLE each input Figure 3 CONVERSION RATE Maximum Clock Frequency CLK Minimum Clock Frequency Data Latency Figure 5 DYNAMIC CHARACTERISTICS differential inputs Small Signal Noise Floor SSNF Input at 35dBFS fin 3MHz at 0 5dBFS fin 32 5 2 at 0 5dBFS fin 70MHz at 0 5dBFS fin 175MHz at 0 5dBFS Signal to Noise Ratio 2 MAXIM Dual 65Msps 14 Bit IF Baseband ADC ELECTRICAL CHARACTERISTICS continued Vpop 3 3 OVpp 2 0V GND 0 REFIN REFOUT internal reference 10pF at digital outputs Vin 0 5aBFS differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND G T GND 65MHz TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS Hz at 0 5dBFS Note 3 5MHz at 0 5dBFS Hz at 0 5dBFS 175MHz at 0 5dBFS 3MHz at 0 5dBFS Note 3 32 5MHz at 0 5dBFS 70MHz at 0 5dBFS 175MHz at 0 5dBFS z at 0 5dBFS Note 3 84 5 74 5 Hz at 0 5aBFS 80 7 z at O 5dBFS 81 7 Hz at 0 5dBFS 78 3 at 0 5dBFS 89 5 Hz at 0 5aBFS 84 2 70MHz at 0 5dBFS
30. er supply Bypass Vpp to GND with a parallel capacitor combination of 210uF and O 1uF Connect all Vpp pins to the same potential 27 43 60 12 Output Driver Power Input Connect OVpp to a 1 7V to Vpp power supply Bypass OVpp to GND with parallel capacitor combination of gt 10 and O 1uF MAXIM Dual 65Msps 14 Bit IF Baseband ADC Pin Description continued FUNCTION B CMOS Digi g B CMOS Digi g D2B Channel B CMOS Digital Output Bit 2 B CMOS Digi B CMOS Digi B CMOS Digi B CMOS Digi B CMOS Digi B CMOS Digi it 9 B CMOS Digi it 10 B CMOS Digi it 11 p p p p p p B CMOS Digi p p p p p p p B B B B B B B B B B B B B CMOS Digi it 12 B CMOS Digi put Bit 13 MSB Channel B Data Out of Range Indicator The DORB digital output indicates when the channel B analog input voltage is out of range DORB 1 Digital outputs exceed full scale range DORB 0 Digital outputs are within full scale range Data Valid Digital Output The rising edge of DAV indicates that data is present on the digital outputs The MAX12557 evaluation kit utilizes DAV to latch data into any external back end digital logic Channel A CMOS Digital Output Bit O LSB Channel A CMOS Digi Channel A CMOS Digi Channel A CMOS Digi p p p Channel A CMOS Digi Channel A CMOS Digi Channel A CMOS Digi C
31. erating Characteristics continued Vpp 3 3V OVpp 2 0V GND 0 REFIN R DIFFCLK SECLK OVpp PD GND G T GND 65MHz 50 duty cycle TA 25 C unless otherwise noted 80 SNR SINAD vs DIGITAL SUPPLY VOLTAGE 65 00352MHz fiy 70MHz 12557 toc23 80 76 75 Z0 a 70 68 wn 65 64 60 60 30 31 32 33 34 35 36 15 18 21 24 27 30 33 36 Voo V OVpp V SNR SINAD vs DIGITAL SUPPLY VOLTAGE THD SFDR vs DIGITAL SUPPLY VOLTAGE 65 00352MHz fin 175MHz 65 00352MHz fiy 175MHz 75 s 80 8 72 E 76 E 2 8 2m id 6 68 63 64 60 60 15 18 21 24 27 30 33 36 15 18 21 24 27 30 33 36 OVpp V OVpp V Poiss lovon DIGITAL vs DIGITAL SUPPLY VOLTAGE SNR SINAD vs CLOCK DUTY CYCLE fcLk 65 00352MHz fin 175MHz fin 70MHz Ajy 0 5dBFS i 3 3 70 3 3 60 ea 50 5 2 40 5 e 9 2 90 10 SINGLE ENDED CLOCK DRIVE 0 15 18 21 24 27 30 33 36 25 35 45 55 65 75 OVpp V CLOCK DUTY CYCLE 96 10 THD SFDR dBc Poiss ANALOG vs ANALOG SUPPLY VOLTAGE EFOUT internal reference mode 5pF at digital outputs VIN 0 5dBFS THD SFDR vs DIGITAL SUPPLY VOLTAGE 65 00352MHz 70MHz
32. ers allow clock duty cycle variations from 25 to 7596 without negatively impacting the dynamic performance MAXIM 14 Bit IF Baseband ADC The clock duty cycle equalizer uses a delay locked loop DLL to create internal timing signals that are duty cycle independent Due to this DLL the MAX12557 requires approximately 100 clock cycles to acquire and lock to new clock frequencies Clock Input and Clock Control Lines The MAX12557 accepts both differential and single ended clock inputs with a wide 25 to 75 input clock duty cycle For single ended clock input operation connect DIFFCLK SECLK and CLKN to GND Apply an external single ended clock signal to CLKP To reduce clock jitter the external single ended clock must have sharp falling edges For differential clock input opera tion connect DIFFCLK SECLK to OVpp Apply an external differential clock signal to CLKP and CLKN Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines CLKP and CLKN enter high impedance when the MAX12557 is powered down Figure 4 Low clock jitter is required for the specified SNR perfor mance of the MAX12557 The analog inputs are sam pled on the falling rising edge of CLKP CLKN requiring this edge to have the lowest possible jitter Jitter limits the maximum SNR performance of any ADC according to the following relationship SNR 20 x log 1 2x TX N x ty where fin represe
33. g edge of DAV to 7ns after the rising edge of DAV enters high impedance when the 12557 is powered down PD OVpp DAV enters its high impedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low DAV is capable of sinking and sourcing 600 and has three times the driving capabilities of DOA B D13A B and DORA B DAV is typically used to latch the MAX12557 output data into an external digital back end circuit Keep the capacitive load on DAV as low as possi ble 15pF to avoid large digital currents feeding back into the analog portion of the MAX12557 thereby degrading its dynamic performance Buffering DAV Vngr p VREF_N X 2 3 N 3 N 2 Ned N42 Vngr Ver 2 3 E 1 CLKN I CLKP FUN w V E ET V Ed or ey fu wm og Jp i L 2 N fuer Ne2 nea Nos DOR ad 8 0 CLOCK CYCLE DATA LATENCY 9 SETUP Figure 5 System Timing Diagram 18 MAXIM Dual 65Msps 14 Bit IF Baseband ADC externally isolates it from heavy capacitive loads Refer the falling edge of DAV and are valid on the rising edge to the MAX12557 EV kit schematic for recommendations of DAV of how to drive the DAV signal through an external buffer The MAX12557
34. gnal is applied to both channels and the maximum deviation in offset is reported typically in FSR as offset matching MAXIM MAX12557 EXPOSED PADDLE GND DIFFCLK SECLK amp 1 AVLAZCLAVI 27 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC Package Information The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages A 2X e orsIc 4 102 68L QFN THIN EPS 77 Na 1 Xe Ref BOTTOM VIEW DETAIL A R 15 OPTIONAL o E Led rene Le PALAS AVL AXIA EVEN TERMINAL 000 TERMINAL SRR TA M DRHTON MLG PACKAGE OUTLINE 68L THIN QFN 10x10x0 8mm Pk 68L 10 10 y er ww wow wax KG 070 0 75 080 xcu pin re on 0 20 REF 760 020 025 9 90 10 00 1010 050 BSC 0 25 0 45 055 065 JEDEC WNND 2 NOTES 1 DIMENSIONING TOLERANCING CONFORM TO ASME 14 5 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS ANGLES ARE IN DEGREES 3 N 15 THE TOTAL NUMBER OF TERMINALS A THE TERMINAL 1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95 1 5 012 DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED THE TERMINAL 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED
35. hannel A CMOS Digi Channel A CMOS Digi g g g Channel A CMOS Digi g g Channel A CMOS Digi p p p p p p p p p p 9 9 Channel A CMOS Digi Channel A CMOS Digi Channel A CMOS Digi Bit 13 MSB Channel A Data Out of Range Indicator The DORA digital output indicates when the channel A analog input voltage is out of range DORA z 1 Digital outputs exceed full scale range DORA Digital outputs are within full scale range MAXIM Output Format Select Digital Input G T GND Two s complement output format selected G T OVpp Gray code output format selected 13 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC Pin Description continued FUNCTION Power Down Digital Input PD GND ADCs are fully operational PD OVpp ADCs are powered down Shared Reference Digital Input SHREF Vpp Shared reference enabled SHREF GND Shared reference disabled When sharing the reference externally connect REFAP and REFBP together to ensure that VREFAP VREEBP Similarly when sharing the reference externally connect REFAN to REFBN together to ensure hat VREFAN VREFBN nternal Reference Voltage Output The REFOUT output voltage is 2 048V and REFOUT can deliver 1mA or internal reference operation connect REFOUT directly to REFIN or use a resistive divider from REFOUT EFOUT to set the voltage at REFIN Bypass REFOUT
36. ion range is 2 3 x VREFBP VREFBN Bypass REFBP with a 0 1uF capacitor to GND Connect a 10uF and a 1uF bypass capacitor between REFBP and REFBN Place the 1 REFBP to REFBN capacitor as close to the device as possible on the same side of the PC board Channel Common Mode Voltage I O Bypass COMB to GND with a 0 1uF capacitor INBN Channel B Negative Analog Input INBP Channel B Positive Analog Input DIFFCLK SECLK Differential Single Ended Input Clock Drive This input selects between single ended or differential clock input drives DIFFCLK SECLK GND Selects single ended clock input drive DIFFCLK SECLK OVpp Selects differential clock input drive 21 egative Clock Input In differential clock input mode DIFFCLK SECLK OVpp connect a differential clock signal between CLKP and CLKN In single ended clock mode DIFFCLK SECLK GND apply he clock signal to CLKP and connect CLKN to GND Positive Clock Input In differential clock input mode DIFFCLK SECLK OVpp connect a differential clock signal between CLKP and CLKN In single ended clock mode DIFFCLK SECLK GND apply he single ended clock signal to CLKP and connect CLKN to GND Divide by Two Clock Divider Digital Control Input See Table 2 for details 22 Divide by Four Clock Divider Digital Control Input See Table 2 for details 23 26 61 62 63 Analog Power Input Connect Vpp to a 3 15V to 3 60V pow
37. mplified Clock Input Circuit select either one half or one fourth of the clock speed for sampling provides design flexibility relaxes clock requirements and can minimize clock jitter System Timing Requirements Figure 5 shows the timing relationship between the clock analog inputs DAV indicator DOR indicators and the resulting output data The analog input is sam pled on the falling rising edge of CLKP CLKN and the resulting data appears at the digital outputs 8 clock cycles later The DAV indicator is synchronized with the digital out put and optimized for use in latching data into digital back end circuitry Alternatively digital back end cir DIFFERENTIAL ANALOG INPUT IN Table 2 Clock Divider Control Inputs FUNCTION Clock Divider Disabled SAMPLE Divide by Two Clock Divider SAMPLE fCLK 2 Divide by Four Clock Divider fSAMPLE fcLK 4 Not Allowed cuitry can be latched with the rising edge of the con version clock CLKP CLKN Data Valid Output DAV is a single ended version of the input clock that is compensated to correct for any input clock duty cycle variations The MAX12557 output data changes on the falling edge of DAV and DAV rises once the output data is valid The falling edge of DAV is synchronized to have a 5 4ns delay from the falling edge of the input clock Output data at DOA B D13A B and DORA B valid from 7ns before the risin
38. ning to a low power state when conversions are not required Additionally the MAX12557 parallel output bus goes high impedance in power down mode allowing other devices on the bus to be accessed 20 1 LSB 4 3 x VngrN 16 384 H 2 3 x VREFP VREFN t 2 3 x Vnerp VREFN lt 0x2000 0x2001 0x2003 0x3001 0x3000 0x1000 GRAY OUTPUT CODE LSB 8191 8189 10 8189 8191 DIFFERENTIAL INPUT VOLTAGE LSB Figure 7 Gray Code Transfer Function G T 1 In power down mode all internal circuits are off the analog supply current reduces to less than 5 and the digital supply current reduces to 1pA The following list shows the state of the analog inputs and digital out puts in power down mode 1 INAP B INAN B analog inputs are disconnected from the internal input amplifier Figure 3 2 REFOUT has approximately 17kO to GND 3 REFAP B REFAN B enter a high imped ance state with respect to and GND but there is an internal 4 resistor between REFAP B and COMA B as well as an internal 4kQ resistor between REFAN B and COMA B 4 DOA D13A DOB D13B DORA and DORB enter high impedance state 5 DAV enters a high impedance state 6 CLKP CLKN clock inputs enter a high impedance state Figure 4 The wake up time from power down mode is dominated by the time required to charge the capacitors at REF P REF and COM In internal reference mode buffe
39. ns in the clock duty cycle are compensated with the ADC s internal duty cycle equalizer DCE The MAX12557 features two parallel 14 bit wide CMOS compatible outputs The digital output format is pin selectable to be either two s complement or Gray code A separate power supply input for the digital out puts accepts a 1 7V to 3 6V voltage for flexible interfac ing with various logic levels The 12557 is available in a 10mm x 10mm x 0 8mm 68 pin thin QFN package with exposed paddle EP and is specified for the extended 40 C to 85 temperature range For a 12 bit pin compatible version of this ADC refer to the MAX12527 data sheet Applications IF and Baseband Communication Receivers Cellular LMDS Point to Point Microwave MMDS HFC WLAN Receivers Ultrasound and Medical Imaging Portable Instrumentation Digital Set Top Boxes Low Power Data Acquisition MAKIM MAAIM Dual 65Msps 14 Bit IF Baseband ADC Features Direct IF Sampling Up to 400MHz Excellent Dynamic Performance 74 1dB 72 5dB SNR at fin 70MHz 175MHz 83 4dBc 79 5dBc SFDR at fin 70MHz 175MHz 3 3V Low Power Operation 637mW Differential Clock Mode 610mW Single Ended Clock Mode Fully Differential or Single Ended Analog Input Adjustable Differential Analog Input Voltage 750MHz Input Bandwidth Adjustable Internal or External Shared Reference Differential or Single Ended Clock Accepts 25 to 75 Clock Duty Cycle
40. nts the analog input frequency and ty is the total system clock jitter Clock jitter is especially critical for undersampling applications For instance assuming that clock jitter is the only noise source to obtain the specified 72 5dB of SNR with an input fre quency of 175MHz the system must have less than 0 21 5 of clock jitter However in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0 14ps to obtain the speci fied 72 5dBc of SNR at 175MHz Clock Divider Control Inputs DIV2 DIV4 The MAX12557 features three different modes of sam pling clock operation see Table 2 Pulling both control lines low the clock divider function is disabled and the converters sample at full clock speed Pulling DIVA low and DIV2 high enables the divide by two feature which sets the sampling speed to one half the selected clock frequency In divide by four mode the converter sam pling speed is set to one fourth the clock speed of the MAX12557 Divide by four mode is achieved by applying a high level to DIVA and a low level to DIV2 The option to 17 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC MAXIM MAX12557 DUTY CYCLE EQUALIZER 10kQ SWITCHES 51 AND 5 ARE OPEN DURING POWER DOWN MAKING CLKP AND CLKN HIGH IMPEDANCE SWITCHES Sp_ ARE OPEN IN SINGLE ENDED CLOCK MODE Figure 4 Sii
41. red external reference mode the wake up time is typically 10ms When operating in the unbuffered exter nal reference mode the wake up time is dependent on the external reference drivers AVLAZCLAVI Dual 65Msps 14 Bit IF Baseband ADC BINARY TO GRAY CODE CONVERSION GRAY TO BINARY CODE CONVERSION 1 THE MOST SIGNIFICANT GRAY CODE BIT 15 THE SAME 1 THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE AS THE MOST SIGNIFICANT BINARY BIT MOST SIGNIFICANT GRAY CODE BIT BIT POSITION Di3 5Dt D7 BIT POSITION BINARY 10 Ale 40 0 11 GRAY CODE 0 l 0 GRAY CODE BINARY 2 SUBSEQUENT GRAY CODE BITS ARE FOUND ACCORDING 2 SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO TO THE FOLLOWING EQUATION THE FOLLOWING EQUATION GRAY BINARY 4 BINARY 1 BINARY BINARY 1 GRAY WHERE IS THE EXCLUSIVE OR FUNCTION SEE TRUTH WHERE IS THE EXCLUSIVE OR FUNCTION SEE TRUTH TABLE BELOW AND X IS THE BIT POSITION TABLE BELOW AND X IS THE BIT POSITION GRAY 2 BINARY12 BINARY 13 BINARY 12 BINARY 13 GRAY 2 GRAY12 14 0 BINARY 12 0 1 GRAY12 1 BINARY 12 1 BIT POSITION BIT POSITION BINARY GRAY CODE GRAY CODE BINARY 3 REPEAT STEP 2 UNTIL COMPLETE 3 REPEAT STEP 2 UNTIL COMPLETE GRAY11 BINARY 1 BINARY42 GRAY 1 GRAY 0 BINARY 1 BINARY 42 X GRAY 11 BINARYs 1 5 0 BINARY 4 1 BIT POSITION BIT POSITION BINARY EU GRAY CODE GRAY CODE BINARY
42. se Plus Distortion SINAD SINAD is computed by taking the ratio of the RMS sig nal to the RMS noise plus distortion RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset 25 ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC Total Harmonic Distortion THD THD is the ratio of the RMS sum of the first six harmon ics of the input signal to the fundamental itself This is expressed as 2 V6 Va Ve V THD 20 x where V1 is the fundamental amplitude and V2 through V7 are the amplitudes of the 2nd through 7th order harmonics HD2 through HD7 Spurious Free Dynamic Range SFDR SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental maximum signal compo nent to the RMS value of the next largest spurious component excluding DC offset Intermodulation Distortion IMD IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones and The individual input tone levels are at 7dBFS The inter modulation products are as follows 2nd Order Intermodulation Products 2 fIN1 fIN2 fiN2 find 3rd Order Intermodulation Products IM3 2 X IN1 fIN2 2 x fiN2 fiN1 2 x fiN1 fiN2 2 X fIN2 fiN1 4th Order Intermodulation Products 4 3 x fiN1 fIN2 3 x fiN2 fIN1
43. seband ADC 1 LSB 4 3 x Vagrp VngrN 16 384 H 2 3 x VREFP VREFN t 2 3 x Vnerp VREFN Ox1FFF Ox1FFE Ox1FFD 0x0001 0x0000 Ox3FFF TWO S COMPLEMENT OUTPUT CODE LSB 8191 8189 10H 8189 8191 DIFFERENTIAL INPUT VOLTAGE LSB Figure 6 Two s Complement Transfer Function G T 0 The digital outputs DOA B D13A B are high impedance when the MAX12557 is in power down PD 1 mode DOA B D13A B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low Keep the capacitive load on the MAX12557 digital out puts DOA B D13A B as low as possible lt 15pF to avoid large digital currents feeding back into the ana log portion of the MAX12557 and degrading its dynam ic performance Adding external digital buffers on the digital outputs helps isolate the MAX12557 from heavy capacitive loads To improve the dynamic performance of the MAX12557 add 2200 resistors in series with the digital outputs close to the MAX12557 Refer to the MAX12557 EV kit schematic for guidelines of how to drive the digital outputs through 2200 series resistors and external digital output buffers Power Down Input The MAX12557 has two power modes that are con trolled with a power down digital input PD With PD low the MAX12557 is in its normal operating mode With PD high the MAX12557 is in power down mode The power down mode allows the MAX12557 to effi ciently use power by transitio
44. t Drive for Input Frequencies beyond Nyquist 22 MAXIM Dual 65Msps 14 Bit IF Baseband ADC REFIN REF P AVAXIL VI MAX12557 MAXIM pm Maxim MAX6029 MAKES EUK21 REF_N NOTE ONE FRONT END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT REFIN REF_P MAXIM MAX12557 REF_N Figure 12 External Buffered MAX4230 Reference Drive Using a MAX6029 Bandgap Reference Buffered External Reference Drives The MAX4250 buffers the 2 048V reference and pro Multiple ADCs vides additional 10Hz LP filtering before its output is The buffered external reference mode allows for more applied to the REFIN input of the MAX12557 control over the MAX12557 reference voltage and allows multiple converters to use a common reference Multiple ADCs The REFIN input impedance is gt 50MQ a The unbuffered external reference mode allows for pre Figure 12 shows the MAX6029 precision 2 048V bandgap cise control over the MAX12557 reference and allows reference used as a common reference for multiple con multiple converters to use a common reference verters The 2 048V output of the MAX6029 passes Connecting REFIN to GND disables the internal refer through a single pole 10Hz LP filter to the MAX4230 MAXIM 23 Unbuffered External Reference Drives ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC MAXIM MAX6029 EU
45. to GND with 20 1pF capacitor For external reference operation REFOUT is not required and must be bypassed to GND with a 20 1uF apacitor ingle Ended Reference Analog Input For internal reference and buffered external reference operation apply a 0 7V to 2 3V DC reference voltage to REFIN Bypass REFIN to GND with a4 7pF capacitor Within its specified operating voltage REFIN has a gt 50MQ input impedance and the differential reference voltage P VREF_N is generated from REFIN For unbuffered external reference operation connect REFIN to GND In this mode REF P REF N and COM are high impedance inputs that accept the external reference voltages Exposed Paddle EP is internally connected to GND Externally connect EP to GND to achieve specified dynamic performance MAXI MAX12557 IN_P i STAGE 10 sut STAGE 1 STAGE2 STAGES END OF PIPELINE DIGITAL ERROR CORRECTION DO THROUGH D13_ Figure 1 Pipeline Architecture Stage Blocks Detailed Description Each pipeline converter stage converts its input voltage f to a digital output code At every stage except the last The MAX12557 288224 10 stage fully 2 the error between the input voltage and the digital out Mns 1 1 that allows for high code is multiplied and passed along to the next EC i E power pipeline stage Digital error correction compensates for ION sod Hen tene al Me IMPUS MOVE progressi ADC comparator offsets in e
46. to input Note 3 Input connected to ground MAXIM ZSSCLXVIN MAX12557 Dual 65Msps 14 Bit IF Baseband ADC ELECTRICAL CHARACTERISTICS continued Vpop 3 3 OVpp 2 0V GND 0 REFIN REFOUT internal reference 10pF at digital outputs Vin 0 5 differen tial DIFFCLK SECLK OVpp PD GND SHREF GND DIV2 GND DIV4 GND G T GND 65MHz TA 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS DOA D13A DORA DOB D13B and DORB Tri State COUT Output Capacitance Note 3 DAV Tri State Output Capacitance Note 3 POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Normal operating mode IN 175MHz at 0 5dBFS single ended clock DIFFCLK SECLK GND Normal operating mode Analog Supply Current IN 175MHz at 0 5dBFS differential clock DIFFCLK SECLK OVpp Power down mode PD OVpp clock idle ormal operating mode IN 175 2 at 0 5dBFS single ended clock DIFFCLK SECLK GND TENE ormal operating mode Analog Power Dissipation 175MHz at 0 5dBFS ifferential clock DIFFCLK SECLK OVpp Power down mode PD OVpp clock idle ormal operating mode fin 175MHz at 0 5dBFS Digital Output Supply Current Power down mode PD OVpp clock idle 6 MAXIM Dual 65Msps 14 Bit IF Baseband ADC ELECTRICAL CHARAC
47. to thermal plus quantization noise and is an indication of the con verter s overall noise performance No fundamental input tone is used to test for NOUT IN P IN N COM are connected together and 1024k data points are collected is computed by taking the RMS value of the collected data points after the mean is removed Overdrive Recovery Time Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full scale limits The MAX12557 specifies overdrive recovery time using an input transient that exceeds the full scale limits by 10 The MAX12557 requires one clock cycle to recover from the overdrive condition Crosstalk Coupling onto one channel being driven by a 0 5aBFS signal when the adjacent interfering channel is driven by a full scale signal Measurement includes all spurs resulting from both direct coupling and mixing components AVLAZCLAVI Dual 65Msps 14 Bit IF Baseband ADC Gain Matching Pin Configuration Gain matching is a figure of merit that indicates how well the gains between the two channels are matched TOP VIEW to each other The same input signal is applied to both channels and the maximum deviation in gain is report ed typically in dB as gain matching Offset Matching Like gain matching offset matching is a figure of merit that indicates how well the offsets between the two chan nels are matched to each other The same input si
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