Intel UPI-C42 User's Manual
Contents
1. 0 5V to 7V Power Dissipation 1 5W UPI C42 UPI L42 NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability DC CHARACTERISTICS 0 C to 70 Voc Vpp 5V 10 3 3V 10 UPI L42 UPI C42 UPI L42 Symbol Parameter Units Notes Min Max Min Max VIL Input Low Voltage 0 5 0 8 0 3 0 8 V All Pins Input High Voltage 2 0 Voc 20 Vcc 0 3 V Except XTAL2 RESET Input High Voltage 3 5 Voc 20 Vcc 03 V XTAL2 RESET VoL Output Low Voltage Do D7 0 45 0 45 V 2 0 mA UPI C42 loy 1 3 UPI L42 Output Low Voltage 0 45 0 45 V 1 6 mA UPI C42 P10P17 P20P27 Sync lo 1 mA UPI L42 VoL2 Output Low Voltage PROG 0 45 0 45 V 1 0 mA UPI C42 0 7 mA UPI L42 VoH Output High Voltage Do D7 2 4 2 4 V 400 uA UPI C42 lou 260 pA UPI L42 Output High Voltage 2 4 2 4 lon 50 pA UPI C42 All Other Outputs lon 25 pA UPI L42 lit Input Leakage Current 10 10 Vss Vin Voc To T4 RD WR2. Test 0 Setup Time for Program Mode Atcy twT Test 0 Hold Time after Program Mode Atcy tpo Test 0 to Data Out Delay Atcy tww RESET Pulse Width to Latch Address Atcy tr tr PROG Rise and Fall Times 0 5 100 ps tcy CPU Operation Cycle Time 2 5 3 75 ps tRE RESET Setup Time before EA T Atcy topw Overprogram Pulse Width 2 85 78 75 ms 1 tpE EA High to Vpp High 1tcv NOTES 1 This variation is a function of the iteration counter value X 2 If TEST 0 is high tpo can be triggered by RESET T AC TESTING INPUT OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT INPUT OUTPUT 2 4 2 0 2 0 DEVICE ba T gt vest Ponts T X m n 0 8 0 8 Hi 0 45 290414 16 290414 17 19 UPI C42 UPI L42 DRIVING FROM AN EXTERNAL SOURCE 1 2 soxa 3 ene XTAL1 XTAL1 XTALI 2 XTAL1 LE 5V XTAL2 XTAL2 3 xm 4702 XTAL2 290414 18 TENE NOTE Rise and Fall Times Should Not See XTAL1 Configuration Table Exceed 10 ns Resistors to Vcc are Needed to Ensure Vj 3 5V if TTL Circuitry is Used LC OSCILLATOR MODE CRYSTAL OSCILLATOR MODE L C NOMINAL 45H 20 5 2 MHz t 120H 20pF 3 2 MHz 2m LC L 2 5 10 pF Pin to Pin Capacitance 290414 20 Each C Should be Approximately 20 pF including Stray Capacitance XTAL1 Configuration Table XTAL1 Connection 290414 21 C1 5 pF STRAY 5 pF C2 CRYSTAL STRAY 8 pF 20 30 pF INCLUDING STRAY Crystal Series Resistance Sh
3. TO ov sv SYNC ov E RESET 0V w 290414 15 Minimum Specifications SYNC Operation Time tsyNc 3 5 XTAL 2 Clock cycles Reset Time tas 4 tcy NOTE The rising and falling edges of TO should occur during low state of XTAL 2 clock APPLICATIONS KEYLOCK KEYBOARD SYSTEM CONTROL INTERF ACE SIGNALS KBDATA A20GATE ADDRESS BUS CONTROL KBDATA SERIAL DATA FROM KEYBOARD 290414 12 Figure 7 UPI C42 Keyboard Controller TO PERIPHERAL DEVICES s as a e ga EHE z j 215 a 290414 9 Figure 8 8088 UPI C42 Interface 13 UPI C42 UPI L42 APPLICATIONS Continued TO PERIPHERAL DEVICES 290414 10 KEYBOARD MATRIX 8243 EXPANDER s ROWS DATA BUS CONTROL 8US 290414 11 Figure 10 UPI C42 8243 Keyboard Scanner DOT MATRIX PRINTER FORM PRINT LF HOLD SOLENOIDS MOTOR DRIVERS SOLENOID DAIVERS z 5 o rj a TOP OF FORM LINE FEED POSITION PORT 2 PORT PORT 2 UPI C42 CONTROL M CONTROL BUS j 290414 13 Figure 11 UPI C42 80 Column Matrix Printer Interface 14 intel ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Voltage on Any Pin with Respect to Ground
4. the Program Counter Contents are Available 23 UPI C42 UPI L42 Table 4 UPI Instruction Set Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles ACCUMULATOR DATA MOVES ADD A Rr Add register to A 1 1 MOV A Rr Move register to A 1 1 ADD A Rr Add data memory 1 1 MOV A Rr Move data memory 1 1 toA toA ADD A data Add immediate to A 2 2 MOV A data Move immediate to A 2 2 ADDC A Rr Add register to A 1 1 MOVRr A Move A to register 1 1 with carry MOV Rr A Move A to data 1 1 ADDC A Rr Add data memory 1 1 memory to A with carry MOV Rr data Move immediate to 2 2 ADDC A data Add immediate 2 2 register to A with carry MOV Rr Move immediate to 2 2 ANL A Rr AND register to A 1 1 data data memory ANL A Rr AND data memory 1 1 MOV A PSW Move PSW to A 1 1 toA MOV PSW A Move A to PSW 1 1 ANL A data AND immediate to A 2 2 XCH A Rr Exchange A and 1 1 ORL A Rr OR register to A 1 1 register ORL A eRr OR data memory 1 1 XCH A eRr Exchange A and 1 1 to A data memory ORLA 4data immediate to A 2 2 XCHD A Rr Exchange digit of A 1 1 XRL A Rr Exclusive OR regis 1 1 and register ter to A MOVP A A Move to A from 1 2 XRL A Rr Exclusive OR data 1 1 current page memory to A MOVP3 A 9A Move to A from 1 2 XRLA data Exclusive OR imme 2 2 page 3 Sa T TIMER COUNTER INGA Increment A 1 1 MOV A T Read Timer Counter 1 1 DECA Decrement A 1 MOV T A Load Timer Counter 1
5. Vin 5 V DBy DB VOV DATA IN DATA OUT NEXT ADDRESS IL PoP WGV ADDRESS NEXT ADDRESS 207 25 VpopH 12 75 V Vpp 5 po 5 V toy gt PROG tow twp 290414 25 NOTES 1 Ao must be held low OV during program verify modes 2 For Vin Vina Vict and Vppi please consult the D C Characteristics Table 3 When programming the 87C42 0 1 uF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device VERIFY MODE EA VIH TO VIH1 RESET VIL1 TWA 7 VIH DBO DB7 ADDRESS 0 DATA OUT NEXT ADDRESS VIL VIH P20 P23 NEXT ADDRESS VIL 290414 26 NOTES 1 PROG must float if EA is low 2 PROG must float or 5V when EA is high 3 P4o0 P47 5V or must float 4 Po4 P27 5V or must float 5 Ag must be held low during programming verify modes 22 i ntel UPI C42 UPI L42 WAVEFORMS Continued DMA BACK DATA BUS ORO 290414 27 PORT 2 SYNC EXPANDER PORT OUTPUT PORT 20 3 DATA EXPANDER PORT INPUT PCRT 29 3 DATA PROG 290414 28 PORT TIMING DURING EXTERNAL ACCESS EA SYNC EE uu RENT ae _ 1017 PORT PORT P DATA DATA 20 22 290414 29 On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync
6. DATA see port timing diagrams at end of this data sheet 7 The UPI C42 supports the Quick Pulse Program ming Algorithm but can also be programmed with the Intelligent Programming Algorithm See the Programming Section UPI C42 FEATURES Programmable Memory Size Increase The user programmable memory on the UPI C42 will be increased from the 2K available in the NMOS product by 2X to 4K The larger user programmable memory array will allow the user to develop more complex peripheral control micro code P2 3 port 2 bit 3 has been designated as the extra address pin required to support the programming of the extra 2K of user programmable memory The new instruction SEL PMB1 73h allows for ac cess to the upper 2K bank locations 2048 4095 The additional memory is completely transparent to users not wishing to take advantage of the extra memory space No new commands are required to access the lower 2K bytes The SEL PMBO 63h has also been added to the UPI C42 instruction set to allow for switching between memory banks Extended Memory Program Addressing Beyond 2K For programs of 2K words or less the UPI C42 ad dresses program memory in the conventional man ner Addresses beyond 2047 can be reached by ex ecuting program memory bank switch instruction SEL PMBO SEL PMB1 followed by a branch in struction JMP or CALL The bank switch feature extends the range of branch instructions beyond their normal 2K r
7. 1000 0010 82h or 1110 0010 E2h Enables device to enter micro power mode In this mode the external oscillator is off CPU operation is stopped and the Port pins are tristated This mode can only be exited via a RESET signal PROGRAMMING AND VERIFYING THE UPI C42 The UPI C42 programming will differ from the NMOS device in three ways First the C42 will have a 4K user programmable array The UPI C42 will also be programmed using the Intel Quick Pulse Program ming Algorithm Finally port 2 bit three P2 3 will be used during program as the extra address pin re quired to program the upper 2K bank of additional memory None of these differences have any effect on the full CHMOS to NMOS device compatibility The extra memory is fully transparent to the user who does not need or want to use the extra memo ry space of the UPI C42 In brief the programming process consists of acti vating the program mode applying an address latching the address applying data and applying a programming pulse Each word is programmed com pletely before moving on to the next and is followed by a verification step The following is a list of the pins used for programming and a description of their functions UPI C42 UPI L42 Pin Function XTAL 2 Clock Input Reset Initialization and Address Latching Test 0 Selection of Program or Verify Mode EA Activation of Program Verify Signature Row Security Bit Modes BUS Address and
8. ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and the Security Bit respectively Also the programming and verification modes are included for comparison Control Signals Data Bus Access code Modes Port 2 Port 1 TO RST SS EAJPROG Vpp 0 1 2 3 4 5 6 7 0123 0 1234567 Programming 0 0 1JHV 1 VppH Vcc Address Addr ao ay X X X X X X Mode 1 4 HV STB Voon Voc Data In Addr Verification o 1 Hv 1 Voc Vcc Address Add aoaoX X X X X X Mode 1 1 Voc Voc Data Out Addr Sync Mode STB Hv o X vcc Vcc X X X X X X X XIXXX IX XXXXXXX High Signature Prog 0 0 1 HV 1 Vppu Voc Addr see Sig Mode Table 000 01 111XX1 Mode o 1 1 STB Vppu Vcc Data In 000 Verify o 1 HV 1 Vcc Vcc Addr see Sig Mode Table o 0 0 1 1 1 HV 1 Voc Vcc Data Out 000 Security Prog 0 0 1 HV 1 VppH Vcc Address 000 Bit Byte 1 1 STB Vppu Voc Data In 000 Verify 0 O 1HV 1 Voc Vcc Address 000 1 1 1 HV 1 Voc Vcc Data Out 000 NOTE 1 890 00r 1 12 0 or 1 ao must a4 i ntel UPI C42 UPI L42 SYNC MODE TIMING DIAGRAMS LU LT LE UU A AA Le PURE et EE ee i PHASE 2 L rr r1 TIME STATE 1 2 3 12V SS e ee LR c0
9. COMPATIBLE FEATURES 1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol INTERNAL DATA BUS OUTPUT DATA zi BUS BUFFER 8 Warn 290414 5 2 8 Bits of Status ST7 STe STs 4 F4 Fo IBF OBF D De Ds D4 D3 D Dy Do ST4 ST7 are user definable status bits These bits are defined by the MOV STS A single byte single cycle instruction Bits 4 7 of the acccumulator are moved to bits 4 7 of the status register Bits 0 3 of the status register are not affected MOV STS Op Code 90H 1 o0 o0 1 o0 o0 o0 0 D7 Do 3 RD and WR are edge triggered IBF OBF F4 and INT change internally after the trailing edge of RD or WR During the time that the host CPU is reading the status register the UPI is prevented from updat ing this register or is locked out FLAGS AFFECTED RD or WR 7 290414 6 UPI C42 UPI L42 4 P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master proces sor These pins default to port pins on Reset If the EN FLAGS instruction has been execut ed Po4 becomes the OBF Output Buffer Full pin 1 written to P24 enables the OBF pin the pin outputs the OBF Status Bit A 0 written to P24 disables the OBF pin the pin remains low This pin can be used
10. The test code checksum is present on ROMs and OTPs B Intel signature This allows the programmer to read from the UPI 41AH 42AH C42 the manu facturer of the device and the exact product name It facilitates automatic device identification UPI C42 UPI L42 and will be present in the ROM and OTP ver sions Location 10H contains the manufacturer code For Intel it is 89H Location 11H contains the device code The code is 43H and 42H for the 8042AH 80C42 and OTP 8742AH 87C42 respectively The code is 44H for any device with the security bit set by Intel C User signature The user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signa ture code for identification purposes and quick sorting of previously programmed materials D Test signature This memory is used to store testing information such as test data bin num ber etc for use in quality and manufacturing control E Security byte This byte is used to check whether the security bit has been programmed see the security bit section F UPI C42 Intel Signature Applies only to CHMOS device Location 20H contains the man ufacturer code and location 21H contains the de vice code The Intel UPI C42 manufacturer s code is 99H The device ID s are 82H for the OTP version and 83H for the ROM version The device ID s are the same for the UPI L42 The signature mode can be accessed by setting
11. 1 Glar A 1 STRTT Start Timer 1 1 CREA Complement A 1 STRT CNT Start Counter 1 1 DAA Decimal Adjust A 1 1 STOPTCNT Stop Timer Counter 1 1 SWARA Swab nibbles of A 1 i EN TCNTI Enable Timer 1 1 RLA Rotate A left 1 1 Counter Interrupt RLC A Rotate Aleftthrough 1 1 DIS TCNTI Disable Timer 1 1 Carry Counter Interrupt RRA Rotate A right 1 1 RRC A Rotate A right 1 1 CONTROL through carry EN A20 Enable A20 Logic 1 1 EN DMA Enable DMA Hand 1 1 INPUT OUTPUT shake Lines IN A Pp Input port to 1 2 Enable IBF Interrupt 1 1 OUTL Pp A Output A to port 1 2 ANL Pp data AND immediate to 2 2 DIS I Diable IBF Inter 1 1 rupt ORL Pp data OR immediate to 2 2 EN FLAGS Enable Master 1 1 port Interrupts IN A DBB Input DBB to A 1 1 SEL PMBO Select Program 1 1 clear IBF memory bank 0 SULBEBUN Output to DBB 1 SELPMB1 Select Program 1 1 set OBF memory bank 1 OMEN BIAS l 1 SEL RBO Select register 1 1 Status bank 0 Input Expander 1 2 SEL RB1 Select register 1 1 port to A bank 1 MEPE z UPI C42 UPI L42 Only ANLD Pp AND A to Expander 1 2 por ORLD Pp A OR A to Expander 1 2 por 24 intel UPI C42 UPI L42 Table 4 UPI Instruction Set Continued UPI C42 UPI L42 Only REVISION SUMMARY The following has been changed since Revision 003 1 Delete all references to standby power down mode The following has been ch
12. 243 I O expander device and contain address and data information during PORT 4 7 access P24 can be programmed to provide hardware A20 gate support The upper 4 bits Po4 P27 can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full OBF interrupt Pos as Input Buffer Full IBF interrupt Pog as DMA Request DRQ and P27 as DMA ACKnowledge DACK PROG 25 28 43 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This pin should be tied high if unused Voc 40 44 17 POWER 5V main power supply pin Vpp 26 29 1 POWER 5V during normal operation 12 75V during programming operation Low power standby supply pin Vss 20 22 38 GROUND Circuit ground potential INTERNAL BUS e PROGRAM Par diy Do E RESIDENT 128x8 RANDOM SYSTEM INTERFACE WA o qa A ps 9 PERIPHERAL INTERFACE CONTROL EA SYNC Pao 58 Par PROG RESET 9 ARITHMETIC PROM ROM CRYSTAL XTAL1 es MEMORY CONDITION LC OR xs si Vss PROM PROGRAM SUPPLY Vec 5 SUPPLY GROUND REGISTER 12 BIT PROGRAM COUNTER BBT TIMER EVENT COUNTER 290414 4 Figure 4 Block Diagram UPI C42 UPI L42 in
13. 2K bank and bit 11 of the program counter is held at 0 during the interrupt service routine The end of the service routine is sig naled by the execution of an RETR instruction Inter rupt service routines should therefore be contained entirely in the lower 2K words of program memory The execution of a SEL PMBO or SEL PMB1 instruc tion within an interrupt routine is not recommended since it will not alter PC11 while in the routine but will change the internal flip flop Hardware A20 Gate Support This feature has been provided to enhance the per formance of the UPI C42 when being used in a key board controller application The UPI C42 design has included on chip logic to support a hardware GATEA20 feature which eliminates the need to pro vide firmware to process A20 command sequences intel thereby providing additional user programmable memory space This feature is enabled by the A20EN instruction and remains enabled until the de vice is reset It is important to note that the execu tion of the A20EN instruction redefines Port 2 bit 1 as a pure output pin with read only characteristics The state of this pin can be modified only through a valid D1 command sequence see Table 1 Once enabled the A20 logic will process a D1 com mand sequence write to output port by setting re setting the A20 bit on port 2 bit 1 P2 1 without requiring service from the internal CPU The host can directly control the sta
14. CS Ao EA loFL Output Leakage Current 10 10 pA Vss 0 45 lt Vout lt Voc Do D7 High Z State li Low Input Load Current 50 250 35 175 pA Port Pins P10P47 P20P27 Min Vin 2 4V Max Vin 0 45V lin Low Input Load Current 40 40 pA V VIL RESET SS Ini Port Sink Current Voc 3 0V 5 0 mA 1 1 P20P27 Vin 5 0V Ipp Vpp Supply Current 4 2 5 mA 15 UPI C42 UPI L42 DC CHARACTERISTICS Ta 0 C to 70 C Vpp 5V 10 3 3V 10 UPI L42 Continued UPI C42 UPI L42 Symbol Parameter Units Notes Min Max Min Max Icc IDD Total Supply Current Active Mode 12 5 MHz 30 20 mA Typical 14 mA UPI C42 9 mA UPI L42 Suspend Mode 40 26 uA Osc 4 Ipp Standby Power Down 5 3 5 mA NMOS Compatible Supply Current Power Down Mode Input Leakage Current 100 100 pA Vin Voc 17 P20 P27 Cin Input Capacitance 10 10 pF TA 25 C 1 Cio I O Capacitance 20 20 pF TA 25 C 1 NOTE 1 Sampled not 100 tested DC CHARACTERISTICS PROGRAMMING UPI C42 AND UPI L42 TA 25 5 6 25V 0 25V Vpp 12 75V 0 25V Symbol Parameter Min Max Units VDDH Vpp Program Voltage High Level 12 5 13 va VpDL Vpp Voltage Low Level 4 75 5 25 V VPH PROG Program Voltage High Level 2 0 5 5 V PROG Voltage Low Level 0 5 0 8 V VEAH Input High Vol
15. Data Input Data Output During Verify P o 23 Address Input VDD Programming Power Supply PROG Program Pulse Input WARNING An attempt to program a missocketed UPI C42 will result in severe damage to the part An indication of a properly socketed part is the appearance of the SYNC clock output The lack of this clock may be used to disable the program mer The Program Verify sequence is 1 Insert 87C42 in programming socket 2 CS 5V Vcc 5V Vpp 5V RESET OV Ao OV TEST 0 5V clock applied or inter nal oscillator operating BUS floating PROG 5V TEST 0 OV select program mode EA 12 75V active program mode Voc 6 25V programming supply Vpp 12 75V programming power Address applied to BUS and Pap_23 RESET 5V latch address Data applied to BUS PROG 5V followed by one 100 us pulse to ov 11 TEST 0 5V verify mode 12 Read and verify data on BUS 13 TEST 0 OV 14 RESET OV and repeat from step 6 15 Programmer should be at conditions of step 1 when the 87C42 is removed from socket o OQ E Please follow the Quick Pulse Programming flow chart for proper programming procedure shown in Figure 6 UPI C42 UPI L42 ADD 1ST LOC Voc 6 25V Vpp 12 75V PROGRAM ONE 100 ws PULSE VERIFY ONE BYTE FAIL LAST ADDRESS INC ADDR DEVICE FAILED COMPARE ALL BYTES T
16. O ORIGINAL DATA DEVICE PASSED 290414 14 Figure 6 Quick Pulse Programming Algorithm Quick Pulse Programming Algorithm As previously stated the UPI C42 will be pro grammed using the Quick Pulse Programming Algo rithm developed by Intel to substantially reduce the thorughput time in production programming The Quick Pulse Programming Algorithm uses initial pulses of 100 us followed by a byte verification to determine when the address byte has been suc cessfully programmed Up to 25 100 us pulses per byte are provided before a failure is recognized A 10 intel flow chart of the Quick Pulse Programming Algo rithm is shown in Figure 6 The entire sequence of program pulses and byte verifications is performed at Voc 6 25V and Vpp 12 75V When programming has been com pleted all bytes should be compared to the original data with Vcc Vpp 5V A verify should be performed on the programmed bits to ensure that they have been correctly pro grammed The verify is performed with TO 5V Vpp 5V EA 12 75V SS 5V PROG 5V AO OV and CS 5V In addition to the Quick Pulse Programming Algo rithm the UPI C42 OPT is also compatible with In tel s Inteligent Programming Algorithm which is used to program the NMOS UPI 42AH OTP devices The entire sequence of program pulses and byte verifications is performed at 6 25V and Vpop 12 75V When the inteligent Programming cycle has been co
17. P10 0 P11 P17 1 and then following the pro gramming and or verification procedures The loca tion of the various address partitions are as shown in Table 3 SYNC MODE The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time The Sync Mode may also be utilized by automatic test equipment ATE for quick easy and efficient synchronizing between the tester and the DUT de vice under test Sync Mode is enabled when SS pin is raised to high voltage level of 12 volts To begin synchroniza tion TO is raised to 5 volts at least four clock cycles after SS TO must be high for at least four X2 clock cycles to fully reset the prescaler and time state generators TO may then be brought down during low state of X2 Two clock cycles later with the ris ing edge of X2 the device enters into Time State 1 Phase 1 SS is then brought down to 5 volts 4 clocks later after TO RESET is allowed to go high 5 tCY 75 clocks later for normal execution of code 11 UPI C42 UPI L42 Table 3 Signature Mode Table Address piu Briss Test Code Checksum 0 OFH ROM OTP 25 16H 1EH Intel Signature 10H 11H ROM OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM OTP 2 Security Byte 1FH ROM OTP 2 UPI C42 Intel Signature 20H 21H ROM OTP 2 User Defined UPI C42 OTP EPROM Space 22H 3EH ROM OTP 30
18. RPORATION 1996 December 1995 Order Number 290414 003 UPI C42 UPI L42 intel Table 1 Pin Description DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No No No TEST 0 1 2 18 TEST INPUTS Input pins which be directly tested using conditional TEST 1 39 43 16 branch instructions FREQUENCY REFERENCE TEST 1 T4 functions as the event timer input under software control TEST 0 To is a multi function pin used during PROM programming and ROM EPROM verification during Sync Mode to reset the instruction state to 51 and synchronize the internal clock to PH1 XTAL 1 2 3 19 OUTPUT Output from the oscillator amplifier XTAL 2 3 4 20 INPUT Input to the oscillator amplifier and internal clock generator circuits RESET 4 5 22 RESET Input used to reset status flip flops set the program counter to zero and force the UPI C42 from the suspend power down mode RESET is also used during EPROM programming and verification 55 5 6 23 SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction EPROM This should be tied to 5V when not used This pin is also used to put the device in Sync Mode by applying 12 5V to it cs 6 7 24 CHIP SELECT Chip select input used to select UPI microcomputer out of several connected to a common data bus EA 7 8 25 EXTERNAL ACCESS External access
19. a CHMOS product The UPI L42 offers the same functionality and socket compatibility as the UPI C42 as well as providing low voltage 3 3V operation The UPI C42 is essentially a slave microcontroller or a microcontroller with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family as well as other 8 16 and 32 bit systems To allow full user flexibility the program memory is available in ROM and One Time Programmable EPROM OTP Yoo Pi E pi si UPi C42 1505 2300 sync Miner TE Pi Eje UPI C42 PISE 7 UPI L42 27 nes 26RD ergo 25 Pea eoio P2 0BF 011 23155 LI LE LIE LIE LI 290414 1 gg Figure 1 DIP Pin 290414 2 290414 3 Configuration Figure 2 PLCC Pin Configuration Figure 3 QFP Pin Configuration Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CO
20. ange and at the same time prevents the user from inadvertently crossing the 2K boundary intel PROGRAM MEMORY BANK SWITCH The switching of 2K program memory banks is ac complished by directly setting or resetting the most significant bit of the program counter bit 11 see Figure 5 Bit 11 is not altered by normal increment ing of the program counter but is loaded with the contents of a special flip flop each time a JMP or CALL instruction is executed This special flip flop is set by executing an SEL PMB1 instruction and reset by SEL PMBO Therefore the SEL PMB instruction may be executed at any time prior to the actual bank switch which occurs during the next branch instruc tion encountered Since all twelve bits of the pro gram counter including bit 11 are stored in the stack when a Call is executed the user may jump to subroutines across the 2K boundary and the proper PC will be restored upon return However the bank switch flip flop will not be altered on return Conventional Program Counter Counts 000H to 7FFH Overflows 7FFH to 000H JMP or CALL instructions transfer contents of internal flip flop to 1 Flip flop set by SEL MB1 Flip flop reset by SEL MBO or by RESET During interrupt service routine Aj is forced to 0 All 12 bits are saved in stack 290414 30 Figure 5 Program Counter INTERRUPT ROUTINES Interrupts always vector the program counter to lo cation 3 or 7 in the first
21. anged since Revision 002 1 Added information on keyboard controller prod uct family 2 Added specification for the UPI L42 The following has been changed since Revision 001 1 Added UPI L42 references and specification for Bit Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles CONTROL Continued BRANCH SUSPEND Invoke Suspend Power 1 2 JMP addr Jump unconditional 2 2 down mode JMPP A Jump indirect 1 2 NOP No Operation 1 1 DJNZ Rr addr Decrement register 2 2 REGISTERS and jump INC Rr Increment register 1 1 JC addr Jump on Carry 1 2 2 INC Rr Increment data 1 1 ING Jump ofer 2 memory JZ addr Jump on A Zero 2 2 DEC Rr Decrement register 1 1 JNZ addr Jump on A not Zero 2 2 JTO addr Jump on TO 1 2 2 SUBROUTINE JNTO addr Jump on TO 0 2 2 CALL addr to subroutine 2 2 JT1 addr Jump on T1 1 2 2 RET Return 1 2 JNT1 addr Jump on T1 0 2 2 RETR Return and restore 1 2 JFO addr Jump on Flag 1 2 2 status JF1 addr Jump on F1 Flag 1 2 2 FLAGS JTF addr Jump on Timer Flag 2 2 CLRC Clear Carry 1 1 1 Clear Flag CPLC Complement Carry 1 1 JNIBF addr Jump on IBF Flag 2 2 CLR FO Clear Flag 0 1 1 0 CPL FO Complement Flag 0 1 1 JOBF addr Jump on OBF Flag 2 2 CLR F1 Clear F1 Flag 1 1 1 CPL F1 Complement F1 Flag 1 1 JBb addr Jump on Accumula 2 2 25
22. e completely compatible with all current NMOS code applications In order to use new features however some code modifications will be necessary All new instructions can easily be in serted into existing code by use of the ASM 48 mac ro facility as shown in the following example Macname MACRO DB 63H ENDM New Instructions The following is a list of additions to the UPI 42 in struction set These instructions apply only to the UPI C42 These instructions must be added to exist ing code in order to use any new functionality SEL PMBO Select Program Memory Bank 0 OPCODE 0110 0011 63h PC Bit 11 is set to zero on next JMP or CALL instruc tion All references to program memory fall within the range of 0 2047 0 7FFh SEL PMB1 Select Program Memory Bank 1 OPCODE 0111 0011 73h PC Bit 11 is set to one on next JMP or CALL instruc tion All references to program memory fall within the range of 2048 4095 800h FFFh ENA20 Enables Auto A20 hardware OPCODE 0011 0011 33h Enables on chip logic to support Hardware A20 Gate feature Will remain enabled until device is reset intel This circuitry gives the host direct control of port 2 bit 1 P2 1 without intervention by the internal CPU When this opcode is executed P2 1 becomes a ded icated output pin The status of this pin is read able but can only be altered through a valid D1 com mand sequence see Table 1 SUSPEND Invoke Suspend Power Down Mode OPCODE
23. gin from PC 000h when the UPI C42 exits from the suspend power down mode Suspend Mode Summary Oscillator Not Running CPU Operation Stopped e Ports Tristated with Weak 2 10 uA Pull Up e Micropower Mode loc lt 40 pA e This mode is exited by RESET UPI C42 UPI L42 Table 2 covers all suspend mode pin states In addi tion to the suspend power down mode the UPI C42 will also support the NMOS power down mode as outlined in Chapter 4 of the UPI 42AH users manual Table 2 Suspend Mode Pin States Pins Suspend Ports 1 and 2 Outputs Tristate Inputs Weak Pull Up Disabled DBB 1 Outputs Normal Inputs Normal System Control Disabled RD WR CS AO Reset Enabled Crystal Osc Disabled XTAL1 XTAL2 Test 0 Test 1 Disabled Prog High Sync High EA Disabled No Pull Up SS Disabled Weak Pull Up loc lt 40 pA NOTES 1 DBB outputs are Tristate unless CS and RD are ac tive DBB inputs are disabled unless CS and WR are active 2 A disabled input will not cause current to be drawn regardless of input level within the supply range 3 Weak pull ups have current capability of typically 5 uA intel NEW UPI C42 INSTRUCTIONS The UPI C42 will support several new instructions to allow for the use of new C42 features These in structions are not necessary to the user who does not wish to take advantage of any new C42 function ality The C42 will b
24. input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused RD 8 9 26 READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register Ao 9 10 27 COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data Ao 0 F1 is reset or command Ao 1 F1 is set Ag 0 during program and verify operations WR 10 11 28 WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER SYNC 11 13 29 OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation Do D7 12 19 14 21 30 37 I O DATA BUS Three state bidirectional DATA BUS BUFFER lines used to BUS interface the UPI microcomputer to an 8 bit master system data bus P4o P47 27 34 30 33 2 10 PORT 1 8 bit PORT 1 quasi bidirectional I O lines Pjg P47 access the 35 38 signature row and security bit UPI C42 UPI L42 Table 1 Pin Description Continued DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No No No P20 P27 21 24 24 27 39 42 PORT 2 8 bit PORT 2 quasi bidirectional I O lines The lower 4 bits 35 38 39 42 11 13 15 P20 P23 interface directly to the 8
25. intel UPI C42 UPI L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8 BIT SLAVE MICROCONTROLLER Pin Software and Architecturally m One 8 Bit Status and Two Data Compatible with all UPI 41 and UPI 42 Registers for Asynchronous Slave to Products Master Interface Low Voltage Operation with the UPI Fully Compatible with all Intel and Most L42 Other Microprocessor Families Full 3 3V Support Interchangeable ROM and OTP EPROM m Hardware A20 Gate Support Versions m Suspend Power Down Mode m Expandable I O m Security Bit Code Protection Support m Sync Mode Available 8 Bit CPU plus ROM OTP EPROM RAM Over 90 Instructions 70 Single Byte 1 0 Timer Counter and Clock a Quick Pulse Programming Algorithm Single Package Fast OTP Programming m 4096 x 8 ROM OTP 256 x 8 RAM 8 Bit m Available in 40 Lead Plastic 44 Lead Timer Counter 18 Programmable I O Plastic Leaded Chip Carrier and Pins 44 Lead Quad Flat Pack Packages m DMA Interrupt or Polled Operation See Packaging Spec Order 240800 Package Type P N Supported and S The UPI C42 is an enhanced CHMOS version of the industry standard Intel UPI 42 family It is fabricated on Intel s CHMOS III E process The UPI C42 is pin software and architecturally compatible with the NMOS UPI family The UPI C42 has all of the same features of the NMOS family plus a larger user programmable memory array 4K hardware A20 gate support and lower power consumption inherent to
26. k Period 80 613 ns tPwH Clock High Time 30 ns tPwL Clock Low Time 30 ns tR Clock Rise Time 10 ns t Clock Fall Time 10 ns NOTE 1 toy 15 f XTAL AC CHARACTERISTICS DMA Symbol Parameter Min Max Units tacc DACK to WR or RD 0 ns tcac RD or WR to DACK 0 ns tACD DACK to Data Valid 0 130 ns RD or WR to Cleared 110 ns 1 NOTE 1 CL 150 pF AC CHARACTERISTICS port 2 Symbol Parameter f tcy Min Max Units tcp Port Control Setup Before Falling Edge of PROG 1 15 tcy 28 55 ns 1 tpc Port Control Hold After Falling Edge of PROG 1 10 tcy 125 ns 2 tpr PROG to Time P2 Input Must Be Valid 8 15 tcy 16 650 ns 1 tPF Input Data Hold Time 0 150 ns 2 tpp Output Data Setup Time 2 10 250 ns 1 tpp Output Data Hold Time 1 10 tcy 80 45 ns 2 tpp PROG Pulse Width 6 10 tcy 750 ns NOTES 1 CL 80 pF 2 CL 20 pF 3 tcy 1 25 us 18 intel UPI C42 UPI L42 AC CHARACTERISTICS PROGRAMMING UPI C42 AND UPI L42 TA 25 C 5 C Voc 6 25V 0 25V 5V 0 25V 12 75V 0 25V 87C42 87L42 ONLY Symbol Parameter Min Max Units taw Address Setup Time to RESET T 4tcy twa Address Hold Time after RESET T 4icy tpw Data in Setup Time to PROG 4tcv twp Data in Hold Time after PROG 4tcv tpw Initial Program Pulse Width 95 105 ps
27. mpleted all bytes should be com pared to the original data with 5 0 Vpp Verify A verify should be performed on the programmed bits to determine that they have been correctly pro grammed The verify is performed with TO 5V Vpp 5V EA 12 75V SS 5V PROG 5V AO OV and CS 5V SECURITY BIT The security bit is a single EPROM cell outside the EPROM array The user can program this bit with the appropriate access code and the normal program ming procedure to inhibit any external access to the EPROM contents Thus the user s resident program is protected There is no direct external access to this bit However the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not The security bit has no effect on the signature mode so the security byte can always be examined SECURITY BIT PROGRAMMING VERIFICATION Programming a Read the security byte of the signature mode Make sure it is OOH intel b Apply access code to appropriate inputs to put the device into security mode c Apply high voltage to EA and Vpp pins d Follow the programming procedure as per the Quick Pulse Programming Algorithm with known data on the databus Not only the security bit but also the security byte of the signature row is pro grammed e Verify that the security byte of the signature mode contains the same data as ap
28. ould be Less Than 300 at 12 5 MHz 1 to Ground 2 10 Resistor to Ground 3 Not Connected Not recommended for CHMOS designs Causes approximately 16 mA of additional current flow through the XTAL1 pin on UPI C42 and approximately 11 mA of additional current through XTAL1 on the UPI L42 Recommended configuration for designs which will use both NMOS and CHMOS parts This configuration limits the additional current through the XTAL1 pin to approximately 1 mA while maintaining compatibility with the NMOS device Low power configuration recommended for CHMOS only designs to provide lowest possible power consumption This configuration will not work with the NMOS device 20 i ntel UPI C42 UPI L42 WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER SYSTEM S CS OR Ao ADDRESS BUS READ CONTROL DATA BUS OUTPUT lt vata VALID gt 290414 22 WRITE OPERATION DATA BUS BUFFER REGISTER iSYSTEM S OR Ag ADDRESS BUS IWRITE CONTROL DATA BUS DATA DATA NPUTI MAY CHANGE PATAMVALID MAY CHANGE 290414 23 CLOCK TIMING XTAL2 290414 24 21 UPI C42 UPI L42 intel WAVEFORMS Continued COMBINATION PROGRAM VERIFY MODE END OF PROGRAM P 4 VERIFY 4 PROGRAM gt PROGRAM OR VERIFY Veqy 12 75 V EA Vin 5 V vy Co V Vin 5 V Co V reser MGV v OY
29. peared on the data bus If DBO DB7 high the security byte will contain FFH f Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification If the EPROM can still be read the security bit may have not been fully programmed though the se curity byte in the signature mode has Verification Since the security bit address overlaps the address of the security byte of the signature mode it can be used to check indirectly whether the security bit has been programmed or not Therefore the security bit verification is a mere read operation of the security byte of the signature row OFFH security bit pro grammed 00H security bit unprogrammed Note that during the security bit programming the reading of the security byte does not necessarily indicate that the security bit has been successfully pro grammed Thus it is recommended that two consec utive known bytes in the EPROM array be read and the wrong data should be read at least once be cause it is highly improbable that random data coin cides with the correct ones twice SIGNATURE MODE The UPI C42 has an additional 64 bytes of EPROM available for Intel and user signatures and miscella neous purposes The 64 bytes are partitioned as fol lows A Test code checksum This can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory
30. tage for EA 12 0 13 0 v 2 VEAL EA Voltage Low Level 0 5 5 25 V Ipp Vpp High Voltage Supply Current 50 0 mA IEA EA High Voltage Supply Current 1 0 mA NOTES 1 Voltages over 13V applied to pin Vpp will permanently damage the device 2 VEAH must be applied to EA before and removed after 3 Vcc must be applied simultaneously or before Vpp and must be removed simultaneously or after Vpp 4 Sampled not 100 tested 16 i ntel UPI C42 UPI L42 AC CHARACTERISTICS TA 0 C to 70 C Vss OV Voc Vpp 5V 10 3 3V 10 for the UPI L42 NOTE All AC Characteristics apply to both the UPI C42 and UPI L42 DBB READ Symbol Parameter Min Max Units tar CS Ao Setup to RD 0 ns tra CS Ao Hold After RD T 0 ns tnn RD Pulse Width 160 ns tAD CS Ao to Data Out Delay 130 ns trp RD to Data Out Delay 0 130 ns tpr RD f to Data Float Delay 85 ns DBB WRITE Symbol Parameter Min Max Units taw CS Ao Setup to WR 0 ns iwa CS Ao Hold After WR T 0 ns twi WR Pulse Width 160 ns tpw Data Setup to WR 130 ns twp Data Hold After WR T 0 ns 17 UPI C42 UPI L42 intel AC CHARACTERISTICS TA 0 C to 70 C Vas OV Vpp 5V 10 3 3V 10 for the UPI L42 Continued CLOCK Symbol Parameter Min Max Units tcy UPI C42 UPI L42 Cycle Time 1 2 9 20 ps tcyc UPI C42 UPI L42 Cloc
31. tel UPI C42 L42 PRODUCT SELECTION GUIDE UPI C42 Low power CHMOS version of the UPI 42 Device Package ROM OTP Comments 80042 N PS 4K ROM Device 82C42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82C42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 82C42PE S Phoenix MultiKey 42G firmware Energy Efficient solution 87C42 N P S 4K One Time Programmable Version UPI L42 The low voltage 3 3V version of the UPI C42 Device Package ROM OTP Comments 80L42 N PS 4K ROM Device 82L42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82L42PD N P S Phoenix Multikey 42L firmware and SCC for portable apps 87142 N P 4K One Time Programmable Version N 44 lead PLCC P 40 lead PDIP S 44 lead QFP D 40 lead CERDIP Key Board Control SCC Scan Code Control THE INTEL 82C42 As shown in the UPI C42 product matrix the UPI C42 is offered as a pre programmed 80C42 with var ious versions of MultiKey 42 keyboard controller firmware developed by Phoenix Technologies Ltd The 82C42PC provides a low powered solution for industry standard keyboard and PS 2 style mouse control The 82C42PD provides a cost effective means for keyboard and scan code control for note book platforms The 82C42PE allows a quick time to market low cost solution for energy efficient desk top designs intel UPI 42
32. to indicate that valid data is available from the UPI in Output Data Bus Buff er If EN FLAGS has been executed Pos be comes the IBF Input Buffer Full pin A 1 writ ten to Pos enables the IBF pin the pin outputs the inverse of the IBF Status Bit A 0 written to Pos disables the IBF pin the pin remains low This pin can be used to indicate that the UPI is ready for data Data Bus Buffer Interrupt Capability OBF INTERRUPT REQUEST IBF INTERRUPT REQUEST 290414 7 EN FLAGS Code 5 151 31 110 1 0 1 D7 Do 5 Pog and P are port pins or DMA handshake pins for use with a DMA controller These pins default to port pins on Reset If the DMA instruction has been executed Pog becomes the DRQ DMA Request pin A 1 written to Pog causes a DMA request DRQ is activated DRQ is deactivated by DACKeRD DACKeWR or execution of the EN DMA in struction DMA Handshake Capability UPI C42 290414 8 UPI C42 UPI L42 If EN DMA has been executed Po becomes the DACK DMA ACKnowledge pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers EN DMA Op Code 0E5H 1 1 1 0 0 140 1 D7 Do 6 When EA is enabled on the UPI the program counter is placed on Port 1 and the lower four bits of Port 2 MSB P23 LSB P49 On the UPI this information is multiplexed with PORT
33. tus of the A20 bit At no time during this host interface transaction will the IBF flag in the status register be activated Table 1 gives several possible GATEA20 command data se quences and UPI C42 responses Table 1 D1 Command Sequences A0 R W DB Pins IBF A20 Comments 1 W Dih 0 n 1 Set A20 Sequence O W DFh 0 1 Only DB1 Is Processed 1 W FFH JO n 1 W Dih 0 n Clear A20 Sequence O W DDh 1 W FFh 0 n 1 W Dih 0 n Double Trigger Set 1 W Dih 0 n Sequence 0 W DFh 0 1 1 W FFh 0n 1 W Dih 0 n Invalid Sequence 1 W XXh 3 1 n No Change in State O W DDh 1 n of A20 Bit NOTES 1 Indicates that P2 1 remains at the previous logic level 2 Only FFh commands in a valid A20 sequence have no effect on IBF An FFh issued at any other time will activate IBF 3 Any command except D1 The above sequences assume that the GATEA20 logic has been enabled via the A20EN instruction As noted only the value on DB 1 data bus bit 1 is processed This bit will be directly passed through to P2 1 port 2 bit 1 UPI C42 UPI L42 SUSPEND The execution of the suspend instruction 82h or E2h causes the UPI C42 to enter the suspend mode In this mode of operation the oscillator is not running and the internal CPU operation is stopped The UPI C42 consumes lt 40 uA in the suspend mode This mode can only be exited by RESET CPU operation will be
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