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Intel S5000PSL User's Manual

1. G A B CDE E H J K L LEE t UU 11 B ear IT l Gi M H zz 1n P J i RR ZP I L i QQ mmm LI Q PP i X D O Oo Lg NN D W Pr Oe tog LL d a 2 S ke e REL ll JJ th 5 d o B AAR ge FFIDDBB Z X V GGEECCAA Y W BoSS Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables A PCI X 64 bit 100 MHz slot 1 Q DIMM sockets GG Enclosure management SAS SGPIO header order code S5000PSLSAS only B PCI X 64 bit 133 100 MHz slot 2 R Processor 1 socket HH Enclosure management SAS SES DC order code S5000PSLSAS only C PCI Express x4 x8 slot 3 S Processor 2 socket Il Hot swap backplane A header D Advanced Server Management Interface NIC connector T Processor 2 fan header JJ SATA 0 E PCI Express x4 slot 4 ROMB Slot U Processor 1 fan header KK SATA 1
2. AF000422 Figure 17 Jumper Blocks J1C3 J1D1 J1D2 J1E32 Table 35 Server Board Jumpers J1C3 J1D1 J1D2 J1E3 Jumper Name Pins System Results J1C3 BIOS Bank 1 2 If these pins are jumper the system will boot from an alternate BIOS image Select 2 3 System is configured for normal operation Default J1D1 CMOS Clear 1 2 These pins should have a jumper in place for normal system operation Default 2 3 If these pins are jumpered the CMOS settings will be cleared immediately These pins should not be jumpered for normal operation J1D2 Password 1 2 These pins should have a jumper in place for normal system operation Default Clear 2 3 If these pins are jumpered administrator and user passwords will be cleared immediately These pins should not be jumpered for normal operation J1E3 BMC Forced 1 2 BMC Firmware Force Update Mode Disabled Default Update 2 3 BMC Firmware Force Update Mode Enabled 68 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 6 1 CMOS Clear and Password Reset
3. 1 1 ER n 1 e Es SREBRN e Dmm m ps D o EH U Ge UJ SI i i H WU oo MYL S el el Gel But i a S d ij D S e T IE U 1 BIB l H 9 zn AF000205 Figure 21 DIMM Fault LED Locations 76 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 7 5 Processor Fault LEDs The server board provides a fault LED for each processor socket These LEDs are located near the processor sockets 1 W n o i
4. 2 2 2 Server Board Mechanical Drawings 3 18 0 01 0 01 0 125 0 000 0 000 NO COMPONENT KEEPOUT 120 00 172 10 3X NON PLATED THRU WITH 4 724 6 776 7 MM TOP SIDE 3 5 MM BOTTOM SIDE 124 46 176 10 281 94 0 00 4 900 6 933 11 100 0 000 TER 8 0 079 0 00 NR T rm 4 TYP jim L 2286 3000 H TEREE 0200 1 181 Ii 91 60 Gn 3 606 D H ZA ann P906 LLLA M 3 732 98 80 a 3 890 L T 154 94 6 100 187 96 n deeg 7 400 aa DIN s 8 950 0 400 TYP I i AKA zen J 10 600 3 96 0 13 0 03 Ld 0 156 0 005 0 001 Lp d 312 42 Thru hole with s 12 300 0 394 inch 10 mm E 14125 179 35 223 80 261 90 0 200 5 561 7 061 8 811 10 311 TP000217 Figure 3 Mounting Hole Positions 0 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Revision 1 2 0 00 o 0001 Pit 13 31 524 24 92 0981 31 37 1 235 30 96 1 219 1233 0 485 152 02 5 965 203 83 8 025 220 83 8 694 237 83 9 363 25483 10 033 271 83 10 702 28883 11 371 315 00 12 402 1170040 13 34 0525 1407 0564 0000 00 192312 List of Tables 8 S S 3 3 S 3 2 E ES x E z EI S E amp a S J 121 048 F x 1354 L 10 533 i 3 n E 288229 t J
5. AF000203 72 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 7 3 System ID LED and System Status LED The server board provides LEDs for both system ID and system status These LEDs are located in the rear I O area of the server board between the PS 2 mouse keyboard stacked connectors and the video serial stacked connectors The location of these LEDs are shown in the following figure
6. e cM mmm is 22295992 E l o SE 1 I l E E E D N EH i DEI l yc d DE US E IU 2 Oe G X L j m i E SS oO O BE EE o Gi AF000204 A System ID LED B System Status LED Figure 20 System ID LED and System Status LED Locations The blue System ID LED can be illuminated using either of two mechanisms By pressing the System ID Button on the system front panel the ID LED will display a solid blue color until the button is pressed again By issuing the appropriate hex IPMI Chassis Identify value the ID LED will either Blink Blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issued to turn it off Revision 1 2 73 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS The bi color System Status LED operates as follows Table 36 System Status LED Color State Criticality Not ready AC power off Green Alternating Not ready Pre DC Power On 20 30 second BMC Initialization when AC is Amber Blink applied to the server Control Panel buttons are disabled until BMC initialization is complete System OK System booted and ready Green Blink Degraded System degraded e Unable to use all of the installed memory more than one DIMM installed Correctable errors over a threshold of 10 and migrating to a spare DIMM memory sparing
7. Network interface support is provided from the built in Dual GbE MAC features of the ESB2 in conjunction with the Intel 82563EB compact Physical Layer Transceiver PHY Together they provide the server board with support for dual LAN ports designed for 10 100 1000 Mbps operation The 82563EB device is based upon proven PHY technology integrated into Intel s gigabit Ethernet controllers The physical layer circuitry provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab The 82563EB device is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps Each network interface controller NIC drives two LEDs located on each network interface connector The link activity LED at the right of the connector indicates network connection when on and transmit receive activity when blinking The speed LED at the left of the connector indicates 1000 Mbps operation when amber 100 Mbps operation when green and 10 Mbps when off The table below provides an overview of the LEDs Table 8 NIC2 Status LED LED Color LED State NIC State Active Connection Green Right B e a o Blinking Transmit Receive activity 48 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 3 5 1 Intel UO Acceleration Technolgy Intel UO Acceleration Technology moves netwo
8. 7 3 1 System Status LED BMC Initialization sess 74 7 4 DIMM Fault RE 76 7 5 Processor Fault EEDSs 5 vt rer t bie d p NIR e b eerte b tai EE 7T 7 6 Post Code Diagnostic LEDS eai oio t Det bebe ege dee dante 78 8 Design and Environmental Specifications cessere 79 8 1 Server Boards SSOOOPSL and S5000XSL Design Specifications 79 8 2 Server Board Power Requirements eee 80 8 2 1 Processor Power Support 81 8 3 Power Supply Output Requirements esses 81 8 3 1 Cosme 82 8 3 2 leiere 82 8 3 3 eu E eme 82 8 3 4 Voltage Regulation EEN 83 8 3 5 Dyriamic Loading isere e E Seb pe haa e e fiutie p tot ocn aAa 83 8 3 6 Capacitive in e EE 84 8 3 7 aie SANI LER I DU 84 8 3 8 Tiri Requirements TEE 84 8 3 9 Residual Voltage Immunity in Standby Mode sene 87 9 Regulatory and Certification Information e eeeeeeeeeeeeeee eere 88 9 1 Product Regulatory Compliance irr etie ere Kin a Een 88 9 1 1 Product Safety ue TEE 88 9 1 2 Product EMC Compliance Class A Compliance sss sese eee eee ee 88 9 1 3 Certifications Registrations Declarations eee eee eee 89 92 Product Regulatory Compliance Markings eee eee eee eee 89 9 3 Electromagnetic Compatibility Notices sees eee eee eee 90 9 3 1 FCC Verification Statement USA eee 90 9 3 2 IGES 003 06 Tae AE 90 9 3 3 Europe CE Declaration of Conformity see
9. Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables List of Tables Table 1 Server Board Eealules TE 14 Table 2 Processor Support Matrix eee 29 Table 3 lC Addresses for Memory Module SMB ss s sisnsisnisinrninrsienrsisnrarrnrnnsnrsrnnrerenrnrenrn 33 Table 4 Maximum Eight DIMM System Memory Configruation x8 Single Hank eee 34 Table 5 Maximum Eight DIMM System Memory Configuration x4 Dual Rank 34 Table 5 PCI Bus Segment GCharacteristis eg asi ne bee EENS aon 42 Table et ER EE 47 Table e NOZ Status E ciu E o ani E eet 48 Table 9 Serial B Header Te 50 Table 10 Board Connector MatIIx reto re Seer PRECOR ER rk verba teer Deer eds 53 Table 11 Power Connector Pin out JOBS sees eee eee 54 Table 12 12 V Power Connector Pin out J3J2 sss 55 Table 13 Power Supply Signal Connector Pin out J9D1 sse eee eee eee 55 Table 14 P12V4 Power Connector Pin out J5A2 eee eee 55 Table 15 RMM Connector Pin out J5B 1 eee tii reos ie e riae teens 56 Table 16 LPC AUX IPMB Header Pin out LI 57 Table 17 IPMB Header Pin out Al E 58 Table 18 HSBP Header Pin out J1J7 JIDD 58 Table 19 SGPIO Header Pin out J2H1 JD eee 58 Table 20 SES TC Header Pin out LUJ 58 Table 21 HDD Activity LED Header Pin out J2J231 sese 59 Table 22 Front Panel SSI Standard 24 pin Connector Pin out JE sese 59 Table 23 VGA Connector Pin out JTA 59 Table 24 RJ 45 10 100 1000 NIC Connector P
10. Pin Signal Name V IO DDCDAT DDCDAT V IO HSYNC CONN HSYNC horizontal sync V IO VSYNC CONN VSYNC vertical sync V IO DDCCLK DDCCLK 5 5 2 NIC Connectors The server board provides two stacked RJ45 2xUSB connectors side by side on the back edge of the board JA6A1 JA6A2 The pin out for NIC connectors are identical and are defined in the following table Table 24 RJ 45 10 100 1000 NIC Connector Pin out JA6A1 JAGA2 Pin Signal Name P1V8 NIC NIC A MDI3P NIC A MDI3N NIC A MDI2P Neame o 7 s NcAWwop NIC A MDION 11 D1 NIC LINKA 1000 N LED 5 5 3 IDE Connector The server board provides one legacy IDE ATA100 40 pin connector J2J2 The pin out is defined in the following table Table 25 IDE 40 pin Connector Pin out J2J2 Pin Signal Name Pin Signal Name 3 RIDE DD 7 RIDE DD 8 eem s monos LH L S 60 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Signal Name Pin Pin E RIDE DCS1 N 38 RIDE DCS3 N D D RIDE DIOR N 26 D D D 5 5 4 Intel Remote Management Module NIC Connector The server board provides an internal 40 pin connector J3B2 to accommodate a proprietary form factor Intel Remote Management Module NIC module The following table details the pin out of the Intel RMM NIC module connector Table 26 40 pin RMM NIC Modu
11. 3 Functional Architecture The architecture and design of the Intel Server Boards S5000PSL and S5000XSL are based on the Intel S5000P and S5000X chipsets respectively These chipsets are designed for systems that use the Intel Xeon processor with system bus speeds of 667 MHz 1066 MHz and 1333 MHz The chipset contains two main components the Memory Controller Hub MCH for the host bridge and the UO controller hub for the UO sub system The chipset uses the Enterprise South Bridge ESB2 E for the I O controller hub This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server board For more information about the functional architecture blocks see the Inte S5000 Server Board Family Datasheet Revision 1 2 27 Intel order number D41763 003 Server Board Overview Storage LC Intel amp Server Boards S5000PSL and S5000XSL TPS Processors Dual Core Intel Dual Core Intel Memory FBDIMM Sockets 533 677 SAS x4 Xeon Processors 5000 sequence Xeon Processors 5000 sequence Channel A Channel B ROMB Performance SKU Only B 8 Port SAS 1066 1333 MTS PCI Express x4 or x8 Intel 5000P Memory Controller Hub x8 PCI Express 4GB s PCI Express x8 Slot 6 x16 connectors PCI Express x8 Slot 5 x4 PCI Express 2GB s PCI Express x4 Slot 4 x8 connectors x4 PCI Express 2GB s PCI
12. For more detailed platform management information see the Intef S5000 Server Board Family Datasheet Revision 1 2 51 Intel order number D41763 003 Design and Environmental Specifications NOTE RMIVMII ESB2 FML MASTER T lass ESB2 FML BLAVE FLB SR SE EN 0 OHM 90 SMBD2 SMBCLK2 i i PCI SMBUS SMBD4 SMBCLK4 SMBDS SMBCLKS AS alae FRU SDR SI AUX POWER CONN B2 V ICH6 wma ees Ft alar SMLINK SL ADDR 0X88 BB TMP141 o pHM ADDR 0X02 EMPTY T E 1 LE PWRGD uUNStuEE For ese 33V 52 7 I REPEATER S388 ILPCA9515 ft Intel Server Boards S5000PSL and S5000XSL TPS TRANSACTIONS OVER FMLO ESB2 IS SLAVE TRANSACTIONS OVER FML1 ESB2 I5 MASTER GCM3 8 lt S z ILCPAPMB OEM IPMB ADDR 0X22 ADDR OXTBD 5VSB IPMB SMBUS RISERPC SLOTS DYNAMIC BUS ADDRESSING FOR IO SLOTS FP HEADER FRU OXA4 A6 AC AE TEMP 0X98 0X9E TET OEM RMC ADDR 0X5C ADDR 0X76 4 SENSOR SMBUS CLOCK SMBUS CK410B DB800 DB1200G ADDR OXD2 ADDR OXDC ADDR OXDE HOST SMBUS Figure 16 SMBUS Block Diagram Intel order number D41763 003 SPD2 SPD DIMM 1A SEEPROM 0XA0 AMB ADDR OXBO DIMM 1D SEEPROM OXA0 AMB ADDR OXBO DIMM 2A SEEPROM OXA2 AMB ADDR OXB2 DIMM 2D SEEPROM OXA2 AMB ADDR OXB2 DIMM 3A SEEPROM OXA4 AMB ADDR OXB4 DIMM 3D SEEPROM OXA4 AMB ADDR OXB4 DIMM 4A SEEPROM OXA6 AMB ADDR OXB6 DIMM 4
13. GOST R 50377 92 Listed on one System License Russia Belarus License Listed on System License Belarus CE Low Voltage Directive 73 23 EEE Europe IRAM Certification Argentina 9 1 2 Product EMC Compliance Class A Compliance FCC ICES 003 Emissions USA Canada Verification CISPR 22 Emissions International EN55022 Emissions Europe EN55024 Immunity Europe CE EMC Directive 89 336 EEC Europe VCCI Emissions Japan AS NZS 3548 Emissions Australia New Zealand BSMI CNS13438 Emissions Taiwan GOST R 29216 91 Emissions Listed on one System License Russia GOST R 50628 95 Immunity Listed on one System License Russia Belarus License Listed on one System License Belarus 88 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications RRL MIC Notice No 1997 41 EMC amp 1997 42 EMI Korea 9 1 3 Certifications Registrations Declarations UL Certification or NRTL US Canada CB Certifications International CE Declaration of Conformity CENELEC Europe FCC ICES 003 Class A Attestation USA Canada C Tick Declaration of Conformity Australia MED Declaration of Conformity New Zealand BSMI Certification Taiwan RRL Certification Korea Ecology Declaration International 9 2 Product Regulatory Compliance Markings The Intel Server Board bears the foll
14. Intel Server Boards S5000PSL and S5000XSL TPS Event Event Offset Criticality Assert Readable Event Data Standby Reading Triggers De assert Value Type Offsets C E PCle Bus correctable OK See the Link5 error BIOS EPS Bus Degraded uncorrectable error PCle Bus correctable OK Link6 error Bus Degraded uncorrectable error PCle Bus correctable OK Link7 error Bus Degraded uncorrectable error PCle Bus correctable OK Link8 error Bus Degraded uncorrectable error PCle Bus correctable OK Link9 error Bus Degraded uncorrectable error PCle Bus correctable OK Link10 error Bus Degraded uncorrectable error PCle Bus correctable OK Link11 error See the BIOS EPS See the BIOS EPS See the BIOS EPS See the BIOS EPS EN aM See the A BIOS EPS Revision 1 2 See the BIOS EPS W Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Sensor Sensor System Sensor Type Name Number Applica bility LEE d Sensor Specific 6Fh PCle ACh Critical Link12 Interrupt 13F PCle ADh Critical Link13 Interrupt 13F Proc 1 COh Thermal h h Sensor Specific 6Fh Temperature 01h Temperature Thermal 01h Control Temperature 01h m C All Temperature Oth 0 Control 1 8 9 Proc 2 VRD Over Temp Proc 1 Vcc Proc 2 Vcc D3h Proc 1 Vcc Out of Range 0 0 0 Voltage Voltage Voltage Voltage Appendix B BMC S
15. black 8 12Vdc Yellow black Table 13 Power Supply Signal Connector Pin out J9D1 Pin Signal Color i SMS ARL3ESER Rei Table 14 P12V4 Power Connector Pin out J5A2 Pin Signal Colr 12 Vdc Yellow black 12 Vdc Yellow black Intel order number D41763 003 Design and Environmental Specifications 55 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 5 3 System Management Headers 5 3 1 Intel Remote Management Module Intel RMM Connector A 120 pin Intel RMM connector J5B1 is included on the server board to support the optional Intel Remote Management Module There is no support for third party ASMI cards on this server board Note This connector is not compatible with the Inte Server Management Module Professional Edition Product Code AXXIMMPRO or the Inte Server Management Module Advanced Edition Product Code AXXIMMADV Table 15 RMM Connector Pin out J5B1 Signal Name Pin ESB PLT RST G1 N 4 ND LPC LAD 1 LPC FRAME N LPC_LAD lt 0 gt SMB 1 3V3SB MS DAT SMB 1 3V3SB SL DAT SMB 1 3V3SB MS CLK SMB 1 3V3SB INT 56 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Signal Name FM MAN LAN TYPE1 FM MAN LAN TYPE2 MI MDC RMII SPARE MI COL RMIIB RXER MI TXER RMIIB TXEN MI MDIO RMIIB PRE
16. Description 5 GND Ground s mo Ground e SPa Dsk DSR dae setra s SPACTS mge s SA mge Revision 1 2 Intel order number D41763 003 Design and Environmental Specifications 63 Design and Environmental Specifications 5 5 7 Table 29 Internal 9 pin Serial B Header Pin out J1B1 Pin Signal Name SPB DCD DCD carrier detect SPB DSR DSR data set ready E SPB SIN L RXD receive data 3 4 s sw amp cs cTS dearosen s SPEI ament s SEN ewe L SPERIS RTS eqestiosend Keyboard and Mouse Connector Intel amp Server Boards S5000PSL and S5000XSL TPS Two stacked PS 2 ports J9A1 support a keyboard and a mouse Either PS 2 port can support a mouse or keyboard The following table details the pin out of the PS 2 connectors 64 Table 30 Stacked PS 2 Keyboard and Mouse Port Pin out J9A1 6 TP PS26 Test point keyboard mouse Mouse data 8 TPPS28 Test point keyboard mouse e foo smm Mouse clock Test point keyboard mouse Ground o Intel order number D41763 003 Revision 1 2 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 5 5 8 USB Connector The following table details the pin out of the external USB connectors JA6A1 JA6A2 found on the back edge of the server board Table 31 External USB Connector Pin
17. Generic Device present OK specific Revision 1 2 99 Intel order number D41763 003 Fan 8 Chassis Present specific Appendix B BMC Sensor Tables Intel Server Boards S5000PSL and S5000XSL TPS 8h 8h Generic Device present As and De T l 08h Fan 9 Chassis Generic Device present OK As and De T Present specific 08h Fan 10 Chassis Generic Device present OK As and De T Present specific 0 08h K Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Standby Name Number Applica Reading Triggers De assert Value bility Type Offsets 6Fh Chassis Fan Generic Redundancy O As Trig Offset A specific 04h OBh regained Redundancy Degraded lost Redundancy degraded Non red suff OK res from redund Non red suff from insuff Non red Critical insufficient Redun degrade OK from full Redun degrade from non redundant Fan 5 Chassis Generic Device present As and De T Present specific 8h Power 7 Chassis Power Supply Sensor Presence OK As and De Trig Offset X Supply specific Specific Failure Critical Status 1 6Fh Predictive fail Non Crit A C lost Critical OK 0 Fan 6 Chassis Generic Device present OK As and De T Present specific 0 Generic Device present OK As and De T 0 ii o c 100 Revision 1 2 Intel order number D41763 003 Fan 7 6 Chassis Present specific 6 4h 5h 6h 7h 8h 9h Oh Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 4
18. Server Boards S5000PSL and S5000XSL TPS 5 3 7 HDD Activity LED Header Table 21 HDD Activity LED Header Pin out J2J3 Pin Signal Name Description 1 LED SCSI CONN N HDD Activity LED Input 2 GND Ground 5 4 Front Panel Connector The server board provides a 24 pin SSI front panel connector J1E4 for use with Intel and third party chassis The following table provides the pin out for this connector Pin EN Table 22 Front Panel SSI Standard 24 pin Connector Pin out J1E4 Key P3V3 GND GND 5 5 lO Connectors 5 5 1 Revision 1 2 Signal Name P3V3 STBY FP PWR LED N LED HDD ACTIVITY N FP PWR STN N BMC RST BTN N FP ID BTN N EM SIO TEMP SENSOR FP NMI BTN N VGA Connector The following table details the pin out definition of the VGA connector J7A1 that is part of the stacked video serial port A connector FP LED STATUS AMBER N NIC1 ACT LED N NIC2 LINK LED N Table 23 VGA Connector Pin out J7A1 Signal Name i V O R CONN Red analog color signal R V IO G CONN Green analog color signal G 2 V IO B CONN Blue analog color signal B Pin i 3 pe GND GND ND ND Ground ER s oo L 5 TeMDCONVEP Nose Description Intel order number D41763 003 Design and Environmental Specifications 59 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS
19. Trying bootdeviceseleston ooe A fa Of _ R__ Tryngbootdevieseleston oo A fa fe R Tweetexdeiesdecn ODF A Ja G Trying boot device selection Pre EFI Initialization PEI Core ees IS Is ER R R Off Started dispatching early initialization modules PEIM Off Initial memory found configured and installed correctly OxE1h R R G Reserved for initialization module use PEIM OxE3h IR IR A IG Reserved for initialization module use PEIM Driver Execution Environment DXE Core DXE Drivers O O o ff Entered EFI driver execution phase DXE Started dispatching drivers lii o ff Started connecting drivers Waiting for user input n Q ff Checking password Entering BIOS setup Off Flash Update Off Calling Int 19 One beep unless silent boot is enabled Unrecoverable boot failure S3 resume failure E i ees CH Runtime Phase EFI Operating System Boot OxF8h A Operating system has requested EFI to close boot services ExitBootServices has been called OxF9h A A Operating system has switched to virtual address mode SetVirtualAddressMap has been called OxFAh A A Operating system has requested the system to reset ResetSystem has been called Pre EFI Initialization Module PEIM Recovery Ox30h of of R R Crisis recovery has been initiated because of a user request Ox31h of of Ip JA Crisis recovery has been initiated by software corrupt flash g s 112
20. 2 9Ah All Temperature Threshold Tu c nc Threshold As and De Analog R T Temp Oth 01h defined PCIe LinkO AOh Critical Sensor PCle Bus correctable OK See the Interrupt Specific LinkO error BIOS EPS 13F 6Fh Bus Degraded uncorrectable error PCle Link1 Ath Critical Sensor PCle Bus correctable OK See the Interrupt Specific Link1 error BIOS EPS AS AS 13F 6Fh Bus Degraded uncorrectable error AS AS S See the BIOS EPS PCIe Link2 A2h Critical Sensor PCle Bus correctable OK Interrupt Specific Link2 error 13F 6Fh Bus Degraded uncorrectable error a PCIe Link3 A3h Critical Sensor PCle Bus correctable K Interrupt Specific Link3 error 13F 6Fh Bus Degraded uncorrectable error PCIe Link4 A4h Critical Sensor PCle Bus correctable OK A Interrupt Specific Link4 error See the BIOS EPS See the A BIOS EPS Revision 1 2 103 Intel order number D41763 003 Appendix B BMC Sensor Tables Sensor Sensor System Sensor Type Name Number Applica bility 13F 6Fh Bus uncorrectable error PCle Link10 Critical Interrupt 13F Critical Interrupt 13F AT7h Critical Interrupt 13F A8h Critical Interrupt 13F Bh Critical Interrupt 13F Critical Interrupt 13F PCle A Critical Sensor Link11 Interrupt Specific 104 Sensor Specific 6Fh Sensor Specific 6Fh Sensor Specific 6Fh Sensor Specific 6Fh Sensor Specific 6Fh Sensor Specific 6Fh
21. Degraded Trig Offset Trig Offset Trig Offset Sparing OK Sensor Correctable As Specific ECC 6Fh Uncorrectable ECC System Sensor Correctable As S specific Specific ECC 6Fh Uncorrectable 6Fh Uncorrectable ECC System Sensor Correctable specific Specific ECC 6Fh Uncorrectable ECC Entity Sensor Entity present Sparing Presence Specific Enabled 25h 6Fh DO DIMM System Sensor Correctable specific Specific ECC E7h ECh EDh ECC EEh EFh FOh 1h NE EN Trig Offset A Revision 1 2 107 Intel order number D41763 003 Appendix B BMC Sensor Tables Intel Server Boards S5000PSL and S5000XSL TPS Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Standby Name Number Applica Reading Triggers De assert Value bility Type Offsets Sparing OCh OBh Non red suff Degraded Redun res from redund dancy Non red suff res from insuff res Non red Insuff Crtical res A B1 DIMM Entity Sensor Entity present As Trig Offset Sparing Presence Specific Enabled 25h 6Fh B1 DIMM Discrete Fully redundant Trig Offset A Spari OBh pang Non red suff Redun f dund dancy res from redun Non red suff res from insuff res Non red insuff res B01 DIMM Entity Sensor Entity present Trig Offset Mirroring Presence Specific Enabled 25h 6Fh B01 DIMM F5h All Memory Discrete Fully redundant OK As Trig Offset A Mirrori OBh Been Geh Non red suff res Degra
22. E cccccssseeeeecceeeeeeeseeessenseeeeeeeeeesesennecenees 41 3 2 1 mesure at nae Tn 42 3 2 2 Serial ATA Support ied eee kde nde PR EGER ERR ERR ede aede XE dread 44 3 2 3 Parallel ATA PATA Support certe eren irent ea net Rue EES secus 45 3 2 4 USB r2 O SUPP OMe eret e e e E n ine e oem EE 45 3 3 Video Support to FR D ERR e de PEE Re PER EIER E REO E aves andes 45 3 3 1 VidGO MOdES IE 47 3 3 2 Video Memory Interface iet wath estes eae enced Eeer 47 3 3 3 DU Al VIGGO PEUT 47 3 4 SAS sls Ur EE 48 3 4 1 SAS RAID Suppor c 48 3 4 2 SAS SATA Connector Sharing esses nennen nennen 48 3 5 Network Interface Controller NIC seen 48 3 5 1 Intel UO Acceleration Techno 49 3 5 2 MAG Address R TaLe TTT 49 3 6 Super VO VE 49 3 6 1 Setlal POorts EE 50 iv Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Table of Contents 3 6 2 Floppy Disk Controller esses 50 3 6 3 Keyboard and Mouse Support nemen 50 3 6 4 Wake Up Gontrol exei RR e e ENEE ERR ERR RR AER PR RR Pre 50 3 6 5 System Health S pport irre Ree n ENEE 50 4 Platform Management e retento Dekor diio adiac ca Conca das ad Cat cU Ca e EER Eod cO See UE 51 5 Connector Header Locations and Pin outs eese 53 5 1 Board Connector Information 53 5 2 Power CONNGCIONS conc ttr pea age eelere a 54 5 3 System Ma
23. Express Bus Segment One x4 PCI Express bus segment is directed through the ESB2 E This PCI Express segment PE1 is routed to PCI Express Slot 3 This becomes a x8 PCI Express bus segment for server boards that do not support SAS by combining PE2 with PE1 3 2 1 5 PE2 One x4 PCI Express Bus Segment One x4 PCI Express bus segment is directed through the ESB2 E This PCI Express segment PE2 is routed to PCI Express Slot 3 for server boards that do not support SAS or to the onboard SAS controller for server boards that do support SAS 3 2 1 6 PE4 PE5 Two x4 PCI Express Bus Segments Two x4 PCI Express bus segments are directed through the MCH These PCI Express segments DEZ and DER are routed to PCI Express Slot 5 3 2 1 7 PE6 PE7 Two x4 PCI Express Bus Segments Two x4 PCI Express bus segments are directed through the MCH These PCI Express segments PE6 and PE7 are routed to PCI Express Slot 6 3 2 1 8 PCI Express Riser Slot PCI Express Slot 6 supports 3 party riser cards for both 1U and 2U system configurations Two PCI Express pins are designated as Riser Type pins with the definitions noted in the table below Revision 1 2 43 Intel order number D41763 003 Design and Environmental Specifications Intel amp Server Boards S5000PSL and S5000XSL TPS SLOT 6 SETUP LP Riser TYPE 1 LP Riser Type 0 GPI ESB2 GPI 28 GPI ESB2 GPI 27 PCI E Pin B48 RSVD PCI E Pin
24. Express x4 Slot 3 133 100 MHz PCI X Slot 2 100 MHz PCI X Slot 1 Dual GbE ATI ES1000 Video Controller GJ Serial Port Int Serial Port Rear PS 2 Keyboard x8 PCI Express 4GB s x8 PCI Express 4GB s Super I O VO Controller Hub ESB2 E SAS SKU ele Storage UO e Module Connector Optional Network I O and Management Figure 10 Functional Block Diagram 28 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables 3 1 Intel 5000P 5000X Memory Controller Hub MCH The Memory Controller Hub MCH is a single 1432 pin FCBGA package which includes the following core platform functions System Bus Interface for the processor sub system Memory Controller PCI Express Ports including the Enterprise South Bridge Interface ESI FBD Thermal Management SMBUS Interface This section provides a high level overview of some of these core functions as they pertain to this server board Additional information can be obtained from the nte S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory Controller Hub Datasheet 3 1 1 System Bus Interface The MCH is configured for symmetric multi processing across two independent front side bus interfaces that connect to the Dual Core Intel Xeon processors Each front side bus on the MCH uses a 64 bit wide 667 1066 or 1333 MHz data bus The 1333 MHz data bus is capable of transferring
25. F PCI Express x8 slot 5 V System fan 4 header LL SATA 2 or SAS 0 SAS 0 on order code S5000PSLSAS only G PCI Express x8 slot 6 W System fan 3 header MM SATA 3 or SAS 1 SAS 1 on order code S5000PSLSAS only H CMOS battery X IPMB connector NN SATA 4 or SAS 2 SAS 2 on order code S5000PSLSAS only L P12V4 connector Y System fan 2 header OO SATA 5 or SAS 3 SAS 3 on order code S5000PSLSAS only J RMM connector connector for Intel Remote Management Module Z System fan 1 header PP USB port K Back panel UO ports AA Processor power connector QQ Front control panel header L Diagnostic and identify LEDs BB USB header RR SATA software RAID 5 key connector M System fan 6 header CC IDE connector SS SAS software RAID 5 key connector order code S5000PSLSAS only N System fan 5 header DD Enclosure management SATA SGPIO header TT Serial B emergency management port header O Main power connector EE Intel Local Control Panel header UU Chassis intrusion header P Auxilliary power signal connector FF Hot swap backplane B header Revision 1 2 Figure 2 Major Board Components Intel order number D41763 003 19 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS
26. Glossary Intel amp Server Boards S5000PSL and S5000XSL TPS Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first e g 82460GX with alpha entries following e g AGP 4x Acronyms are then entered in their respective place with non acronyms following ACPI Advanced Configuration and Power Interface AR GE Application Processor APIC Advanced Programmable Interrupt Control Advanced Programmable Tana Eaa OOOO Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board E Intelligent Chassis Management Bus Internal Error 118 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Glossary Term Low Pin Count Logical Unit Number Media Access Control ITP KB KCS LAN LCD LED LPC LUN MAC z UJ 1024KB Memory Controller Hub Message Digest 2 Hashing Algorithm Message Digest 5 Hashing Algorithm Higher Security MTTR Memory Type Range Register Multiplexor Network Interface Controller Nonmaskable Interrupt Output Buffer MCH MD2 i i MDS S SR l ms Mux NIC NMI
27. LED Figure 27 Diagnostic LED Placement Diagram Revision 1 2 109 Intel order number D41763 003 Appendix C POST Code Diagnostic LED Decoderlntel amp Server Boards S5000PSL and S5000XSL TPS In the below example BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Red bits 1010b Ah Green bits 1100b Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble the two are concatenated as ACh Table 47 POST Progress Code LED Example Table 48 Diagnostic LED POST Code Decoder Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber MSB Bit2 Bit i LSB Ox10h of Of Of R Power on initialization of the host processor bootstrap processor Ox11h Host processor cache initialization including AP Ox12h orf of G FR Starting application processor initialization 0x13h SMM initialization Chipset Ox21h of lof R Je Initializing a chipset component Ox22h Reading configuration data from memory SPD on DIMM Ox23h Detecting presence of memory Ox24h Of G Ip of Programming timing parameters in the memory controller Ox25h Of G JR G Configuring memory parameters in the memory controller Ox26h Optimizing memory controller settings Ox27h Initializing memory such as ECC init PCI Bus Ox50h pof Ip Of R Enumerating PCI busses 0x51h pof R fof JA Allocating resources to PCI busses 0x52h
28. Number Applica Reading Triggers De assert Value y Type Offsets BB 1 2V M S Threshold u c nc Threshold As and De Analog Vtt 01h defined BB 1 9V he Threshold u c nc Threshold As and De Analog NIC Core 01h defined BB 1 5V a Threshold u c nc Threshold As and De Analog AUX 01h defined BB 1 5V vous Threshold u I cnc Threshold As and De Analog 01h defined BB 1 8V Threshold u c nc Threshold As and De Analog 02h 01h defined BB 3 3V 15h AII Voltage Threshold u I cnc Threshold As and De Analog 02h 01h defined BB 3 3V 16h All Voltage Threshold u I c nc Threshold As and De Analog STB 02h 01h defined BB 1 5V 17h All e Threshold u I cnc Threshold As and De Analog ESB 01h defined BB 5V vous Threshold u c nc Threshold As and De Analog 01h defined BB 1 2V vos Threshold u c nc Threshold As and De Analog NIC 01h defined BB 12V 1Ah Ves Threshold u I cnc Threshold As and De Analog AUX 02h 01h defined BB 0 9V 1Bh All a Threshold Iu c nc Threshold As and De Analog 01h defined BB Vbat vous Digital 01h Limit Critical As and De Discrete exceeded BB Temp Temperature Threshold u cnc Threshold As and De Analog 01h 01h defined Temperature Threshold u c nc Threshold As and De Analog 01h 01h defined 98 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix B
29. OBF PWM RAM Pulse Width Modulation RASUM Reliability Availability Serviceability Usability and Manageability ROM RTC SDR L SE Revision 1 2 119 Intel order number D41763 003 Glossary Intel amp Server Boards S5000PSL and S5000XSL TPS SO Server Input Output SMI Server Management Interrupt SMI is the highest priority nonmaskable interrupt SMM Server Management Mode Server Management Software SIO SMI SMM We SevrWamgemniSowae SNMP Simple Network Management Protocol To Be Determined UDP UTC RD F UD Tester O UTC Umwmalmecodnae O 120 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Reference Documents Reference Documents See the following documents for additional information Intel S5000 Server Board Family Datasheet Intel Server Boards S5000PSL and S5000XSL Specification Update Intel 5000 Series Chipset Memory Controller Hub Datasheet Intel 631xESB 632xESB UO Controller Hub Datasheet Revision 1 2 121 Intel order number D41763 003
30. PS2 or USB 0x98h Off Jof R Resetting the mouse 0x99h Detecting the mouse Ox9Ah A o Je JR Detecting the presence of mouse Ox9Bh o Je Enabling the mouse Fixed Media OxBOh IR of R R Resetting fixed media device OxB1h R of Ip Disabling fixed media device 0xB2h R Io X m Detecting presence of a fixed media device IDE hard drive detection etc OxB3h R ot Enabling configuring a fixed media device Removable Media OxB8h pe TOf R R Resetting removable media device OxB9h Of Ip Disabling removable media device OxBAh A Off A Detecting presence of a removable media device IDE CDROM detection etc OxBCh A Je JR FR Enabling configuring a removable media device Boot Device Selection Revision 1 2 111 Intel order number D41763 003 Appendix C POST Code Diagnostic LED Decoderlntel amp Server Boards S5000PSL and S5000XSL TPS cuckoo Stes Re nter Description Checkpoint G Green R Red A Amber MSB Bit2 Bitt LSB lg IS of R Tree oo R R Of A Tryngbootdeviceseleston moz R R IR R Twmoboxdeesdedon 005 R IS e A Tring bootdeviceselesion x4 IR G R Tpmgboidwkesdedon oos IS Of A Twmotoxdeiesseon oo R a fe R Twmobetdeesdedon oor R a e A Tring bootdevieeseleston o A fR fo R Tweotoxdeiessenon os A IS Of A Tryngbootdeviceselecton OA fa R fe R Twmoietdeesedon DB fa R e A
31. RAID levels data stripping RAID Level 0 data mirroring RAID Level 1 and data stripping with mirroring RAID Level 10 For higher performance data stripping can be used to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers Data mirroring is used for data security Should a disk fail a mirrored copy of the failed disk is brought on line There is no loss of either PCI resources request grant pair or add in card slots With the addition of an optional Intel RAID Activation Key Intel Embedded Server RAID Technology is also capable of providing fault tolerant data stripping software RAID Level 5 such that if a SATA hard drive should fail the lost data can be restored on a replacement drive from the other drives that make up the RAID 5 pack See Figure 2 Major Board Components for the location of Intel RAID Activation Key connector location Note Availability of the Intel RAID Activation Key to support software RAID 5 will be deferred until after product launch of this server board 44 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Intel Embedded Server RAID Technology functionality requires the following items e Intel ESB 2 IO Controller Hub e Intel Embedded Server RAID Technology Option ROM e Intel Embedded Server RAID Technology II drivers most recent revision e Atl
32. Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPSAppendix C POST Code Diagnostic LED Decoder Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber MSB Bit2 Bit t LSB Ox34h om e JR JR Loading crisis recovery capsule 0x35h of G JR JA Handing off control to the crisis recovery capsule 0x3Fh Unable to complete crisis recovery Revision 1 2 113 Intel order number D41763 003 Appendix D POST Code Errors Intel Server Boards S5000PSL and S5000XSL TPS Appendix D POST Code Errors Whenever possible the BIOS will output the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware that is being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes a progress code can be customized to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The progress codes may be reported by the system BIOS or option ROMs The response column in the following table is divided into two types Pause The message is displayed in the Error Manager screen an error is logged to the SEL and user input is required to continue The user can take imme
33. Usage Procedure The CMOS Clear J1D1 and Password Reset J1D2 recovery features are designed such that the desired operation can be achieved with minimal system down time The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model Power down server Do not unplug the power cord Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait 5 seconds Move the jumper back to default position covering pins 1 and 2 Close the server chassis IU D CUT p Power up the server The password and or CMOS is now cleared and can be reset by going into BIOS setup Note Removing AC Power before performing the CMOS Clear operation will cause the system to automatically power up and immediately power down after the procedure is followed and AC power is re applied If this happens remove the AC power cord again wait 30 seconds and re install the AC power cord Power up system and proceed to the F2 BIOS Setup Utility to reset the desired settings 6 2 BMC Force Update Procedure When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event that the BMC fi
34. and De Analog defined OK Trig Offset S1 S3 S4 EE ul a Event Reading Type Threshold 01h System ACPI Power State 22h Sensor Specific 6Fh S5 G2 G3 mechanical off Button Button Power button 14h Sensor Specific 6Fh Digital Discrete 03h OEM Sensor Specific 73h Reset button SMI Timeout SMI Timeout F3h 01h State asserted Trig Offset TC device not found Sensor Failure F6h Sensor Failure UC device error detected UC bus timeout 01h State asserted NMI Signal State Digital Discrete 03h Digital Discrete 03h SMI Signal State 01h State asserted Proc 1 Status 102 Processor Sensor Specific 6Fh IERR Thermal trip Config error Presence Critical Non rec Critical ME SS LI S EM Trig Offset Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Name Number Applica Reading Triggers De assert Value bility Type Offsets Standby Proc 2 Processor Sensor IERR Critical As and De Trig Offset M Status 07h Specific Thermal trip Non rec 6Fh Config error Critical Presence OK Disabled Degraded EE 22 A 91h All Proc 1 98h All Temperature Threshold u c nc Threshold As and De Analog R T Temp 01h 01h defined Proc
35. data at up to 10 66 GB s The MCH supports a 36 bit wide address bus capable of addressing up to 64 GB of memory The MCH is the priority agent for both front side bus interfaces and is optimized for one processor on each bus 3 1 2 Processor Support The server board supports one or two Dual Core Intel Xeon processors 5000 sequence with system bus speeds of 667 MHz 1066 MHz and1333 MHz and core frequencies starting at 3 73 GHz Previous generations of the Intel Xeon processor are not supported on this server board Note Only Dual Core Intef Xeon processors 5000 Sequence that support system bus speeds of 667 MHz 1066 MHz and 1333 MHz are supported on this server board See the following table for a list of supported processors Table 2 Processor Support Matrix Processor Family System Bus Speed Core Frequency Cache Watts Support Intel Xeon Processor 5030 667MHz 2 67 GHz 2x 2 MB Revision 1 2 29 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS ni Xeon rower ge Uwe Jeer aame e ve zer Processor G Iezm i30 Ys rie xeon Processor S10 sz i56 D fe Yes meP zeon Proessors 0 es fes fame fe fe mier xeon Processors e fes D fo fe mie xeon Processor 5750 i838 286 Jg fe fe mie Xeon Processor s160 uui ao I fo Yes 3 1 2 1 Processor Population Rules When two processors are installed both must be of ide
36. n dual mode On board Video enabled Dual Monitor Video enabled the on board video controller is enabled and will be the primary video device The external video card will be allocated resources and is considered the secondary video device The BIOS Setup utility provides options to configure the feature as follows On board Video Enabled Disabled Dual Monitor Video Enabled Shaded if on board video is set to Disabled Disabled Revision 1 2 47 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 3 4 SAS Controller The SAS1064e controller supports x4 PCI Express link widths and is a single function PCI Express end point device The SAS controller supports the SAS protocol as described in the Serial Attached SCSI Standard version 1 0 The controller also supports SAS 1 1 features The SAS1064e controller supports a 32 bit external memory bus that provides an interface for Flash ROM and NVSRAM devices 3 4 1 SAS RAID Support RAID modes 0 1 and 10 are supported An optional SAS RAID Key can be used to support SW RAID 5 3 4 2 SAS SATA Connector Sharing Four SATA connectors are shared between SATA and SAS depending on the version of the server board For SAS server boards four of the six SATA connectors are used for SAS functionality For SATA server boards all six SATA connectors are used for SATA functionality 3 5 Network Interface Controller NIC
37. need not be identical in organization size and speed Sparing should be enabled in BIOS setup The BIOS will configure Rank Sparing Mode The larger of the pairs DIMM A1 DIMM B1 DIMM A2 DIMM B2 DIMM C1 DIMM D1 and DIMM C2 DIMM_D2 are selected as the spare pair units 3 1 4 Snoop Filter 5000X MCH only The 5000X version of the MCH includes a snoop filter Depending on the application of the server this feature can be used to enhance the performance of the server by eliminating traffic on the snooped system bus of the processor being snooped By removing snoops form the snooped bus the full bandwidth is available for other transactions 3 2 Enterprise South Bridge ESB2 E The ESB2 E is a multi function device that provides four distinct functions an I O controller a PCI X bridge a GB Ethernet controller and a baseboard management controller BMC Each function has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller The ESB2 E provides the gateway to all PC compatible I O devices and features The server boards use the following ESB2 E features PCI X bus interface Six channel SATA interface with SATA Busy LED Control Dual GbE MAC Baseboard Management Controller BMC Single ATA interface with Ultra DMA 100 capability Universal Serial Bus 2 0 USB interface Removable media drives LPC bus interface PC compatible t
38. out JA6A1 JA6A2 Pin Signal Name USB OC USB PWR USB PN DATALO Differential data line paired with DATAHO USB PP DATAHO Differential data line paired with DATALO One 2x5 connector on the server board J3J1 provides an option to support an additional two USB ports The pin out of the connector is detailed in the following table Table 32 Internal USB Connector Pin out J3J1 Pin Signal Name Description 5 us ess CON usb gripe su pem c c ep eee s Gm s Wm Revision 1 2 65 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 5 6 Fan Headers The server board provides four SSl compliant 4 pin and four SSI compliant 6 pin fan headers to be used as CPU and IO cooling fans 3 pin fans are supported on all fan headers 6 pin fans are supported on header J3H4 J3H3 J3H2 and J3H1 4 pin fans are supported on header J9J1 J5J1 J3H4 J3H3 J9B4 and J9B3 4 pin fans are not supported on header J3H2 and J3H1 since these headers are tied to the CPU1 PWM These fan headers should also not be used for CPU cooling fans The pin configuration for each of the 4 pin and 6 pin fan headers is identical and is defined in the following tables Two 4 pin fan headers are designated as processor cooling fans CPU1 fan J9J1 CPU2 fan J5J1 Four 6 pin fan headers are designat
39. required for their specific application and environmental conditions Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright Intel Corporation 2006 Revision 1 2 iii Intel order number D41763 003 Table of Contents Intel amp Server Boards S5000PSL and S5000XSL TPS Table of Contents DEM nulli T TE 12 1 1 Chapter Outline sais E 12 1 2 server Board Use Disclaimer 22 cioe tiet e boite tend yx aUe dons EES 12 2 Server Board OVervleW nie eae ees Eege 14 2 1 Server Board Feature Selt geg Gebees degt de dete eor Onenn 14 2 2 Server Board Layout ee etes e en REIR Ne enre ERR TM REX Dee EN 17 2 2 1 Server Board Connector and Component Layout 18 2 2 2 Server Board Mechanical Drawings sees eee eee eee eee 20 2 2 3 Server Board ATX lO Layout eee Ee GSO Se lade eee eA ONS 26 3 Functional e E TN 27 3 1 Intel 5000P 5000X Memory Controller Hub MCH 29 3 1 1 System B s Interfaeb coiere de ie at bero Epsom dada du dede dau oc Rtas 29 3 1 2 Processor le Le dE 29 3 1 3 Memory SUD Sys RE 32 3 1 4 snoop Filter 5000 X MCH Only si accepere opened eet eai thea eg pee zen de ies 41 3 2 Enterprise South Bridge ESB2
40. 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 9 Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations before computer integration make sure that the chassis power supply and other modules have passed EMC testing using a server board with a microprocessor from the same family or higher and operating at the same or higher speed as the microprocessor used on this server board The final configuration of your end system product may require additional EMC compliance testing For more information please contact your local Intel Representative This is an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 9 1 Product Regulatory Compliance Intended Application This product was evaluated as Information Technology Equipment ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product categories and environments such as medical industrial telecommunications NEBS residential alarm systems test equipment etc other than an ITE application may require further evaluation 9 1 1 Product Safety Compliance UL60950 CSA 60950 USA Canada EN60950 Europe EC60950 International CB Certificate amp Report IEC60950 report to include all country national deviations
41. 003 Video Modes Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Table 7 Video Modes The ATI ES1000 chip supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD 2D Mode Refresh Rate Hz 2D Video Mode Support 8 bpp 16 bpp 32 bpp 640x480 60 72 75 85 90 Supported Supported Supported 100 120 160 200 800x600 60 70 72 75 85 Supported Supported Supported 90 100 120 160 1024x768 60 70 72 Supported Supported Supported 75 85 90 100 1152x864 43 47 60 70 75 80 85 Supported Supported Supported 1280x1024 60 70 74 75 Supported Supported Supported 1600x1200 52 Supported Supported Supported Video Memory Interface The memory controller sub system of the ES1000 arbitrates requests from the direct memory interface the VGA graphics controller the drawing co processor the display controller the video scalar and the hardware cursor Requests are serviced in a manner that ensures display integrity and maximum CPU co processor drawing performance The server board supports a 16 MB 4 Meg x 16 bit x 4 banks DDR SDRAM device for video memory 3 3 3 Dual Video The BIOS supports single and dual video modes The dual video mode is enabled by default n single mode Dual Monitor Video disabled the on board video controller is disabled when an add in video card is detected
42. 1 3355 nen j i A n r ot rs Rr 347011385 Be ee er ee eer 33 46 1 317 lt 41 45 1 632 5854 2 305 E ES t S Z e 2 1 1 mi ri ME S L L E 28450 11201 L H Ul I EG 117 34 4 620 bd 5 um H zd S ES L N pj 2 52 14 E 24887 9 837 258 87 10 192 287 87 10546 276 87 10 9001 Nir i mE Wz 7 Fr I TT ET e I e 1 i H e r H 1 1 N E LY T LF E 2 Z S 2 5 5 S E S Z ZS Z ZS 3 a E S 2 8 g B E 8 8 2 S 8 S e FL z E Kaz AF000218 a E e amp E Figure 4 Component Positions 21 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 30480 1200 el je x 041 eg 116000 60100 45660 23680 1872 Lan 073 TYP 1MM3 COMPONENT HEIGHT 3 6 MM i i i i i LZ n H C AH uA Ee Jl J L A H p L 4 L 7 72800 J e 28661 pl 4 PA 4 Al 4 PA P A Ca L f f 30150 Le y 11870 d PA TYP E ed 4 e 4 J rd 4 f Al d A Z 32240 i LI IRSSSSSSSSpTT LE p 12693 i P PA CO SS Ow 32657 TT Es P d XN 5 TN 12857 d WANNA NNN W 4 Z Ee T T T TN s SS a S KYAAAAAAA SN NIC NS NC INS E SON RANA X i m D Hi E A t Lb i LA A Y Z LEE ED jp d 4 d 2 ow 240 533 0210
43. 12V 11 40 SETS 1 Maximum continuous total output power should not exceed 670 W 2 Maximum continuous load on the combined 12 V output shall not exceed 48 A 3 Peak load on the combined 12 V output shall not exceed 52 A 4 Peaktotal DC output power should not exceed 730 W 8 3 5 Dynamic Loading The output voltages shall remain within limits for the step loading and capacitive loading specified in the table below The load transient repetition rate shall be tested between 50 Hz and 5 kHz at duty cycles ranging from 1096 9096 The load transient repetition rate is only a test specification The A step load may occur anywhere within the minimum load to the maximum load conditions Table 41 Transient Load Requirements Output A Step Load Size Load Slew Rate Test Capacitive Load 1 Step loads on each 12V output may happen simultaneously Revision 1 2 83 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 8 3 6 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges Table 42 Capacitive Loading Conditions Minimum Maximum S a Ia pw 1 Maximum continuous total output power should not exceed 670 W 2 Maximum continuous load on the combined 12 V output shall not exceed 48 A 3 Peak load on the combined 12 V output shall not exceed 52 A 4 Peaktotal DC output power shou
44. 23 6 6190 15 0mm COMPONENT HEIGHT e EF I T LIMIT DEFINED BY DUCT Pt 178 578 7 0306 9 C EH y rN lt O 23 C E 4 EIS 2 O L 235 085 9 2553 4 9 0 mm COMPONENT HEIGHT LIMIT DEFINED BY DUCT DETAIL S e SC a a C OD QJ CS 282 585 27 0 mm COMPONENT HEIGHT 11 1254 7 LIMIT DEFINED BY DUCT DETAIL 13 0 mm COMPONENT HEIGHT LIMIT DEFINED BY DUCT DETAIL A 5 C 320040 317 580 12 5032 12 6000 SIS a 3 zx als S 3 5 or 101 402 3 9922 112 851 4 4430 Figure 8 CPU and Memory Duct Keepout Revision 1 2 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 2 2 3 Server Board ATX UO Layout The drawing below shows the layout of the rear I O components for the server board CO lo I of ECKE AF000222 A PS 2 mouse E NIC port 1 1 Gb B PS 2 keyboard F USB port 2 top 3 bottom C Serial port G NIC port 2 1 Gb D Video H USB port 0 top 1 bottom Figure 9 ATX I O Layout 26 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables
45. 3 12 V and 5 VSB The power supply uses remote sense 3 3 VS to regulate out drops in the system for the 3 3 V output The 5 V 12 V1 12 V2 12 V3 12 V and 5 VSB outputs only use remote sense referenced to the remote sense return signal The remote sense input impedance to the power supply must be greater than 200 O on 3 3 VS and 5 VS This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply Remote sense must be able to regulate out a minimum of a 200 mV drop on the 3 3 V output The remote sense return must be able to regulate out a minimum of a 200 mV drop in the power ground return The current in any remote sense line shall be less than 5 mA to prevent voltage sensing errors The power supply must operate within specification over the full range of voltage drops from the power supply s output connector to the remote sense points 82 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 8 3 4 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise Table 40 Voltage Regulation Limits Parameter Tolerance Minimum Nominal Maximum Units 3 3V 5 5 3 14 5V 5 5 4 75 5 5 11 40 5 5 11 40
46. 3 TYP 792 d 118 3 81mm MAX COMPONENT n HEIGHT RESTRICTION 2 PLACES 16 05 0632 TYP HEATSINK AREA 325 8 26mm MAX 22 COMPONENT HEIGHT RESTRICTIO 2 PLACES MAX HEIGHT OF COMPONENTS AND MATING COMPONENTS SHALL NOT EXCEED 15 24mm 600 Figure 5 Restricted Areas on Side 1 Intel order number D41763 003 HEATSINK DISSASEMBLY AREA 275 826mm MAX COMPONENT HEIGHT RESTRICTION 4 PLACES 10160 04000 GROUND PAD BOTH SIDES NO COMPONENT 8PLCS 1 433 14mm MAX COMPONENT HEIGHT RESTRICTION SOCKET AREA NO COMPONENT PLACEMENT ALLOWED 2 PLACES 93 98 370 635 0250 Revision 1 2 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables LIMITED COMPONENT HEGHT ka X 3120 1058 MAXIMUM 13 PLACES 0128 7874 310 7620 mp 20320 Lal wl 0300 0800 SEEDETAIL B 20320 0800 3 1PLCS R2540 2X 8000 GE 100 03150 0038 Tp L 49 d L NO COMPONENTS ALLOWED a mm 5 08 TRACES OKAY IN THIS REGION 26202 0200 EX TYP R14730 TP 0579 17780 700 10160 GROUND PAD 0400 NO COMPONENT 1PLACE 100 2 54 lt lt MAX COMPONENT e HEIGHTIN THESE ZONES A ES N S Nd Y 2 9652 380 5715 2250 1207 045 NN NN N Ne b 0700 0200 NO COMPONENTS T
47. 5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables Sensor Sensor System Sensor pou Event Event Offset Criticality Assert Readable Event Data Standby Name Number N rente Reading Triggers De assert Value Deeg Type Offsets Watchdog ae 2 Sensor Timer expired Trig Offset Specific status only 6Fh Hard reset Power down Power cycle Timer interrupt Platform 04h Platform Sensor Secure mode T Security Security Specific violation Violation Violation 6Fh attempt Attempt Out of band 06h access password violation FP Diag Critical Sensor Front panel NMI Interrupt Interrupt Specific diagnostic NMI 13h 6Fh interrupt Bus uncorrectable error Trig Offset System Event Sensor Log area reset Trig Offset Event Log Logging Specific cleared Disabled 6Fh 10h Session Session Audit Sensor 00h Session Audit 2Ah Specific activation 6Fh 01h Session As defined by IPMI deactivation System System Event Sensor 00 System Event 12h Specific reconfigured En 6Fh 04 PEF action ven Trig Offset Physical Chassis Physical Sensor Chassis As and De Trig Offset Security Intrusion Security Specific intrusion is chassis 05h 6Fh LAN leash lost specific 1 Revision 1 2 97 Intel order number D41763 003 Appendix B BMC Sensor Tables Intel amp Server Boards S5000PSL and S5000XSL TPS Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Standby Name
48. B PCI Express Express Ports 4 5 PE6 PE7 3 20 Gb S PCI X8 throughput PCI Express Slot 6 BNB PCI Express Express Ports 6 7 PE1 10 Gb S PCI x4 throughput PCI Express Slot 3 x8 ESB2 E PCI Express throughput for server boards that do not Express Port support SAS by combining PE2 with PE1 3 3 V 3 3 V 3 3 V 3 3 V 3 V 42 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 3 2 1 1 PCI32 32 bit 33 MHz PCI Sub system All 32 bit 33 MHz PCI I O is directed through the ESB2 E ICH6 The 32 bit 33 MHz PCI segment created by the ESB2 E ICH6 is known as the PCI32 segment The PCI32 segment supports the following embedded devices 2D Graphics Accelerator ATI ES1000 Video Controller 3 2 1 2 PXA 64 bit 133 MHz PCI Sub system One 64 bit PCI X bus segment is directed through the ESB2 E ICH6 This PCI X segment PXA is routed to PCI X Slots 1 and 2 With only one PCI X adapter populated in Slot 2 and Slot 1 left empty PCI X Slot 2 supports a maximum speed of 133MHz With both Slot 1 and Slot 2 populated Slot 2 supports a maximum speed of 100MHz PCI X Slot 1 supports a maximum speed of 100MHz even when Slot 2 is not populated 3 2 1 3 PEO One x4 PCI Express Bus Segment One x4 PCI Express bus segment is directed through the ESB2 E This PCI Express segment PEO is routed to PCI Express Slot 4 ROMB Slot 3 2 1 4 PE1 One x4 PCI
49. B49 GND 2U Riser 2 x4 PCI Express Slots 0 1 1U Riser 1 x8 PCI Express Slot 1 0 Notes 1 The server board contains a weak pull up resistor on the two Riser Type nets 2 The 2U riser card needs to pull down the PCI Express pin B48 with a 0 ohm resistor and leave as a No Connect NC PCI Express pin B49 3 The 1U riser card needs to follow the standard PCI Express Adapter pin out by leaving pin B48 as a No Connect NC and pin B49 as ground The following table provides the supported bus throughput for the given riser card used and the number of add in cards installed PCI Express Slot 6 Riser 1 add in card 2 add in cards Support 1U Riser Card X8 NA 2U Riser Card X4 X4 Note There are no population rules for installing a single add in card in the 2U riser card a single add in card can be installed in either PCI Express slot 3 2 2 Serial ATA Support The ESB2 E has an integrated Serial ATA SATA controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3 0 Gb s The six SATA ports on the server board are numbered SATA 0 thru SATA 5 The SATA ports can be enabled disabled and or configured by accessing the BIOS Setup utility during POST 3 2 2 1 Intel Embedded Server RAID Technology Il Support The onboard storage capability of this server board includes support for Intel Embedded Server RAID Technology which provides three standard software
50. BMC Sensor Tables Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Standby Name Number Applica Reading Triggers De assert Value Deeg Type Offsets BNB Temp 33h Temperature Threshold u c nc Threshold As and De Analog 01h 01h defined Tach Fan 50h Chassis Fan Threshold I c nc Threshold As and De Analog 1 specific 01h defined E Fan Chassis Threshold I c nc Threshold As and De Analog specific 01h defined SH Fan Chassis Threshold I c nc Threshold As and De Analog specific 01h defined EU Fan Chassis Threshold I c nc Threshold As and De Analog specific 01h defined Chassis Threshold I c nc Threshold As and De Analog specific 01h defined Chassis Threshold I c nc Threshold As and De Analog specific 01h defined Chassis Threshold I c nc Threshold As and De Analog specific 01h defined Threshold I c nc Threshold As and De Analog 01h defined SC Fan GH Fan GH Fan SCH Fan Chassis specific Chassis Threshold I c nc Threshold As and De Analog specific 01h defined ia Fan Chassis Threshold I c nc Threshold As and De Analog specific 01h defined D Fan Fan 1 Chassis Generic Device present As and De specific Present Chassis Generic Device present As and De specific Fan 2 Present Fan 3 Present Fan 4 Present Chassis Generic Device present OK As and De specific Chassis
51. Capacity Maximum Capacity x4 Dual Rank Mirrored Mode BGB m EEE mirrored Mode 1024 Mb 16 GB 32 GB 2048 Mb 16 GB 32 GB Note Only fully buffered DDR2 DIMMs FBDIMMs are supported on this server board See the Intel Server Board S5000PSL S5000XSL Tested Memory List for a list of supported memory for this server board 3 1 3 3 DIMM Population Rules and Supported DIMM Configurations DIMM population rules depend on the operating mode of the memory controller which is determined by the number of DIMMs installed DIMMs must be populated in pairs DIMM pairs are populated in the following DIMM slot order A1 amp B1 C1 amp D1 A2 amp B2 C2 amp D2 DIMMs within a given pair must be identical with respect to size speed and organization However DIMM capacities can be different between different DIMM pairs 34 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables For example a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 amp B1 and 1GB DIMMs installed in DIMM slots C1 amp D1 Intel supported DIMM configurations for this server board are shown in the following table IW Supported and Validated configuration Slot is populated mM Supported but not validated configuration Slot is populated Slot is not populated Mirroring Y Yes Indicates that configuration supports Memory Mirroring Sparing Y x
52. Channel C Channel A rv Channel D Branch 1 hee TP02300 Figure 13 Minimum Two DIMM Memory Configuration Note The server board supports single DIMM mode operation Intel will only validate and support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1 Revision 1 2 37 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 3 1 3 4 Non mirrored Mode Memory Upgrades The minimum memory upgrade increment is two DIMMs per branch The DIMMs must cover the same slot position on both channels DIMMs pairs must be identical with respect to size speed and organization DIMMs that cover adjacent slot positions do not need to be identical When adding two DIMMs to the configuration shown in Figure 13 above the DIMMs should be populated in DIMM sockets C1 and D1 as shown in the following diagram Populated DIMM sockets are shown in Grey Channel B Channel C Channel A 71 O Channel D TP02301 Figure 14 Recommended Four DIMM Configuration Functionally DIMM sockets A2 and B2 could also have been populated instead of DIMM sockets C1 and D1 However your system will not achieve equivalent performance Figure 13 on the previous page shows the supported DIMM configuration that is recommended because it allows both branches to operate independently and simultaneously FBD bandwidth is double
53. D SEEPROM OXA5 AMB ADDR OXB6 DIMM 1B SEEPROM 0XA0 AMB ADDR OXBO DIMM 1C SEEPROM OXAO AMB ADDR OXBO DIMM 2B SEEPROM OXA2 AMB ADDR OXB2 DIMM 2C SEEPROM OXA2 AMB ADDR OXB2 DIMM 3B SEEPROM OXA4 AMB ADDR OXB4 DIMM 3C SEEPROM ON Ad AMB ADDR OXB4 DIMM AC SEEPROM ON A6 AMB ADDR OXB6 EPROM OXA6 SPDO SPD1 SPD2 SPD3 MCH ADDR OXCO Revision 1 2 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 5 Connector Header Locations and Pin outs 5 1 Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server board Table 10 Board Connector Matrix lists all connector types available on the board and the corresponding reference designators printed on the silkscreen Table 10 Board Connector Matrix Quantity Reference Designators Connector Type Pin Count Power supply 4 Main power 24 CPU power 8 P S aux IPMB 5 P12V4 power 4 240 2 J8G1 J5G1 CPU sockets J7B1 J7B2 J7B3 J8B1 J8B2 J8B3 J9B1 JOB2 DIMM sockets 240 J2B2 J3B1 Card edge J4B2 J4B1 Card edge J1E1 J1D3 3 J3H1 J3H2 J3H3 J3H4 Header f6 ay 4 Stacked RJ45 2xUSB Stacked video 1 verial port A Serial port B Front panel Internal USB Internal USB Chassis Intrusion 1 Serial ATA SAS JA6A1 JA6A2 External LAN 22 buil
54. HIS ZONE 16 PLCS CEK HEATSINK SPRING PLATE ZONE NO COMPONENT PLACEMENT OR THROUGH HOLE LEADS ALLOWED Figure 6 Restricted Areas on Side 2 Revision 1 2 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 5 00 B 5 00 0197 0 197 3X 400 md keng 0157 i S X S es E 3X 300 i S Sc 0118 3X 10 13 0399 7 CHASSIS ID PADS Figure 7 Restricted Areas on Side 2 Detail B 24 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables 188 152 7 4076 z D S S 8 E o 8 Ka e e S 3 LI 2 Z S 3 2 B i S E D 1 S amp amp 10 160 0 4000 0 000 0 0000 3 o 14 0mm COMPONENT HEIGHT LIMIT DEFINED BY DUCT DETAIL 26 635 i 26 578 1 0464 1 0486 I S T 16 5mm COMPONENT HEIGHT lt SUPORTER 43 302 1 7048 LIMIT DEFINE BY DUCT DETAIL NO COMPONENT ALLOWED 14 0mm COMPONENT HEIGHT Wed LIMIT DEFINED BY DUCT DETAIL Ne GE 2B 97 846 1 25mm COMPONENT HEIGHT mix 8 8522 LIMIT DEFINE BY DUCT DETAIL SUPPORT AREA S NO COMPONENT ALLOWED a ig E S 143 732 L 145 600 5 7323 5 6588 L 143 136 5 6353 154 685 6 0900 FS __ NO COMPONENT ALLOWED Ei DS A xd 168 1
55. Hexavalent Chromium Polybrominated Biphenyls Diphenyl Ethers PBDE Quantity limit of 0 01 by mass 100 PPM for Cadmium 92 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Appendix A Integration and Usage Tips Appendix A Integration and Usage Tips When adding or removing components or peripherals from the server board AC power must be removed With AC power plugged into the server board 5 volt standby is still present even though the server board is powered off Processors must be installed in order CPU 1 is located near the edge of the server board and must be populated to operate the board On the back edge of the server board are four diagnostic LEDs that display a sequence of red green or amber POST codes during the boot process If the server board hangs during POST the LEDs will display the last POST event run before the hang Only Fully Buffered DIMMs FBDIMMs are supported on this server board For a list of supported memory for this server board see the Intel S5 amp 000PSL S5000XSL Tested Memory List Fora list of Intel supported operating systems add in cards and peripherals for this server board see the Inte S amp 000PSL S5000XSL Tested Hardware and OS List Only Dual Core Intel Xeon processors 5000 Series with system bus speeds of 667 1066 or 1333 MHz are supported on this server board Previous generation Intel Xeon processors
56. Intel amp Server Boards S5000PSL and S5000XSL Technical Product Specification Intel order number D41763 003 Revision 1 2 September 2006 Enterprise Platforms and Services Division Marketing ii Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL Revision History Revision History Revision Modifications Number November 2005 0 Preliminary Draft March 2006 Updated all sections with the latest product information updated illustrations added section for Regulatory Certification added appendix for Sensor Table POST Code Diagnostic LED s POST Code amp Error Handling Supported Chassis Added references for the S5000XSL 5 May 2006 1 0 Updated the Server Board picture and Block Diagram added information for which slot the ROMB card goes into added information on the HDD LED Header added information on the Snoop Filter and cleaned other general things up in the document September 2006 Updated legal disclaimer Updated Processor Table Updated Memory Section September 2006 Updated Reference Documents Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied wa
57. K Processor Mounting Revision 1 2 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 3 1 3 Memory Sub system The MCH masters four fully buffered DIMM FBD memory channels FBD memory utilizes a narrow high speed frame oriented interface referred to as a channel The four FBD channels are organized into two branches of two channels per branch Each branch is supported by a separate memory controller The two channels on each branch operate in lock step to increase FBD bandwidth The four channels are routed to sixteen DIMM sockets and are capable of supporting registered DDR2 533 and DDR2 667 FBDIMM memory stacked or unstacked The read bandwidth of each FBDIMM channel 4 25 GB s for DDR2 533 FBDIMM memory which gives a total read bandwidth of 17 GB s for four DIMM channels The read bandwidth of each FBDIMM channel 5 35 GB s for DDR2 667 FBDIMM memory which gives a total read bandwidth of 21 4 GB s for four DIMM channels On the Intel Server Boards S5000PSL and S5000XSL a pair of channels becomes a branch where Branch 0 consists of channels A and B and Branch 1 consists of channels C and D FBD memory channels are organized into two branches for support of RAID 1 mirroring Channel B Channel C Channel A T1 JW Channel D TP02299 Figure 12 Memory Layout 32 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL T
58. Of R fe R Hot Plug PCI controller initialization ox53h off R e fA Reserved for PCI bus ox54h Off A Off R Reserved for PCI bus 0x55h pof ja fof JA Reserved for PCI bus ox56h off A G Ip jReservedforPCI bus 110 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPSAppendix C POST Code Diagnostic LED Decoder Description Checkpoint MSB Bit2 Bit1 LSB oem or j fe A ResenediorPoras os e pR Tor R RmeweUsbha osn a R Of A Reenwd rUSBdeWss ATA ATAPI SATA oem G R e R Reet PATAT SATA bus andal deves oem a R e A ems O 0x5Ch e a Jof R Resetting SMBUS 0x5Dh Reserved for SMBUS Local Console 0x70h of R DRE m Resetting the video controller VGA 0x71h om R R JA Disabling the video controller VGA 0x72h Of R A R Enabling the video controller VGA Remote Console 0x78h o us Bee DRE Resetting the console controller Ox79h G E R DA Disabling the console controller Ox7Ah x R Ja IR Enabling the console controller Keyboard PS2 or USB 0x90h R Off of Resetting the keyboard LS mem R o of A Beemer CS Ox92h R o Je Re Detecting the presence of the keyboard 0x93h R o G Enabling the keyboard 0x94h R G8 fof R Clearing keyboard input buffer 0x95h R fe fof Instructing keyboard controller to run Self Test PS2 only Mouse
59. PS List of Tables To boot the system the system BIOS on the server board uses a dedicated DC bus to retrieve DIMM information needed to program the MCH memory registers The following table provides the VC addresses for each DIMM socket Table 3 UC Addresses for Memory Module SMB Go DIMM C1 OxAO DIMM C2 0xA2 3 1 3 1 Memory RASUM Features The MCH supports several memory RASUM Reliability Availability Serviceability Usability and Manageability features These features include the Intel x4 Single Device Data Correction Intel x4 SDDC for the following Memory error detection and correction Memory scrubbing Retry on correctable errors Memory built in self test DIMM sparing Memory mirroring See the Intel S5000 Server Board Family Datasheet for more information about these features Revision 1 2 33 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 3 1 3 2 Supported Memory The server board supports up to eight DDR2 533 or DDR2 667 fully buffered DIMMs FBD memory The following tables show the maximum memory configurations supported with the specified memory technology Table 4 Maximum Eight DIMM System Memory Configruation x8 Single Rank DRAM Technology Maximum Capacity Maximum Capacity x8 Single Rank Mirrored Mode Ee mirrored Mode Table 5 Maximum Eight DIMM System Memory Configuration x4 Dual Rank DRAM Technology Maximum
60. Reading Type Codes or Sensor Type Codes tables in the IPMI specification depending on whether the sensor event reading type is generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicators reveal the type of events the sensor generates As Assertions De De assertion Readable Value Offsets Readable Value indicates the type of value returned for threshold and other non discrete type sensors Readable Offsets indicate the offsets for discrete sensors that are readable with the Get Sensor Reading command Unless otherwise indicated all event triggers are readable Readable Offsets consist of the reading type offsets that do not generate events Event Data Event data is the data that is included in an event message generated by the sensor For threshold based sensors the following abbreviations are used R Reading value T Threshold value 94 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables s Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states Rearming the sensors can be done manually or automatically This column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm Default Hysteresis
61. SB 2 0 ports Four external connectors are located on the back edge of the server board One internal 2x5 header J3J1 is provided capable of supporting two optional USB 2 0 ports One USB port Type A connector J3G1 is provided to support installation of a USB device inside the server chassis An additional USB port is dedicated to the Intel Remote Management Module Intel RMM connector 3 3 Video Support The server board provides an ATI ES1000 PCI graphics accelerator along with 16 MB of video DDR SDRAM and support circuitry for an embedded SVGA video sub system The ATI ES1000 chip contains an SVGA video controller clock generator 2D engine and RAMDAC in a 359 pin BGA One 4M x 16 x 4 bank DDR SDRAM chip provides 16 MB of video memory Revision 1 2 45 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS The SVGA sub system supports a variety of modes up to 1024 x 768 resolution in 8 16 32 bpp modes under 2D It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate Video is accessed using a standard 15 pin VGA connector found on the back edge of the server board The on board video controller can be disabled using the BIOS Setup Utility or when an add in video card is installed The system BIOS provides the option for dual video operation when an add in video card is configured in the system 46 Revision 1 2 Intel order number D41763
62. SENT MI RXD3 RMIIB RXD1 MI RXD2 RMIIB RXDO MI RXD1 RMIIA RXD1 GND GND MI RXDO RMIIA RXDO GND MI TXEN RMIIA TXEN MI RXCLK MI RXER RMIIA TXER 5 3 2 LCP AUX IPMB Header Table 16 LPC AUX IPMB Header Pin out J2J1 Pin Signal Name SMB IPMB 5VSB DAT BMC IMB 5V standby data line SMB IPMB 5VSB CLK BMC IMB 5V standby clock line P5V STBY 5 V standby power Revision 1 2 57 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 5 3 3 IPMB Header Table 17 IPMB Header Pin out J4J1 Pin Signal Name SMB IPMB 5VSB DAT BMC IMB 5V Standby Data Line SMB IPMB 5VSB CLK BMC IMB 5V Standby Clock Line 5 3 4 HSBP Header Table 18 HSBP Header Pin out J1J7 J1J2 Pin Signal Name SMB IPMB 5V DAT BMC IMB 5V Data Line SMB IPMB 5V CLK BMC IMB 5V Clock Line 4 GND HSBP A Ground for HSBP A P5V HSBP B 5V for HSBP B 5 3 5 SGPIO Header Table 19 SGPIO Header Pin out J2H1 J1J5 Pin Signal Name Description 1 SGPIO CLOCK SGPIO Clock Signal 2 SGPIO LOAD SGPIO Load Signal 3 SGPIO DATAOUT SGPIO Data Out 4 SGPIO DATAIN SGPIO Data In 5 3 6 SES C Table 20 SES UC Header Pin out J1J3 Pin Signal Name Description 1 SMB SAS 3V3 DAT BMC SAS 3V Data Line 2 GND Ground 3 SMB SAS 3V3 CLK BMC SAS 3V Clock Line 58 Revision 1 2 Intel order number D41763 003 Intel amp
63. TBY is present the BMC controller on the server board requires 5 10 seconds to initialize During this time the system status LED will blink alternating between amber and green and the power button functionality of the control panel is disabled preventing the server from powering up Once 74 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications BNC initialization has completed the status LED will stop blinking and the power button functionality is restored and can be used to turn on the server Revision 1 2 75 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 7 4 DIMM Fault LEDs The server board provides a memory fault LED for each DIMM socket These LEDs are located towards the rear of the server board next to each DIMM connector
64. Table 44 Output Voltage Timing Output voltage rise time from each main output All main outputs must be within regulation of each other within this IP S time All main outputs must leave regulation within this time EM 400 1 The 5VSB output voltage rise time is from 1 0 ms to 25 ms V out 1096 V out V3 lt gt Tvout_off N H Tout rise H6 ag Tvout on TP02313 Figure 25 Output Voltage Timing Revision 1 2 85 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS Table 45 Turn On Off Timing Description o RR from AC being applied to 5VSB being within regulation iens pem 1500 Tac on delay Delay from AC being applied to all output voltages being within 2500 regulation Time all output voltages stay within regulation after loss of AC 2 mws Delay from loss of AC to de assertion of PWOK 20 ms Delay from PSON active to output voltages within regulation Ua NER LUN limits Delay from PSON deactivate to PWOK being de asserted 2 im Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on Tpwok off Delay from PWOK de asserted to output voltages 3 3V 5V 12V 12V dropping out of regulation limits Tpwok_low Duration of PWOK being in the de asserted state during an ms off on cycle using AC or the PSON signal Tsb_vou
65. The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysterisis for the sensor which can be 1 or 2 positive or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the Control Panel Status LED s Standby Some sensors operate on standby power These sensors may be accessed and or generate events when the main system power is off but AC power is present Revision 1 2 95 Intel order number D41763 003 Appendix B BMC Sensor Tables Intel amp Server Boards S5000PSL and S5000XSL TPS Table 46 BMC Sensors Event Reading Sensor Sensor System Sensor Type Name Number Applica bility Type Power Unit O1h All Power Unit Sensor 09h Specific 6Fh Status Power Unit 02h Chassis Power Unit Generic specific 09h OBh Power down Power cycle A C lost Soft power control failure Power unit failure Predictive failure Redundancy regained Non red suff res from redund Redundancy lost Redundancy degraded Non red suff from insuff Non red insufficient Redun degrade from full Redun degrade from non redundant 96 Event Offset Criticality Assert Triggers De assert Readable Value Event Data Standby Offsets i i D H Revision 1 2 Non Crit Degraded OK Critical OK Intel order number D41763 003 Intel Server Boards S
66. This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED should light up In mirrored configuration when memory mirroring takes place and system loses memory redundancy This is not covered by 2 Redundancy loss such as power supply or fan This does not apply to non redundant sub systems PCI e link errors CPU failure disabled if there are two processors and one of them fails Fan alarm Fan failure Number of operational fans should be more than minimum number needed to cool the system Non critical threshold crossed Temperature and voltage Amber Blink Non critical Non fatal alarm system is likely to fail Critical voltage threshold crossed VRD hot asserted Minimum number of fans to cool the system not present or failed In non sparing and non mirroring mode if the threshold of ten correctable errors is crossed within the window Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable DIMM failure when there is one DIMM present no good memory present Run time memory uncorrectable error in non redundant mode IERR signal asserted Processor 1 missing Temperature CPU ThermTrip memory TempHi critical threshold crossed No power good power fault Processor configuration error for instance processor stepping mismatch 7 3 1 System Status LED BMC Initialization When the AC power is first applied to the system and 5V S
67. Yes Indicates that configuration supports Memory Sparing Where x 0 Sparing supported on BranchO only 1 Sparing supported on Branch1 only 0 1 Sparing supported on both branches Notes Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1 The supported memory configurations must meet population rules defined above Revision 1 2 35 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS For best performance the number of DIMMs installed should be balanced across both memory branches For Example a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1 B1 C1 and D1 An eight DIMM configuration will perform better then a six DIMM configuration Although mixed DIMM capacities between channels is supported Intel does not validate DIMMs in mixed DIMM configurations Revision 1 2 36 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 3 1 3 3 1 Minimum Non Mirrored Mode Configuration The server board is capable of supporting a minimum of one DIMM installed However for system performance reasons Intel s recommendation is that at least 2 DIMMs be installed The following diagram shows the recommended minimum DIMM memory configuration Populated DIMM slots are shown in Grey Channel B
68. ade radit n rd etes dt ir ee aq et Ie ded 84 Ripple and Noise cest e eere Rt YD EXE Coe EP RE Pru NR didi 84 Output Voltage agi Te WEE 85 T rn COATT PUMA Gea Bees n ee ae e tote e perde de hus De doko taeda dc ER ER a oe 86 BMG SefIsO S35 de tete e ates ERE SE ERR NR E NER ERE Er Ee 96 POST Progress Code LED Example nee 110 Diagnostic LED POST Code Decoder sss sse eee 110 POST Error Messages and Handlmg 114 POST Error Beep Codes iet ct etie a RR RE tad td 116 BMG Beep Codes oe ere EC RR HERR LER YER IR UR nn due REIR ERR NUR E seuss tin aa dun 116 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables This page intentionally left blank Revision 1 2 xi Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 1 Introduction This Technical Product Specification TPS provides board specific information about the features functionality and high level architecture of the Intel Server Boards S5000PSL and S5000XSL See the InteP S5000 Server Board Family Datasheet for details about board sub systems including the chipset BIOS and server management In addition design level information for specific sub systems can be obtained by ordering the External Product Specifications EPS for a given sub system EPS documents are not publicly available and must be ordered through your local Intel representative 1 4 Chapte
69. amp RRBBSSRO po oe S amp S n zs T l e CO Hi EH D Oo CO i JU 2 i d E i r1 a E ge C 7 dB e 3 in sacer qoum WIS ETT o d E D g Uu d S Qr 39 Ce E i mmm m E AF000206 Figure 22 Processor Fault LED Locations Revision 1 2 77 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 7 6 Post Code Diagnostic LEDs POST code diagnostic LEDs are located on the back edge of the server board in the rear I O area of the server board between the PS 2 mouse keyboard stacked connectors and the video serial stacked connectors During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS will display the given POST code to the POST code diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process the Diagnostic LEDs can be used to identify the last POST process to be executed See Appendix C for a complete description of how these LEDs are read and for a list of all supported POST codes M AF000541 A Status LED D Bit 2 LED POST LED B ID LED E Bit 1 LED POST LED C MSB LED POST LED F LSB LED POST LED Figure 23 POST Code Diagnostic LED Location 78 Revisi
70. are not supported For the best performance the number of FBDIMMs installed should be balanced across both memory branches For example a four DIMM configuration will perform better than a two DIMM configuration In a four DIMM configuration FBDIMMs should be installed in DIMM sockets A1 B1 C1 and D1 An eight DIMM configuration will perform better then a six DIMM configuration e The Intel RMM connector is not compatible with the Intel Server Management Module Professional Edition Product Code AXXIMMPRO or with the Intel Server Management Module Advanced Edition Product Code AXXIMMADV Removing AC power before performing the CMOS Clear operation will cause the system to automatically power up and immediately power down after the CMOS Clear procedure is followed and AC power is re applied If this happens remove the AC power cord wait 30 seconds and then re connect the AC power cord Power up the system and proceed to the F2 BIOS Setup Utility to reset the desired settings Normal BMC functionality is disabled with the force BMC update jumper set to the enabled position pins 2 3 The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position pins 1 2 when the server is running normally When performing a BIOS update procedure the BIOS select jumper must be set
71. ber D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 7 2 Fan Fault LEDs Fan fault LEDs are present for the two CPU fans and the two rear system fans The two CPU fan fault LEDs are located next to each CPU fan header The two rear system fan fault LEDs are located next to each rear system fan header are shown in the following figure 1 il il mja m D jg mg D Ho HEH ce Se D r eee D S i O O Q EB T CM OMIM a 9 Figure 19 Fan Fault LED Locations
72. d when both branches operate in parallel 38 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 3 1 3 4 1 Mirrored Mode Memory Configuration When operating in mirrored mode both branches operate in lock step In mirrored mode branch 1 contains a replicate copy of the data in branch 0 The minimum DIMM configuration to support memory mirroring is four DIMMs populated as shown in Figure 14 above All four DIMMs must be identical with respect to size speed and organization To upgrade a four DIMM mirrored memory configuration four additional DIMMs must be added to the system All four DIMMs in the second set must be identical to the first with the exception of speed The MCH will adjust to the lowest speed DIMM 3 1 3 4 2 Sparing Mode Memory Configuration The MCH provides memory sparing capabilities Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails DIMM sparing occurs within a given bank of memory and is not supported across branches There are two supported Memory Sparing configurations Single Branch Mode Sparing Dual Branch Mode Sparing Revision 1 2 39 Intel order number D41763 003 Design and Environmental Specifications 3 1 3 4 2 1 DIMM A1 and DIMM B1 must be identical in organization size and speed DIMM A2 and DIMM B2 must be identical in organi
73. ded dancy from redund Non red suff res from insuff res Non red insuff Crtical res Note 1 Not supported except for ESB2 embedded NICs 108 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPSAppendix C POST Code Diagnostic LED Decoder Appendix C POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process the Diagnostic LEDs can be used to identify the last POST process that was executed Each POST code is represented by a combination of colors from the four LEDs The LEDs are capable of displaying three colors green red and amber The POST codes are divided into two nibbles an upper nibble and a lower nibble Each bit in the upper nibble is represented by a red LED and each bit in the lower nibble is represented by a green LED If both bits are set in the upper and lower nibbles then both red and green LEDs are lit resulting in an amber color If both bits are clear then the LED is off iim AF000541 A Status LED D Bit 2 LED POST LED B ID LED E Bit 1 LED POST LED C MSB LED POST LED F LSB LED POST
74. diate corrective action or choose to continue booting Halt The message is displayed in the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system Table 49 POST Error Messages and Handling Response 8198 Operating system boot watchdog timer expired on last boot Pause 0192 L3 cache size mismatch Halt 114 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix D POST Code Errors Error Code Response 84F2 Baseboard management controller failed to respond Pause 84F3 Baseboard management controller in update mode Pause 84F4 Sensor data record empty Pause 84FF System event log full Pause 8500 Memory Component could not be configured in the selected RAS mode 8520 DIMM_A1 failed Self Test BIST 8521 DIMM A2 failed Self Test BIST 8522 DIMM A3 failed Self Test BIST 8523 DIMM A4 failed Self Test BIST 8524 DIMM B1 failed Self Test BIST 8525 DIMM B2 failed Self Test BIST 8526 DIMM B3 failed Self Test BIST 8527 DIMM B4 failed Self Test BIST 8528 DIMM_C1 failed Self Test BIST 8529 DIMM C2 failed Self Test BIST 852A DIMM C3 failed Self Test BIST 852B DIMM C4 failed Self Test BIST 852C DIMM D1 failed Self Test BIST 852D DIMM D2 failed Self Test BIST 852E DIMM D3 failed Self Test BIST Pause 852F DIMM_D4 failed Self Test BIST Pause 8540 Memory compone
75. e common across all Intel server boards and systems that use the Intel 5000 chipset are listed in the following table Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 51 BMC Beep Codes Reason for Beep Associated Sensors Supported 1 5 2 1 CPU Empty slot population error Processor CPU Population Error Yes slot 1 is not populated 1 5 2 2 CPU No processors terminators only NA No 1 5 2 3 CPU Configuration error e g VID mismatch LONE E NA No 1 5 2 4 CPU CPU Configuration error e g BSEL mismatch error e CPU Configuration error e g BSEL mismatch BSEL mismatch N 1 5 4 2 Power fault DC power unexpectedly lost power LM Unit power unit ed good dropout failure offset NA S No 1 5 4 3 5 4 3 Chipset control failure e control failure E 5 4 4 a EE control fault TORRES Unit soft power Yes control failure offset 116 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix D POST Code Errors Appendix E Supported Intel Server Chassis The Intel Server Boards S5000PSL and S5000XSL are supported in the following Intel pedestal server chassis Intel Server Chassis SC5400 BASE Intel Server Chassis SC5400 BRP Intel Server Chassis SC5400 LX Intel Entry Server Chassis SC5299 E DP Revision 1 2 Intel order number D41763 003 117
76. east two SATA hard disk drives Intel Embedded Server RAID Technology is not available in the following configurations e The SATA controller in compatible mode e Intel Embedded Server RAID Technology II has been disabled 3 2 2 2 Intel Embedded Server RAID Technology Option ROM The Intel Embedded Server RAID Technology for SATA Option ROM provides a pre OS user interface for the Intel Embedded Server RAID Technology implementation and provides the ability for an Intel Embedded Server RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel Embedded Server RAID Technology volume s attached to the Intel RAID controller 3 2 3 Parallel ATA PATA Support The integrated IDE controller of the ESB2 E ICH6 provides one IDE channel It redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB s For this server board the IDE channel was designed to provide optical drive support to the platform The BIOS initializes and supports ATAPI devices such as LS 120 240 CD ROM CD RW and DVD ROM The IDE channel is accessed through a single standard 40 pin IDE connector J2J2 that provides the I O signals The ATA channel can be configured and enabled or disabled by accessing the BIOS Setup utility during POST 3 2 4 USB 2 0 Support The USB controller functionality integrated into ESB2 E provides the server board with the interface for up to eight U
77. ed 21h 6Fh Device installed ma Disabled Degraded Sparing OK DIMM A2 Slot Sensor Fault status Degraded Trig Offset Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded Sparing OK DIMM B1 E2h All Slot Sensor Fault status Degraded As Trig Offset A Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded Sparing OK DIMM B2 E3h All Slot Sensor Fault status Degraded Trig Offset Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded Sparing OK DIMM C1 E4h All Slot Sensor Fault status Degraded Trig Offset Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded Sparing OK DIMM C2 E5h A Slot Sensor Fault status Degraded Trig Offset Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded 106 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Name Number Applica Reading Triggers De assert Value bility Type Offsets E E IM psu DIMM D1 E6h All Slot Sensor Fault status Degraded Trig Offset A Connector Specific asserted 21h 6Fh Device installed OK Disabled Degraded Sparing OK DIMM D2 Slot Sensor Fault status Degraded Trig Offset A Connector Specific asserted Memory A Trig Offset A Error 21h 6Fh Device installed OK Trig Offset Disabled
78. ed as hot swap system fans Hot swap system fan 1 J3H4 Hot swap system fan 2 J3H3 Hot swap system fan 3 J3H2 Hot swap system fan 4 J3H1 Two 4 pin fan headers are designated as rear system fans System fan 5 J9B4 System fan 6 J9B3 Table 33 SSI 4 pin Fan Header Pin out J9J1 J5J1 J9B3 J9B4 Pin Signal Name Power supply 12 V erate hi 3 FAN TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM Out FAN_PWM signal to control fan speed Table 34 SSI 6 pin Fan Header Pin out J3H1 J3H2 J3H3 J3H4 Pin Signal Name BL A EENEG 3 FanTach in FAN TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM Out FAN PWM signal to control fan speed 6 Fan Fault LED Lights the fan fault LED Note Intel Corporation server boards support peripheral components and contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these 66 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air fl
79. ensor Tables Readable Value Event Offset Criticality Assert Event Data Standby Triggers De assert Offsets mergi fi uncorrectable error Bus correctable OK As See the A error BIOS EPS Bus Degraded uncorrectable error Bus correctable OK As See the A error BIOS EPS Bus Degraded uncorrectable error u c nc Threshold As and De Analog Trig Offset defined u c nc Threshold As and De Analog Trig Offset defined 01h Limit Non Critical a DN Trig Offset exceeded Non Critical Trig Offset u c nc Threshold As and De Analog R defined u I c nc Threshold As and De Analog R defined R Event Reading Type PCle Link12 PCle Link13 Threshold 01h Threshold 01h Digital Discrete 05h Digital Discrete 05h Threshold 01h Threshold 01h Digital Discrete 05h Digital Discrete 05h 01h Limit exceeded 01h Limit exceeded p EM ii Revision 1 2 Intel order number D41763 003 T T T T 01h Limit exceeded Appendix B BMC Sensor Tables Intel Server Boards S5000PSL and S5000XSL TPS Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Standby Name Number Applica Reading Triggers De assert Value bility Type Offsets D8h All CPU Processor Generic 01h State Critical As and De Population 07h 03h asserted Error DIMM A1 Slot Sensor Fault status pes i Trig Offset Connector Specific assert
80. er of the power supply The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions Table 39 550 W Load Ratings ep xm cmm Te Continuous Continuous 333V 15A E T 5V R JAA 12v3 osa 14A 32V Ins SA Maximum continuous total DC output power should not exceed 550 W Maximum continuous combined load on 3 3 VDC and 5 VDC outputs shall not exceed 140W Maximum peak total DC output power should not exceed 660W Peak power and current loading shall be supported for a minimum of 12 seconds Maximum combined current for the 12 V outputs shall be 41 A Peak current for the combined 12 V outputs shall be 50A Oh e h c Revision 1 2 81 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 8 3 1 Grounding The grounds of the pins of the power supply output connector provide the power return path The output connector ground pins is connected to safety ground power supply enclosure This grounding should is designed to ensure passing the maximum allowed common mode noise levels 8 3 2 Standby Outputs The 5 VSB output shall be present when an AC input greater than the power supply turn on voltage is applied 8 3 3 Remote Sense The power supply has remote sense return to regulate out ground drops for all output voltages 3 3 V 5 V 12 V1 12 V2 12 V
81. f the product ERR SSES UE bh EERE REFERS FRESE Hisar CAES RA KARL BAR 9 3 6 RRL Korea Following is the RRL certification information for Korea 1 71719 EC ER MIC 4 3 SC EECH 5 HENES English translation of the notice above re D Type of Equipment Model Name On License and Product Certification No On RRL certificate Obtain certificate from local Intel representative Name of Certification Recipient Intel Corporation Date of Manufacturer Refer to date code on product Manufacturer Nation Intel Corporation Refer to country of origin marked on product oO Rom Revision 1 2 91 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 9 3 7 CNCA CCC China The CCC Certification Marking and EMC warning is located on the outside rear area of the product A 9 4 Restriction of Hazardous Substances ROHS Compliance Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002 95 EC Compliance is based on declaration that materials banned in the RoHS Directive are either 1 below all applicable substance threshold limits or 2 an approved pending RoHS exemption applies Note RoHS implementation details are not fully defined and may change Threshold limits and banned substances are noted below Quantity limit of 0 1 by mass 1000 PPM for Lead Mercury
82. h Intel Server Boards S5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables Sensor Sensor System Sensor Type Event Event Offset Criticality Assert Readable Event Data Name Number Applica Reading Triggers De assert Value bility Type Offsets Configuration Non Crit a a ee ee Power 71h Chassis Power Supply Sensor Presence OK As and De Trig Offset Supply specific Specific Failure Critical Status 2 6Fh Predictive fail Non Crit A C lost Critical Standby X Configuration Non Crit error Chassis Current Threshold Threshold As and De A specific 03h 01h defined Chassis Current Threshold Threshold As and De A specific 03h 01h defined Power Nozzle Power Supply 1 Power Supply 2 Power Chassis Current Threshold Threshold As and De Gauge specific 03h Oth defined 7 Chassis Other Units Threshold Threshold As and De specific OBh Oth defined V1 rail Revision 1 2 101 12v Intel order number D41763 003 Power 7Ah Chassis Current Threshold Threshold As and De Gauge specific 03h 01h defined V1 rail 12v Power Supply 1 Ch Appendix B BMC Sensor Tables Sensor Sensor System Sensor Type Name Number Applica bility Power Chassis Other Units Gauge specific OBh aggregate power Power Supply 2 Intel Server Boards S5000PSL and S5000XSL TPS Readable Value Event Offset bed Assert Event Data Standby Triggers De assert Offsets u c nc eme As
83. imer counter and DMA controllers APIC and 8259 interrupt controller Power management Revision 1 2 41 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS System RTC General purpose UO This section describes the function of most of the listed features as they pertain to these server boards For more detail information see the Intel 5000 Server Board Family Datasheet or the Intel 631XESB 632xESB I O Controller Hub Datasheet 3 2 1 PCI Sub system The primary I O buses for the server board are PCI PCI Express and PCI X with six independent PCI bus segments The PCI buses comply with the PC Local Bus Specification Revision 2 3 The table below lists the characteristics of the PCI bus segments Details about each bus segment follow the table Table 6 PCI Bus Segment Characteristics PCIBus Segment Voltage Width Speed Type PCI I O Card Slots PCI32 3 3 V 32 bit 33 MHz PCI None Used internally for video controller Ee JI ITT ET PXA 3 3V 5 0V 64 bit 100 MHz PCI X PCI X Slot 1 PXA 3 3V 5 0V 64 bit 133 MHz PCI X PCI X Slot 2 X4 10 Gb S PCI X4 throughput PCI Express Slot 4 ROMB Express Slot ESB2 E PCI Express Port PE2 ESB2 E PCI Express Port2 DEA PES 10 Gb S PCI x4 throughput to onboard SAS re routed Express to Slot 3 for server boards that do not support SAS 20 Gb S PCI X8 throughput PCI Express Slot 5 BN
84. in out JAGA1 JAGA7 sees 60 Table 25 IDE 40 pin Connector Pin out J2J2 sse eee 60 Table 26 40 pin RMM NIC Module Connector Pin out LI3B7 sees 61 Table 27 SATA SAS Connector Pin out J1J1 J1H2 J1H1 J1G2 J1G1 J1F2 63 Table 28 External DB9 Serial A Port Pin out J7A1 esee 63 Table 29 Internal 9 pin Serial B Header Pin out GI1BI L eeeeeeeeeeeeeeeeeeeeeeeaaaees 64 Table 30 Stacked PS 2 Keyboard and Mouse Port Pin out J9A1 sss eee 64 Table 31 External USB Connector Pin out JA6A1 JADAT eee eee 65 Table 32 Internal USB Connector Pin out 31 65 Revision 3 7 i Intel order number D41763 003 List of Tables Intel amp Server Boards S5000PSL and S5000XSL TPS Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 SSI 4 pin Fan Header Pin out J9J1 J5J1 J9B3 JOBS cece eee eeeeeeeeeeeeees 66 SSI 6 pin Fan Header Pin out J3H1 J3H2 J3H3 DHA 66 Server Board Jumpers J1C3 J1D1 J1D2 J1E3 e 68 System Status LED M DS ieren eebe 74 Server Board Design Specifications 79 Intel Xeon Processor Dual Processor TDP Guidelines cccccccceccseeeceeeseseceeeeeeee 81 550 W Load le Le CT 81 Voltage Regulation Limits dre OASE REENEN 83 Transient Load Reourements eene 83 Capacitive Loading COhdlllOFis ee e L
85. ision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 8 2 1 Processor Power Support The server board supports the Thermal Design Point TDP guideline for Intel Xeon processors The Flexible Motherboard Guidelines FMB has also been followed to help determine the suggested thermal and current design values for anticipating future processor needs The following table provides maximum values for Icc TDP power and Tcase for the dual core Intel Xeon processor 5000 sequence family Table 38 Intel Xeon Processor Dual Processor TDP Guidelines TDP Power Max TCASE lee MAX k Note These values are for reference only The Dual Core Intel Xeon processor 5000 sequence Datasheet contains the actual specifications for the processor If the values found in the Dual Core Intel r Xeon r processor 5000 sequence Datasheet are different than those published here the Dual Core Intel r Xeon r processor 5000 sequence Datasheet values will supersede these and should be used 8 3 Power Supply Output Requirements This section is for reference purposes only The intent is to provide guidance to system designers to determine a power supply for use with this server board This section specifies the power supply requirements Intel used to develop a power supply for its 5U server system The combined power of all outputs shall not exceed the rated output pow
86. lation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception 9 3 2 ICES 003 Canada Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe B prescrites dans la norme sur le mat riel brouilleur Apparei
87. ld not exceed 730 W 8 3 7 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of OHz to 20MHz at the power supply output connectors A 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor are placed at the point of measurement Table 43 Ripple and Noise 1 Maximum continuous total output power should not exceed 670 W 2 Maximum continuous load on the combined 12 V output shall not exceed 48 A 3 Peakload on the combined 12 V output shall not exceed 52 A 4 Peaktotal DC output power should not exceed 730 W 8 3 8 Timing Requirements The following are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tyout rise within 5 to 70 ms 5 VSB is allowed to rise from 1 0 to 25 ms All outputs must rise monotonically Each output voltage shall reach regulation within 50 ms Tout on of each other during turn on of the power supply Each output voltage shall fall out of regulation within 400 msec Tyout of of each other during turn off The following tables and diagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied 84 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications
88. le Connector Pin out J3B2 Pin Signal Name Pin Signal Name 1 FM MAN LAN TYPE2 2 FM MAN LAN TYPE Revsioni 2 6 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS Pin Signal Name Pin Signal Name P3V3 AUX MIL COL RMIIB RXER P3V3 AUX MI CRS RMIIB CRS P3V3 AUX MI TXER RMIIB TXEN 62 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS 5 5 5 The pin configuration for each connector is identical and is defined in the following table 5 5 6 SATA SAS Connectors The server board provides up to six SATA SAS connectors SATA 0 J1J1 SATA 1 J1H2 SATA 2 SAS 0 SATA 3 SAS 1 SATA 4 SAS 2 SATA 5 SAS 3 J1H1 J1G2 J1G1 J1F2 ee Table 27 SATA SAS Connector Pin out J1J1 J1H2 J1H1 J1G2 J1G1 J1F2 Pin Signal Name GND Ground 1 SATA SAS TX P C Positive side of transmit differential pair SATA SAS TX N C Negative side of transmit differential pair GND 4 Ground SATA SAS RX N C Negative side of receive differential pair 6 SATA SAS RX P C Positive side of receive differential pair Serial Port Connectors The server board provides one external DB9 Serial A port J7A1 and one internal 9 pin serial B header J1B1 The following tables define the pin outs Table 28 External DB9 Serial A Port Pin out J7A1 Pin SignalName
89. le Positions MM c m 20 Component Positions o erede ee t ere e P e ey ea Ee Ye n erede 21 Restricted Areas on Side 1 crc ene Lees Eta n ku e Sog ee EY CIN RR EE RR ENEE 22 Restricted Areas on Side sos e iae t ec esee ome tans atu teat Re beca 23 Restricted Areas on Side 2 Detail B eene 24 CPU and Memory Duct Keepout sse eee eee 25 P MO TRAY cot HL Quant ea teignah Gude di a mebieGh oi thee ch eal 26 Functional Block Diagrarri rite t RR ER UO RIDERE PE e Magnan 28 GBEK Processor Mounting 5 i tete tt petri eb tpe toe epe der o SM Ec Rd 31 MUERE 32 Minimum Two DIMM Memory Confouraton 37 Recommended Four DIMM Configuration sss sese ee ee eee eee eee 38 Single Branch Mode Sparing DIMM Configuration sees eee eee eee 40 zoMBUS Black DISP Brito cod peni rebas Rte Ito dele EE Leod Loa tatto n fedi 52 Jumper Blocks 163 JTD T J1D2 J1E32 EE 68 5 Volt Standby Status LED Location eite c tte 71 RH LED E e EC E 72 System ID LED and System Status LED Locations 73 DIMM Fault LED Locations rte et En etd e pace eck 76 Processor Fault E e 7T POST Code Diagnostic LED Locatioh reiecit tert RR ey ate de a due 78 Power Distribution Block Diagram sss sse eee eee 80 Output Voltage Hin e EE 85 Turn On Off Timing Power Supply Signals eem 86 Diagnostic LED Placement Diagram sse eee eee 109 Revision 1 2 Intel order number D41763 003
90. ller interface However the system BIOS recognizes USB floppy devices 3 6 3 Keyboard and Mouse Support Dual stacked PS 2 ports are provided on the back edge of the server board for keyboard and mouse support Either port can support a mouse or keyboard Neither port supports hot plugging 3 6 4 Wake up Control The super I O contains functionality that allows various events to power on and power off the system 3 6 5 System Health Support The super I O provides an interface via GPIOs for BIOS and system management firmware to activate the diagnostic LEDs the FRU fault indicator LEDs for processors FBDIMMS fans and the system status LED See section 7 for the location of the LEDs on the server board The super UO provides PMW fan control to the system fans monitors tach and presence signals for the system fans and monitors server board and front panel temperature 50 Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 4 Platform Management The platform management sub system is based on the integrated Baseboard Management Controller features of the ESB2 E The on board platform management sub system consists of communication buses sensors system BIOS and server management firmware The following diagram provides an overview of the Server Management Bus SMBUS architecture used on this server board See Appendix B for on board sensor data
91. ls Num riques NMB 003 dict e par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications 90 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 9 3 3 Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 9 3 4 VCCI Japan TORE HHUBRESE RS E LRR RZ LV CC II DEH CHOC VAFABRRMHRECT COREL ZXEIRSC RHSTOSCC 2BMCLTIETH Code det a SIE RIE LC ASNA amEetspamROCC DeUt4 BW IR SN BBS 71T AC IE L LRN U IRURE L CTE SL English translation of the notice above This is a Class B product based on the standard of the Voluntary Control Council for Interference VCCI from Information Technology Equipment If this is used near a radio or television receiver in a domestic environment it may cause radio interference Install and use the equipment according to the instruction manual 9 3 5 BSMI Taiwan The BSMI Certification Marking and EMC warning is located on the outside rear area o
92. n with the BMC Force Update jumper set in this position This jumper setting should only be used when the standard firmware update process fails This jumper should remain in the default disabled position when the server is running normally 6 3 BIOS Select Jumper The jumper block at J1C3 located at the left of PCI X slot 1 is used to select which BIOS image the system will boot to Pin 1 on the jumper is identified with a Y This jumper should only be moved if you want to force the BIOS to boot to the secondary bank which may hold a different version of BIOS The rolling BIOS feature of the server board will automatically alternate the boot BIOS to the secondary bank if the BIOS image in the primary bank is corrupted and cannot boot 70 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 7 Intel Light Guided Diagnostics The server boards have several on board diagnostic LEDs to assist in troubleshooting board level issues This section provides a description the location and function of each LED on the server board For a more detailed description of what drives the diagnostic LED operation see the InteP S5000 Server Board Family Datasheet 7 1 5 Volt Standby LED Several server management features of this server board require that a 5 volt stand by voltage be supplied from the power supply Some of the features and components that requi
93. nagement Headers sse 56 5 3 1 Intel Remote Management Module Intel RMM Connector 56 5 3 2 LOP FAUX TE resin cocotte dn ceto ber eeu teet eut cto T P PER pr sae ds 57 5 3 3 PMB Head E 58 5 3 4 ASB E Le EE 58 5 3 5 SGBIO Fleader nte tote t Eh eee perde SoA ed Hives RNAS ev deed 58 BOG JSESTO AE titudo otc cna Lo CUM E ciae 58 5 3 7 HDD Activity Re Ee EE 59 5 4 Front Panel Connector nre e Ex ERR ER ENEE SEN EEN BCEE 59 5 5 l O Connectors 4er EE TE rer e EE AT 59 5 5 1 bier Wege E 59 5 5 2 Nexerngeterseee UMS 60 5 5 3 IDE e ele ioo trea 60 5 5 4 Intel Remote Management Module NIC Connector 61 5 5 5 SATA SAS Connectors rci D eO V ERE RR EXE RE XXE AER YR MER XR eH Y RS 63 5 5 6 Serial Port Connectors t ent er d Rd E Ra ee ca USED s 63 5 5 7 Keyboard and Mouse Connector eee eee eee 64 5 5 8 USB iGOMMECIOM ET 65 5 6 Fan ale creation 66 6 Id lbrls cae 68 6 1 CMOS Clear and Password Reset Usage Procedure sese 69 6 2 BMC Force Update Procedure seems 69 6 3 BIOS Select JUMPED reinsar eae rt uti t att ete e ES 70 7 Intel Light Guided Diagnostics ss ssscsssssessssssrsesesesssessssearseseseestersesearaetessestaeateranaets 71 T 1 Rel Standby PED EEN 71 7 2 SCIENCE RTE 72 7 3 System ID LED and System Status LED 73 Revision 1 2 v Intel order number D41763 003 Table of Contents Intel amp Server Boards S5000PSL and S5000XSL TPS
94. nditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Revision 1 2 13 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 2 Server Board Overview The Intel Server Boards S5000PSL and S5000XSL are monolithic printed circuit boards with features that support the pedestal server markets 2 4 Server Board Feature Set Table 1 Server Board Features Feature 11 0Jg GI Descipin 5 Processors Socket J 771 pin LGA sockets supporting one or two Dual Core Intel Xeon processors 5000 sequence with system bus speeds of 667 MHz 1066 MHz and 1333 MHz Memory Eight DIMM sockets supporting fully buffered DIMM technology FBDIMM memory 240 pin DDR2 533 and DDR2 677 FBDIMMs can be used Chipset Intel 5000P Memory Controller Hub Server Board S5000PSL only Intel 5000X Memory Controller Hub Server Board S5000XSL only Intel ESB2 E UO Controller 14 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables Feature 3 10 Bescipin On board External connections Connectors Headers Stacked PS 2 ports for keyboard and mouse Stacked video DB9 serial port A connector Two RJ45 2xUSB connectors for 10 100 1000 Mb and USB 2 0 support O
95. ne USB 2x6 pin header which supports two USB ports One USB port Type A connector One DH10 serial port B header Six SATA 2 connectors with integrated RAID 0 1 and 10 support order code S5000PSLSATA only Software RAID 5 support through an optional SATA RAID KEY this feature is currently not supported and will be made available after production launch Two SATA 2 connectors and four SATA 2 SAS connectors with integrated RAID 0 1 and 10 support order code S5000PSLSAS only Software RAID 5 support through an optional SAS RAID KEY order code S5000PSLSAS only this feature is currently not supported and will be made available after production launch One ATA100 40 pin connector One RMM connector to support the optional Intel Remote Management Module One I O connector supporting an optional RMM NIC UO module SSI compliant front panel header SSI compliant 24 pin main power connector supporting the ATX 12 V standard on the first 20 pins Add in PCI PCI X PCI One full length full height PCI X 64 bit slot with up to 133 MHz support when Express Cards only one PCI X slot is populated One full length full height PCI X 64 bit slot with up to 100 MHz support One full length full height PCI Express x8 x4 throughput x8 x8 throughput with order code S5000PSLSATA slot One half length full height PCI Express x8 x8 throughput slot Two full length full height PCI Express x16 x8 throughput slots Hard Drive Suppor
96. ng parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Revision 1 2 79 Intel order number D41763 003 Design and Environmental Specifications Intel amp Server Boards S5000PSL and S5000XSL TPS 8 2 Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel Server Boards S5000PSL and S5000XSL including voltage and current specifications and power supply on off sequencing characteristics The following diagram shows the power distribution implemented on these server boards CPU1 P3V3 AUX VRD 11 0 PCI EXPRESS PCI X 1 5V AUX VREG Mech P1V5 AUX ESB2 BMC ICH6 GILGAL CPU1 FAN P1VB8 NIC CPU2 VRD 11 0 1 2 AUX P1V2 NIC ACTIVE 0 58A STANDBY 2 05A CPU2 FAN 5V STBY PSVSTBY 3 3V STBY _P3V3_STBY VREG 40A PIW 12V FROM P5V_STBY S3 FB DIMM 24 PIN CONN 18V VREG pava 1 2V AUX 3 3V P1V2 VDOG AT RN50 VREG CORE 15A 25V aux VH MEMORY VO 12V FROM P 3 25A 4 PIN CONN 48V vreal R An RINGO PCIE SLOT 03A PCI X SLOT SYSTEM FANSI 9 BNB FB sx ioc FB DIMM Figure 24 Power Distribution Block Diagram 80 Rev
97. nt lost redundancy during the last boot Pause 8580 DIMM Ad1 correctable ECC error encountered Pause 8581 DIMM A2 correctable ECC error encountered Pause 858C DIMM D1 correctable ECC error encountered Pause 858D DIMM D2 correctable ECC error encountered Pause Pause Pause Pause Pause c l lt Pause 3 Pause Pause Pause c l Pause Pause Pause Pause c l Pause Pause S Pause 8602 Watchdog timer expired secondary BIOS may be bad Pause 8603 Secondary BIOS checksum fail Pause Revision 1 2 115 Intel order number D41763 003 Appendix D POST Code Errors Intel Server Boards S5000PSL and S5000XSL TPS POST Error Beep Codes The following table lists POST error beep codes Prior to system Video initialization BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on POST Progress LEDs Table 50 POST Error Beep Codes POST Progress Code 3 Memory error System halted because a fatal error related to the memory was detected BIOS rolling back The system has detected a corrupted BIOS in the flash error part and is rolling back to the last good BIOS The BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Codes that ar
98. ntical revision core voltage and bus core speed When only one processor is installed it must be in the socket labeled CPU1 The other socket must be empty The board is designed to provide up to 130A of current per processor Processors with higher current requirements are not supported No terminator is required in the second processor socket when using a single processor configuration 3 1 2 2 Common Enabling Kit CEK Design Support The server board complies with Intel s Common Enabling Kit CEK processor mounting and heatsink retention solution The server board ships with a CEK spring snapped onto the underside of the server board beneath each processor socket The heatsink attaches to the CEK over the top of the processor and the thermal interface material TIM See the figure below for the stacking order of the chassis CEK spring server board TIM and heatsink The CEK spring is removable allowing for the use of non Intel heatsink retention solutions 30 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables Note The processor heat sink and CEK spring shown in the following diagram are for reference purposes only The actual processor heat sink and CEK solutions compatible with this generation server board may be of a different design Heatsink assembly Thermal Interface Material TIM Server Board 3 AF000196 Figure 11 CE
99. on 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 8 Design and Environmental Specifications 8 1 Server Boards S5000PSL and S5000XSL Design Specifications The operation of the server boards at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 37 Server Board Design Specifications DC Voltage 5 of all nominal voltages Shock Packaged 20 pounds 36 inches 20 to 40 pounds 30 inches 40 to 80 pounds 24 inches 80 to 100 pounds 18 inches 100 to 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note Chassis design must provide proper airflow to avoid exceeding the Dual Core Intel Xeon processor 5000 sequence maximum case temperature Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operati
100. ow required for their specific application and environmental conditions Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Revision 1 2 67 Intel order number D41763 003 Design and Environment al Specifications Intel Server Boards S5000PSL and S5000XSL TPS 6 Jumper Blocks The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board Pin 1 on each jumper block can be identified by the following symbol on the silkscreen V BIOS Bank Select Force Lower Bank Normal Operation default J CMOS Clear Q Disable Enable e Oo J1D1 Password Clear L Protect Clear E BMC Force Update O Disable 1 Enable z m D eaaa ee 10 p HHE
101. owing regulatory marks Regulatory Compliance Region Marking UL Mark USA Canada CE Mark Europe C EMC Marking Class A Canada CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A BSMI Marking Class A Taiwan BAGH BHOSLE bp ERR He BAS AER MAAS GSB FAES HERRN BD SOAR C tick Marking Australia New Zealand RRL MIC Mark Korea Country of Origin Exporting Requirements Made in xxxxx Provided by label not silkscreen Model Designation Regulatory Identification Examples Server Board S5000PSL for boxed type boards or Board PB number for non boxed boards typically high end boards Revision 1 2 89 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 9 3 Electromagnetic Compatibility Notices 9 3 1 FCC Verification Statement USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 Phone 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential instal
102. r Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 Platform Management Chapter 5 Connector and Header Location and Pin out Chapter 6 Configuration Jumpers Chapter 7 Light Guided Diagnostics Chapter 8 Power and Environmental specifications Chapter 9 Regulatory and Certification Information Appendix A Integration and Usage Tips Appendix B BMC Sensor Tables Appendix C POST Code Diagnostic LED Decoder Appendix D POST Code Errors e Appendix E Supported Intel Server Chassis 1 2 Server Board Use Disclaimer Intel Corporation server boards support add in peripherals and contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server 12 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental co
103. re this voltage be present when the system is Off include the BMC within the ESB2 E onboard NICs and optional RMM connector with Intel RMM installed The LED is located just to the right of the CMOS Battery in the center of the server board and is labeled 5VSB LED is illuminated when AC power is applied to the platform and 5 volt standby voltage is supplied to the server board by the power supply n 9 9 I i 22285992 pen pen a To Hz l E MT i D E zl is Il B I i i i 9 O O n D HO H i E AECH i de l m m Gc He B i SU HUE II A GO Exc kz Figure 18 5 Volt Standby Status LED Location Revision 1 2 71 Intel order num
104. rk data more efficiently through Dual Core Intel Xeon processor 5000 sequence based servers for improved application responsiveness across diverse operating systems and virtualized environments Intel I OAT improves network application responsiveness by unleashing the power of Dual Core Intel Xeon processors 5000 sequence through more efficient network data movement and reduced system overhead Intel multi port network adapters with Intel I OAT provide high performance UO for server consolidation and virtualization via stateless network acceleration that seamlessly scales across multiple ports and virtual machines Intel I OAT provides safe and flexible network acceleration through tight integration into popular operating systems amp virtual machine monitors avoiding the support risks of 3rd party network stacks and preserving existing network requirements such as teaming and failover 3 5 2 MAC Address Definition Each Intel Server Board S5000PSL S5000XSL has four MAC addresses assigned to it at the Intel factory During the manufacturing process each server board will have a white MAC address sticker placed on the board The sticker will display the MAC address in both bar code and alpha numeric formats The printed MAC address is assigned to NIC 1 on the server board NIC 2 is assigned the NIC 1 MAC address 1 Two additional MAC addresses are assigned to the Baseboard Management Controller BMC embedded in the ESB 2 These MAC addre
105. rmware update process fails due to the BMC not being in the proper update state the server board provides a BMC Force Update jumper J1E3 which will force the BMC into the proper update state The following procedure should be following in the event the standard BMC firmware update process fails Power down and remove the AC power cord 2 Open the server chassis See your server chassis documentation for instructions Move jumper from the default operating position covering pins1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC cord and power up the server Perform the BMC firmware update procedure as documented in the README TXT file that is included in the given BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating that the BMC is still in update mode Revision 1 2 69 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 7 Power down and remove the AC power cord 8 Open the server chassis 9 Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server Note Normal BMC functionality is disabled with the Force BMC Update jumper is set to the enabled position The server should never be ru
106. rranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Server Boards S5000PSL and S5000XSL may contain design defects or errors known as errata which may cause the product to deviate from published specifications Refer to the Intel amp Server Boards S5000PSL and S5000XSL Specification Update for published errata Intel Corporation server baseboards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow
107. s eee eee 91 scr MER CC apace E 91 9 35 IR Kawaii EE 91 9 3 6 ESL KOIG d otro sepe dut eC Et CM did 91 S37 VONOAT OCG GhISa sius dee eR REF lg D RR MN GS IN ED 92 9 4 Restriction of Hazardous Substances RoHS Compliance 92 Appendix A Integration and Usage Tips censes nennen nnn 93 Appendix B BMC Sensor Tables eeeeeeeeeee eese eeeee esee eene nenne nnn e eenn eee 94 vi Revision 1 2 Intel order number D41763 003 Intel Server Boards S5000PSL and S5000XSL TPS Table of Contents Appendix C POST Code Diagnostic LED Decoder eene 109 Appendix D POST Gode Errors n dee Ee ee rere 114 Appendix E Supported Intel Server Chassis essent rennen tenente nnne 117 LIII DE 118 Reference DOOGUmehnls 5 n ceni eege KU dx culla d VSS EIN CLER E MTS qe a ania 121 Revsioni 2 5 02 2 wi Intel order number D41763 003 List of Figures Intel Server Boards S5000PSL and S5000XSL TPS List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 viii server Board Ree ge Ee ET 17 Major Board Components ette eee 19 Mounting Ho
108. sses are used by the BMC s embedded network stack to enable IPMI remote management over LAN BMC LAN Channel 1 is assigned the NIC1 MAC address 2 and BMC LAN Channel 2 is assigned the NIC1 MAC address 3 3 6 Superl O Legacy I O support is provided by using a National Semiconductor PC87427 Super I O device This chip contains all of the necessary circuitry to support the following functions GPIOs Two serial ports Keyboard and mouse support Wake up control System health support Revision 1 2 49 Intel order number D41763 003 Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS 3 6 1 Serial Ports The server board provides two serial ports an external DB9 serial port and an internal DH10 serial header The rear DB9 serial A port is a fully functional serial port that can support any standard serial device Serial B is an optional port that is accessed through a 9 pin internal DH 10 header A standard DH10 to DB9 cable can be used to direct serial B to the rear of a chassis The serial B interface follows the standard RS232 pin out as defined in the following table Table 9 Serial B Header Pin out Pin Signal Name Serial Port B Header Pin out DCD DSR RX RTS TX CTS DTR RI GND OO Sg wna o w OOOO CO CO NI OO By GI N gt 3 6 2 Floppy Disk Controller The server board does not support a floppy disk contro
109. t Delay from 5VSB being in regulation to O Ps being in 4000 ms regulation at AC turn on Time the 5VSB output voltage stays within regulation after loss CREE SUN of AC AC Input k Tvout_holdup l m MEE SEE ERE H H SU H 1 i i Ee Tsb_on_delay R gt le pwok_off Fa Ta on delay lt Teer PWOK Tpson_pwok Tpwok_on Tpwok_on Tpwok holdup j Tsvsp holdup l L L i i i i i l i Tyson on delay i i i i i PSON i i i i i k AC turn on off cycle j lt PSON turn on off cycle i Figure 26 Turn On Off Timing Power Supply Signals 86 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 8 3 9 Residual Voltage Immunity in Standby Mode The power supply should be immune to any residual voltage placed on its outputs typically a leakage voltage through the system from standby output up to 500 mV There shall be no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously It also should not trip the power supply protection circuits during turn on Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV when AC voltage is applied and the PSON signal is de asserted Revision 1 2 87 Intel order number D41763
110. t for six SATA 2 hard drives TT eessen Technology Revision 1 2 Intel order number D41763 003 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS Feature 305 10 jDescipin Support for Two processor fans Four front hot swap fans Two rear system fans Server Management Support for Intel System Management Software 16 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS List of Tables 2 2 Server Board Layout Figure 1 Server Board Photograph Revision 1 2 Intel order number D41763 003 17 Server Board Overview Intel amp Server Boards S5000PSL and S5000XSL TPS 2 2 1 Server Board Connector and Component Layout The following figure shows the board layout of the server board Each connector and major component is identified by a letter A table of component descriptions follows the figure
111. t in magnetic and dual USB J7A1 External DSub 2 DB9 J1E4 connector J1G1 J1F2 J1H1 J1G2 J1J1 J1H2 4 J1J2 J1J7 J2H1 J1J5 Revision 1 2 53 Intel order number D41763 003 Be as ee HII Design and Environmental Specifications Intel Server Boards S5000PSL and S5000XSL TPS Quantity Reference Designators Connector Type Pin Count J2J1 Header Amy Ir n Jee 2 Configuration J1D2 Password Clear J1D1 CMOS Clear J1C3 Jumper jumpers BIOS Bank Select J1E3 BMC Force Update 5 2 Power Connectors The main power supply connection uses an SSI compliant 2x12 pin connector J9B5 In addition there are three additional power related connectors One SSl compliant 2x4 pin power connector J3J2 provides 12V power to the CPU Voltage Regulators One SSI compliant 1x5 pin connector J9D1 provides DC monitoring of the power supply One SSl compliant 2x2 pin connector J5A2 provides additional 12V power to the server board The following tables define the connector pin outs Table 11 Power Connector Pin out J9B5 Pin Signal in Signal Color avec e e few ane eu RER S Tea 5 VSB 54 Revision 1 2 Intel order number D41763 003 Intel amp Server Boards S5000PSL and S5000XSL TPS Revision 1 2 Table 12 12 V Power Connector Pin out J3J2 Color GND Black 1 2 Be 12 Vdc Yellow black 6 12 Vdc Yellow black 7 12 Vdc Yellow
112. to its default position pins 2 3 Revision 1 2 93 Intel order number D41763 003 Appendix B BMC Sensor Tables Intel Server Boards S5000PSL and S5000XSL TPS Appendix B BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type The Sensor Type is the values enumerated in the Sensor Type Codes table in the IPMI specification The Sensor Type provides the context in which to interpret the sensor such as the physical entity or characteristic that is represented by this sensor Event Reading Type The Event Reading Type values are from the Event Reading Type Code Ranges and Generic Event Reading Type Codes tables in the IPMI specification Digital sensors are a specific type of discrete sensor which have only two states Event Offset Triggers Event Thresholds are event generating thresholds for threshold types of sensors u nr c nc upper nonrecoverable upper critical upper noncritical lower nonrecoverable lower critical lower noncritical uc lc upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors The offsets can be found in the Generic Event
113. zation size and speed Single Branch Mode Sparing Slot 2 a DIMM D3 DIMM DIMM D I Slot 1 Figure 15 Single Branch Mode Sparing DIMM Configuration Intel amp Server Boards S5000PSL and S5000XSL TPS DIMM AT and DIMM A2 need not be identical in organization size and speed DIMM B1 and DIMM B2 need not be identical in organization size and speed Sparing should be enabled in BIOS setup The BIOS will configure Rank Sparing Mode The larger of the pairs DIMM A1 DIMM B1 and DIMM A2 DIMM B2 will be selected as the spare pair unit 40 Intel order number D41763 003 Revision 1 2 Intel amp Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 3 1 3 4 2 2 Dual Branch Mode Sparing Dual branch mode sparing requires that all eight DIMM sockets be populated and must comply with the following population rules DIMM A1 and DIMM B1 must be identical in organization size and speed DIMM A2 and DIMM B2 must be identical in organization size and speed DIMM C1 and DIMM D1 must be identical in organization size and speed DIMM_C2 and DIMM D2 must be identical in organization size and speed DIMM AT and DIMM A2 need not be identical in organization size and speed DIMM B1 and DIMM B2 need not be identical in organization size and speed DIMM C1 and DIMM C2 need not be identical in organization size and speed DIMM D1 and DIMM D2

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