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Intel PXA27X User's Manual

1. m m O gt o BE o gt KYBD 2c UARTs AC 32 768 k 13M 13M 32 842 M 14 857 M ext clk 19 500 o 8 1 O VCC_BATT gt Application Note 7 Intel 27 Processor Family Power Requirements ntel 2 1 Power Domains and System Voltage Current Requirements The following sections document the power requirements for the PXA27x processor but do not include external support memory or other peripheral components The power consumption values shown in Table 5 are all worst case numbers These numbers give the worst case system power supply requirements and do not reflect typical system power consumption Intel PXA27x Processor Power Supplies Viewed externally the processor can require up to nine independent voltages provided by regulated supplies In some cases multiple voltage domains might be strapped together reducing the number of separate regulators to as few as four Internally there are more domains but these are powered from the externally supplied domains by on chip regulators The internal domains are documented for informational purposes only
2. 18 4 I ntel amp PXA27x Processor Power Manager Sleep Reset State 26 Tables External Power Supply Descriptions nnn 6 Intel PXA27x Processor Voltage Domains sse eene kek AKA AKA AA KAWA A AA 9 Regulators Required to Power the Intel PXA27x 11 Intel PXA27x Processor Supply Current For Each Power 11 Intel PXA27x Processor VCC CORE Supply Current sss 13 Possible Backup Battery Configurations eene 14 Intel PXA27x Processor Operating Modes 17 Power Controller Interface Siqal x laii lak ka nlsan 19 General Characteristics sind d canes n k h n ARA a kk Aka ke K R k n sesenta nennt nna 33 Application Note 1 1 Intel PXA27x Processor Family Power Requirements Introduction The Intel PX A27x Processor Family PXA27x processor is a highly integrated system on chip optimized for handheld battery powered devices such as PDAs and 2 5G or 3G cell phones The PXA27x processor is ideal for products requiring substantial computing and multimedia capabil
3. ERA Rana 31 Fault EEE kk Eka KE kk KAKA KAKA KA KA KAK A A KK 31 GW HYDD FAULT iioi ree rog eeepc rb ae Db JJJ 31 Application Note iii Contents Intel 27 Processor Family Power Requirements tel 7 2 _ EAULT aasia iia aa D kan dand de kane ees 32 8 0 Power Management Integrated Circuit Requirements 32 8 1 General Characteristics i 32 9 2 Features ot a PMC uisi 33 8 3 Programmable Voltage Control 34 98 31 DVM Control Register ns riche eh ede Erde e ete deed 34 8 32 Control Register 2 cR seed dn rak ceu 34 8 3 3 DVM Control and Status Register 3 35 8 3 4 Other Aspects of an Integrated Power 35 90 SUMMA DR 35 Figures 1 Intel amp PXA27x Processor Internal and External Power Domains 7 2 Typical Battery and External Regulator Configuration eese 16 3 Overview of Power Management Operating
4. 20 4 6 2 User Initiated Hard Reset Input k l 20 4 6 3 nRESET Output from PMIC to the Intel PXA27x 21 4 7 X Universal Subscriber Identity Module USIM uu EEE kk ek 21 4 8 Power Manager Capacitor Signals EEE kk kek 21 Power Mode KA een nennen 22 5 1 uel m 22 5 1 1 Cold Start Power On and Hardware 22 5 1 2 Initial Power Up and Deep Sleep Exit 23 5 1 3 Hardware Reset nennen mnes 24 5 2 Sleepand Deep Sleep eite pe ie irte kada ETE FRED EAE EH kana 27 5 2 1 Sleep Entry and kaka kak AKA KAKA KAKA KAK AA A A A 27 5 2 2 Deep Sleep Entry and Exit 28 Dynamic Voltage Management DVM kk kk Ek KK KAK KA KAK KA 29 6 1 CORE Regulator and Dynamic Voltage 29 6 2 Intel PXA27x Processor Voltage 30 6 3 Power Manager I2C 1 ener nennen nnne 31 04 DVM S6equ 6 amp tclrig bb
5. must be disabled using SYS EN or an command when the PXA27x processor enters deep sleep mode During deep sleep the UVSO nUVSI and nUV S2 outputs are not driven and cannot control VCC_USIM regulator Power Manager Capacitor Signals This section describes connection of external capacitors to PX A27x processor signals These capacitors do not have a direct design impact on a PMIC but are included here for completeness Application Note 21 Intel PXA27x Processor Family Power Requirements ntel 5 0 5 1 22 Note The PXA27x processor has a low power DC to DC converter that is enabled by software while in sleep or deep sleep mode Enabling the low power DC to DC converter further reduces power consumption by shutting off the high power regulators on the PMIC eliminating losses in the external power supply subsystem Use of the sleep mode DC to DC converter requires three external capacitors connected to the PXA27x processor PWR_CAP signals These capacitors are required for the DC to DC converter e 0 1 capacitor connected between PWR_CAP lt 0 gt and PWR_CAP lt 1 gt signals e 0 1 capacitor connected between PWR_CAP lt 2 gt and PWR_CAP lt 3 gt signals 0 1 capacitor connected between the PWR OUT signal and ground is always required Use ceramic unpolarized capacitors with a low equivalent series resistance ESR No other connections are allowed the PVR OUT and
6. 10 2 1 3 Intel PXA27x Processor Supply Current for Each Power Domain 11 2 1 4 Intel PXA27x Processor CORE Supply 12 2 1 5 Default Reset Values ree KA VE RA 13 2 27 14 2 271 N K s a E wee 14 2 2 2 Backup Battery d ni k hun dale Xe ekk EK E Va 14 2 2 3 Battery Chargers and Main kak KA AA KAK AA A A AA AA KA 15 Intel PXA27x Processor Low Power Operating 17 Power Controller Interface 19 kk kk ek kek kk KK KAK 18 4 1 Power Enable PWR_B N K K kek kak kk kk kk KA KAK KA KA 19 42 System Power Enable SYS_EN lt 2 gt kk 19 4 3 Power Manager I2C Clock PWR_SCL lt 3 gt 19 4 4 Power Manager I2C Data PWR_SDA lt 4 gt 20 4 5 System Level Considerations for I2C 1 kek kk Kek kk KA KAK KA 20 46 Off and RESET a R 20 4 6 1 On and Off Control e
7. ensures that each regulator powers up to its designated voltage without processor intervention Software must read this configuration information using I C command Batteries The PXA27x processor supports a variety of system battery configurations with both a main battery and backup battery and a main battery alone In systems with only a main battery the main battery must drive directly or use a regulator In systems with a backup battery the backup battery connects directly to VCC_BATT or the backup battery can be connected to a power controller which in turn drives the PXA27x processor VCC_BATT Main Battery The main battery is a rechargeable single cell or multiple cells in parallel using lithium ion or lithium polymer technology These batteries typically present a voltage as high as 4 2 V when fully charged declining to under 3 0 V as they discharge A main battery capacity of 500 to 1200 mAh is typical for most applications Backup Battery The backup battery is a lithium or lithium manganese coin cell with an output voltage of approximately 3 0 V The backup battery is a small rechargeable coin cell permanently mounted to the printed circuit board PCB in many handset applications The PMIC must include a regulator and associated circuitry for recharging this type of backup battery The two backup battery configurations are shown in Table 6 l excluding VCC BATT and VCC USB 14 Application No
8. PWR_CAP lt 3 0 gt signals The signals must not be shared with the GPIO lt 5 8 gt functions under any conditions Power Mode Sequencing The PXA27x processor supply voltages must be powered up in a specific sequence to avoid damage to the processor Refer to the ntel amp PXA27x Processor Family Electrical Mechanical and Thermal Specification for power on reset timing specifications In general _ must be the first domain to be powered on and the last to be powered off After that I O voltages must be powered on before internal voltages and powered off after internal voltages are turned off I O voltages are the higher voltages 1 8 V to 3 3 V that power the I O cells VCC IO VCC LCD VCC MEM VCC BB VCC USB VCC USIM These voltages must power on first after VCC BATT powers up and must be the last to power off before VCC BATT powers off Internal voltages are those that power the PX A27x processor core the PLLs and internal SRAM VCC CORE VCC PLL and VCC SRAM VCC CORE ranges from 0 85 V to 1 55 V in normal operation while VCC PLL and VCC SRAM are fixed at 1 3 V and 1 1 V respectively Within the I O supply group VCC IO must be established at or before but not after any other supply except VCC USB Within the internal supply group there is no specific sequencing requirement within the internal supply group The internal supplies can be turned on or off in any order or simultaneously For po
9. Processor Family Electrical Mechanical and Thermal Specification data sheet for entry and exit sleep mode timings Upon exiting from sleep mode the processor returns to the last clock frequency prior to sleep mode entry Likewise the PMIC must also be able to return to the previous voltage level prior to entering sleep mode It is necessary for the PMIC to accommodate the appropriate voltage level upon exiting All wake up events are ignored until nBATT FAULT is de asserted if the nBATT FAULT signal asserts in sleep or deep sleep Deep Sleep Entry and Exit The PXA27x processor prepares the PMIC for deep sleep prior to entering deep sleep by specifying which additional system regulators are to be disabled or shut down when the PXA27x processor commands deep sleep entry The PX A27x processor controls deep sleep entry by de assertion of the SYS EN signal The set of regulators to be turned off can be fixed in PMIC hardware or it can be programmable If programmable a register in the PMIC 15 loaded via PC to specify which regulators turn off The regulators for VCC IO VCC LCD VCC MEM BB VCC USB USIM are enabled and disabled using SYS but other regulators in the system may or may not need to be enabled disabled depending upon system design The PXA27x processor places DRAM memory into self refresh mode before entering deep sleep In self refresh mode the DRAM must still be powered but power decreases substan
10. SYS EN Memory controller input output 1 8 2 5 3 0 3 3 otherwise 10 20 5 1 8 V VCC_BB SYS_EN Baseband interface 1 8 2 5 3 0 3 3 otherwise 10 j 20 5 1 8 V VCC_USIM SYS_EN USIM interface 1 8 3 0 otherwise 10 VCC_USB SYS_EN Differential USB input output 3 0 3 3 10 VCC_PLL PWR_EN Phase locked loops 1 3 10 VCC_SRAM PWR_EN Internal SRAM units 1 1 10 VCC_CORE PWR_EN CPU and other internal units variable 0 85 1 551 5 10 NOTE SYS EN and PWR EN are PXA27x processor output control signals 1 PXA27x processors have different maximum frequencies and VCC CORE voltages Refer to both of the Intel PXA27x Processor Family EMTSs for details Application Note tel Intel PXA27x Processor Family Power Requirements Figure 1 Intel PXA27x Processor Internal and External Power Domains VCC_PLL VCC_CORE VCC_SRAM cpi VCC PLL VCC CPU prg frq Control MEM Control VCC_OSC VCC_PER LCD Control vcc_Osc SRAM Control vcc_LCD MEM VCC USB EEE EEE HEEE EEE VCC_IO VCC_RTC VCC_REG
11. also fixed at 1 1V no dynamic voltage changes are used and the maximum core clock frequency is not supported these two supplies are connected together and powered by a common regulator In sleep and deep sleep modes VCC_SRAM is powered down and the internal SRAM banks under program control are powered from an internal regulator connected to VCC BATT Doing so retains their contents although no accesses are allowed SRAM must be enabled when PWR EN is asserted and disabled when PWR EN is de asserted Application Note Intel 27 Processor Family Power Requirements Table 2 2 1 2 10 Intel amp PXA27x Processor Voltage Domains Sheet 2 of 2 Voltage Description VCC IO Fixed 3 0 V or 3 3 V 10 for standard CMOS interfacing to external components which are also supplied from fixed 3 0 V or 3 3 V The I Os for external components connected to the corresponding signals on the PXA27x processor must be supplied from the same regulator Driving VCC_BATT in this manner prevents forward biasing of protection diodes and inadvertent charging of the backup battery through inputs on the PXA27x processor VCC REG domain The VCC IO supply must be the highest potential in the system excluding VCC_BATT and VCC_USB and must be sequenced on at the same time or before the other supplies enabled by SYS EN VCC are connected to any of the LCD MEM VCC BB or VCC USIM supplies as long as none
12. at least temporarily at this time to prevent draining the backup battery prematurely With the backup battery in place the PX A27x processor begins the initial cold start power up sequence enabling its power manager unit and one of the oscillators Refer to the Intel PXA27x Processor Family Electrical Mechanical and Thermal Specification for power on reset timing specifications The PXA27x processor waits for the assertion of nBATT FAULT from the PMIC The PXA27x processor internal power manager unit PMU also powers up its own section of low power circuitry with the installation of the backup battery Doing so allows the PMU to monitor voltages as they come up and generate the nBATT_ FAULT and nVDD FAULT signals Because the main battery is not installed and only is supplying power to the PXA27x processor the PMIC initially must assert both nBATT FAULT and nVDD FAULT Note that the PMIC outputs must be powered from the supply at this time The PMIC must not de assert nBATT FAULT until the main battery 1s inserted and charged When the backup battery is installed but the main battery is not installed the PXA27x processor draws approximately 1 mA from the backup battery on _ To preserve the backup battery life Intel recommends the temporary installation of a a main battery long enough to complete an initial boot sequence and run software to configure the PXA27x processor to enter deep sleep mod
13. into sleep or deep sleep for example the user presses the OFF button and closes the unit cover or by a hardware event such as assertion of the nVDD FAULT or nBATT FAULT signals from the PMIC See Section 7 0 for fault conditions and interaction between the PXA27x processor and the PMIC during those events Sleep Entry and Exit Prior to entering sleep mode the PXA27x processor prepares the PMIC by specifying which additional system regulators if any are to be disabled or shut down when the PMIC is commanded to go into sleep mode The set of regulators to be turned off can be fixed in PMIC hardware or it might be programmable If programmable a register in the PMIC is loaded via PC to specify which regulators turn off For optimal power savings during sleep enable and disable the CORE VCC PLL SRAM regulators using but other regulators in the system may or may not require enabling disabling depending upon system design For example if a memory device or peripheral must retain its contents during sleep under certain conditions it may require another regulator that is software controllable The PXA27x processor places DRAM memory into self refresh mode Note that in self refresh mode the DRAM must still be powered but power decreases substantially Alternatively if DRAM contents do not need to be preserved the processor places the DRAMs into deep power down mode Doing so reduces DRAM power to microamp
14. mode where VCC REG 15 powered from VCC BATT PXA27x processor internal registers and processes are held at their defined reset conditions during hardware reset While the nRESET signal is asserted the only activity inside the PXA27x processor is the stabilization of the 13 000 MHz oscillator and phase locked loops The remaining internal clocks are stopped and the processor is fully static Additionally all signals assume their reset conditions and the nBATT FAULT and nVDD FAULT signals are ignored The nRESET OUT signal from the PX A27x processor is asserted when the nRESET input signal is asserted Universal Subscriber Identity Module USIM The PXA27x processor provides signals to control an external regulator that powers the USIM card interface used in many digital cell phones The VCC_USIM regulator output voltage is set to 1 8 V or 3 0 V or disabled 0 V under software control The software voltage control is implemented either by using commands or by decoding the PXA27x processor UVSO nUVS1 and nUVS2 outputs in the PMIC The regulator must drive USIM to ground when UVSO is driven high The regulator must drive to 1 8 V when nUVSI is driven low The regulator must drive to 3 0 V when nUVS2 is driven low The PXA27x processor USIM interface asserts only one of these signals at a time such that they can be used to control the gate of simple FET switches directly The regulator that generates
15. of these supplies are driven at a voltage higher than VCC IO VCC must be enabled when SYS EN is asserted and disabled when SYS EN is de asserted NOTE When the main battery is installed VCC_BATT must be driven by a regulator whose output is matched to the regulator so that and VCC BATT remain within 200 mV of each other when the regulator is enabled VCC LCD Power for output drivers to LCD panel 1 8 V 20 5 2 5 V 3 0V or 3 3 V 10 Optionally these are strapped to one of the existing I O supplies at 3 3 V 2 5 V or 1 8 V if appropriate for the panel used This supply must be enabled when SYS EN is asserted and disabled when SYS EN is de asserted VCC MEM Power for memory system bus at 1 8 V 20 5 2 5 V 3 0V or 3 3 V 10 fixed strappable by input signals on the power controller to one of these voltages The power controller automatically powers up VCC MEM to the voltage specified by its input control signals when this regulator is enabled Corresponding I Os of the memory components or companion chips must be powered from the same regulator This supply must be enabled when SYS EN is asserted and disabled when SYS EN is de asserted VCC BB Power for I Os to an external baseband module or device at 1 8 V 20 5 2 5 V 3 0V or 3 3 V 10 Corresponding I Os of the baseband device must be powered from the same regulator In systems that use PCMCIA or Compact flas
16. only be used or copied in accordance with the terms of the license The information in this document is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http Awww intel com Copyright O Intel Corporation 2004 AlertVIEW i960 AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips Commerce Cart CT Connect CT Media Dialogic DM3 EtherExpress ETOX FlashFile GatherRound i386 i486 iCat iCOMP Insight960 InstantIP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel ChatPad Intel Create amp Share Intel Dot Station Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetB
17. reset initiates when the PMIC asserts the nRESET signal low On assertion of nRESET the PXA27x processor enters hardware reset state and asserts nRESET OUT The PMIC must hold nRESET low long enough to allow internal stabilization and propagation of the reset state which is a minimum of 50 ms The sequence for hardware reset is as follows Application Note 5 Intel PXA27x Processor Family Power Requirements The PMIC asserts nRESET The PXA27x processor asserts the nRESET OUT signal The time between nRESET assertion and nRESET OUT assertion depends on whether this event the PXA27x processor was previously running or whether this is an initial power up event The PMIC de asserts nRESET after a minimum of 50 ms from nRESET assertion The internal processor PMU waits for the 13 000 MHz oscillator and internal PLLs to stabilize if needed The PXA27x processor de asserts the nRESET OUT signal The timing for hardware reset is shown in the Intel PXA27x Processor Family Electrical Mechanical and Thermal Specification The PXA27x processor power manager sleep reset state 1s shown in Figure 4 The timing between nRESET assertion and nRESET OUT assertion is shown in the Intel PXA27x Processor Family Electrical Mechanical and Thermal Specification data sheet Application Note 25 Intel 27 Processor Family Power Requirements ntel Note 1 OUT assertion is software programmable during pr
18. N and SYS EN and the system is operating normally The interface does not support the hardware general call 10 bit addressing high speed mode Hs mode 3 4 Mbits s or CBUS compatibility Although other compatible protocols such as SMBus can be used with the PXA27x processor interface they have not been tested for compatibility Refer to the Bus Interface Unit section ofthe ntel amp 27 Processor amily Developer 5 Manual for more information On Off and RESET On and Off Control User initiated ON and OFF events are accomplished using a push button or similar type of system power switch The system power switch is a momentary contact type making contact shorts the normally high input to GND The switch signal can be connected directly to PXA27x processor GPIO input or preferably to the PMIC which debounces the input and forwards the clean signal to a PXA27x processor GPIO This process requires two signals on the PMIC one input and one output GPIO lt 0 gt or GPIO lt 1 gt are recommended for this purpose because they can generate deep sleep wake up events User Initiated Hard Reset Input This signal from a momentary contact push button switch connects to a power controller input for user initiated hard reset Detection of hard reset forces assertion of the nRESET output from the power controller IC to the PXA27x processor The input must be debounced to cause clean 1 See I2C Bus Specificati
19. OUT Power Control Interface U 01 IN our f D Pid PAR ADAPTER DETECIED C gt af m R2 RI Main Battery VCC_B3 VCC LCO VCC MEM VCC IO VCC USIM Uvso PXA27x Processor nUVS2 VCC SRAM VOC_CORE SYS EN PWREN rBATI FAULT nRESET OUT nRESET 5 PWR SDA GPI00 GPIO1 VCC BATT 16 Application Note Intel 27 Processor Family Power Requirements 3 0 Intel amp PXA27x Processor Low Power Operating Modes The PXA27x processor provides several low power operating modes that temporarily suspend or power down the core or peripherals to reduce power consumption The external power supplies are disabled in some modes Transitions between certain domains require a sequence of events and handshakes between the PXA27x processor and the external power management integrated circuit PMIC that are detailed in this section The PXA27x processor supports six operating modes shown in Table 7 Table 7 Intel PXA27x Processor Operating Modes Operating Modes Description Normal mode Run Turbo mode All external power supplies are enabled and all internal domains are powered The CPU core and peripherals are fully functional Idle mode The clocks to the CPU are disabled but context is retained The peripherals continue normal operation All power supplies are enabled An interrupt assertion causes the transiti
20. agement integrated circuit PMIC for the PXA27x processor General PMIC Characteristics Table 9 shows the overall characteristics for a PX A27x processor PMIC Application Note Intel PXA27x Processor Family Power Requirements Table 9 General PMIC Characteristics Characteristic Description Multi Function Highly Integrated Incorporating buck boost buck boost and LDO regulators for the PXA27x processor and surrounding system elements with dynamic voltage management DVM logic for the core supply It includes power up power down and sleep mode power sequencing and generates correct nRESET nBATT_FAULT FAULT outputs for the System Ideally it also incorporates battery charger circuits and an output to notify the system when AC power input is present touchscreen and audio CODECs would be a plus if they can meet industry standard noise and distortion requirements when combined on the same silicon Low Cost High integration provides a packaged device that must be lower cost than the alternative comprised of discrete power supply devices High Efficiency Converters operate in the 85 95 efficiency range under all load conditions and with very low quiescent current and shutdown currents off or sleep mode 2 Interface Must be standard 12C interface operating at either 40 kHz standard mode or 160 kHz fast mode clock rate Stable and Accurate Meets x 396 accuracy or better at t
21. al power domains are powered from one of three internal regulators driven from the backup battery signal VCC_BATT Recovery is initiated by external or select internal wake up events and requires a system reboot because the program counter is invalid NOTE Refer to the Intel PXA27x Processor Family Developers Manual Clocks and Power section for more information on low power modes The state diagram in Figure 3 shows the transitions between operating modes and the events and conditions that cause or enable transitions Application Note 17 Intel 27 Processor Family Power Requirements Figure 3 Overview of Power Management Operating Modes Reset Mode reset de asserted any reset asserted Standby Mode Idle Mode Fault amp xIDAE 0 QULA GUAE Idle Normal Mode Sleep instruction instruction CPDIS 1 Idle instruction Vake up event CPDIS o Standby ORNFault amp xIDAE 1 Interrupt instruction OR Fault amp XIDAE 1 Wake up event OR Fault amp XIDAEx1 Interrupt OR amp xIDAE 1 Wake up event OR Fault amp x DAE Sleep Mode Fault amp x DAE 0 Deep Sleep instruction OR Fault amp 0 Deep Sleep Mode Fault amp xIDAE 0 4 0 18 Power Controller Interface Signals The PXA27x processor has an internal power manager unit PMU and a set of I O signals for communicating with a
22. as increments of the PMIC internal oscillator used by its voltage converters Many switching regulators use oscillators in the 500 kHz to 1 MHz range Section 8 0 contains more information on the recommended PMIC register set and bit fields The worst case load or maximum di dt from the slowest run mode setting to the fastest turbo mode setting expected is 200 mA per 10 ns It may be advantageous to allow scaling of the VCC_CORE domain above 1 55V for debug purposes which would require the PMIC and associated power circuitry being able to drive VCC_CORE up to 2 0V Intel PXA27x Processor Voltage Manager The PXA27x processor power manager unit PMU includes an internal voltage manager unit with a dedicated interface and a command sequencer The I C interface provides the PXA27x processor with dynamic and static voltage control capability using an I C module for communicating with the external PMIC The voltage manager provides these features Static Halted or dynamic operational voltage change e Up to 32 commands automatically sent to PC Single and multi byte command support The PXA27x processor commands are user defined to match the format defined by the PMIC Programmable delay between commands l Astep down or voltage dropping converter 30 Application Note 6 4 7 0 7 1 Intel PXA27x Processor Family Power Requirements Power Manager l2C Interface The PXA27x processor commun
23. d then VCC LCD VCC MEM VCC USIM VCC BB and VCC USB The latter regulators power on and achieve regulation in any order 8 After the 125 ms SYS DEL timer expires the PXA27x processor asserts PWR_EN to enable the PXA27x processor low voltage power supplies Refer to the Intel PXA27x Processor Family Electrical Mechanical and Thermal Specification for Power On reset timing specifications The PXA27x processor starts its DEL countdown timer set to the default 125 ms period 9 The PMIC enables the regulators driving VCC CORE VCC PLL and VCC SRAM These regulators power on and achieve regulation in any order 10 The PMIC de asserts nVDD FAULT when all supplies are stable and within regulation specifications 11 After the 125 ms PWR DEL timer expires the PXA27x processor samples the nVDD FAULT input If nVDD FAULT is asserted the PXA27x processor returns to sleep or deep sleep mode otherwise the sequence continues 12 The PXA27x processor continues its power up initialization by enabling the processor 13 000 oscillator and internal PLLs and switching the supply power for the internal domains from to IO 13 The PXA27x processor de asserts the nRESET OUT signal and begins the execution of code from the reset vector Refer to the Intel PXA27x Processor Family Electrical Mechanical and Thermal Specification for power on reset timing specifications Hardware Reset Behavior Hardware
24. e and that the low voltage core power supplies are to be shut down The PMIC turns on the core low voltage supplies in response to PWR_EN assertion to resume normal operation The power controller must preserve during sleep or deep sleep the previous state of its regulators including the voltage for the core so that on resumption of core power the regulators return to their last known voltage levels System Power Enable SYS EN GPIO 2 SYS EN is an active high output from the PXA27x processor input to the PMIC that enables the external system power supplies De asserting SYS informs the power supply that the processor 18 going into deep sleep mode and that the high voltage system power supplies VCC IO VCC LCD VCC MEM VCC USIM VCC BB and VCC USB are to be shut down Assertion and de assertion of SYS EN occurs in the correct sequence with PWR_EN to ensure the correct sequencing of power supplies when powering on and off the various voltage domains To resume normal operation the PMIC first turns on the system I O high voltage supplies in response to SYS EN assertion and then turns on the core low voltage supplies in response to PWR EN assertion The power controller must return all system I O voltages to their pre deep sleep mode levels Power Manager I C Clock PWR SCL GPIO lt 3 gt The PWR SCL signal is the power manager clock in to the external PMIC The serial bus must operate at a minimum 40 kHz a
25. e 1 55 V 10 regardless of the value set in this register This regulator output threshold may be higher depending upon the scope of operation of the PMIC Refer to Section 6 1 of this document for more information DVM Control Register 2 This 4 bit to 8 bit register controls the voltage ramp rate The specific bit encoding is left to the PMIC designer This register might contain a time delay value that controls the time between output voltage microsteps in implementations that use a discrete voltage ramp rate mechanism During a voltage change the regulator output 1s stepped from the initial voltage to the new set point one microstep at a time to achieve a controlled voltage ramp rate The input clock is expected to be in the range of 500 kHz to 1 MHz so it can count out intervals with a minimum of 2 us for each voltage microstep but the exact delay depends upon the size of the voltage steps used Application Note n 8 3 3 8 3 4 9 0 Intel PXA27x Processor Family Power Requirements DVM Control and Status Register 3 The Control and Status registers contain the GO bit which once set activates the voltage change requested by the new voltage in DVM Control register 1 at the ramp rate specified in DVM Control register 2 Additional bits can be added to this register to provide the status for system regulators whose voltage is configured by strapping hardware control signals Other Aspects of an Integrated Power Controlle
26. e using the internal DC to DC converter The GPIO pins on the PXA27x processor initially default to inputs so they cannot be used for power regulator control at initial power up or for exiting deep sleep mode unless they have been programmed to respond to an edge or level change Application Note 23 Intel 27 Processor Family Power Requirements ntel 24 Note The nRESET signal must be asserted earlier in the reset sequence for the processor Refer to the Intel amp PX427x Processor Family Electrical Mechanical and Thermal Specification for power on reset timing specifications The sequence for initial start of life power on reset is as follows 1 VCC BATT power is applied to the processor and reaches a stable voltage of at least 2 25 V initiating the power on reset event with nRESET asserted from PMIC to the processor 2 The PMIC must assert nBATT FAULT because the main battery is not installed 3 The PMIC de asserts nRESET after a minimum of 50 ms 4 The PXA27x processor enables its internal PMU which waits for the de assertion of nBATT FAULT to indicate main battery installation 5 The fully charged main battery is installed and the PMIC de asserts FAULT 6 The PXA27x processor asserts SYS EN to enable the system high voltage power supplies The PXA27x processor starts its SYS DEL countdown timer set to the default 125 ms period 7 The PMIC enables the regulators driving VCC IO an
27. evel given a typical environment in order to show what the overall power envelope for these domains could look like In a real system each domain will see varying amounts of power consumption based on the type of workload run For instance an MPEG 4 decoder is going to utilize the memory controller much more than performing simple email transactions would Guidance on the power consumption for each domain in order to show Table 5 lists power supply current for each PXA27x processor power domain except for VCC_CORE Table 4 shows data for VCC_CORE The environment test conditions are at room temperature and the voltage levels are specified below Note that the I O domain regulator s VCC_IO VCC_LCD VCC_MEM VCC_BB VCC_USIM VCC_USB have additional loading from external devices attached to the PXA27x processor For example when flash memory or SDRAM is connected to the system bus These loads must be added to those of PXA27x processor 1 if they are powered by the same regulator when specifying the total load to be provided by a given regulator 12 Application Note intel Intel amp PXA27x Processor Family Power Requirements Table 5 Intel PXA27x Processor Supply Current For Each Power Domain Current Functional Units voltage V mW VCC BATT Power manager and real time clock max during power on and 10 3 75 V 37 5 sleep wakeup Power manager and
28. ge suitable for powering the regulators and charging the batteries The PMIC must have an input voltage detect that can sense when AC power is supplied to the system to manage main power An output from the PMIC must make this information available to a PXA27x processor GPIO ata suitable voltage normally 3 3 V CMOS logic levels For GPIO lt 0 gt or GPIO lt 1 gt to generate deep sleep wake up events the PMIC must make the input voltage detect information available as an output to one of these GPIO signals Application Note 15 Intel 27 Processor Family Power Requirements Figure 2 Typical Battery and External Regulator Configuration N ENABLE SER OUT 1 8V 25V 30V or 3 3 Requlator T Bockup Battery nj SYSEN QUT 1 84 354 30V or 3 Regulator ut s ENABLE SUN 4 OUT 33 or 30V Regulator 9 IN QUT S98 E ENABLE se 12C Controlled Switch PAREN OUT 1 AV Fixed Regulator U5 SEN BE PAREN 8 PIREN oo N out m 1 3V Fixed Regulator PWREN nBATT FAULT 8 ae EE SISEN ENABLE IN REG_OK out 0 85 1 307 Adj Regulator gek ALL REGULATORS OK Fault Monitor ult nRESET POWER SWITCH C gt LOGC VCC 12C DATA ADAPTER PUR PIRSIL
29. h and the baseband interface VCC BB must be tied to VCC MEM because some of the card interface signals are multiplexed with baseband interface signals This supply must be enabled when SYS_EN is asserted and disabled when SYS EN is de asserted if any of these GPIOs are used as either a GPIO or as an alternate function GPIO lt 48 gt GPIO lt 57 50 gt GPIO lt 85 81 gt VCC_USIM Power for I Os to an external Universal Subscriber Identity Module USIM card The VCC_USIM voltage generated by the PMIC is software configurable at settings of 1 8 V 20 5 or 3 0 V 10 or disabled 0 V The software voltage control is implemented using commands or the decodes the PXA27x processor UVSO nUVS1 and nUVS2 outputs Refer to Section 4 7 Universal Subscriber Identity Module USIM on page 21 for more information VCC_USB Power for USB at 3 0 V or 3 3V 10 for standard differential USB I Os interfacing to external components which are also supplied from fixed 3 0 V or 3 3 V NOTE VCC_USB powers the I O for the USB interfaces the USB differential signals D D is out of compliance with the USB specification if VCC_USB is below 2 8 V NOTE The 5 V VBUS source from USB host controller which must be available for bus powered peripherals must be supplied from an external source but it is not part of the PXA27x processor silicon Power Supply Configuration in a Minimal System For minimal sys
30. he VCC_IO regulator so that VCC IO and remain within 200 mV of each other when the regulator is enabled VCC CORE CORE VOLTAGE Dynamically variable core voltage of 0 85 V to 1 55 V CORE also powers internal peripheral logic blocks such as the memory controller LCD controller digital audio and Serial ports It does not power the internal SRAM In a full featured system this supply is software controllable as described in Section 6 1 Regulator and Dynamic Voltage Management on page 29 In a simple system this supply might be a fixed voltage chosen to meet the minimum voltage requirement for the highest frequency at which the PXA27x processor operates In systems that use standby mode there must also be a provision to set VCC_CORE to 1 10 V 10 prior to entry into standby mode VCC CORE must be enabled when PWR EN is asserted and disabled when PWR EN is de asserted VCC PLL PHASE LOCK LOOP VOLTAGE 1 3 V 10 for internal PLL circuits fixed VCC_PLL must not be connected to VCC CORE even though they both may be at the same voltage 1 3 V A separate low noise voltage source is recommended to keep the PLL supply clean This supply must be enabled when PWR EN is asserted and disabled when PWR EN is de asserted VCC SRAM Power for the internal SRAM during operation in run or turbo modes This supply is fixed at 1 1 V 410 If the core supply VCC CORE is
31. he PMIC output signals over input variation load variation and temperature for all regulators and converter outputs Switching regulators must minimize noise propagated into regulator outputs Reliable Current and thermal limiting on all regulators 8 2 Features of a PMIC The basic features of a PMIC for use with the PXA27x processor include Multiple channels of regulated power output Dynamic voltage management DVM capability for the PXA27x processor core supply Debounced push button ON OFF and user reset inputs AC adapter detect capability Power on user reset output to the PXA27x processor nRESET input nBATT FAULT signal signifying main battery removed nVDD FAULT signal indicating any power regulator out of spec Automatic switch over from main battery to backup battery when main battery is discharged or removed Responds to the PXA27x processor mode change requests by switching regulators on or off Control and Status registers accessible through interface Provides USIM power FET control to supply 3 0 V or 1 8 V to USIM card The features of a PMIC for battery charging also include Application Note Charging capability for lithium ion or lithium polymer main battery Support for either rechargeable or non rechargeable backup battery Digital output battery level monitor fuel gauge for main and backup batteries optional Battery charging current and temperature monitoring for fast charging of mai
32. icates with the PMIC using the serial bus The flexible IC controller in the processor can pre load a buffer with a series of commands or multi byte commands of any size up to a total of 32 bytes of command address and data The controller can be programmed to send a series of commands with programmable intervals between groups of commands to accommodate a variety of different power controllers and regulators Refer to the Intel PXA27x Processor Family EMTS for voltage change timing specifications The 12 interface runs in either standard mode at 40 kHz or fast mode at 160 kHz using standard 7 bit addressing The hardware general call and 10 bit extended addressing are not supported DVM Sequencing The PMIC contains registers that enable at a minimum these functions Programming a voltage change from the current voltage to a new voltage Programming a ramp rate at which the voltage change occurs A GO bit which once set triggers the requested voltage change Fault Management The PXA27x processor provides two digital status inputs nBATT FAULT and nVDD FAULT driven by the external PMIC that indicate status of the main battery and the power supply regulators These signals permit a combination of hardware and software management of power fault conditions Both signals are asserted low to the PXA27x processor inputs They can be used to place the processor into sleep or deep sleep power down modes to reduce power quick
33. ity nBATT FAULT nBATT FAULT indicates that the main battery is low or has been removed from the device giving the PXA27x processor an indication that power will shortly cease Until that time the processor can operate for a limited period from a lithium lithium manganese coin cell backup battery or from a super cap that can only supply the processor for a few cycles of full run power In the event of nBATT FAULT assertion the PXA27x processor enters an emergency form of sleep where the only handshaking is with external SDRAM memory putting it into self refresh mode to ensure that memory contents are preserved if possible obviously the refresh current can eventually deplete the super cap or backup battery but not as quickly as the PXA27x processor in run mode Supporting these features must be understood at both the board level design and by the PMIC The PXA27x processor does not recognize a wakeup event while nBATT FAULT is asserted If the system is powered from an AC main source 90 VAC to 240 VAC or equivalent while nBATT FAULT is asserted that fact may be used to gate off nBATT FAULT and its normal effects on the system Recognition of this condition can be built into the PMIC and a signal indicating an AC power source is active is provided from the PMIC to the PXA27x processor GPIO lt 0 gt or GPIO lt 1 gt signals Power Management Integrated Circuit Requirements This section provides guidelines for designing a power man
34. ity with very low power consumption The PXA27x processor combines a high performance CPU with a variety of integrated peripheral functions The processor has separate power supply domains for the processor core memory and peripherals to enable low power system design The PXA27x processor provides several dedicated control signals as well as an interface to connect to an external power management integrated circuit Other system components such as SDRAM and flash memory audio codecs touchscreen controllers and specialized companion chips have with their own unique power requirements In many designs a highly integrated power controller supplies power for these other components particularly those that interface directly to the PXA27x processor An advanced power controller can contain circuitry for charging batteries powering the display panel and include other analog functions required by the system In any system design factors such as operating conditions application workload environmental considerations and the sophistication of the device s power management software all play a role in determining the amount of power consumed When designing a system manufacturers need to take into account where the device is intended to be used such as high temperature environments and what it is expected to do for an end user such as play a game a video or do simple email transactions The Intel PXA27x Processor Family EMTS provide
35. le bit is set the PXA27x processor shortens the wakeup sequence by asserting PWR EN as soon as the PXA27x processor PMU detects all the corresponding power supplies have powered up as shown in Figure 4 Refer to the Intel PXA27x Processor Family EMTS manual for deep sleep entry and exit timing specifications Dynamic Voltage Management DVM The PXA27x processor has a number of features that enable the dynamic management of power consumption which is based on the computing power required at any particular time These features enable the processor to modify the core frequency voltage of the processor during operation dynamically matching the computing performance to the current computing workload A system combining the PX A27x processor a power management integrated circuit PMIC and supporting DVM software can run a wide range of applications using only a fraction of the battery power that would be required running at the fixed frequency and voltage needed for the peak computing workload VCC_CORE Regulator and Dynamic Voltage Management The PMIC must have these minimum features for its VCC_CORE regulator to support dynamic voltage and frequency management High efficiency programmable buck converter output providing VCC_CORE in the voltage range 0 85 1 55 V 5 10 with a default reset output in the same range Application Note 29 Intel 27 Processor Family Power Requirements ntel 6 2 Note e PC
36. lel Intel amp PXA27x Processor Family Power Requirements Application Note Order Number 280005 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel amp PXA27x processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it are furnished under license and may
37. ly and to preserve as much system state or context as possible Entry into sleep or deep sleep can be initiated directly by the PXA27x processor PMU hardware upon assertion of nBATT FAULT and nVDD FAULT or these events can trigger a software exception handler that saves the system state and issues the command to enter sleep or deep sleep The PXA27x processor power manager PMCR BIDAE and PMCR VIDAE control bits select between hardware or software handling of these respective fault events nVDD FAULT nVDD FAULT signals the PXA27x processor that one or more of its currently enabled supplies are below the minimum regulation limit supplies that are not enabled do not cause nVDD FAULT assertion Functionally nVDD FAULT signals the processor when it is safe to exit sleep or when it must enter sleep using the mechanism selected by the PMCR VIDAE setting nVDD FAULT is ignored after a wakeup event until the SYS DEL and PWR DEL timers expires The PXA27x processor also has a configuration bit that allows nVDD FAULT to be ignored in sleep mode 1 See the Intel PXA27x Processor Family Developer 5 Manual 2 PSLR IVF bit see the ntel amp PXA27x Processor Family Developer s Manual Application Note 31 Intel PXA27x Processor Family Power Requirements ntel 7 2 8 0 8 1 32 Note System designers can include a software controlled threshold level detection for nVDD FAULT to allow an optional SDRAM keep alive capabil
38. n battery optional 33 n Intel PXA27x Processor Family Power Requirements tel 8 3 8 3 1 8 3 2 34 Note USB on the go charge pump which generates 5 0 V optional The following analog mixed signal features are required in many handheld or battery powered systems and it is a good idea to provide them in a highly integrated PMIC Power supply for LCD panels or other display types USB host VBUS 5 V power output Power supply for CMOS or CCD image sensor Touchscreen controller Stereo audio CODEC Headset amplifier Buzzer vibration motor driver LED drivers General purpose input output GPIO signals Temperature sensor Programmable Voltage Control Maintaining the functionality of the PXA27x processor during any VCC CORE voltage change static or dynamic requires a special external voltage regulator which must have the features described in Section 6 1 These features are configured through a set of control registers like those described in the following subsections The PMIC can contain additional registers to control additional system regulators and to provide status bits for system regulators whose voltage is configured by strapping hardware control signals DVM Control Register 1 This 8 bit register specifies the target voltage for VCC CORE The specific bit encoding is left to the PMIC designer The output of the regulator for VCC CORE must not go below 0 85 V or abov
39. n external power management integrated circuit PMIC These signals are active for initial power up certain reset events device on off events and transitions between some operating modes In addition two fault signals are required from the PMIC to communicate the onset of power supply problems to the processor These signals and their function are described fully in Section 7 0 The PXA27x processor communicates to the power controller using the signals defined in Table 8 Application Note intel Table 8 4 1 4 2 4 3 Application Note Intel amp PXA27x Processor Family Power Requirements Power Controller Interface Signals Signal Definition Active State Signal Direction PWR_EN Power enable high Output SYS_EN System enable high Output PWR_SCL 2 bus clock Clock Output PWR_SDA 2 bus data Bidirectional Forces an unconditional hardware nRESET roset low Input Indicates main battery removed or nBATT_FAULT discharged low Input Indicates one or more supplies are out nVDD_FAULT of regulation low Input NOTE 1 Input and output refers to the signal direction from the standpoint of the PXA27x processor Power Enable PWR EN PWR EN is an active high output from the PXA27x processor input to the PMIC that enables the external core power supplies VCC CORE VCC SRAM and VCC PLL De asserting PWR EN informs the external regulator that the processor is going into sleep mod
40. nd optionally be able to operate at a 160 kHz clock rate 19 n Intel PXA27x Processor Family Power Requirements tel 4 4 4 5 4 6 4 6 1 4 6 2 Power Manager 12 Data PWR_SDA GPIO lt 4 gt The PWR_SDA signal is the power manager data signal to the external PMIC It functions like an open drain signal so either component can pull it down to a logic low level System Level Considerations for 2 signals have an alternate function on the PXA27x processor GPIO signals Following cold start power on or a hard reset both signals default to the GPIO mode of operation and are configured as inputs An internal nominally 50 pull down resistor on each signal prevents them from floating during reset power on events To use the capabilities after power up reset the PXA27x processor must while under software control configure these signals as I C signals and disconnect the internal pull down resistor These signals behave functionally like open drain outputs and require an external pull up resistor on the system module in the 2 KQ to 20 range A typical system uses approximately 5 resistor connected to 3 3 V The PC signals from the PXA27x processor are pulled low after power up or reset events The PMIC must ignore those signals logic low is the asserted or ON state for bus after either type of event until the PX A27x processor has asserted E
41. nded configuration for connecting the PXA27x processor directly to the backup battery In such a configuration the regulated main battery powers through regulator U7 and the backup battery powers when the main battery discharges Regulator U7 also charges the backup battery and its output voltage must be chosen to ensure that remains between 2 25 V and 3 75 V when is disabled and within 200 mV of VCC IO when IO is enabled D1 protects regulator U7 from back current when the backup battery drives _ to a higher potential than the output of U7 D3 and R2 are chosen to limit intentional charging current to the backup battery D2 and R1 prevent the PXA27x processor from driving unintended charging current into the backup battery if an input signal on the VCC REG domain is driven above the backup battery voltage while the processor is powering the VCC REG domain from VCC BATT Signals from the PMIC to the processor on the VCC REG domain must be powered from the VCC BATT supply voltage when SYS EN de asserts in deep sleep mode Doing so prevents forward biasing the PXA27x processor input protection diodes Battery Chargers and Main Power The PMIC includes as an option a way of charging the main battery when the system is plugged into an AC power outlet or through the USB port An external power brick is often used to convert the main voltage 90 VAC to 240 VAC to a low DC volta
42. nternal SRAM can optionally remain powered in sleep mode to retain data at the expense of approximately 100 LLW per bank In sleep and deep sleep modes the PXA27x processor power supplies VCC_CORE VCC_SRAM and VCC_PLL can be disabled to achieve greater system power savings In deep sleep mode the system power supplies VCC_IO VCC_LCD VCC_USIM VCC_BB VCC_USB and VCC_MEM can also be powered down for additional power savings The PXA27x processor then uses VCC_BATT to power an internal DC to DC converter optimized for high efficiency at low power to create the internal supplies The penalty for removing power from VCC_CORE and VCC_SRAM is that the processor execution state is lost Once the processor activity has stopped recovery from sleep and deep sleep modes must be through an external wakeup event or a real time clock timer event that initiates a sleep reset sequence to boot the PXA27x processor again Retaining SDRAM contents while in sleep and deep sleep modes requires an additional efficient low current supply powered from either the main or backup battery Pull down the PXA27x processor SDCKE signal to retain SDRAM contents while in sleep and deep sleep Before entering the sleep or deep sleep modes software must program the appropriate registers within the PXA27x processor to Set up delay timers Shut off internal functional blocks Specify the wakeup sources for exiting sleep or deep sleep Software initiates entry
43. ocessor resets Refer to the nte PXA27x Processor Family Developer 5 Manual Figure 4 Intel amp PXA27x Processor Power Manager Sleep Reset State Diagram Software initiated deep sleep OR nVDD FAULT 0 clk_32k_ok 1 nBATT_FAULT 1 nBATT_FAULT 0 wakeup 1 amp nBATT_FAU wakeup 1 amp nBATT_FAULT 0 wakeup 1 amp nBATT_FAULT 1 nBATT_FAULT 1 SYS 1 nBATT FAULT 0 count done 1 amp nBATT FAULT 1 OR all vcc hi 1 amp PSSD 1 amp nBATT FAULT 1 PWR EN 1 All external IO pads use IO or corresponding power supply Power manager continues wr i to use VCC_BATT nBATT_FAULT 0 nBATT_FAULT 0 nVDD_FAULT 0 amp count_done 1 nBATT_FAULT 1 amp nVDD FAULT 1 amp count done 1 OR all vcc low 1 amp PSSD 1 O power manager powered by VCC_CORE O power manager powered by VCC_BATT 26 Application Note 5 2 1 Intel 27 Processor Family Power Requirements Sleep and Deep Sleep The sleep and deep sleep modes reduce power consumption by powering down most units in the PXA27x processor However the real time clock timekeeping oscillator 32 768 kHz and PMU circuits remain active The processor oscillator 13 000 MHz power manager and JTAG units may also be active One two or four banks of i
44. odeled as VCC CORE Section 2 1 3 1 All other power domains such as memory controller LCD etc Section 2 1 3 2 The core model section contains power consumption data with differing workloads The model for the remaining domains shows power consumption data for each domain Use the guidelines detailed in Section 2 1 3 1 and Section 2 1 3 2 in conjunction with the Power Consumption Specifications listed in the Intel PXA27x Processor Family EMTS 2 1 3 1 Intel amp PXA27x Processor VCC CORE Supply Current This section specifies the power consumption expected for VCC CORE power supply domain across differing workloads Table 4 shows the typical current consumption for the VCC CORE power domain at room temperature at nominal voltage levels but with differing workloads All data is taken using the Intel PXA270 Processor Development Kit processor card running low level boot code no operating system unless specified Dhrystones 2 1 Dhrystones workload Configured to run 20 000 000 cycles with LCD disabled MPEG4 Decode Frame rate unlimited Intel IPP Performance Suite v4 0 for the Intel PXA270 processor for Linux QVGA LCD with frame buffer in SRAM Power Stress Test Code Low level code executing a repetitive test case of back to back 64bit MAC instructions in an infinite loop This stress code is written specifically to exercise the core power domain to yield data at the higher end of usage It does not represen
45. on 2 1 dated January 2000 by Phillips Semiconductors order 9398 358 10011 pp 39 42 20 Application Note 4 6 3 4 8 Note Intel PXA27x Processor Family Power Requirements assertion of nRESET for a minimum of 50 ms This type of reset would be used only for a severe and otherwise unrecoverable hardware or software problem because it completely resets the state of the processor and may result in lost data Refer to the ntel amp PXA27x Processor Family Electrical Mechanical and Thermal Specification for the hardware reset timing specification nRESET Output from PMIC to the Intel PXA27x Processor nRESET is an active low signal from the PMIC to the PXA27x processor that tells the processor to enter the hardware reset state The assertion of nRESET cannot be gated and causes the PXA27x processor to enter a complete and unconditional reset state The nRESET signal contains an internal resistive pull up that is always active no pull up required on the system module or in the PMIC nRESET is a hard reset that can cause the system to lose state or data when asserted It is asserted for a cold start power on event or if for any reason the user pushes the system reset button The power controller must assert nRESET for both events nRESET must remain asserted for at least 50 ms when asserted When not asserted nRESET is pulled up internally to VCC REG VCC REG is normally powered from VCC IO except when in deep sleep
46. on back to normal mode Deep Idle mode The core frequency is at 13 MHz CCCR CDPIS is set and the processor is in idle mode Standby mode The clocks to the CPU are disabled and the CPU is placed in a low leakage state but context is retained All external power supplies are enabled Each internal SRAM bank can be independently placed in a low power mode where the state is retained but no activity is allowed under program control The PLLs are disabled and peripheral operation is suspended An interrupt assertion causes the transition back to normal mode Sleep mode All internal power domains except VCC_RTC VCC OSC are optionally powered down All clock sources except the real time clock and power manager are disabled and all external low voltage power supplies VCC CORE and VCC_SRAM controlled by PWR EN are disabled Recovery is initiated by external wake up events or select internal wake up events A system reboot is required because the program counter is invalid Deep sleep mode All internal power domains except VCC_RTC and VCC_OSC are powered down All clock sources except the real time clock RTC and power manager are disabled and the external low voltage supplies VCC CORE PLL VCC SRAM controlled by PWR EN are disabled The high voltage power supplies IO VCC MEM LCD BB and VCC_USIM controlled by SYS are disabled The active intern
47. programmable output voltage ramp rate with a default reset ramp rate of 10mV us Refer to the Intel PXA27x Processor Family EMTS for ramp rate specifications The VCC_CORE regulator must support a minimum set of these six output voltages 0 85 0 95 1 1 1 2 1 3 1 4 and 1 55 V It is preferable to provide more voltage steps by dividing the range between 0 85 V and 1 55 V using a step size of 10 to 50 mV The accuracy of each voltage set point must be at least 1 voltage step When using more than the minimum set of five steps it is not necessary to support these five exact step values The VCC_CORE regulator must also support programming the voltage ramp rate over a one decade range of the nominal default value 10mV per us Ramping is accomplished via a smooth analog ramp driven by an internal ramp generator or through a series of microsteps of 10 25 mV per microstep which are performed sequentially after a small delay to make up the requested change in voltage Faster ramp rates can in practice be limited by the capabilities of the regulator and by the amount of bulk capacitance on the VCC_CORE supply Controlling the core voltage is accomplished by loading registers in the PMIC via the serial bus The bus transfers data one byte at a time to the PMIC Register loads are 8 bits wide although not all bits need be used by accompanying circuitry If voltage ramps are comprised of a series of microsteps the step rate can be programmed
48. r If a backup battery or supercap is available in the system PMIC must be able to switch between the main battery and backup system when the main battery is depleted to ensure _ remains powered and the PXA27x processor enters sleep or deep sleep mode to maximize the life of the backup system If the PMIC supports a rechargeable backup battery the PMIC must be able to charge the backup battery from the main battery until the backup battery reaches a threshold voltage or until the main battery falls below a threshold voltage During the initial power up or during a deep sleep wakeup sequence when SYS EN is asserted ensure that is driven to the same potential 200 mV as IO Doing so prevents the PMIC from overdriving the PXA27x processor inputs nVDD FAULT nBATT FAULT nRESET GPIO lt 0 gt and GPIO lt 1 gt using the VCC IO supply while the PXA27x processor I O ring is initially powered from lower VCC_BATT supply Such an overdriving condition is particularly dangerous because it can result in sourcing current into a non rechargeable backup battery Once the wakeup sequence is completed the PXA27x processor does not draw current or drive I O from the VCC BATT input but this supply must remain available to support sleep and deep sleep wakeup and reset The PMIC must tolerate input voltages of up to 3 75 V on its SYS EN and input signals to prevent damage when these signals are driven by the PXA27
49. real time clock typical during deep sleep 6 uA 3 0 V 20 uW VCC IO Peripheral input output 25 3 3 V 82 5 VCC_LCD LCD input output 11 3 3 V 33 Memory controller input output 300 3 3 V 1080 1 ra Memory controller input output 150 1 80 V 2971 VCC_BB Baseband interface 9 3 3 V 30 VCC USB Differential USB interface 25 3 3 V 82 5 VCC_USIM USIM interface 0 3 3 0 V 1 VCC_PLL Phase locked loops 40 1 3 V 52 VCC_SRAM Internal SRAM 50 1 1V 55 NOTE 1 This data does not include the Intel PXA27x Processor Family with Intel StrataFlash memory power requirements Refer to the appropriate top package data sheet for power requirements and include this data when sizing power regulators that will support the PXA27x processors with Intel StrataFlash memory 2 1 4 Note For each I O domain maximum current draw and power use is highest at the 3 3 V supply as shown For lower voltages 2 5 V or 1 8 V maximum current draw and power use is reduced following the P C Vr relationship Use these specifications as a guideline for power supply capacity These typical guidelines will vary across different platforms and software applications Default Reset Values Of the nine power domains besides two SRAM and PLL are fixed Five domains VCC MEM VCC IO VCC LCD VCC BB and VCC USB can take one of several possible values but once powered up remain fixed VCC CORE and VCC USIM are dynamicall
50. s even though voltage from the PMIC 15 still maintained on the DRAM power signals Application Note 27 Intel 27 Processor Family Power Requirements ntel 5 2 2 28 Note Note The processor commands entry into sleep mode by de asserting PWR_EN to the PMIC once the PMIC and system are prepared The PMIC responds by turning off the specified set of supplies along with CORE PLL SRAM For entry into sleep mode there is requirement for how long these supplies require to shut down after de assertion of PWR_EN However for entry into deep sleep mode these supplies must shut down before the de assertion of SYS EN to ensure that supply sequencing requirements are met A wakeup event must occur to exit sleep mode For example the wakeup event can be a transition on one of the wakeup capable GPIOs that has been programmed to respond to a level change or it can be an interrupt from a timer in the real time clock unit In response the PXA27x processor asserts EN to the PMIC and starts its PWR DEL timer The PMIC turns on all of its low voltage supplies VCC CORE VCC SRAM and VCC PLL and when all supplies are stable and within regulation the PMIC de asserts nVDD FAULT The PXA27x processor returns the system to sleep mode ifnVDD FAULT is not de asserted before the DEL timer expires Otherwise the PXA27x processor completes the sleep reset boot sequence See the Intel PXA27x
51. s manufacturers with a typical system power consumption specification for all frequencies of the processor family The purpose of this application note is to provide guidance on how power consumption in a typical environment can change based on different software workloads In addition this application note provides further details on the requirements for providing power to the processor and for interfacing to its power control signals including behavioral requirements and typical system design examples under these workloads The power numbers generated utilized Intel development platforms in lab conditions and the information provided should be used as a guideline only Naming Conventions SEE In this document active low items are prefixed with a lowercase nRESET Bits within a signal name are enclosed in angle brackets EXTERNAL ADDRESS lt 31 0 gt nCS lt 1 gt Bits within a register bit field are enclosed in square brackets REGISTER BITFIELD 3 0 REGISTER 0 Application Note 5 Intel 27 Processor Family Power Requirements 2 0 intel The terms run mode and normal mode are used interchangeably although normal mode comprises both the run mode and turbo mode settings Intel amp PXA27x Processor Power Supply Domains Viewed externally the main or backup battery powers ten power supply domains Additional supply domains are present internally but power for these is derived from the external
52. sfied A wakeup event must occur to exit deep sleep The wakeup event can include the following Atransition on one ofthe deep sleep wakeup capable GPIOs that has been programmed to respond to an edge or level change An interrupt from a timer in the real time clock unit Upon exiting from deep sleep mode the processor returns to the last clock frequency prior to deep sleep mode entry Likewise the PMIC must also be able to return to the previous voltage level prior to entering deep sleep mode The PMIC must accommodate the appropriate voltage level upon exiting The PXA27x processor asserts SYS EN to the PMIC and starts its SYS DEL timer The PMIC turns on its high voltage supplies VCC IO VCC LCD VCC USIM VCC BB VCC USB and After waiting the period set by SYS DEL the processor asserts PWR EN to the PMIC and starts its PWR_DEL countdown timer The PMIC turns on the low voltage supplies CORE VCC SRAM and PLL and de asserts nVDD FAULT when all supplies stable and within regulation If nVDD FAULT is not de asserted before the PWR DEL timer expires the PXA27x processor returns the system to deep sleep mode otherwise the PXA27x processor completes the sleep reset boot sequence If the nBATT FAULT signal asserts in sleep or deep sleep all wake up events are ignored until nBATT FAULT is de asserted If the deep sleep configuration 15 set and PSLR PSSD sleep mode shorten wakeup delay disab
53. supply inputs functional units within a power domain connect to the same power supply and are powered up and down together The PXA27x processor architecture with its multiple power supply domains provides flexibility in system configuration including selection of I O voltages for different memory and peripherals and efficient power management for instance flexibility in selecting which peripherals are powered at the same time Together these let system designers make power complexity trade offs and optimize a product for intended markets Product designers can also choose to strap certain supplies together to power several domains from a common regulator to reduce complexity cost and the number of regulators in the system Guidelines showing which supplies can be combined are provided in this document A summary of the voltage and tolerance requirements for each external supply input is shown in Table 1 Figure 1 shows the PXA27x processor internal and external power domains and their connections Table 1 External Power Supply Descriptions 1 7 Specified Levels Tolerance Power Domain Enable Units Volts VCC Sleep control subsystem oscillators and 3 0 25 real time clock j 10 3 0 V VCC_IO SYS_EN Peripheral input output 3 0 3 3 10 10 3 20 5 Q 1 8 V VCC LCD SYS EN LCD input output 1 8 2 5 3 0 3 3 otherwise 10 20 5 Q 1 8 V VCC MEM
54. t a real application Application Note 11 Intel PXA27x Processor Family Power Requirements ntel Note The figures in Table 4 where taken from a system with no enhanced power management optimization such as Intel Wireless Speedstep which allows control over the PXA27x processors low power modes and dynamically selectable frequency and voltage change capability Table4 Intel PXA27x Processor VCC CORE Supply Current jose Dhrystones 2 1 Power MPEG4 Decode Power Kap 5 da Power voltage V Current mA mW current mA mW Current mA mW 624 MHz 455 V 658 1019 622 964 1006 1559 520 Mh E 503 729 475 689 767 1112 1 45V 416 MH j 395 533 420 567 594 802 1 35V 312 MH 297 371 333 416 436 545 1 25V 208 MH 8 208 239 263 303 295 339 1 15 NOTE Core Frequency shown above Internal bus 208MHz Memclk 208MHz SDCLK 104MHz Note Use these specifications as a guideline for power supply capacity These typical guidelines will vary across different platforms and software applications 2 1 3 2 Supply Current For Each Power Domain This section provides guidelines for the power consumption that could be seen for each power supply domain when running a heavily loaded system Focused workloads were used to exercise each power supply domain separately It is important to note that the workloads were designed to push the power consumption on each domain to a higher than normal l
55. te Intel PXA27x Processor Family Power Requirements Table 6 Possible Backup Battery Configurations 2 2 3 Backup Battery Connection Description VCC_BATT and PMIC The backup battery connects to both the VCC_BATT input and PMIC charging regulator driven from the main battery or AC adaptor supply Powering VCC from a battery directly eliminates the inefficiency of an external regulator in the PMIC maximizing the battery life in sleep and deep sleep In such a configuration ensure that the requirements for limiting current to the backup battery are observed regardless of whether it is a rechargeable or non rechargeable type Information on battery current limits is available from the battery manufacturer Series resistors and diodes might be needed to limit intentional charging current to prevent the backup battery from being drained by a discharged main battery and to prevent unintentional backup battery charging by the PXA27x processor These components may be internal or external to the PMIC PMIC only There is more flexibility in the number of cells and allowable charging voltage when the backup battery is connected only to the PMIC and the PMIC drives VCC_BATT In this configuration the PMIC must ensure that requirements for limiting current into the backup battery are observed regardless of whether it is a rechargeable or non rechargeable type The system schematic in Figure 2 shows one recomme
56. tems only five four if VCC USIM is disabled regulators are required to power the PXA27x processor and its input output interfaces as shown in Table 3 Application Note intel Table 3 Intel amp PXA27x Processor Family Power Requirements Regulators Required to Power the Intel amp PXA27x Processor Regulator Description Regulated main battery voltage nominally 3 0 V limited to a maximum of 3 75 V to power VCC and charge the optional backup battery also connected to VCC_BATT VCC IO LCD MEM BB VCC USB connected together can be powered at 1 2 3 0V or 3 3 V 10 3 VCC_USIM at 1 8V and 3 0 V 10 VCC CORE and VCC_SRAM may be connected together fixed at 1 1 V Dynamic voltage 4 management cannot be used and the maximum core clock frequency is not supported using this arrangement 5 VCC_PLL at 1 3 V More complex systems might require further separation of supply domains and additional regulators Independent PXA27x power domains provide flexibility when supporting peripherals with different I O voltages which makes it possible to reduce overall system power by supporting 1 8 V low power memory with 3 0 V peripherals Modeling Intel PXA27x processor power consumption This section provides guidelines for the power consumption required for the processor by varying the software workload In this analysis the information 1s divided into two groups Core m
57. the external power controller does not have to consider them in its design Table 2 shows the PXA27x processor voltage domains Application Note Intel amp PXA27x Processor Family Power Requirements Table 2 Intel PXA27x Processor Voltage Domains Sheet 1 of 2 Voltage Description VCC BATT BATTERY VOLTAGE Voltage limited power from the main battery or directly from a backup battery at nominal 3 0 V 25 VCC_BATT must be supplied to start the power manager When the main battery is installed VCC_BATT powers the real time clock and power management circuitry during initial power on sleep deep sleep and sleep wake up so it remains powered from the backup battery when the main power source has been discharged or removed See Section 2 2 Batteries on page 14 for information about directly connecting VCC_BATT to the backup battery or main battery NOTE The power management integrated circuit PMIC output drivers for logic signals nRESET nVDD_FAULT nBATT FAULT PWR_SDA GPIOO and GPIO1 must be powered from the VCC_BATT supply This also applies to all other digital outputs such as the JTAG signals driving PXA27x processor inputs on the VCC REG domain Any devices that have a digital input driven by PXA27x processor digital output powered from the VCC REG domain must tolerate output high drive levels between 2 25 V and 3 75 V NOTE VCC BATT must be driven by a regulator whose output is matched to t
58. tially Alternatively if DRAM contents do not need to be preserved the PXA27x processor can place the DRAMs into deep power down mode Doing so reduces DRAM power to microamps even though voltage from the PMIC is still maintained on the DRAM power signals The PXA271 and PXA272 processors contain stacked memory which is supplied power via the VCC MEM power domain The PXA27x processor commands entry into deep sleep mode by de asserting PWR_EN once the PMIC and system are prepared The PMIC responds by turning off the set of low voltage power supplies designated either by the prior register setting or fixed in PMIC hardware After a delay to allow the low voltage supplies to shut down the PXA27x processor de asserts SYS EN to the PMIC and the PMIC responds by turning off the necessary combination of high voltage supplies Note that all power supply sequencing requirements must be observed low voltage supplies must power down before any high voltage supplies power down See the ntel amp PXA27x Processor Family Electrical Mechanical and Thermal Specification data sheet for entry and exit deep sleep mode timings Application Note 6 0 6 1 Note Intel amp PXA27x Processor Family Power Requirements If the PMIC does not disable VCC CORE VCC PLL or VCC SRAM when PWR EN is de asserted the PMIC must not disable any of the regulators controlled by SYS EN when SYS EN is de asserted to ensure that supply sequencing requirements are sati
59. urst Intel NetStructure Intel Play Intel Play logo Intel Pocket Concert Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel WebOutfitter Intel Xeon Intel XScale Itanium JobAnalyst LANDesk LanRover MCS MMX MMX logo NetPort NetportExpress Optimizer logo OverDrive Paragon PC Dads PC Parents Pentium Pentium Il Xeon Pentium Xeon Performance at Your Command ProShare RemoteExpress Screamline Shiva SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside This Way In TokenExpress Trillium Vivonic and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others ii Application Note Contents ntel Intel PXA27x Processor Family Power Requirements Contents 1 0 2 0 3 0 4 0 5 0 6 0 7 0 mm 5 1 4 Naming Conventions 5 Intel PXA27x Processor Power Supply 5 2 1 Power Domains and System Voltage Current 8 2 1 1 Intel PXA27x Processor Power Supplies cceeeeeeeeeeneeceaeeeeeeeeeeeseeeteeeteneees 8 2 1 2 Power Supply Configuration in a Minimal
60. wering on from a cold start each domain must not exceed the maximum quickest ramp rate specification and the power on timing requirements should be strictly observed Refer to the Intel PXA27x Processor Family EMTS for details Power On Cold Start Power On and Hardware Reset Power on reset occurs when power is first supplied to the backup battery signal _ following a powered off condition All PXA27x processor internal units are reset to a known state exactly like hardware reset Power on reset is a complete and total reset that occurs at initial power on only Application Note Note Intel PXA27x Processor Family Power Requirements Initial Power Up and Deep Sleep Exit Sequence As shown in Figure 2 the external power management integrated circuit PMIC supplies both high voltage I O and low voltage internal power to the PXA27x processor The external voltage regulator also sources nBATT FAULT and nVDD FAULT signals to the PXA27x processor There are two power control signals e SYS EN controls the high voltage I O supplies IO LCD VCC MEM BB USB VCC_USIM PWR EN controls low voltage internal supplies VCC CORE PLL VCC SRAM Typically during system assembly the fully charged backup battery 1s soldered permanently into the system To prevent draining the backup battery prematurely Intel recommends installing the main battery
61. x processor using the maximum backup battery voltage Summary The power management integrated circuit PMIC for the PXA27x processor is a highly integrated device with both required and optional features to support the nine power domains on the PXA27x processor as well as dynamic voltage management features The PMIC and the PX A27x processor have specific signaling requirements and power mode sequencing for initial power on hardware reset and sleep and deep sleep entry and exit Performance tests and ratings contained within this application note are measured using specific computer systems and or components and reflect the approximate performance of Intel products as measured by those tests Any difference in system hardware or software design or configuration may affect actual performance Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing For more information on performance tests and on the performance of Intel products reference www intel com procs perf limits htm or call U S 1 800 628 8686 or 1 916 356 3104 88 Application Note 35 Intel 27 Processor Family Power Requirements 36 Application Note
62. y variable On power up VCC BATT is the first voltage supplied to the PXA27x processor limit VCC BATT to a maximum of 3 75 V Other voltages power domains power up following a predefined sequence as set by the control signals PWR EN and SYS EN Refer to the nte amp PXA27x Processor Family Electrical Mechanical and Thermal Specification for a description of the power on sequence VCC SRAM must power up and remain at 1 1 V VCC PLL must power up to and remain at 1 3 V VCC CORE must power up to any user selected voltage between 0 85 and 1 55V VCC USIM must default to 0 V at power up The five supplies that individually take one of several values are VCC IO VCC LCD VCC MEM VCC BB and VCC USB The voltages required for these domains are determined by other components in the system and the I O voltages they use When the system powers up Application Note 13 Intel 27 Processor Family Power Requirements ntel 2 2 2 2 1 2 2 2 these supplies must come up at the required voltage to operate reliably and to avoid damage to the external components VCC IO must be the highest potential of the system I O supplies VCC IO can be connected to any of VCC LCD VCC MEM VCC USIM VCC USB and VCC BB but none of these supplies can exceed VCC IO The power up voltage requirement must be communicated by some input strapping mechanism on the PMIC if a PMIC can provide more than one voltage level for any of these domains This

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