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Intel IXF1104 User's Manual

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1. Signal Name p m Signal Name e m Signal Name Te m GND R2 GND A21 NC P18 GND R6 GND AD21 NC R5 GND RQ PC L23 NC R10 GND R11 03 124 NC R12 GND R14 DATA 13 M24 NC R13 GND R16 DATA 23 N24 NC R15 GND R19 DATA 3 P24 NC R20 GND R23 LED CLK K24 NC T6 GND T10 LED DATA M22 NC T7 GND T15 LED LATCH L22 NC T8 GND U4 MDC W24 NC T9 GND U8 MDIO V21 NC T21 GND 012 MOD DEF INT N22 NC T22 GND U13 NC D24 NC U5 GND U17 NC E12 NC U7 GND U21 NC F11 NC U9 GND w2 NC G15 NC U11 GND W6 NC H7 NC U18 GND W10 NC H18 NC V9 GND W15 NC J21 NC V10 GND W19 NC K7 NC v11 GND W23 NC K18 NC V13 GND AAA NC K20 NC AB18 GND AAS NC K22 NC AD4 GND AA12 NC L18 NC AD5 GND AA13 NC L19 No Ball A2 GND AA17 NC L21 No Ball A3 GND 21 7 No Ball A22 GND AC6 NC M18 No Ball A23 GND AC10 NC M20 No Ball A24 GND AC15 NC N3 No Ball B1 GND AC19 NC N18 No Ball B2 GND AC14 NC P2 No Ball B23 GND L20 NC P4 No Ball B24 GND L5 NC P6 No Ball C1 GND R7 NC P7 No Ball C24 GND AB12 NC P8 No Ball AB1 GND A4 NC P17 No Ball AB24 Datasheet 25 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 26 Intel Ball B
2. 8 4 5 Global Status and Configuration Register Overview Table 103 through Table 112 ID 0x50C on page 192 provide an overview for the Global Control and Status Registers Table 103 Port Enable 0x500 Bit Name Description Type Default Register Description A control register for each port in the IXF1104 MAC Port ID bit position in the register To make a port active the bit must be set High For example Port 2 0x00000000 active implies a register value of 0000 0100 Setting the bit to 0 de asserts the enable The default state for this register is for all four ports to be disabled 31 4 Reserved Reserved RO 0x0000000 Port 3 3 Port 3 Enable 0 Disable R W 1 Enable Port 2 2 Port 2 Enable 0 Disable R W 0 1 2 Enable Port 1 1 Port 1 Enable 0 Disable R W 0 1 Enable Port 0 0 Port 0 Enable 0 Disable R W 0 1 Enable 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 104 Interface Mode 0x501 Bit Name Description Type Default Register Description If Mode Four bits of this register determines the PHY interface mode 0 Fiber SerDes OMI interface 1 Copper GMII or RGMII interface Changes to the data setting of this register must be made in conjunction with the Clock and 0x00000000 Interface Mode Change Enable Ports 0 3 0x794 to ensure a s
3. KS 147 47 CPU Interface Read Cycle AC 149 48 CPU Interface Write Cycle AC 149 49 Pause Control Interface 151 SEP CP ORELLI cm 152 51 System Reset AC Timing 153 52 LED AC Interface 154 53 Memory Overview Diagram 155 54 Register Overview 156 55 QCBGA Package aste isset Itu 225 56 CBGA Package Side View 226 57 FC PBGA Package Top and Bottom eene 227 58 FC PBGA Mechanical Specifications 228 59 Package Marking 229 60 Ordering Information Sample sess 230 Tables 1 Ball List in Alphanumeric Order by Signal 24 2 Ball List in Alphanumeric Order by Ball 30 3 SPIS Interface Signal Descriptions 39 4 SerDes Interface Signal Descriptions 47 5 GMI Interface Signal Descriptions 48 6 Interface Signal Descriptions 50 7 Interface Signal Descriptions 51 8 Transmit Pause Control Interface Signal 53 9 Optica
4. Signal Name Ball 2 Type Standard Description MPHY SPHY Designator Polled PHY Transmit Packet Available PTPA allows the polling of the port selected by the TADR address bus When High PTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark When the High watermark is crossed PTPA transitions Low to indicate that the TX FIFO is almost full It stays Low until the amount data in the TX FIFO goes back below the TX FIFO Low watermark At this point PTPA transitions High to indicate that the programmed number of bytes are 33V now available for data transfers PTPA PTPA B11 Output LVTTL NOTE For more information see Table 132 TX FIFO High Watermark Ports 0 3 0x600 0x603 on page 203 and Table 133 TX FIFO Low Watermark Register Ports 0 3 0x60A 0x60D on page 204 The port reported by PTPA is updated on the following rising edge of TFCLK after the port address on TADR is sampled by the PHY device PTPA is updated on the rising edge of TFCLK RDAT31 RDAT7 3 F24 Receive Data Bus RDAT30 RDAT6 G24 RDAT carries payload data and in band RDATS_3 G23 addresses from the IXF1104 MAC RDAT28 RDAT4 3 G22 Output 3 3 V RDAT27 RDAT3_3 G21 LVTTL Mode Bits RDAT26 RDAT2 3 G20 RDAT25 RDAT1 G19 32 bit dud 31 24 RDAT24 RDATO 3 G18 4 x 8 Single PHY 7 0 for port 3 RDAT23 RDAT7 2 E21 Receive Data Bus RDAT22 RDAT6_2 E22 RDAT ca
5. Figure 10 Transmit Pause Control Interface TXPAUSEFR A TXPAUSEADDO TXPAUSEADD1 TXPAUSEADD2 A This example shows the following conditions Strobe 1 Port 0 Transmit Pause Packet XOFF Strobe 2 All Ports Transmit Pause Packet with pause time 0 XON Strobe 3 Port Transmit Pause Packet B3234 01 Datasheet 74 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 1 3 5 1 3 1 Note 5 1 3 2 75 Mixed Mode Operation The IXF1104 MAC gives the user the option of configuring each port for 10 100 Mbps half duplex copper 10 100 1000 Mbps full duplex copper or 1000 Mbps full duplex fiber operation This gives the IXF1104 MAC the ability to support both copper and fiber operation line side interfaces operating at the same time within a single device Refer to Figure 16 Line Side Interface Multiplexed Balls on page 58 The IXF1104 MAC provides complete flexibility in line side connectivity by offering RGMII integrated SerDes and GMII Configuration The memory maps Table 59 Control Registers Port Index Offset on page 156 through Table 69 Optical Module Registers 0x799 0x79F on page 162 are logically split into the following two distinct regions Per Port Registers Global Registers To achieve a desired confi
6. 159 65 TX FIFO Registers 0x600 0 63 160 66 MDIO Registers 0x680 0 683 161 67 SPI3 Registers 0x700 0 716 161 68 SerDes Registers 0x780 0 798 162 69 Optical Module Registers 0x799 0 79 162 70 Station Address Port Index 0 00 163 71 Desired Duplex Port Index 0x02 163 72 FD FC Port Index 0x03 163 73 Collision Distance Port Index 0x05 164 74 Collision Threshold Port Index 0 06 164 Datasheet 9 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents ntel 10 TX Timer Value Port Index 0 7 164 FD FC Address Port Index 0x08 0 09 nennen 164 IPG Receive Time 1 Port Index 165 IPG Receive Time 2 Port Index 165 IPG Transmit Time Port Index 0 165 Pause Threshold Port Index OXOE 166 Max Frame Size Addr Port_Index 166 MAC IF Mode and RGMII Speed Port Index 0x10 167 Flush TX Port Index OXT 1 cred ae Monies 167 FC Enable Port Index 0x
7. 2 Y16 Output SerDes Transmit Differential Output Negative TX 3 AD18 P0 P22 RX P 1 V22 ONE RX P2 T24 Input SerDes Receive Differential Input Positive P 3 U24 RX R22 RX N 1 U22 RXN2 R24 Input SerDes Receive Differential Input Negative RX_N_3 V24 1 Internally terminated differentially with 100 Q Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 5 GMII Interface Signal Descriptions Sheet 1 of 2 Signal Name Ball Designator Type Standard Description TXD7 0 Y4 TXD6 0 AB4 TXD5_0 AC3 TXD4_0 AB3 TXD3_0 AA3 TXD2_0 Y3 TXD1_0 Y2 TXDO 0 Y1 TXD7_1 Transmit Data TXD6 1 AD8 TXD5 1 AB8 Each bus carries eight data bits 7 0 of TXD4 1 AAT the transmitted data stream to the PHY TXD3_1 AD9 device TXD2 1 AB9 ABT RGMII Mode When a port is TXDO_1 25y configured in copper mode and the Output CMOS RGMII interface is selected only bits TXD7 2 AA18 TXD S3 0 n are used The data is TXD6 2 AA20 transmitted on both edges of 0 3 TXD5 2 AB19 TXD4 2 AD16 Fiber Mode The following signals TXD3 2 AB23 have multiplexed functions when a port is configured in fiber mode TXDO 2 AB20 TXD4_n TX_DISABLE_0 3 TXD7_3 W14 TXD6 3 AA16 TXD5 3 Y15 TXD4 3 AA14 TXD3 3 V17 TXD2 3 V16 TXD1 3 V15 TXDO 3 V14 Tra
8. Copper Mode Fiber Mode mem m Optica Module Unused Port Ball Designator TXC_0 3 TXC_0 3 NC NC AA1 AD7 AC20 AB14 TXD 3 0 0 TD 8 0 0 Y2 Y1 TXD 3 0 1 TD 8 0 1 NC NC AD9 AB9 AB7 TXD 3 0 2 TD 3 0 2 AB23 AB22 21 AB20 TXD 3 0 3 TD 8 0 3 V17 V16 V15 V14 TXD4 0 3 NC TX DISABLE 0 3 NC AB3 AA7 16 14 TXD 7 5 0 YA NC NO AMIS TXD 7 5 3 Wi4 AA16 15 TX EN 0 3 TX 0 3 NC NC AB2 Y8 AC22 12 TX ER 0 3 NC NC NC wi AD6 017 1 RXC_0 3 RXC_0 3 GND GND V4 AD11 AA24 V23 RXD 3 0 0 RD 3 0 0 Y7 W7 V7 V8 RxDj 9 2 GND GND v s RXD 3 0 3 RD 3 0 3 W18 Y19 Y18 Y17 RXD4 0 3 GND MOD DEF 0 3 GND Y6 AD10 W22 T16 RXD5 0 3 GND TX FAULT 0 3 GND Y5 AC11 V20 T17 RXD6 0 3 GND RX LOS 03 GND AB5 AA11 V19 T18 RXD7 0 3 GND GND GND AC5 Y10 W20 T19 DV 0 3 0 3 GND GND V5 ABI1 Y24 V18 RX ER 0 3 GND GND GND W5 Y12 AA22 U20 CRS_0 3 GND GND GND 5 9 5 16 COL 0 3 GND GND GND AB6 AB10 AD15 AB17 GND GND RX_P_0 3 GND P22 V22 T24 U24 GND GND RX_N_0 3 GND R22 U22 R24 V24 NC NC TX_P_0 3 NC Y13 AD13 W16 AC18 NC NC TX 0 3 NC Y14 AD14 Y16 AD18 1 An external pull up resistor is required with most optical modules 2 An open drain I O external 4 7 Q pull up resistor is required Datasheet 58 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4
9. 135 45 ROMI PONG 136 46 SPI3 Receive Interface Signal Parameters 138 47 Transmit Interface Signal Parameters 140 48 RGMII Interface Timing Parameters 141 49 GMII 1000BASE T Transmit Signal Parameters 142 50 1000BASE T Receive Signal Parameters 143 51 SerDes Timing Parameters 144 52 MDIO Timing Parameters 146 58 CAG Timing iet nni Gut 147 54 CPU Interface Write Cycle AC Signal Parameters 150 55 Transmit Pause Control Interface Timing Parameters seen 151 56 JTAG AC Timing Parameters 152 57 System Reset AC Timing Parameters 153 58 LED Interface AC Timing 154 59 Control Registers Port Index Offset sss 156 60 MAC Statistics Registers Port Index 157 61 MAC TX Statistics Registers Port Index 158 62 PHY Autoscan Registers Port Index 159 63 Global Status and Configuration Registers 0x500 159 64 RX FIFO Registers 0x580
10. Table 148 Address Parity Error Packet Drop Counter 0x70A Bit Name Description Default Register Description This register counts the number of packets dropped due to parity error 0x00000000 detection during the address selection cycle 31 8 Reserved Reserved RO 0x000000 This is an 8 bit counter that counts the number of packets dropped due to parity error detection during the address selection cycle This gets 7 0 Address Parity Error cleared when read and saturates at 8 hFF There R 0x00 is only one counter for address parity drop as address will be used only in MPHY mode of operation The counter gets cleared once the register is read 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 8 4 10 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller SerDes Register Overview Table 149 through Table 152 Clock and Interface Mode Change Enable Ports 0 3 0x794 on page 221 define the contents of the SerDes registers at base location 0x780 which contain the control and status for the four SerDes interfaces on the IXF1104 MAC Table 149 TX Driver Power Level Ports 0 3 0x784 Bit Name Description Type Default Register Description Allows
11. Tsu min 16 ns Tpw min 16 ns 39 4 amp Thold min 16 ns Transmit Pause Control Interface Timing Parameters Symbol Parameter Min Max Units Tsu TXPAUSEADD stable prior to TXPAUSEFR High 16 ns Tpw TXPAUSEFR pulse width 16 ns Thold TXPAUSEADD stable after TXPAUSEFR High 16 ns Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 10 JTAG AC Timing Specification Figure 50 and Table 56 provide the JTAG AC timing specifications Figure 50 JTAG AC Timing Table 56 JTAG AC Timing Parameters Symbol Parameter Min Max Units Tjc TCLK cycle time 90 ns Tjh TCLK High time 0 4 x 0 6 x Tjc ns TCLK low time 0 4 x 0 6 x Tjc ns Tjval TCLK falling edge to TDO valid 25 ns Tjsu TMS TDI setup to TCLK 20 ns Tjsh TMS TDI hold from TCLK 5 ns Datasheet 152 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 7 11 System AC Timing Specification Figure 51 and Table 57 illustrate the system reset AC timing specifications Figure 51 System Reset AC Timing Sys Res H m Trt CPU Access Table 57 System Reset AC Timing Parame
12. anes se 69 5 1 2 1 802 3x Flow Control Full Duplex 70 5 1 3 Mixed Mode Operation 75 5 1 3 1 75 5 1 3 2 Key Configuration Registers 2 75 514 Fiber MOGO iunii nidi sa inea so 76 5 1 4 1 Fiber 71 5 1 4 2 Determining If Link Is Established Auto Negotiation Mode 77 5 1 4 3 Fiber Forced 71 5 1 4 4 Determination of Link Establishment in Forced Mode 77 Dil ERN 77 Datasheet 3 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents 5 2 5 3 5 4 5 5 5 6 m BEES E AEE 78 5 1 5 2 DIU EE 78 5 1 5 3 Copper Auto Negotiation 78 5 1 6 Jumbo Packet Support 78 51601 RX Statistics 79 5 1 6 2 TX SIatisli6S eee caet cetur rtr ehe bbe oa ene 79 5 1 6 3 Loss less Flow entrent 79 5 1 7 Packet Buffer Dimensions 80 5 1 7 1 TX and RX FIFO Operation 80 5 1 8 RMON Statistics 5 80 muB Rime m 82 5 1 8 2 Advantages gt 83 S
13. Table 120 RX FIFO Low Watermark Port 3 0x58D Bit Name Description Default Register Description The default value of 0x072 represents 114 eight byte locations This equates to 912 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO falls below the Low watermark flow control is 0x072 automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 31 12 Reserved Reserved RO 0x00000 The High watermark value RX FIFO Low R W 0x072 Watermark Port 3 NOTE Should never be greater or equal to the High Watermark 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 121 RX FIFO Overflow Frame Drop Counter Ports 0 3 0x594 0x597 Name Description Address Default RX FIFO Overflow When RX FIFO on port 0 becomes full or Frame Drop reset the number of frames lost dropped on 0x594 R 0x00000000 Counter on port 0 this port are shown in this register RX FIFO Overflow When RX FIFO on port 1 becomes full or Frame Drop reset the number of frames lost dropped on 0x595 R 0x00000000 Counter on port 1 this port are shown in this register RX FIFO Overflow When RX FIFO on port 2 becomes full or Frame Drop reset the number of frames lost dropped on 0x596
14. 81 83 X Y 56 59 00001 Bo B3 X Vm XXX ir X 0 X X na f wo car B3217 02 Figure 13 MPHY 32 Bit Interface SPI3 Bus Network Processor IXF1104 MPHY Line Side Interface Mode TFCLK TFCLK TENB TENB 0 Transceiver TDAT 31 0 TDATT 31 0 TMOD 1 0 TMOD 1 0 TPRTY TPRTY 0 TSOP TSOP 0 TEOP TEOP 0 Transceiver TERR TSX DTPA 0 3 STPA PTPA TADR 1 0 RFCLK RENB RDAT 31 0 RMOD 1 0 TERR 0 TSX DTPA 0 3 STPA PTPA TADR 1 0 Transceiver RFCLK RENB 0 RDAT 31 0 RMOD 1 0 Transceiver RPRTY RPRTY 0 RVAL RVAL 0 RSOP RSOP 0 REOP REOP 0 RERR RERR_O RSX RSX 0660 02 Datasheet 86 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 2 2 3 Note 5 2 2 4 5 2 2 5 87 Note Clock Rates In MPHY mode the TFCLK and RFCLK can be independent of each other TFCLK and RFCLK should be common to the IXF1104 MAC and the Network Processor The IXF1104 MAC requires a single clock source for the transmit path and a single clock source for the receive path To allow all four IXF1104 MAC ports to operate at 1 Gbps the IXF1104 MAC is designed to allow this interface to be overclocked This allows operation for data transfer at data rates of up to 4 256 Gbps when operating at an overclocked frequ
15. 9 9 9 W9 V9 9 9 R9 P9 N9 9 L9 K9 J9 H9 G9 F9 E9 D9 C9 B9 9 19 10 AD10 10 10 10 Y10 W10 V10 U10 T10 R10 P10 M10 L10 H10 G10 F10 D10 C10 B10 A10 10 11 AD11 11 ABT1 11 11 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11 11 12 AD12 12 12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 K12 J12 H12 G12 F12 E12 D12 C2 B12 A12 12 13 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 L13 K13 J13 H13 G13 F13 E13 D13 C13 B13 A13 13 14 14 AC14 14 14 Y14 W14 V14 U14 T14 R14 P14 N14 M14 L14 K14 J14 H14 G14 F14 E14 D14 C14 B14 A14 14 15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 P15 N15 M15 L15 15 J15 H15 G15 F15 E15 D15 C15 B15 15 15 16 AD16 AC16 16 AA16 Y16 w16 vie U16 T16 R16 P16 N16 MIG 116 K16 J16 H16 G16 F16 E16 Die c16 B16 Ais 16 17 AD17 AC17 17 AA17 17 W17 V17 U17 T17 R17 P17 N17 M17 L17 K17 J17 H17 G17 F17 E17 D17 C17 B17 A17 17 18 AD18 AC18 18 AA18 Y18 W18 V18 U18 T18 R18 P18 N18 M18 118 K18 J18 H18 G18 F18 E18 D18 C18 B18 A18 18 19 AD19
16. Bit Name Description Default 10BASE T 0 DTE is 10BASE T full duplex mode 6 Full Duplex capable RO 1 1 DTE is 10BASE T full duplex mode capable 10BASE T 0 2 10BASE T half duplex mode HS up 1 DTE is 10BASE T half duplex mode capable 00001 IEEE 802 3 00010 IEEE 802 9 ISLAN 16T 00000 Reserved for future auto negotiation development 4 0 Selector Field 11111 Reserved for future auto negotiation RO 00001 514 0 development Unspecified or reserved combinations should not be transmitted Setting this field to a value other than 00001 will most likely cause auto negotiation to fail 1 RO Read Only RR Clear on Read W Write R W Read Write Table 100 Auto Negotiation Link Partner Base Page Ability Port Index 0x65 Sheet 1 of 2 Bit Name Description Default 0 0 01001111000 01 31 16 Reserved Reserved RO 0 0 Link partner has no ability to send multiple 15 Next Page pages RO NA 9 1 Link partner has the ability to send multiple pages 0 Link partner has not received Link Code Word from the IXF1104 MAC 14 Acknowledge 1 Link partner has received Link Code Word RO from the IXF1104 MAC No remote fault 13 Remote Fault ie Remote fault RO NA 12 Reserved Reserved RO 0 Advertise Asymmetric Pause Direction Register bit This register bit is used in conjunction with P Register bit 4 10 11 ASM DIR
17. 99 MDIO Control and Interface iei eiecit canens che ns eta 99 5 5 1 MIDIO cc c 100 5 5 2 MDIO Register Descriptions 100 5 5 3 Clear When 100 5 5 4 Generalo PE 100 5 5 4 1 MDC High Frequency Operation 100 5 5 4 2 MDC Low Frequency Operation 100 5 5 5 Management 5 101 5 5 6 Single MDI Command 101 5 5 7 MDI State Machine 101 5 5 8 A utoscan Operation aprecio 103 SOMOS NLC MACC TE 103 5 6 1 Features c eatin 103 5 6 2 Functional 103 5 6 2 1 Transmitter Operational Overview 104 5 6 2 2 Transmitter Programmable Driver Power Levels 104 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ntel 8 Contents 5 7 5 8 5 9 Datasheet 5 6 2 3 Receiver Operational Overview 105 5 6 2 4 Selective 105 5 6 2 5 Receiver Jitter 105 5 6 2 6 transiit Jitter cernere deren x 106 5 6 2 Receive Jillor o cortice dec tee d 106 Optical Module Interface t ee ER OR DARE Od EN 107 5 7 1 Intel I
18. Error Pass Filter bit 0 Table 22 CRC Errored Packets Drop Enable Behavior 5 1 1 4 5 1 2 69 RX FIFO Errored CRC Error RERR 3 Pass cie Enable Actions When CRC Errored PASS 1 CRC errored packets 1 x are not filtered and are passed to the interface They are not marked as bad cannot be dropped and cannot be signaled with RERR Packets are marked as bad but not dropped in the 0 0 1 RX FIFO These packets are sent to the SPIS interface and are signaled with an RERR to the Switch or Network Processor Packets are marked as bad but not dropped in the 0 0 0 RX FIFO These packets are sent to the SPIS interface and are not signaled with an RERR CRC errored packets are marked as bad dropped in the RX FIFO and never appear at the interface NOTE Packet sizes above the RX FIFO Transfer 0 1 Threshold see Table 128 through Table 131 cannot be dropped in the RX FIFO and are passed to the SPI3 interface These packets can optionally be signaled with RERR on the SPI3 interface if the RERR Enable bit 1 1 See Table 91 RX Packet Filter Control Port Index 0x19 on page 172 2 See Table 123 RX FIFO Errored Frame Drop Enable 0x59F on page 196 3 See Table 147 SPI3 Receive Configuration 0x701 on page 215 NOTE x DON T CARE CRC Error Detection Frames received by the MAC are checked for a correct CRC When an incorrect
19. Symbol Parameter Min Max Units frequency 133 2 duty cycle 45 55 926 TStenb TENB setup time to TFCLK 1 8 5 THtenb TENB hold time to TFCLK 0 5 ns TStdat TDAT 31 0 setup time to TFCLK 1 8 ns THtdat TDAT 31 0 hold time to 0 5 ns TStprty TRPTY setup time to TFCLK 1 8 ns THtprty TPRTY hold time to TFCLK 0 5 E ns TStsop TSOP setup time to TFCLK 1 8 ns THtsop TSOP hold time to TFCLK 0 5 ns TSteop TEOP setup time to TFCLK 1 8 5 THteop TEOP hold time to TFCLK 0 5 5 TStmod TMOD setup time to TFCLK 1 8 ns THtmod TMOD hold time to TFCLK 0 5 ns TSterr TERR setup time to TFCLK 1 8 ns THterr TERR hold time to TFCLK 0 5 ns TStsx TSX setup time to TFCLK 1 8 ns THtsx TSX hold time to TFCLK 0 5 ns TStadr TADR setup time to TFCLK 1 8 5 THtadr TADR hold time to TFCLK 0 5 ns TPdtpa TFCLK High to DTPA valid 1 5 3 7 ns TPstpa TFCLK High to STPA valid 1 5 3 7 ns TPptpa TFCLK High to PTPA valid 1 5 3 7 ns NOTES Transmit I O Timing 1 When a setup time is specified between an input and a clock the setup time is the time in nanoseconds from the 1 4 V point of the input to the 1 4 volt point of the clock 2 When a hold time is specified between an input and clock the hold time is the time in nanoseconds from the 1 4 V point of the clock to the 1 4 volt point of the input 3 Output propagation delay time is the time in nanoseconds from the 1 4 V point of the reference signal to the
20. Table 123 RX FIFO Errored Frame Drop Enable 0x59F Sheet 1 of 2 Port 3 1 Frame Drop Enable 0 Frame Drop Disable Bit Name Description Default Register Description This register configures the dropping of error packets DEBAD 0x00000000 NOTE Jumbo packets are not dropped 31 4 Reserved Reserved RO 0x0000000 This bit is used in conjunction with MAC filter bits RX FIFO Errored This allows the user to select whether the errored 3 Frame Drop Enable packets are to be dropped or not R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 196 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 123 RX FIFO Errored Frame Drop Enable 0x59F Sheet 2 of 2 Intel Bit Name Description Default This bit is used in conjunction with MAC filter bits RX FIFO Errored This allows the user to select whether the errored 2 Frame Drop Enable packets are to be dropped or not R W 0 Port 2 1 Frame Drop Enable 0 Frame Drop Disable This bit is used in conjunction with MAC filter bits RX FIFO Errored This allows the user to select whether the errored 1 Frame Drop Enable packets are to be dropped or not R W 0 Port 1 1 Frame Drop Enable 0
21. TxDeferred Number of times the initial transmission attempt of a frame is postponed due to another frame already being transmitted on the Ethernet network TxTotalCollisions NOTE NA half duplex only Port_Index 0x4C 0x00000000 TxTotalCollisions Sum of all collision events NOTE NA half duplex only Port_Index 0x4D R 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 94 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller MAC TX Statistics Port Index 0x40 0x58 Sheet 3 of 4 Name Description Address Default TxSingleCollisions A count of successfully transmitted frames on a particular interface where the transmission is inhibited by exactly one collision A frame that is counted by an instance of this object is also counted by the corresponding instance of either the UnicastPkts MulticastPkts or BroadcastPkts and is not counted by the corresponding instance of the MultipleCollisionFrames object NOTE NA half duplex only Port Index Ox4E 0x00000000 TxMultipleCollisions A count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one
22. inputs to IXF1104 MAC These signals are pulled to a logic Low level by the optical module during normal operation which indicates that no loss of signal exists If a loss of signal occurs a logic High is received on these inputs through the use of an external pull up resistor at the IXF1104 MAC device pad The status of each bit one for each port is found in Optical Module Status Ports 0 3 0x799 bits 23 20 Any change in the state of these bits causes a logic Low level on the RX LOS INT output if this operation is enabled 5 7 2 2 4 TX DISABLE 0 3 TX DISABLE 0 3 are outputs from the IXF1104 MAC These signals are driven to a logic Low level by the IXF1104 MAC during normal operation This indicates that the optical module transmitter is enabled If the optical module transmitter is disabled this signal is switched to a logic High level On the IXF1104 MAC these outputs are open drain types and pulled up by the 4 7 k to 10 k pull up resistor at the Optical Module Interface Each of these signals is controlled through bits 3 0 respectively of the Optical Module Control Ports 0 3 0x79A 5 7 2 2 5 MOD DEF INT MOD DEF INT is a single output open drain type signal and is active Low A change in state of any MOD DEF 0 3 inputs causes this signal to switch Low and remain in this state until a read of the Optical Module Status Ports 0 3 0x799 The signal then returns to an inactive state 5 7 2 2 6 TX FAULT INT
23. Port 0 of the MAC IF Mode and RGMII Speed Port Index 0x10 and the Change Enable Bit 1 Port 1 Interface Mode 0x501 copper fiber Ports 0 A Bit 2 Port 2 When any of these two configuration values are changed for a port the 0x794 Bit 3 Port 3 corresponding bits must be kept in this register under reset by writing 0x0 to the relevant bit NOTE The initialization sequence provided in Section 6 1 Change Port Mode Initialization Sequence on page 130 must be followed for proper configuration of the IXF1104 MAC Fiber Mode When the IXF1104 MAC is configured for fiber mode the TX Data path from the MAC is an internal 10 bit interface as described in the IEEE 802 3z specification It is connected directly to an internal SerDes block for serialization deserialization and transmission reception on the fiber medium to and from the link partner The MAC contains all of the PCS 8B 10B encoding and 10B 8B decoding required to encode and decode the data The MAC also supports auto negotiation per the IEEE 802 32 specification via access to the TX Config Word Port Index 0x17 RX Config Word Index 0x16 and Diverse Config Write Port Index 0x18 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 76 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 1 4 1 Note 5 1 4 2 5 1 4 3 5 1 4 4 Note
24. Symbol Parameter Min Max Units tsu STA Start setup time 4 7 us Data in hold time 0 us tsu DAT Data in setup time 200 ns Inputs rise time 1 0 us tr Inputs fall time 300 ns tsu sto Stop setup time 4 7 us Data out hold time 100 ns twr Write cycle time 10 ms Datasheet 148 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 7 8 CPU AC Timing Specification 7 8 1 CPU Interface Read Cycle AC Timing Figure 47 Figure 48 and Table 54 illustrate the CPU interface read and write cycle AC timing Figure 47 CPU Interface Read Cycle AC Timing lt Tcas uPx ADD 12 0 x uPx CsN Torr gt 4 TCAH gt uPx RdN gt uPx Data 31 0 gt i uPx RdyN TCDRD gt 7 8 2 CPU Interface Write Cycle AC Timing Figure 48 CPU Interface Write Cycle AC Timing lt Toas gt lt _ TcAH uPx Add 12 0 uPx CsN uPx WrN pae uPx Data 31 0 lt Tcbws uPx RdyN TCDWD 3 149 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 54 CPU Interface Write Cycle AC Signal Paramet
25. 209 140 TX FIFO Occupancy Counter for Ports 0 0x62D 0 630 210 141 TX FIFO Port Drop Enable 50 630 210 142 MDIO Single Command 0 680 211 143 MDIO Single Read and Write Data 90 681 211 144 Autoscan PHY Address Enable 0 682 212 145 MDIO Control 683 212 146 Transmit and Global Configuration 90 700 213 147 Receive Configuration 90 701 77777 215 148 Address Parity Error Packet Drop Counter 60 70 219 149 TX Driver Power Level Ports 0 90 784 220 150 TX and RX Power Down 0 787 2 220 4 000 000000 220 151 RX Signal Detect Level Ports 0 0x793 serene 220 152 Clock and Interface Mode Change Enable Ports 0 3 0 794 221 153 Optical Module Status Ports 0 3 0x799 sse 222 154 Optical Module Control Ports 0 0x79A 222 155 Control Ports 0 S0X79B 223 156 I C Data Ports 0 79 223 157 Product 230 Datasheet 11 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents Revis
26. 3 3 eI t ree Rape 189 MAC Soft Reset 0 505 189 MDIO Soft Reset 0x506 aient ertet ka de OL 190 CPU Interface 508 cet Canter Rae bn Aene Rer 190 EED Control 5 09 er eere EEUU RE Drs ae EORR ean eed ae 190 LED 0 50 191 16 0 50 24 Hane nea ce e aee e 191 JTAG IDADOXS0C 192 RX FIFO High Watermark Port 0 0 580 193 RX FIFO High Watermark Port 1 0 581 193 RX FIFO High Watermark Port 2 0x582 sse 193 RX FIFO High Watermark Port 0 583 194 RX FIFO Low Watermark Port 0 GOX58A 194 RX FIFO Low Watermark Port 1 0 58 194 RX FIFO Low Watermark Port 2 GOX58C 195 RX FIFO Low Watermark Port GOX58D 195 RX FIFO Overflow Frame Drop Counter Ports 0 0x594 0 597 195 RX FIFO Port Reset 0x59E 196 RX FIFO Errored Frame Drop Enable 59 196 RX FIFO Overflow Event 0x5A0 cescceecceeseeseceeeeeeeeeceaecesaeceaeeceaeeeaeesaaeseaeeseeeeeeeeseneestees 197 Datasheet Document Number 278757 Revi
27. Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 2 in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 RX FIFO transfer threshold for port 2 This must be less than the RX FIFO High water mark User definable control register that sets the threshold where a packet starts transitioning to the 110 RX FIFO Transfer SPI3 interface from the RX FIFO before the is pyw Ox0BE 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 131 RX FIFO Transfer Threshold Port 3 0x5BB Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 3 in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 RX FIFO Transfer Threshold Port 3 RX FIFO transfer threshold for port 3 This must be less than the RX FIFO High water mark User definable control register that sets the threshold where a packet starts transitioning to the SPI3 interface from the RX FIFO before the EOP is received Packets received in the RX FIFO below this threshold are treated as store and forward NOTE Do not program the RX FIFO transfer threshold below a setting of OXBE 1520bytes R W OxOBE 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear
28. Packet Filter Control Port Index 0x19 0 Pause frames received in this mode are marked by the MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the pause frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3 Receive Configuration 0x701 on page 215 When bit 4 of the RX Packet Filter Control Port_Index 0x19 1 all pause frames are sent out the SPI3 interface Pause packets are not filtered if flow control is disabled in the Enable Port Index 0x12 5 1 1 3 6 Filter CRC Error Packets This feature is enabled when bit 5 of the Packet Filter Control Port Index 0x19 0 Frames received with an errored CRC are marked as bad frames and may optionally be dropped in the RX FIFO Otherwise the frames are sent to the SPI3 interface and may be optionally signaled with an RERR see Table 22 CRC Errored Packets Drop Enable Behavior on page 69 68 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel When the CRC Error Pass Filter bit 0 RX Packet Filter Control Index 0x19 it takes precedence over the other filter bits Any packet Pause Unicast Multicast or Broadcast packet with a error will be marked as a bad frame when the
29. TX FAULT INT is a single output open drain type signal and is active Low A change in state of any TX FAULT 0 3 inputs causes this signal to switch Low and remain in this state until a read of the Optical Module Status Ports 0 3 0x799 The signal then returns to an inactive state 5 7 2 2 7 RX LOS INT RX LOS INT is a single output open drain type signal and is active low A change in state of any of the LOS 3 0 inputs causes this signal to switch low and remain in this state until a Read of the Optical Module Status Ports 0 3 0x 799 has taken place The signal returns to an inactive state MOD DEF INT TX FAULT INT and LOS INT are open drain type outputs With the three signals on the device the system can decide which Optical Module Status Ports 0 3 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 7 3 Note 5 7 3 1 5 7 3 2 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 0x799 bits to look at to identify the interrupt condition source port However this is achieved at the expense of the three device signals 2 Module Configuration Interface The PC interface is supported on SFP optical modules Details of the operation are found in the SFP Multi Source Agreement which details the contents of the registers and addresses accessible on a given Optical Module Interface supporting this interface The SFP MSA identi
30. amount of data stored in the RX FIFO falls below the Low Watermark flow control is 0x072 automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 31 12 Reserved Reserved RO 0x00000 The High Watermark value 11 0 EL EUR 1 NOTE Should never be greater or equal to the R W 0x072 High Watermark 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet 194 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 119 RX FIFO Low Watermark Port 2 0x58C Bit Name Description Default Register Description The default value of 0x072 represents 114 eight byte locations This equates to 912 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO falls below the Low Watermark flow control is 0x072 automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 31 12 Reserved Reserved RO 0x00000 The High Watermark value 11 0 1 2 NOTE Should never be greater or equal to the R W 0x072 High Watermark 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write
31. 0x500 0X50C Register BitSize Mode Ref Page Address Port Enable 0x500 32 R W 188 0x500 Interface Mode 0x501 32 R W 188 0x501 Link LED Enable 0x502 32 R W 189 0x502 Reserved 32 RO 0x503 0x504 MAC Soft Reset 0x505 32 R W 189 0x505 MDIO Soft Reset 0x506 32 R W 190 0x506 Reserved 32 RO 0 507 CPU Interface 0x508 32 R W 190 0x508 LED Control 0x509 32 R W 190 0x509 LED Flash Rate 0x50A 32 R W 191 0x50A LED Fault Disable 0x50B 32 R W 191 0x50B JTAG ID 0x50C 32 R 192 0x50C RX FIFO Registers 0x580 0 5 Sheet 1 of 2 Register Bit Size Mode Ref Page Address RX FIFO High Watermark Port 0 0x580 32 R W 193 0x580 RX FIFO High Watermark Port 1 0x581 32 R W 193 0x581 RX FIFO High Watermark Port 2 0x582 32 R W 193 0x582 RX FIFO High Watermark Port 3 0x583 32 R W 194 0x583 Reserved 32 RO 0x584 0x589 RX FIFO Low Watermark Port 0 0x58A 32 R W 194 0x58A RX FIFO Low Watermark Port 1 0x58B 32 R W 194 0x58B RX FIFO Low Watermark Port 2 0x58C 32 R W 195 0x58C Datasheet 159 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 64 RX FIFO Registers 0x580 OX5BF Sheet 2 of 2 Register Bit Size
32. 4 0 Ball Assignments and Signal Descriptions 4 1 4 1 1 4 1 2 37 Naming Conventions Signal Name Conventions Signal names begin with a Signal Mnemonic and can also contain one or more of the following designations a differential pair designation a serial designation a port designation RGMII interface and an active low designation Signal naming conventions are as follows Differential Pair Port Designation The positive and negative components of differential pairs tied to a specific port are designated by the Signal Mnemonic immediately followed by an underscore and either P positive component or N negative component and an underscore followed by the port designation For example SerDes interface signals for port 0 are identified as TX P Oand TX 0 Serial Designation A set of signals that are not tied to any specific port are designated by the Signal Mnemonic followed by a bracketed serial designation For example the set of 11 CPU Address Bus signals is identified as UPX_ADD 10 0 Port Designation Individual signals that apply to a particular port are designated by the Signal Mnemonic immediately followed by an underscore and the Port Designation For example Transmit Control signals are identified as TX 0 TX CTL 1 TX 2 and so on Port Bus Designation A set of bus signals that apply to a particular port are designated by the Signal Mnemonic immediately followed by a
33. Added Table 122 Tx and Rx Power Down Register Addr 0x787 194 Replaced Figure 53 Intel IXF1104 Example Package Marking Revision 005 Revision Date April 30 2003 Page Description Initial external release Revisions 001 through 004 Revision Date April 2001 December 2002 Page Description Internal releases Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 19 intel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 1 0 Introduction This document contains information on the IXF1104 MAC a four port Gigabit Media Access Controller that supports IEEE 802 3 10 100 1000 Mbps applications 1 1 What You Will Find in This Document This document contains the following sections Section 2 0 General Description on page 21 provides the block diagram system architecture Section 3 0 Ball Assignments and Ball List Tables on page 23 shows the signal naming methodology and signal descriptions Section 4 0 Ball Assignments and Signal Descriptions on page 37 illustrates and lists the IXF1104 ball grid diagram with two ball list tables by signal name and ball location Section 5 0 Functional Descriptions on page 66 gives detailed information about the operation of the IXF1104 including general features and interface types and descriptions Section 7 0 Electrical Specification
34. Datasheet 146 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 7 Optical Module and I C AC Timing Specification 7 7 1 2 Interface Timing Figure 45 and Figure 46 illustrate bus timing and write cycle and Table 53 shows the Interface AC timing characteristics Figure 45 Bus Timing Diagram HIGH PC Low Low 15 5 HD DAT 4 gt 4 gt 5 gt susTo In e tan 4 H toy PC Data Out Figure 46 Write Cycle Diagram PC CIK nts Data Be ACK WORD n gt STOP START CONDITION CONDITION Table 53 AC Timing Characteristics Sheet 1 of 2 Symbol Parameter Min Max Units Clock frequency SCL 100 kHz Clock pulse width low 4 7 us THIGH Clock pulse width High 4 0 us ti Noise suppression 100 us tAA Clock low to data valid out 0 1 4 5 us tBuF Time the bus must be free before a new transmission starts 4 7 us tuD STA Start hold time 4 0 us 147 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 53 2 AC Timing Characteristics Sheet 2 of 2
35. Enables the selected RX port R W 0 1 Rx port enable Port 0 SPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected RX port MPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected RX port R W 0 1 Rx core enable SPHY Mode NA Write as 1 ignore on Read MPHY Mode 0 Disables the RX core 1 Enables the RX core R W 0 1 IBA 5 0 SPHY Mode NA Write as 0 ignore on Read MPHY Mode Sets the 6 bit value appended to the 2 bit address during the port address selection R W 0x00 RERR_enable SPHY Mode MPHY Mode Frames marked to be filtered based on the settings in the RX Packet Filter Control Port_Index 0x19 or frames above the Max Frame Size Addr Port Index 0x0F that are not dropped in the RX FIFO see RX FIFO Errored Frame Drop Enable 0x59F can be optionally indicated with an RERR when sent out the SPI3 interface 0 Packets not indicated with RERR 1 Packets indicated with RERR R W 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 218 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 219 In
36. Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Datasheet The Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller hereafter referred to as the IXF1104 MAC supports IEEE 802 3 10 100 1000 Mbps applications The IXF1104 MAC supports a System Packet Interface Phase 3 SPI3 system interface to a network processor or ASIC and concurrently supports copper and fiber physical layer devices PHYs The copper PHY interface supports the standard and reduced pin count Gigabit Media Independent Interface GMII and for high port count applications For fiber applications the integrated Serializer Deserializer SerDes on each port supports direct connection to optical modules to reduce PCB area requirements and system cost Product Features m Four Independent Ethernet MAC Ports for m Programmable Packet handling Copper or Fiber Physical layer connectivity Filter broadcast multicast unicast VLAN IEEE 802 3 compliant and errored packets Independent Enable Disable of any port Automatically pad undersized Tx packets m Copper Mode Remove CRC from Rx packets for 10 100 1000 Mbps links m Performance Monitoring and Diagnostics for 1000 Mbps full duplex links RMON Statistics IEEE 802 3 MDIO interface CRC calculation and error detection m Fiber Mode Detection of length error runt or overly Integrated SerDes interface for direct large packets connection
37. Mode Ref Page Address RX FIFO Low Watermark Port 3 0x58D 32 R W 195 0x58D Reserved 32 RO Ox58E 0x593 RX FIFO Overflow Frame Drop Counter Port 0 32 R 195 0x594 RX FIFO Overflow Frame Drop Counter Port 1 32 R 195 0x595 RX FIFO Overflow Frame Drop Counter Port 2 32 R 195 0x596 RX FIFO Overflow Frame Drop Counter Port 3 32 R 195 0x597 Reserved 32 RO 0x598 0x59D RX FIFO Port Reset 0x59E 32 R W 196 Ox59E RX FIFO Errored Frame Drop Enable 0x59F 32 R W 196 0x59F RX FIFO Overflow Event 0x5A0 32 R 197 0x5A0 Reserved 32 R Ox5A1 0x5A5 RX FIFO Errored Frame Drop Counter Port 0 32 R 198 0x5A2 RX FIFO Errored Frame Drop Counter Port 1 32 R 198 0x5A3 RX FIFO Errored Frame Drop Counter Port 2 32 R 198 0x5A4 RX FIFO Errored Frame Drop Counter Port 3 32 R 198 0x5A5 Reserved 32 RO 0x5A6 0x5B1 bein SPI3 Loopback Enable for Ports 0 3 32 RW 199 0x5B2 RX FIFO Padding and CRC Strip Enable 0x5B3 32 R W 200 0x5B3 Reserved 32 R 0x5B4 0x5B7 RX FIFO Transfer Threshold Port 0 0x5B8 32 R W 201 0x5B8 RX FIFO Transfer Threshold Port 1 0x5B9 32 R W 201 0x5B9 RX FIFO Transfer Threshold Port 2 0x5BA 32 R W 201 0x5BA RX FIFO Transfer Threshold Port 3 0x5BB 32 R W 202 0x5BB Reserved 32 R Ox5BC 0x5BF Table 65 TX FIFO Registers 0x600 Ox63E Sheet 1 of 2 Register Bit Size Mode Ref Page Address TX FIFO High Watermark Port 0 32 R W 203 0x600 TX FIFO High Watermark Port 1 32 R W 203 0x
38. Source Agreement MSA There are specific mechanical and electrical requirements for the size form factor and connections supported on all Optical Module Interfaces There are also specific requirements for each Optical Module Interface that supports a particular media requirement or interface configuration These requirements are detailed in the relevant specifications or manufacturers datasheets IXF1104 MAC Intel amp IXF1104 MAC Supported Optical Module Interface Signals To describe the Optical Module Interface operation three supported signal subgroups are required allowing a more explicit definition of each function and implementation The three subgroups are as follows High Speed Serial Interface Low Speed Status Signaling Interface PC Module Configuration Interface Table 30 provides descriptions for IXF1104 MAC to SFP optical module connection signals Table 30 Intel IXF1104 MAC to SFP Optical Module Interface Connections Sheet 1 of 2 107 IXF1104 MAC SFP Signal Signal Names Names oe holes TX P 0 3 TD Transmit Data Differential LVDS Output from the IXF1104 MAC TX_N_0 3 TD Transmit Data Differential LVDS Output from the IXF1104 MAC RX_P_0 3 RD Receive Data Differential LVDS Input to the IXF1104 MAC RX_N_0 3 RD Receive Data Differential LVDS Input to the IXF1104 MAC 2 output from the MOD DEF1 IXF1104 MAC SCL Output from the IXF1104 MAC I C DATA 0
39. 0x5B2 renamed heading and bit name changed description and type for bits 7 0 201 Renamed Table 128 RX FIFO Transfer Threshold Port 0 0x5B8 on page 201 from RX FIFO Jumbo Packet Size changed bit names and edited added text under description Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 17 Contents Revision Number 007 Revision Date March 24 2004 Sheet 5 of 5 Page Description 207 Modified Table 136 Loop RX Data to TX FIFO Line Side Loopback Ports 0 3 0x61F renamed heading and bit name 208 Modified Table 138 TX FIFO Overflow Frame Drop Counter Ports 0 3 0x621 0x624 renamed from TX FIFO Number of Frames Removed Ports 3 0 209 Modified Table 139 TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0x629 renamed from TX FIFO Number of Dropped Packets Ports 0 3 and text under the description 210 Modified Table 141 TX FIFO Port Drop Enable 0x63D changed description for bits 3 0 211 Modified Table 142 MDIO Single Command 0x680 changed default changed description and default for bits 9 8 changed default for bits 4 0 212 Modified Table 144 Autoscan PHY Address Enable 0x682 added note to register description 213 Modified Table 146 SPI3 Transmit and Global Configuration 0x700 broke out bits 19 16 7 4 and 3 0 and change
40. 1 4 V point of the output Datasheet 140 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 3 RGMII AC Timing Specification 141 Figure 37 and Table 48 provide RGMII interface timing parameters Figure 37 RGMII Interface Timing TXC at Transmitter TD 3 0 TX CTL n TXC at Receiver RXC at Transmitter RD 3 0 RX_CTL RXC at Receiver B3251 01 Table 48 RGMII Interface Timing Parameters Symbol Parameter Min Typ Max Unit TskewT Data to Clock Output Skew at Transmitter 500 0 500 ps TskewR Data to Clock Input Skew at Receiver 1 2 8 5 Tcyc Clock Cycle Duration 7 2 8 8 8 ns Duty T Duty Cycle for Gigabit 45 50 55 96 Duty G Duty Cycle for 10 100T 40 50 60 96 Tr Tf Rise Fall Time 20 80 75 ns 1 This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1 5 ns is added to the associated clock signal 2 For 10 Mbps and 100 Mbps scales to 400 ns 40 ns and 40 ns 4 ns respectively 3 Duty cycle may be stretched shrunk during speed changes or while transitioning to a received packet s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between Datasheet Document Numbe
41. 200 phon center of receive eye 1 Refer to Section 5 6 2 2 Transmitter Programmable Driver Power Levels on page 104 Datasheet 134 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 42 SerDes Transmit Characteristics Sheet 2 of 2 Normalized Power F Parameter Symbol Drive Min Typ Max Units Comments Settings Receiver common mode voltage range RxCMV 900 1275 1650 mV Receiver termination impedance RxZ 40 51 62 5 Signal detect level RxSigDet 50 125 200 mVp pdiff 1 Refer to Section 5 6 2 2 Transmitter Programmable Driver Power Levels on page 104 Table 43 SerDes Receive Characteristics Normalized Power Symbol Drive Min Typ Max Units Comments Settings Receiver differential voltage requirement at RxDiffV 200 mVp p diff center of receive eye Receiver common mode voltage range RxCMV 900 1275 1650 mV Receiver termination impedance RxZ 40 51 62 5 Signal detect level RxSigDet 50 125 200 mVp pdiff 7 1 1 Undershoot Overshoot Specifications The overshoot figures given in this section represent the maximum voltage that can be applied without affecting the reliability of the device see Table 44 Caution If th
42. 27 Oct 2005 a ntel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 8 4 2 MAC RX Statistics Register Overview The MAC RX Statistics registers contain the MAC receiver statistic counters and are cleared when read The software polls these registers and accumulates values to ensure that the counters do not wrap The 32 bit counters wrap after approximately 30 seconds Table 93 covers the RX statistics for the four MAC ports Port Index is the port number 0 1 2 or 3 Table 93 Statistics Port Index 0x20 0x39 Sheet 1 of 4 Name Description Address Default Counts the bytes received in all legal frames including all bytes from the destination MAC RxOctetsTotalOK address to and including the cyclic redundancy check CRC The initial preamble and Start of Frame Delimiter SFD bytes are not counted Port Index 0x20 R 0x00000000 Counts the bytes received in all bad frames with legal size frames with CRC error alignment errors or code violations including all bytes from the destination MAC address to and including the CRC The initial preamble and Port Index SFD bytes are not counted Frames with illegal 0x21 size do not add to this counter shorts runts longs jabbers and very longs Note This register does not count octets on undersized received packets RxOctetsBAD R 0x00000000 The total number of unicast packets received excluding b
43. 32 bit data bus would support only one IXF1104 MAC To support variable length packets the RMOD 1 0 TMOD 1 0 signals are defined to specify valid bytes in the 32 bit data bus structure Each double word must contain four valid bytes of packet data until the last double word of the packet transfer which is marked with the end of packet REOP TEOP signal This last double word of the transfer contains up to four valid bytes specified by the RMOD 1 0 TMOD 1 0 signals The IXF1104 MAC port selection is performed using in band addressing In the transmit direction the network processor device selects an IXF1104 MAC port by sending the address on the TDATT 1 0 bus marked with the TSX signal active and TENB signal inactive All subsequent TDATT 1 0 bus operations marked with the TSX signal inactive and the TENB active are packet data for the specified port In the receive direction the IXF1104 MAC specifies the selected port by sending the address on the RDAT 1 0 bus marked with the RSX signal active and RVAL signal inactive All subsequent 1 0 bus operations marked with RSX inactive and RVAL active are packet data from the specified port See Table 17 SPI3 MPHY SPHY Interface on page 59 for a complete list of the MPHY mode signals The control signals with the port designator for Port 0 are the only ones used in MPHY mode and they apply to all 4 ports Table 3 SPI3 Interface Signal Descriptions on page 39 provides a comprehensi
44. Auto Negotiation Next Page Transmit Port Index 0x67 added Need one sentence descriptions of register and register default value 211 Modified Table 143 MDIO Single Read and Write Data 0x681 changed MDIO write data to MDIO write data to external device 213 Modified Table 146 SPI3 Transmit and Global Configuration 0x700 changed default value for bits 3 0 from 0 to 1 and changed default value for entire register from 0x0020000F to 0 00200000 215 Modified Table 147 SPI3 Receive Configuration 0x701 changed default value for bits 11 8 from OxF to Ox1 222 Modified Table 154 Optical Module Control Ports 0 3 0x79A changed default value for bits 16 13 from OxF to 1 1 227 Added Figure 57 Package Top and Bottom Views on page 227 and Figure 58 FC PBGA Mechanical Specifications on page 228 229 Replaced Figure 59 Package Marking Example 229 Added Section 9 4 RoHS Compliance on page 229 230 Added CBGA RoHS compliant and FC PBGA ordering information under Table 157 Product Information Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 13 Contents Revision Number 007 Revision Date March 24 2004 Sheet 1 of 5 Page Description All Globally replaced GBIC with Optical Module Interface All Globally edit
45. Clear on Write PHY Autoscan Registers These register hold the current values of the PHY registers only when Autoscan see Section 5 5 8 Autoscan Operation on page 103 is enabled and the IXF1104 MAC is configured in copper mode These registers are not applicable in fiber mode Table 95 PHY Control Port Index 0x60 Sheet 1 of 2 181 Bit Name Description Default 0x00000010 001000 31 16 Reserved Reserved RO 0x0000 PHY Soft Reset Resets the PHY registers to their default value This register bit self clears after the reset is 15 Reset complete RO 0 0 Normal Operation 1 PHY reset 0 Disable loopback mode 14 Loopback RO 0 P 1 Enable loopback mode 0 6 Speed lt 1 gt 0 13 Speed lt 0 gt 00 210 Mbps 13 Speed Selection 01 2100 Mbps RO 0 10 21000 Mbps manual mode not allowed 11 Reserved 1 RO Read Only RR Clear on Read W Write R W Read Write 2 This register is ignored if auto negotiation is enabled Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 95 PHY Control Port Index 0x60 Sheet 2 of 2 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Bit Name Description Type Default 0 Disable auto negotiation process 12 Auto Negotiation 1 Enable auto negotiation
46. Frame Drop Disable This bit is used in conjunction with MAC filter bits RX FIFO Errored This allows the user to select whether the errored 0 Frame Drop Enable packets are to be dropped or not R W 0 Port 0 1 Frame Drop Enable 0 Frame Drop Disable 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 124 RX FIFO Overflow Event 0x5A0 Bit Name Description Default Register Description This register provides a status if a FIFO full situation occurs for example a FIFO overflow The bit position equals the port number This register is cleared on 0x00000000 Read 31 4 Reserved Reserved RO 0x0000000 Port 3 RX FIF fl 3 0 FIFO overflow event did not occur R 0 Event on Port 3 1 FIFO overflow event occurred Port 2 RX FIFO Overflo 2 E 0 FIFO overflow event did not occur R 0 Event on Port 2 1 FIFO overflow event occurred Port 1 RX FIFO Overflo 1 oa 0 FIFO overflow event did not occur R 0 Event on Port 1 1 FIFO overflow event occurred Port 0 RX FIFO Overflo 0 2 0 overflow event did not occur R 0 Event on Port 0 1 FIFO overflow event occurred 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 197 Datasheet Document Number 278757 Revision N
47. Intel IXF1104 to Optical Module Interface Connections 65 Modified first paragraph under Section 5 3 1 2 Clock Rates 87 Modified Section 5 8 2 1 High Speed Serial Interface 100 Modified Figure 27 Microprocessor External and Internal Connections 110 Changed PECL to LVDS under Section 6 1 DC Specifications 113 Modified table note 4 in Table 32 SPI3 Receive Interface Signal Parameters 119 Modified Table 37 SerDes Timing Parameters 125 Modified Table 40 Microprocessor Interface Write Cycle AC Signal Parameters 18 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents Revision Number 006 Revision Date August 21 2003 Sheet 2 of 2 Page Description 140 Modified Table 53 IPG Receive and Transmit Time Register Addr Port Index 0x00 143 Modified Table 60 Short Runts Threshold Register Addr Port Index 0x14 143 Modified Table 61 Discard Unknown Control Frame Register Addr Port Index 0x15 143 Modified Table 62 RX Config Word Register Bit Definition Addr Port Index 0x16 145 Modified Table 64 DiverseConfigWrite Register Addr Port Index 0x18 148 Modified Table 67 RX Statistics Registers Addr Port Index 0x20 0x39 163 Modified Table 82 Microproc
48. Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 56 CBGA Package Side View Diagram 45L4867 552 Solder ball C4 Encapsulant Fillet N Chip 225 0 81 2 0 1 2 47 Max 2 03 Min 6X 0 77 Max 0 69 Min 6X 3 24 Max 2 72 Min 6X 4 16 Max 3 43 Min 0 857 Max 0 779 Min 3 327 Max 2 809 Min 4 237 Max 3 619 Min 07515 gt Seating Plane Note All dimensions are in mm B0555 01 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 226 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Intel 9 3 2 Flip Chip Plastic Ball Grid Array Package Diagram Figure 57 illustrates the FC PBGA top and bottom package views and Figure 58 lists the FC PBGA mechanical specifications Note Please contact your field sales representative for more information on the FC PBGA package Figure 57 FC PBGA Package Top and Bottom Views D TOP VIEW i 250 Nom 02 aaa 0 20 A All around E 25 0 0 2 Terminal 01 Identifier Y B Lid EBEN cec 0 35 C Z bbb 0 25 Substrate gt es
49. TEOP 2 TEOP 3 Input 3 3V LVTTL Transmit End of Packet TEOP indicates the end of a packet and is valid when asserted simultaneously with TENB 32 bit Multi PHY mode TEOP_0 is the bit asserted for all 32 bits 4x8 Single PHY mode Each bit of TEOP 0 3 corresponds to the respective TDAT 3 0 n channel Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 40 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 3 SPIS Interface Signal Descriptions Sheet 3 of 8 Signal Name Ball Designator Type Standard Description MPHY SPHY TMOD 1 0 Transmit Word Modulo 32 bit Multi PHY mode TMOD 1 0 indicates the valid data bytes of TDAT 31 0 During transmission TMOD 1 0 should always be 00 until the last double word is transferred on TDAT 31 0 TMOD 1 0 specifies the valid bytes of TDAT when TEOP is asserted TMOD1 NA 09 3 3V TMODJ 1 0 Valid Bytes TMODO A6 npu LVTTL 00 4 bytes 31 0 01 3 bytes 31 8 10 2 bytes 31 16 11 1 byte 31 24 TENB must be asserted simultaneously for TMOD 1 0 to be valid 4x 8 Single PHY mode MOD 1 0 is not required Transmit Start of Transfer 32 bit Multi PHY mode TSX asserted with TENB 1 indicates that the PHY address is present on TDAT 7 0 The valid values on 3 3 V TDAT 7 0 3 2 1 and 0 When LVTTL TENB 0 TSX
50. UPX DATA18 G10 UPX DATA17 K10 urn UPX DATA16 M10 Input bit mode Uses 31 0 x 3 3 V LVTTL UPX_DATA15 N10 Output 16 bit mode Uses 15 0 UPX_DATA14 J9 UPX DATA13 H9 8 bit mode Uses 7 0 UPX DATA12 L8 UPX DATA11 N7 DATA10 L7 UPX DATA9 L6 UPX DATA8 P5 UPX K5 UPX_DATA6 M5 UPX_DATA5 N5 UPX_DATA4 L4 UPX_DATA3 M3 UPX_DATA2 L3 UPX_DATA1 K3 UPX_DATAO L2 UPX_CS_L R3 Input 3 3 V LVTTL Chip Select Active Low UPX WR L T4 Input 3 3 V LVTTL Write Strobe Active Low UPX RD V6 Input 3 8 V LVTTL Read Strobe Active Low Cycle complete indicator Active Low Open NOTE An external pull up resistor is required for UPX RDY L M1 Drain 3 3 V LVTTL proper operation Output NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output Data bus width select UPX WIDTHT 1 0 specifies the CPU bus width UPX WIDTH1 T5 UPX WIDTH 1 0 Mode UPX WIDTHO U16 Input 3 3 V LVTTL 56 M 01 16 bit 1x 32 bit Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 52 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 53 Table 8 Transmit Pause Control Interface Signal Descriptions Ball NT Signal Name Designator Type Standard Description rd 25 TXPAUSEADD 2 0 is the port selection address 5 P20 Input CMOS for pause frame insertion TXPAUSEADDO N20 TXPAUSEFR T20 Input paN TX
51. back to transmit 126 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 34 Line Side Interface Loopback Path TX SPIS Interface Block Line Side Internal Loopback TX FIFO RAE a MAC Line Side Interface B3230 01 When the IXF1104 MAC is configured in this loopback mode all of the MAC functions and features are available including flow control and pause packet generation To configure the IXF1104 MAC to use the line side loopback mode the Loop RX Data to TX FIFO Line Side Loopback Ports 0 3 0x61F must be configured Each IXF1104 MAC port has a unique bit in this register designated to control the loopback It is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode Note Line side interface loopback packets also appear at the SPI3 interface 5 12 Clocks The IXF1104 MAC system interface has several reference clocks including the following SPI3 data path input clocks RGMII input and output clocks MDIO output clock JTAG input clock C clock LED output clock This section details the unique clock source requirements 5 12 1 System Interface Reference Clocks The following system interface clock is required by the IXF1104 MAC e CLKI25 127
52. both OK CRC and the integral number of octets Default maximum allowed is 1518 bytes untagged and 1522 bytes tagged but the value can be changed by a register Frames bigger than the larger of 2 maxframesize and 50 000 bits are not counted here but they are counted in the VeryLongError counter Port Index 0x30 0x00000000 RxJabberErrors Frames bigger than the maximum allowed with either a bad CRC or a non integral number of octets The default maximum allowed is 1518 bytes untagged and 1522 bytes tagged but the value can be changed by a register Frames bigger than the larger of 2 maxframesize and 50 000 bits are not counted here but they are counted in the VeryLongError counter Port Index 0x31 0x00000000 RxPauseMacContr olReceivedCounter Number of Pause MAC control frames received This statistic register increments on any valid 64 byte pause frame with a valid CRC and also increments on a 64 byte pause frame with an invalid CRC if bit 5 of the RX Packet Filter Control Port Index 0x19 is set to 1 Port Index 0x32 0x00000000 RxUnknownMac ControlFrame Counter Number of MAC control frames received with an op code different from 0001 Pause Port Index 0x33 0x00000000 RxVeryLongErrors Frames bigger than the larger of 2 maxframesize and 50 000 bits Port Index 0x34 R 0x00000000 1 RO Read Only No clear on Read R Read Cle
53. bus F18 E18 E17 F16 SPHY Separate 8 bit data bus for each RDAT 15 8 RDAT 7 0 1 E16 C17 A17 Ethernet port F14 E14 D14 C13 RDAT 7 0 RDAT 7 0 0 C14 Bi4 A15 A14 To achieve maximum bandwidth set RFCLK as follows RFCLK RFCLK A19 MPHY 133 MHz SPHY 125 MHz RPRTY 0 RPRTY 0 E15 Use RPRTY 0 as the RPRTY NC RPRTY 1 G16 signal NC RPRTY 2 E20 SPHY Each port has a dedicated RPRTY n signal NC RPRTY 3 F20 RENB 0 RENB 0 A13 Use RENB 0 as the RENB VDD2 RENB 1 A18 signal VDD2 RENB 2 C19 SPHY Each port has a dedicated RENB n signal VDD2 RENB 3 E24 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 60 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 17 SPI3 MPHY SPHY Interface Sheet 3 of 3 Intel SPI3 Signals Ball Number Comments MPHY SPHY RERR 0 0 16 MPHY Use RERR 0 as the RERR NC RERR 2 D20 SPHY Each port has a dedicated RERR n signal NC RERR 3 H20 RVAL 0 RVAL 0 C15 MPHY Use RVAL 0 as the RVAL NC RVAL 2 E19 SPHY Each port has a dedicated RVAL n signal NC RVAL 3 F22 RSOP 0 RSOP 0 B16 MPHY Use TSOP 0 as the TSOP NC RSOP 1 C18 signal NC RSOP 2 E23 SPHY Each port has a dedicated TSOP n signal NC RSOP 3 J18 REOP 0 REOP 0 C16 MPHY Use TEOP 0 as the NC REOP 2 C23 SPHY Each port has a dedicated
54. lt THrenb comm RDAT 31 0 TPrdat RPRY X Frprty RMOD i gt RSOP X l TPrsop REOP 4 gt RERR X Prerr gt RVAL I Prval gt RSX X gt 137 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 46 SPI3 Receive Interface Signal Parameters Symbol Parameter Min Max Units RFCLK frequency 90 133 MHz RFCLK duty cycle 45 55 Tsrenb RENB setup time to RFCLK 1 8 ns Threnb RENB hold time to RFCLK 0 5 ns TPrdat RFCLK High to RDAT valid 1 5 3 7 ns TPrprty RFCLK High to RPRTY valid 1 5 3 7 ns TPrsop RFCLK High to RSOP valid 1 5 3 7 ns TPreop RFCLK High to REOP valid 1 5 3 7 ns TPrmod RFCLK High to RMOD valid 1 5 3 7 ns TPrerr RFCLK High to RERR valid 1 5 3 7 ns TPrval RFCLK High to RVAL valid 1 5 3 7 ns TPrsx RFCLK High to RSX valid 1 5 3 7 ns NOTES Receive Timing 1 When a setup time is specified between an input and a clock the setup time is the time in nanoseconds from the 1 4 volt point of the input to the 1 4 volt point of the clock 2 When a hold time is specified between an input and a clock the hold time is the time in nanoseconds from the 1 4 volt point of the clock to the 1 4 volt point of the input 3 Output propagation time is
55. to 0x0 permits read only access 3 Set the Device ID field to Ox A and the Register Address 10 8 between the values of 0x1 and 0 7 to access the PHY registers 4 Poll the Read Valid field bit 20 The read data is available when this bit is set to 0x1 Figure 24 shows an 8 bit read access Note The user software ensures the order of the contiguous accesses required to read the High and Low bytes of 16 bit wide PHY registers Figure 24 Random Read Transaction S 5 T R T R S A T R DM T ADDRESS E ADDRESS T ADDRESS D P M LRE M LA M L A N 8 s s sc s s c am B B BK B B K A DUMW WATE K DONT CAFEDt for 1k Note Only one optical module PC access sequence can be run at any given time If a second write is carried out to the Control Ports 0 3 0x79B and Data Ports 0 3 0x79F before a result is returned for the previous write the data for the first write is lost An internal state machine completes the Optical Module Interface register access for the first write It attempts to place the data in the DataRead field and checks to see if the WriteCommand bit is OOh If it is not OOh it discards the data and signals the PC access state machine to begin a new cycle using the data from the second write 5 7 3 3 2 Write Operation Th
56. 0 for port 2 TDAT15 1 H3 Transmit Data Bus TDAT14 TDAT6_1 J3 Carries payload data to the IXF1104 MAC TDAT13 TDAT5_1 J2 egress path TDAT12 TDAT4_1 3 3 V TDAT11 TDAT3_1 H1 pu LVTTL Mode Bits TDAT10 TDAT2_1 G2 TDAT9 TDAT1 1 G1 32 bit Multi PHY 15 8 TDAT8 TDATO 1 F1 4 x 8 Single PHY 7 0 for port 1 TDAT7 0 C6 Transmit Data Bus TDATS TDAT6_0 B5 Carries payload data to the IXF1104 MAC TDAT5 TDAT5 0 C5 egress path TDAT4 TDAT4_0 C4 Input 3 3V TDAT3 0 D1 pu LVTTL Mode Bits TDAT2 TDAT2_0 C3 TDAT1 TDAT1_0 C2 32 bit Multi PHY 7 0 TDATO TDATO 0 B3 4 x 8 Single PHY 7 0 for port 0 Transmit Clock 33V TFCLK is the clock associated with all TFCLK TFCLK D7 Input LVTTL transmit signals Data and control lines are sampled on the rising edge of TFCLK requency operation range 90 z f i 90 183 MHz 39 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 3 Interface Signal Descriptions Sheet 2 of 8 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Signal Name MPHY SPHY Ball Designator Type Standard Description TPRTY 0 TPRTY 0 TPRTY 1 TPRTY 2 TPRTY 3 D5 G3 B9 J6 Input 3 3V LVTTL Transmit Parity TPRTY indicates odd parity for the TDAT bus TPRTY is valid only when a channel asserts either TENB or TSX Odd parity is the default configuration however
57. 0 40 min Seating Plane Lae X KY ddd 0 20 BOTTOM VIEW 02 03 OOOOOOOOOOOOOOOOOOO OOOOOOOOQOOOOOOOOO 5 1 00 0 55 0 75 Y eee 0 25 x c A B 010 Notes Legend All dimensions are in millimeters Ball B5181 02 227 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 58 FC PBGA Mechanical Specifications Mechanical Specifications FC PBGA Mechanical Specifications Di id Package BGA Pitch imensions 1 00 mm Pitch e f T 1 All dimensions are in millimeters 2 Indicated feature does not conform to JEDEC 034 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 228 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 9 3 3 Note Top Label Marking Example Figure 59 shows the IXF1104 MAC non RoHS compliant device marking label In contrast to the Pb Free RoHS compliant package the non RoHS compliant package does not have the 1 symbol Figure 59 Package Marking Example 229 Topside fields not to scale Pin 1 mark 7 H County EM AAAO00AAA Intel Product Number 3 XX Intel Silicon revision number 0 A1
58. 1 VeryLongErrors is never incremented but LongErrors is incremented This is due to a limitation in the counter size which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2 14 1 3 This register is relevant only when configured for copper operation 4 This register is relevant only when configured for fiber operation line side interface is SerDes Datasheet 174 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 93 MAC RX Statistics Port Index 0x20 0x39 Sheet 2 of 4 Intel Name Description Address Type Default The total number of packets received including RxPkts65to127 bad packets that were 65 127 octets in length Port Index R 0x00000000 Octets Incremented for tagged packets with a length of 0x26 65 127 bytes including tag field The total number of packets received including RxPkts128t0255 bad packets that were 128 255 octets in length Port Index R 0x00000000 Octets Incremented for tagged packets with a length of 0x27 128 255 bytes including tag field The total number of packets received including RxPkts256to511 bad packets that were 256 511 octets in length Port Index R 0x00000000 Octets Incremented for tagged packets with a length of 0x28 256 511 bytes including tag field The total number of packets received i
59. 142 through Table 145 provide an overview of the MDIO registers Table 142 MDIO Single Command 0x680 Bit Name Description Default Register Description Gives the CPU the ability to perform single MDIO read and write 0x00010000 accesses to the external PHY for ports that are configured in copper mode 31 21 Reserved Reserved RO 00000000000 Performs the MDIO operation Cleared when done 20 MDIO Command R W 0 0 MDIO ready operation complete 1 Perform operation 19 18 Reserved Reserved RO 00 MDIO Op Code two bits identify operation to be performed 00 Reserved 01 2 Write operation as defined in IEEE 802 3 17 16 OP Code clause 22 2 4 5 R W 01 10 Read operation as defined in IEEE 802 3 clause 22 2 4 5 11 Reserved 15 10 Reserved Reserved RO 000000 Sets bits 1 0 of the external PHY address Bits 4 2 2 8 S UEPIEAGOISBS of the PHY address are fixed at 000 iiid 00 7 5 Reserved Reserved RO 000 Five bit address to one among 32 registers in an 0 4 REG Address addressed PHY device RAN 00000 1 Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 143 MDIO Single Read and Write Data 0x681 Bit Name Description Default Register Description MDIO read and write data 0x00000000 31 16 MDIO Read Data MDIO Read
60. 27 Oct 2005 a intel 5 1 5 1 Note 5 1 5 2 5 1 5 3 Note Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller by the user The RGMII interface supports operation at 10 100 1000 Mbps when a full duplex link is established and supports 10 100 Mbps when a half duplex link is established The GMII interface only supports a 1000 Mbps full duplex link Speed The copper MAC supports 10 Mbps 100 Mbps and 1000 Mbps required speed adjustments clocks etc are supplied by the MAC The operating speed of the MAC is programmable through the IF Mode RGMII Speed Index 0x10 MAC IF Mode The 1104 MAC speed setting must be programmed by the system software to match the speed of the attached PHY for proper IXF1104 MAC operation When the IXF1104 MAC is configured to use the GMII interface the only mode of operation that is supported is 1000 Mbps full duplex If 10 100 Mbps operation is required in either full duplex or half duplex the IXF1104 MAC must be configured to use the RGMII interface Duplex The MAC supports full duplex or half duplex depending on the line side interface that is configured by IF Mode and RGMII Speed Index 0x10 MAC IF Mode The duplex of the MAC is set in the Desired Duplex Port Index 0x02 on page 163 The IXF1104 MAC duplex setting must be programmed by the system software to match the attached PHY d
61. 3 0x60A 0x60D on page 204 DTPA is updated on the rising edge of TFCLK Selected PHY Transmit Packet Available STPA is only meaningful in a 32 bit multi PHY mode STPA is a direct status indication for transmit FIFOs of ports 0 3 When High STPA indicates that the amount of data in the TX FIFO specified by the latest in band address is below the TX FIFO High watermark When the High watermark is crossed STPA transitions Low to indicate the TX FIFO is almost full It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark At this point STPA transitions High to indicate that the programmed STPA NA C11 Output a number of bytes are now available for data transfers NOTE For more information see Table 132 TX FIFO High Watermark Ports 0 3 0x600 0x603 on page 203 and Table 133 TX FIFO Low Watermark Register Ports 0 3 0x60A 0x60D on page 204 STPA provides the status indication for the selected port to avoid FIFO overflows while polling is performed The port reported by STPA is updated on the following rising edge of TFCLK after TSX is sampled as asserted STPA is updated on the rising edge of TFCLK Datasheet 42 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 3 Interface Signal Descriptions Sheet 5 of 8
62. 3 MOD DEF2 DATA I O SDA Input Output 5 MOD DEF 0 is TTL Low level MOD DEF 03 MOD DEFO during normal operation Input to the IXF1104 MAC Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel Table 30 5 7 2 5 7 2 1 5 7 2 2 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Intel IXF1104 MAC to SFP Optical Module Interface Connections Sheet 2 of 2 IXF1104 MAC SFP Signal Signal Names Names Description Notes Transmitter disable logic High TX DISABLE 0 3 TX DISABLE open collector compatible Output from the IXF1104 MAC Transmitter fault logic High open collector compatible Input to the IXF1104 MAC Receiver loss of signal logic High FOE 55 open collector compatible Input to the IXF1104 MAC Functional Descriptions High Speed Serial Interface These signals are responsible for transfer of the actual data at 1 25 Gbps Table 41 DC Specifications on page 134 shows the data is 8B 10B encoded and transmitted differentially The following signals are required to implement the high speed serial interface TX P 03 TX 03 0 3 0 3 Low Speed Status Signaling Interface The following Low Speed signals indicate the state of the line through the Optical Module Interface MOD DEF 0 3 TX FAULT 0 3 RX LOS 0 3
63. 31 0 During transmission RMOD is always 00 except when the last double word is transferred RDAT 31 0 RMODJ 1 0 specifies the valid packet data bytes on RDAT 31 0 when REOP is asserted RMOD 1 0 Valid Bytes of RDAT 00 4 bytes 31 0 01 3 bytes 31 8 10 2 bytes 31 16 11 1 byte 31 24 4 x 8 Single PHY mode RMOD 1 0 is not required RMOD is considered valid only when RVAL is simultaneously asserted RENB must be asserted for RMOD 1 0 to be valid RSX NA E13 Output 3 3 V LVTTL Receive Start of Transfer 32 bit Multi PHY mode RSX indicates when the in band port address is present on the RDAT bus When RSX is High and RVAL 0 the value of RDAT 7 0 is the address of the receive FIFO to be selected Subsequent data transfers on RDAT are from the FIFO specified by this in band address Values of 0 1 2 and 3 select the corresponding port RSX is ignored when RVAL is de asserted 4x8 Single PHY mode RSX is ignored Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 46 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 47 Table 4 SerDes Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TX Y13 TX P 1 AD13 mm EA P2 W16 Output SerDes Transmit Differential Output Positive TX P3 AC18 TX 0 Y14 TX N 1 AD14
64. 32 NA NA NA Object etherStatsDataSource identifier NA NA NA RX Number of Frames Counter Removed etherStatsDropEvents 32 TX Number of Fram s Counter 32 See table note 1 Removed The IXF1104 MAC has two counters for receive and transmit RxOctetsTotalOK that use different RxOctetsBad naming conventions etherStatsOctets 2 Counter 32 for the total Octets OctetsTransmittedOK and Octets Bad OctetsTransmittedBad These counters must be combined to meet the RMON definition for this statistic The IXF1104 MAC has three counters RxUCPKts TxUCPkts forthe etherStatsPkts etherStatsPkts Counter32 RXBCPkts TxBCPkts Counter 32 that be combined to give the RxMCPkts TxMCPkts total packets as defined by the RMON specification Same as RMON etherStatsBroadcastPkts Counter32 RXBCPkts TxBCPkts Counter 32 specification etherStatsMulticastPkts Counter32 RXMCPkts TxMCPkts Counter 32 See table note 2 The IXF1104 MAC has two counters for the alignment and RxAlignErrors CRC errors for the etherStatsCRCAlignErrors Counter32 RxFCSErrors Counter 32 RX side only TxCRCError The IXF1104 MAC has a CRC Error counter for the TX side The IXF1104 MAC RxRuntErrors has two counters etherStatsUndersizedPkts Counter32 RxShortErrors Counter 32 one for Runt errors and one for ShortErrors NOTE The RMON specification requires that this is The total number of events where packets were dropped by the probe due to a la
65. 44 and Table 52 7 6 1 MDC High Speed Operation Timing Figure 41 MDC High Speed Operation Timing 24ns 32 3 X 125 MHz clocks 4 X 125 MHz clocks MDC 4 56 ns 17 85 MHz gt 7 6 2 MDC Low Speed Operation Timing Figure 42 MDC Low Speed Operation Timing 200 ns 200 ns 25 X 125 MHz clocks 25 X 125 MHz clocks q 4 gt MDC gt 400 ns 2 5 MHz 145 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 n ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 6 3 MDIO AC Timing Figure 43 MDIO Write Timing Diagram MAX MDC MDIO Figure 44 MDIO Read Timing Diagram MDC MDIO Table 52 MDIO Timing Parameters Parameter Symbol Min Units Test Conditions 10 ns MDC 17 8 MHz MDIO Setup before MDC t1 10 5 MDC 2 5 MHz 10 ns MDC 17 8 MHz MDIO Hold after MDC t2 10 ns MDC 2 5 MHz 0 42 ns MDC 17 8 MHz MDC to MDIO Output delay t3 0 300 ns MDC 2 5 MHz 1 Typical values are at 25 C and are for design aid only not guaranteed and not subject to production testing
66. 77 When configured for fiber mode the full set of Optical Module interface control and status signals is presented through re use of GMII signals on a per port basis see Table 4 5 Multiplexed Ball Connections on page 58 Fiber mode supports only full duplex Gigabit operation Fiber Auto Negotiation Auto negotiation is performed by using the TX Config Word Port_Index 0x17 RX Config Word Port_Index 0x16 and Diverse Config Write Port_Index 0x18 When autoneg_enable Diverse Config Write Port Index 0x18 is set the IXF1104 MAC performs hardware defined auto negotiation with the TX Config Word Port_Index 0x17 used as an Auto Negotiation Advertisement Port Index 0x64 and the RX Config Word Port_Index 0x16 used as an Auto Negotiation Link Partner Base Page Ability Port Index 0x65 While the MAC supports auto negotiation functions the IXF1104 MAC does not automatically configure the MAC or other device blocks to be consistent with the auto negotiation results This configuration is done by the user and system software Determining If Link Is Established in Auto Negotiation Mode A valid link is established when the AN_complete bit is set and the RX_Sync bit reports that synchronization has occurred Both register bits are located in the RX Config Word Port_Index 0x16 If the link goes down after auto negotiation is completed RX_Sync indicates that a
67. AC19 AB19 19 Y19 W19 V19 U19 T19 R19 P19 N19 M19 L19 K19 J19 H19 G19 F19 E19 019 C19 B19 A19 19 20 AD20 AC20 AB20 20 Y20 w20 V20 U20 T20 R20 P20 N20 M20 120 K20 J20 H20 G20 F20 E20 020 C20 B20 A20 20 21 AD 1 21 21 21 Y21 W21 V21 021 T21 R21 P21 121 M21 121 21 J21 H21 G21 F21 E21 D21 C21 B21 A21 21 22 AD22 AC22 22 22 W22 V22 U22 T22 R22 P22 N22 M22 122 K22 922 H22 622 F22 E22 D22 C22 B22 A22 22 23 AD23 AC23 AB23 23 Y23 W23 V23 U23 T23 R23 P23 N23 M23 123 K23 J23 H23 G23 F23 E23 023 C23 B23 A23 23 24 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 N24 M24 124 K24 J24 H24 G24 F24 E24 D24 C24 B24 A24 24 ADACABAA Y 0 T P ML B A No Pad 1 No Ball A2 A3 A22 A23 A24 B1 B2 B23 B24 C1 C24 ABL AB24 AC1 AC2 AC23 AC24 AD1 AD2 AD22 AD23 AD24 B1458 01 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 3 2 3 2 1 24 Table 1 Ball List Tables Balls Listed in Alphabetic Order by Signal Name Table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name The following
68. Counter Port 1 32 R 209 0x626 TX FIFO Errored Frame Drop Counter Port 2 32 R 209 0x627 TX FIFO Errored Frame Drop Counter Port 3 32 R 209 0x628 Reserved 32 R 0x629 0x62C TX FIFO Occupancy Counter for Port 0 32 R 210 0x62D TX FIFO Occupancy Counter for Port 1 32 R 210 0 62 TX FIFO Occupancy Counter for Port 2 32 R 210 0 62 TX FIFO Occupancy Counter for Port 3 32 R 210 0x630 Reserved 32 R 0x631 63 Table 66 MDIO Registers 5 0x680 0x683 Register Bit Size Mode Ref Page Address MDIO Single Command 0x680 32 R W 211 0x680 MDIO Single Read and Write Data 0x681 32 R W 211 0x681 Autoscan PHY Address Enable 0x682 32 R W 212 0x682 MDIO Control 0x683 32 R W 212 0x683 Table 67 SPI3 Registers 0x700 0x716 Sheet 1 of 2 Register Bit Size Mode Ref Page Address SPI3 Transmit and Global Configuration 0x700 32 R W 213 0x700 SPI3 Receive Configuration 0x701 32 R W 215 0x701 161 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 67 SPI3 Registers 0x700 0x716 Sheet 2 of 2 Register Bit Size Mode Ref Page Address Reserved 32 R 0x702 0x709 Address Parity Error Packet Drop Counter 0x70A 32 R 219 0x70A Reserved 32 R 0x70B 0x716 Table 68 SerDes Registers 0x780 0x798 Register Bit Siz
69. Duplex 12 PHY able to operate in 10 Mbps in full duplex mode 1 R Read Only RR Clear on Read W Write R W Read Write Datasheet 182 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller n Table 96 PHY Status Port Index 0x61 Sheet 2 of 2 Bit Name Description Default 0 PHY not able to operate in 10 Mbps in half 11 10 Mbps duplex mode RO 1 Half Duplex 1 PHY able to operate in 10 Mbps in half duplex mode 0 PHY not able to operate in 10BASE T2 in full 10 100BASE T2 duplex mode not supported RO 0 Full Duplex 1 PHY able to operate in 100BASE T2 in full duplex mode 0 PHY not able to operate in 100BASE T2 in 9 100BASE T2 half duplex mode RO 0 Half Duplex 1 PHY able to operate in 100BASE T2 in half duplex mode 0 No extended status information in Register 15 Extended Status 1 Extended status information in Register 15 RO 1 7 Reserved Reserved RO 0 0 PHY will not accept management frames with 6 MF Preamble preamble suppressed RO 0 Suppression 1 PHY will accept management frames with preamble suppressed 5 Reserved Reserved RO 0 4 Remote Fault 0 2 RO 0 1 Remote fault condition detected 3 Auto Negotiation 0 Mm RO 1 Ability 1 PHY is able to perform auto negotiation 2 Link Status Le RO 0 1 Jabber Detect 7 Jabber condton not detected ro o o exte
70. Pre pending Enable every pac et Port R W 0 Port 2 0 Disabled 1 Enabled Enables pre pending of two bytes at the start of pendi 2 ket Port 1 1 Pre pending Enable every pac et Port R W 0 Port 1 0 Disabled 1 Enabled Enables pre pending of two bytes at the start of pendi 2 ket Port 0 0 Pre pending Enable every pae et Port 0 RW 0 Port 0 0 Disabled 1 Enabled 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 Pre pending should not be enabled in loopback mode Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 200 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 128 RX FIFO Transfer Threshold Port 0 0x5B8 Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 0 in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 RX FIFO transfer threshold for port 0 This must be less than the RX FIFO High water mark User definable control register that sets the threshold where a packet starts transitioning to the SPI3 interface from the RX FIFO before the EOP 11 0 2 is received Packets received the RX FIFO R W OxOBE below this threshold are treated as store and forward NOTE Do not program the RX FIFO transfer threshold below a setting of OXBE 1520bytes 1 RO Rea
71. R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 202 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller n 8 4 7 TX FIFO Register Overview Table 132 through Table 139 provide an overview of the TX FIFO registers which include the TX FIFO High and Low watermark Table 132 TX FIFO High Watermark Ports 0 3 0x600 0x603 Name Description Address Default High watermark for TX FIFO Port 0 The default value of represents 992 8 byte locations This equates to 7936 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x600 R W 0x000003E0 FIFO exceeds the high watermark flow control is automatically initiated on the SPI3 interface to request that the switch fabric stops data transfers to avoid an overflow condition High watermark for TX FIFO Port 1 The default value of represents 992 8 byte locations This equates to 7936 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x601 R W 0x000003E0 FIFO exceeds the high watermark flow control is automatically initiated on the SPI3 interface to request that the switch fabric stops data transfers to avoid an overflow condition High watermark for TX FIFO Port 2 The default value of represents 992 8 byte locations Thi
72. Random Read Operation A random Read requires a dummy Byte Write sequence to load the data word address The dummy write is achieved by first sending the device address word with the Read Write bit cleared to Low which signals a Write operation The optical module acknowledges receipt of the device address word The IXF1104 MAC sends the data word address which is again acknowledged by the optical module The IXF1104 MAC generates another start condition This completes the dummy write and sets the optical module E7 PROM pointers to the desired location 114 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel The IXF1104 MAC initiates a current address read by sending a device address with the Read Write bit set High The optical module acknowledges the device address and serially clocks out the data word The IXF1104 MAC does not respond with a zero but generates a stop condition see Figure 28 Figure 28 Random Read 5 8 5 8 1 115 S Ww S T R T R S A T R T WCFD R DEMCE A T ADDRESS E ADDRESS T ADDRESS D P M LRE M LA M L A N 8 8 2 s sc s s c DA o B Bwb B BK B B K A C DUMVYWATE K DONTCAPELt for 1k LED Interface The IXF1104 MAC uses a Serial interface consisting
73. TEOP n signal NC REOP 3 J19 RMOD 1 0 NC 013 G14 RSX and RMOD 1 0 are applicable RSX NC E13 only in MPHY mode 4 6 Ball State During Reset Table 18 Definition of Output and Bi directional Balls During Hardware Reset Sheet 1 of 2 Interface Ball Name Ball Reset State Comment DTPA 0 3 0x0 STPA 0x0 0x0 RDAT 31 0 0x00000000 RVAL 0 3 0x0 SPI3 RERR_0 3 0x0 RPRTY 0 3 0x0 RMOD 1 0 0 0 RSX 0x0 RSOP_0 3 0x0 REOP 0 3 0 0 NOTE Z High impedance 61 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 18 Definition of Output and Bi directional Balls During Hardware Reset Sheet 2 of 2 Interface Ball Name Ball Reset State Comment JTAG TDO 0 0 MDIO High Z Bi directional MDIO MDC 0 0 UPX DATA 31 0 High Z Bi directional UPX RDY L 0X1 Open drain output requires an external pull up LED_CLK 0x0 LED LED DATA 0x0 LED LATCH 0x0 Fiber mode is the default Copper interfaces TXO Oa disabled Fiber mode is the default TXD 7 0 0 High Z 701 H Bit 4 is driven by the optical module as MOD DEF 0 Fiber mode is the default TXD 7 0 1 High Z 7 0 _ 9 Bit 4 is driven by the optical module as MOD DEF 1 Fiber mode
74. Th d d the Link LED Enabl m e port is transmitting data and the Lin nable Green Blinking 0x502 bit is set NOTE Table 35 assumes the port is enabled in the Port Enable 0x500 and the LEDs are enabled in the LED Control 0x509 If a port is not enabled all the LEDs for that port will be off If the LEDs are not enabled all of the LEDs will be off Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 5 8 6 1 2 Copper LED Behavior Table 36 LED Behavior Copper Mode 5 9 Datasheet Type Status Description Port does not have a remote fault and LED Control 0x509 on page 190 bit is not set Port has an RGMII RXERR condition detected and LED Control 0x509 on page 190 bit is set Link LED Pes Port has a remote fault and LED Fault Disable Amber Blinkirig 0x50B on page 191 is not set LED Control 0x509 on page 190 bit is set and port Green On does not have an RGMII RXERR error or remote fault condition present Off Amber On Off Port is not transmitting and receiving data E LED Control 0x509 on page 190 set Port is Activity LED Green Blinking transmitting and or receiving LED Control 0x509 on page 190 not set Port is receiving data NOTE Table 34 LED_DATA Decodes assumes the port is enabled in the Port Enable 0x500 on page 188
75. Timing sessi 113 27 Acknowledge roii e irre repr re 114 Vi MCI uU Ec 115 29 eramus E 116 30 Mode T TNM ecese AEE A E AEE E EE AE E 118 31 Read Timing Diagram Asynchronous 121 32 Write Timing Diagram Asynchronous 122 33 Interface Loopback Path oie aes dria e ka duran a A EE 126 34 Line Side Interface Loopback 127 35 SPIS Receive Interface Timing 137 36 SPIS Transmit Interface Timing 139 Datasheet 7 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents ntel 37 RGMIl Interface ceeded dne ee 141 38 1000BASE T Transmit Interface 142 39 1000BASE T Receive Interface 143 40 SerDes Timing Diagram 144 41 MDC High Speed Operation 145 42 MDC Low Speed Operation 145 43 Write Timing 146 44 MDIO Read Timing 146 45 Bus TIMING DiaQram cire eee deser dcc dee ev de Lee ee dne 147 46 Write Cycle Diagram pne dea emp re eet
76. Transmit Error TX ER 2 TX ER MAC Synchronous input to PHY causes the transmission of EH error symbols in 1000 Mbps links 3 RXC 0 RXC_1 RX CLK PHY Receive Clock RXC_2 E Continuous reference clock is 125 MHz 100 ppm RXC 3 RXD 7 0 0 Receive Data Bus RXD 7 0 1 Width of the bus varies with the speed and mode of RXD lt 3 0 gt PHY operation In 1000 Mbps mode all 8 bits are driven by RXD 7 0 2 the PHY device RXD 7 0 3 Note MII operation at 10 100 Mbps is not supported RX DV 0 RX DV 1 Receive Data Valid RX DV 2 RX_DV PHY This signal is asserted when valid data is present on ilies the corresponding RXD bus RX_DV_3 RX ER 0 Receive Error RX ER 1 RX ER PHY In 1000 Mbps mode asserted when error symbols or RX_ER_2 carrier extension symbols are received RX_ER_3 Always synchronous to RX_CLK CRS 0 CRS 1 Carrier Sense CRS 2 CRS PHY Asserted when valid activity is detected at the line MA side interface COL 0 Collision COL 1 COL PHY Asserted when a collision is detected and remains COL 2 asserted for the duration of the collision event In full COL 3 duplex mode the PHY should force this signal Low Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 4 Note Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Reduced Gigabit Media Independent Interface RGMII The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Ve
77. W4 wat AA6 10 15 AA19 B4 B8 B12 D2 F8 F12 H2 H6 i VDD2 J12 M2 M6 M9 Input 3 3V Digital 3 3 V supply M12 B13 B17 B21 D23 F13 F17 H19 H23 M VDD3 J13 M13 M16 M19 Input 3 3V Digital 3 3 V supply M23 N13 N16 N19 N23 T13 019 23 W13 VDD4 Wi7 AA23 17 Input 2 5V Digital 2 5 V supply AC21 N2 N6 N9 N12 T12 U2 U6 W8 VDD5 W12 AA2 Input 2 5V Digital 2 5 V supply AC12 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 56 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 4 4 57 Table 15 Ball Usage Summary Ball Usage Summary Type Quantity Inputs 158 Outputs 126 Bi directional 37 Total Signals 321 Power 75 Ground 82 No Connects 74 Total 552 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 4 5 Multiplexed Ball Connections 4 5 1 GMII RGMII SerDes OMI Multiplexed Ball Connections Table 16 lists the balls used for the line side interfaces GMII RGMII SerDes OMI and provides a guide to connect these balls Some of these balls are multiplexed depending on the mode of operation selected for that port Note Do not connect any balls marked as unused NC Table 16 Line Side Interface Multiplexed Balls Sheet 1 of 2
78. bits 3 0 on the leading edge of RXC and register bits 9 Rmo zd 7 4 on the trailing edge of RXC RX DVi he leadi f RXC RX DV RX CTL PHY DV is on the eading edge C RX DV or RXERR is the falling edge of RXC The value of RGMII TX ER and RGMII TX EN are valid at the rising edge of the clock while TX ER is presented on the falling edge of the clock RX_ER coding behaves in the same way see Table 28 Figure 19 and Figure 20 Table 28 TX ER and RX ER Coding Description 97 Condition Description Receiving valid frame DV true RX ER false no errors Logic High on rising edge of RXC Logic High on the falling edge of RXC Receiving valid frame DV true RX ER true with errors Logic High on rising edge of RXC Logic Low on the falling edge of RXC Receiving invalid frame RX DV false RX ER false or no frame Logic Low on rising edge of RXC Logic Low on the falling edge of RXC Transmitting valid frame TX EN true TX ER false no errors Logic High on rising edge of TXC Logic High on the falling edge of TXC Transmitting valid frame TX EN true TX ER true with errors Logic High on rising edge of TXC Logic Low on the falling edge of TXC Transmitting invalid TX EN false TX ER false frame or no frame Logic Low on rising edge of TXC Logic low on the falling edge of TXC NOTE Refer to Figure 19 for TX CTL behavior and Figure 20 for RX CTL behavior Dat
79. collided transmission attempts before a successful frame transmission do not add to this counter Port Index 0x41 0x00000000 TxUCPkts The total number of unicast packets transmitted excluding bad packets Port_Index 0x42 0x00000000 TxMCPkts The total number of multicast packets transmitted excluding bad packets NOTE This count includes pause control packets which are also counted in the TxPauseFrames Counter Thus these types of packets are counted twice Take care when summing register counts for reporting MIB information Port_Index 0x43 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 178 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 179 Table 94 MAC TX Statistics Port Index 0x40 0x58 Sheet 2 of 4 Name Description Address Default TxBCPkts The total number of broadcast packets transmitted excluding bad packets Port Index 0x44 0x00000000 TxPkts64Octets The total number of packets transmitted including bad packets that were 64 octets in length Incremented for tagged packets with a length of 64 bytes including tag field Port Index 0x45 0x00000000 Txpkts65to127Octets The total number of pack
80. collision A frame that is counted by an instance of this object is also counted by the corresponding instance of either the UnicastPkts MulticastPkts or BroadcastPkts and is not counted by the corresponding instance of the SingleCollisionFrames object NOTE NA half duplex only Port Index Ox4F 0x00000000 TxLateCollisions The number of times a collision is detected on a particular interface later than 512 bit times into the transmission of a packet Such frame are terminated and discarded NOTE NA half duplex only Port Index 0x50 0x00000000 TxExcessiveCollisionErrors A count of frames which collides 16 times and is then discarded by the MAC Not effecting xMultipleCollisions NOTE NA half duplex only Port_Index 0x51 0x00000000 TxExcessiveDeferralErrors Number of times frame transmission is postponed more than 2 MaxFrameSize because of another frame already being transmitted on the Ethernet network This causes the MAC to discard the frame NOTE NA half duplex only Port_Index 0x52 0x00000000 TxExcessiveLengthDrop Frame transmissions aborted by the MAC because the frame is longer than maximum frame size These frames are truncated by the MAC when the maximum frame size violation is detected by the MAC Port_Index 0x53 0x00000000 TxUnderrun Internal TX error that causes the MAC to end the transmission before the end of the frame because
81. default pause quanta for each port is held by the FC TX Timer Value Port Index 0x07 The default value of this register is OxOSE after reset is applied Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 23 Valid Decodes for TXPAUSEADD 2 0 TXPAUSEADD 2 0 Operation of TX Pause Control Interface 0 0 Transmits a PAUSE frame on every port with a pause time ZERO Cancels all previous pause commands 0 1 Transmits a PAUSE frame on port 0 with pause time equal to the value programmed in the port 0 FC TX Timer Value Port Index 0x07 XOFF 0 2 Transmits a PAUSE frame on port 1 with pause time equal to the value programmed in the port 1 TX Timer Value Port Index 0x07 0x3 Transmits a PAUSE frame on port 2 with pause time equal to the value programmed in the port 2 FC TX Timer Value Port Index 0x07 0x4 Transmits a PAUSE frame on port 3 with pause time equal to the value programmed in the port 3 TX Timer Value Port Index 0x07 XOFF 0x5 to 0 6 Reserved Do not use these addresses The TX Pause Control interface will not operate under these conditions 0 7 Transmits a PAUSE frame on every port with pause time equal to the value programmed in the TX Timer Value Port Index 0x07 for each port XOFF
82. did not occur R 0 1 FIFO out of sequence event occurred Port 2 10 FOSE2 0 FIFO out of sequence event did not occur R 0 1 2 FIFO out of sequence event occurred Port 1 9 FOSE1 0 FIFO out of sequence event did not occur R 0 1 FIFO out of sequence event occurred Port 0 8 FOSEO 0 FIFO out of sequence event did not occur R 0 1 2 FIFO out of sequence event occurred Port 3 7 FUES 0 FIFO underflow event did not occur R 0 1 FIFO underflow event occurred Port 2 6 FUE2 0 FIFO underflow event did not occur R 0 1 FIFO underflow event occurred Port 1 5 FUE1 0 FIFO underflow event did not occur R 0 1 FIFO underflow event occurred Port 0 4 0 FIFO underflow event did not occur R 0 1 FIFO underflow event occurred Port 3 3 FOES 0 FIFO overflow event did not occur R 0 1 FIFO overflow event occurred 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet 206 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel Table 135 TX FIFO Overflow Underflow Out of Sequence Event 0x61E Sheet 2 of 2 Bit Name Description Default Port 2 2 2 0 FIFO overflow event did not occur R 0 1 FIFO overflow event occurred Port 1 1 FOE1 0 FIFO overflow event did not oc
83. equates to 1664 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x60A R W 0x000000D0 FIFO falls below the low watermark flow control is automatically de asserted on the SPI3 interface to allow further data to be sent by the switch fabric to the IXF1104 MAC Low watermark for TX FIFO Port 1 The default value of 0 000 represents 208 8 byte locations This equates to 1664 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x60B R W 0x000000D0 FIFO falls below the low watermark flow control is automatically de asserted on the SPI3 interface to allow further data to be sent by the switch fabric to the IXF1104 MAC Low watermark for TX FIFO Port 2 The default value of 0 000 represents 208 8 byte locations This equates to 1664 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x60C R W 0x000000D0 FIFO falls below the low watermark flow control is automatically de asserted on the SPI3 interface to allow further data to be sent by the switch fabric to the IXF1104 MAC Low watermark for TX FIFO Port 3 The default value of 0 000 represents 208 8 byte locations This equates to 1664 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0 600 R W 0x000000D0 FIFO falls below the low watermark
84. equates to 3568 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX FIFO reaches this threshold data is forwarded to the MAC core and line side interfaces for onward transmission By setting the threshold to an appropriate value the user can configure the TX FIFO to operate in a cut through mode rather than the default store and forward operation mode 0x615 R W 0x000001BE TX FIFO MAC Threshold Port 2 MAC threshold for TX FIFO Port 2 The default value of OX1BE represents 446 8 byte locations This equates to 3568 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX FIFO reaches this threshold data is forwarded to the MAC core and line side interfaces for onward transmission By setting the threshold to an appropriate value the user can configure the TX FIFO to operate in a cut through mode rather than the default store and forward operation mode 0x616 R W 0x000001BE TX FIFO MAC Threshold Port 3 MAC threshold for TX FIFO Port 3 The default value of OX1BE represents 446 8 byte locations This equates to 3568 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX FIFO reaches this threshold data is forwarded to the MAC core and line side interfaces for onward transmission By setting the threshold to an appropriate
85. even parity can be selected see Table 146 SPIS Transmit and Global Configuration 0x700 on page 213 32 bit Multi PHY mode TPRTY 0 is the parity bit covering all 32 bits 4 8 Single PHY mode TPRTY 0 3 bits correspond to the respective TDAT 3 0 n channels TENB 0 TENB 0 TENB 1 TENB 2 TENB 3 Input 3 3V LVTTL Transmit Write Enable TENB 0 3 asserted causes an attached PHY to process TDAT n TMOD TSOP TEOP and TERR signals 32 bit Multi PHY mode TENB 0 is the enable bit for all 32 bits 4x8 Single PHY mode TENB 0 3 bits correspond to the respective TDAT 3 0 n channels and their associated control and status signals TERR 0 TERR 0 TERR 1 TERR 2 TERR 3 Input 3 3V LVTTL Transmit Error TERR indicates that there is an error in the current packet TERR is valid when simultaneously asserted with TEOP and TENB 32 bit Multi PHY mode TERR 0 is the bit asserted for all 32 bits 4 x 8 Single PHY mode Each bit of TERR 0 3 corresponds to the respective 0 n channel TSOP 0 TSOP 0 TSOP 1 TSOP 2 TSOP 3 C7 C10 J5 Input 3 3 V LVTTL Transmit Start of Packet TSOP indicates the start of a packet and is valid when asserted simultaneously with TENB 32 bit Multi PHY mode 0 is the bit asserted for all 32 bits 4 x 8 Single PHY mode Each bit of TSOP 0 33 corresponds to the respective TDAT 3 0 n channel TEOP 0 TEOP 0 TEOP 1
86. has space for some predefined number of bytes in its transmit FIFO it informs the Network Processor device by asserting one of the Transmit Packet Available TPA signals The Network Processor device writes the in band address followed by packet data to the IXF1104 MAC using an enable signal TENB The network processor device monitors the TPA signals for a High to Low transition which indicates that the transmit FIFO is almost full the number of bytes left in the FIFO is user selectable by setting the FIFO High Watermark Ports 0 3 0x600 0x603 and suspends data transfer to avoid an overflow The Network Processor device can pause the data flow by de asserting the enable signal TENB Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Data Note sheet Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller The IXF1104 MAC provides the following three types of TPA signals Dedicated per port Direct Transmit Packet Available DTPA Selected PHY Transmit Packet Available STPA which is based on the current in band port address in MPHY mode Polled PHY Transmit packet Available PTPA which provides FIFO information on the port selected by the TADR 1 0 signals The following three TPA signals DTPA 0 3 STPA and PTPA provide flow control based on the programmable TX FIFO High and Low watermarks Refer to Table 132 TX FIFO High Watermark Ports 0 3 0x600
87. is the default GMII RGMII TXD 7 0 2 High Z 701 9 4 is driven by the optical module as MOD DEF 2 Fiber mode is the default TXD 7 0 3 High Z 7 0 H Bit 4 is driven by the optical module as MOD DEF 3 Fiber mode is the default TX High 2 Copper interfaces are disabled Fiber mode is the default High Z Copper interfaces are disabled Fiber mode is the default nom TX CTL 0 3 High Z Copper interfaces are disabled TX_P_0 3 0x0 SerDes TX N 0 3 0 0 TX FAULT INT High Z Open drain output requires external pull up RX_LOS_INT High Z Open drain output requires external pull up Optical Module MOD_DEF_INT High Z Open drain output requires external pull up 0 1 2 DATA 0 3 OxF Open drain output requires external pull up NOTE Z High impedance Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 62 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 4 7 Caution 4 7 1 4 7 2 63 Caution Figure 5 Power Supply Sequencing Follow the power up and power down sequences described in this section to ensure correct IXF1104 MAC operation The sequence described in Section 4 7 covers all IXF1104 MAC digital and analog supplies Failure to follow the sequence described in this section might damage the IXF1104 MAC Power Up Sequence Ensure that the 1 8 V analog and digital supplies are app
88. loss of synchronization occurred The IXF1104 MAC restarts auto negotiation and attempts to reestablish a link Once a link is reestablished the AN_complete bit is set and the RX_Sync bit shows that synchronization has occurred To manually restart auto negotiation bit 5 of the Diverse Config Write Port_Index 0x18 AN_enable must be de asserted then re asserted Fiber Forced Mode The MAC fiber operation can be forced to operate at 1000 Mbps full duplex without completion of the auto negotiation function In this mode the MAC RX path must achieve synchronization with the link partner Once achieved the MAC TX path is enabled to allow data transmission This forced mode is limited to operation with a link partner that operates with a full duplex link at 1000 Mbps Determination of Link Establishment in Forced Mode When the IXF1104 MAC is in forced mode operation the RX Config Word Port Index 0x16 bit 20 RX Sync indicates when synchronization occurs and a valid link establishes The RX Sync bit indicates a loss of synchronization when the link is down Copper Mode In copper mode the IXF1104 MAC transmits data on the egress path of the RGMII or GMII interface depending on the port configuration defined by the user The copper MAC receives data on the ingress path of the RGMII or GMII interface depending on the port configuration defined Datasheet Document Number 278757 Revision Number 009 Revision Date
89. low frequency MDC is 2 5 MHz which is derived from the 125 MHz system clock by dividing the frequency by 50 The duty cycle is as follows MDC High duration 25 x 1 125 MHz 25 x 8 ns 200 ns MDC Low duration 25 x 1 125 MHz 25 x 8 ns 200 ns MDC runs continuously after reset 100 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 5 5 Refer to Figure 42 MDC Low Speed Operation Timing on page 145 for the low frequency MDC timing diagram Management Frames The Management Interface serializes the external register access information into the format specified by IEEE 802 3 Section 22 2 4 5 see Figure 21 Figure 21 Management Frame Structure Single Frame Format 5 5 6 9 5 7 101 Preamble Start Op Code PHY Addr REG Addr Turnaround Data 32 Bits 2 Bits 2 Bits 5 Bits 5 Bits 2 Bits 16 Bits First Bit Transmitted Last Bit Transmitted Single MDI Command Operation The Management Data Interface is accessed through the MDIO Single Command 0x680 and the MDIO Single Read and Write Data 0x681 A single management frame is sent by setting Register 0 bit 20 to logic 1 and is automatically cleared when the frame is completed The Write data is first set up in Register 1 bits 15 0 for Write operation Register 0 is initialized with the appropriate con
90. modes See Section 5 1 3 Mixed Mode Operation on page 75 for proper configuration of the IXF1104 MAC in GMII mode GMII Interface Signal Definition Table 26 GMII Interface Signal Definitions on page 95 provides the GMII interface signal definitions For information on 1000BASE T GMII transmit and receive timing diagrams and tables please refer to Table 49 1000BASE T Transmit Signal Parameters on page 142 Figure 38 1000BASE T Transmit Interface Timing on page 142 Figure 39 1000BASE T Receive Interface Timing on page 143 and Table 50 1000BASE T Receive Signal Parameters on page 143 94 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 95 Table 26 GMII Interface Signal Definitions IXF1104 MAC GMII Standard Signal Signal Source Description TXC 0 Transmit Reference Clock TXC 1 GTX CLK IXF1104 125 MHz for Gigabit operation TXC_2 2 MAC MII operation for 10 100 Mbps operation is not TXC 3 supported TXD 7 0 0 Transmit Data Bus TXD 7 0 1 TXD 7 0 IXF1104 Width of this synchronous output bus varies with the TXD 7 0 2 MAC speed mode of operation In 1000 Mbps mode all 8 TXD 7 0 3 bits are used TX EN 0 TX EN 1 IXF1104 Transmit Enable TX EN 2 TX_EN MAC Synchronous input that indicates Valid data is being T ENS driven on the TXD 7 0 data bus TX ER 0 TX 1 IXF1104
91. packet exceeds this value it is considered to be an excessive collision and the frame is dropped Only valid in half duplex Port Index 4 0x06 R W 0x0000000F 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 75 FC TX Timer Value Port Index 0x07 Name Description Address Default The 16 bit pause length inserted in the flow ae ie control pause frame sent to the receiving dos 0x0000005E is station The value is in 512 bit times 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 76 FD FC Address 5 Port Index 0x08 0x09 Datasheet Name Description Address Default The lowest 32 bits of the 48 bit globally Port Index FD FC Address Low assigned multicast pause frame destination 0x08 R W 0xC2000001 address The highest 16 bits 47 32 of the globally assigned multicast pause frame destination Port Index FD FC Address High address The higher 16 bit address is 0x09 RAW 0x00000180 derived from bits 15 0 of this register 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Document Number 278757
92. phenomenon of unlimited amplitude while a feed forward section suppresses high frequency jitter having limited amplitude The static edge position is held at a constant position in the over sampled by a constant adjustment of the sampling phases with the early and late signals Selective Power Down The IXF1104 MAC offers the ability to selectively power down any of the SerDes TX or RX ports that are not being used This is done via TX and RX Power Down 0x787 on page 220 Receiver Jitter Tolerance The SerDes receiver architecture is designed to track frequency mismatch recover phase and is tolerant of low frequency data jitter Figure 23 specifies the SerDes core receiver sinusoidal jitter tracking capabilities Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 23 SerDes Receiver Jitter Tolerance 5 6 2 6 5 6 2 7 Datasheet Sinusoidal Jitter Mask 375 Hz 16 ui 1041 22 5836 kHz 8 5 ui Peak to Peak Amplitude UI 10 1 1 9195 MHz 0 1 ui 100 101 10 103 104 105 108 107 Frequency 0745 02 Note Unit interval Transmit Jitter The SerDes core total transmit jitter including contributions from the intermediate frequency PLL is comprised of the following two components A deterministic component attributed to the SerDes core s architectural characteristics Arandom comp
93. selection of various programmable drive strengths on each SerDes port Refer to Section 5 6 2 2 Transmitter Programmable Driver Power Levels on 0x0000dddd page 104 31 16 Reserved Reserved RO 0x0000 15 12 DRVPWR3 S3 0 Encoded input that sets Power Level for Port 3 R W 1101 11 8 DRVPWR2 3 0 Encoded input that sets Power Level for Port 2 R W 1101 7 4 DRVPWR1 3 0 Encoded input that sets Power Level for Port 1 R W 1101 3 0 DRVPWRO 3 0 Encoded input that sets Power Level for Port 0 R W 1101 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 150 TX and RX Power Down 0x787 Bit Name Description Type Default s Description TX and RX power down bits to allow per port power down of unused 0x00000000 31 14 Reserved Reserved RO 0x0000000 13 10 TPWRDWN S 0 TX power down for Ports 3 0 1 Power down R W 0000 9 4 Reserved Reserved RO 0x00 3 0 RPWRDWN 3 0 RX Power down for Ports 3 0 1 2 Power down R W 0000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 151 RX Signal Detect Level Ports 0 3 0x793 Datasheet Bit Name Description Default Register Description This register shows the status of the Rx input in relation to the level of 0x000
94. serial data line and clocked out by the LED CLK Figure 29 shows the basic timing relationship and relative positioning in the data stream of each bit Figure 29 shows the 36 clocks that are output on the LED pin The data is changed on the falling edge of the clock and is valid for almost the entire clock cycle This ensures that the data is valid during the rising edge of the LED which clocks the data into the M5450 device The actual data shown in Figure 29 consists of a chain of 36 bits 12 of which are valid LED DATA The 36 bit data chain is built up as follows Figure 29 Mode 0 Timing Datasheet 1 2 4 2526272829 30 31 32 33 34 35 LED CLK ruuuuv Tuuuuuuuuuuui LED DATA 1 TT ZZI2SIZ425T26 27I28 29 80 2 LED LATCH 116 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller intel Table 32 Mode 0 Clock Cycle to Data Bit Relationship LED DATA LED CLK Cycle Name LED DATA Description 1 START BIT This bit synchronizes the M5450 device to expect 35 bits of data to follow These bits are used only as fillers in the data stream to extend the 2 3 PAD BITS length from the actual 12 bit LED DATA to the required 18 bit frame length These bits should always be a logic 0 These bits are the actual data transmitted to the M5450 device The 445 LED DATA 1 12 decode for each individu
95. signals Datasheet 44 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 3 5 Interface Signal Descriptions Sheet 7 of 8 Signal Name Ball Designator Type Standard Description MPHY SPHY Receive Error RERR indicates that the current packet is in error RERR is only asserted when REOP is asserted Conditions that can cause RERR to be set include FIFO overflow CRC error code error and runt or giant packets NOTE RERR can only be set for these conditions if bit 0 in the SPI3 RERR 1 G17 33V Receive Configuration 0x701 is RERR 2 D20 Output ceri setto 1 RERR 3 H20 RERR is considered valid only when RVAL is asserted 32 bit Multi PHY mode RERR 0 covers all 32 bits 4x8 Single PHY mode The RERR 0 3 bits correspond to the RDAT 7 0 n channels n 0 1 2 or 3 RERR 0 RERR 0 A16 Receive Data Valid RVAL indicates the validity of the receive data signals RVAL is Low between transfers and assertion of RSX It is also Low when the IXF1104 MAC pauses a transfer due to an empty receive FIFO When a transfer is paused by holding RENB High RVAL holds its value unchanged although no new data is present on RDAT S31 0 until the transfer resumes RVAL 0 RVAL 0 C15 When RVAL is High the RDAT 31 0 RVAL 1 B18 Output 3 3 V RMOD 1 0 RSOP REOP and RERR
96. specifications for this clock 2 5 V CMOS drive 2 5 18 MHz operation selectable by the MDC speed bit in the MDIO Control 0x683 50 50 duty cycle for 2 5 MHz operation 128 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 12 5 5 12 6 5 12 7 129 43 57 duty cycle for 18 MHz operation JTAG Clock The IXF1104 MAC supports JTAG The source of this clock must meet the following specifications e 2 5 V CMOS drive Maximum clock frequency 11 MHz Maximum duty cycle distortion 40 60 Clock The IXF1104 MAC supports a single output clock to support all ten Optical Module interfaces The IXF1104 MAC meets the following specifications for this clock 2 5 V CMOS drive Maximum clock frequency of 100 KHz LED Clock The IXF1104 MAC supports a serial LED data stream and meets the following specifications for this clock 2 5 V CMOS drive Maximum frequency of 720 Hz Maximum duty cycle distortion 50 50 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 6 0 Applications 6 1 Change Port Mode Initialization Sequence Use the change port mode initialization sequence after power up and anytime a port is configured into or switching between fiber or copper mode switching to from RGMII and
97. the MAC did not get the needed data in time for transmission The frames are lost and a fragment or a CRC error is transmitted Port_Index 0x54 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 180 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 94 MAC TX Statistics Port Index 0x40 0x58 Sheet 4 of 4 8 4 4 Note Name Description Address Type Default Number of OK frames with VLAN tag Port_Index TxTagged Type field 0x8100 0x55 0 00000000 Number of frames transmitted with Port Index TxCRCError legal size but with the wrong CRC field 0x56 R 0x00000000 also called FCS field Number of pause MAC frames Port Index TxPauseFrames transmitted 0x57 R 0x00000000 Intentionally generates collisions to curb reception of incoming traffic due to insufficient memory available for additional frames The port must be in half duplex mode with flow control a enabled i R 0x00000000 NOTE To receive a correct statistic a last frame may have to be transmitted after the last flow control collisions send NOTE NA half duplex only 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write
98. to be introduced between back to back transfers for all ports 0 Zero pause cycles 1 Two pause cycles R W 23 22 RX_BURST Port 3 SPHY Mode NA MPHY Mode NA R W 0x0 21 20 RX BURST Port 2 SPHY Mode NA MPHY Mode NA R W 0x0 19 18 RX_BURST Port 1 SPHY Mode NA MPHY Mode NA R W 0x0 17 16 RX_BURST Port 0 SPHY Mode NA MPHY Mode Selects the maximum burst size on the RX path for all ports Ox 64 bytes maximum burst size 10 2128 bytes maximum burst size 11 256 bytes maximum burst size R W 0x0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 216 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 147 SPI3 Receive Configuration 0x701 Continued Sheet 3 of 4 Bit Name Description Default SPHY Mode Indicates the parity sense to check the parity on RDAT bus for port 3 15 Rx parity sense Port 3 0 Odd Parity R W 0x0 12 Even Parity MPHY Mode NA SPHY Mode Indicates the parity sense to check the parity on RDAT bus for port 2 14 parity sense Port2 0 Odd Parity R W 0 0 1 Even Parity MPHY Mode NA SPHY Mode Indicates the parity sense to check the parity on RDAT b
99. value of OXOE6 represents 230 eight byte locations This equates to 1840 bytes of data A unit entry in this register equates to 8 bytes of data When the 0 0 6 amount of data stored in the RX FIFO exceeds the high watermark flow control is automatically initiated within the MAC to avoid an overflow condition 31 12 Reserved Reserved RO 0x00000 The high water mark value RX FIFO High 11 0 9 NOTE Must be greater than the RX FIFO Low R W 0x0E6 Watermark Port 0 Watermark and RX FIFO transfer threshold 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 114 RX FIFO High Watermark Port 1 0x581 Bit Name Description Default Register Description The default value of OXOE6 represents 230 eight byte locations This equates to 1840 bytes of data A unit entry in this register equates to 8 bytes of data When the 0 0 6 amount of data stored the RX FIFO exceeds the high watermark flow control is automatically initiated within the MAC to avoid an overflow condition 31 12 Reserved Reserved RO 0x00000 The high water mark value RX FIFO High 11 0 9 NOTE Must be greater than the FIFO Low R W 0x0E6 Watermark Port 1 Watermark and RX FIFO transfer threshold 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear o
100. 0 Y3 TDAT14 J3 TPRTY 2 B9 TXD2 1 AB9 TDAT15 H3 TPRTY 3 J6 TXD2 2 AB22 TDAT16 E5 TRST L J23 TXD2 3 V16 TDAT17 E6 TSOP 0 C7 TXD3 0 AA3 TDAT18 E7 TSOP 1 E3 TXD3 1 AD9 TDAT19 E8 TSOP 2 C10 TXD3 2 AB23 TDAT20 E9 TSOP 3 J5 TXD3 3 V17 TDAT21 E10 TSX E1 TXD4 0 AB3 Datasheet 27 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 28 Intel Signal Name a Signal Name Signal ma TXD4_1 AA7 UPX DATA5 N5 VDD H10 TXD4 2 AD16 UPX DATA6 M5 VDD H15 TXD4 3 AA14 UPX_DATA7 K5 VDD J11 TXD5 0 AC3 UPX DATA8 P5 VDD J14 TXD5 1 AB8 UPX_DATA9 L6 VDD K4 TXD5 2 AB19 UPX DATA10 L7 VDD K8 TXD5 3 Y15 UPX DATA11 N7 VDD K17 TXD6 0 ABA UPX DATA12 L8 VDD K21 TXD6_1 AD8 UPX_DATA13 H9 VDD L9 TXD6 2 AA20 UPX DATA14 J9 VDD L11 TXD6 3 AA16 UPX DATA15 N10 VDD L14 TXD7 0 Y4 UPX_DATA16 M10 VDD L16 TXD7_1 AC9 UPX DATA17 K10 VDD P9 7 2 AA18 UPX DATA18 G10 VDD P11 TXD7 3 W14 UPX DATA19 H11 VDD P14 TXPAUSE ADDO N20 UPX DATA20 G11 VDD P16 TXPAUSE ADD1 P20 UPX_DATA21 K12 VDD R4 TXPAUSE_ADD2 P21 UPX_DATA22 G12 VDD R8 TXPAUSEFR T20 UPX_DATA23 K13 VDD R17 UPX_ADDO P3 UPX_DATA24 H14 VDD R21 UPX_ADD1 N1 UPX DATA25 K15 VDD T11 UPX_ADD2 P1 UPX_DATA26 N15 VDD T14 UPX_ADD3 R1 UPX_DATA27 M15 VDD U10
101. 0 Selector Field S 4 0 11111 Reserved for future auto negotiation RO 00001 development Unspecified or reserved combinations should not be transmitted Setting this field to a value other than 00001 will most likely cause auto negotiation to fail 1 RO Read Only RR Clear on Read W Write R W Read Write Table 101 Auto Negotiation Expansion Port Index 0x66 Sheet 1 of 2 Bit Name Description Type Default 0x0000000 31 6 Reserved Reserved RO 0 This register bit indicates the status of the auto negotiation variable base page It flags synchronization with the auto negotiation state diagram allowing detection of interrupted links 5 Base Page This register bit is only used if Register bit 16 1 RO 0 alternate Next Page feature is set 0 base page false 1 base page true 4 Parallel Detection 0 Parallel detection fault has not occurred RO 0 Fault 1 Parallel detection fault has occurred 3 Link Partner Next Page 0 Link partner is not Next Page able RO 0 Able 1 Link partner is Next Page able 1 RO Read Only RR Clear on Read W Write R W Read Write Datasheet 186 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller intel Table 101 Auto Negotiation Expansion Port Index 0x66 Continued Sheet 2 of 2 Bit Name Description Type Default 0 Local device is not Next Page able 2
102. 0 TENB 0 B7 MPHY Use TENB 0 as the VDD2 TENB 1 E2 signal VDD2 TENB 2 C9 SPHY Each port has its own dedicated TENB n signal VDD2 TENB 3 J4 59 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 17 SPI3 MPHY SPHY Interface Sheet 2 of 3 SPI3 Signals Ball Number Comments MPHY SPHY TERR 0 TERR 0 A8 MPHY Use TERR 0 as the TERR GND TERR 2 E11 SPHY Each port has its own dedicated TERR n signal GND TERR 3 J8 TSOP 0 TSOP 0 C7 MPHY Use TSOP 0 as the TSOP GND TSOP 1 signal GND TSOP 2 C10 SPHY Each port has a dedicated n signal GND TSOP 3 J5 TEOP 0 TEOP 0 MPHY Use TEOP 0 as the TEOP GND TEOP 1 F3 signal GND TEOP 2 4 SPHY Each port has a dedicated signal GND TEOP 3 H5 TMOD 1 0 GND D9 6 TSX and TMOD 1 0 are only applicable TADR 1 0 TADR 1 0 A12 A11 Used to address port for PTPA signal PTPA can be used in MPHY and SPHY PTPA PTPA B11 m des is available on a per port basis in PHP 03 D3 L A9 J7 both MPHY and SPHY modes STPA NC C11 STPA is only applicable in MPHY mode F24 G24 G23 G22 RDAT 31 24 RDAT 7 0 G21 G20 619 G18 E21 E22 D22 C22 MPHY Consists of a single 32 bit data RDAT 23 16 RDAT 7 0 2 C21 C20 B22 B20
103. 00000 the signal being received from the line This register is meant for debug and test use 31 4 Reserved Reserved RO 0x0000000 Signal Detect for Ports 0 3 3 0 SIGDET 3 0 0 2 Noise RO 0x0 1 2 Signal 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 220 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 152 Clock and Interface Mode Change Enable Ports 0 3 0x794 Intel Bit Name Description Type Default Register Description This register is used when a change to the operational mode or speed of the IXF1104 MAC is required This register ensures that when a change is made that the 0x00000000 internal clocking of the IXF1104 MAC is managed correctly and no unexpected effects of the operational or speed change are observable on the line interfaces 31 4 Reserved Reserved RO 0x0000000 Enables internal clock generator for Port 3 to sample the MAC IF Mode and RGMII Speed Port Index 0x10 and the Interface Mode 0x501 Clock and Interface 0 Setto zero when changes are being made to R the MAC IF Mode and RGMII Speed mn Port Index 0x10 and the Interface Mode 0x501 1 Setto 1 for the configuration changes to take effect Enables internal clock gener
104. 0000000 RxSequenceErrors Records the number of sequencing errors that occur in fiber mode Port Index 0x38 R 0x00000000 RxSymbolErrors Records the number of symbol errors encountered by the PHY Port Index 0x39 R 0x00000000 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 When sending in large frames the counters can only handle certain limits The behavior of the LongErrors and VeryLongErrors counters is as follows VeryLongErrors counts frames that are 2 maxframesize dependent upon where maxframesize is set If maxframesize sets greater than half of the available count in RxOctetsBad 2 14 1 VeryLongErrors is never incremented but LongErrors is incremented This is due to a limitation in the counter size which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2 14 1 3 This register is relevant only when configured for copper operation 4 This register is relevant only when configured for fiber operation line side interface is SerDes Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 8 4 3 MAC TX Statistics Register Overview Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller The MAC TX Statistics registers contain all the MAC transmit statistic counters and are cleared wh
105. 01 Name Description Address Default Source MAC address bit 31 0 This address is inserted in the source address pu Address field when transmitting pause frames and is also R W 0x0000000 ow 0x00 used to compare against unicast pause frames at the receiving side Source MAC address bit 47 32 This address is inserted in the source address Station Address field when transmitting pause frames and is also Port Index High used to compare against unicast pause frames 0x01 FUN 0 00000000 atthe receiving side Bits 15 0 of this register are assigned to bits 47 32 of the station address 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 71 Desired Duplex Port Index 0x02 Bit Name Description Default Register Description Chooses between half duplex and full duplex operation in RGMII 100 Mbps or 10 Mbps mode only 0 00000001 This register must be set to the default value of 1 and must not be changed when operating in RGMII 1000 Mbps GMII or fiber mode 31 1 Reserved Reserved R 0x00000000 0 Half duplex 1 Full duplex 0 Duplex Select NOTE Half duplex operation applies only to R W 1 p 10 100 Mbps speed on copper media in RGMII mode only Gigabit speed on either media requires full duplex 1 RO Read Only No clear o
106. 0x603 on page 203 and Table 133 TX FIFO Low Watermark Register Ports 0 3 0x60A 0x60D on page 204 for more information DTPA 0 3 A direct status indication for the TX FIFOs of ports 0 3 When DTPA is High it indicates the amount of data in the TX FIFO is below the TX FIFO High watermark When the High watermark is crossed DTPA transitions Low to indicate the TX FIFO is almost full It stays low until the amount data in the TX FIFO goes back below the TX FIFO Low watermark At this point DTPA transitions High to indicate the programmed number of bytes are now available for data transfers DTPA 0 3 is updated on the rising edge of the TFCLK STPA STPA provides TX FIFO status for the currently selected port in MPHY mode When High STPA indicates that the amount of data in the TX FIFO for the port selected specified by the latest in band address is below the TX FIFO High watermark When the High watermark is crossed STPA transitions Low to indicate the TX FIFO is almost full It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark At this point STPA transitions High to indicate the programmed number of bytes are now available for data transfers The port reported by STPA is updated on the rising edge of TFCLK after TSX is sampled as asserted STPA is updated on the rising edge of TFCLK STPA is only used when the IXF1104 MAC is configured for MPHY mode of operation PTPA PTPA provi
107. 1 Y8 TX EN 1 AA22 RX ER 2 AC12 VDD5 Y9 RXDO 1 AA23 VDD4 AC13 VDD4 Y10 RXD7 1 AA24 RXC 2 AC14 GND Y11 RXD1 1 AB1 No Ball AC15 GND Y12 RX ER 1 AB2 TX EN 0 AC16 CRS 3 Y13 TX P 0 AB3 TXD4_0 AC17 VDD4 Y14 TX 0 ABA TXD6 0 AC18 TX P 33 Y15 TXD5 3 AB5 RXD6_0 AC19 GND Y16 TX 2 AB6 COL 0 AC20 TXC 2 Y17 RXDO 3 AB7 TXD1 1 21 VDD4 Y18 RXD1 3 AB8 TXD5 1 AC22 TX EN 2 Y19 RXD2_3 ABQ TXD2_1 AC23 No Ball Y20 RXDO 2 AB10 COL 1 AC24 No Ball Y21 RXD1 2 AB11 RX DV 1 AD1 No Ball Y22 RXD2 2 AB12 GND AD2 No Ball Y23 RXD3 2 AB13 TX ER 3 AD3 No Ball Y24 DV 2 AB14 TXC 3 AD4 NC AA1 TXC 0 AB15 CRS 2 AD5 NC Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Toon Signal Name ADE TX ER 1 AD7 TXC 1 AD8 TXD6_1 ADI TXD3 1 AD10 RXD4_1 AD11 RXC 1 AD12 SYS RST L AD13 TX P AD14 TON H 015 COL 21 AD16 TXD4_21 AD17 TX ER 2 AD18 TX 3 AD19 CLK125 AD20 AVDD2P5_1 AD21 GNG AD22 No Ball AD23 No Ball AD24 No Ball Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 36 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel
108. 12 eene nennen nnns nnne 168 FC Back Pressure Length Port Index 0x13 168 Short Runts Threshold Port Index 0x14 169 Discard Unknown Control Frame Port Index 0x15 169 RX Config Word Port Index 16 169 TX Config Word Port Index 0x17 170 Diverse Config Write Port Index 0 18 171 RX Packet Filter Control Port Index 0 19 172 Port Multicast Address Port Index 0 1 173 MAC RX Statistics Port Index 0 20 0 39 174 MAC TX Statistics Port Index 0 40 0x58 178 PHY Control Port Index 60 181 PHY Status Port Index 0 61 182 PHY Identification 1 Port Index 0 62 2 183 PHY Identification 2 Port Index 0 63 184 Auto Negotiation Advertisement Port Index 0x64 184 Auto Negotiation Link Partner Base Page Ability Port Index 0 65 185 Auto Negotiation Expansion Port Index 0 66 186 Auto Negotiation Next Page Transmit Port Index 0 67 187 Port Enable 0X500 5 tor ent ise de e def 188 Interface Mode 0x501 188 Link LED Enable 0x502 5
109. 12 Reserved Reserved RO 0x00000 The high water mark value RX FIFO High 9 NOTE Must be greater than the FIFO Low R W Ox0E6 Watermark Port 3 Watermark and RX FIFO transfer threshold 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 11 0 Table 117 RX FIFO Low Watermark Port 0 0x58A Bit Name Description Type Default Register Description The default value of 0x072 represents 114 eight byte locations This equates to 912 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO falls below the Low Watermark flow control is 0x072 automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 31 12 Reserved Reserved RO 0x00000 The High Watermark value 11 0 2 0 NOTE Should never be greater or equal to the R W 0x072 High Watermark 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 118 RX FIFO Low Watermark Port 1 0x58B Bit Name Description Type Default Register Description The default value of 0x072 represents 114 eight byte locations This equates to 912 bytes of data A unit entry in this register equates to 8 bytes of data When the
110. 13 RDAT 4 D23 VDD3 C14 RDAT 3 D24 NC C15 RVAL 0 E1 TSX C16 REOP 0 E2 TENB 1 C17 RDAT 9 E3 TSOP 1 2 C18 RSOP 1 E4 TEOP 22 C19 RENB 2 5 TDAT16 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Te Signal Name Vues Signal Name ie Signal Name E6 TDAT17 F20 RPRTY 3 H10 VDD E7 TDAT18 F21 VDD H11 UPX DATA19 E8 TDAT19 F22 3 H12 GND E9 TDAT20 F23 GND H13 GND E10 TDAT21 F24 RDAT 31 H14 UPX DATA24 E11 TERR 2 G1 92 H15 VDD E12 NC G2 TDAT10 H16 UPX DATA29 E13 RSX G3 TPRTY 12 H17 GND E14 RDAT 62 G4 TDAT24 H18 NC E15 RPRTY 0 G5 TDAT25 H19 VDD3 E16 RDAT 112 G6 TDAT26 H20 RERR 3 E17 RDAT 13 G7 TDAT27 H21 GND E18 RDAT 14 G8 TDAT28 H22 TMS E19 RVAL 2 G9 TDAT292 H23 VDD3 E20 RPRTY 2 G10 UPX DATA18 H24 TDO E21 RDAT 23 G11 UPX_DATA20 J1 TDAT12 E22 RDAT 22 G12 UPX DATA22 J2 TDAT13 E23 RSOP 2 G13 RMOD1 J3 TDAT14 E24 RENB 3 G14 RMODO J4 TENB 3 F1 TDAT8 G15 NC J5 TSOP 3 F2 GND G16 RPRTY 1 J6 TPRTY 3 F3 TEOP 1 G17 RERR 1 J7 DTPA 3 F4 VDD G18 RDAT 24 J8 TERR 3 F5 TDAT30 G19 RDAT 25 J9 UPX DATA14 F6 GND G20 RDAT 26 J10 GND F7 TDAT31 G21 RDAT 27 J11 VDD F8 VDD2 G22 RDAT 28 J12 VDD2 F9 TDAT22 G23 RDAT 29 J13 VDD3 F10 GND G24 30
111. 16 RDAT 25 G19 RX DV 3 V18 RXD5 0 Y5 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Signal Name Tom Signal Name es oom Signal Name Te m RXD5 1 11 222 F9 TX EN 0 AB2 RXD5 2 V20 TDAT23 C8 TX EN 1 Y8 RXD5 3 T17 TDAT24 G4 TX EN 2 AC22 RXD6 0 AB5 TDAT25 G5 TX EN 3 V12 RXD6 1 AA11 TDAT26 G6 TX ER 0 w1 RXD6_2 V19 TDAT27 G7 TX ER 1 AD6 RXD6_3 T18 TDAT28 G8 TX ER 2 AD17 RXD7 0 AC5 TDAT29 G9 TX ER 3 AB13 RXD7 1 Y10 TDAT30 F5 TX FAULT INT P23 7 2 20 TDAT31 F7 TX 03 Y14 RXD7 3 T19 TDI J24 TX 13 AD14 STPA C11 TDO H24 TX 23 Y16 SYS RST L AD12 TENB 0 B7 TX N 3 AD18 TADRO 11 _1 2 TX P 0 Y13 TADR1 A12 TENB 2 C9 TX P 13 AD13 TCLK J22 TENB 3 J4 TX P 23 W16 TDATO B3 TEOP 0 A7 TX P 3 AC18 C2 TEOP 1 F3 TXC 0 AA TDAT2 C3 TEOP 2 E4 TXC 1 AD7 TDAT3 D1 TEOP 3 H5 TXC 2 AC20 TDAT4 C4 TERR 0 A8 TXC 3 AB14 TDAT5 C5 TERR 1 K1 TXDO 0 Y1 B5 TERR 22 E11 TXDO 1 AC7 TDAT7 C6 TERR 3 J8 TXDO 2 AB20 TDAT8 F1 TFCLK D7 TXDO 3 V14 TDAT9 G1 TMODO A6 TXD1 0 Y2 TDAT10 G2 TMOD1 D9 TXD1_1 AB7 TDAT112 H1 TMS H22 TXD1 2 21 TDAT122 J1 0 05 TXD1 3 V15 TDAT13 J2 TPRTY 1 G3 TXD2
112. 18 4 379 5 To eliminate the memory management problems for a network processor or switch fabric the two remaining bytes are dealt with by the addition of two bytes to the start of a packet This results in a standard 1518 byte Ethernet packet received by the IXF1104 MAC being forwarded to the higher layer device as a 380 long word packet The upper layer device is responsible for stripping the additional two bytes This feature was added to the IXF1104 MAC to assist in the design of higher layer memory management The addition of the two extra bytes is not the default operation of the IXF1104 MAC and must be enabled by the user The default operation of the IXF1104 MAC SPI3 receive interface forwards data exactly as it is received by the IXF1104 MAC line interface Gigabit Media Independent Interface GMII The IXF1104 MAC supports a subset of the GMII interface standard as defined in IEEE 802 3 2000 Edition for 1 Gbps operation only This subset is limited to operation at 1000 Mbps full duplex The GMII Interface operates as a source synchronous interface only and does not accept a TXC clock provided by a PHY device when operating at 10 100 Mbps speeds The RGMII interface must be used for applications that require 10 100 1000 Mbps operation The IXF1104 MAC does NOT support 10 100 Mbps copper PHY devices that are implemented using the MII Interface MII operation is not supported by the IXF1104 MAC The user can select GMII RGMII o
113. 2 DATA 0 L24 Input UNT DATA 1 M24 25V NOTE An external pull up resistor is PC DATA 2 N24 Drain CMOS required for proper operation C DATA 3 P24 Output NOTE Dual mode I O 7 Normal operation Input open drain output Boundary Scan Mode Standard CMOS output Table 10 MDIO Interface Signal Descriptions Signal Name Pan Type Standard Description Designator MDIO is the management data input and output Input 25V MDI V21 9 Output CMOS NOTE An external pull up resistor is required for proper operation MDC W24 Output End is the management clock to external devices Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 54 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 11 LED Interface Signal Descriptions Ball Signal Name Designator Type Standard Description 25V LED CLK K24 Output CMOS LED CLK is the clock output for the LED block LED DATA M22 Output LED is the data output for the LED block LED LATCH L22 Output 2 LED LATCH is the latch enable for the LED block Table 12 JTAG Interface Signal Descriptions Ball s Signal Name Designator Type Standard Description TCLK J22 Input 33 JTAG Test Clock LVTTL TMS H22 Input 3 3 V Test Mode Select LVTTL 3 3 V TDI J24 Input LVTTL Test Data Input TDO H24 Output Test Data Output LVTTL
114. 3 Internal Loopback TX FIFO SPI3 Interface Block Line Side Interface px RX FIFO B3229 01 There is a restriction when using this loopback mode At least one clock cycle is required between a TEOP assertion and a TSOP assertion This is required when the pre pend feature of the receive FIFO is enabled to allow the addition of the extra two bytes to the data sent on the transmit interface Where the pre pend feature has not been enabled data can be sent back to back on the transmit SPI3 interface with TSOP following TEOP on the next cycle To configure the IXF1104 MAC to use the SPI3 loopback mode the RX FIFO SPI3 Loopback Enable for Ports 0 3 0x5B2 must be configured Each IXF1104 MAC port has a unique bit in this register designated to control loopback It is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode Line Side Interface Loopback To provide a diagnostic loopback feature on the line side interfaces the IXF1104 MAC can be configured to loop back any data received by the IXF1104 MAC through one of the line interfaces back to the corresponding transmit line interface This is done by using the data path shown in Figure 34 The line side interface can be either SerDes RGMII or GMII Please note that it is not possible to loop one line side interface back to a different one for example Rx SerDes looped
115. 3 TX port 3 R W 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 214 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 146 SPI3 Transmit and Global Configuration 0x700 Sheet 3 of 3 Intel Bit Name Description Type Default SPHY Mode 0 Disables the selected SPI3 TX port 2 1 Enables the selected TX port 2 2 T le Port 2 R 1 port enable Port MPHY Mode AN 0 Disables the selected SPI3 TX port 2 1 Enables the selected TX port 2 SPHY Mode 0 Disables the selected SPI3 TX port 1 1 Enables the selected TX port 1 1 T le Port 1 R 1 x port enable Port MPHY Mode AN 0 Disables the selected SPI3 TX port 1 1 Enables the selected SPI3 TX port 1 SPHY Mode 0 Disables the selected TX port 0 1 Enables the selected TX port 0 T le P R 1 0 port enable Port 0 MPHY Mode AN 0 Disables the selected SPI3 TX port 0 1 Enables the selected TX port 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 147 SPI3 Receive Configuration 0x701 Sheet 1 of 4 Bit Name Description Default Register Descript
116. 30 shows that the LED LATCH signal is active High during the Low period on the 35th LED cycle This avoids any possibility of trying to latch data as it is shifting through the register When this operation mode is implemented on a board with a shift register chain containing three 74 599 devices the LED DATA bit 1 is output on Shift register bit 1 and so on up the chain Only Shift register bits 31 and 32 do not contain valid data The actual data shown in Figure 30 consists of a 36 bit chain of which 12 bits are valid LED DATA The 36 bit data chain is built up as shown in Figure 30 117 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Note The LED DATA signal is now inverted from the state in Mode 0 Figure 30 Mode 1 Timing 12 3 4 2526 27 28 29 30 31 32 33 34 35 LED CLK LED DATA L11 U2IZSIZA P5 P6 27 28 20 80 LED LATCH d Table 33 Mode 1 Clock Cycle to Data Bit Relationship LED CLK Cycle LED DATA Name LED DATA Description This bit has no meaning in Mode 1 operation and is shifted out of 1 START BIT the 16 stage shift register chain before the LED LATCH signal is asserted These bits have no meaning in Mode 1 operation and are shifted 2 8 PAD BITS out of the 16 stage shift register chain before the LED LATCH signal is as
117. 4 Interface Signals modified SPI3 interface signals and added MPHY and SPHY categories modified signal names 39 Broke old Table 1 IXF1104 Signal Descriptions into the following Table 3 SPI3 Interface Signal Descriptions on page 39 through Table 14 Power Supply Signal Descriptions on page 56 39 Modified Table 3 SPI3 Interface Signal Descriptions on page 39 edited description for DTPA added text to TFCLK description added text to RFCLK description 50 Modified Table 6 RGMII Interface Signal Descriptions Added Ball Designators added notes under descriptions 51 Modified Table 7 CPU Interface Signal Descriptions UPX DATA 16 deleted J10 added M10 53 Modified Table 9 Optical Module Interface Signal Descriptions added Ball Designators 54 Modified Table 10 MDIO Interface Signal Descriptions moved note from MDC to 56 Modified Table 14 Power Supply Signal Descriptions added Ball Designators A4 A21 and AD21 to GND added AVDD1P8 1 AVDD1P8 2 AVDD2P5 1 and AVDD2P5 21 14 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents Revision Number 007 Revision Date March 24 2004 Sheet 2 of 5 Page Description 39 Modified Section 4 3 Signal Description Tables changed heading from Signal Naming Conventions added new headings Section 4 1 1 Signal Name Convent
118. 56 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 59 MAC Control Registers Port Index Offset Sheet 2 of 2 Intel Register Bit Size Mode Ref Page Offset Max Frame Size Addr Port Index OxOF 32 R W 166 Ox0F MAC IF Mode and RGMII Speed Port Index 0x10 32 R W 167 0x10 Flush TX Port_Index 0x11 32 R W 167 0x11 FC Enable Port_Index 0x12 32 R W 168 0x12 FC Back Pressure Length Port_Index 0x13 32 R W 168 0x13 Short Runts Threshold Port Index 0x14 32 R W 169 0x14 hem Unknown Control Frame Port Index 32 R W 169 0x15 RX Config Word Port Index 0x16 32 RO 169 0x16 TX Config Word Port_Index 0x17 32 R W 170 0x17 Diverse Config Write Port Index 0x18 32 R W 171 0x18 RX Packet Filter Control Port Index 0x19 32 R W 172 0 19 PorMulicastAddressLow RW 173 a Table 60 RX Statistics Registers Port Index gt Offset Sheet 1 of 2 Register Bit Size Mode Ref Page Offset RxOctetsTotalOK 32 174 0x20 RxOctetsBAD 32 R 174 0x21 RxUCPckts 32 R 174 0x22 RxMCPkts 32 R 174 0x23 RxBCPkts 32 R 174 0x24 RxPkts64Octets 32 R 174 0x25 RxPkts65to1270Octets 32 R 174 0x26 RxPkt
119. 601 TX FIFO High Watermark Port 2 32 R W 203 0x602 TX FIFO High Watermark Port 3 32 R W 203 0x603 Reserved 32 RO 0x604 0x609 TX FIFO Low Watermark Port 0 32 R W 204 0x60A TX FIFO Low Watermark Port 1 32 R W 204 0x60B TX FIFO Low Watermark Port 2 32 R W 204 0 60 TX FIFO Low Watermark Port 3 32 R W 204 0x60D 160 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller n Table 65 TX FIFO Registers 0x600 0x63E Sheet 2 of 2 Register Bit Size Mode Ref Page Address Reserved 32 RO Ox60E 0x613 TX FIFO MAC Threshold Port 0 32 R W 205 0x614 TX FIFO MAC Threshold Port 1 32 R W 205 0x615 TX FIFO MAC Threshold Port 2 32 R W 205 0x616 TX FIFO MAC Threshold Port 3 32 R W 205 0x617 Reserved RO 0x618 0x61D TX FIFO Overflow Underflow Event Out of Sequence 32 R 206 0 61 Loop Data to TX FIFO 32 R W 207 0x61F TX FIFO Port Reset 32 R W 207 0x620 TX FIFO Overflow Frame Drop Counter Port 0 32 R 208 0x621 TX FIFO Overflow Frame Drop Counter Port 1 32 R 208 0x622 TX FIFO Overflow Frame Drop Counter Port 2 32 R 208 0x623 TX FIFO Overflow Frame Drop Counter Port 3 32 R 208 0x624 TX FIFO Errored Frame Drop Counter Port 0 32 R 209 0x625 TX FIFO Errored Frame Drop
120. 70 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel Figure 7 Packet Buffering FIFO SPI3 Interface High Watermark TX FIFO Data Flow TX Side MAC MAC Transfer Threshold Low Watermark High Watermark Data Flow RX FIFO Low Watermark RX FIFO High TXPAUSEFR External 802 3 Flow Strobe Control 802 3x Pause Frame Generation B3231 01 5 1 2 1 1 Pause Frame Format PAUSE frames are MAC control frames that are padded to the minimum size 64 bytes Figure 8 and Figure 9 illustrate the frame format and contents Figure 8 Ethernet Frame Format Number of bytes 46 1500 4 7 1 6 6 2 S Type i Ethernet Frame ff Note 64 Byte Minimum 1518 bytes Maximum B2277 02 71 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 9 PAUSE Frame Format Number of bytes 7 1 6 a Preamble Pause Pad Length with Os Ee i Note In the Intel IXF1104 architecture the TX block of the MAC sets this as the pause multicast address The RX interface of the MAC will process this as the pause multicast or the MAC address B3218 02 An IEEE 802 3 MAC PAUSE frame is identified by detecting all of the following OpCode o
121. 8 L2 UPX DATAO M16 VDD3 P6 NC L3 UPX DATA2 M17 GND P7 NC L4 UPX DATA4 M18 NC P8 NC L5 GND M19 VDD3 P9 VDD L6 UPX DATAS M20 NC P10 GND L7 UPX DATA10 M21 GND P11 VDD L8 UPX_DATA12 M22 LED_DATA P12 GND L9 VDD M23 VDD3 P13 GND L10 GND M24 DATA 13 14 VDD L11 VDD N1 UPX_ADD1 P15 GND L12 GND N2 VDD5 P16 VDD L13 GND N3 NC P17 NC Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller T Signal Name eae Signal Name mi Signal Name P18 NC T8 NC U22 1 P19 RX LOS INT T9 NC U23 VDD4 P20 TXPAUSE_ADD1 T10 GND U24 RX P 3 P21 TXPAUSE ADD2 T11 VDD v1 UPX_ADD6 P22 RX P 0 T12 VDD5 v2 UPX_ADD7 P23 TX FAULT INT T13 VDD4 V3 UPX_ADD8 P24 2 DATA 33 14 VDD V4 RXC 0 R1 UPX ADD3 T15 GND V5 RX DV 0 R2 GND T16 RXD4 3 V6 UPX RD L R3 UPX CS T17 RXD5 3 V7 RXD1_0 R4 VDD T18 RXD6_3 V8 RXDO 0 R5 NC T19 RXD7 V9 NC R6 GND T20 TXPAUSEFR V10 NC R7 GND T21 NC v11 NC R8 VDD T22 NC V12 TX EN 3 R9 GND T23 AVDD1P8_2 V13 NC R10 NC T24 RX P 23 V14 TXDO 3 R11 GND U1 UPX ADD5 V15 TXD1 3 R12 NC U2 VDD5 V16 TXD2 3 R13 NC U3 UPX ADD9 V17 TXD3 3 R14 GND U4 GND V18 RX DV 3 R15 NC U5 NC V19 RXD6 2 R16 GND U6 VDD5 20 RXD5 2 R17 VDD U7 NC V21 R18 AVDD2P5 2 U8 GND v22 RX P 1 R19 GND U9 N
122. AB14 data bus in either RGMII or GMII mode TD3 0 AA3 TD2 0 0 Y2 TDO 0 Y1 TD3_1 AD9 TD2 1 AB9 TD1 1 AB7 Transmit Data 1 7 Bits 3 0 are clocked on the rising edge of TXC i Output 2 5 V Bits 7 4 are clocked on the falling edge of TXC P CMOS AB23 NOTE Shares data signals TXD 3 0 _n with the IBS E Apes GMII interface TD1 2 AB21 TDO 2 AB20 3 V17 3 V16 TD1 3 V15 TDO 3 V14 Transmit Control TX is TX_EN on the rising edge of TXC and a DTI EU ADA logical derivative of TX_EN and TX_ER on the POTEZI Output falling edge of TXC TX 2 AC22 p CMOS 9 9 TX CTL 3 V12 NOTE TX CTL multiplexes with TX EN nonthe GMII interface Receiver Reference Clock Operates at RXC 0 V4 125 MHz for 1 Gigabit RXC_1 AD11 Input Gane 25 MHz for 100 Mbps RXC_2 AA24 RXC 3 V23 2 5 MHz for 10 Mbps NOTE Shares the same balls as RXC on the GMII interface Datasheet 50 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 51 Table 6 RGMII Interface Signal Descriptions Sheet 2 of 2 Ball Signal Name Designator Type Standard Description RD3 0 Y7 RD2_0 W7 RD1_0 V7 RDO 0 v8 RD3 1 wg RD2_1 w11 i RD1 1 Y41 Receive Data RDO 1 Y9 Bits 3 0 are clocked on the rising edge of RXC Input 25V Bits 7 4 are clocked on the falling edge of RXC P CMOS Es NOTE
123. Address Conventions 44 4 224000 essen eee nnns 37 4 2 Interface Signal Groups ee tee o peer 38 4 3 Signal Description Tables 39 44 Ball Usage SUMINA uti 57 4 5 Multiplexed Ball 58 4 5 1 GMII RGMII SerDes OMI Multiplexed Ball 58 4 5 2 SPI3 MPHY SPHY Ball Connections 59 46 Ball State During 61 4 7 Power Supply 63 4 71 PowerUp rrr ete erede nied redde Fleece leve ete 63 4 7 2 Power Down 63 4 8 Pull Up Pull Down Ball 8 64 49 Analog Power Filtering eite or n 64 5 0 Functional Descriptions oerte eene 66 5 1 Media Access Controller MAC 66 5 1 1 Features for Fiber and Copper 67 5 1 1 1 Padding of Undersized Frames on 67 5 1 1 2 Automatic CRC Generation 67 5 1 1 3 Filtering of Receive Packets 67 5 1 1 4 CRC Error Detection ueniret pne occ 69 5 1 2 tr nece ear
124. C V23 RXC 3 R20 NC U10 VDD V24 RX N 3 R21 VDD U11 NC w1 TX ER 0 R22 0 U12 GND w2 GND R23 GND 013 GND UPX BADD1 R24 N 28 U14 AVDD2P5 2 W4 VDD T1 UPX_ADD4 U15 VDD W5 RX_ER_0 T2 UPX_BADDO U16 UPX_WIDTHO W6 GND T3 UPX_ADD10 U17 GND W7 RXD2_0 T4 UPX WR L U18 NC 8 VDD5 T5 UPX WIDTH1 U19 VDD4 9 RXD3 1 T6 NC U20 ER 3 W10 GND T7 NC 21 GND w11 RXD2_1 Datasheet 33 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 34 Intel Ball Ball Ball Ldcatiori Signal Name Signal Signal W12 VDD5 AA2 VDD5 AB16 AVDD1P8 2 W13 VDD4 AA3 TXD3 0 AB17 COL 3 W14 TXD7 3 AAA GND AB18 NC W15 GND AAS CRS_0 AB19 TXD5 2 W16 TX P 23 AAG VDD AB20 TXDO 2 W17 VDD4 4 1 21 TXD1 2 W18 RXD3 3 AA8 GND AB22 TXD2 2 W19 GND AA9 CRS 1 AB23 TXD3 2 W20 7 2 AA10 VDD AB24 No Ball w21 VDD AA11 RXD6_1 AC1 No Ball w22 RXD4 2 AA12 GND AC2 No Ball W23 GND AA13 GND AC3 TXD5 0 W24 14 4 3 4 VDD5 Y1 TXDO 0 AA15 VDD AC5 0 Y2 TXD1 0 AA16 TXD6 3 AC6 GND Y3 TXD2_0 AA17 GND AC7 TXDO 1 Y4 TXD7 0 AA18 TXD7_2 AC8 VDD5 Y5 RXD5 0 AA19 VDD AC9 TXD7 1 Y6 RXD4_0 AA20 TXD6 2 AC10 GND Y7 RXD3 0 AA21 GND AC11 RXD5
125. CRC is detected on a received frame the RX FCSError RMON statistic counter is incremented for each CRC errored frame Received frames with CRC errors may optionally be dropped in the RX FIFO refer to Section 5 1 1 3 6 Filter CRC Error Packets on page 68 Otherwise the frames are sent to the SPI3 interface and may be dropped by the switch or system controller Frames transmitted by the MAC are also checked for correct CRC When an incorrect CRC is detected a transmitted frame the TX CRCError RMON statistic counter is incremented for each incorrect frame Flow Control Flow Control is an IEEE 802 3x defined mechanism for one network node to request that its link partner take a temporary Pause in packet transmission This allows the requesting network node to prevent FIFO overruns and dropped packets by managing incoming traffic to fit its available memory The temporary pause allows the device to process packets already received or in transit thus freeing up the FIFO space allocated to those packets Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 1 2 1 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller The IXF1104 MAC implements the IEEE 802 3x standard RX FIFO threshold based Flow Control in copper and fiber modes When appropriately programmed the MAC can both generate and respond to IEEE standard pause frames in full duplex operation The IX
126. CTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The IXF1104 MAC Media Access Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in th
127. DAT 7 0 _0 3 RDAT 3t0 4 amp 3 RFCLK RFCLK P RENB 0 3 RENB RVAL 0 3 RVALO amp RERR 0 3 RERR 0 amp 4 RPRTY 0 3 RPRTY 0 RMOD 1 0 45 5 RSX 55 RSOP 0 3 RSOP 0 4 amp 4 REOP 0 3 REOP 0 TMS Interface 4 TRST_L MDIO 4 Interface MDC Pause 2 0 J Control interace TXPAUSEFR UPX_WIDTH 1 0 gt UPX_DATA 31 0 0 38 UPX_ADD 10 0 gt CPU UPX_BADD 1 0 J Interface UPX WR UPXRDL 9 UPXCSL gt UPXRDYL LED LED DATA amp 4 nterface LED LATCH amp 3 Intel IXF 1104 Media Access Controller GMII RGMII p TXC_0 3 TXC 0 3 P 0 7 0 0 TD 3 0 0 H TXD 7 0 _1 TD 3 0 1 H TXD Z0 2 TD 8 0 2 JM TXD Z0 3 TD 3 0 3 pP TXEN 03 TXCTL 0 3 p TX ER 0 3 RXC 03 RXC 0 3 Gud l RXD 7 0 3 RD 3 0_0 AGHA RXD 70 2 RD 3 0 _1 Interfaces M 7 0 1 0 3 0 2 MC RXD 7 0 0 RD 3 0 3 MC RXDV03 RXCTLO3 44 ER CRS 0 3 coL Data and clock balls are shared for GMII and RGMII Interfaces RX P N 0 3 SerDes TX P N 03 Interface IK TX DISABLE 0 3 I p MOD DE
128. Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 12 1 1 5 12 2 5 12 3 5 12 4 Datasheet Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller CLK125 The system interface clock which supplies the clock to the majority of the internal circuitry is the 125 MHz clock The source of this clock must meet the following specifications 2 5 V CMOS drive 50 ppm e Maximum duty cycle distortion 40 60 SPI3 Receive and Transmit Clocks The IXF1104 MAC transmit clock requirements include the following 3 3 V LVTTL drive 50 ppm e Maximum frequency of 133 MHz in MPHY mode e Maximum frequency of 125 MHz in SPHY mode e Maximum duty cycle distortion 45 55 The IXF1104 MAC meets the following specifications for the receive clock 3 3 V LVTTL drive e 50 ppm Maximum frequency of 133 MHz in MPHY mode Maximum frequency of 125 MHz in SPHY mode Maximum duty cycle distortion 45 55 RGMII Clocks The RGMII interface is governed by the Hewlett Packard 1 2a specification The IXF1104 MAC compliant to this specification with the following 2 5 V CMOS drive Maximum duty cycle distortion 40 60 100 ppm 125 MHz for 1000 Mbps 25 MHz for 100 Mbps and 2 5 MHz for 10 Mbps MDC Clock The IXF1104 MAC supports the IEEE 802 3 MII Management Interface also known as the Management Data Input Output MDIO Interface The IXF1104 MAC meets the following
129. Des devices that allow direct connection to optical modules and remove the requirement for external SerDes devices This increases integration which reduces the size of the PCB area required to implement this function reduces total power reduces silicon and manufacturing costs and improves reliability Each SerDes interface is identical and fully compliant with the relevant IEEE 802 3 Specifications including auto negotiation Each port is also compliant with and supports the requirements of the Small Form Factor Pluggable SFP Multi Source Agreement MSA see Section 5 7 Optical Module Interface on page 107 The following sections describe the operations supported by each interface the configurable options and the register bits that control these options A full list of the register addresses and full bit definitions are found in the register maps Table 59 through Table 69 Features The SerDes cores are designed to operate in point to point data transmission applications While the core can be used across various media types such as PCB or backplanes it is configured specifically for use in 1000BASE X Ethernet fiber applications in the IXF1104 MAC The following features are supported 10 bit data path which connects to the output input of the 8B 10B encoder decoder PCS that resides in the MAC controller Data frequency of 1 25 GHz Low power 200 mW per SerDes port Asynchronous clock data recovery Functional Des
130. Ethernet Media Access Controller 3 0 Ball Assignments and Ball List Tables 3 1 23 Ball Assignments See Figure 3 Table 1 Ball List in Alphanumeric Order by Signal Name on page 24 and Table 2 Ball List in Alphanumeric Order by Ball Location on page 30 for the IXF1104 MAC ball assignments Figure 3 552 Ball CBGA Assignments Top View ADACABAA W V U T P ML EDC BA 1 AD1 AC1 ABI AM Y1 wi Vi Ut Ti R1 P1 N1 L1 K1 H1 G1 F1 E1 01 C1 B1 A1 1 2 AD2 2 AB2 2 Y2 W2 v2 U2 T2 R2 P2 N2 M2 12 K2 J2 H2 G2 F2 E2 D2 C2 B2 A2 2 AD3 AB3 W3 V3 U3 T3 R3 P13 N3 M3 L3 K3 J3 H3 G3 F3 D3 C3 B3 3 AD4 Y4 4 V4 U4 T4 R4 P4 N4 M4 L4 K4 J4 H4 G4 F4 E4 D4 C4 B4 A4 4 5 AD5 5 AB5 AM Y5 w5 V5 U5 T5 R5 5 5 M5 15 K5 J5 H5 G5 F5 5 05 C5 B5 5 5 6 AD6 6 6 AA6 Y6 we V6 U6 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 F6 D6 C6 B6 6 7 7 7 Y7 W7 V7 U7 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 G7 B7 7 7 8 AD8 AC8 AB8 AA8 Y8 8 V8 U8 T8 R8 P8 N8 M8 L8 K8 J8 H8 G8 F8 E8 D8 C8 B28 A8 8 9 09 9
131. F 03 Tx FAULT M LOS 03 Optical 4 TX_FAULT_INT LOS INT Signals L MOD DEF INT p lt p DATA 0 3 These optical module signals are multiplexed on the GMII balls i SYS RES L System Interface CLK125 B3181 01 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 38 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 4 3 Signal Description Tables The I O signals power supplies or ground returns associated with each IXF1104 MAC connection ball are described in Table 3 through Table 14 Table 3 SPI3 Interface Signal Descriptions Sheet 1 of 8 Signal Name Ball 2 Standard Description MPHY SPHY Designator TDAT31 TDAT7 3 F7 Transmit Data Bus TDATSO TDAT6 F5 Carries payload data to the IXF1104 MAC TDAT29 TDAT5 3 G9 egress bah TDAT28 3 G8 TT 3 3 V 27 TDAT3 3 G7 pu LVTTL Mode Bits TDAT26 TDAT2_3 G6 TDAT25 TDAT1 3 G5 32 bit Multi PHY 81 24 TDAT24 TDATO 3 G4 4 x 8 Single PHY 7 0 for port 3 TDAT23 2 C8 Transmit Data Bus 22 TDAT6 2 F9 Carries payload data to the IXF1104 MAC TDAT21 5 2 E10 Su path TDAT20 TDAT4_2 E9 7 3 3 V TDAT19 TDAT3 2 E8 pu LVTTL Mode Bits TDAT18 TDAT2 2 E7 TDATI7 2 E6 32 bit Multi PHY 23 16 TDAT16 TDATO 2 E5 4 x 8 Single PHY 7
132. F1104 MAC also supports externally triggered flow control through the Transmit Pause Control interface In half duplex operation the MAC generates collisions instead of sending pause frames to manage the incoming traffic from the link partner 802 3x Flow Control Full Duplex Operation The IEEE 802 3x standard identifies four options related to system flow control No Pause Symmetric Pause both directions Asymmetric Pause Receive direction only Asymmetric Pause Transmit direction only The IXF1104 supports all four options on a per port basis Bits 2 0 of the Enable Port Index 0x12 on page 168 provide programmable control for enabling or disabling flow control in each direction independently The IEEE 802 3x flow control mechanism is accomplished within the MAC sublayer and is based on RX FIFO thresholds called watermarks The RX FIFO level rises and falls as packets are received and processed When the RX FIFO reaches a watermark either exceeding a High or dropping below a Low after exceeding a High the IXF1104 control sublayer signals an internal state machine to transmit a PAUSE frame The FIFOs automatically generate PAUSE frames also called control frames to initiate the following Halt the link partner when the High watermark is reached Restart the link partner when the data stored in the FIFO falls below the Low watermark Figure 7 illustrates the IEEE 802 3 FIFO flow control functions
133. FCLK RFCLK A19 Input Receive Parity RPRTY indicates odd parity for the RDAT bus RPRTY is valid only when a channel asserts RENB or RSX Odd parity is the RPRTY 0 RPRTY 0 E15 default configuration however even parity RPRTY 1 G16 3 3V can be selected see Table 147 on RPRTY 2 E20 Output page 215 RPRTY 3 F20 32 bit Multi PHY mode RPRTY_0 is the parity bit for all 32 bits 4 x 8 Single PHY mode Each bit of RPRTY 0 3 corresponds to the respective 0 n channel Receive Read Enable The RENB signal controls the flow of data from the receive FIFOs During data transfer RVAL must be monitored as it indicates if the RDAT 31 0 RPRTY RMOD 1 0 RSOP REOP RERR and RSX are valid The system may de assert RENB at any time if itis unable to accept data from the IXF1104 MAC When RENB is sampled Low a read is performed from the receive FIFO and the RDAT 31 0 RPRTY 0 0 A13 RMOD 1 0 RSOP REOP RERR RSX and RENB_1 A18 Input 3 3 V RVAL signals are updated on the following RENB_2 C19 LVTTL rising edge of RFCLK E24 When RENB is sampled High by the PHY device a read is not performed and the RDAT 31 0 RPRTY RMOD 1 0 RSOP REOP RERR RSX and RVAL signals remain unchanged on the following rising edge of RFCLK 32 bit Multi PHY Mode RENB 0 covers all receive bits 4 x 8 Single PHY Mode The RENB 0 3 bits correspond to the per port data and control
134. GMII modes or switching speeds and duplex in RGMII mode The following sequence applies to all four ports and can be done simultaneously for all ports or as a subset of the ports 1 Place MAC in reset for the port s which require a change by asserting set to 1 the Soft Reset 0x505 Place the TX FIFO in reset for the port s which require a change by asserting set to 1 the TX FIFO Port Reset 0x620 Disable the port s which require change by de asserting set to 0 the appropriate bits in the Port Enable 0x500 Wait 1 us 5 De assert set to 0 Clock and Interface Mode Change Enable Ports 0 3 0x794 for the 8 9 ports being changed Set the speed mode and duplex as follows for the ports being changed a Copper mode Select copper mode for the Interface Mode 0x501 ports Set the per port IF Mode and RGMII Speed Port Index 0x10 to the appropriate speed and RGMII GMII interface setting Set the per port Desired Duplex Port Index 0x02 Note Half duplex is supported only when RGMII 10 Mbps or 100 Mbps is selected in the IF Mode and RGMII Speed Port Index 0x10 b Fiber mode Select fiber mode by setting the appropriate bit to 0 in the Interface Mode 0x501 ports Assert set to 1 Clock and Interface Mode Change Enable Ports 0 3 0x794 for the ports being changed Wait 1 us De assert s
135. IO in Progress Misa 2 Enable 0 Disable MDIO in progress register bit R W 0 1 Enable MDIO in progress register bit Autoscan enable 1 Autoscan Enable 0 Disable Autoscan R W 0 1 Enable Autoscan MDC speed 0 MDC Speed 0 MDC runs at 2 5 MHz R W 0 1 MDC runs at 18 MHz 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet 212 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 8 4 9 SPI3 Register Overview Intel Table 146 through Table 148 Address Parity Error Packet Drop Counter 0x70A on page 219 provide an overview of the SPI3 registers Table 146 SPI3 Transmit and Global Configuration 0x700 Sheet 1 of 3 Bit Name Description Default Register Description This register gives the configuration related to the SPI3 Transmitter and Global configuration 4 x 8 mode 0x00200000 31 24 Reserved Reserved RO 0x00 23 SPI3 Transmitter Soft Reset 1 SPI3 TX block is reset R W 0 22 SPI3 Receiver Soft Reset 1 The SPI3 RX block is reset R W 21 SPHY MPHY Mode 0 Indicates that block operates in 32 bit MPHY mode 1 Indicates that the SPI3 block operates 4 x 8 SPHY mode This configurati
136. J14 VDD F11 NC H1 TDAT11 J15 GND F12 VDD2 H2 VDD2 J16 UPX_DATA28 F13 VDD3 H3 TDAT15 J17 UPX DATA30 F14 RDAT 7 H4 GND J18 RSOP 3 F15 GND H5 TEOP 3 J19 REOP 3 F16 RDAT 12 H6 VDD2 J20 VDD F17 VDD3 H7 NC J21 NC F18 RDAT 15 H8 GND J22 TCLK F19 GND H9 UPX DATA13 J23 TRST Datasheet 31 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 32 Intel Ball Ball Ball Ldcatiori Signal Name Signal Name Luestiori Signal Name J24 TDI L14 VDD N4 GND Ki TERR 1 L15 GND N5 UPX 5 K2 GND L16 VDD N6 VDD5 K3 UPX DATA1 L17 UPX_DATA31 N7 UPX_DATA11 K4 VDD L18 NC N8 GND K5 UPX_DATA7 L19 NC N9 VDD5 K6 GND L20 GND N10 UPX DATA15 K7 NC 121 NC N11 GND K8 VDD L22 LED LATCH N12 VDD5 K9 GND L23 PC N13 VDD4 K10 UPX DATA17 L24 C DATA 03 N14 GND Kt GND M1 UPX RDY L N15 UPX DATA26 K12 UPX DATA 1 M2 VDD2 N16 VDD4 K13 UPX DATA23 M3 UPX DATA3 N17 GND K14 GND M4 GND N18 NC K15 UPX DATA25 M5 UPX DATA6 N19 VDD4 K16 GND M6 VDD2 N20 TXPAUSE ADDO K17 VDD M7 NC N21 GND K18 NC M8 GND N22 MOD DEF INT K19 GND M9 VDD2 N23 VDD4 K20 NC M10 UPX DATA16 N24 DATA 23 21 VDD M11 GND P1 UPX ADD2 K22 NC M12 VDD2 P2 NC K23 GND M13 VDD3 P3 UPX ADDO K24 LED CLK M14 GND P4 NC L1 DTPA 1 M15 UPX_DATA27 P5 UPX_DATA
137. MII SerDes Optical Module These specifications are not guaranteed and are subject to change without notice Minimum and maximum values listed in Table 41 DC Specifications on page 134 through Table 58 LED Interface AC Timing Parameters on page 154 apply over the recommended operating conditions specified in Table 40 Table 39 Absolute Maximum Ratings Parameter Symbol Min Max Units Comments VDD 0 3 2 2 volts Core digital power VDD2 VDD3 0 3 4 25 volts digital power Supply voltage VDD4 VDD5 0 3 4 25 volts digital power AVDD1PS8 1 2 0 3 2 2 volts Analog power AVDD2P5 1 2 0 3 4 25 volts Analog power Operating Ambient TOPA 40 85 C Copper mode temperature Ambient TOPA 0 0 70 C Fiber mode Storage temperature TST 40 150 C Caution Exceeding these values may cause permanent damage to the device Functional operation under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 132 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 40 Recommended Operating Conditions Parameter Symbol Min Typ Max Units VDD 1 65 1 95 Volts VDD2 VDD3 3 0 3 6 Volts VDD4 VDD5 2 3 2 7 Volts Recommended s
138. Next Page Able 1 Local device is Next Page able RO Indicates that a new page has been received and the received code word has been loaded into 1 Page Received Register 5 base pages or Register 8 next pages RO 0 as specified in the EEE 802 3 Standard This bit clears on Read 0 Link Partner Auto 0 Link partner is not auto negotiation able RO 0 Negotiation Able 1 Link partner is auto negotiation able 1 RO Read Only RR Clear on Read W Write R W Read Write Table 102 Auto Negotiation Next Page Transmit Port Index 0x67 187 Bit Name Description Default 0x0000000 31 16 Reserved Reserved RO 0 0 Last page m Next Page NP 1 Additional Next Pages follow RO 0 14 Reserved Reserved RO 0 0 Unformatted page 13 Message Page MP 1 Message page RO 0 0 Cannot comply with message 15 Acknowledge 2 1 Complies with message RO 9 0 Previous value of the transmitted Link Code Word was logic one Toggle 1 Previous value of the transmitted Link Code RO 0 Word was logic zero 10 0 Message Unformatted 11 bit message code field RO 0 Code Field See IEEE 802 3 Annex 28C 1 RO Read Only RR Clear on Read W Write R W Read Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller
139. Octets 32 R 178 Ox4A TxPkts1519toMaxOctets 32 R 178 Ox4B TxDeferred 32 R 178 0 4 TxTotalCollisions 32 R 178 Ox4D TxSingleCollisions 32 R 178 Ox4E TxMultipleCollisions 32 R 178 Ox4F TxLateCollisions 32 R 178 0x50 TxExcessiveCollisionErrors 32 R 178 0x51 TxExcessiveDeferralErrors 32 R 178 0x52 TxExcessiveLengthDrop 32 R 178 0x53 TxUnderrun 32 R 178 0x54 TxTagged 32 R 178 0x55 TxCRCError 32 R 178 0x56 TxPauseFrames 32 R 178 0x57 TxFlowControlCollisionsSend 32 R 178 0x58 Datasheet 158 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 62 PHY Autoscan Registers Port Index Offset Table 64 Intel Register BitSize Mode Ref Page Offset PHY Control Port Index 0x60 32 RO 181 0x60 PHY Status Port Index 0x61 32 RO 182 0x61 PHY Identification 1 Port Index 0x62 32 RO 183 0x62 PHY Identification 2 Port Index 0x63 32 RO 184 0x63 Auto Negotiation Advertisement Port Index 0x64 32 RO 184 0x64 Link Partner Base Page Ability Port 32 RO 185 0x65 Auto Negotiation Expansion Port Index 0x66 32 RO 186 0x66 oo Next Page Transmit Port Index 32 RO 187 0x67 Reserved 32 RO 0x68 Ox6F Table 63 Global Status and Configuration Registers
140. PIM I E sii 83 5 244 MPAY Operation eocen ina a E T T 84 5 2 1 1 SPI3 RX Round Robin Data Transmission 84 5 2 2 MPAY Logical Timing 252 eoi eterne beoe once n EEE OE 84 5 12 21 TRANSMIT TImiligz eec needed re edt Sade et 85 52 2 2 HecelVe Timing oec e ner RARE ne 85 521213 GIOCK Rates erre 87 ELE MEM m 87 5222252 OPRY MOOG sui 87 5 2 26 SPHY Logical TIMIN ccce ener tian 88 5 2 2 7 Transmit Timing 5 88 5 2 2 8 Receive Timing SPHY 88 52290 SPIS Perte 91 5 2 3 Pre Pending Function iini cence ence 93 Gigabit Media Independent Interface GMII essen 93 5 3 1 GMII Signal Multiplexing 94 5 3 2 Interface Signal 94 Reduced Gigabit Media Independent Interface RGMII 96 5 4 1 Multiplexing of Data and 96 542 Timing eee EE nuns 97 543 TX_ER and ER 97 5 4291 Statista enhn areae ae esa se E ERR 99 5 4 4 10 100 Mbps
141. Pause Interface Strobe CMOS Table 9 Optical Module Interface Signal Descriptions Sheet 1 of 2 Ball er Signal Name Designator Type Standard Description Transmit Disable TX_DISABLE_0 3 outputs disable the Optical Module Interface transmitter An external pull up resistor usually resident in an optical module is TX DISABLE 0 AB3 Open required for proper operation TX_DISABLE_1 Dian 2 5V TX DISABLE 2 AD16 Output CMOS NOTE These signals are multiplexed with the TX DISABLE ATO 4 n bits of the GMII Interface NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output MOD DEF 90 3 inputs determine when an MOD DEF 0 Y6 Optical Module Interface is present MOD DEF 1 AD10 Input 2 5V MOD_DEF_2 W22 CMOS 2 T16 NOTE These signals are multiplexed with the RXD 4 n bits of the GMII interface LOS 0 3 inputs determine when the Optical RX LOS 0 ABS Module Interface receiver loses synchronization RX LOS 1 AA11 Input 2 5V RX_L 2 V19 CMOS T18 NOTE These signals are multiplexed with the RXD 6 n bits of the GMII interface TX FAULT 0 3 inputs determine an Optical TX FAULT 0 YS Module Interface transmitter fault TX_FAULT_1 AC11 Input 2 5V TX FAULT 2 V20 CMOS 117 NOTE These signals are multiplexed with the x RXD 5 n bits of the GMII Interface Receiver Loss of Signal Interrupt RX LOS INT is an open drain
142. Pb Reduced indicator Same as Jedec a Syww9001 Intel Finished Process Order FPO number e Back of the die Bare Silicon JJJJJJJJ Manufacturing Lot Number Country Assy plant Country of Origin QQ Quality Level P Proto Type PQ Potential Qual able 7 Production no marking 7 5 7 5 Rework Indicator E 5 0 mm 25 0 mm Ch ter Font aracter Fon Size 0 04 0 10 Diameter of Pin 1 mark is 70 mils 0 19 0 24 and is located opposite the top side substrate Pin 1 identifier amp intel id 0 06 0 10 Note Diameter of Trademark Circles are 70 mils Height of circles surrounding Pb redced symbol are equal to overall character height NOTE Pin1 does mean a Pin1 indicator not an actual mark B5131 01 NOTE The actual product name marking is IXF1104CE not HFIXF1104CE leaded version and WFIXF1104CE Pb reduced due to lidless package space limitation Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ntel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller G 10 0 Product Ordering Information Table 157 and Figure 60 provide IXF1104 MAC product ordering information Table 157 Product Information 5 4 RoHS Product Number Revision Type Compliant HFIXF1104CE BO BO CBGA No WFIXF1104CE BO BO CBGA Yes 1104 0 BO PBGA No NOTE 1 P
143. Port Gigabit Ethernet Media Access Controller Table 16 Line Side Interface Multiplexed Balls Sheet 2 of 2 Intel Copper Mode Fiber Mode mo Optica Module Unused Port Ball Designator NC NC TX FAULT INT NC P23 NC NC RX LOS INT NC P19 NC NC MOD DEF INT NC N22 MDC MDC NC NC W24 MDIO MDIO NC NC 21 NC NC PC CLK NC L23 NC NC PC DATA 0 3 NC L24 M24 N24 P24 1 An external pull up resistor is required with most optical modules 2 An open drain I O external 4 7 Q pull up resistor is required 4 5 2 SPI3 MPHY SPHY Ball Connections Table 17 lists the balls used for the SPI3 Interface and provides a guide to connect these balls in MPHY and SPHY mode Table 17 SPI3 MPHY SPHY Interface Sheet 1 of 3 SPI3 Signals Ball Number Comments MPHY SPHY 7 F7 F5 G9 G8 TDAT 31 24 TDAT 7 0 _3 G7 G6 G5 G4 C8 F9 E10 E9 MPHY Consists of a single 32 bit data TDAT 23 16 TDAT 7 0 2 E7 E6 5 bus H3 J3 J2 J1 SPHY Separate 8 bit data bus for each TDAT 15 8 TDAT 7 0 1 G2 G1 F4 Ethernet port C6 B5 C5 C4 TDAT 7 0 TDAT 7 0 0 D1 C3 C2 B3 To achieve maximum bandwidth set TFCLK as follows TFCLK TFCLK D7 MPHY 133 MHz SPHY 125 MHz TPRTY 0 TPRTY 0 D5 MPHY Use TPRTY 0 as the TPRTY GND TPRTY 1 G3 signal GND TPRTY 2 B9 SPHY Each port has its own dedicated TPRTY n signal GND TPRTY 3 J6 TENB
144. R 0x00000000 Counter on port 2 this port are shown in this register RX FIFO Overflow When RX FIFO on port 3 becomes full or Frame Drop reset the number of frames lost dropped on 0x597 R 0x00000000 Counter on port 3 this port are shown in this register 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 195 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 122 RX FIFO Port Reset 0x59E Bit Name Description Type Default Register Description The soft reset register for each port in the RX block Port ID bit position in the register To make the reset active the bit must be set High For example reset 0x00000000 of port 1 implies register value 0000 0018 Setting the bit to 0 de asserts the reset 31 4 Reserved Reserved RO 0x0000000 Port 3 Reset RX FIFO for 3 0 De assert reset R W 0 Port 3 1 Reset Port 2 Reset RX FIFO for 2 porto 0 De assert reset R W 0 1 Reset Port 1 Reset RX FIFO for 1 Porti 0 De assert reset R W 0 1 Reset Port 0 Reset RX FIFO for 0 0 De assert reset R W 0 Port 0 1 Reset 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write
145. RVAL 2 E19 LVTTL signals are valid When RVAL is Low the RVAL 3 F22 RDAT 31 0 RMOD 1 0 RSOP REOP and RERR signals are invalid and must be disregarded The RSX signal is valid only when RVAL is Low 32 bit Multi PHY mode RVAL 0 covers all receive bits 4x8 Single PHY mode The RVAL 0 3 bits correspond to the per port data and control signals Receive Start of Packet RSOP indicates the start of a packet when RSOP 0 RSOP 0 B16 asserted with RVAL RSOP 1 C18 Output 3 3V 32 bit Multi PHY mode RSOP 0 covers RSOP 2 E23 LVTTL all 32 bits HEROS dua 4 x 8 Single PHY mode The RSOP 0 3 bits correspond to the RDAT 7 0 n channels 45 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 3 Interface Signal Descriptions Sheet 8 of 8 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Signal Name MPHY SPHY Ball Designator Type Standard Description REOP 0 REOP 0 REOP 1 REOP 2 REOP 3 C16 D18 C23 J19 Output 3 3V LVTTL Receive End of Packet REOP indicates the end of a packet when asserted with RVAL 32 bit Multi PHY mode REOP 0 covers all 32 bits 4x8 Single PHY mode The REOP 0 3 bits correspond to the RDAT 7 0 n channels RMOD1 RMODO NA G13 G14 Output 3 3V LVTTL Receive Word Modulo 32 bit Multi PHY mode RMOD 1 0 indicates the valid bytes of data in RDAT
146. RX FIFO SPI3 Loopback Enable for Ports 0 3 0x5B2 199 Name Description Address Type Default RX FIFO Errored Frame Drop Counter on Port 2 This register counts all frames dropped from the RX FIFO for port 2 by meeting one of the following conditions Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable 0x59F and the RX Packet Filter Control Port_Index 0x19 Frames are greater than the Frame Size Addr Port Index OxOP This register is cleared on Read 0 5 4 R 0x00000000 RX FIFO Errored Frame Drop Counter on Port 3 This register counts all frames dropped from the RX FIFO for port 3 by meeting one of the following conditions Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable 0x59F and the RX Packet Filter Control Port_Index 0x19 Frames are greater than the Frame Size Addr Port Index OxOFP This register is cleared on Read 0 5 5 R 0x00000000 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Bit Name Description Type Default Register Description Enables t into the TX FIFO creating a SPI3 loopback he TX SPI3 port to send packets into the FIFO in stead of 0x00000000 31 12 Rese
147. Receive Configuration 0x701 on page 215 When bit 1 of the RX Packet Filter Control Port Index 0x19 0 all multicast frames are sent out the SPI3 interface 5 1 1 3 3 Filter Broadcast Packets This feature is enabled when bit 2 of the Packet Filter Control Port Index 0x19 1 Any broadcast frame received in this mode is marked by the MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3 Receive Configuration 0x701 on page 215 When bit 2 of the RX Packet Filter Control Port_Index 0x19 0 all broadcast frames are sent out the SPI3 interface 5 1 1 3 4 Filter VLAN Packets This feature is enabled when bit 3 of the RX Packet Filter Control Index 0x19 1 VLAN frames received in this mode are marked by the MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3 Receive Configuration 0x701 on page 215 When bit 3 of the RX Packet Filter Control Port Index 0x19 0 all VLAN frames are sent out the SPI3 interface 5 1 1 3 5 Filter Pause Packets This feature is enabled when bit 4 of the
148. Revision Number 009 Revision Date 27 Oct 2005 164 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 77 IPG Receive Time 1 Port Index 0 0 Name Description Address Default This timer is used during half duplex operation when there is a packet waiting for transmission from the MAC This timer starts after CRS is de asserted If CRS is asserted during this time no transmission is initiated IPG Receive Time 1 and the counter restarts once CRS is de Port Index R W 0x00000008 asserted again 0x0A The value specified in this register is calculated as follows register value 8 in terms of bit times Therefore default value of 8 gives the following 8 8 64 bit times for the default 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 78 IPG Receive Time 2 Port Index OxOB Name Description Address Default This is only used in half duplex operation It starts counting at the same time as RXIPG1 Once RXIPG1 expires a frame is transmitted when RXIPG2 expires regardless of the CRS value If CRS is asserted before RXIPG1 expires no transmission occurs and both IPG Receive Time 2 RXIPG1 an RXIPG2 are reset once CRS is Port Index Ryw 0 00000007 de asserted again Ox0B The value specified in this registe
149. SE T Receive Signal Parameters Symbol Parameter Min 11 RXD 7 0 DV RXER Setup to Rx CLK High 2 0 ns t2 RXD 7 0 DV RXER Hold after Rx High 0 0 ns testing 1000BASE T 10 or 1 ns 1 Typical values are at 25 and are for design aid only not guaranteed and not subject to production 2 Bit Time BT is the duration of one bit as transferred to from the PHY and is the reciprocal of bit rate BT for 143 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 5 SerDes AC Timing Specification Figure 40 SerDes Timing Diagram Tv Table 51 SerDes Timing Parameters Symbol Parameter Min Max Units Tt Transmit eye width 800 pS Rt Receiver eye width 280 pS Tv Transmit amplitude 1000 mV Rv Receiver amplitude 200 mV Datasheet 144 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 7 6 AC Timing Specification The MDIO Interface on the IXF1104 MAC can operate in two modes low speed and high speed In low speed mode the MDC clock signal operates at a frequency of 2 5 MHz In high speed mode the MDC clock signal operates at a frequency of 18 MHz See Figure 41 through Figure
150. Shares balls with RXD 3 0 0 on the GMII RD1_2 21 interface RDO 2 Y20 RD3 3 W18 RD2 3 Y19 RD1 3 Y18 RDO 3 Y17 Receive Control RX CTL is RX DV on the rising edge of RXC and bi a logical derivative of RX DV and RERR on the RX CTL 1 AB11 25V talling ed f 2 Y24 pu cmos 1819 edge o RX_CTL_3 V18 NOTE RX_CTL shares the same balls as RX_DV on the GMII interface Table 7 CPU Interface Signal Descriptions Sheet 1 of 2 Ball Signal Name Designator Type Standard Description UPX_ADD10 T3 UPX_ADD9 U3 UPX ADD8 V3 UPX ADD7 V2 UPX ADD6 V1 UPX ADDS Ut Input 33 V LVTTL 42 address bus from the UPX ADD4 Ti P UPX ADDS R1 UPX ADD2 P1 UPX ADD1 N1 UPX ADDO P3 16 bit mode The data word select uses UPX_BADD1 W3 UPX_BADD1 Input 3 3 V LVTTL UPX BADDO T2 2d 8 bit mode BADD 1 0 selects the individual bytes Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 7 CPU Interface Signal Descriptions Sheet 2 of 2 Datasheet Ball Signal Name Designator Type Standard Description 117 417 UPX DATA29 H16 UPX DATA28 J16 UPX DATA27 M15 UPX DATA26 N15 UPX DATA25 K15 UPX DATA24 H14 UPX DATA23 K13 UPX DATA22 G12 UPX DATA 21 K12 UPX DATA20 G11 UPX DATA19 H11
151. TRST J23 Input Jav Test Reset reset input for JTAG test LVTTL Table 13 System Interface Signal Descriptions Ball Signal Name Designator Type Standard Description 2 5V CLK125 is the input clock to PLL 125 MHz CLK125 AD19 Input CMOS 50 ppm SYS_RES_L AD12 Input eue SYS RES Lis the system hard reset active Low 55 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 14 Power Supply Signal Descriptions Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Signal Name Ball Designator Type Standard Description A4 A21 B6 B10 B15 B19 D4 D8 D12 013 D17 D21 F2 F6 F10 F15 F19 F23 H4 H8 H12 H13 H17 H21 J10 J15 K2 K6 K9 K11 K14 K16 K19 K23 L5 L10 L12 L13 L15 L20 M4 M8 M11 M14 GND M17 M21 N4 N8 Input Digital ground N11 N14 N17 N21 P10 P12 P13 P15 R2 R6 R7 R9 R11 R14 R16 R19 R23 T10 T15 U4 U8 U12 013 U17 021 W2 W6 W10 W15 W19 W23 AA4 AA8 12 AA13 AA17 AA21 AB12 6 10 AC14 AC15 19 AD21 AVDD1P8_1 A5 A20 Input 1 8V Analog 1 8 V supply AVDD1P8 2 AB16 T23 Input 1 8V Analog 1 8 V supply AVDD2P5 1 AD20 Input 2 5V Analog 2 5 V supply AVDD2P5 2 U14 R18 Input 2 5V Analog 2 5 V supply A10 C12 D6 D10 D11 D15 D19 F4 F21 H10 H15 J11 J14 J20 K4 K8 K17 K21 L9 L11 522 VDD L14 L16 P9 P11 Input 1 8V Digital 1 8 V supply P14 P16 R4 R8 R17 R21 T11 T14 U10 U15
152. TX DISABLE 0 3 MOD DEF INT TX FAULT INT RX LOS INT 5 7 22 1 MOD DEF 0 3 MOD DEF 0 3 are direct inputs to the IXF1104 MAC and are pulled to a logic Low level during normal operation indicating that a module is present for each channel respectively If a module is not present a logic High is received which is achieved by an external pull up resistor at the IXF1104 MAC device pad The status of each bit one for each port is found in bits 3 0 of the Optical Module Status Ports 0 3 0x799 on page 222 Any change in the state of these bits causes a logic Low level on the MOD DEF INT output if this operation is enabled 108 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 109 Note 5 7 22 2 TX FAULT 0 3 TX FAULT 0 3 are inputs to the IXF1104 MAC These signals are pulled to a logic Low level by the optical module during normal operation A logic Low level on these signals indicates no fault condition exists If a fault is present a logic High is received through the use of an external pull up resistor at the IXF1104 MAC pad The status of each bit one for each port can be found in bits 13 10 of the Optical Module Status Ports 0 3 0x799 on page 222 Any change in the state of these bits causes a logic Low level on the TX FAULT INT output if this operation is enabled 5 7 2 23 LOS 0 3 RX LOS 0 3
153. Table 34 LED DATA Decodes 5 8 6 1 LED MAC Port Fiber Designation Copper Designation 1 Rx LED Amber Link LED Amber 2 0 Rx LED Green Link LED Green 3 TX LED Green Activity LED Green 4 Rx LED Amber Link LED Amber 5 1 Rx LED Green Link LED Green 6 TX LED Green Activity LED Green 7 Rx LED Amber Link LED Amber 8 2 Rx LED Green Link LED Green 9 TX LED Green Activity LED Green 10 Rx LED Amber Link LED Amber 11 3 Rx LED Green Link LED Green 12 TX LED Green Activity LED Green LED Signaling Behavior Operation in each mode for the decoded LED data in Table 34 is detailed in Table 35 and Table 36 5 8 6 1 1 Fiber LED Behavior Table 35 LED Behavior Fiber Mode 119 Type Status Description Off Synchronization occurs but no packets are received and the Link LED Enable 0x502 is not set RX Synchronization has not occurred or no optical Amber signal exists The port has remote fault and the Link LED Enable RXLED Amber Blinking 0x502 is not set based on remote fault bit setting received in Rx Config word RX Synchronization occurs and the Link LED Enable Green 0x502 bit is set Green Blinking RX Synchronization occurs and the port is receiving data Off The port is not transmitting data or the Link LED Enable 0x502 is not set SES
154. UPX_ADD4 T1 UPX DATA28 J16 VDD U15 UPX ADD5 U1 UPX DATA29 H16 VDD W4 UPX_ADD6 V1 UPX_DATA30 J17 VDD wet UPX_ADD7 UPX DATAS1 L17 VDD AA6 UPX_ADD8 V3 UPX_RD_L V6 VDD AA10 UPX_ADD9 U3 UPX_RDY_L M1 VDD AA15 UPX_ADD10 T3 UPX_WIDTHO U16 VDD AA19 UPX_BADDO T2 UPX_WIDTH1 T5 VDD C12 UPX_BADD1 W3 UPX_WR_L T4 VDD D11 UPX CS L R3 VDD D6 VDD J20 UPX DATAO L2 VDD D10 VDD A10 UPX DATA1 K3 VDD D15 VDD2 B4 UPX DATA2 L3 VDD D19 VDD2 B8 UPX DATAS M3 VDD F4 VDD2 B12 UPX_DATA4 L4 VDD F21 VDD2 D2 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Signal Name m Signal Name Poe VDD2 F8 VDD5 N12 VDD2 F12 VDD5 T12 VDD2 H2 VDD5 U2 VDD2 H6 VDD5 U6 VDD2 J12 VDD5 W8 VDD2 M2 VDD5 W12 VDD2 M6 VDD5 AA2 VDD2 M9 VDD5 ACA VDD2 M12 VDD5 AC8 VDD3 B13 VDD5 AC12 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VDD4 N13 VDD4 N16 VDD4 N19 VDD4 N23 VDD4 T13 VDD4 U19 VDD4 U23 VDD4 W13 VDD4 W17 VDD4 AA23 VDD4 AC13 VDD4 AC17 VDD4 AC21 VDD5 N2 VDD5 N6 VDD5 N9 Datasheet 29 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 3 2 2 Balls Listed in Alphabeti
155. XF1104 MAC Supported Optical Module Interface Signals 107 5 7 2 Functional Descriptions re 108 5 7 2 1 High Speed Serial 108 5 7 2 2 Low Speed Status Signaling 108 5 7 3 PC Module Configuration 110 5 7 3 1 Control and Data 110 5 7 3 2 55 22 pua aser dps tud 110 5753 9 1C Write Operation 111 5 7 3 4 26 Protocol 112 5 7 3 5 Port Protocol Operation 113 5 7 3 6 Clock and Data Transitions seen 113 BEC M AX 115 5 8 1 Modes ae terrent andes anaemia cane aie 115 5 8 2 LED Interface Signal Description 116 5 8 3 Mode 0 Detailed 22222 4 116 5 8 4 Mode 1 Detailed 117 5 8 5 Power On Reset Initialization 118 5 8 6 LED DATA Decodes s cie be ei e d d 118 5 8 6 1 LED Signaling 119 e dcum 120 5 9 4 Functional Description uertice taedet naue ARE VR UR 121 5 9 1 1 Read AcCess nencen ee ete de no E
156. Y de ve E dn ER NER 121 5 9 1 2 WMO ACCESS 121 5 9 1 3 CPU Timing 5 122 IMP zr ee 122 TAP Interface J TAQ need E REED ERR T oiu 123 5 10 1 State 123 5 10 2 Instruction Register and Supported 124 5 10 3 D chicgm c marae 125 5 10 4 Boundary Scan Register simus ee i eani eR daa i 125 5 10 5 Bypass Reglster ccce nenne needed nene 125 Loopback MOd S 125 5 11 1 SPIS Interface 125 5 11 2 Line Side Interface Loopback 126 127 5 12 1 System Interface Reference 127 pm EH opi EE 128 5 12 2 SPI3 Receive and Transmit Clocks 128 5 12 3 ROMII ClOCKS eicere ertt nente rmn Ra eene iai x ra Cog eR x 128 5 12 4 E 128 5 12 5 TAG dee d aet pad or E EASE 129 512 6 FO Clock TC onc 129 S127 LED EE 129 5 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents ntel 6 0 Applications niece ete need set
157. abit Media Independent Interface Reduced Gigabit Media Independent Interface RGMII Figure 1 illustrates the IXF1104 MAC block diagram Figure 1 Block Diagram PHY 1 Device PHY 2 Device Intel IXF1104 MAC PHY 3 Device PHY 4 Device SerDes RGMII GMII Interface o o o 2 2 c 2 o B3175 01 21 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 2 illustrates the IXF1104 MAC internal architecture Figure 2 Internal Architecture CPU Interface RMON Statistics RGMII GMII Interface 10 100 1000 MAC PMA Layer SerDes Packet TX Bx Buffer RGMII GMII Interface M Packet 10 100 1000 MAC Buffer PMA Layer SerDes SPI3 Interface Packet RGMII GMII Interface Buffer 10 100 1000 MAC Packet PMA Layer SerDes RX Buffer RGMII GMII Interface Clock Control Block Clock Register Block 10 100 1000 MAC PMA Layer SerDes PLLs MDIO OMI B3176 01 Datasheet 22 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit
158. able the block R W 0 24 start Start the I C transfer R W 0 23 Reserved Reserved RO 0 22 write complete Bit is asserted when write access is complete R 0 21 Reserved Reserved RO 0 20 Read complete Bit asserted when read access is complete R 0 19 18 Reserved Reserved RO 0 Selects the port for which the 2 transaction is 17 16 Port Select targeted Valid range is 0 to 3 BAL ap 0 Write transaction us Read Write 1 Read transaction PUE 0 14 11 Device ID Most significant four bits of device address field R W 0x0 Bits 10 8 select the least significant three bits of 10 0 Register Address the device address field R W 0x000 Bits 7 0 select the word register address 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 156 I C Data Ports 0 3 0x79F Bit Name Description Default Register Description These registers hold data bytes that are read and written using the 1 C interface to Optical Module Interfaces connected to each port of the Intel IXF1104 4 Port 0x00000000 Gigabit Ethernet Media Access Controller 31 24 Reserved Reserved RO 0x00 Bit 23 MSB Bit 16 LSB 23 16 Write Data R W 0X00 Data to be written to the Optical Module Interface 15 8 Reserved Reserved RO 0x00 Bit 7 MSB Bit 0 LSB 7 0 Read Data R W 0X00 Data read from the Optical Module Interf
159. ace 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 223 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 tel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 9 0 Mechanical Specifications The IXF1104 MAC is packaged in a 576 ball BGA package with 6 balls removed diagonally from each corner for a total of 552 balls used measuring 25 mm x 25 mm The pitch of the package balls is 1 mm 9 1 Overview CBGA standard and RoHS compliant and FC PBGA packages are suited for applications requiring high I O counts and high electrical performance and are recommended for high power applications with high noise immunity requirements Note The FC PBGA package will not be available until mid 2006 Please see your field sales representative for more detailed information 9 1 1 Features Flip chip die attach surface mount second level interconnect High electrical performance High I O counts Area array I O options Multiple power zone offering supports core and four additional voltages JEDEC compliant package 9 2 Package Specifics The IXF1104 MAC uses the following package 576 ball BGA package with 6 balls removed diagonally from each corner for a total of 552 balls used Ball pitch of 1 0 mm Overall package dimensions of 25 mm x 25 m
160. ad W Write only R W Read Write No clear R W C Read Write Clear on Write Bit Name Description Type Default Register Description Per port s oftware activated reset of the MAC core 0x00000000 31 4 Reserved Reserved R W 0x00000 Port 3 3 Software Reset MAC 0 Reset inactive R W 0 1 Enable Port 2 2 Software Reset MAC 2 0 Reset inactive R W 0 1 Enable Port 1 1 Software Reset 1 0 Reset inactive R W 0 1 Enable Port 0 0 Software Reset MAC 0 0 Reset inactive R W 0 1 Enable 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 107 MDIO Soft Reset 0x506 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 1 2 Reset active Bit Name Description Type Default Register Description Software activated reset of the MDIO module 0x00000000 31 1 Reserved Reserved RO 0x00000000 Software Reset 9 Reset inactive R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 108 CPU Interface 0x508 Bit Name Description Type Default Register De
161. ad packets Note This count includes non pause control and RxUCPkts VLAN packets which are also counted in other Port Index R 0x00000000 counters These packet types are counted twice 0x22 Take care when summing register counts for reporting Management Information Base MIB information The total number of multicast packets received excluding bad packets Note This count includes pause control packets port Ingex RxMCPkts which are also counted in the PauseMacContro 9x03 R 0x00000000 ReceivedCounter These packet types are counted twice Take care when summing register counts for reporting MIB information The total number of Broadcast packets received Port Index excluding bad packets 0x24 0x00000000 The total number of packets received including bad packets that were 64 octets in length Port_Index FxPkts64Octets Incremented for tagged packets with a length of 0x25 0x00000000 64 bytes including tag field 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 When sending in large frames the counters can only handle certain limits The behavior of the LongErrors and VeryLongErrors counters is as follows VeryLongErrors counts frames that are 2 maxframesize dependent upon where maxframesize is set If maxframesize sets greater than half of the available count in RxOctetsBad 2 14
162. afe transition to a new operational mode see Section 6 1 Change Port Mode Initialization Sequence on page 130 The Enable clock mode change bit has to be set back to 1 after the configuration change takes effect 31 4 Reserved Reserved RO 0x0000000 0 Fiber mode 3 Port 3 Interface Mode 1 Copper mode R W 0 0 Fiber mode 2 Port 2 Interface Mode 1 Copper mode R W 0 0 Fiber mode 1 Port 1 Interface Mode 1 Copper mode R W 0 0 Fiber mode 0 Port 0 Interface Mode 1 Copper mode R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet 188 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 105 Link LED Enable 0x502 Table 106 MAC Soft Reset 0x505 189 Intel Bit Name Description Default Register Description Per port bit should be set upon detection of link to enable proper 0x00000000 operation of the link LEDs 31 4 Reserved Reserved R W 0x00000 Port 3 link 3 Link LED Enable Port3 0 No link R W 0 1 2 Link Port 2 link 2 Link LED Enable Port2 o No link R W 0 1 2 Link Port 1 link 1 Link LED Enable Port 0 No link R W 0 1 2 Link Port O link 0 Link LED Enable PortO 0 No link R W 0 1 2 Link 1 RO Read Only No clear on Read R Read Clear on Re
163. al bit in each mode is defined in Table 34 on page 119 The data is TRUE Logic 1 LED ON High These bits are used as fillers in the data stream to extend the length 36 38 PAD BITS from the actual 30 bit LED DATA to the required 36 bit frame length These bits should always be a logic 0 When implemented on the board with the M5450 device the LED DATA bit 1 appears on Output bit 3 of the M5450 and the LED DATA bit 2 appears on Output bit 4 etc This means that Output bits 1 2 and 15 through 35 will never have valid data and should not be used 5 8 4 Mode 1 Detailed Operation Note Please refer to generic specifications for 74LS HC599 for information on device operation The operation of the LED Interface in Mode 1 is based on a 36 bit counter loop The data for each LED is placed in turn on the serial data line and clocked out by the LED CLK Figure 30 on page 118 shows the basic timing relationship and relative positioning in the data stream of each bit Figure 30 on page 118 shows the 36 clocks which are output on the LED pin The data is changed on the falling edge of the clock and is valid for the almost the entire clock cycle This ensures that the data is valid during the rising edge of the LED CLK which clocks the data into the shift register chain devices The LED LATCH signal is required in Mode 1 and latches the data shifted into the shift register chain into the output latches of the 74HC599 device Figure
164. al bus in 32 bit mode The CPU Interface 0x508 selects Big Endian or Little Endian mode The byte swapper causes the behavior seen in Table 37 for accessing a register with data bits data 31 0 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 122 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 37 Byte Swapper Behavior 5 10 5 10 1 123 intel Little Endian Big Endian UPX BADD 32 bit 16 bit 8 bit 32 bit 16 bit 8 bit 1 0 UPX_DATA_ UPX_DATA UPX_DATA UPX_DATA UPX_DATA UPX_DATA 81 0 15 0 7 0 31 0 15 0 7 0 7 0 15 8 7 0 00 81 0 15 0 7 0 23 16 15 8 7 0 31 24 01 15 8 15 8 _ _ 23 16 10 31 16 23 16 81 24 23 16 11 31 24 31 24 1 In 8 bit mode data is output in Little Endian format regardless of the IXF1104 MAC Endian setting TAP Interface JTAG The IXF1104 MAC includes an IEEE 1149 1 compliant Test Access Port TAP interface used during boundary scan testing The interface consists of the following five signals e TDI Serial Data Input TMS Test Mode Select TCLK TAP Clock TRST L Active Low asynchronous reset for the TAP TDO Serial Data Output TDI and TMS require external pull up resistors to float the signals High per the IEEE 1149 1 specification Pull ups are recommended on TCK and TDO Fo
165. all Ball Signal Name Location Signal Name ection Signal Name Location No Ball AC1 RDAT 26 G20 ER 0 W5 No Ball AC2 RDAT 27 621 RX ER 1 Y12 No Ball AC23 RDAT 28 G22 RX ER 2 AA22 No Ball AC24 RDAT 29 G23 RX ER 3 U20 No Ball AD1 30 G24 RX LOS INT P19 No Ball AD2 RDAT 31 F24 0 R22 No Ball AD3 RENB 0 A13 N 1 U22 No Ball AD22 RENB 1 A18 23 R24 No Ball AD23 RENB 22 C19 3 V24 No Ball AD24 RENB 3 E24 RX P 03 P22 No Pad A1 REOP 0 C16 P 13 v22 PTPA B11 REOP 1 D18 RX P 23 T24 RDAT 0 A15 REOP 2 C23 RX P 33 U24 RDAT 1 A14 REOP 3 J19 RXC 0 V4 RDAT 2 B14 RERR 0 A16 RXC 1 AD11 RDAT 3 C14 RERR 1 G17 2 AA24 RDAT 4 C13 RERR 2 D20 RXC 3 V23 RDAT_5 D14 RERR 3 H20 RXDO 0 V8 RDAT 6 E14 RFCLK A19 RXDO 1 Y9 RDAT 7 F14 RMODO G14 RXDO 2 Y20 RDAT 8 A17 RMOD1 G13 RXDO 3 Y17 RDAT_9 C17 RPRTY 0 E15 RXD1 0 V7 RDAT 102 D16 RPRTY 1 G16 RXD1 1 Yu 112 E16 RPRTY 2 E20 RXD1 2 Y21 RDAT 12 F16 RPRTY 3 F20 RXD1 3 Y18 RDAT 13 E17 RSOP 0 B16 RXD2 0 W7 RDAT 14 E18 RSOP 1 C18 RXD2 1 w11 RDAT 152 F18 RSOP 2 E23 RXD2_2 Y22 RDAT 16 B20 RSOP 3 J18 RXD2_3 Y19 RDAT 17 B22 RSX E13 RXD3 0 Y7 RDAT 18 C20 RVAL 0 C15 RXD3 1 W9 RDAT 19 C21 1 B18 RXD3 2 Y23 RDAT_202 C22 RVAL 22 E19 RXD3 3 W18 212 D22 RVAL_ 3 F22 RXD4 0 Y6 RDAT 22 E22 RX DV 0 V5 RXDA 1 AD10 RDAT 23 E21 RX DV 1 AB11 RXD4 21 W22 RDAT 24 G18 RX DV 2 Y24 RXD4 3 T
166. an 2 V at any time during the power up or power down sequence NOTE The 3 3 V supply VDD2 and VDD3 can be applied at any point during this sequence 4 8 Pull Up Pull Down Ball Guidelines The signals shown in Table 20 require the addition of a pull up or pull down resistor to the board design for normal operation Any balls marked as unused NC should be unconnected Table 20 Pull Up Pull Down and Unused Ball Guidelines Pin Name Pull Up Pull Down Comments TX FAULT INT Pull up 4 7 Q to 2 5 V Optical module signal with open drain I O RX_LOS_INT Pull up 4 7 k Q to 2 5 V Optical module signal with open drain I O MOD_DEF_INT Pull up 4 7 Q to 2 5 V Optical module signal with open drain I O TDI Pull up 10 k Q to 3 3 V JTAG test pin TDO Pull up 10 k Q to 3 3 V JTAG test pin TMS Pull up 10 k Q to 3 3 V JTAG test pin TCLK Pull up 10 k Q to 3 3 V JTAG test pin TRST L Pull down 10 k Q to 3 3 V JTAG test pin MDIO Pull up 4 7 k Qto 2 5 V UPX RDY L Pull up 4 7 k Qto 3 3 V DATA 0 3 Pull up 4 7 k Q to 2 5 V TX DISABLE 0 3 Pull up 4 7 k Qto 2 5 V 4 9 Analog Power Filtering Figure 21 illustrates an analog power supply filter network and Table 21 lists the analog power balls Datasheet 64 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 65 Figure 6 Analog Power Supply Filte
167. and the LEDs are enabled in the LED Control 0x509 on page 190 If a port is not enabled all the LEDs for that port are off If the LEDs are not enabled all of the LEDs are off CPU Interface The CPU interface block provides access to registers and statistics in the IXF1104 MAC The interface is asynchronous externally and operates within the 125 MHz clock domain internally The interface provides access to the following Receive statistics registers Transmit statistics registers Receive FIFO registers Transmit FIFO registers Global configuration and control registers MAC 0 to MAC 3 registers The CPU interface width can be configured with the two strap signals UPX WIDTH 1 0 to operate as an 8 bit 16 bit or 32 bit bus internal accesses to registers are 32 bit 4 2 or 1 data cycles respectively are required to fully access a register When operating in 8 bit or 16 bit mode read data for bytes 3 1 is strobed into read holding registers when byte 0 is read Subsequent reads of bytes 1 2 3 in byte mode or of bytes 2 3 in 16 bit mode are supplied from the holding register independent of the upper address bits On write accesses in 8 bit mode the data of bytes 0 1 2 is similarly captured in internal write holding registers and the complete 32 bit write is committed when byte 3 is written to the IXF1104 MAC When writing in 16 bit mode bytes 1 0 are captured and the double word
168. ar on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 When sending in large frames the counters can only handle certain limits The behavior of the LongErrors and VeryLongErrors counters is as follows VeryLongErrors counts frames that are 2 maxframesize dependent upon where maxframesize is set If maxframesize sets greater than half of the available count in RxOctetsBad 214 1 VeryLongErrors is never incremented but LongErrors is incremented This is due to a limitation in the counter size which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2414 1 3 This register is relevant only when configured for copper operation 4 This register is relevant only when configured for fiber operation line side interface is SerDes Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 176 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 177 Table 93 MAC RX Statistics Port Index 0x20 0x39 Sheet 4 of 4 Intel Name Description Address Type Default RxRuntErrors The total number of packets received that are less than 64 octets in length but longer than or equal to 96 bit times which corresponds to a 4 byte frame with a well formed preamble and SFD This is the shortest fragment and can be transmitted in case of a collision event on a half duplex segment This coun
169. ar on Write 2 Reserved bits must be written to the default value for proper operation Table 91 RX Packet Filter Control Port Index 0x19 Sheet 1 of 2 Bit Name Description Type Default Register Description This register allows for specific packet types to be marked for filtering and is used in conjunction with the RX FIFO Errored Frame Drop Counter Ports 0 0x5A2 0x00000000 0x5A5 31 6 Reserved Reserved 0 This bit enables a Global filter on frames with a CRC Error 0 When CRC Error Pass 0 all frames with a CRC Error are marked as bad 1 2 Frames with a CRC Error are not marked as bad and are passed to the SPI3 interface for transfer as good frames regardless of the state of the bits in the RX FIFO Errored 5 CRC Error Pass Frame Drop Enable 0x59F RAN 0 NOTE When the CRC Error Pass Filter bit O it takes precedence over the other filter bits Any packet whether is a Pause Unicast Multicast or Broadcast packet with a CRC error is marked as a bad frame when CRC Error Pass 0 This bit enables a Global filter on Pause frames 0 All pause frames are dropped 1 All pause frames are passed to the SPI3 4 Pause Frame Pass R W 0 NOTE Pause Frames can only be filtered if RXFD flow control is enabled in the FC Enable Port Index 0x12 This bit enables a global filter on VLAN frames 3 VLAN Drop En 0 All VLAN frames are passe
170. asheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 19 TX CTL Behavior Valid Frame TXC 0 3 at Transmitter _f Vy Xo wg 2 03 en TX EN False TX ER False TX CTL 0 3 TX ER False End of Frame TX EN True Frame with Error TXC 0 3 at Transmitter meos TX EN False TX ER False X EN True TX ER False TX CTL 0 3 End of Frame 0616 02 Figure 20 RX Behavior Valid Frame DV False ER False RX CTL 0 3 RX ER False End of Frame ad DV True Frame with Error 0 3 fex ova ER True s RX DV False RX_ER False End of Frame B3237 01 Datasheet 98 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 4 3 1 5 4 4 5 5 99 Note In Band Status Carrier Sense CRS is generated by the PHY when a packet is received from the network interface CRS is indicated when RXDV true RXDV false RXERR true and a value of FF exists on the RXD 7 0 bits simultaneously Carrier Extend Carrier Extend Error or False Carrier occurs please reference the Hewlett Packard Version 1 2a RGMII Specification for
171. at a frequency of 104 MHz The IXF1104 MAC defines operation for the transfer of data at data rates of up to 4 256 Gbps when operating at a maximum frequency of 133 MHz in MPHY mode and 125 MHz in SPHY Mode There is no guarantee of the number of bytes available since the size of packets is variable An IXF1104 MAC port transmit packet available status is provided on signals DTPA STPA or PTPA indicating the TX FIFO is nearly full In the receive direction RVAL indicates if valid data is available on the receive data bus and is defined so that data transfers can be aligned with packet boundaries Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 2 1 5 2 1 1 5 2 2 Note Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller The SPI3 interface supports the following two modes of operation MPHY or 32 bit mode one 32 bit data bus e SPHY or 4 x 8 mode four individual 8 bit data buses MPHY Operation The MPHY operation mode is selected when bit 21 of the SPI3 Transmit and Global Configuration 0x700 is set to 0 and bit 7 of the SPI3 Receive Configuration 0x701 is set to 1 Data Path The IXF1104 MAC SPI3 interface has a single 32 bit data path in the MPHY configuration mode see Figure 13 The bus interface is point to point one output driving only one input load so a
172. ata Parity Errors Short SOPs two consecutive SOPs for a port TX FIFO errored with no EOP frame drop counter 0x626 R 0x00000000 on Port 1 Small Packets 9 14 bytes Frames received that are signaled with TERR on the SPI3 TX interface NOTE This register is cleared on Read This register provides the number of packets dropped by the TX FIFO due to the following Data Parity Errors Short SOPs two consecutive SOPs for a port TX FIFO errored with no EOP frame drop counter 0x627 R 0x00000000 on Port 2 Small Packets 9 14 bytes Frames received that are signaled with TERR on the SPI3 TX interface NOTE This register is cleared on Read This register provides the number of packets dropped by the TX FIFO due to the following Data Parity Errors Short SOPs two consecutive SOPs for a port TX FIFO errored with no EOP frame drop counter 0x628 R 0x00000000 on Port 3 Small Packets 9 14 bytes Frames received that are signaled with TERR on the SPI3 TX interface NOTE This register is cleared on Read 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 209 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 140 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller TX FIFO Occupancy Counter for Ports 0 3 0x62D 0x630 Name D
173. ator for Port 2 to sample the MAC IF Mode and RGMII Speed Index 0x10 and the Interface Mode 0x501 Clock and interface 0 Setto zero when changes are being made to cg hange Enagle the MAC IF Mode and RGMII Speed RAN 9 Port Index 0x10 the Interface Mode 0x501 1 Setto 1 for the configuration changes to take effect Enables internal clock generator for Port 1 to sample the MAC IF Mode and RGMII Speed Index 0x10 and the Interface Mode 0x501 and Interface 0 Setto zero when changes are being made to R nanga Enaole the MAC IF Mode and RGMII Speed 9 Port Index 0x10 and the Interface Mode 0x501 1 Setto 1 for the configuration changes to take effect Enables internal clock generator for Port 0 to sample the MAC IF Mode and RGMII Speed Port Index 0x10 and the Interface Mode 0x501 Interface 0 Setto zero when changes are being made to MUNERE the MAC IF Mode and RGMII Speed 2 Port Index 0x10 the Interface Mode 0x501 1 Setto 1 for the configuration changes to take effect 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 Refer to Section 6 1 Change Port Mode Initialization Sequence on page 130 for the proper sequence to change the port mode and speed in conjunction with this regi
174. bracketed bus designation followed by an underscore and the port designation For example RGMII transmit data bus signals are identified as TD 3 0 0 TD 3 0 1 TD 3 0 _2 and so on Active Low Designation A control input or indicator output that is active Low is designated by a final suffix consisting of an underscore followed by an upper case L For example the CPU cycle complete identifier is shown as 1 Register Address Conventions Registers located in on chip memory are accessed using a register address which is provided in Hex notation A Register Address is indicated by the dollar sign followed by the memory location in Hex Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 4 2 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Interface Signal Groups This section describes the IXF1104 MAC signals in groups according to the associated interface or function Figure 4 shows the various interfaces available on the IXF1104 MAC Figure 4 Interface Signals SPHY MPHY 7 0 0 3 TDAT 31 0 gt TFCLK TFCLK gt TENB 0 3 TENB gt TERR 0 3 TERR 0 P TPRTY 0 3 TPRTY 0 gt TMOD 1 0 TSX TSOP_0 3 TSOP gt TEOP 03 TEOP 0 TADR 1 0 TADR 1 0 9 SPI3 DTPA 0 3 DTPA 03 46 6 Interface STPA 4 j PTPA PTPA 4 R
175. c Order by Ball Location Intel Table 2 shows the ball locations and signal names arranged in order by ball location Table 2 Ball List in Alphanumeric Order by Ball Location 30 Ball Ball Te Signal Name Al No Pad A2 No Ball A3 No Ball d GND AS AVDD1P8_1 A6 TMODO A7 TEOP 0 A8 TERR_0 A9 DTPA 2 A10 UB 11 TADRO A12 TADR1 A13 RENB_0 A14 RDAT 1 15 RDAT 0 A16 RERR 0 A17 8 A18 RENB 1 A19 RFCLK A20 AVDD1P8_1 A21 GND A22 No Ball ABS No Ball A24 No Ball EN No Ball No Ball p3 TDATO B4 VDD2 B5 TDAT6 6 GND B7 TENB 0 B8 VDD2 B9 TPRTY_2 Location Signal Name Location Signal Name B10 GND C20 RDAT 18 B11 PTPA C21 RDAT 19 B12 VDD2 C22 20 B13 VDD3 C23 REOP 2 B14 RDAT 2 C24 No Ball GND D1 TDAT32 B16 RSOP_0 D2 VDD2 B17 VDD3 D3 DTPA 0 B18 RVAL_12 D4 GND B19 GND D5 TPRTY 0 B20 RDAT 16 D6 VDD 21 VDD3 D7 TFCLK B22 RDAT 17 D8 GND B23 No Ball D9 TMOD1 B24 No Ball D10 VDD C1 No Ball D11 VDD C2 TDAT1 D12 GND C3 TDAT2 D13 GND C4 TDAT4 D14 RDAT 5 C5 52 015 VDD C6 TDAT7 D16 RDAT 10 C7 TSOP 0 D17 GND C8 TDAT23 D18 REOP 1 C9 TENB 2 D19 VDD C10 TSOP 2 D20 RERR 2 C11 STPA 21 GND C12 VDD D22 RDAT 21 C
176. cal Module Registers 0x799 79 159 Edited Table 63 Global Status and Configuration Registers 0x500 0X50C no offset 159 Edited Table 64 RX FIFO Registers 0x580 Ox5BF no offset 160 Edited Table 65 TX FIFO Registers 0x600 Ox63E no offset 161 Edited Table 66 MDIO Registers 0x680 0x683 no offset 161 Edited Table 67 SPI3 Registers 0x700 0x716 no offset 162 Edited Table 68 SerDes Registers 0x780 0x798 no offset 162 Edited Table 69 Optical Module Registers 0x799 0x79F no offset 163 Modified Table 71 Desired Duplex Port Index 0x02 changed 100 Mbps to 1000 Mbps in register description 167 Modified Table 82 IF Mode and RGMII Speed Port Index 0x10 Added text to register description 168 Modified Table 84 Enable Port Index 0x12 changed description for bits 1 0 169 Modified Table 88 RX Config Word Port Index 0x16 edited Register Description text changed description and type for bits 13 12 170 Modified Table 89 TX Config Word Port Index 0x17 edited description and type for bits 14 13 12 171 Modified Table 90 Diverse Config Write Port Index 0x18 edited description and type for bits 18 8 changed bits 3 1 to Reserved added table note 2 172 Renamed modified Table 91 RX Packet Filte
177. ceeds the RX FIFO transfer threshold it can no longer be dropped by the RX FIFO even if it is marked to be dropped by the MAC RMON Statistics Support The IXF1104 MAC supplies RMON statistics through the CPU interface These statistics are available in the form of counter values that can be accessed at specific addresses in the register maps Table 59 through Table 69 Once read these counters automatically reset and begin counting from zero separate set of RMON statistics is available for each MAC device in the IXF1104 MAC Implementation of the RMON Statistics block is similar to the functionality provided by existing Intel switch and router products This implementation allows the IXF1104 MAC to provide all of the RMON Statistics group as defined by RFC2819 The IXF1104 MAC supports the RMON RFC2819 Group statistics counters Table 25 notes the differences and additional statistics registers supported by the IXF1104 MAC that are outside the scope of the RMON RFC2819 document 80 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 81 Table 25 RMON Additional Statistics Sheet 1 of 2 Intel Definition of RMON Rx Statistics ONLY RMON Ethernet Statistics IXF1104 MAC Equivalent Versus Group 1 Statistics Statistics IXF1104 Documentation etherStatsindex Integer
178. ck of resources This number is not necessarily the number of packets dropped itis the number of times this condition is detected The RX FIFO Overflow Frame Drop Counter Ports 0 3 0x594 0x597 and TX FIFO Overflow Frame Drop Counter Ports 0 3 0x621 0x624 in the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows If any IXF1104 MAC programmable packet filtering is enabled the RX FIFO Errored Frame Drop Counter Ports 0 3 0x5A2 0x5A5 and TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0x629 increment with every frame removed in addition to the existing frames counted due to FIFO overflow Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 25 RMON Additional Statistics Sheet 2 of 2 Definition of RMON RMON Ethernet Statistics Type IXF1104 MAC Equivalent Type Versus Group 1 Statistics yp Statistics 1104 Documentation etherStatsOversizePkts Counter32 FAXEODITHES Counter 32 Same as RMON TxExcessiveLength Drop specification Same as RMON etherStatsFragments Counter32 RuntErrors Counter 32 specification Same as RMON etherStatsJabbers Counter32 JabberErrors Counter 32 specification The TxTotalCollision count value is xMultipleCollision equivalent to the etherSta
179. ckets 69 Added note under Table 22 CRC Errored Packets Drop Enable Behavior 69 Added new Section 5 1 2 Flow Control including Figure 7 Packet Buffering FIFO Figure 8 Ethernet Frame Format and Figure 9 PAUSE Frame Format 73 Replaced Section 5 1 2 1 5 Transmit Pause Control Interface added Table 23 Valid Decodes for TXPAUSEADD 2 0 and modified Table 10 Transmit Pause Control Interface 74 Modified Figure 10 Transmit Pause Control Interface 75 Added note under Section 5 1 3 1 Configuration 76 Added table note to Table 24 Operational Mode Configuration Registers 77 Added note under Section 5 1 4 3 Fiber Forced Mode 79 Modified Section 5 1 6 2 TX Statistics added text to third sentence in first paragraph 79 Modified Section 5 1 6 3 Loss less Flow Control changed two kilometers to five kilometers in last sentence 80 Modified Section 5 1 7 1 2 RX FIFO changed 10 KB to 9 6 KB added text to last paragraph 83 Rewrote replaced Section 5 2 SPI3 Interface 86 Edited signal names in Figure 13 32 Bit Interface 90 Edited signal names in Figure 16 SPHY Connection for Two Intel IXF1104 MAC Ports 8 Bit Interface 91 Added new Section 5 2 2 9 SPI3 Flow Control Removed old Packet Level and Byte Level Transfers section 94 Modified Figure 17 MAC GMII Interconn
180. cription The SerDes transmit interface sends serialized data at 1 25 GHz The interface is differential with two signals for transmit operation The transmit interface is designed to operate in 100 Q differential environment and all the terminations are included on the device The outputs are high Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 6 2 1 5 6 2 2 Table 29 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller speed SerDes and are capable of operating in either an AC or DC coupled environment AC coupling is recommended for this interface to ensure that the correct input bias current is supplied at the receiver The SerDes receive interface receives serialized data at 1 25 GHz The interface is differential with two signals for the receive operation The equalizer receives a differential signal that is equalized for the assumed media channel The SerDes transmit and receive interfaces are designed to operate within a 100 differential environment and all terminations are included on the device The SerDes is capable of operating in either AC or DC coupled environments Transmitter Operational Overview The transmit section of the IXF1104 MAC has to serialize the Ten Bit Interface TBI data from the IXF1104 MAC MAC section and outputs this data at 1 25 GHz differential signal levels The 1 25 GHz differential SerDes signals are compliant with th
181. cur R 0 1 FIFO overflow event occurred Port 0 0 FOEO 0 FIFO overflow event did not occur R 0 1 FIFO overflow event occurred 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 136 Loop RX Data to TX FIFO Line Side Loopback Ports 0 3 0x61F Bit Name Description Type Default Register Description This register enables data received from the line side receive interface 0x00000000 through the MAC to be sent to the TX FIFO and back to the line side transmit interface 31 4 Reserved Reserved RO 0x0000000 3 Port 3 Line Side 0 Disable line side loopback R W 0 Loopback 1 Enable line side loopback 2 Port 2 Line Side 0 Disable line side loopback RW 0 Loopback 1 Enable line side loopback 1 Port 1 Line Side 0 Disable line side loopback RW 0 Loopback 1 Enable line side loopback 0 Port 0 Line Side 0 Disable line side loopback RW 0 Loopback 1 Enable line side loopback 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 137 TX FIFO Port Reset 0x620 Sheet 1 of 2 Bit Name Description Default Register Description This is a port reset register for each port in the TX block Port ID bit position in the register To make the port active the bit must be se
182. d Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 129 RX FIFO Transfer Threshold Port 1 0x5B9 Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 1in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 RX FIFO transfer threshold for port 1 This must be less than the RX FIFO High watermark User definable control register that sets the threshold where a packet starts transitioning to the SPI3 interface from the RX FIFO before the 11 0 EOP is received Packets received in the RX R W 0x0BE FIFO below this threshold are treated as store and forward NOTE Do not program the RX FIFO transfer threshold below a setting of OXBE 1520bytes 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 201 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 130 RX FIFO Transfer Threshold Port 2 0x5BA Threshold Port 2 received Packets received in the RX FIFO below this threshold are treated as store and forward NOTE Do not program the RX FIFO transfer threshold below a setting of OXBE 1520bytes
183. d description text 215 Modified Table 147 SPI3 Receive Configuration 0x701 broke out bits and modified all text adding SPHY and MPHY modes 221 Modified Table 152 Clock and Interface Mode Change Enable Ports 0 3 0x794 deleted second paragraph of the Register Description renamed bits to match caption changed text under Description 222 Added note under Section 8 4 11 Optical Module Register Overview 222 Modified Table 153 Optical Module Status Ports 0 3 0x799 edited register description 222 Modified Table 154 Optical Module Control Ports 0 3 0x79A changed register description NA Removed Reserved Table 190 TX and RX AC DC Coupling Selection 7x780 NA Deleted old Figure 19 Typical GBIC Module Functional Diagram under Section 5 7 Optical Module Interface NA Removed old Section 5 1 1 5 Pause Command Frames 180 old Removed old Table 13 TX FIFO Mini Frame Size for MAC and Padding Enable Port 0 to 3 Register Addr Ox63E and replaced with Reserved Revision Number 006 Revision Date August 21 2003 Sheet 1 of 2 Page Description 19 Modified Table 1 Intel IXF1104 Signal Descriptions 53 Modified Section 5 1 1 1 Padding of Undersized Frames on Transmit 60 Modified text for etherStatsCollision in Table 9 RMON Additional Statistics 87 Modified Table 17
184. d to the SPI3 R W 0 Interface 1 All VLAN frames are dropped 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 Used in conjunction with the RX FIFO Errored Frame Drop Enable 0x59F on page 196 This allows the frame to be dropped in the RX FIFO Otherwise the frame is sent out the SP3 interface and may be optionally signaled with an RERR see bit 0 of SPI3 Receive Configuration 0x701 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 172 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 91 RX Packet Filter Control Port Index 0x19 Sheet 2 of 2 Bit Name Description Type Default This bit enables a Global filter on broadcast frames 2 B Cast Drop En 0 All broadcast frames are passed to the R W 0 Interface 1 All broadcast frames are dropped This bit enables a filter on multicast frames 0 All muticast frames are good and passed to the SPI3 Interface 1 M Cast Match En 1 Only multicast frames with a destination R W 0 address that matches the PortMulticastAddress are forwarded All other muticast frames are dropped This bit enables a filter on unicast frames 0 All unicast frames are good and are passed to the SPI3 Interface 1 Only unicast frames with a Destination 0 U Cast Match Address that
185. d to the four ports of IXF1104 MAC when those ports are in copper mode The MDIO Master Interface block is implemented once in the IXF1104 MAC The MDIO Interface block contains the logic through which the user accesses the registers in PHY devices connected to the MDIO MDC interface which is controlled by each port The MDIO Master Interface block supports the management frame format specified by IEEE 802 3 clause 22 2 4 5 This block also supports single MDI access through the CPU interface and an autoscan mode Autoscan allows the IXF1104 MAC MDIO master to read all 32 registers of the per port copper PHYs and store the contents in the IXF1104 MAC This provides external CPU ready access to the PHY register contents through a single CPU read without the latency of waiting on the low speed serial MDIO data bus for each register access Scan of a single register with low frequency operation takes approximately 25 6 us Scan of a 32 register block takes approximately 820 us 3 3 ms for all four ports Autoscan data is not valid until approximately 19 2 us after enabling scan These numbers scale by 7 50 for high frequency operation Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 5 1 5 5 2 5 5 3 5 5 4 5 5 4 1 5 5 4 2 Datasheet Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller MDIO Address The 5 bit PHY address for the MDIO transactions can be set in th
186. data from external device RO 0x0000 15 0 MDIO Write Data MDIO Write data to external device R W 0x0000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 211 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 144 Autoscan PHY Address Enable 0x682 Bit Name Description Type Default Register Description Defines valid PHY addresses Each bit enables the corresponding PHY address 0 Disable the PHY address 0x00000000 1 Enable the PHY address NOTE Autoscan is only applicable for the ports in copper mode 31 4 Reserved Reserved RO 0x0000000 Autoscan PHY address enable Aut n PHY 3 0 ns 0 Disable address R W 1111 Address 1 Enable address 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 145 MDIO Control 0x683 Bit Name Description Default Register Description Miscellaneous control bits 0x00000000 31 4 Reserved Reserved RO 0x000 MDIO progress This bit reflects the status of MDIO transaction 3 MDIO in Progress RO 0 i g 0 MDIO Single command not in progress 1 2 MDIO Single Command in progress Enables the MDIO in progress bit MD
187. des status of the TX FIFO based on the port selected by the TADR 1 0 address bus When High PTPA indicates that the amount of data in the TX FIFO for the port selected is below the TX FIFO High watermark When the High watermark is crossed PTPA transitions Low to indicate the TX FIFO is almost full It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark PTPA then transitions High to indicate the programmed number of bytes are now available for data transfers The port reported by PTPA is updated on the rising edge of TFCLK after the TADR 1 0 port address 15 sampled PTPA is updated on the rising edge of TFCLK 92 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 2 3 5 3 93 Note Note Pre Pending Function The IXF1104 MAC implements a pre pending feature to allow 1518 byte Ethernet packets to be pre padded with two additional bytes of data so that the packet becomes low word aligned The 2 byte pre pend value is all zeros and is inserted before the destination address of the packet being pre pended This value is fixed and cannot be changed This function is enabled by writing the appropriate data to the RX FIFO Padding and CRC Strip Enable 0x5B3 for each port A standard 1518 byte Ethernet packet occupies 379 long words four bytes with two additional bytes left over 15
188. details Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only Collision is determined at the MAC by the assertion of TXEN being true while either CRS or RXDV are true The PHY will not assert CRS as a result of TXEN being true 10 100 Mbps Functionality The RGMII interface implements the 10 100 Mbps Ethernet Media Independent Interface MIT by reducing the clock rate to 25 MHz for 100 Mbps operation and 2 5 MHz for 10 Mbps The TXC is generated by the MAC and the RXC is generated by the PHY During packet reception the RXC is stretched on either the positive or negative pulse to accommodate transition from the free running clock to a data synchronous clock domain When the speed of the PHY changes a similar stretching of the positive or negative pulses is allowed No glitching of the clocks is allowed during speed transitions This interface operates at 10 Mbps and 100 Mbps speeds in the same manner as 1000 Mbps speed although the data may be duplicated on the falling edge of the appropriate clock The MAC holds TX CTL Low until it is operating at the same speed as the PHY The IXF1104 MAC does not support 10 100 Mbps operation when configured in GMII mode MDIO Control and Interface The IXF1104 MAC supports the IEEE 802 3 MII Management Interface also known as the Management Data Input Output MDIO Interface This interface allows the IXF1104 MAC to monitor and control each of the PHY devices that are connecte
189. e Ref Page Address Reserved 32 RO 0x780 0x783 TX Driver Power Level Ports 0 3 0x784 32 R W 220 0x784 Reserved 32 RO 0x785 0x786 TX and RX Power Down 0x787 32 R W 220 0x787 Reserved 32 RO 0x788 0x792 RX Signal Detect Level Ports 0 3 0x793 32 R W 220 0x793 acre Interface Mode Change Enable Ports 0 3 32 R W 221 0x794 Reserved 32 RO 0x795 0x798 Table 69 Optical Module Registers 0x799 0x79F Register Bit Size Mode Ref Page Address Optical Module Status Ports 0 3 0x799 32 R 222 0x799 Optical Module Control Ports 0 3 0x79A 32 R W 222 0x79A IC Control Ports 0 0x79B 32 R W 223 0x79B Reserved 32 RO 0 79 0 79 Data Ports 0 3 0x79F 32 R W 223 Ox79F Datasheet 162 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 8 4 1 MAC Control Registers In Table 70 through Table 92 Port Multicast Address Port Index 0x1A 0 1 on page 173 provide details on the control and status registers associated with each MAC port The register address is index 0x where the port index is set at any value from 0 0 through 0x5 registers are 32 bit The unused bits of the registers are read only and are set permanently to zero Table 70 Station Address Port Index 0x00 0x
190. e MDIO Single Command 0x680 Bits 5 2 of the PHY address are fixed to a value of 0 Bits 1 and 0 are programmable in bits 9 and 8 of MDIO Single Command 0x680 MDIO Register Descriptions For complete information on the MDI registers refer to the Table 142 MDIO Single Command 0x680 on page 211 Table 143 MDIO Single Read and Write Data 0x681 on page 211 Table 144 Autoscan PHY Address Enable 0x682 on page 212 and Table 145 Control 0x683 on page 212 Clear When Done The MDI Command register bit in the MDIO Single Command 0x680 clears upon command completion and is set by the user to start the requested single MDIO Read or Write operation This bit is cleared automatically upon operation completion MDC Generation The MDC clock is used for the MDIO MDC interface The frequency of the MDC clock is selectable by setting bit 0 MDC Speed in an IXF1104 MAC configuration register see Table 145 MDIO Control 0x683 on page 212 MDC High Frequency Operation The high frequency MDC is 18 MHz derived from the 125 MHz system clock by dividing the frequency by 7 The duty cycle is as follows MDC High duration 3 x 1 125 MHz 3 x 8 ns 24 ns e MDC Low duration 4 x 1 125 MHz 4 x 8 ns 32 ns MDC runs continuously after reset Refer to Figure 41 MDC High Speed Operation Timing on page 145 for the high frequency MDC timing diagram MDC Low Frequency Operation The
191. e SPHY mode signals Unlike MPHY mode each port has a dedicated control signal associated with each of the per port 8 bit data buses Table 3 SPI3 Interface Signal Descriptions on page 39 provides signal descriptions for all SPI3 signals 5 2 2 5 2 Receive Data Transmission Packets are transmitted on each port as they become available from the RX FIFO The burst length is determined by the setting of per port burst size and the B2B pause settings in the SPI3 Receive Configuration 0x701 If the B2B pause setting is zero pause cycles inserted then the entire packet will be burst without any pauses unless the Network Processor de asserts RENB If the B2B Pause setting calls for the insertion of two pause cycles on a port these are inserted after each data burst for that port The data bursts are user configurable for each port in the SPI3 Receive Configuration 0x701 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 2 2 6 5 2 2 7 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller SPHY Logical Timing SPI3 interface AC timing for SPHY can be found in Section 7 2 SPI3 AC Timing Specifications on page 137 Logical timing in the following diagrams illustrates all signals associated with SPHY mode SPHY mode is similar to MPHY mode except the following signals are not used e TMOD I 0 e RMOD 1 0 TSX RSX Address Data appearing on the data bus T
192. e Small Form Factor Pluggable SFP Multi Source Agreement MSA The transmitter section takes the contents of the data register within the MAC and synchronously transfers the data out ten bits at a time Least Significant Bit LSB first followed by the next Most Significant Bit MSB When these ten bits have been serialized and transmitted the next word of 10 bit data from the MAC is ready to be serialized for transmission The data is transmitted by the high speed current mode differential SerDes output stage using an internal 1 25 GHz clock generated from the 125 MHz clock input Transmitter Programmable Driver Power Levels The IXF1104 MAC SerDes core has programmable transmitter power levels to enhance usability in any given application The SerDes Registers are programmable to allow adjustment of the transmit core driver output power When driving a 100 differential terminated network these output power settings effectively establish the differential voltage swings at the driver output The TX Driver Power Level Ports 0 3 0x784 allows the selection of four discrete power settings The selected power setting of these inputs is applied to each of the transmit core drivers on a per port basis Table 29 SerDes Driver TX Power Levels lists the normalized power settings of the transmit drivers as a function of the Driver Power Control inputs The normalized current setting is 10 mA which corresponds to the normalized powe
193. e eens 130 6 1 Change Port Mode Initialization 130 6 2 Disable and Enable Port 131 6 2 1 Disable Port Sequence ecce 131 622 Port Sequere ipee ete dual itenedesanncandesbinendug 131 7 0 Electrical 132 7 4 5 iss vised 133 71 1 Undershoot Overshoot 135 7 1 2 RGMII Electrical Characteristics 135 7 2 SPI3 AC Timing Specifications 137 7 2 1 Receive Interface 0 137 7 2 2 Transmit Interface Timing 139 7 3 RGMII AC Timing Specification 141 7 4 GMII AC Timing Specification 142 7 4 1 1000 Base T Operation 142 7 4 1 1 1000 BASE T Transmit 142 7 4 1 2 1000BASE T Receive Interface 143 7 5 SerDes AC Timing 5 144 7 6 MDIO AC Timing 5 145 7 6 1 MDC High Speed Operation 145 7 6 2 MDC Low Speed Operation 145 7 6 39 AC Timing iecore cct le seen aet eheu e 146 77 Opt
194. e following sequence provides an example of writing data to Register Address OxFF for Port 3 1 Program the Control Ports 0 3 0x79B with the following information a Enable the C block by setting Register bit 25 to Ox1 111 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Set the port to be accessed by setting Register bits 17 16 to 0 3 Select a Write access by setting Register bit 15 to 0 0 a Set the Device ID Register bits 14 11 to Ah Atmel compatible Set the 11 bit register address Register bits 10 0 to OFFh f Enable the 2 controller by setting Register bit 2 to 0 1 g Initiate the C transfer by setting Register bit 24 to 0 1 All other bits in this register should be set to 0 0 This data is written into the Control Ports 0 3 0x79B in a single cycle via the CPU interface 2 When this register is written and the Start bit is at a Logic 1 the access state machine examines the Port Address Select and enables the PC DATA 0 3 output for the selected port 3 The state machines uses the data in the Device ID and Register Address fields to build the data frame to be sent to the optical module 4 The DATA WRITE FSM internal state machine takes over the task of transferring the actual data between the IXF1104 MAC and the selected optical
195. e only R W Read Write No clear R W C Read Write Clear on Write 167 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 84 FC Enable Port Index 0x12 Bit Name Description Type Default Register Description Indicates which flow control mode is used for the RX and TX MAC 0x00000007 31 3 Reserved Reserved R 0x00000000 When TX HDFC is enabled half duplex mode only the MAC generates deliberate collisions on incoming packets when the RX FIFO occupancy 2 TX HDFC crosses the High Watermark flow control R W 1 0 Disable TX half duplex flow control 1 Enable TX half duplex flow control 0 Disable TX full duplex flow control the MAC will not generate internally any flow control frames based on the RX FIFO watermarks or the Transmit Pause Control interface 1 TX FDFC 1 Enable TX full duplex flow control enables R W 1 the MAC to send flow control frames to the link partner based on the RX FIFO programmable watermarks or the Transmit Pause Control interface 0 Disable RX full duplex flow control the MAC will not respond to flow control frames sent to it by the link partner 0 RX FDFC 1 Enable RX full duplex flow control MAC will R W 1 respond to flow control frames sent by the link partner and will stop packet transmission for the time specified in the flow control
196. e threshold value is a 16 bit value that sets the time in terms of 512 bit quantum after the previous pause frame when the next pause frame has to be sent This ensures that the link partner is kept in pause mode continuously 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Pause Threshold Port Index OXOE R W 0x0000002F Table 81 Max Frame Size Addr Port_Index 0x0F Name Description Address Type Default This is a 14 bit value configuring the maximum frame size the MAC can receive or transmit without activating any error counters and without truncation This value is excluding the 4 byte CRC in the Max Frame Size transmit direction when CRC append is enabled in the MAC Hence this value has to be set four bytes less when CRC append is enabled in the MAC The maximum frame size is internally adjusted by 4 if the frame is VLAN tagged 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Port Inde x OXOF R W 0x000005EE Datasheet 166 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 82 MAC IF Mode and RGMII Speed 5 Port Index 0x10 Intel 011 Re
197. eceive interface to be looped back to the transmit line side interface A SPI3 loopback mode allows the SPI3 transmit interface to be looped back to the SPI3 receive interface The IXF1104 MAC line side and SPI3 loopback modes are effective diagnostic tools for validation of system level connectivity and interface compatibility In loopback mode operation the data path is internally redirected to allow for the data flow return path Redirection requires the data path to circumvent resources that are required during normal traffic flow For example while operating in SPI3 loopback mode the data path does not pass through the MAC or TX FIFO and those resource features are not used The result is a possible degradation of throughput performance and statistical data accuracy Intel recommends that loopback modes be used for diagnostic purposes only SPI3 Interface Loopback To provide a diagnostic loopback feature on the SPI3 interface it is possible to configure the IXF1104 MAC to loop back any data written to the IXF1104 MAC through the SPI3 transmit interface back to the SPI3 receive interface This is accomplished using the data path shown in Figure 33 Loopback packets also appear on the line side TX interface Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 33 SPI3 Interface Loopback Path Note 5 11 2 Datasheet SPI
198. ect edited signal names NA Removed old Section 5 3 3 Electrical Requirements and Table 27 Electrical Requirements changed Input high current Max from 40 to 15 and Input low current Min from 600 to 15 96 Added a note under Section 5 4 Reduced Gigabit Media Independent Interface RGMII 96 Modified Figure 18 RGMII Interface edited signal names Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 15 Contents 16 Revision Number 007 Revision Date March 24 2004 Sheet 3 of 5 Page Description 98 Modified Figure 19 TX CTL Behavior changed signal names 98 Modified Figure 20 RX_CTL Behavior changed signal names 99 Modified Section 5 5 MDIO Control and Interface changed 3 3 us to 3 3 ms in fourth paragraph third sentence 103 Modified replaced all text under Section 5 6 SerDes Interface on page 103 added Table 29 SerDes Driver TX Power Levels NA Removed old Section 5 6 2 4 AC DC Coupling NA Removed old Section 5 6 2 9 System Jitter 107 Modified Table 30 Intel IXF1104 MAC to SFP Optical Module Interface Connections edited signal names 107 Modified replaced text and deleted old Figure 19 Typical GBIC Module Functional Diagram under Section 5 7 Optical Module Interface 108 Modified second sentence u
199. ed as a runt packet when the length excluding Preamble and SFD is equal to or greater than this value and less than 64 bytes NOTE This register is only relevant when the IXF1104 MAC port is configured for copper operation the line side interface is configured for either RGMII or GMII Port Index 0x14 R W 0x00000008 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 87 Discard Unknown Control Frame Port Index 0x15 Bit Name Description Default Register Description Discards or forwards unknown control frames Known control frames 0x00000000 are pause frames 31 1 Reserved Reserved R 0x00000000 0 Discard Unknown 0 Forward unknown control frames R W 0 Control Frame 1 Discard unknown control frames 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 88 RX Config Word Port_Index 0x16 Sheet 1 of 2 Bit Name Description Default Register Description This register is used in fiber MAC only for auto negotiation and to report the receive status The lower 16 bits of this register are the config reg received from the link 0x00000000 partner as described in IEEE 802 3 2000 Edition Section 37 2 1 31 22 R
200. ed signal names All Globally changed SerDes and PLL analog power ball names as follows TXAVTT and RXAVTT changed to AVDD1P8_2 TXAV25 and RXAV25 changed to AVDD2P5 2 PLL1 VDDA and PLL2 VDDA changed to AVDD1P8 1 PLL3_VDDA changed to AVDD2P5 1 PLL1 GNDA PLL2 GNDA and PLL3 GNDA changed to GND Reworded and rearranged the Product Features section on page one Changed Jumbo frame support from 10 kbytes to 9 6 KB 21 Changed heading to Section 2 0 General Description was Section 2 0 Block Diagram 23 37 Reversed sections as follows Section 3 0 Ball Assignments and Ball List Tables Section 4 0 Ball Assignments and Signal Descriptions 24 Modified Table 1 Ball List in Alphanumeric Order by Signal Name Changed A10 from VCC to VDD Changed C12 from VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD Changed Ball A1 from NC to No Pad Changed Balls A2 A3 A22 A23 A24 B1 B2 B23 B24 C1 C24 AB1 AB24 AC1 AC2 AC23 AC24 AD1 AD2 AD3 AD22 AD23 AD24 from NC to No Ball 30 Modified Table 2 Ball List in Alphanumeric Order by Ball Location Changed A10 from VCC to VDD Changed C12 form VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD Changed Ball A1 from NC to No Pad Changed Balls A2 A3 A22 A23 A24 B1 B2 B23 B24 C1 C24 AB1 AB24 AC1 AC2 AC23 AC24 AD1 AD2 AD3 AD22 AD23 AD24 from NC to No Ball 38 Updated Figure
201. en read The software must poll these registers to accumulate values and to ensure that the counters do not wrap The 32 bit counters wrap after approximately 30 seconds Table 94 covers all four MAC ports TX statistics Port Index is the port number 0 1 2 or 3 Table 94 MAC TX Statistics Port Index 0x40 0x58 Sheet 1 of 4 Datasheet Name Description Address Default OctetsTransmittedOK Counts the bytes transmitted in all legal frames The count includes all bytes from the destination MAC address to and including the CRC The initial preamble and SFD bytes are not counted Any initial collided transmission attempts before a successful frame transmission do not add to this counter Port Index 0x40 0x00000000 OctetsTransmittedBad Counts the bytes transmitted in all bad frames The count includes all bytes from the destination MAC address to and including the CRC The initial preamble and SFD bytes are not counted Late collision counted The count is close to the actual number of bytes transmitted before the frame is discarded Excessive collision counted The count is close to the actual number of bytes transmitted before the frame is discarded TX under run counted The count is expected to match the number of bytes actually transmitted before the frame is discarded TX CRC error counted All bytes not sent with success are counted by this counter Any initial
202. enable disable bits Enable 0x500 Bits 3 0 2 Apply TX FIFO soft reset TX FIFO Port Reset 0x620 Bits 3 0 3 Introduce some delay to allow completion of packet transmission not necessary if link is dropped 4 Flush TX Flush TX Port Index 0x11 Bit 0 5 Apply MAC soft reset MAC Soft Reset 0x505 Bits 3 0 6 Apply RX FIFO soft reset RX FIFO Port Reset 0x59E Bits 3 0 6 2 2 Enable Port Sequence Use the following sequence to enable an individual port 1 Enable the port s using MAC port enable disable bits Port Enable 0x500 Bits 3 0 2 Disable TX FIFO soft reset FIFO Port Reset 0x620 Bits 3 0 3 Reset flush TX Flush TX Index 0x11 Bit 0 4 Disable MAC soft reset Soft Reset 0x505 Bits 3 0 5 Disable RX FIFO soft reset FIFO Port Reset 0x59E Bits 3 0 131 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 7 0 Electrical Specifications Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 39 through Table 58 LED Interface AC Timing Parameters on page 154 and Figure 35 SPI3 Receive Interface Timing on page 137 through Figure 52 LED AC Interface Timing on page 154 represent the target specifications of the following IXF1104 MAC interfaces SPB JTAG MDIO Pause Control CPU LED System GMII and RG
203. ency of 133 MHz MPHY mode operates at a maximum clock frequency of 133 MHz TFCLK and RFCLK Parity The IXF1104 MAC can be odd or even the IXF1104 MAC is odd by default when calculating parity on the data bus This can be changed to accommodate even parity if desired and can be set for transmit and receive independently The RX Parity is set in bit 12 of the SPI3 Receive Configuration 0x701 and the TX Parity is set in bit 4 of the SPI3 Transmit and Global Configuration 0x700 SPHY Mode The SPHY operation mode is selected when bit 21 of the Table 146 SPI3 Transmit and Global Configuration 0x700 on page 213 is set to 1 The SPHY mode is the default operation for the IXF1104 MAC SPD interface 5 2 2 5 1 Data Path The IXF1104 MAC SPI interface has four 8 bit data paths that can support four independent 8 bit point to point connections in SPHY mode see Figure 16 Since each MAC port has its own dedicated 8 bit SPI3 data bus each port has it own status signal unlike MPHY See the For a detailed list of all the signals refer to the SPI3 pin multiplexing table Furthermore since each port has it own dedicated bus the in band port addressing is not needed The 8 bit data bus eliminates the need to have separate control signals determine the number of valid bytes on an EOP Therefore TSX RSX TMOD 1 0 RMOD 1 0 are not used in SPHY mode See Table 17 SPI3 MPHY SPHY Interface on page 59 for a complete list of th
204. enn no Aa edad 81 26 GMIl Interface Signal Definitions 95 27 RGMII Signal Definitions sce csi cette citt cta uo RE 97 28 TX ER Coding 97 29 SerDes Driver TX Power 5 104 30 Intel IXF1104 MAC to SFP Optical Module Interface 107 31 LED Interface Signal Descriptions 116 32 Mode 0 Clock Cycle to Data Bit 117 33 Mode 1 Clock Cycle to Data Bit 118 34 LED DATA Decodes 22 rac tone nale Rape 119 35 LED Behavior Fiber Mode 119 36 LED Behavior Copper 120 37 Byte Swapper a RA eA ge 123 38 Instruction Register 124 39 Absolute Maximum 5 132 40 Recommended Operating 133 41 DC 5 amp 134 42 SerDes Transmit 134 43 SerDes Receive Characteristics 4 4010 000 eee 135 44 Undershoot Overshoot Limits
205. ernet Media Access Controller 5 7 3 6 3 Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8 bit words The optical module E7PROM sends zero to acknowledge that it has received each word which happens during the ninth clock cycle see Figure 27 Figure 27 Acknowledge Timing Data sheet DATAIN X DATA OUT START ACKNOWLEDGE 5 7 3 6 4 Memory Reset After an interruption in protocol power loss or system reset any 2 wire optical module can be reset by following three steps 1 Clock up to 9 cycles 2 Wait for PC DATA High in each cycle while PC CLK is High 3 Initiate a start condition 5 7 3 6 5 Device Addressing All E7PROMS SFP optical module devices require an 8 bit device address word following a start condition to enable the chip to read or write The device address word consists of a mandatory one Zero sequence for the four most significant bits This is common to all devices The next three bits are the A2 Al and AO device address bits that are tied to zero in an optical module The eighth bit of the device address is the Read Write operation select bit A Read operation is initiated if this bit is High and a Write operation is initiated if this bit is Low Upon comparison of the device address the optical module outputs a zero If a comparison is not made the optical module E7PROM returns to a standby state 5 7 3 6 6
206. ers Symbol Parameter Min Max Tcas Address chip select setup time 5ns Tcah Address chip select hold time 10 ns Terr Ready assertion to read de assertion 10 ns Terh Read High width 24 ns Read data setup time to ready assertion 10 ns Tedrh Read data hold time after read de assertion 8ns 32 ns Tcdrd Read data driving delay 24 ns 355 ns Tewl Write assertion width 40 ns Tcwh Ready assertion to write assertion 16 ns Tcdws Write data setup to write de assertion 10 ns Tcdwh Write data hold time after ready assertion 5ns Tedwd Write data sampling delay 8ns 32 ns Tcyd Ready width in write cycle 24 ns 40 ns Datasheet 150 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 9 intel Transmit Pause Control AC Timing Specification Figure 49 and Table 55 show the pause control AC timing specifications The Pause Control interface operates as an asynchronous interface relative to the main system clock CLK125 There is however a relationship between the TXPAUSEADD bus and the strobe signal TXPAUSEFR Figure 49 Pause Control Interface Timing 151 Table 55 001 010 011 100 110 101 111 TXPAUSEADD 2 0 TxPauseFr XON packet on all ports XOFF Porto XOFF Port1 XOFF Port2 XOFF Port3 Reserved XOFF on all ports
207. erview Diagram 8 4 Note Table 59 Datasheet 10 6 0 Port Select amp Global Registers Per Port Registers Register Map Table 59 through Table 69 Optical Module Registers 0x799 0x79F on page 162 present the IXF1104 MAC memory map details Global control and status registers are used to configure or report on all ports and some registers are replicated on a per port basis All IXF1104 MAC registers are 32 bits MAC Control Registers Port Index Offset Sheet 1 of 2 Register Bit Size Mode Ref Page Offset Station Address Port Index 0x00 0x01 Low 32 R W 163 0x00 Station Address Port Index 0x00 0x01 High 32 R W 163 0x01 Desired Duplex Port Index 0x02 32 R W 163 0x02 FD FC Type Port Index 0x03 32 R W 163 0x03 Reserved 32 R 0x04 Collision Distance Port Index 0x05 32 R W 164 0x05 Collision Threshold Port Index 0x06 32 R W 164 0x06 FC TX Timer Value Port Index 0x07 32 R W 164 0x07 Index 0x08 0x09 32 RW 164 0x08 21 Index 0x08 0x09 32 RW 164 0x09 IPG Receive Time 1 5 Port Index 32 R W 165 0x0A IPG Receive Time 2 Port Index 0x0B 32 R W 165 0x0B IPG Transmit Time Port Index 32 R W 165 0x0C Reserved RO 0x0D Pause Threshold 5 Port Index 32 R W 166 OxOE 1
208. escription Address Type Default ee C ME ee com rece gt Qecupancy ort t RE ges OnoupeneyfOrTXFIFO 8 0000000 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 141 TX FIFO Port Drop Enable 0x63D Bit Name Description Type Default Register Description Independently enables the individual TX FIFOs to drop erroneous 0x0000000f packets 31 4 Reserved Reserved RO 0x000000 0 Disable the TXFIFO from dropping erroneous packets Port 3 Drop 1 Enable the TXFIFO to drop erroneous packets R W 1 0 Disable the TXFIFO from dropping erroneous packets 2 Port Drop 1 Enable the TXFIFO to drop erroneous packets RUN 1 0 Disable the TXFIFO from dropping erroneous packets POET Drop 1 Enable the TXFIFO to drop erroneous packets FN 1 0 Disable the TXFIFO from dropping erroneous packets 0 Port 0 Drop 1 Enable the TXFIFO to drop erroneous packets R W 1 Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 210 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 8 4 8 MDIO Register Overview Table
209. ese limits are exceeded damage to the device will occur Table 44 Undershoot Overshoot Limits Pin Type Undershoot Overshoot 2 5 V CMOS 0 60 V 3 9 V 3 3 V LVTTL 0 60 V 3 9 V 7 1 2 RGMII Electrical Characteristics The signals including MDIO MDC are based on 2 5V CMOS interface voltages as defined by JEDEC EIA JESD8 5 see Table 45 135 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 45 RGMII Power Symbol Parameter Conditions Min Max Units VOH Output High Voltage IOH 1 0 MA Vpp MIN 2 0 VDD 3 V VoL Output Low Voltage loL 1 0 MA Vpp MIN GND 3 0 40 V VIH Input High Voltage VIH gt VIH_MIN Vpp MIN VDD 3 V VIL Input Low Voltage VIL lt VIL MAX MIN 70 V IIH Input High Current Vpp MAX VIN 2 5V 15 uA liL Input Low Current Vpp MAX VIN 0 4V 15 Datasheet 136 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller intel 7 2 SPI3 AC Timing Specifications 7 2 1 Receive Interface Timing Figure 35 and Table 46 illustrate and provide SPI3 receive interface timing information Figure 35 SPI3 Receive Interface Timing RFCLK
210. eserved RO 0 0 19 wext Page 1 Manual control of Next Page software 27 0 14 Reserved Reserved RO 0 0 No remote fault 13 Remote Fault iz Remote faut RO 0 12 Reserved Reserved RO 0 Advertise Asymmetric Pause Direction register bit This register bit is used in conjunction with Pause Register bit 4 10 11 ASM DIR inl RO 1 0 Link partner is not capable of asymmetric pause 1 2 Link partner is capable of asymmetric pause Advertise to link partner that Pause operation is 10 Pause desired IEEE 802 3x Standard RO 0 0 100BASE T4 capability is not available 1 100BASE T4 capability is available The IXF1104 MAC does not support 100BASE T4 9 100BASE T4 but allows this register bit to be set to advertise in RO 0 auto negotiation sequence for 100BASE T4 operation If this capability is desired an external 100BASE T4 transceiver can be switched in 0 DTEis not 100BASE TX full duplex mode 8 100BASE TX capable RO 1 Full Duplex 1 DTEis 100BASE TX full duplex mode capable 0 DTEis not 100BASE TX half duplex mode 7 100BASE TX capable RO 1 Half Duplex 1 DTEis 100BASE TX half duplex mode capable 1 RO Read Only RR Clear on Read W Write R W Read Write Datasheet 184 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 99 Auto Negotiation Advertisement Port Index 0x64 Sheet 2 of 2 Intel
211. eserved Reserved RO 0x000 Auto negotiation complete This bit remains cleared from the time auto negotiation is reset until auto negotiation reaches the LINK OK state It 21 complete remains set until auto negotiation is disabled or RO 0 restarted This bit is only valid if auto negotiation is enabled 0 Loss of synchronization 20 Rx Sync 1 2 Bit synchronization The bit remains Low until RO 0 the register is read 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 169 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 88 RX Config Word Port Index 0x16 Sheet 2 of 2 Bit Name Description Default 0 Receiving idle data stream 18 RX Config 1 Receiving C ordered sets RO 0 RxConfigWord has changed since last read 1 RxConfigWord has not changed since last 18 Config Changed read 9 9 R 0 This bit remains High until the register is read 0 Have not received an invalid symbol 17 Invalid Word 1 Have received an invalid symbol RO 0 This bit remains High until the register is read 0 Deviceis not receiving idle characters carrier sense is true 18 Carrier Sense 1 Device is receiving idle characters carrier RO 0 sense is fa
212. essor Interface Register Addr 0x508 164 Modified Table 84 LED Flash Rate Register Addr 0x50A 169 Modified Table 93 RX FIFO Errored Frame Drop Enable Register Addr 0x59F 170 Modified Table 96 RX FIFO Loopback Enable for Ports 0 3 Register Addr 0x5B2 171 Added Table 98 RX FIFO Jumbo Packet Size 0 3 Register Addr 0x5B8 0 5 172 Added Table 99 RX FIFO Jumbo Packet Size Port 0 Register Bit Definitions Addr 0x5B8 172 Added Table 100 RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions Addr 0x5B9 172 Added Table 101 RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions Addr 0 5 172 Added Table 102 RX FIFO Jumbo Packet Size Port Register Bit Definitions Addr 0 5 178 Modified Table 110 TX FIFO Number of Dropped Packets Register Ports 0 3 Addr 0x625 0x629 177 Modified Table 108 TX FIFO Port Reset Register Addr 0x620 177 Modified Table 108 TX FIFO Port Reset Register Addr 0x620 177 Modified Table 107 Loop RX Data to TX FIFO Register Ports 0 Addr 0x61 F 179 Added Table 111 TX FIFO Occupancy Counter for Ports 0 3 Registers Addr 0x62D 0x630 180 Added Table 112 TX FIFO Port Drop Enable Register Addr 0x63D 181 Modified Table 114 MDI Single Command Register Addr 0x680 186
213. et Match This feature is enabled when bit 0 of the RX Packet Filter Control Index 0x19 1 Any frame received in this mode that does not match the Station Address MAC address is marked by the IXF1104 MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3 Receive Configuration 0x701 on page 215 When bit 0 of the Packet Filter Control Port Index 0x19 0 all unicast frames are sent out the SPI3 interface The VLAN filter overrides the unicast filter Therefore a VLAN frame cannot be filtered based on the unicast address Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Data Note sheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 5 1 1 3 2 Filter on Multicast Packet Match This feature is enabled when bit 1 of the Packet Filter Control Port Index 0x19 1 Any frame received in this mode that does not match the Port Multicast Address reserved multicast address recognized by IXF1104 MAC is marked by the MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3
214. et payload on SPI3 and in network processor memories Remove CRC from RX frames Append CRC to transmitted frames Performance Monitoring and Diagnostics Loopback modes Detection of runt and overly large packets Cyclic Redundancy Check CRC calculation and error detection RMON statistics for dropped packets packets with errors etc Compliant with IEEE Spec 802 3x standard for flow control Receive and execute PAUSE Command Frames Support for non standard packet sizes up to 10 KB including loss less flow control Note The IXF1104 MAC does not support 10 100 Mbps operation when configured in GMII mode The IXF1104 MAC is fully integrated designed for use with Ethernet 802 3 frame types and compliant to all of the IEEE 802 3 MAC requirements The IXF1104 MAC adds preamble and Start of Frame Delimiter SFD to all frames sent to it transmit path and removes preamble and SFD on all frames received by it receive path A CRC check is also applied to all transmit and receive packets CRC is optionally appended to transmit Datasheet 66 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 1 1 1 Note 5 1 1 2 5 1 1 3 Note 67 packets CRC is removed optionally from receive packets after validation and is not forwarded to SPI3 Packets with a bad CRC are marked counted in the statistics bl
215. et to 0 Soft Reset 0x505 for the ports being changed 10 De assert set to 0 TX FIFO Port Reset 0x620 for the ports being changed 11 Wait 1 to 2 us 12 Set the Diverse Config Write Index 0x18 to the appropriate value as follows Datasheet a Copper mode Write the reserved bits to the default value 130 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel Enable packet padding appending on transmitted packets in bits 6 and 7 as needed Set bit 5 to 0 0 b Fiber Mode Write the reserved bits to the default value Enable Packet padding and CRC Appending on transmitted packets in bits 6 and 7 as needed Set bit 5 to 1 to enable auto negotiation Set bit 5 to 0 to enable forced mode operation 13 Assert set to 1 Port Enable 0x500 14 Wait 1 to 2 us 15 Perform additional device configurations as needed 6 2 Disable and Enable Port Sequences Intel recommends the following sequences to disable and enable individual ports and for dropped links When a link is dropped Intel recommends the port be completely reset and flushed to remove packet fragments that may interfere with the auto negotiation process on link recovery 6 2 1 Disable Port Sequence Use the following sequence to disable an individual port 1 Disable the port using MAC port
216. ets transmitted including bad packets that were 65 127 octets in length Incremented for tagged packets with a length of 65 127 bytes including tag field Port_Index 0x46 0x00000000 Txpkts128to255Octets The total number of packets transmitted including bad packets that were 128 255 octets in length Incremented for tagged packets with a length of 128 255 bytes including tag field Port Index 0x47 0x00000000 Txpkts256to5110Octets The total number of packets transmitted including bad packets that were 256 511 octets in length Incremented for tagged packets with a length of 256 511 bytes including tag field Port Index 0x48 0x00000000 Txpkts512to1023Octets The total number of packets transmitted including bad packets that were 512 1023 octets in length Incremented for tagged packets with a length of 512 1023 bytes including tag field Port Index 0x49 0x00000000 Txpkts1024to1518Octets The total number of packets transmitted including bad packets that were 1024 1518 octets in length Incremented for tagged packet with a length between 1024 1522 including the tag Port Index Ox4A 0x00000000 Txpkts1519toMaxOctets The total number of packets transmitted including bad packets that were greater than 1518 octets in length Incremented for tagged packet with a length between 1523 max fame size including the tag Port Index 0x4B 0x00000000
217. f 00 01 Length Type field of 88 08 DA matching the unique multicast address 01 80 C2 00 00 01 XOFF A PAUSE frame informs the link partner to halt transmission for a specified length of time The PauseLength octets specify the duration of the no transmit period If this time is greater than Zero the link partner must stop sending any further packets until this time has elapsed This is referred to as XOFF XON The MAC continues to transmit PAUSE frames with the specified Pause Length as long as the FIFO level exceeds the threshold If the FIFO level falls below the threshold before the Pause Length time expires the MAC sends another PAUSE frame with the Pause Length time specified as zero This is referred to as XON and informs the link partner to resume normal transmission of packets 5 1 2 1 2 Pause Settings The MAC must send PAUSE frames repeatedly to maintain the link partner in a Pause state The following two inter related variables control this process Pause Length is the amount of time measured in multiples of 512 bit times that the MAC requests the link partner to halt transmission for Pause Threshold is the amount of time measured in multiples of 512 bit times prior to the expiration of the Pause Length that the MAC transmits another Pause frame to maintain the link partner in the pause state The transmitted Pause Length in the IXF1104 MAC is set by the FC TX Timer Value Port Index 0x07 on page 164 T
218. f the optical modules PC CLK runs continuously when enabled PC Enable 01h0 The Serial Data PC DATA 3 0 signals one per port are bi directional for serial data transfer These signals are open drain Datasheet 112 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 7 3 5 5 7 3 6 Port Protocol Operation Clock and Data Transitions The C DATA is normally pulled High with an extra device Data on the PC DATA pin changes only during the PC CLK Low time periods see Figure 25 Data changes during PC High periods indicate a start or stop condition Figure 25 Data Validity Timing PC Data DATA STABLE DATA STABLE DATA CHANGE 5 7 3 6 1 Start Condition A High to Low transition of C DATA with PC CLK High is a start condition that must precede any other command see Figure 26 5 7 3 6 2 Stop Condition Low to High transition of the PC DATA with PC High is a stop condition After a Read sequence the stop command places the E7PROM and the optical module in a standby power mode see Figure 26 Figure 26 Start and Stop Definition Timing 113 Data DEP PC Data N START STOP Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 tel Intel IXF1104 4 Port Gigabit Eth
219. fering FIFO ierit cede intl red etta Y Y ae aed Ya 71 8 Ethernet Frame Format uisa ues eee ubera Exe aa Esa range pepe 71 9 PAUSE Fraime 72 10 Transmit Pause Control 74 11 Transmit Logical nnne 85 12 MPHY Receive Logical Timing 86 13 MPHY 32 Bit Interface teret vete vd Pee e adve ete Eu Foe 86 14 Transmit Logical Timing sees 88 15 SPHY Receive Logical Timing docete ed Lees need E rete 89 16 SPHY Connection for Two Intel IXF1104 MAC Ports 8 Bit 1 90 17 MAC GMI Interconnect uu cioe eerte 94 iacu 96 n 98 20 CT LIBS RAVI OM wise 98 21 Management Frame Structure Single Frame Format 101 22 1 cime T 102 23 SerDes Receiver Jitter 106 24 C Random Read 111 25 Data Validity s us RUE Dr AE MEER 113 26 Start and Stop Definition
220. fies up to 512 8 bit registers that are accessible in each optical module The Optical Module Interface is read only and supports either sequential or random access to the 8 bit parameters The maximum clock rate of the interface is 100 kHz address select signals on the internal are tied Low to give a device address equal to zero 00h Several PHY vendors may offer copper CAT5 based SFP optical compliant modules To program the internal configuration registers of these modules the IXF1104 MAC interface needs to provide the capability to write data to the SFP modules The IXF1104 MAC IC interface is designed to allow individual writes of byte wide data to the SPP The specific interface in the IXF1104 MAC supports only a subset of the full PC interface and only the features required to support the Optical Module Interfaces are implemented This leads to the following support features Single PC CLK pin connected to all optical modules and implemented to save unnecessary signals use Four per port PC DATA signals PC Data 3 0 are required because of the optical module requirement that all modules must be addressed as OOh The interface has both read and write functionality Due to the single internal optical module controller only one optical module may be accessed at any one time Each access contains a single register Read Since these register accesses will most likely be done during power up or discovery
221. flow control is automatically de asserted on the SPI3 interface to allow further data to be sent by the switch fabric to the IXF1104 MAC 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write TX FIFO Low Watermark Port 0 TX FIFO Low Watermark Port 1 TX FIFO Low Watermark Port 2 TX FIFO Low Watermark Port 3 Datasheet 204 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 134 TX FIFO MAC Threshold Register Ports 0 3 0x614 0x617 Intel Name Description Address Default TX FIFO MAC Threshold Port 0 MAC threshold for TX FIFO Port 0 The default value of OX1BE represents 446 8 byte locations This equates to 3568 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX FIFO reaches this threshold data is forwarded to the MAC core and line side interfaces for onward transmission By setting the threshold to an appropriate value the user can configure the TX FIFO to operate in a cut through mode rather than the default store and forward operation mode 0x614 R W 0x000001BE TX FIFO MAC Threshold Port 1 MAC threshold for TX FIFO Port 1 The default value of OX1BE represents 446 8 byte locations This
222. frame 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 85 FC Back Pressure Length Port_Index 0x13 duplex mode Flow control in the receive path is executed by deliberately colliding the incoming packets in half duplex mode Register bits 5 0 are used alone Name Description Address Type Default This register sets number the byte cycles for which the collision has to be applied The 6 bit configuration holds the value in bytes which applies to the minimum be length duration of back pressure in half s R W 0x0000000C 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 168 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 86 Short Runts Threshold Port Index 0x14 Intel Name Description Address Default Short Runts Threshold The 5 bit configuration holds the value in bytes which applies to the threshold in determining between runts and short The bits 4 0 of this register are alone used A received packet is reported as a short packet when the length excluding Preamble and SFD is less than this value A received packet is report
223. ged SerDes analog power to 133 AVDD1P8 2 AVDD2P5 2 changed PLL1 VDDA and PLL2 to AVDD1P8 1 changed PLL3 VDDA to AVDD2P5 1 134 Modified Table 42 SerDes Transmit Characteristics included SerDes power driver level information 142 Modified Table 49 GMII 1000BASE T Transmit Signal Parameters changed Min values for t1 and t2 143 Modified Table 50 GMII 1000BASE T Receive Signal Parameters changed Min values for t1 and t2 146 Replaced old MDIO Timing diagram and table with Figure 43 MDIO Write Timing Diagram Figure 44 Read Timing Diagram and Table 52 MDIO Timing Parameters Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Contents Revision Number 007 Revision Date March 24 2004 Sheet 4 of 5 Page Description 156 Broke up the old Register Map into Table 59 MAC Control Registers Port Index Offset Table 60 MAC RX Statistics Registers Port Index Offset Table 61 TX Statistics Registers Port Index Offset Table 62 PHY Autoscan Registers Port Index Offset Table 63 Global Status and Configuration Registers 0x500 OX50C Table 64 RX FIFO Registers 0x580 0 5 Table 65 TX FIFO Registers 0x600 Ox63E Table 66 MDIO Registers 0x680 0x683 Table 67 SPI3 Registers 0x700 0x716 Table 68 SerDes Registers 0x780 0x798 and Table 69 Opti
224. guration 0x700 Sheet 2 of 3 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Bit Name Description Default 16 Dat prtyer drp Port O SPHY MPHY Mode Indicates whether to drop packets with data parity error for port O 0 Do not drop packets with data parity error default 1 Drop packets with data parity error R W 15 8 Reserved Write as 0 ignore on Read R W 00000000 Tx_parity_sense Port 3 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 3 0 Odd Parity 1 Even Parity MPHY Mode NA R W Tx_parity_sense Port 2 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 2 0 Odd Parity 12 Even Parity MPHY Mode NA R W Tx_parity_sense Port 1 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 1 0 Odd Parity 1 Even Parity MPHY Mode NA R W Tx_parity_sense Port 0 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 0 0 Odd Parity 1 Even Parity MPHY Mode Indicates the parity sense to check the parity on TDAT bus for all ports 0 Odd Parity 12 Even Parity R W Tx_port_enable Port 3 SPHY Mode 0 Disables the selected SPISTX port 3 1 Enables the selected TX port MPHY Mode 0 Disables the selected SPI3 TX port 1 Enables the selected SPI
225. guration for a given port the relevant per port registers must be configured correctly by the user The Table 59 through Table 69 also contain registers that affect the operation of all ports such as the SPI3 interface configuration See Section 8 0 Register Set on page 155 for a complete description of IXF1104 MAC configuration and status registers The Register Maps Table 59 through Table 69 present a summary of important configuration registers The initialization sequence provided in Section 6 1 Change Port Mode Initialization Sequence on page 130 must be followed for proper configuration of the IXF1104 MAC Key Configuration Registers The following key registers select the operational mode of a given port Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 24 Operational Mode Configuration Registers 5 1 4 Datasheet Register Name Register Address Description Desired Duplex Port Index 0x02 0x002 Port 0 0x082 Port 1 0x102 Port 2 0x182 Port 3 The Desired Duplex Port Index 0x02 on page 163 defines whether a port is to be configured for full duplex or half duplex operation NOTE Half duplex operation is only valid for 10 100 speeds where the RGMII line interface has been selected The MAC IF Mode and RGMII Speed Port Index 0x10 on page 167 determi
226. he IXF1104 MAC pushes data to the link layer device For the transmit interface the packet available status granularity is byte based 5 2 2 9 1 RX SPI3 Flow Control In the receive direction when the IXF1104 MAC has stored an end of packet a complete small packet or the end of a larger packet or some predefined number of bytes in its receive FIFO it sends the in band address followed by FIFO data to the link layer device in MPHY mode The data on the interface bus is marked with the valid signal RVAL asserted The network processor device can pause the data flow by de asserting the Receive Read Enable RENB signal RENB 0 3 RENB 0 3 controls the flow of data from the IXF1104 MAC RX FIFOs In SPHY mode there is a dedicated RENB for each port In MPHY mode RENB 0 is used as the global signal covering all ports When RENB is sampled Low the network processor can accept data A read is performed from the RX FIFO and RDAT RPRTY RMOD 1 0 RSOP REOP RERR RSX signals are updated on the following rising edge of RFCLK RENB can be asserted High by the Network Processor at any time if it is unable to accept any more data When the RENB is sampled High by the IXF1104 MAC a read of the RX FIFO is not performed and the RDAT RPRTY RMOD 1 0 RSOP REOP RERR RSX and RVAL signals remain unchanged on the following rising edge of RFCLK 5 2 2 9 2 TX SPI3 Flow Control In the transmit direction when the IXF1104 MAC
227. he IXF1104 PAUSE frame transmission interval is set by the Pause Threshold Index OxOE on page 166 Datasheet 72 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel Note Note Note 73 5 1 2 1 3 Response to Received PAUSE Command Frames When Flow Control is enabled in the receive direction bit 0 in the FC Enable Index 12 the IXF1104 responds to PAUSE Command frames received from the link partner as follows 1 The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame addressed to the Multicast Address 01 80 C2 00 00 01 as specified in IEEE 802 3 Annex 31B or has a Destinations Address matching the address programmed in the Station Address Index 0x00 40x01 2 If the PAUSE frame is valid the transmit side of the IXF1104 pauses for the required number of PAUSE Quanta as specified in IEEE 802 3 Clause 31 3 PAUSE does not begin until completion of the frame currently being transmitted The IXF1104 response to valid received PAUSE frames is independent of the PAUSE frame filter settings Refer to Section 5 1 1 3 5 Filter Pause Packets on page 68 for additional details Pause packets are not filtered if flow control is disabled in bit 0 of the FC Enable Index 0x12 5 1 2 1 4 Half Duplex Operation Transm
228. he LongErrors and VeryLongErrors counters is as follows VeryLongErrors counts frames that are 2 maxframesize dependent upon where maxframesize is set If maxframesize sets greater than half of the available count in RxOctetsBad 2 14 1 VeryLongErrors is never incremented but LongErrors is incremented This is due to a limitation in the counter size which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2 14 1 3 This register is relevant only when configured for copper operation 4 This register is relevant only when configured for fiber operation line side interface is SerDes Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 93 Statistics Port Index 0x20 0x39 Sheet 3 of 4 Name Description Address Default RxAlignErrors Frames with a legal frame size but containing less than eight additional bits This occurs when the frame is not byte aligned The CRC of the frame is wrong when the additional bits are stripped If the CRC is OK then the frame is not counted but treated as an OK frame This counter increments in 10 Mbps or 100 Mbps RGMII mode only NOTE This counter increments in 10 or 100 Mbps RGMII mode only Port Index Ox2F 0x00000000 RxLongErrors Frames bigger than the maximum allowed with
229. ical Module and 2 AC Timing Specification 147 _1 Interface WE EORR 147 7 8 CPU AC Timing 149 7 8 1 Interface Read Cycle AC Timing seen 149 7 8 2 Interface Write Cycle AC 149 7 9 Transmit Pause Control AC Timing 5 151 7 10 JTAG AC Timing Specification 152 7 11 System AC Timing 5 153 7 12 LED AC Timing 5 154 80 Register Sit 155 8 1 Document Stuttu Cm 155 8 2 Graphical 155 8 39 Per Port Heglsters Lo dg iem EFE 156 E MEME c 156 8 4 1 Control 163 8 4 2 MAC RX Statistics Register 174 8 4 3 MAC TX Statistics Register Overview 178 8 4 4 PHY Autoscan Registers 181 8 4 5 Global Status and Configuration Register Overview 188 8 4 6 RX FIFO Register Overview 193 847 TX FIFO Register 203 8 4 8 Register 211 8 4 9 Reg
230. ied Figure 9 PAUSE Frame Format changed Preamble byte count to 7 bytes 85 Modified Figure 11 MPHY Transmit Logical Timing updated TDAT 31 0 86 Modified Figure 12 MPHY Receive Logical Timing updated RDAT 31 0 88 Modified Figure 14 SPHY Transmit Logical Timing updated TDAT 7 0 89 Modified Figure 15 SPHY Receive Logical Timing updated RDAT 7 0 and RPRTY 121 Modified Figure 31 Read Timing Diagram Asynchronous Interface changed uPx ADD 12 0 to uPx ADD 10 0 125 Added paragraphs two and three under Section 5 11 Loopback Modes 129 Changed 3 3 V CMOS to 2 5 V CMOS under Section 5 12 5 JTAG Clock on page 129 131 Added Section 6 2 Disable and Enable Port Sequences 136 Modified Table 45 Power changed Voy minimum conditions to and changed Vy value to Vpp 3 138 Modified Table 46 SPI3 Receive Interface Signal Parameters changed RFCLK duty cycle to 45 min and 55 max Changed Min for RFCLK frequency to 90 140 Modified Table 47 Transmit Interface Signal Parameters changed duty cycle to 45 min and 55 max 146 Changed MDC to MDIO Output delay max for t3 for 2 5 MHz from 200 to 300 in Table 52 MDIO Timing Parameters on page 146 12 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Content
231. incremented and the RxERR flag is asserted on the SPI3 receive interface Jumbo frames also impact flow control The maximum frame size needs to be taken into account when determining the FIFO watermarks The current transmission must be completed before a Pause frame is transmitted needed when the receiver FIFO High watermark is exceeded If the current transmission is a jumbo frame the delay may be significant and increase data loss due to insufficient available FIFO space Loss less Flow Control The IXF1104 MAC supports loss less flow control when the size of a Jumbo packet is restricted to 9 6 k bytes If this condition is met the IXF1104 MAC has sufficient memory resources allocated to each MAC port to ensure that if both the IXF1104 MAC and link partner are required to send Pause packets simultaneously during jumbo packet transfers across a medium of five kilometers of fiber no packet data should be lost due to FIFO overflows Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 1 7 5 1 7 1 Datasheet Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Packet Buffer Dimensions TX and RX FIFO Operation 5 1 7 1 1 TX FIFO The IXF1104 MAC TX FIFOs are implemented with 10 KB for each channel This provides enough space for at least one maximum size 10 KB packet per port storage and ensures that no under run conditions occur assuming that the sending device can suppl
232. ing signals RXD6 2 V19 have multiplexed functions when a port RXD5 2 v20 is configured in fiber mode RXD4_2 W22 RXD4_n MOD_DEF_0 3 RXD3_2 Y23 RXD5_n TX_FAULT_0 3 RXD2_2 Y22 RXD1 2 Y21 RXD6 n RX LOS 03 RXDO 2 Y20 RXD7 3 T19 RXD6 3 T18 RXD5 3 T17 RXD4 3 T16 RXD3 3 W18 RXD2 3 Y19 RXD1 3 Y18 RXDO 3 Y17 RX DV V5 Receive Data Valid RX DV 1 AB11 Input 25V RX DV indicates that valid data is RX DV 2 Y24 CMOS being driven on Receive Data RX DV 3 V18 RXD 7 0 n RX ER 0 WS Receive Error RX ER 1 Y12 2 5V EN 2 AA22 Input CMOS RX ER indicates an error in Receive RX ER 3 U20 Data RXD 7 0 n aes 25V Carrier Sense CRS 2 AB15 Input CMOS CRS indicates the PHY device has CRS 3 AC16 detected a carrier Receiver Reference Clock RXC 0 V4 RXC operates at RXC_1 Input 25V 125 MHz for 1 Gigabit RXC 2 AA24 CMOS RXC_3 V23 NOTE Shares the same balls as RXC on the RGMII interface NOTE Refer to the RGMII interface for shared data and clock signals 49 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 6 RGMII Interface Signal Descriptions Sheet 1 of 2 Ball E Signal Name Designator Type Standard Description TXC 0 1 Source Synchronous Transmit Clock TXC 1 AD7 2 5V 2 AC20 Output CMOS This clock is supplied synchronous to the transmit TXC 3
233. interrupt output to signal an RX LOS condition Open 2 5V NOTE A pull istor is required RX LOS INT P19 Drain n externa pu up resistor is require Output CMOS for proper operation NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 9 Optical Module Interface Signal Descriptions Sheet 2 of 2 Signal Name De a r Type Standard Description Transmitter Fault Interrupt TX FAULT INT is an open drain interrupt output that signals a TX FAULT condition Open TX FAULT INT P23 Bin 2 5V NOTE An external pull up resistor is Output CMOS required for proper operation NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output Module Definition Interrupt MOD_DEF_INT is an open drain interrupt output that signals a MOD_DEF condition Open MOD DEF INT N22 Brain 25V NOTE An external pull up resistor is PI Output CMOS required for proper operation NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output 2 25V is the clock used for the 2 bus L23 Output CMOS interface 2 Data Bus DATA 0 3 are the data I Os for the 2 bus interface
234. io Regi RO 1 0 Link partner is not capable of asymmetric pause 1 Link partner is capable of asymmetric pause Link partner wants to utilize Pause Operation as 10 Link Partner Pause Gefined in IEEE 802 3x Standard RO 0 0 Link partner is not 100BASE T4 capable 1 Link partner is 100 5 4 capable RO 9 1 RO Read Only RR Clear on Read W Write R W Read Write 185 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 100 Auto Negotiation Link Partner Base Page Ability Port Index 0x65 Sheet 2 of 2 Bit Name Description Default 0 Link partner is not 100BASE TX full duplex 8 100BASE TX mode capable RO 1 Full Duplex 1 Link partner is 100BASE TX full duplex mode capable 0 Link partner is not 100BASE TX half duplex 7 100BASE TX mode capable RO 1 Half Duplex 1 Link partner is 100BASE TX half duplex mode capable 0 Link partner is not 10BASE T full duplex 6 10BASE T mode capable RO 1 Full Duplex 1 Link partner is 10BASE T full duplex mode capable 0 Link partner is not 10BASE T half duplex 5 10BASE T mode capable RO 1 Half Duplex 1 Link partner is 10BASE T half duplex mode capable 00001 IEEE 802 3 00010 IEEE 802 9 ISLAN 16T 00000 Reserved for future auto negotiation development 4
235. ion This regist er gives the configuration related to the receiver 0x00000F80 31 28 Reserved Reserved RO 0x0 27 B2B PAUSE Port 3 SPHY Mode Indicates the number of pause cycles to be introduced between back to back transfers for port 3 0 Zero pause cycles 1 2 Two pause cycles MPHY Mode NA R W 26 B2B_PAUSE Port 2 SPHY Mode Indicates the number of pause cycles to be introduced between back to back transfers for port 2 0 Zero pause cycles 1 Two pause cycles MPHY Mode NA R W 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 215 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 147 SPI3 Receive Configuration 0x701 Continued Sheet 2 of 4 Bit Name Description Default 25 B2B PAUSE Port 1 SPHY Mode Indicates the number of pause cycles to be introduced between back to back transfers for port 1 0 Zero pause cycles 1 Two pause cycles MPHY Mode NA R W 24 B2B_PAUSE Port 0 SPHY Mode Indicates the number of pause cycles to be introduced between back to back transfers for port 0 0 Zero pause cycles 1 Two pause cycles MPHY Mode Indicates the number of pause cycles
236. ion History Revision Number 009 Revision Date 27 Oct 2005 Page Description 71 Modified Figure 8 Ethernet Frame Format changed Preamble byte count to 7 bytes 136 Section 45 RGMII Power changed Vec to Vpp in 111 110 Added bullet to Section 5 7 3 2 Module Configuration Interface The 2 interface only supports random single byte reads and does not guarantee coherency when reading two byte registers 227 Replaced Figure 57 FC PBGA Package and Bottom Views on page 227 215 Modified Table 147 SPI3 Receive Configuration 0x701 222 Modified Table 154 Optical Module Control Ports 0 3 0x79A changed default values 223 Modified Table 155 I C Control Ports 0 3 0x79B 249 Modified Table 208 42 Data Ports 0 9 0x79F changed address from 0x79C to 0x79F 229 Added Section 9 3 3 Top Label Marking Example 230 Modifed Table 157 Product Information and Figure 60 Ordering Information Sample under Section 10 0 Product Ordering Information Revision Number 008 Revision Date August 1 2005 Sheet 1 of 2 Page Description Added 552 ball Ceramic Ball Grid Array CBGA compliant with RoHS and Product Ordering Number information 55 Modified Table 12 JTAG Interface Signal Descriptions changed Standard to 3 3 V LVTTL from 2 5 V CMOS 72 Modif
237. ions and Section 4 1 2 Register Address Conventions and added enhanced material under headings 58 Added new Section 4 5 Multiplexed Ball Connections with Table 16 Line Side Interface Multiplexed Balls and Table 17 SPI3 MPHY SPHY Interface 63 Modified Section 4 7 Power Supply Sequencing changed language under this section and added Section 4 7 1 Power Up Sequence and Section 4 7 2 Power Down Sequence 63 Modified Table 5 Power Supply Sequencing deleted 3 3 V Supplies Stable changed Apply 1 8 V to VDD AVDD1P8 1 and AVDD1P8 2 changed Apply 2 5 V to AVDD2P5 1 and AVDD2P5 2 61 Modified Table 18 Definition of Output and Bi directional Balls During Hardware Reset changed comments for Optical Modules 64 Modified Table 20 Pull Up Pull Down and Unused Ball Guidelines changed TRST to pull down added UPX_RDY_L I C DATA 3 0 and TX DISABLE 3 0 64 Added new Section 4 9 Analog Power Filtering including Figure 6 Analog Power Supply Filter Network on page 65 and Table 21 Analog Power Balls on page 65 66 Modified edited text under Section 5 1 Media Access Controller MAC rearranged and created new bullets 67 Modified first paragraph under Section 5 1 1 1 Padding of Undersized Frames on Transmit 67 Modified entire Section 5 1 1 3 Filtering of Receive Packets 68 Added new Section 5 1 1 3 6 Filter CRC Error Pa
238. is committed when bytes 3 2 are written The complete address for write is ignored except for the write which causes the commit operation 120 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 9 1 Functional Description 5 9 1 1 Read Access Read access involves the following Detect assertion of asynchronous Read control signal and latch address Generate internal Read strobe Drive valid data onto processor bus Assert asynchronous Ready signal for required length of time Figure 31 shows the timing of the asynchronous interface for Read access Figure 31 Read Timing Diagram Asynchronous Interface Ludi k Tos uPx ADD 10 0 V 14 P4 I uPx_CsN K ToaR gt i Y uPx M N IA VA TCRH MN C Y uPx Data 31 0 TcDRH gt Px RdyN T 1 lt TODRD gt B5103 01 5 9 1 2 Write Access Write process involves the following Detect assertion of asynchronous Write control signal and latch address Detect de assertion of asynchronous Write control signal and latch data Generate internal Write strobe Assert asynch
239. is document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2005 Intel Corporation 2 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ntel 8 Contents Contents 1 0 lei EE aee eere 20 1 4 What You Will Find in This 20 1 2 Related Documents niter rere 20 2 0 General Description oe 21 3 0 Assignments and Ball List 1 2 2121 212 2 2 1 23 3 1 23 3 2 Ball List Fables eodein E et nde eoe co i E Edda ea du 24 3 2 1 Balls Listed in Alphabetic Order by Signal Name 24 3 2 2 Balls Listed in Alphabetic Order by Ball Location 30 4 0 Ball Assignments and Signal Descriptions 1 2 37 4 1 Naming COnVentlon seei dace M 37 4 1 1 Signal Name Conventions 37 4 1 2 Register
240. is not used by the PHY device NOTE Only TDAT 1 0 are relevant all other bits are Don t Care 4 x 8 Single PHY mode TSX is not used TADR 1 0 Transmit PHY Address TADR1 TADR1 A12 Input 3 3 V The value on TADR 1 0 selects one of the TADRO TADRO 11 LVTTL PHY ports that drives the PTPA signal after the rising edge of TFCLK TSX NA E1 Input 41 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 3 Interface Signal Descriptions Sheet 4 of 8 Signal Name Ball Designator Type Standard Description MPHY SPHY DTPA 0 3 Direct Transmit Packet Available A direct status indication for transmit FIFOs of ports 0 3 When High DTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark When the High watermark is crossed DTPA transitions Low to indicate that the TX FIFO is almost full It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low TELA B E 33V watermark At this point DTPA transitions DTPA 2 DTPA 2 A9 Output LVTTL High to indicate that the programmed DTPA 3 DTPA 3 J7 of bytes are now available for data E transfers NOTE For more information see Table 132 TX FIFO High Watermark Ports 0 3 0x600 0x603 on page 203 and Table 133 TX FIFO Low Watermark Register Ports 0
241. isted by ascending address in the table Document Structure The following sections are structured to provide a general overview of the register map Later sections provide detailed descriptions of each register segment or bit registers are accessed and addressed as 32 bit doublewords When accessed using 8 or 16 bit accesses the CPU interface packs or unpacks the partial accesses into a 32 bit register value Graphical Representation Figure 53 represents an overview of the IXF1104 MAC global control status registers that are used to configure or report on all ports All register locations shown in Figure 53 represent a 32 bit double word Figure 53 Memory Overview Diagram 155 Ox7FF Global Configuration RX Block Configuration TX Block Configuration 0x500 0x480 0x400 0x380 0x300 0x280 0x200 0x180 0x100 0x080 0x000 B0744 01 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 8 3 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Per Port Registers Section 8 4 covers all of the registers that are replicated in each port of the IXF1104 MAC These registers perform an identical function in each port The address vector for the IXF1104 MAC is 11 bits wide This allows for 7 bits of port specific access and a 4 bit vector to address each port and all global registers The address format is shown in Figure 54 Figure 54 Register Ov
242. ister 213 8 4 10 SerDes Register 220 8 4 11 Optical Module Register 222 6 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ntel 8 Contents 9 0 Mechanical 5 224 Qed OVERVIOW 224 ERR 224 9 2 Package aed 224 93 Information 225 9 3 1 CBGA Package Diagrams sss nennen nennen 225 9 3 2 Flip Chip Plastic Ball Grid Array Package 227 9 3 8 Top Label Marking 229 10 0 Product Ordering Information 230 Figures 1 Block DiaQraim iscec eis ree ci IR EUR ER e eA UE ee eb ERE Ree cena 21 2 reto ene ciere nr the Lr Rue ke Rue ka Rak ue ka ERR 22 3 552 Ball CBGA Assignments Top 23 4 Interface Signals oae eee ite 38 5 Power Supply Sequencing E 63 6 Analog Power Supply Filter Network 65 7 Packet But
243. it flow control is implemented only in half duplex operation Upon entering the flow control state the MAC generates a collision for all subsequent receive packets until exiting the flow control state Any receive packet in progress when the MAC enters the flow control state will not be collided with but could be lost due if there is insufficient FIFO depth to complete packet reception Bit 2 of the FC Enable Port_Index 0x12 enables the transmit flow control function 5 1 2 1 5 Transmit Pause Control Interface The Transmit Pause Control interface allows an external device to trigger the generation of pause frames The Transmit Pause Control interface is completely asynchronous It consists of three address signals TXPAUSEADD 2 0 and a strobe signal TXPAUSEFR The required address for this interface operation is placed the TXPAUSEADDJ 2 0 signals and the TXPAUSEFR is pulsed High and returned Low Refer to Figure 10 Transmit Pause Control Interface on page 74 and Table 55 Transmit Pause Control Interface Timing Parameters on page 151 Table 23 shows the valid decodes for TXPAUSEADD 2 0 signals Figure 10 illustrates the transmit pause control interface Flow control must be enabled in the Enable Port Index 0x12 for Transmit Pause Control interface operation There are two additional decodes provided that allow the user to generate either an XOFF frame or XON frame from all ports simultaneously The
244. l Module Interface Signal 53 10 MDIO Interface Signal 54 11 LED Interface Signal 101 ener nnne 55 12 JTAG Interface Signal 55 13 System Interface Signal 11 55 14 Power Supply Signal 56 15 Ball Usage are ce eaae E aged 57 16 Line Side Interface Multiplexed 58 17 SPIS MPHY SPHY lnterface eiii eate e tte e nhe erneut nena sante ku dnte X oda e 59 18 Definition of Output and Bi directional Balls During Hardware 61 19 Power Supply Sequencing 64 20 Pull Up Pull Down and Unused Ball Guidelines eene 64 21 Analog Power Balls ee a edu s esu 65 22 CRC Errored Packets Drop Enable 69 23 Valid Decodes for 2 2 74 24 Operational Mode Configuration Registers 76 8 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ntel 8 Contents 25 RMON Additional Statistics cesis k
245. lash Rate 0x50A Intel Bit Name Description Default Register Description Global selection of LED flash rate 0x00000000 31 3 Reserved Reserved RO 0x00000000 2 0 LED Flash Rate Control 000 2100 ms flash rate 001 2200 ms flash rate 010 2300 ms flash rate 011 400 ms flash rate 100 500 ms flash rate 101 Reserved 110 Reserved 111 Reserved R W 000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 111 LED Fault Disable 0x50B Bit Name Description Default Description Per port fault disable Disables the LED flashing for local or remote 0x00000000 31 4 Reserved Reserved RO 0x0000000 Port 3 LED Port 3 Fault 3 Control 0 Fault enabled R W 0 1 Fault disabled LED Port 2 Fault 2 Control 0 Fault enabled R W 0 1 Fault disabled LED Port 1 Fault Forti u 1 Control 0 Fault enabled R W 0 1 Fault disabled Port 0 LED Port 0 Fault 0 Control 0 Fault enabled R W 0 1 Fault disabled 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 191 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Etherne
246. lease contact your field sales representative for detailed information on the FC PBGA package Datasheet 230 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 231 Figure 60 Ordering Information Sample HF IXF 1104 Product Revision xn 2 Alphanumeric characters Temperature Range A Ambient 0 55 C C Commercial 0 70 C E Extended 40 85 C Internal Package Designator L LQFP K HSBGA BGA with heat slug Product Code XXxxx 3 5 Digit alphanumeric IXA Product Prefix LXT PHY layer device IXE Switching engine IXF Formatting device MAC Framer IXP Network processor Intel Package Designator Pb Free Package Leaded Wi LQFP DJ BJ LQFP FA JA TQFP FA EL TPBGA FL EL PBGA FL PR BGA FY PR PBGA Fy LU PBGA GD EW BGA GW WB HQFP HB WD PQFP HD WE CBGA HF WG QFN HG JP FCBGA HL RU BGA Hz Qu KU UB QFN LB EE PLCC NL EE PLCC NS EP SSOP PA Uc PDIP PD PC RC EG PQFP SL EG HGFP SL EG SL 5 TPBGA TL B5118 03 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005
247. led the RX FIFO Errored Frame Drop Counter Ports 0 3 0x5A2 0x5A5 and TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0x629 increment with every frame removed in addition to the existing frames counted due to FIFO overflow 5 1 8 1 Conventions The following conventions are used throughout the RMON Management Information Base MIB and its companion documents Good Packets Error free packets that have a valid frame length For example on Ethernet good packets are error free packets that are between 64 and 1518 octets long They follow the form defined in IEEE 802 3 Section 3 2 Bad Packets Bad packets are packets that have proper framing and recognized as packets but contain errors within the packet or have an invalid length For example on Ethernet bad Datasheet 82 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 1 8 2 5 2 83 packets have a valid preamble and SFD but have a bad CRC or are either shorter than 64 octets or longer than 1518 octets Advantages The following lists additional IXF1104 MAC registers that support features not documented in RMON MAC flow control frames VLAN Tagged Sequence Errors Symbol Errors CRC Error These additional counters allow for differentiation beyond standard RMON probes In fiber mode a packet transfer with an inva
248. lid 10 bit symbol does not always update the statistics registers correctly e Behavior The IXF1104 MAC 8B10B decoder substitutes a valid code word octet in its place The packet transfer is aborted and marked as bad The new internal length of the packet is equal to the byte position where the invalid symbol was No packet fragments are seen at the next packet transfer Issue If the invalid 10 bit code is inserted in a byte position of 64 or greater expected RX statistics are reported However if the invalid code is inserted in a byte position of less than 64 expected RX statistics are not stored SPI3 Interface The IXF1104 MAC SPD Interface is implemented to the System Packet Interface Level 3 SPI3 Physical Layer Interface standard The interface function allows the IXF1104 MAC blocks to interface to higher layer network processors or switch fabric The IXF1104 MAC transmit interface allows data flows from a network processor or switch fabric device to the IXF1104 MAC The receive interface allows data to flow from the IXF1104 MAC to the network processor or switch fabric device This interface receives and transmits data between the MAC and the Network Processor with compliant SPI3 interfaces The SPI3 interface operation is defined in the OIF SPI3 01 0 available from the Optical Internet Working Forum www oiforum com The OIF specification defines operation for the transfer of data at data rates of up to 3 2 Gbps when operating
249. lied and stable prior to application of the 2 5 V analog and digital supplies Power Down Sequence Remove the 2 5 V supplies prior to removing the 1 8 V power supplies the reverse of the power up sequence Damage can occur to the ESD structures within the analog I Os if the 2 5 V digital and analog supplies exceed the 1 8 V digital and analog supplies by more than 2 0 V during power up or power down Figure 5 and Table 19 provide the IXF1104 MAC power supply sequencing Power Supply Sequencing 1 8 V Supplies Stable 2 5 V Supplies Stable Apply VDD AVDD1P8_1 Apply VDD4 VDDS AVDDIPS 2 AVDD2PS 1 and AVDD2PS 2 Time 0 Sys_Res NOTE The 3 3 V supply VDD2 and VDD3 can be applied at any point during this sequence Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 19 Power Supply Sequencing Power Supply Power Up Order us Notes VDD AVDD1P8 1 2 AVDD1P8 2 First 0 1 8 V supplies VDDA VDD5 AVDD2P5 1 Second 10 us 2 5 V supplies AVDD2P5 2 1 The value of 10 us given is a nominal value only The exact time difference between the application of the 2 5 V analog supply is determined by a number of factors depending on the power management method used NOTE To avoid damage to the IXF1104 MAC the TXAV25 supply must not exceed the VDD supply by more th
250. lse 15 Next Page Next Page request RO 0 14 Reserved Reserved RO 0 Remote fault definitions 00 No error link okay 13 12 Remote Fault 1 0 01 Offline R W 00 10 Link failure 11 Auto negotiation Error 11 9 Reserved Reserved RO 000 8 Asym Pause Asym Pause The ability to send pause frames RO 0 7 Sym Pause EA Pause The ability to send and receive pause RO 0 rames 6 Half Duplex Half duplex RO 0 5 Full Duplex Full duplex RO 0 4 0 Reserved Reserved RO 0x0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 89 TX Config Word Port Index 0x17 Sheet 1 of 2 Bit Name Description Default Register Description This register is used in fiber MAC for auto negotiation only The contents of this register are sent as the config word The contents of this register are the 0 000001 0 config reg sent to the link partner as described IEEE 802 3 2000 Edition subclause 37 2 1 31 16 Reserved Reserved RO 0x0000 15 Next Page Next Page request R W 0 14 Reserved Write as 0 ignore on read R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write NOTE A value of 0x0 must be written to all reserved bits of the TX Config Word Port_Index 0x17 Register Datasheet 170 D
251. m Datasheet 224 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 9 3 Package Information 9 3 1 CBGA Package Diagrams Figure 55 and Figure 56 illustrate the CBGA top bottom and side package views Figure 55 CBGA Package Diagram Chip 47P6802 Substrate 25 0 2 Note All dimensions are in mm B0034 01 a 8 32 575 0 8 0 05 gt 20 1 5 0 825 MAX 020 OPASES NA gt Pads amp 23 0 325 MIN Reference 000000000000000000000 222222222 900000000000000000 000000000000000000 28 0000000000 N OOOOOOOOQOOOOOOOOOOQO No ball 0000000000000000000 20 QOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOO C OO 0000000006 550000000000 amp OOO0O000000000 000000000000 amp 00000000000 Y 20000000000000000000 Y 00000000000 i lt 23x TYP Chip Carrier A01 Corner 23 25 0 2 a Note All dimensions are in mm B0035 03 225 Datasheet Document Number 278757
252. matches the Station Address R W 0 are forwarded All other unicast frames are dropped NOTE The VLAN filter overrides the unicast filter Therefore a VLAN frame cannot be filtered based on the unicast address 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 Used in conjunction with the RX FIFO Errored Frame Drop Enable 0x59F on page 196 This allows the frame to be dropped in the RX FIFO Otherwise the frame is sent out the SP3 interface and may be optionally signaled with an RERR see bit 0 of SPI3 Receive Configuration 0x701 Table 92 Port Multicast Address Port Index 0x1A 0 1 Name Description Address Type Default This address compares against multicast frames Port Multicast at the receiving side if multicast filtering is Port Index Address Low enabled OX1A R W 0x0000000 This register contains bits 31 0 of the address This address compares against multicast frames Port Multicast at the receiving side if Multicast filtering is Port_Index Address High enabled 0x1B This register contains bits 47 32 of the address 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write R W 0x00000000 173 Datasheet Document Number 278757 Revision Number 009 Revision Date
253. mber 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 16 SPHY Connection for Two Intel IXF1104 MAC Ports 8 Bit Interface Note Datasheet Network Processor TFC TDAT 7 0 TPRTY TSOP TEOP TERR DTPA RFC RENB RDAT 7 0 RPRTY RVAL RSOP REOP RERR PTPA TADR 1 0 TFC TENB TDAT 7 0 TPRTY TSOP TEOP TERR DTPA RFC RENB RDAT 7 0 RPRTY RVAL RSOP REOP RERR SPI3 Bus Intel IXF1104 Port 0 TFCLK TENB 0 TDAT 7 0 0 TPRTY 0 TSOP 0 TEOP 0 TERR 0 DTPA 0 Line Side Interface RFCLK RENB 0 RDAT 7 0 0 RPRTY 0 RVAL 0 RSOP 0 REOP 0 RERR 0 SPI3 Flow Control PTPA TADR 1 0 Port 1 TFCLK TENB 1 TDAT 7 0 1 TPRTY 1 TSOP 1 TEOP 1 TERR 1 DTPA 1 Line Side Interface RFCLK RENB 1 RDAT 7 0 1 RPRTY 1 RVAL_1 RSOP_1 REOP_1 RERR_1 Port 0 Transceiver gt Q Port 1 Transceiver O gt 0659 02 5 2 2 8 1 Clock Rates The TFCLK and RFCLK can be independent of each other in SPHY mode operation TFCLK and RFCLK should be common to all the Network Processor devices The IXF1104 MAC requires an individual single clock source for the device transmit path and a single clock source for the device receive path The IXF1104 MAC allows this interface to be overclocked so that all four IXF1104 MAC ports can operate at 1 Gbps Thi
254. module refer to the details in Section 5 7 3 4 Protocol Specifics on page 112 5 The PC DATA WRITE FSM internal state machine uses the data from the Write Data field bits 23 16 of the Data Ports 0 3 0x79F on page 223 and sets the Write Complete Register bit 22 of the IC Control Ports 0 3 0x79B to 0x1 to signify that the Write Access is complete 6 The data is written through the CPU interface The CPU must poll the Write Complete bit until it is set to 0x1 It is safe to request a new access only when this bit is set Note Only one optical module access sequence can be run at any given time The data for the first Write is lost if a second Write is carried out to the Control Ports 0 3 0x79B before result is returned for the previous Write Make sure Write complete 0x1 before starting the next Write sequence to ensure that no data is lost 5 7 3 4 PC Protocol Specifics Section 5 7 3 4 describes the IXF1104 MAC PC Protocol behavior which is controlled by an internal state machine Specific protocol states are defined below with an additional description of the hardware signals used on the interface The Serial Clock Line PC CLK is an output from the IXF1104 MAC The serial data is synchronous with this clock and is driven off the rising edge by the IXF1104 MAC and off the falling edge by the optical module The IXF1104 MAC has only one IC line that drives all o
255. n Around MDO Reg_Bit_WO Cnt MDC EN 1 Y Cnt 2 Cnt 16 MDOE Wr_Op Data MDO Data Cnt nt gt or Cnt 16 and Go 0 Cnt 16 And Go 1 Datasheet 19 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 5 8 5 6 5 6 1 5 6 2 103 Autoscan Operation The autoscan function allows the 32 registers in each external PHY up to four to be stored internally in the IXF1104 MAC Autoscan is enabled by setting bit 1 of the MDI Control register When enabled autoscan runs continuously reading each PHY register When a PHY register access is instigated through the CPU interface the current autoscan register Read is completed before the CPU register access starts Upon completion of the CPU induced access the autoscan functionality restarts from the last autoscan register access The Autoscan PHY Address Enable 0x682 determines which PHY addresses are being occupied for each IXF1104 MAC port The least significant bit LSB that is set in the register is Port 0 the next significant bit that is set is assumed to be port 1 and so on If more than four bits are set the bits beyond the fourth bit are ignored If less than four bits are set the round robin process returns to the port identified by the LSB being set SerDes Interface The IXF1104 MAC integrates four integrated Serializer Deserializer Ser
256. n Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 72 FD FC Type Port Index 0x03 Name Description Address Type Default This value fills the Type field of the Transmitted Port Index FD FC Type Pause frames Only bits 15 0 of this register are 0x03 R W 0x00008808 used 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 163 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 73 Collision Distance Port Index 0x05 Name Description Address Default This is a 10 bit value that sets the limit for late Collision collision Collisions happening at byte times Port Index Distance beyond the configured value are considered to be 0x05 RWY 0x00000043 late collisions Only valid in half duplex 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 74 Collision Threshold Port Index 0x06 Name Description Address Default Collision Threshold This is a 4 bit value that sets the limit for excessive collisions When the number of transmission attempts performed for a
257. n Write Table 115 RX FIFO High Watermark Port 2 0x582 Bit Name Description Default Register Description The default value of OXOE6 represents 230 eight byte locations This equates to 1840 bytes of data A unit entry in this register equates to 8 bytes of data When the Ox0E6 amount of data stored in the RX FIFO exceeds the high watermark flow control is automatically initiated within the MAC to avoid an overflow condition 31 12 Reserved Reserved RO 0x00000 The high water mark value RX FIFO High 11 0 9 NOTE Must be greater than the FIFO Low R W 0x0E6 Watermark Port 2 Watermark and RX FIFO transfer threshold 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 193 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 116 RX FIFO High Watermark Port 3 0x583 Bit Name Description Default Register Description The default value of OXOE6 represents 230 eight byte locations This equates to 1840 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO exceeds the high watermark flow control is automatically initiated within the MAC to avoid an overflow condition 31
258. n resumed when TENB is low The valid bytes in the final word during an active TEOP are indicated by state of TMOD 1 0 Figure 11 MPHY Transmit Logical Timing 5 2 2 2 85 wok TSOP A f mmm 1 3 mt TERR 5 rc EE TDAT 31 0 Tav X OX X XXX OC CX X X X X X B3216 02 0000 BO B3 X B4 B7 44 47 48 51 52 55 56 594 B60 B64X 0001 BO B3 X B4 B7 1 Applies to all transmit packet available signals STPA PTPA DTPA 0 3 Receive Timing A packet is received when RSX indicates port address information on the data bus followed by RSOP to indicate the data bus contains the first word of a packet All subsequent data is valid only while RVAL is High and until REOP is asserted Receive data can be temporarily halted when RENB is de asserted and starts again on the second rising edge of RFCLK following the assertion of RENB RMOD indicates the number of valid bytes in the last transfer when REOP is asserted Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 12 MPHY Receive Logical Timing I RENB f Y f BERE NEC 50 7 5 7 c C ANM 7 9o o ir 5 4 8 RSX ET 81 83
259. ncluding RxPkts512t01023O bad packets that were 512 1023 octets in Port Index R 0x00000000 ctets length Incremented for tagged packets with a 0x29 length of 512 1023 bytes including tag field The total number of packets received including RxPkts1024to1518 bad packets that were 1024 1518 octets in Port Index R 0x00000000 Octets length Incremented for tagged packet with a 0 2 length between 1024 1522 including the tag The total number of packets received including bad packets that were greater than 1518 octets 5 519toMaxO in length Incremented for tagged packet with a R 0x00000000 length between 1523 max frame size including the tag Number of frames received with legal size but with wrong CRC field also called Frame Check Sequence FCS field Port Index RxFCSErrors NOTE Legal size is 64 bytes through the value R 0x00000000 Ox2C programmed in the Max Frame Size Addr Port Index OxOF page 166 Number of OK frames with VLAN tag Port Index RxTagged Type field 0x8100 0x2D R 0 00000000 Number of frames received with legal length Port Index RxDataError containing a code violation signaled with OX2E R 0x00000000 RX ERR on RGMII 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 When sending in large frames the counters can only handle certain limits The behavior of t
260. nded Capabiny 2 No extended register capable ro o 1 R Read Only RR Clear on Read W Write R W Read Write Table 97 PHY Identification 1 Port Index 0x62 Bit Name Description Type Default 0x00013 31 16 Reserved Reserved RO 0 The PHY identifier is composed of register bits 15 0 PHY ID Number 18 3 of the OUI Organizationally Unique RO h0013 Identifier 1 RO Read Only RR Clear on Read W Write R W Read Write 183 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 98 PHY Identification 2 Port Index 0x63 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Bit Name Description Type Default 0x001111001 00000000 31 16 Reserved Reserved RO 0 The PHY identifier is composed of register bits 15 10 PHY ID Number 24 19 of the OUI Organizationally Unique RO 011110 Identifier 9 4 Manufacturer s Model Six bits containing the manufacturer s part number RO 010000 3 0 Manufacturer S Four bits containing the manufacturer s revision RO 0000 Revision Number number 1 RO Read Only RR Clear on Read W Write R W Read Write Table 99 Auto Negotiation Advertisement Port Index 0x64 Sheet 1 of 2 Bit Name Description Type Default 0x00000100 111100001 31 16 Reserved R
261. nder Section 5 7 2 2 1 MOD DEF 0 3 109 Modified second sentence under Section 5 7 2 2 3 LOS 0 3 109 Removed third paragraph under Section 5 7 2 2 7 LOS INT 110 Modified first and second paragraphs under Section 5 7 3 Module Configuration Interface 111 Modified Section 5 7 3 3 2 Write Operation edited portions of text 116 Modified Table 31 LED Interface Signal Descriptions changed 0 5 MHz to 720 Hz for LED CLK under Signal Description 119 Modified Table 35 LED Behavior Fiber Mode changed links under Description to Link LED Enable 0 502 NA Removed old Figure 30 CPU External and Internal Connections 123 Modified Table 37 Byte Swapper Behavior edited added new values 123 Modified second paragraph under Section 5 10 TAP Interface JTAG 126 Modified Figure 33 Interface Loopback Path 126 Added note under Section 5 11 2 Line Side Interface Loopback 127 Modified Figure 34 Line Side Interface Loopback Path 127 Changed Section 5 12 Clocks from GBIC output clock to 12 Clock 129 Changed Section 5 12 6 IC Clock from GBIC Clock to 2 Clock 130 Added new Section 6 0 Applications Modified Table 39 Absolute Maximum Ratings changed SerDes analog power to AVDD1P8 2 132 and AVDD2P5 2 changed PLL1 PLL2 VDDA to AVDD1P8 1 changed PLL3 VDDA to AVDD2P5 1 Modified Table 40 Recommended Operating Conditions chan
262. nes the MAC operational frequency and mode for a given port hier haa NOTE Setthe Clock and Interface Mode Change Enable Ports 0 3 Speed 0x090 Port 1 0x794 on page 221 to 0x0 prior to any change in the E idoi 0x110 Port 2 register value This ensures that a change in the MAC clock 0x10 0x190 Port 3 frequency is controlled correctly If the Clock and Interface Mode Change Enable Ports 0 3 0x794 is not used correctly the IXF1104 MAC may not be configured to the proper mode 0x500 Part Enable Bit 0 Port 0 Each Port Enable 0x500 bit relates to a port Set the appropriate bit 0x500 Bit 1 Port 1 to Ox1 to enable a port This should be the last step in the configuration Bit 2 Port 2 process for a port Bit 3 Port 3 The Interface Mode 0x501 selects whether a port operates with a 0x501 copper RGMII or GMII line side interface an integrated SerDes fiber Bit 0 Port 0 line side interface Interface Mode Bit 1 Port 1 For copper operation for a given port set the relevant bit to Ox1 0x501 Bit 2 Port 2 For fiber operation for a given port set the relevant bit to 0 0 Bit 3 Port NOTE All ports are configured for fiber operation in the IXF1104 MAC default mode of operation 0x794 The Clock and Interface Mode Change Enable Ports 0 3 0x794 Clock and indicates to an internal clock generator when to sample the new value Interface Mode Bit 0
263. nore on Read R W 1 0 Normal operation 1 Enable padding of undersized packets 7 bl R W 0 pad enable NOTE Assertion of this bit results in the automatic addition of a CRC to the padded packet 0 Normal operation 8 crer aca 1 Enable automatic CRC appending R W 0 Enable auto negotiation used for fiber mode only to be performed by the hardware state machines in the MAC 5 AN enable The hardware auto negotiation AN state R W 0 machine controls the config words transmitted when this bit is set NOTE copper mode this bit must be set to 0 reserved 4 Reserved Write as 0 ignore on Read R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 Reserved bits must be written to the default value for proper operation 171 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 90 Diverse Config Write Port Index 0x18 Sheet 2 of 2 Bit Name Description Default 3 2 Reserved Write as 1 ignore on Read R W 11 1 Reserved Write as 0 ignore on Read R W 0 0 Reserved Write as 1 ignore on Read R W 1 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Cle
264. nsmit Enable TX EN 0 AB2 m TX EN 1 Y8 25V TX_EN indicates that valid data is TX EN 2 AC22 Output being driven on the corresponding TX EN 3 12 Transmit Data TXD 0 TXD 1 TXD 2 and TXD 3 TX ER 0 W1 Transmit Error TX_ER_1 AD6 Output 25V TX ER indicates a transmit error in the TX ER 2 AD17 CMOS corresponding Transmit Data 0 TX_ER_3 AB13 TXD_1 TXD_2 and TXD_3 Source Synchronous Transmit Clock TXC 0 AA1 This clock is supplied synchronous to TXC 1 AD7 Output 25V the transmit data bus in either RGMII or TXC 2 AC20 P CMOS GMII mode TXC 3 AB14 NOTE Shares the same balls as RXC on the RGMII interface NOTE Refer to the RGMII interface for shared data and clock signals Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 48 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 5 GMII Interface Signal Descriptions Sheet 2 of 2 Signal Name Ball Designator Type Standard Description RXD7 0 AC5 RXD6 0 AB5 RXD5 0 Y5 RXD4 0 Y6 RXD3 0 Y7 RXD2_0 W7 RXD1_0 V7 RXDO 0 V8 RXD7 1 Y10 aoe AH Receive Data RXD4 1 AD10 Each bus carries eight data bits 7 0 of RXD3 1 w9 the received data stream RXD2_1 W11 RGMII Mode When a port ID is RXD1 1 Y11 configured in copper mode and the RXDO 1 Y9 RGMII interface is selected only bits Input 25V RXD 3 0 n are used to receive data RXD7 2 w20 GMOS Fiber Mode The follow
265. nt Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 5 8 2 Table 31 5 8 3 Note Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller LED Interface Signal Description The IXF1104 MAC LED interface consists of three output signal signals that are 2 5 V CMOS level pads Table 31 provides LED signal names pin numbers and descriptions LED Interface Signal Descriptions Pin Name Pin 4 Pin Description This signal is an output that provides a continuous clock synchronous to the serial data stream output on the LED DATA pin This clock has a maximum LED CLK K24 speed of 720 Hz The behavior of this signal remains constant in all modes of operation This signal provides the data in various formats as a serial bit stream The data must be valid on the rising edge of the LED signal In Mode 0 the data presented on this pin is TRUE Logic 1 High In Mode 1 the data presented on this pin is INVERTED Logic 1 Low LED DATA M22 This is an output pin and the signal is used only in Mode 1 as the Latch enable LED LATCH L22 for the shift register chain This signal is not used in Mode 0 and should be left unconnected Mode 0 Detailed Operation Please refer to the SGS Thompson M5450 datasheet for device operation information The operation of the LED Interface in Mode 0 is based on a 36 bit counter loop The data for each LED is placed in turn on the
266. ock and may be optionally dropped A bad packet may be signaled with RERR on the SPI3 interface if it is not dropped The IXF1104 MAC operates only in full duplex mode at 1000 Mbps rates on both SerDes and GMII interface connections The IXF1104 MAC is capable of operation at 1000 Mbps full duplex in RGMII mode and at full duplex and half duplex operation for 10 100 Mbps links Features for Fiber and Copper Mode Section 5 1 1 1 through Section 5 1 1 4 cover IXF1104 MAC functions that are independent of the line side interface Padding of Undersized Frames on Transmit The padding feature allows Ethernet frames smaller than 64 bytes to be transferred from the SPI3 interface to the TX MAC and padded up to 64 bytes automatically by the MAC This feature is enabled by setting bit 7 of the Diverse Config Write Port Index 0x18 When the user selects the padding function the MAC core adds an automatically calculated CRC to the end of the transmitted packet Automatic CRC Generation Automatic CRC Generation is used in conjunction with the padding feature to generate and append a correct CRC to any transmit frame This feature is enabled by setting bit 6 of the Diverse Config Write Index 0x18 Filtering of Receive Packets This feature allows the IXF1104 MAC to filter receive packets under various conditions and drop the packets through an interaction with the Receive FIFO control 5 1 1 3 1 Filter on Unicast Pack
267. ocument Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 89 TX Config Word Port Index 0x17 Sheet 2 of 2 Bit Name Description Default Remote fault definitions 00 No error link okay 13 12 Remote Fault 1 0 01 Offline R W 00 10 Link failure 11 Auto negotiation Error 11 9 Reserved Write as 0 ignore on Read R W 000 8 Asym Pause Asym Pause The ability to send pause frames R W 1 Sym Pause The ability to send and receive pause 7 Sym Pause frames R W 1 6 Half Duplex Half duplex R W 0 5 Full Duplex Full duplex R W 1 4 0 Reserved Write as 0 ignore on read R W 0x00 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write NOTE A value of 0x0 must be written to all reserved bits of the TX Config Word Port Index 0x17 Register Table 90 Diverse Config Write Port_Index 0x18 Sheet 1 of 2 Bit Name Description Type Default Register Description This register contains various configuration bits for general use 0x00110D 31 19 Reserved Reserved RO 0x0000 18 13 Reserved Write as 0 ignore on Read R W 0x0000 12 Reserved Write as 1 ignore on Read R W 1 11 9 Reserved Write as 0 ignore on Read R W 0x0 8 Reserved Write as 1 ig
268. of a new module these restrictions should not affect normal operation The interface supports byte write accesses to the full address range The interface only supports random single byte reads and does not guarantee coherency when reading two byte registers Control and Data Registers In the IXF1104 MAC the entire PC interface is controlled through the following two registers Control Ports 0 3 0x79B on page 223 Data Ports 0 3 0x79F on page 223 These registers can be programmed by system software using the CPU interface 2 Read Operation To perform a read operation using the 2 interface use the following sequence 110 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 1 Initialize the Control register by setting the following values a Enable the C Controller by setting bit 25 to 0 1 Initiate the C transfer by setting bit 24 of the control register to 0 1 c Select the port by using bits 17 16 d Select the Read mode of operation by setting bit 15 to Ox1 e Select the Device ID by setting bits 14 11 f Select the register address by setting bits 10 0 2 Set the Device ID field to OxA and the register address bits 10 8 to 0x0 to access the fiber module serial 2 Setting the Device ID field to OxA and the Register Address 10 8
269. of three signals to provide LED data to some form of external driver This provides the data for 12 separate direct drive LEDs and allows three LEDs per MAC port There are two modes of operation each with its own separate LED decode mapping Modes of operation and LEDs are detailed in the following sections Modes of Operation There are two modes of operation Mode 0 and Mode 1 Mode selection is accomplished by using the LED SEL MODE bit This bit is globally selected and controls the operation of all ports see Table 109 LED Control 0x509 on page 190 Mode 0 LED SEL MODE 0 Default This mode selects operations compatible with the SGS Thompson M5450 LED Display Driver device This device converts the serial data stream output by the IXF1104 MAC into 30 direct drive LED outputs Although the LED interface is capable of driving all 30 LEDs only twelve will be driven in the four port IXF1104 MAC three LEDs per port Mode 1 LED SEL MODE 1 This mode is used with standard TTL 74LS599 or HCMOS 74 599 octal shift registers with latches providing the most general and cost effective implementation of the serial data stream conversion In addition to these physical modes of operation there are two types of specific LED data decodes available for fiber and copper modes This option is a global selection and controls the operation of all ports see Table 109 LED Control 0x509 on page 190 Datasheet Docume
270. on affects both the SPI3 transmitter and receiver functionality R W 20 Tx_ad_prtyer_drop Indicates whether to drop packets received with parity error during the address selection phase Tsx and nTenb High should be dropped 0 Do not drop packets with address parity error 1 Drop packets with address parity error This is applicable only in MPHY mode of operation This bit is ignored in SPHY 4 x 8 mode as there will be no address selection R W 19 Dat_prtyer_drp Port 3 SPHY MPHY Mode Indicates whether to drop packets with data parity error for port 3 0 Do not drop packets with data parity error default 1 Drop packets with data parity error R W 0x0 18 Dat_prtyer_drp Port 2 SPHY MPHY Mode Indicates whether to drop packets with data parity error for port 2 0 Do not drop packets with data parity error default 1 Drop packets with data parity error R W 17 Dat_prtyer_drp Port 1 SPHY MPHY Mode Indicates whether to drop packets with data parity error for port 1 0 Do not drop packets with data parity error default 1 Drop packets with data parity error R W 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 213 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 146 SPI3 Transmit and Global Confi
271. onent attributed to random thermal noise effects Since the thermal noise component is random and statistical in nature the SerDes core total transmit jitter must be specified as a function of BER Receive Jitter The SerDes core total receiver jitter including contributions from the intermediate frequency PLL is comprised of the following two components A deterministic component attributed to the SerDes core architectural characteristics Arandom component attributed to random thermal noise effects 106 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 5 7 5 7 1 intel Optical Module Interface This section describes the connection of the IXF1104 MAC ports to an Optical Module Interface and details the minimal connections that are supported for correct operation The registers used for write control and read status information are documented The Optical Module Interface allows the IXF1104 MAC a seamless connection to the Small Form Factor Optical Modules SFP that form the system s physical media connection eliminating the need for any FPGAs or CPUs to process data All required optical module information is available to the system CPU through the IXF1104 MAC CPU interface leading to a more integrated reliable and cost effective system The IXF1104 MAC supports all the functions required for the Small Form Factor pluggable Multi
272. process RO 1 Enable This register bit must be enabled for 1000BASE T operation 0 Normal operation 11 Power Down 12 Power down RO 0 0 10 Isolate 1 Electrically isolate PHY from GMII RO 0 9 Restart 0 Normal operation RO 0 Auto Negotiation 1 Restart auto negotiation process 0 Half duplex mode 2 8 Duplex Moda 1 Full duplex mode RO 0 Disable COL signal test 1 Enable COL signal test 7 Collision Test RO 0 e This register bit is ignored unless loopback is enabled Register bit 0 14 1 0 6 Speed lt 1 gt 0 13 Speed lt 0 gt Exod Esel 00 210 Mbps peed Selection 2 6 1000 Mbps 01 100 Mbps RO 0 10 1000 Mbps manual mode now allowed 11 Reserved 5 0 Reserved Reserved RO 0 1 RO Read Only RR Clear on Read W Write R W Read Write 2 This register is ignored if auto negotiation is enabled Table 96 PHY Status Port Index 0x61 Sheet 1 of 2 Bit Name Description Default 0x001111001 00001001 31 16 Reserved Reserved RO 0 0 PHY not able to operate in 100BASE T4 15 100BASE T4 1 PHY able to operate in 100BASE T4 RO 0 0 PHY not able to operate in 100BASE X in full 14 100BASE X duplex mode RO 1 Full Duplex 1 PHY able to operate in 100BASE X in full duplex mode 0 PHY not able to operate in 100BASE X in 13 100BASE X half duplex mode RO 1 Half Duplex 1 PHY able to operate in 100BASE X in half duplex mode 0 PHY not able to operate in 10 Mbps in full 12 10 Mbps duplex mode RO 1 Full
273. r 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 7 4 7 4 1 7 4 1 1 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller GMII AC Timing Specification 1000 Base T Operation Figure 38 and Figure 39 and Table 49 and Table 50 provide GMII AC timing specifications 1000 BASE T Transmit Interface Figure 38 1000BASE T Transmit Interface Timing Table 49 Datasheet GE RET RUE NEN NENNEN TXEn o Hit 1 XB ag wu po ac po ox 1 E TXER i 5 B0634 01 GMII 1000BASE T Transmit Signal Parameters Symbol Parameter Min Typ Max Unit t TXD 7 0 TXEN TXER Set up to TXC High 2 5 ns t2 TXD 7 0 TXEN TXER Hold from TXC High 0 5 ns t3 TXEN sampled to CRS asserted 16 BT t4 TXEN sampled to CRS de asserted 16 BT 1 Typical values are at 25 and are for design aid only not guaranteed and not subject to production testing 2 Bit Time BT is the duration of one bit as transferred to from the PHY and is the reciprocal of bit rate BT for 1000BASE T 10 or 1 ns 142 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 4 1 2 1000BASE T Receive Interface Figure 39 1000BASE T Receive Interface Timing intel RxDV t2 RXD 7 0 RX CLK CRS ic Table 50 GMII 1000BA
274. r Control Port Index 0x19 old register name added RX to heading added table note 2 174 Modified Table 93 RX Statistics Port Index 0x20 0x39 added note to RxPauseMacControlReceivedCounter description edited note 3 and added note 4 178 Modified Table 94 MAC TX Statistics Port Index 0x40 40x58 changed 1526 max to 1523 max frame size for Txpkts1519toMaxOctets description 193 Modified Table 113 RX FIFO High Watermark Port 0 0x580 Table 114 RX FIFO High Watermark Port 1 0x581 Table 115 RX FIFO High Watermark Port 2 0x582 and Table 116 RX FIFO High Watermark Port 3 0x583 changed bits 11 0 description 195 Renamed and modified Table 121 RX FIFO Overflow Frame Drop Counter Ports 0 3 0x594 0x597 old register name RX FIFO Number of Frames Removed Ports 0 to 3 renamed bit names to match register names removed This register gets updated after one cycle of sw reset is applied under Description 196 Modified Table 123 RX FIFO Errored Frame Drop Enable 0x59F renamed bit names to match register name 198 Renamed modified Table 125 RX FIFO Errored Frame Drop Counter Ports 0 3 0x5A2 0x5A5 on page 198 older register name RX FIFO Dropped Packet Counter for Ports 0 to 3 renamed bit names to match register name 199 Modified Table 126 RX FIFO SPI3 Loopback Enable for Ports 0 3
275. r Network Table 21 250r1 8wv YOC 01 pF 1 I Analog ower Ball Analog Power Balls Ball Signal Name Designator Comments AVDD1P8 1 A5 A20 Need to provide a filter see Figure 6 AVDD2P5 1 AD20 R AVDD1P8 1 and AVDD2PS5 1 5 6 Q resistor AVDD1P8 2 AB16 T23 Need to provide a filter see Figure 6 AVDD2P5 2 U14 R18 AVDD1P8_2 and AVDD2P5 2 1 0 resistor Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 tel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Functional Descriptions 5 1 Media Access Controller MAC The IXF1104 MAC main functional block consists of four independent 10 100 1000 Mbps Ethernet MACs which support interfaces for fiber and copper connectivity Copper Mode RGMII for 10 100 1000 Mbps full duplex operation and 10 100 Mbps half duplex operation GMII for 1000 Mbps full duplex operation Fiber Mode Integrated SerDes OMI interface for direct connection to optical modules 1000 Mbps full duplex operation in fiber mode The following features support copper and fiber modes Programmable Options Automatic padding of transmitted packets that are less than the minimum frame size Broadcast multicast and unicast address filtering on frames received Filter and drop packets with errors Pre padded RX frames with two bytes aligns the Ethern
276. r Optical Module SerDes functionality on a per port basis This mode of operation is controlled through a configuration register While IEEE 802 3 specifies 3 3 V operation of GMII devices most PHYs use 2 5 V signaling The IXF1104 MAC provides a 2 5 V drive and is 3 3 V tolerant on inputs Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 17 MAC GMII Interconnect 5 3 1 5 3 2 Datasheet TXC 3 0 TXC 3 0 TXD 7 0 0 TXD 7 0 0 TXD 7 0 1 TXD 7 0 1 TXD 7 0 2 TXD 7 0 2 TXD 7 0 3 TXD 7 0 3 TX EN 3 0 TX EN 3 0 TX ER 3 0 ER 3 0 5 3 0 l RXC 3 0 9 RXD 7 0 0 4 RXD 7 0 0 B 85 RXD ZO 1 4 RXD 7 0 1 2 TS RXD 70 2 4 4 RXDI 7 0 2 9 2 RXD 7 0 3 4 RXD 7 0 3 EN 3 0 4 EN 3 0 ER 3 0 4 ER 3 0 CRS 3 0 4 CRS 3 0 COL 3 0 M4 3 0 B3203 01 GMII Signal Multiplexing The GMII balls are reassigned when using the RGMII mode or fiber mode Table 16 Line Side Interface Multiplexed Balls on page 58 specifies the multiplexing of GMII balls in these
277. r is calculated as follows register_value 5 8 RXIPG2 in terms of bit times Therefore a default of 7 gives the following 7 5 8 96 bit times for default 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 79 IPG Transmit Time Port_Index 0x0C Name Description Address Type Default This is a 10 bit value configuring IPG time for back to back transmissions The value specified in this register is calculated as follows register value 4 8 Port Index R W TXIPG in terms of bit times Therefore a 0x0C default value of 8 gives the following 8 4 8 96 bit times for the default IPG Transmit Time 0x00000008 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 165 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 80 Pause Threshold Port Index OxOE Name Description Address Type Default When a pause frame has been sent an internal timer checks when the next pause frame must be scheduled for transmission to keep the link partner in pause mode this is required only if the flow control has to be extended for one more session The paus
278. r normal operation TRST L can be pulled Low permanently disabling the JTAG interface If the JTAG interface is used the TAP controller must be reset as described in Section 5 10 1 TAP State Machine on page 123 and returned to a logic High TAP State Machine The TAP signals drive a TAP controller which implements the 16 state state machine specified by the IEEE 1149 1 specification Following power up the TAP controller must be reset by one of following two mechanisms Asynchronous reset Synchronous reset Asynchronous reset is achieved by pulsing or holding TRST L Low Synchronous reset is achieved by clocking TCLK with five clock pulses while TMS is held or floats High This ensures that the boundary scan cells do not block the pin to core connections in the IXF1104 MAC Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 5 10 2 Instruction Register and Supported Instructions The instruction register is a 4 bit register that enacts the boundary scan instructions After the state machine resets the default instruction is IDCODE The decode logic in the TAP controller selects the appropriate data register and configures the boundary scan cells for the current instruction Table 38 shows the supported boundary scan instructions Table 38 Instruction Register Description In
279. r setting of 1 0 This is the default setting of the IXF1104 MAC SerDes interface Other values listed in the Normalized Driver Power Setting column are multiples of 10 mA For example with inputs at 1110 the driver power is the following 5x10mA 5 SerDes Driver TX Power Levels Normalized DRVPWRx 3 DRVPWRx 2 DRVPWRx 1 DRVPWRx 0 Driver Power Driver Power Setting 0 0 1 1 1 33 13 3 mA NOTE All other values are reserved 104 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 29 SerDes Driver TX Power Levels 5 6 2 3 5 6 2 4 5 6 2 5 105 intel Normalized DRVPWRx 3 DRVPWRx 2 DRVPWRx 1 DRVPWRx 0 Driver Power Driver Power Setting 1 0 1 1 2 0 20 mA 1 1 0 1 1 0 10 mA 1 1 1 0 0 5 5 mA NOTE All other values are reserved Receiver Operational Overview The receiver structure performs Clock and Data Recovery CDR on the incoming serial data stream The quality of this operation is a dominant factor for the Bit Error Rate BER system performance Feed forward and feedback controls are combined in one receiver architecture for enhanced performance The data is over sampled and a digital circuit detects the edge position in the data stream A signal is not generated if an edge is not found A feedback loop takes care of low frequency jitter
280. ransmit Timing SPHY Packet transmission starts when TENB and TSOP indicate present data on the bus is the first word in the packet subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted Data transmission can be temporally halted when TENB goes high then resumed when TENB is low Figure 14 SPHY Transmit Logical Timing 5 2 2 8 Datasheet VILLAS LL LL TENB i top 0 5 5 o 5 J TENER 5 ro Xe 0 B3249 02 Receive Timing SPHY A packet is received when RSOP is asserted to indicate the data bus contains the first word of the packet All subsequent data is valid only while RVAL is high and until REOP is asserted Receive data can be temporarily halted when RENB is de asserted and starts again on the second rising edge of RFCLK following the assertion of RENB When REOP is asserted RMOD indicates the number of valid bytes in the last transfer 88 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 89 Figure 15 SPHY Receive Logical Timing ol o 089 seg e v Emm X X X AL Datasheet Document Number 278757 Revision Nu
281. rising edge and the upper four bits on the falling edge Control signals are multiplexed into a single clock cycle using the same technique For further information on timing parameters see Figure 37 RGMII Interface Timing on page 141 and Table 48 RGMII Interface Timing Parameters on page 141 96 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 5 4 2 5 4 3 Timing Specifics The IXF1104 MAC RGMII complies with RGMII Rev1 2a requirements Table 27 provides the timing specifics TX ER and RX ER Coding To reduce interface power the transmit error condition TX ER and the receive error condition RX_ER are encoded on the RGMII interface to minimize transitions during normal network operation refer to Table 28 on page 97 for the encoding method Table 27 provides signal definitions for RGMII Table 27 RGMII Signal Definitions RGMII Standard Source Description 9 Signal Depending speed the transmit reference clock is 125 MHz 25 d Ue MAG MHz or 2 5 MHz 50ppm Contains register bits 3 0 on the rising edge of TXC and register bits MA 7 4 on the falling edge of TXC TX EN TX CTL MAC TXEN is on the leading edge of TX xor TX is on the falling edge of TXC RXC 0 3 RXC PHY reference clock is 125 MHz 25 MHz or 2 5 MHz 50 Contains register
282. ronous Ready signal for required length of time Figure 32 shows the timing of the asynchronous interface for Write accesses 121 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a ntel Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 32 Write Timing Diagram Asynchronous Interface 4 TCAS uPx_Add 12 0 4 gt uPx_CsN 2 uPx WrN TcwL TCWH uPx Data 31 0 lt 5 TCDWD 3 5 9 1 3 CPU Timing Parameters For information on the CPU interface Read and Write cycle AC timing parameters refer to Figure 47 CPU Interface Read Cycle AC Timing on page 149 Figure 48 CPU Interface Write Cycle AC Timing on page 149 and Table 54 CPU Interface Write Cycle AC Signal Parameters on page 150 5 9 2 Endian The Endian of the CPU interface may be changed to allow connection of various CPUs to the Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller The Endian selection is determined by setting the Endian bit in the CPU Interface 0x508 The following describes Endianness control There is a byte swapper between the internal 32 bit bus and the external 32 bit bus n 8 bit or 16 bit mode operation the byte packer byte unpacker holding registers sink and source data just like the 32 bit extern
283. rries payload data and in band RDAT21 RDATS_2 D22 addresses from the IXF1104 MAC RDAT20 2 C22 Output 3 3 V RDAT19 RDAT3_2 C21 p LVTTL Mode Bits RDAT18 RDAT2_2 C20 RDATI7 2 B22 32 bit Mae 23 16 RDAT16 RDATO 2 B20 4 x 8 Single PHY 7 0 for port 2 RDAT15 RDAT7 1 F18 Receive Data Bus RDATi4 6 1 E18 RDAT carries payload data and in band RDAT13 RDATS_1 E17 addresses from the IXF1104 MAC RDAT12 RDAT4_1 F16 Output 3 3 V RDAT11 RDAT3_1 E16 LVTTL Mode Bits RDAT10 RDAT2_1 D16 RDAT1 1 C17 32 bit Multi PHY 15 8 RDAT8 RDATO 1 A17 4 x 8 Single PHY 7 0 for port 1 43 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 3 Interface Signal Descriptions Sheet 6 of 8 Signal Name Ball Designator Type Standard Description MPHY SPHY RDAT7 RDAT7 0 F14 Receive Data Bus RDAT6 RDAT6 0 E14 RDAT carries payload data and in band RDATS RDATS_0 D14 addresses from the IXF1104 MAC RDAT4 RDAT4_0 C13 3 3 V RDAT3 0 C14 Output LVTTL Mode Bits RDAT2 RDAT2 0 14 D 4 32 bit Mult PHY 7 0 RDATO RDATO 0 A15 4x 8 Single PHY 7 0 for port 0 Receive Clock 33V RFCLK is the clock associated with all LVTTL receive signals Data and controls are driven on the rising edge of RFCLK frequency operation range 90 133 MHz R
284. rsion 1 2 specification The RGMII interface is an alternative to the IEEE 802 3u MII interface The RGMII interface is intended as an alternative to the IEEE 802 3u MII and the IEEE 802 3z GMII The principle objective of the RGMII is to reduce the number of balls from a maximum of 28 balls to 12 balls required to interconnect the MAC and the PHY This reduction is both cost effective and technology independent To accomplish this objective the data paths and all associated control signals are reduced control signals are multiplexed together and both edges of the clock are used 1000 Mbps operation clocks operate at 125 MHz 100 Mbps operation clocks operate at 25 MHz 10 Mbps operation clocks operate at 2 5 MHz The IXF1104 MAC interface is multiplexed with signals from the GMII interface See Table 16 Line Side Interface Multiplexed Balls on page 58 for detailed information Figure 18 RGMII Interface 5 4 1 Datasheet 3 0 TXD 3 0 3 TXD 3 0 2 TXD 3 0 1 TXD 3 0 0 TX CTL 3 0 TXD 3 0 TXD 3 0 TXD 3 0 TXD 3 0 TX CTL 3 3 0 RXD 3 0 3 RXD 3 0 2 RXD 3 0 1 RXD 3 0 0 RX CTL 3 0 e X 2 Media Access Controller 891A9Q AHd B3203 01 Multiplexing of Data and Control Multiplexing of data and control information is achieved by utilizing both edges of the reference clocks and sending the lower four bits on the
285. rts configured in fiber mode 31 17 Reserved Reserved RO 0x0000 16 13 port enable When set individually enables the four 2 ports R W OxF Enable for RX LOS INT operation 12 RX LOS EN 1 Enabled R W 0 Enable for TX FAULT INT operation 11 TX FAULT EN 1 Enabled R W 0 Enable for MOD DEF INT operation 10 MOD DEF EN 12 Enabled R W 0 9 4 Reserved Reserved RO 0X00 3 0 TX DISABLE 3 0 Tx DISABLE outputs for Ports 0 3 R W 0 0 1 Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 222 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 155 2 Control Ports 0 3 0x79B Bit Name Description Default Register Description This register controls and monitors the interface to the optical modules 0x00000000 when used in fiber mode 31 29 Reserved Reserved RO 0x0 28 Port address Err R Port addressing error R 0 An attempt to write to the protected E PROM has zi occurred R This bit is set to 1 when a write and subsequent read from an Optical Module Interface has failed 26 no ack err This signal should be used to validate the data R 0 being read Data is only valid if this bit is equal to zero 25 enable En
286. rved Reserved RO 0x00000 LANE LC NER LANE LANE LANE 7 0 Reserved Write as 0 ignore on Read R W 0x00 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 127 RX FIFO Padding and CRC Strip Enable 0x5B3 Bit Name Description Default Register Description This control register enables to pre pend every packet with two extra 0 00000000 bytes and also enables the stripping of a packet 31 8 Reserved Reserved RO 0x000000 CRC stripping is enabled for Port 3 R Enabl 7 CRC Stripping Enable O Disabled RW 0 for Port 3 12 Enabled uu CRC stripping is enabled for Port 2 R Enabl 0 12 Enabled tom CRC stripping is enabled for Port 1 5 CRC Stripping Enable 0 Disabled RW 0 for Port 1 12 Enabled e CRC stripping is enabled for Port 0 CRC St Enabl S 477 o Pre pending Disabled R W 0 1 Pre pending Enabled Enables pre pending of two bytes at the start of Pre pending Enable every packet Port 3 3 R W 0 Port 3 0 Disabled 1 Enabled Enables pre pending of two bytes at the start of 2 ket Port 2 2
287. rwise damage to the IXF1104 MAC will occur Table 41 DC Specifications Parameter Symbol Min Typ Max Units Comments 2 5 V CMOS I O Cells Input High voltage VIH 1 7 V 2 5 V I Os Input low voltage VIL B 0 7 V 2 5 V I Os Output High voltage VOH 2 0 V 2 5 V I Os Output low voltage VOL 0 4 V 2 5 V I Os 3 3 V I O Cells Input High voltage VIH 1 7 V 3 3 V LVTTL I Os Input low voltage VIL 0 7 V 3 3 V LVTTL I Os Output High voltage VOH 2 4 V 3 3 V LVTTL I Os Output low voltage VOL 0 4 V 3 3 V LVTTL I Os Table 42 SerDes Transmit Characteristics Sheet 1 of 2 Normalized Power 5 Parameter Symbol Drive Min Typ Max Units Comments Settings 0 50 180 230 325 itdi 1 00 350 440 700 Transmit differential mVpp diff AVDD1P8_2 terminated signal level 1 33 425 580 900 to 1 8V Rload 50 Q 2 00 600 770 1050 0 50 1300 1600 1940 1 00 1000 1400 1870 AVDD1P8_2 terminated EE TxCMV mV to 1 8V RLoad 50 mode voltage range 1 33 800 1300 1825 ohms FIR coeffs 0 2 00 700 1100 1760 Differential signal rise Diff rise Rload 50 20 to fall time fall 100 60 96 132 max Differential output _ Nominal value 100 impedance TxDiffZ 60 105 150 Q diff differential Receiver differential voltage requirement at RxDiffV
288. s Revision Number 008 Revision Date August 1 2005 Sheet 2 of 2 Page Description 170 Modified Table 89 TX Config Word Port Index 0x17 changed default value for the register from 0Ox0001A0 to 0 000001 0 and changed default value for bit 6 Half Duplex from 1 to 0 181 Modified Table 95 PHY Control Port Index 0x60 added Need one sentence descriptions of register and register default value 182 Modified Table 96 PHY Status Port Index 0x61 added Need one sentence descriptions of register and register default value 183 Modified Table 97 PHY Identification 1 Port Index 0x62 added Need one sentence descriptions of register and register default value 184 Modified Table 98 PHY Identification 2 Port Index 0x63 added Need one sentence descriptions of register and register default value 184 Modified Table 99 Auto Negotiation Advertisement Port Index 0x64 added Need one sentence descriptions of register and register default value 185 Modified Table 100 Auto Negotiation Link Partner Base Page Ability Port Index 0x65 added Need one sentence descriptions of register and register default value 186 Modified Table 101 Auto Negotiation Expansion Port Index 0x66 added Need one sentence descriptions of register and register default value 187 Modified Table 102
289. s on page 132 provides information on the product operating parameters electrical specifications and timing parameters Section 8 0 Register Set on page 155 illustrates and lists the memory map detailed descriptions default values for the register set and detailed information on each register Section 9 0 Mechanical Specifications on page 224 illustrates the packaging information Section 10 0 Product Ordering Information on page 230 provides ordering information 1 2 Related Documents Document Document Number Intel IXF1104 Media Access Controller Design and Layout Guide 278696 Intel IXF1104 Media Access Controller Thermal Design Considerations 278751 Intel IXF1104 Media Access Controller Development Kit Manual 278785 Intel IXF1104 Media Access Controller Specification Update 278756 Datasheet 20 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 a Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 2 0 General Description The IXF1104 MAC provides up to a 4 0 Gbps interface to four individual 10 100 1000 Mbps full duplex or 10 100 Mbps half duplex capable Ethernet Media Access Controllers MACs The network processor is supported through a System Packet Interface Phase 3 SPI3 media interface The following PHY interfaces are selected on a per port basis Serializer Deserializer SerDes with Optical Module Interface support Gig
290. s allows data transfer at data rates of up to 4 0 Gbps when operating at an overclocked frequency of 125 MHz SPHY operates at a maximum frequency of 125 MHz 90 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 2 2 9 91 5 2 2 8 2 Parity The IXF1104 MAC can be odd or even the IXF1104 MAC defaults to odd when calculating parity on the data bus This can be changed to accommodate even parity if desired and can be set for transmit and receive ports independently The RX and TX parity sense bits have a direct relationship to the port parity in SPHY mode The per port RX parity is set in the SPI3 Receive Configuration 0x701 and the per port TX Parity is set in the SPI3 Transmit and Global Configuration 0x700 SPI3 Flow Control The SPI3 packet interface supports transmit and receive data transfers at clock rates independent of the line bit rate As a result the IXF1104 MAC supports packet rate decoupling using internal FIFOs These FIFOs are 10 KB per port in the transmit direction egress from the IXF1104 MAC to the line interfaces and 32 KB per port in the receive direction ingress to the IXF1104 MAC from the line interfaces Control signals are provided to the network processor and the IXF1104 MAC to allow either one to exercise flow control Since the bus interface is point to point the receive interface of t
291. s equates to 7936 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x602 R W 0x000003E0 FIFO exceeds the high watermark flow control is automatically initiated on the SPI3 interface to request that the switch fabric stops data transfers to avoid an overflow condition High watermark for TX FIFO Port 3 The default value of represents 992 8 byte locations This equates to 7936 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the TX 0x603 R W 0x000003E0 FIFO exceeds the high watermark flow control is automatically initiated on the SPI3 interface to request that the switch fabric stops data transfers to avoid an overflow condition 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write TX FIFO High Watermark Port 0 TX FIFO High Watermark Port 1 TX FIFO High Watermark Port 2 TX FIFO High Watermark Port 3 203 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 133 TX FIFO Low Watermark Register Ports 0 3 0x60A 0x60D Name Description Address Type Default Low watermark for TX FIFO Port 0 The default value of OXODO represents 208 8 byte locations This
292. s128to255Octets 32 R 174 0x27 RxPkts256t05110Octets 32 R 174 0x28 RxPkts512to1023Octets 32 R 174 0x29 RxPkts1024to15180ctets 32 R 174 2 RxPkts1519toMaxOctets 32 R 174 0x2B RxFCSErrors 32 R 174 0x2C RxTagged 32 R 174 0x2D RxDataError 32 R 174 Ox2E RxAlign Errors 32 R 174 Ox2F RxLongErrors 32 R 174 0x30 RxJabberErrors 32 R 174 0x31 PauseMacControlReceivedCounter 32 R 174 0x32 Datasheet 157 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 60 MAC RX Statistics Registers Port Index Offset Sheet 2 of 2 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Register Bit Size Mode Ref Page Offset RxUnknownMacControlFrameCounter 32 174 0x33 RxVeryLongErrors 32 R 174 0x34 RxRuntErrors 32 R 174 0x35 RxShortErrors 32 R 174 0x36 RxCarrierExtendError 32 R 174 0x37 RxSequenceErrors 32 R 174 0x38 RxSymbolErrors 32 R 174 0x39 Table 61 MAC TX Statistics Registers Port Index Offset Register Bit Size Ref Page Offset OctetsTransmittedOK 32 178 0x40 OctetsTransmittedBad 32 R 178 0x41 TxUCPkts 32 R 178 0x42 TxMCPkts 32 R 178 0x43 TxBCPkts 32 R 178 0x44 TxPkts64Octets 32 R 178 0x45 TxPkts65to127Octets 32 R 178 0x46 TxPkts128to255Octets 32 R 178 0x47 TxPkts256to511Octets 32 R 178 0x48 TxPkts51 2to10230ctets 32 R 178 0x49 TxPkts1024to1518
293. scription CPU Interface Endian select Allows the user to select the Endian of 0x00000000 the CPU interface to allow for various CPUs to be connected to the IXF1104 MAC 31 25 Reserved Reserved RO 0x00 Reserved in Little Endian 24 CPU Endian Valid in Big endian R W 0 0 Little Endian 1 2 Big Endian 23 1 Reserved Reserved RO 0x000000 Reserved in Big Endian CPU Endian Control Valid in Little Endian R W 0 0 Little Endian 1 2 Big Endian 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write NOTE Since the Endianess of the bus is unknown when writing to this register write 0x01000001 to set the bit and 0 0 to clear it Table 109 LED Control 0x509 Bit Name Description Type Default Register Description Global selection of LED mode 0x00000000 31 2 Reserved Reserved RO 0x00000000 0 Disable LED Block 1 EED Enable 1 Enable LED Block R W 0 Enable LED Mode 0 for use with SGS Thomson M5450 LED driver Default 1 LED Mode 1 for use with Standard Octal Shift P W register 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 190 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 110 LED F
294. serted These bits are the actual data to be transmitted to the 16 stage shift register chain The decode for each bit in each mode is defined in is LED DATA 1 12 Table 34 on page 119 The data is INVERTD Logic 1 LED ON Low These bits have no meaning in Mode 1 operation and are latched into positions 31 and 32 in the shift register chain These bits are 36 38 PAD BITS not considered as valid data and should be ignored They should always be a Logic 0 High 5 8 5 Power On Reset Initialization The LED interface is disabled at power on or reset The system software controller must enable the LED interface The internal state machines and output signals are held in reset until the full Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller device configuration is completed This is done by setting the LED_ENABLE bit to a logic 1 see Table 109 LED Control 0x509 on page 190 The power on default for this bit is logic 0 5 8 6 LED DATA Decodes The data transmitted on the LED_DATA line is determined by programming the global operation mode as either fiber or copper Table 34 shows the data decode of the data for both fiber and copper MACs Datasheet 118 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Note Intel The data decode of the LED bits is independent of the Physical mode selection
295. served 100 RGMII 10 Mbps operation 101 RGMII 100 Mbps operation 11x RGMII 1000 Mbps operation Bit Name Description Default Register Description MAC IF Mode Determines the MAC operation frequency and mode per port Changes to the data setting of this register must be made in conjunction with the Clock and Interface Mode Change Enable Ports 0 3 0x794 to ensure a safe transition to a new 0x00000003 operational mode Changes to this register must follow a proper sequence Refer to Section 6 1 Change Port Mode Initialization Sequence on page 130 for the proper sequence for changing the port mode and speed 31 3 Reserved Reserved R 0x00000000 These bits are used to define the clock mode and the RGMII GMII mode of operation 000 Reserved 001 Reserved 2 0 Port Mode 010 GMII 1000 Mbps operation R W 011 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 83 Flush TX Port Index 0x11 Bit Name Description Default Register Description Used to flush all TX data It is used if all traffic sent to a port should be 0x00000000 stopped 31 1 Reserved Reserved R 0x00000000 This bit flushes all TX data and is used if all the E traffic sent to a port should be stopped RUM 1 Read Only No clear on Read R Read Clear on Read W Writ
296. sion Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 1 6 1 5 1 6 2 5 1 6 3 79 The register should be programmed to 0x2667 for the 9 6 KB length jumbo frame optimized for the IXF1104 MAC The RMON counters are also implemented for jumbo frame support as follows Rx Statistics RxOctetsTotalOK Addr Port Index 0x20 RxPkts1519toMaxOctets Addr Port Index Ox2B RxFCSErrors Addr Port Index 0x2C RxDatatError Addr Port Index 0x02E RxAlignErrors Addr Index 0x2F RxLongErrors Addr Port Index 0x30 RxJabberErrors Addr Port Index 0x31 RxVeryLongErrors Addr Port Index 0x34 TX Statistics OctetsTransmittedOK Addr Port Index 0x40 TxPkts1519toMaxOctets Addr Port Index Ox4B TxExcessiveLengthDrop Addr Port Index 0x53 TxCRCError Addr Index 0x56 The IXF1104 MAC checks the CRC for all legal length jumbo frames frames between 1519 and the Max Frame Size On transmission the MAC can be programmed to append the CRC to the frame or check the CRC and increment the appropriate counter On reception the MAC transmits these frames across the SPI3 interface jumbo frames above the setting in the RX FIFO Transfer Threshold Port 0 0x5B8 with a bad CRC cannot be dropped and are sent across the SPI3 interface If the receive frame has a bad CRC the appropriate counter is
297. sion Number 009 Revision Date 27 Oct 2005 ntel 8 Contents 125 RX FIFO Errored Frame Drop Counter Ports 0 0x5A2 5 5 198 126 RX FIFO Loopback Enable for Ports 0 60 5 2 nna 199 127 RX FIFO Padding and CRC Strip Enable 0x5B3 sse 200 128 RX FIFO Transfer Threshold Port 0 60 5 8 201 129 RX FIFO Transfer Threshold Port 1 0 5 9 201 130 RX FIFO Transfer Threshold Port 2 202 131 RX FIFO Transfer Threshold Port 0 5 202 132 TX FIFO High Watermark Ports 0 600 0X603 203 133 TX FIFO Low Watermark Register Ports 0 0x60A 0 600 204 134 TX FIFO MAC Threshold Register Ports 0 0x614 0 617 205 135 TX FIFO Overflow Underflow Out of Sequence Event 0 61 206 136 Loop RX Data to TX FIFO Line Side Loopback Ports 0 3 0 61 207 137 TX FIFO Port Reset 0X620 prensa a rg netu ca nieces 207 138 TX FIFO Overflow Frame Drop Counter Ports 0 0x621 0x624 208 139 TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0 629
298. ster 221 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 intel 8 4 11 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Optical Module Register Overview Table 153 through Table 156 Data Ports 0 3 0x79F page 223 provide an overview of the Optical Module Registers Note Table 153 Optical Module Status Ports 0 3 0x799 registers in this section are only applicable to ports that are configured in fiber mode Bit Name Description Type Default Register Description This register provides a means to control and monitor the interface to 0x00000000 the optical modules when a port is used in fiber mode 31 24 Reserved Reserved RO 0x00 23 20 Rx LOS 3 0 Rx LOS inputs for Ports 0 3 R 0 0 19 14 Reserved Reserved 0X00 13 10 Tx 3 0 Tx FAULT inputs for Ports 0 3 R 0x0 9 4 Reserved Reserved 0X00 3 0 MOD DEF 3 0 MOD DEF inputs for Ports 0 3 R 0x0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 154 Optical Module Control Ports 0 0 79 Bit Name Description Default Register Description This register provides access to optical module interrupt enables and 0x1E000 sets the TX_DISABLE output for the po
299. struction Code Description Data Register BYPASS 1111 1 bit Bypass Bypass EXTEST 0000 External Test Boundary Scan SAMPLE 0001 Sample Boundary Boundary Scan IDCODE 0110 ID Code Inspection ID HIGHZ 0101 Float Boundary Bypass CLAMP 0111 Clamp Boundary Bypass Datasheet 124 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 10 3 5 10 4 5 10 5 5 11 5 11 1 125 Note ID Register The ID register is a 32 bit register The IDCODE instruction connects this register between TDI and See Table 112 ID 0x50C on page 192 for detailed information Boundary Scan Register The Boundary Scan register is a shift register made up of all the boundary scan cells associated with the device signals The number type and order of the boundary scan cells are specified in the IXF1104 MAC BSDL file The EXTEST and SAMPLE instructions connect this register between TDI and TDO Bypass Register The Bypass register is a 1 bit register that bypasses the IXF1104 MAC to reduce the JTAG chain length when accessing other devices on the chain besides the IXF1104 MAC The BYPASS HIGHZ and CLAMP instructions connect this register between TDI and Loopback Modes The IXF1104 MAC provides two loopback modes for device diagnostic testing when it has been integrated into a user system line side loopback allows the line side r
300. t Media Access Controller Table 112 JTAG ID 0x50C Bit Name Description Type Default Register Description The value of this register follows the same scheme as the device identification register found in the IEEE 1149 1 specification The upper four bits correspond to silicon stepping The next 16 bits store a Part ID Number The next 11 bits contain a JEDEC 0x10450013 manufacturer ID Bit zero 1 if the chip is the first in a stack The encoding scheme used for the Product ID field is implementation dependent 31 28 Version Version RO 0001 0000010001 27 12 Part ID Part ID RO 010000 JEDEC Continuation A 11 8 Characters JEDEC Continuation Characters RO 0000 7 1 JEDEC ID JEDEC ID RO 0001001 0 Fixed Fixed RO 1 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 2 These bits vary with stepping Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 192 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 8 4 6 RX FIFO Register Overview Intel Table 113 through Table 131 provide an overview of the RX FIFO registers which include the RX FIFO High and Low watermarks Table 113 RX FIFO High Watermark Port 0 0x580 Bit Name Description Default Register Description The default
301. t or removed Ma counter on this port is shown in this register This ae n 0x00000009 register is cleared on Read When TX FIFO on Port 2 becomes full or TX FIFO overflow reset the number of frames lost or removed counter on this port is shown in this register This 0x623 R 00000000 register is cleared on Read When TX FIFO on Port 3 becomes full or TX FIFO overflow frame drop counter reset the number of frames lost or removed 0x624 R 0x00000000 on Port 3 on this port is shown in this register This register is cleared on Read 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 208 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 139 TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0x629 Name Description Address Type Default This register provides the number of packets dropped by the TX FIFO due to the following Data Parity Errors Short SOPs two consecutive SOPs for a port TX FIFO errored with no EOP frame drop counter 0x625 R 0x00000000 on Port 0 Small Packets 9 14 bytes Frames received that are signaled with TERR on the SPI3 TX interface NOTE This register is cleared on Read This register provides the number of packets dropped by the TX FIFO due to the following D
302. t to Low For example reset 0x00000000 of Port 3 implies register value 1000 setting the bit to 1 asserts the port reset 31 4 Reserved Reserved RO 0x0000000 Port 3 3 Port 3 Reset 0 De assert Reset R W 0 1 Assert Reset 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 207 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 137 TX FIFO Port Reset 0x620 Sheet 2 of 2 Bit Name Description Type Default Port 2 2 Port 2 Reset 0 De assert Reset R W 0 1 Assert Reset 1 1 Port 1 Reset 0 De assert Reset R W 0 1 Assert Reset Port 0 0 Port 0 Reset 0 De assert Reset R W 0 1 Assert Reset 1 Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 138 TX FIFO Overflow Frame Drop Counter Ports 0 3 0x621 0x624 Datasheet Name Description Address Type Default When TX FIFO on Port 0 becomes full or ie reset the number of frames lost or removed 0x621 R 0x00000000 Port 0 on this port is shown in this register This register is cleared on Read When TX FIFO on Port 1 becomes full or TX FIFO overflow reset the number of frames los
303. table notes relate to Table 1 and Table 2 1 GMII Ball Connection See Table 16 for connection in RGMII or fiber mode 2 SPI3 Ball Connection See Table 17 for proper SPHY and MPHY connection 3 Fiber Mode Ball Connection See Table 16 for use in RGMII and GMII copper mode Ball List in Alphanumeric Order by Signal Name Ball Signal Name Location AVDD1P8_1 A5 AVDD1P8_1 A20 AVDD1P8_2 T23 AVDD1P8 2 AB16 AVDD2P5 1 AD20 AVDD2P5 2 R18 AVDD2P5 2 U14 CLK125 AD19 COL 0 AB6 COL 1 AB10 COL 2 AD15 COL 3 AB17 CRS 0 AAS CRS 1 AA9 CRS 2 AB15 CRS 3 AC16 DTPA 0 D3 DTPA 1 L1 DTPA 2 A9 DTPA 3 J7 GND B6 GND B10 GND B15 GND B19 Signal Name S Signal Name ct GND D4 GND K14 GND D8 GND K16 GND D12 GND K19 GND D13 GND K23 GND D17 GND L10 GND D21 GND L12 GND F2 GND L13 GND F6 GND L15 GND F10 GND M4 GND F15 GND M8 GND F19 GND M11 GND F23 GND M14 GND H4 GND M17 GND H8 GND M21 GND H12 GND N4 GND H13 GND N8 GND H17 GND N11 GND H21 GND N14 GND J10 GND N17 GND J15 GND N21 GND K2 GND P10 GND K6 GND P12 GND K9 GND P13 GND K11 GND P15 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller
304. ter indicates fragment sizes which is expected on half duplex segments but not on full duplex links and the counter is only fully updated after receipt of a good frame following a fragment NOTE The ShortRuntsThreshold register controls the byte count used to determine the difference between Runts and Shorts and therefore controls which counter is incremented for a given frame Size This counter is only updated after receipt of two good frames NOTE This counter is only valid when the selected port within the IXF1104 MAC is operating in copper RGMII or GMII mode The RuntError counter is not updated when the selected port within the IXF1104 MAC is configured to operated in fiber SerDes mode Port Index 0x35 R 0x00000000 RxShort Errors The total number of packets received that are less than 96 bit times which corresponds to a 4 byte frame with a well formed preamble and SFD This counter indicates fragment sizes illegal in all modes and is only fully updated after reception of a good frame following a fragment NOTE This register is only relevant when the IXF1104 MAC port is configured for copper operation the line side interface is configured for either RGMII or GMII operation This register will not increment when the IXF1104 MAC port is configured for fiber operation using the SerDes interface Port Index 0x36 R 0x00000000 RxCarrier Extend Error Not applicable Port Index 0x37 R 0x0
305. ters Symbol Parameter Min Max Units Trw Reset pulse width 1 0 us Trt Reset recovery time 200 us 153 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 n ntel Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 12 LED AC Timing Specification Figure 52 and Table 58 provide the LED AC timing specifications Figure 52 LED AC Interface Timing gt LED DATA X LED LATCH LO Table 58 LED Interface AC Timing Parameters Symbol Parameter Min Max Units LED cycle time 1 36 1 40 ms Thi LED CLK High time 680 700 us Tlow LED CLK low time 680 700 us Tdatd LED CLK falling edge to LED DATA valid 2 5 ns Tlath LED CLK rising edge to LED LATCH rising edge 690 700 us Tlatl LED_CLK falling edge to LED_LATCH falling edge 690 700 us Datasheet 154 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 8 0 Register Set 8 1 8 2 The registers shown in this section provide access for configuration alarm monitoring and control of the chip Table 59 Control Registers Port Index Offset on page 156 through Table 69 Optical Module Registers 0x799 0x79F on page 162 provide register map details The registers are l
306. the time in nanoseconds from the 1 4 volt point of the reference signal to the 1 4 volt point of the output 4 Maximum propagation delays are measured with a 30 pF load when operating OIF SPI3 standard 104 MHz Over clocked rates of 125 MHz or higher are measured using a load of 20 pF Datasheet 138 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller 7 2 2 Transmit Interface Timing intel Figure 36 and Table 47 illustrate and provide SPI3 transmit interface timing information Figure 36 SPI3 Transmit Interface Timing TFCLK p 4 TStenb THtenb gt TDAT 31 0 a TStdat p q4 THidat TPRTY X 4 I Strpty THtprty y TMOD 1 0 lt _TStmog THtmod TSOP X 4 TStsopp THtsop TEOP lSteopy l THteop gt TERR i 4 Stem y Hterr gt TADR x p TSX 5 DTPA AC R STPA i 4 4 y 139 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 47 SPI3 Transmit Interface Signal Parameters
307. to 1000BASE X optical modules Counters for dropped and errored packets IEEE 802 3 auto negotiation or forced mode Loopback modes Supports SFP MSA compatible transceivers JTAG boundary scan m SPI3 interface supports data transfers up to m 18 u CMOS process technology 4 Gbps in both modes 1 8 V core 2 5 V RGMII GMII OMI and 32 bit Multi PHY mode 133 MHz 3 3 V SPI3 and CPU 4 x 8 bit Single PHY mode 125 MHz m Operating Temperature Ranges m IEEE 802 3 compliant Flow Control Copper Mode 40 C to 85 C Loss less up to 9 6 KB packets and 5 km links Fiber Mode 0 C to 70 C Jumbo frame support for 9 6 KB packets m Package Options m Internal per channel FIFOs 32 KB Rx 10 KB Tx 552 ball Ceramic BGA standard m Flexible 32 16 8 bit CPU interface 552 ball Ceramic RoHS compliant 552 ball Plastic FC BGA contact your Intel Sales Representative Applications m Load Balancing Systems m Base Station Controllers and Transceivers m Mult Service Switches m Serving GPRS Support Nodes SGSN m Web Caching Appliances m Gateway GPRS Support Nodes GGSN m Intelligent Backplane Interfaces m Packet Data Serving Nodes PDSN m Edge Routers m DSL Access Multiplexers DSLAM m Redundant Line Cards m Cable Modem Termination Systems CMTS Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODU
308. trol information start op code etc and Register 0 bit 20 is set to logic 1 Register 0 bit 20 is reset to logic 0 when the frame is complete The steps are identical for Read operation except that in Register 1 bits 15 0 the data is ignored The data received from the MDIO is read by the CPU interface from Register 1 bits 31 16 MDI State Machine The MDI State Machine sequences the information sent to it by the MDIO control registers and keeps track of the current sequence bit count enabling or disabling the MDIO driver output see Figure 22 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Figure 22 MDI State 0 r M Idle MDO 0 MDC EN 0 gt y Go 1 Cnt gt 32 Preamble Y Cnt 32 Cnt 32 MDOE 1 MDO 1 MDC EN 1 Cnt gt 2 4 Start Bits y 2 m lt 2 MDOE 1 Op Code MDO Reg Bit Op Cnt Cnt lt 2 1 MDO Reg_Bit_St Cnt MDC EN 1 MDC EN 0 Y Cnt 2 gt 5 Cnt lt 5 nt lt MDOE 1 ri Phy Addr MDO Reg_Bit_PA Cnt MDC EN 1 Y 5 gt 5 Cnt lt 5 nt lt MDOE 1 Reg MDO Reg MDC EN 1 Y Cnt 5 Cnt gt 2 Cnt 2 MDOE Wr_Op lt Tur
309. tsCollisions Counter32 TxLateCollision Counter 32 RMON specification minus the TxTotalCollision TxLateCollision RxPkts64Octets Same as RMON etherStatsPkts64Octets Counter32 TxPkts64Octets Counter 32 specification RxPkts65to1270Octets Same a RMON etherStatsPkts65to1270Octets Counter32 TxPkts65to127Octets Counter 32 specification RxPkts128to255Octets Same a RMON etherStatsPkts 128to255Octets Counter32 TxPkts128to255Octets Counter32 specification RxPkts256to5110Octets Same a RMON etherStatsPkts256to5110Octets Counter32 TxPkts256to511Octets Counter32 specification RxPkts512to1023Octets Same a RMON etherStatsPkts512to1023Octets Counter32 TxPkts512to10230ctets Counter32 specification RxPkts1023to15180Octets Same as RMON etherStatsPkts 1023to15180Octets Counter32 TxPkts1023to1518Octets Counter32 specification Owner etherStatOwner String Entry etherStatsStatus Status NA NA NA NOTE The RMON specification requires that this is The total number of events where packets were dropped by the probe due to a lack of resources This number is not necessarily the number of packets dropped it is the number of times this condition is detected The RX FIFO Overflow Frame Drop Counter Ports 0 3 0x594 0x597 and TX FIFO Overflow Frame Drop Counter Ports 0 3 0x621 0x624 in the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows If any IXF1104 MAC programmable packet filtering is enab
310. umber 009 Revisio n Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 125 RX FIFO Errored Frame Drop Counter Ports 0 0x5A2 0x5A5 Sheet 1 of 2 Name Description Address Type Default This register counts all frames dropped from the RX FIFO for port 0 by meeting one of the following conditions Frames are removed in conjunction with the RX FIFO Errored Frame RX FIFO Errored Drop Enable 0x59F and the RX Frame Drop Counter Packet Filter Control Port_Index 0x5A2 R 0x00000000 on Port 0 0x19 Frames are greater than the Frame Size Addr Port_Index OxOF This register is cleared on Read This register counts all frames dropped from the RX FIFO for port 1 by meeting one of the following conditions Frames are removed in conjunction with the RX FIFO Errored Frame RX FIFO Errored Drop Enable 0x59F and the RX Frame Drop Counter Packet Filter Control Port_Index 0 5 0 00000000 on Port 1 0x19 Frames are greater than the Frame Size Addr Index OxOF This register is cleared on Read Datasheet 198 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller intel Table 125 RX FIFO Errored Frame Drop Counter Ports 0 3 0x5A2 0x5A5 Sheet 2 of 2 Table 126
311. uplex for proper IXF1104 MAC operation Copper Auto Negotiation In the copper MAC auto negotiation and all other controls of the PHY devices are achieved through the MDIO interface and are independent of the MAC controller See Section 5 5 MDIO Control and Interface on page 99 for further operation details In copper mode auto negotiation is accomplished by the attached PHY not the IXF1104 MAC Thus the IXF1104 MAC does not automatically configure the MAC or other blocks in the device to be consistent with attached PHY auto negotiation results This must be accomplished by the user and system software Jumbo Packet Support The IXF1104 MAC supports jumbo frames The jumbo frame length is dependent on the application and the IXF1104 MAC design is optimized for a 9 6 KB jumbo frame length Larger lengths can be programmed but limited system performance may lead to data loss during certain flow control conditions The value programmed into the Max Frame Size Addr Port Index OxOF determines the maximum length frame size the MAC can receive or transmit without activating any error counters and without truncation Frame Size Addr Index OxOF bits 13 0 set the frame length The default value programmed into this register is OXOSEE 1518 The value is internally adjusted by 4 if the frame has a VLAN tag The overall programmable maximum is Ox3FFF or 16383 bytes 78 Document Number 278757 Revi
312. upply voltage Ope 1 65 2 1 95 Volts AVDD1P8 2 AVDD2P5 1 AVDD2P5 2 2 3 2 7 Volts VDD AVDD1P8_1 0 780 SerDes Operation Operating Current Transmitting and VDD4 receiving in VDD5 _ 0 050 _ Amps 1000 Mbps mode AVDD2P5 1 AVDD2P5 2 VDD2 VDD3 0 246 Amps VDD AVDD1P8_1 0 757 Amps RGMII Operation AVDDIPS 2 Operating Current Transmitting and VDD4 receiving in VDD5 5 0 224 Amps 1000 Mbps mode AVDD2P5 1 AVDD2P5 2 VDD2 VDD3 0 208 0 235 Amps Ambient TOPA 0 x 70 C Recommended Case with heat 5 Him 2 TOPC HS 0 122 C temperature without heat TOPC NHS 0 gt 121 SerDes Operation Transmitting and _ 2 23 2 72 Watts receiving in Power 1000 Mbps mode consumption RGMII Operation Transmitting and _ 2 84 34 Watts receiving in 1000 Mbps mode 7 1 DC Specifications The IXF1104 MAC supports the following I O buffer types 2 5 V CMOS e 33 V LVTTL SerDes 133 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller See Section 5 1 7 Packet Buffer Dimensions on page 80 for additional information regarding I O buffer types The related driver characteristics are described in this section Caution IXF1104 MAC input signals are not 5 V tolerant Devices driving the IXF1104 MAC must provide 3 3 V signal levels or use level shifting buffers to provide 3 3 V compatible levels Othe
313. us for port 1 13 Rx parity sense Port 1 0 Odd Parity R W 0x0 1 Even Parity MPHY Mode NA SPHY Mode Indicates the parity sense to check the parity on RDAT bus for port 0 0 Odd Parity 12 Rx_parity_sense Port 0 1 gt Even Party R W 0x0 1 diis MPHY Mode Indicates the parity sense to check the parity on RDAT bus for all ports 0 Odd Parity 12 Even Parity SPHY Mode 0 Disables the selected SPI3 RX port Rx port enable 1 Enables the selected SPI3 RX port 11 miS R W 0 1 Port 3 MPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected SPI3 RX port SPHY Mode 0 Disables the selected SPI3 RX port Rx port enable 1 Enables the selected SPI3 RX port 10 R W 0 1 Port 2 MPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected SPI3 RX port 1 RO Read Only No clear on Read Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 217 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Table 147 SPI3 Receive Configuration 0x701 Continued Sheet 4 of 4 Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Bit Name Description Default Rx port enable Port 1 SPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected SPI3 RX port MPHY Mode 0 Disables the selected SPI3 RX port 1
314. value the user can configure the TX FIFO to operate in a cut through mode rather than the default store and forward operation mode 0x617 R W 0x000001BE 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write 205 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller Table 135 TX FIFO Overflow Underflow Out of Sequence Event 0x61E Sheet 1 of 2 Bit Name Description Type Default Register Description TX FIFO Out of Sequence Event These register bits provide status information and indicate if out of sequence data has been 0 0 received The bit position equals the port number 8 These bits are cleared on Read Register Description TX FIFO Underflow Event This register provides a status that a FIFO Empty situation has occurred for example a FIFO 0x0 under run The bit position equals the port number 4 This register is cleared on Read Register Description TX FIFO Overflow Event This register provides a status that a FIFO full situation has occurred for example a FIFO 0x0 overflow The bit position equals the port number This register is cleared on Read 31 12 Reserved Reserved RO 0x00000 Port 3 11 FOSE3 0 FIFO out of sequence event
315. ve list of SPI3 signal descriptions SPI3 RX Round Robin Data Transmission The IXF1104 MAC uses a round robin protocol to service each of the 4 ports dependent upon the enable status of the port and if there is data available to be taken from the RX FIFO The round robin order goes from port 0 port 1 port 2 port 3 and back to port 0 A port is skipped and the next port is serviced if it has no available transmit data The data transfer bursts are user configurable burst lengths of 64 128 or 256 bytes The IXF1104 MAC also has a configurable pause interval between data transfer bursts on the receive side of the interface The RX SPI3 burst lengths and the pause interval can be set in the SPI3 Receive Configuration 0x701 MPHY Logical Timing The SPI3 interface AC timing for MPHY can be found in Section 7 2 SPI3 AC Timing Specifications on page 137 Logical timing in the following diagrams illustrates all signals associated with MPHY mode 84 Inte IXF1104 4 Port Gigabit Ethernet Media Access Controller ntel 5 2 2 1 Transmit Timing In MPHY mode a packet transmission starts with the TSX signal indicating port address information is on the data bus The next clock cycle TENB and TSOP indicate present data on the bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted Data transmission can be temporally halted when TENB goes high the
316. y data at the required data rate A transfer to MAC Threshold parameter which is user programmable determines when the FIFO signals to the MAC that it has data to send This is configured for specific block sizes and the user must ensure that an under run does not occur Also the threshold can be set above the maximum size of a normal Ethernet packet This causes the FIFO to send only data to the MAC when this threshold is exceeded or when the End of Packet marker is received This second condition eliminates the possibility of under run except when the controlling switch device fails It can however cause idle times on the media 5 1 7 1 2 RX FIFO The IXF1104 MAC RX FIFOs are provisioned so that each port has its own 32 KB of memory space This is enough memory to ensure that there is never an over run on any channel while transferring normal Ethernet frame size data The FIFOs automatically generate Pause control frames to halt the link partner when the High watermark is reached and to restart the link partner when the data stored in the FIFO falls below the low watermark The RX and TX FIFOs have been sized to support lossless flow control with 9 6 KB packets The RX FIFO has a programmable transfer threshold that sets the threshold at which packets become cut through and starts transitioning to the SPI3 interface before the EOP is received Packets sizes below this threshold are treated as store and forward Once a packet size ex

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