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Intel I5 User's Manual

1. 1 2 Processor Graphics E 4 Stepping Vendor ID Host Device ID Device or Revision ID E 1 8086h 0150h 0162h 09h L 1 8086h 0150h 0162h 09h N 0 8086h 0150h 0152h 09h Notes Li The Vendor ID corresponds to bits 15 0 of the Vendor ID Register located at offset 00h 01h in the PCI function 0 configuration space 2 The Host Device ID corresponds to bits 15 0 of the Device ID Register located at Device 0 offset 02h 03h in the PCI function 0 configuration space 3 The Processor Graphics Device ID DID2 corresponds to bits 15 0 of the Device ID Register located at Device 2 offset 02h 03h in the PCI function 0 configuration space 4 The Revision Number corresponds to bits 7 0 of the Revision ID Register located at offset 08h in the PCI 14 function 0 configuration space Specification Update Component Marking Information intel The processor stepping can be identified by the following component markings Figure 1 Processor Production Top side Markings Example 1 10 BRAND PROC SLxxx SPEED COO FPO amp puzza LOT NO S N Table 1 Processor Identification Sheet 1 of 6 Core Frequency Max Intel GHz Turbo Boost Shared N Processor P Processor DDR3 MHz umber Number Stepping Signature Processor Technology L3 Cache Notes g 2 0 Frequency Size MB Graphics GHz Frequency 4 core 3 1 SROPQ i7 3770T E 1 000306A9h 2 5 1600 650 i 8 2 3 4 5 6 2 core 3
2. BYSTE x x NOE Context of Probe Mode Redirection Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Byes x x gt No Fix Controller Behavior BV96 X X X No Fix IA32 MC5 CTL2 is Not Cleared by a Warm Reset CPUID Instruction May Not Report the Processor Number in the Brand String for BV97 X X X NOFX Intel Core i3 3227U and i5 3337U Processors BV98 X X X No Fix Performance Monitor Counters May Produce Incorrect Results The Corrected Error Count Overflow Bit in 1A32_ MCO STATUS is Not Updated BEER x x NOEN After a UC Error is Logged BV100 X X X No Fix Spurious VT d Interrupts May Occur When the PFO Bit is Set BV101 X X X No Fix Processor May Livelock During On Demand Clock Modulation IA32 VMX VMCS ENUM MSR 48AH Does Not Properly Report The Highest Bv102 x n Hore Index Value Used For VMCS Encoding BV103 X X X No Fix The Upper 32 Bits of CR3 May be Incorrectly Used With 32 Bit Paging BV104 X X X No Fix EPT Violations May Report Bits 11 0 of Guest Linear Address Incorrectly IA32 VMX VMCS ENUM MSR 48AH Does Not Properly Report The Highest BYd05 2 m X NO Index Value Used For VMCS Encoding DMA Remapping Faults for the Graphics VT d Unit May Not Properly Report Type BV106 x x x NOEN of Faulted Request BV107 X X X No Fix Intel amp Trusted Execution Technology ACM Authentication Failure BV108 X X X No Fix Virtual APIC Page Accesses Wit
3. Shared L3 Cache Size MB Notes SRORG i3 3220 L 1 000306A9h 3 3 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 3 SRORE i3 3220T L 1 000306A9h 2 8 1600 650 4 core N A 3 core N A 2 core N A 1 core 2 8 SRORF SRORH i3 3225 i3 3240 L 1 000306A9h 000306A9h 3 3 1600 650 3 4 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 3 4 core N A 3 core N A 2 core N A 1 core 3 4 SRORK i3 3240T 000306A9h 2 9 1600 650 4 core N A 3 core N A 2 core N A 1 core 2 9 SRORQ 15 3330 E 1 000306A9h 3 0 1600 650 4 core 3 0 3 core 3 1 2 core 3 2 1 core 3 2 4 5 6 SROTJ i5 3335S E 1 000306A9h 2 7 1600 650 4 core 2 8 3 core 2 9 2 core 3 1 1 core 3 2 4 5 6 SROWS i5 3350P 000306A9h 3 1 1600 4 core 3 1 3 core 3 2 2 core 3 3 1 core 3 3 4 5 6 SROUF G2120 P 0 000306A9h 3 1 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 1 SROUJ G2100T 000306A9h 2 6 1600 650 4 core N A 3 core N A 2 core N A 1 core SRORF 13 3225 L 1 000306A9h 3 3 1600 650 4 core 3 core 2 core 1 core 2 4 SRORG i3 3220 L 1 000306A9h 3 3 1600 650 4 core 3 core 2 core 1 core N 2 4 18 Specification Update Table 1 Processor Identifi
4. 1600 650 3 5 1600 0 4 core 3 7 3 core 3 8 2 core 3 9 1 core 3 9 4 core 3 7 3 core 3 8 2 core 3 9 1 core 3 9 2 3 4 5 6 2 3 4 5 6 SROPB E3 1265LV2 000306A9h 2 5 1600 650 4 core 3 1 3 core 3 2 2 core 3 4 1 core 3 5 2 3 4 5 6 SROP9 E3 1245V2 E 1 000306A9h 3 4 1600 650 4 core 3 6 3 core 3 7 2 core 3 8 1 core 3 8 2 3 4 5 6 SROP5 E3 1240V2 E 1 000306A9h 3 4 1600 0 4 core 3 6 3 core 3 7 2 core 3 8 1 core 3 8 2 3 4 5 6 SROP4 E3 1230V2 000306A9h 3 3 1600 0 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 7 2 3 4 5 6 SROPJ E3 1225V2 E 1 000306A9h 3 2 1600 650 4 core 3 4 3 core 3 5 2 core 3 6 1 core 3 6 3 4 5 6 SROPH E3 1220V2 000306A9h 3 1 1600 4 core 3 3 3 core 3 4 2 core 3 5 1 core 3 5 3 4 5 6 SROR6 E3 1220LV2 L 1 000306A9h 2 3 1600 0 4 core 0 3 core 0 2 core 3 3 1 core 3 5 2 3 4 5 6 SRORJ i5 3470T L1 000306A9h 2 9 1600 650 4 core 0 3 core 0 2 core 3 3 1 core 3 6 2 3 4 5 6 Specification Update 17 intel Table 1 Processor Identification Sheet 4 of 6 Number Processor Number Stepping Processor Signature Core Frequency GHz DDR3 MHz Processor Graphics Frequency Max Intel Turbo Boost Technology 2 0 Frequency GHz
5. 3 core 3 4 2 core 3 5 1 core 3 5 4 6 SROT9 i5 3570S N 0 000306A9h 3 1 1600 650 4 core 3 4 3 core 3 5 2 core 1 core d N 3 4 5 6 SROT7 i5 3570 N 0 000306A9h 3 4 1600 650 4 core 3 core 2 core 1 core 3 4 5 6 SROTA i5 3470S N 0 000306A9h 2 9 1600 650 4 core 3 core 2 core 1 core 3 4 5 6 SROT8 i5 3470 N 0 000306A9h 3 2 1600 650 4 core 3 core 2 core 1 core ww ww ww ww ww w U S DQUUWNI CO OND w w ao 3 4 5 6 SRORR i5 3330S E 1 000306A9h 2 7 1600 650 4 core 3 core 2 core 1 core 3 2 wN N me O 4 5 6 SRORQ i5 3330 E 1 000306A9h 3 1600 650 4 core 3 3 core 3 1 2 core 3 2 1 core 3 2 4 5 6 16 Specification Update Table 1 Processor Identification Sheet 3 of 6 Number Processor Number Stepping Processor Signature Core Frequency GHz DDR3 MHz Processor Graphics Frequency Max Intel Turbo Boost Technology 2 0 Frequency GHz Shared L3 Cache Size MB Notes SROPC E3 1290V2 E 1 000306A9h 3 7 1600 0 4 core 3 8 3 core 3 9 2 core 4 1 core 4 1 2 3 4 5 6 SROP7 E3 1280V2 E 1 000306A9h 3 6 1600 0 4 core 3 7 3 core 3 8 2 core 3 9 1 core 4 2 3 4 5 6 SROPA SROP6 E3 1275V2 E3 1270V2 E 1 000306A9h 000306A9h 3 5
6. Maximum None identified For the steppings affected see the Summary Tables of Changes Specification Update 35 intel BV52 Problem Implication Workaround Status BV53 Problem Implication Workaround Status BV54 Problem Implication Workaround Status BV55 Problem Implication Workaround Status 36 I nstructions Retired Event May Over Count Execution of I RET Instructions Under certain conditions the performance monitoring event Instructions Retired Event COH Unmask 00H may over count the execution of IRET instruction Due to this erratum performance monitoring event Instructions Retired may over count None identified For the steppings affected see the Summary Tables of Changes PCle Link May Unexpectedly Exit Loopback State The PCle Port is capable of functioning as 3 independent PCle controllers Due to this erratum if more than one of the controllers is in Loopback Active state and configured as a loopback slave and if any one of these controllers transition to Loopback Exit all controllers in Loopback Active will transition to Loopback Exit Loopback Active state on a given Link may unexpectedly exit Software should avoid configuring more than one of the PCle Controllers as Loopback slave concurrently PCIe endpoints should avoid configuring more than one of PCIe Controllers as Loopback slave For the steppings affected see the Summary Tabl
7. Turbo Boost Technology requires a system with Intel Turbo Boost Technology Intel Turbo Boost Technology and Intel Turbo Boost Technology 2 0 are only available on select Intel processors Consult your PC manufacturer Performance varies depending on hardware software and system configuration For more information visit http www intel com go turbo Intel Hyper Threading Technology requires an Intel HT Technology enabled system check with your PC manufacturer Performance will vary depending on the specific hardware and software used Not available on Intel Core i5 750 For more information including details on which processors support HT Technology visit http www intel com info hyperthreading Intel 64 architecture requires a system with a 64 bit enabled processor chipset BIOS and software Performance will vary depending on the specific hardware and software you use Consult your PC manufacturer for more information For more information visit http www intel com info em64t Intel Intel Core Pentium and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2012 2013 Intel Corporation All rights reserved 2 Specification Update Contents i n tel j Contents Revision History ie ertet tet t etie alude aaa 5 Preface oec ML m ee E 6 Summary Tables of Changes i 8 Identification Inf
8. 4 core N A 3 core N A 2 core N A 1 core 2 3 SROYW i3 3250T P 0 000306A9h 3 0 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 0 2 4 Specification Update 19 intel Table 1 Processor Identification Sheet 6 of 6 Core Frequency Max Intel GHz Turbo Boost Shared Processor i Processor DDR3 MHz so eg L3 ra Not Number Number Stepping Signature Processor echnology c sace ores G E 2 0 Frequency Size MB raphics 1 F GHz requency 4 core N A SROYX i3 3250 P 0 000306A9h 3 5 1600 650 3 core Me 3 2 4 2 core N A 1 core 3 5 4 core N A SROYL i3 3245 L 1 000306A9h 3 4 1600 650 EN 3 2 4 2 core N A 1 core 3 4 4 core N A SROYT G2140 P 0 000306A9h 3 3 1600 650 SRO 3 4 2 core N A 1 core 3 3 4 core N A SROYV G2120T P 0 000306A9h 2 7 1600 650 ee NA 3 4 2 core N A 1 core 2 7 4 core N A SR163 G2030 N 0 000306A9h 3 1600 650 FOr N A 3 4 2 core N A 1 core 3 4 core N A SR164 G2030T P 0 000306A9h 2 6 1600 650 3 core N A 3 4 7 2 core N A 1 core 2 6 Notes 1 This column indicates maximum Intel Turbo Boost Technology 2 0 frequency GHz for 4 3 2 or 1 cores active respectively 2 Intel Hyper Threading Technology enabled 3 Intel Trusted Execution Technology I ntel TXT enabled 4 Intel Virtualization Technology for 1A 32 Intel 64 and Intel Architecture Intel VT x enabled 5 I
9. Incorrectly Set BV48 X X X No Fix BV49 X X X No Fix Accessing Physical Memory Space 0 640K through the Graphics Aperture May avo x x x Ey Cause Unpredictable System Behavior BV51 X X X No Fix PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full BV52 X X X No Fix Instructions Retired Event May Over Count Execution of IRET Instructions BV53 X X X No Fix PCle Link May Unexpectedly Exit Loopback State BV54 X X X No Fix The RDRAND Instruction Will Not Execute as Expected BV55 x x x No Fix du That Initially Transmits Minimal Posted Data Credits May Cause a BV56 X X X No Fix PCI Express Gen3 Receiver Return Loss May Exceed Specifications Direct Access Via VT d to The Processor Graphics Device May Lead to a System BV57 X X X No Fix Hang An Event May Intervene Before a System Management Interrupt That Results from BV58 X X X No Fix IN or INS PCle May Associate Lanes That Are Not Part of Initial Link Training to LO During BV59 X X X NoF X Upcontiguration 10 Specification Update Errata Sheet 4 of 5 Steppings Number Status ERRATA E 1 L 1 N 0 The Processor May Not Comply With PCle Equalization Preset Reflection BYRD 7 2 X DOE Requirements for 8 GT s Mode of Operation BV61 X X X No Fix Processor May Issue PCle EIEOS at Incorrect Rate Reduced Swing Ou
10. and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new Specification Changes in this Specification Update revision Specification Update 53 intel Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new Specification Changes in this Specification Update revision 54 Specification Update intel Documentation Changes The Documentation Changes listed in this section apply to the following documents Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software D
11. before or in lieu of a GP fault Instructions of greater than 15 bytes in length can only occur if redundant prefixes are placed before the instruction None identified For the steppings affected see the Summary Tables of Changes Specification Update BV8 Problem Implication Workaround Status BV9 Problem Implication Workaround Status BV10 Problem Implication Workaround Status LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace Store and BTM Branch Trace Message mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instruction at the lower canonical boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1 s Subsequent BTS and BTM operations which report the LBR will also be incorrect LBR BTS and BTM may report incorrect information in the event of an exception interrupt None identified For the steppings affected see the Summary Tables of Changes Incorrect Address Computed For Last Byte of FXSAVE FXRSTOR or XSAVE XRSTOR I mage Leads to Partial Memory Update A partial memory state save of the FXSAVE or XSAVE image or a partial memory state restore of the FXRS
12. breakpoints matched during the MOV POP SS when the following instruction is either an REP MOVSB or REP STOSB When this erratum occurs DR6 may not contain information about all breakpoints matched This erratum will not be observed under the recommended usage of the MOV SS r m or POP SS instructions i e following them only with an instruction that writes E R SP None identified For the steppings affected see the Summary Tables of Changes Setting Hardware Autonomous Speed Disable Configuration Bit Will Block I nitial Speed Upgrade The PCI Express Base Specification Revision 3 0 states that the Hardware Autonomous Speed Disable bit Link Control Register 2 bit 5 does not block the initial transition to the highest supported common link speed Setting this bit will block all autonomous speed changes Due to this erratum if the Hardware Autonomous Speed Disable bit is set a given PCle link may remain at 2 5 GT s transfer rate This erratum has not been observed with any commercially available add in cards It is possible for software to initiate a directed speed change For the steppings affected see the Summary Tables of Changes LTR Message is Not Treated as an Unsupported Request The PCle root port does not support LTR Latency Tolerance Reporting capability However a received LTR message is not treated as a UR Unsupported Request Due to this erratum an LTR message does not generate a UR error None identified
13. loss of a debug exception when it happens concurrently with the execution of GETSEC SEXIT Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes VM Exits Due to GETSEC May Save an Incorrect Value for Blocking by STI in the Context of Probe Mode Redirection The GETSEC instruction causes a VM exit when executed in VMX non root operation Such a VM exit should set bit 0 in the Interruptability state field in the virtual machine control structure VMCS if the STI instruction was blocking interrupts at the time GETSEC commenced execution Due to this erratum a VM exit executed in VMX non root operation may erroneously clear bit 0 if redirection to probe mode occurs on the GETSEC instruction After returning from probe mode a virtual interrupt may be incorrectly delivered prior to GETSEC instruction Intel has not observed this erratum with any commercially software None identified For the steppings affected see the Summary Tables of Changes Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior Specific source copy blitter instructions in Intel HD Graphics 2500 and 4000 Processor may result in unpredictable behavior when a blit source and destination overlap Due to this erratum the processor may exhibit unpredictable graphics controller behavior Intel has not observed this erratum
14. occur unless initiated by the downstream component This erratum does not affect the ability of the downstream component to initiate a link speed change All known 5 0Gb s capable PCIe downstream components have been observed to initiate the link speed change without relying on the root port to do so Due to this erratum the PCle root port may not initiate a link speed change during some hardware scenarios causing the PCle link to operate at a lower than expected speed Intel has not observed this erratum with any commercially available platform None identified For the steppings affected see the Summary Tables of Changes Successive Fixed Counter Overflows May be Discarded Under specific internal conditions when using Freeze PerfMon on PMI feature bit 12 in IA32 DEBUGCTL Freeze PerfMon on PMI MSR 1D9H if two or more PerfMon Fixed Counters overflow very closely to each other the overflow may be mishandled for some of them This means that the counter s overflow status bit in MSR PERF GLOBAL STATUS MSR 38EH may not be updated properly additionally PMI interrupt may be missed if software programs a counter in Sampling Mode PMI bit is set on counter configuration Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is used Software can avoid this by 1 Avoid using Freeze PerfMon on PMI bit 2 Enable only one fixed counter at a time when using Freeze PerfMon on PMI For the steppings affected se
15. of a UD exception Software should always set the vvvv field of the VEX prefix to 1111b for instances of the VAESIMC and VAESKEYGENASSIST instructions For the steppings affected see the Summary Tables of Changes Unexpected UD on VZEROALL VZEROUPPER Execution of the VZEROALL or VZEROUPPER instructions in 64 bit mode with VEX W set to 1 may erroneously cause a UD invalid opcode exception The affected instructions may produce unexpected invalid opcode exceptions in 64 bit mode Compilers should encode VEX W 0 for the VZEROALL and VZEROUPPER instructions For the steppings affected see the Summary Tables of Changes Specification Update BV71 Problem Implication Workaround Status BV72 Problem Implication Workaround Status BV73 Problem Implication Workaround Status PCI e Root Port May Not I nitiate Link Speed Change The PCIe Base specification requires the upstream component to maintain the PCIe link at the target link speed or the highest speed supported by both components on the link whichever is lower PCle root port will not initiate the link speed change without being triggered by the software when the root port maximum link speed is configured to be 5 0 GT s System BIOS will trigger the link speed change under normal boot scenarios However BIOS is not involved in some scenarios such as link disable re enable or secondary bus reset and therefore the speed change may not
16. of the FRCD REG register in the remapping hardware memory map register set Due to this erratum the request type may not be reported correctly Software processing the DMA remapping faults may not be able to determine the type of faulting graphics device DMA request None identified For the steppings affected see the Summary Tables of Changes Intel Trusted Execution Technology ACM Authentication Failure SINIT ACM 3rd gen i5 i7 SINIT 51 BIN or earlier are revoked and will not launch with new processor configuration information Due to this erratum SINIT ACM 3rd gen i5 i7 SINIT 51 BIN or earlier will fail to run It is possible for the BIOS to contain a workaround for this erratum All Intel TXT enabled software must use SINIT ACM 3rd gen i5 i7 SINIT 67 BIN or later For the steppings affected see the Summary Tables of Changes Specification Update 51 BV108 Problem Implication Workaround Status BV109 Problem Implication Workaround Status 52 Virtual API C Page Accesses With 32 Bit PAE Paging May Cause a System Crash If a logical processor has EPT Extended Page Tables enabled is using 32 bit PAE paging and accesses the virtual APIC page then a complex sequence of internal processor micro architectural events may cause an incorrect address translation or machine check on either logical processor This erratum may result in unexpected faults an uncorrectable TLB error logged in IA32
17. the counter overflow Due to this erratum if the counter overflow occurs after execution of either MOV SS or STI storage of the PEBS record is delayed by one instruction When this erratum occurs software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI The state information in the PEBS record will also reflect the one instruction delay None identified Specification Update 25 BV17 Problem Implication Workaround Status BV18 Problem Implication Workaround Status BV19 Problem Implication Workaround Status BV20 Problem Implication Workaround Status 26 PEBS Record not Updated when in Probe Mode When a performance monitoring counter is configured for PEBS Precise Event Based Sampling overflows of the counter can result in storage of a PEBS record in the PEBS buffer Due to this erratum if the overflow occurs during probe mode it may be ignored and a new PEBS record may not be added to the PEBS buffer Due to this erratum the PEBS buffer may not be updated by overflows that occur during probe mode None identified For the steppings affected see the Summary Tables of Changes MONI TOR or CLFLUSH on the Local XAPI C s Address Space Results in Hang If the target linear address range for a MONITOR or CLFLUSH is mapped to the local XAPIC s address space the processor will hang When this erratum o
18. 32 Architectures Software Developer s Manual P p i i manuals index htm Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Intel 64 and I A 32 Intel Architecture Optimization Reference Manual http www intel com design processor specupdt 252046 htm ACPI Specifications www acpi info Intel 64 and IA 32 Architectures Software Developer s Manual Documentation Changes 6 Specification Update intel Nomenclature Note Errata are design defects or errors These may cause the processor behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices S Spec Number is a five digit code used to identify products Products are differentiated by their unique characteristics such as core speed L2 cache size package type etc as described in the processor identification information table Read all notes associated with each S Spec number Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in an
19. 6 1 core 3 7 4 core 3 5 SROPN i7 3770S E 1 000306A9h 3 1 1600 650 Bearer 3 8 8 2 3 4 5 6 2 core 3 8 1 core 3 9 4 core 3 7 SROPL i7 3770K E 1 000306A9h 3 5 1600 650 Tiene 98 8 2 4 6 2 core 3 9 1 core 3 9 4 core 3 7 SROPK i7 3770 E 1 000306A9h 3 4 1600 650 adus 8 2 3 4 5 6 2 core 3 9 1 core 3 9 4 core 2 9 SROP1 i5 3570T E 1 000306A9h 2 3 1600 650 donee d 6 3 4 5 6 2 core 3 2 1 core 3 3 Specification Update 15 intel Table 1 Processor Identification Sheet 2 of 6 Number Processor Number Stepping Processor Signature Core Frequency GHz DDR3 MHz Processor Graphics Frequency Max Intel Turbo Boost Technology 2 0 Frequency GHz Shared L3 Cache Size MB Notes SROP3 i5 3550S E 1 000306A9h 3 1600 650 4 core 3 3 3 core 3 4 2 core 3 6 1 core 3 7 3 4 5 6 SROPM i5 3570K E 1 000306A9h 3 4 1600 650 4 core 3 6 3 core 3 7 2 core 3 8 1 core 3 8 4 6 SROPO SROPP i5 3550 E 1 i5 3475S E 1 000306A9h 000306A9h 3 3 1600 650 2 9 1600 650 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 7 4 core 3 2 3 core 3 3 2 core 3 5 1 core 3 6 3 4 5 6 3 4 5 6 SROP2 i5 3450S E 1 000306A9h 2 8 1600 650 4 core 3 1 3 core 3 2 2 core 3 4 1 core 3 5 4 6 SROPF 15 3450 E 1 000306A9h 3 1 1600 650 4 core 3 3
20. Desktop 3rd Generation Intel Core Processor Family Specification Update September 2013 Revision 015 Reference Number 326766 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR AN
21. Fix Unused PCle Lanes May Report Correctable Errors BV80 X X X No Fix RDMSR of IA32 PERFEVTSEL 4 7 May Return Erroneous Information BV81 X X X No Fix PCle Link May Fail Link Width Upconfiguration BV82 X X X No Fix Graphics L3 Cache Parity Errors May Not be Detected A PCle Link That is in Link Disable State May Prevent DDR I O Buffers From BEG d 5 x Nous Entering a Power Gated State BV84 X X X No Fix REP MOVSB May Incorrectly Update ECX ESI and EDI BV85 X X X No Fix Performance Counter Overflow Indication May Cause Undesired Behavior BV86 X X X No Fix RDMSR of IA32 PERFEVTSEL4 7 May Return an Incorrect Result BV87 X X X No Fix VEX L is Not Ignored with VCVT 2SI Instructions BV88 x x x No Fix li Changing the Memory Type and Page Size May Lead to a System BV89 X X X No Fix MCI ADDR May be Incorrect For Cache Parity Errors Specification Update 11 intel Errata Sheet 5 of 5 Steppings Number Status ERRATA E 1 L 1 N 0 During Package Power States Repeated PCle and or DMI L1 Transitions May BV90 X X X No Fix Cause a System Instruction Fetches Page Table Walks May be Made Speculatively to Uncacheable BV91 X X X No Fix Memory The Processor May Not Properly Execute Code Modified Using A Floating Point BV92 X X X No Fix Store BV93 X X X No Fix Execution of GETSEC SEXIT May Cause a Debug Exception to be Lost VM Exits Due to GETSEC May Save an Incorrect Value for Blocking by STI in the
22. For the steppings affected see the Summary Tables of Changes Specification Update BV48 Problem Implication Workaround Status BV49 Problem Implication Workaround Status BV50 Problem Implication Workaround Status BV51 Problem Implication Workaround Status 64 bit REP MOVSB STOSB May Clear The Upper 32 bits of RCX RDI And RSI Before Any Data is Transferred If a REP MOVSB STOSB is executed in 64 bit mode with an address size of 32 bits and if an interrupt is being recognized at the start of the instruction operation the upper 32 bits of RCX RDI and RSI may be cleared even though no data has yet been copied or written Due to this erratum the upper 32 bits of RCX RDI and RSI may be prematurely cleared It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes An Interrupt Recognized Prior to First Iteration of REP MOVSB STOSB May Result EFLAGS RF Being Incorrectly Set If a REP MOVSB STOSB is executed and an interrupt is recognized prior to completion of the first iteration of the string operation EFLAGS may be saved with RF 1 even though no data has been copied or stored The Software Developer s Manual states that RF will be set to 1 for such interrupt conditions only after the first iteration is complete Software may not operate correctly if it relies on the value saved for EFLAGS RF w
23. MCi STATUS MCACOD bits 15 0 with a value of 0000 0000 0001 xxxxb where x stands for 0 or 1 a guest or hyper visor crash or other unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Address Translation Faults for Intel VT d May Not be Reported for Display Engine Memory Accesses The Intel VT d Intel Virtualization Technology for Directed I O hardware unit supporting the Processor Graphics device Bus 0 Device 2 Function 0 may not report address translation faults detected on Display Engine memory accesses when the Context Cache is disabled or during time periods when Context Cache is being invalidated Due to this erratum Display Engine accesses that fault are correctly aborted but may not be reported in the FSTS_REG fault reporting register GFXVTDBAR offset 034H None identified For the steppings affected see the Summary Tables of Changes Specification Update intel Specification Changes The Specification Changes listed in this section apply to the following documents Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64
24. No Fix APIC Error Received Illegal Vector May be Lost BV24 X X X No Fix Changing the Memory Type for an In Use Page Translation May Lead to Memory Ordering Violations BV25 X X X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures BV26 X X X No Fix LBR BTM or BTS Records May have Incorrect Branch From Information After an EIST T state S state C1E Transition or Adaptive Thermal Throttling BV27 X X X No Fix Fault Not Reported When Setting Reserved Bits of Intel VT d Queued Invalidation Descriptors BV28 X X X No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode VMREAD VMWRITE Instruction May Not Fail When Accessing an Unsupported BV29 X X X No Fix Field in VMCS BV30 X X X No Fix Spurious Interrupts May be Generated From the Intel VT d Remap Engine i Malformed PCle Transactions May be Treated as Unsupported Requests Instead of BVSL NOIR as Critical Errors Reception of Certain Malformed Transactions May Cause PCle Port to Hang BV32 5 NO FIK Rather Than Reporting an Error intel Errata Sheet 3 of 5 Steppings Number Status ERRATA E 1 L 1 N 0 BV33 X X X No Fix Clock Modulation Duty Cycle Cannot be Programmed to 6 25 BV34 X X X No Fix Processor May Fail to Acknowledge a TLP Request BV35 X X X No Fix An Unexpected PMI May Occur After Writing a Large V
25. No Fix Preempted i LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs Bva X X X NoFPC in 64 bit Mode BV9 x x x No Fix Incorrect Address Computed For Last Byte of FKSAVE FXRSTOR or XSAVE XRSTOR Image Leads to Partial Memory Update BV10 X X X No Fix Values for LBR BTS BTM Will be Incorrect after an Exit from SMM EFLAGS Discrepancy on Page Faults and on EPT Induced VM Exits after a Bult X x x No Fix Translation Change BV12 X X X No Fix BO B3 Bits in DR6 For Non Enabled Breakpoints May be Incorrectly Set BV13 X X x No Fix E aa Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB i Debug Exception Flags DR6 B0 B3 Flags May be Incorrect for Disabled BV14 X X X No Fix Breakpoints BV15 X X X No Fix LER MSRs May Be Unreliable BV16 X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI BV17 X X X No Fix PEBS Record not Updated when in Probe Mode BV18 X X X No Fix MONITOR or CLFLUSH on the Local XAPIC s Address Space Results in Hang BV19 X X X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word i An Uncorrectable Error Logged in IA32 CR MC2 STATUS May also Result in a BV20 X X X No Fix System Hang GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not BYAT 5 x Noi Provide Correct Exception Error Code DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is By22 a di x No Fix Followed by a Store or an MMX Instruction BV23 X X X
26. PESTRI and VPCMPESTRM should support a 64 bit length operation with RAX RDX Due to this erratum the length registers are incorrectly interpreted as 32 bit values Due to this erratum using REX W 1 with PCMPESTRI and PCMPESTRM as well as VEX W 1 with VPCMPESTRI and VPCMPESTRM do not result in promotion to 64 bit length registers It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Multiple Performance Monitor I nterrupts are Possible on Overflow of Fixed Counter O The processor can be configured to issue a PMI performance monitor interrupt upon overflow of the IA32 FIXED CTRO MSR 309H A single PMI should be observed on overflow of IA32 FIXED CTRO however multiple PMIs are observed when this erratum occurs This erratum only occurs when 1A32 FIXED CTRO overflows and the processor and counter are configured as follows Intel Hyper Threading Technology is enabled A32 FIXED CTRO local and global controls are enabled A32 FIXED CTRO is set to count events only on its own thread IA32 FIXED CTR CTRL MSR 38DH bit 2 0 e PMIs are enabled on IA32 FIXED CTRO IA32 FIXED CTR CTRL MSR bit 3 1 Freeze on PMI feature is enabled 1A32 DEBUGCTL MSR 1D9H bit 12 1 When this erratum occurs there may be multiple PMIs observed when IA32 FIXED CTRO overflows Disable the FREEZE PERFMON ON PMI feature in IA32 DEBUGCTL MSR 1D9H bi
27. Summary Tables of Changes VMREAD VMWRI TE I nstruction May Not Fail When Accessing an Unsupported Field in VMCS The Intel 64 and I A 32 Architectures Software Developer s Manual Volume 2B states that execution of VMREAD or VMWRITE should fail if the value of the instruction s register source operand corresponds to an unsupported field in the VMCS Virtual Machine Control Structure The correct operation is that the logical processor will set the ZF Zero Flag write OCH into the VM instruction error field and for VMREAD leave the instruction s destination operand unmodified Due to this erratum the instruction may instead clear the ZF leave the VM instruction error field unmodified and for VMREAD modify the contents of its destination operand Accessing an unsupported field in VMCS will fail to properly report an error In addition VMREAD from an unsupported VMCS field may unexpectedly change its destination operand Intel has not observed this erratum with any commercially available software Software should avoid accessing unsupported fields in a VMCS For the steppings affected see the Summary Tables of Changes Specification Update 29 BV30 Problem Implication Workaround Status BV31 Problem Implication Workaround Status BV32 Problem Implication Workaround Status BV33 Problem Implication Workaround Status 30 Spurious Interrupts May be Generated From the I
28. TOR or XRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16 bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32 bit mode FXSAVE FXRSTOR or XSAVE XRSTOR will incur a GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored Software should avoid memory accesses that wrap around the respective 16 bit and 32 bit mode memory limits For the steppings affected see the Summary Tables of Changes Values for LBR BTS BTM Will be Incorrect after an Exit from SMM After a return from SMM System Management Mode the CPU will incorrectly update the LBR Last Branch Record and the BTS Branch Trace Store hence rendering their data invalid The corresponding data if sent out as a BTM on the system bus will also be incorrect Note This issue would only occur when one of the 3 above mentioned debug support facilities are used The value of the LBR BTS and BTM immediately after an RSM operation should not be used None identified For the steppings affected see the Summary Tables of Changes Specification Update 23 intel BV11 Problem Implication Workaround Status BV12 Problem Implication Workaround Status 24 EFLAGS Discrepancy on Page Faults and on EPT I nduced VM Exits after a Translation Change This erratum is regarding the case where paging str
29. Y OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult your PC manufacturer For more information visit http Awww intel com go virtualization Intel
30. alue to IA32 FIXED CTR2 A Write to the IA32 FIXED CTR1 MSR May Result in Incorrect Value in Certain BV36 X X X No Fix Conditions BV37 X X X No Fix PCle LTR Incorrectly Reported as Being Supported PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have BV38 X X X No Fix Occurred GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch BV39 X X X NoFix netruofione BV40 X X X No Fix Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered PCI Express Differential Peak Peak Tx Voltage Swing May Violate the Specification PCMPESTRI PCMPESTRM VPCMPESTRI and VPCMPESTRM Always Operate with 32 bit Length Registers BV41 X X X No Fix BV42 X X X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter BV43 X X X No Fix 0 BV44 X X X No Fix IA32 FEATURE CONTROL MSR May be Uninitialized on a Cold Reset DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is BV X X X NoFix Followed by a REP MOVSB or STOSB Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial BV46 X X X No Fix Speed Upgrade BV47 X X X No Fix LTR Message is Not Treated as an Unsupported Request 64 bit REP MOVSB STOSB May Clear The Upper 32 bits of RCX RDI And RSI Before Any Data is Transferred An Interrupt Recognized Prior to First Iteration of REP MOVSB STOSB May Result EFLAGS RF Being
31. are read as 0 This can occur only if the DCR Divide Configuration Register is greater than or equal to 4 The erratum does not occur if software writes zero to the Initial Count Register before reading the LVT and IRR bits Software that relies on reads of the LVT and IRR bits to determine whether a timer interrupt is being delivered may not operate properly Software that uses the local APIC timer must be prepared to handle the timer interrupts even those that would not be expected based on reading CCR and the LVT and IRR bits alternatively software can avoid the problem by writing zero to the Initial Count Register before reading the LVT and IRR bits For the steppings affected see the Summary Tables of Changes Specification Update BV41 Problem Implication Workaround BV42 Problem Implication Workaround Status BV43 Problem Implication Workaround Status PCI Express Differential Peak Peak Tx Voltage Swing May Violate the Specification Under certain conditions including extreme voltage and temperature the peak peak voltage may be higher than the specification Violation of PCI Express amp Base Specification of the VTX DIFF PP voltage No failures have been observed due to this erratum None identified PCMPESTRI PCMPESTRM VPCMPESTRI and VPCMPESTRM Always Operate with 32 bit Length Registers In 64 bit mode using REX W 1 with PCMPESTRI and PCMPESTRM or VEX W 1 with VPCM
32. ay store an incorrect value into bits 11 0 of this field The processor correctly stores the guest physical address of the paging structure entry into the guest physical address field in the VMCS Software may not be easily able to determine the page offset of the original memory access that caused the EPT violation Intel has not observed this erratum to impact the operation of any commercially available software Software requiring the page offset of the original memory access address can derive it by simulating the effective address computation of the instruction that caused the EPT violation For the steppings affected see the Summary Tables of Changes IA32 VMX VMCS ENUM MSR 48AH Does Not Properly Report The Highest I ndex Value Used For VMCS Encoding IA32 VMX VMCS ENUM MSR 48AH bits 9 1 report the highest index value used for any VMCS encoding Due to this erratum the value 21 is returned in bits 9 1 although there is a VMCS field whose encoding uses the index value 23 Software that uses the value reported in IA32 VMX VMCS ENUM 9 1 to read and write all VMCS fields may omit one field None identified For the steppings affected see the Summary Tables of Changes DMA Remapping Faults for the Graphics VT d Unit May Not Properly Report Type of Faulted Request When a fault occurs during DMA remapping of Graphics accesses at the Graphics VT d unit the type of faulted request read or write should be reported in bit 126
33. bits 3 0 in DR6 may be incorrectly set for non enabled breakpoints when the following sequence happens 1 MOV or POP instruction to SS Stack Segment selector 2 Next instruction is FP Floating Point that gets FP assist 3 Another instruction after the FP instruction completes successfully 4 A breakpoint occurs due to either a data breakpoint on the preceding instruction or a code breakpoint on the next instruction Due to this erratum a non enabled breakpoint triggered on step 1 or step 2 may be reported in BO B3 after the breakpoint occurs in step 4 Due to this erratum BO B3 bits in DR6 may be incorrectly set for non enabled breakpoints Software should not execute a floating point instruction directly after a MOV SS or POP SS instruction For the steppings affected see the Summary Tables of Changes Specification Update BV13 Problem Implication Workaround Status BV14 Problem Implication Workaround Status BV15 Problem Implication Workaround Status BV16 Problem Implication Workaround MCi Status Overflow Bit May Be Incorrectly Set on a Single I nstance of a DTLB Error A single Data Translation Look Aside Buffer DTLB error can incorrectly set the Overflow bit 62 in the MCi Status register A DTLB error is indicated by MCA error code bits 15 0 appearing as binary value 000x 0000 0001 0100 in the MCi Status register Due to this erratum th
34. bles of Changes The Corrected Error Count Overflow Bit in 1A32 MCO STATUS is Not Updated After a UC Error is Logged When a UC uncorrected error is logged in the IA32 MCO STATUS MSR 401H corrected errors will continue to update the lower 14 bits bits 51 38 of the Corrected Error Count Due to this erratum the sticky count overflow bit bit 52 of the Corrected Error Count will not get updated after a UC error is logged The Corrected Error Count Overflow indication will be lost if the overflow occurs after an uncorrectable error has been logged None identified For the steppings affected see the Summary Tables of Changes Specification Update 49 BV100 Problem Implication Workaround Status BV101 Problem Implication Workaround Status BV102 Problem Implication Workaround Status BV103 Problem Implication Workaround Status 50 Spurious VT d Interrupts May Occur When the PFO Bit is Set When the PFO Primary Fault Overflow field bit 0 in the VT d FSTS Fault Status register is set to 1 further faults should not generate an interrupt Due to this erratum further interrupts may still occur Unexpected Invalidation Queue Error interrupts may occur Intel has not observed this erratum with any commercially available software Software should be written to handle spurious VT d fault interrupts For the steppings affected see the Summary Tables of Changes Pro
35. cation Sheet 5 of 6 Number Processor Number Stepping Processor Signature Core Frequency GHz DDR3 MHz Processor Graphics Frequency Max Intel Turbo Boost Technology 2 0 Frequency GHz Shared L3 Cache Size MB Notes SROPL i7 3770K E 1 000306A9h 3 5 1600 650 4 core 3 7 3 core 3 8 2 core 3 9 1 core 3 9 2 4 6 SROPN i7 3770S E 1 000306A9h 3 1 1600 650 4 core 3 5 3 core 3 6 2 core 3 8 1 core 3 9 2 3 4 5 6 SROPQ i7 3770T E 1 000306A9h 2 5 1600 650 4 core 3 1 3 core 3 4 2 core 3 6 1 core 3 7 2 3 4 5 6 SROYU G2130 000306A9h 3 2 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 2 SROYY i3 3210 P 0 000306A9h 3 2 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 2 2 4 SR10G G2020T P 0 000306A9h 2 5 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 5 SR10H G2020 P 0 000306A9h 2 9 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 9 SR10 G2010 L 1 000306A9h 2 8 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 8 SR10K G1610 000306A9h 2 6 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 6 SR10L G1620 P 0 000306A9h 2 7 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 7 SR10M G1610T P 0 000306A9h 2 3 1333 650
36. ccurs the processor will hang The local xAPIC s address space must be uncached The MONITOR instruction only functions correctly if the specified linear address range is of the type write back CLFLUSH flushes data from the cache Intel has not observed this erratum with any commercially available software Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space For the steppings affected see the Summary Tables of Changes Faulting MMX I nstruction May I ncorrectly Update x87 FPU Tag Word Under a specific set of conditions MMX stores MOVD MOVQ MOVNTQ MASKMOVQ which cause memory access faults GP SS PF or AC may incorrectly update the x87 FPU tag word register This erratum will occur when the following additional conditions are also met The MMX store instruction must be the first MMX instruction to operate on x87 FPU state i e the x87 FP tag word is not already set to 0x0000 For MOVD MOVQ MOVNTQ stores the instruction must use an addressing mode that uses an index register this condition does not apply to MASKMOVQ If the erratum conditions are met the x87 FPU tag word register may be incorrectly set to a 0x0000 value when it should not have been modified None identified For the steppings affected see the Summary Tables of Changes An Uncorrectable Error Logged in 1A32 CR MC2 STATUS May also Result in a System Hang Uncorrectable errors logged in IA32 CR MC2 STATUS MSR 409H ma
37. cessor May Livelock During On Demand Clock Modulation The processor may livelock when 1 a processor thread has enabled on demand clock modulation via bit 4 of the IA32 CLOCK MODULATION MSR 19AH and the clock modulation duty cycle is set to 12 596 02H in bits 3 0 of the same MSR and 2 the other processor thread does not have on demand clock modulation enabled and that thread is executing a stream of instructions with the lock prefix that either split a cacheline or access UC memory Program execution may stall on both threads of the core subject to this erratum This erratum will not occur if clock modulation is enabled on all threads when using on demand clock modulation or if the duty cycle programmed in the IA32 CLOCK MODULATION MSR is 18 75 or higher For the steppings affected see the Summary Tables of Changes IA32 VMX VMCS ENUM MSR 48AH Does Not Properly Report The Highest Index Value Used For VMCS Encoding IA32 VMX VMCS ENUM MSR 48AH bits 9 1 report the highest index value used for any VMCS encoding Due to this erratum the value 21 is returned in bits 9 1 although there is a VMCS field whose encoding uses the index value 23 Software that uses the value reported in IA32 VMX VMCS ENUM 9 1 to read and write all VMCS fields may omit one field None identified For the steppings affected see the Summary Tables of Changes The Upper 32 Bits of CR3 May be Incorrectly Used With 32 Bit Paging When 32 bit paging is in u
38. configuration The processor supports PCIe Hardware Autonomous Width management in which a PCle link can autonomously vary its width Due to this erratum a link that performs a speed change while in a reduced width may no longer be able to return to a wider link width PCIe links that perform speed changes while at a reduced link width may be limited to the link width in effect at the time of the speed change Intel has not observed this erratum with any commercially available devices or platforms A BIOS code change has been identified and may be implemented as a workaround for this erratum For the steppings affected see the Summary Tables of Changes Graphics L3 Cache Parity Errors May Not be Detected The graphics engine should detect parity errors within the Graphics L3 cache However due to this erratum graphics L3 cache parity errors may not be detected There may be undetected parity errors from workloads submitted to the execution units of the graphics engine leading to unpredictable graphics system behavior It is possible for the graphics driver to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes A PCle Link That is in Link Disable State May Prevent DDR I O Buffers From Entering a Power Gated State When entering Link Disable LTSSM state the PCle controller may not properly indicate the Link electrical idle condition An incorrect Link electrical idle indication may
39. d Erratum BV109 September 2013 Specification Update intel Preface This document is an update to the specifications contained in the Affected Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Document Title Document Number Desktop 3rd Generation Intel Core Processor Family Datasheet Volume 1 326764 004 Desktop 3rd Generation Intel Core Processor Family Datasheet Volume 2 326765 003 Related Documents Document Number Document Title Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z http www intel com roducts processor Intel 64 and IA
40. duty cycle is not identical for all the logical processors the processor clock will modulate to the highest duty cycle programmed for processors if the CPUID DisplayFamily DisplayModel signatures is listed in Table 14 2 For all other processors if the programmed duty cycle is not identical for all logical processors in the same core the processor will modulate at the lowest programmed duty cycle For multiple processor cores in a physical package each core can modulate to a programmed duty cycle independently For the P6 family processors on demand clock modulation was implemented through the chipset which controlled clock modulation through the processor s STPCLK pin Table 14 2 CPUID Signatures for Legacy Processors That Resolve to Higher Performance Setting of Conflicting Duty Cycle Requests Specification Update 55 56 DisplayFamily Displa DisplayFamily Display DisplayFamily Displa DisplayFamily Display yModel Model yModel Model OF xx 06 1C 06 1A 06 1E 06 1F 06 25 06 26 06 27 06 2C 06 2E 06 2F 06 35 06 36 Specification Update
41. e Overflow bit in the MCi Status register may not be an accurate indication of multiple occurrences of DTLB errors There is no other impact to normal processor functionality None identified For the steppings affected see the Summary Tables of Changes Debug Exception Flags DR6 B0 B3 Flags May be Incorrect for Disabled Breakpoints When a debug exception is signaled on a load that crosses cache lines with data forwarded from a store and whose corresponding breakpoint enable flags are disabled DR7 G0 G3 and DR7 L0 L3 the DR6 B0 B3 flags may be incorrect The debug exception DR6 B0 B3 flags may be incorrect for the load if the corresponding breakpoint enable flag in DR7 is disabled None identified For the steppings affected see the Summary Tables of Changes LER MSRs May Be Unreliable Due to certain internal processor events updates to the LER Last Exception Record MSRs MSR LER FROM LIP 1DDH and MSR LER TO LIP 1DEH may happen when no update was expected The values of the LER MSRs may be unreliable None Identified For the steppings affected see the Summary Tables of Changes Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PEBS Precise Event Based Sampling overflow of the counter results in storage of a PEBS record in the PEBS buffer The information in the PEBS record represents the state of the next instruction to be executed following
42. e the Summary Tables of Changes Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a NM Exception Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a UD Invalid Opcode exception If either the TS or EM flag bits in CRO are set a NM device not available exception will be raised instead of UD exception Due to this erratum a NM exception may be signaled instead of a UD exception on an FXSAVE or an FXRSTOR with a VEX prefix Software should not use FXSAVE or FXRSTOR with the VEX prefix For the steppings affected see the Summary Tables of Changes Specification Update 41 intel BV74 Problem Implication Workaround Status BV75 Problem Implication Workaround Status BV76 Problem Implication Workaround Status 42 VM Exits Due to NMI Window Exiting May Not Occur Following a VM Entry to the Shutdown State If VM entry is made with the virtual NMIs and NMI window exiting VM execution controls set to 1 and if there is no virtual NMI blocking after VM entry a VM exit with exit reason NMI window should occur immediately after VM entry unless the VM entry put the logical processor in the wait for SIPI state Due to this erratum such VM exits do not occur if the VM entry put the processor in the shutdown state A VMM may fail to deliver a virtual NMI to a virtual machine in the shutdown state Before performing a VM entry to the shutdown s
43. ed After the debug exception occurs DR6 B0 B3 bits will contain information about data breakpoints matched during the MOV POP SS as well as breakpoints detected by the following instruction Due to this erratum DR6 B0 B3 bits may not contain information about data breakpoints matched during the MOV POP SS when the following instruction is either an MMX instruction that uses a memory addressing mode with an index or a store instruction When this erratum occurs DR6 may not contain information about all breakpoints matched This erratum will not be observed under the recommended usage of the MOV SS r m or POP SS instructions i e following them only with an instruction that writes E R SP None identified For the steppings affected see the Summary Tables of Changes APIC Error Received Illegal Vector May be Lost APIC Advanced Programmable Interrupt Controller may not update the ESR Error Status Register flag Received Illegal Vector bit 6 properly when an illegal vector error is received on the same internal clock that the ESR is being written as part of the write read ESR access flow The corresponding error interrupt will also not be generated for this case Due to this erratum an incoming illegal vector error may not be logged into ESR properly and may not generate an error interrupt None identified For the steppings affected see the Summary Tables of Changes Specification Update 27 BV24 Problem Implicati
44. ed for memory mapped I O such I O operations may be invoked as a result of speculative execution that would never actually occur in the executed code path Intel has not observed this erratum with any commercially available software Software should avoid locating paging structures at addresses in uncacheable memory that are used for memory mapped I O For the steppings affected see the Summary Tables of Changes Specification Update BV92 Problem Implication Workaround Status BV93 Problem Implication Workaround Status BV94 Problem Implication Workaround Status BV95 Problem Implication Workaround Status The Processor May Not Properly Execute Code Modified Using A Floating Point Store Under complex internal conditions a floating point store used to modify the next sequential instruction may result in the old instruction being executed instead of the new instruction Self or cross modifying code may not execute as expected Intel has not observed this erratum with any commercially available software None identified Do not use floating point stores to modify code For the steppings affected see the Summary Tables of Changes Execution of GETSEC SEXIT May Cause a Debug Exception to be Lost A debug exception occurring at the same time that GETSEC SEXIT is executed or when an SEXIT doorbell event is serviced may be lost Due to this erratum there may be a
45. endent on the new page memory type UC the data size of each write will now always be 8 bytes as opposed to the original data size WP the data size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation WT there may be a memory ordering violation Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled For the steppings affected see the Summary Tables of Changes IO SMI Indication in SMRAM State Save Area May be Set I ncorrectly ThelO SMI bit in SMRAM s location 7FA4H is set to 1 by the CPU to indicate a System Management Interrupt SMI occurred as the result of executing an instruction that reads from an I O port Due to this erratum the IO SMI bit may be incorrectly set by A non 1 O instruction SMI is pending while a lower priority event interrupts e A REP I O read A I O read that redirects to MWAIT SMM handlers may get false IO SMI indication The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I O port The SMM handler must not restart an I O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I O port address For the steppings affected see the Summary Tables of Changes Specificati
46. erratum can only be observed with a software generated stack frame Software should not generate misaligned stack frames for use with IRET For the steppings affected see the Summary Tables of Changes Performance Monitoring Event FP MMX TRANS TO MMX May Not Count Some Transitions Performance Monitor Event FP MMX TRANS TO MMX Event CCH Umask 01H counts transitions from x87 Floating Point FP to MMX instructions Due to this erratum if only a small number of MMX instructions including EMMS are executed immediately after the last FP instruction a FP to MMX transition may not be counted The count value for Performance Monitoring Event FP MMX TRANS TO MMX may be lower than expected The degree of undercounting is dependent on the occurrences of teption Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes General Protection Fault ZGP for Instructions Greater than 15 Bytes May be Preempted When the processor encounters an instruction that is greater than 15 bytes in length a GP is signaled when the instruction is decoded Under some circumstances the GP fault may be preempted by another lower priority fault e g Page Fault PF However if the preempting lower priority faults are resolved by the operating system and the instruction retried a GP fault will occur Software may observe a lower priority fault occurring
47. es of Changes The RDRAND Instruction Will Not Execute as Expected On processors that support the RDRAND instruction that capability should be reported via the setting of CPUID 01H ECX RDRANDIbit 30 Due to this erratum that bit will not be set and the execution of the RDRAND instruction will result in a UD exception Software will not be able to utilize the RDRAND instruction It is possible for the BIOS to contain a workaround for this erratum to report RDRAND as present via CPUID and allow proper execution of RDRAND For the steppings affected see the Summary Tables of Changes A PCI e Device That Initially Transmits Minimal Posted Data Credits May Cause a System Hang Under certain conditions if a PCle device that initially transmits posted data credits less than Max Payload Size 16 4 16B 4DW is unit of data flow control and is the target of a Peer to Peer write of Max Payload Size the system may hang due to Posted Data credit starvation Under certain conditions the processor may encounter a Posted Data credit starvation scenario and hang A BIOS code change has been identified and may be implemented as a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update BV56 Problem Implication Workaround Status BV57 Problem Implication Workaround Status BV58 Problem Implication Workaround Status intel PCI Expres
48. et after every 32 TS Training Set Ordered Sets Due to this erratum the processor may send an EIEOS after every 33 TS Ordered Sets The processor may send an incorrect number of TS Ordered Sets between two EIEOS Ordered Sets when it initiates Secondary Bus Reset or Link Disable Intel has not observed any failures with commercially available devices due to this erratum None identified For the steppings affected see the Summary Tables of Changes Reduced Swing Output Mode Needs Zero De emphasis to be Supported in PCle 5GT s Speed It may not be possible to support the PCle Transmitter Preset 1 and or Transmitter Preset 0 equalization requests in Phase 0 or Phase 2 of Recovery Equalization LTSSM states when operating in 8GT s in reduced or half swing mode if OdB transmitter de emphasis needs to be supported when operating at 5GT s This erratum does not affect normal full swing mode of operation Endpoints requiring OdB support in half swing mode should avoid requesting Transmitter Preset 1 and or Transmitter Preset 0 as preset requests in Phase 0 or Phase 2 of Recovery Equalization when operating in 8GT s None identified For the steppings affected see the Summary Tables of Changes Specification Update BV63 Problem Implication Workaround Status BV64 Problem Implication Workaround Status BV65 Problem Implication Workaround Status BV66 Problem Implication Workarou
49. et for which the type field is 10 Configuration or the deprecated TCfgRd and the format is 4 DW header then due to this erratum the integrated PCle controller may hang instead of reporting the malformed packet error or issuing an unsupported request completion transaction Due to this erratum the processor may hang without reporting errors when receiving a malformed PCIe transaction Intel has not observed this erratum with any commercially available device None identified Upstream transaction initiators should avoid issuing unsupported requests with 4 DW header formats For the steppings affected see the Summary Tables of Changes PCle Link Width May Degrade After a Warm Reset PCle link width may degrade after a warm reset if the Link is operating at 8 0 GT s or 5 0 GT s transfer speeds prior to the reset Due to this erratum the PCle link may retain to a narrower width e g from x16 to x4 A BIOS code change has been identified and may be implemented as a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update 39 BV67 Problem Implication Workaround Status BV68 Problem Implication Workaround Status BV69 Problem Implication Workaround Status BV70 Problem Implication Workaround Status 40 MSR PKG Cx RESI DENCY MSRs May Not be Accurate If the processor is in a package C state for an extended peri
50. eveloper s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation Note Documentation changes for Intel 64 and IA 32 Architecture Software Developer s Manual volumes 1 2A 2B 3A and 3B will be posted in a separate document Intel 64 and IA 32 Architecture Software Developer s Manual Documentation Changes Follow the link below to become familiar with this file http developer intel com products processor manuals index htm There are no new Documentation Changes in this Specification Update revision BV1 On Demand Clock Modulation Feature Clarification Software Controlled Clock Modulation section of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide will be modified to differentiate On demand clock modulation feature on different processors The clarification will state For Hyper Threading Technology enabled processors the IA32 CLOCK MODULATION register is duplicated for each logical processor In order for the On demand clock modulation feature to work properly the feature must be enabled on all the logical processors within a physical processor If the programmed
51. fication change does not apply to listed stepping Page location of item in this document Document change or update will be implemented This erratum may be fixed in a future stepping of the product This erratum has been previously fixed There are no plans to fix this erratum Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document Errata Sheet 1 of 5 Steppings Number Status ERRATA E 1 L 1 N 0 BV1 X X X No Fix The Processor May Report a TS Instead of a GP Fault REP MOVS STOS Executing with Fast Strings Enabled and Crossing Page BV2 X X X No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory Ordering Violations BV3 X X X No Fix IO SMI Indication in SMRAM State Save Area May be Set Incorrectly BV4 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values BV5 X X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception BV6 x x x No Fix Performance Monitoring Event FP_MMX TRANS_TO_MMX May Not Count Some Transitions 8 Specification Update Errata Sheet 2 of 5 Specification Update Steppings Number Status ERRATA E 1 L 1 N 0 General Protection Fault GP for Instructions Greater than 15 Bytes May be BV7 X X X
52. for the proper procedure for concurrently changing page attributes and page size For the steppings affected see the Summary Tables of Changes MCI ADDR May be Incorrect For Cache Parity Errors In cases when a WBINVD instruction evicts a line containing an address or data parity error MCACOD of 0x124 and MSCOD of 0x10 the address of this error should be logged in the MCi ADDR register Due to this erratum the logged address may be incorrect even though MCi Status ADDRV bit 63 is set The address reported in MCi ADDR may not be correct for cases of a parity error found during WBINVD execution None identified For the steppings affected see the Summary Tables of Changes During Package Power States Repeated PCI e and or DMI L1 Transitions May Cause a System Under a complex set of internal conditions and operating temperature when the processor is in a deep power state package C3 C6 or C7 and the PCle and or DMI links are toggling in and out of L1 state the system may hang Due to this erratum the system may hang It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes I nstruction Fetches Page Table Walks May be Made Speculatively to Uncacheable Memory Page table walks on behalf of instruction fetches may be made speculatively to uncacheable UC memory If any paging structures are located at addresses in uncacheable memory that are us
53. h 32 Bit PAE Paging May Cause a System Crash Address Translation Faults for Intel VT d May Not be Reported for Display Engine BV109 X X X No Fix Memory Accesses Specification Changes Number SPECI FI CATION CHANGES None for this revision of this specification update Specification Clarifications Number SPECI FICATION CLARIFICATIONS None for this revision of this specification update 12 Specification Update Documentation Changes ntel Number DOCUMENTATI ON CHANGES BU1 On Demand Clock Modulation Feature Clarification Specification Update 13 intel Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents Extended Extended Processor Famil Model Stepping Reserved Family Model Reserved Type Code Number I De 31 28 27 20 19 16 15 14 13 12 11 8 7 4 3 0 00000000b 0011b 00b 0110 1010b xxxxb Notes 1 The Extended Family bits 27 20 are used in conjunction with the Family Code specified in bits 11 8 to indicate whether the processor belongs to the Intel386 Intel486 Pentium Pentium Pro Pentium 4 or Intel Core processor family 2 The Extended Model bits 19 16 in conjunction with the Model Number specified in bits 7 4 are used to identify the model of the processor
54. hen an interrupt is recognized prior to the first iteration of a string instruction Debug exceptions due to instruction breakpoints are delivered correctly despite this erratum this is because the erratum occurs only after the processor has evaluated instruction breakpoint conditions Software whose correctness depends on value saved for EFLAGS RF by delivery of the affected interrupts can disable fast string operation by clearing Fast String Enable in bit 0 in the IA32 MISC ENABLE MSR 1A0H For the steppings affected see the Summary Tables of Changes Accessing Physical Memory Space 0 640K through the Graphics Aperture May Cause Unpredictable System Behavior The physical memory space 0 640K when accessed through the graphics aperture may result in a failure for writes to complete or reads to return incorrect results A hang or functional failure may occur during graphics operation such as OGL or OCL conformance tests 2D 3D games and graphics intensive application It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full The Software Developer s Manual states that no PMI should be generated when PEBS index reaches PEBS Absolute Maximum Due to this erratum a PMI may be generated even though the PEBS buffer is full PEBS may trigger a PMI even though the PEBS index has reached the PEBS Absolute
55. ing its own Training Sets the link partner may transmit a TLP Transaction Layer Packet request Due to this erratum the root port may not acknowledge the TLP request After completing the Recovery event the PCIe link partner will replay the TLP request The link partner may set a Correctable Error status bit which has no functional effect None identified For the steppings affected see the Summary Tables of Changes An Unexpected PMI May Occur After Writing a Large Value to IA32 FIXED CTR2 If the fixed function performance counter IA32 FIXED CTR2 MSR 30BH is configured to generate a performance monitor interrupt PMI on overflow and the counter s value is greater than FFFFFFFFFFCOH then this erratum may incorrectly cause a PMI if software performs a write to this counter A PMI may be generated unexpectedly when programming IA32 FIXED CTR2 Other than the PMI the counter programming is not affected by this erratum as the attempted write operation does succeed None identified For the steppings affected see the Summary Tables of Changes A Write to the I A32 FIXED CTR1 MSR May Result in I ncorrect Value in Certain Conditions Under specific internal conditions if software tries to write the IA32 FIXED CTR1 MSR 30AH a value that has all bits 31 1 set while the counter was just about to overflow when the write is attempted i e its value was OxFFFF FFFF FFFF then due to this erratum the new value in the MSR may be corr
56. it error rate may cause the link to hang Under extreme conditions poor link quality during link characterization may result in processor hang Intel has not observed this erratum with any commercially available platforms under normal operating conditions None identified For the steppings affected see the Summary Tables of Changes Unused PCI e Lanes May Report Correctable Errors Due to this erratum during PCle link down configuration unused lanes may report a Correctable Error Detected in Bus 0 Device 1 Function 0 2 and Device 6 Function 0 Offset 158H Bit 0 Correctable Errors may be reported by a PCle controller for unused lanes None identified For the steppings affected see the Summary Tables of Changes RDMSR of 1A32 PERFEVTSEL 4 7 May Return Erroneous I nformation When CPUI D OAH EAX 15 8 reports 8 general purpose performance monitoring counters per logical processor RDMSR of IA32 PERFEVTSEL 4 7 MSR 18AH 18DH may not return the same value previously written by software Software should not rely on values read from these MSRs None identified For the steppings affected see the Summary Tables of Changes Specification Update 43 BV81 Problem Implication Workaround Status BV82 Problem Implication Workaround Status BV83 Problem Implication Workaround Status BV84 Problem Implication Workaround Status 44 PCle Link May Fail Link Width Up
57. m may occur if any of the following conditions are applied concurrent to when an actual counter overflow condition is reached 1 Software disables the counter either globally through the IA32 PERF GLOBAL CTRL MSR 38FH or locally through the IA32 PERFEVTSEL 0 7 MSRs 186H 18DH or the IA32 FIXED CTR CTRL MSR 38DH 2 Software sets the IA32 DEBUGCTL MSR 1D9H FREEZE PERFMON ON PMI bit 12 3 The processor attempts to disable the counters by updating the state of the IA32 PERF GLOBAL CTRL MSR 38FH as part of transitions such as VM exit VM entry SMI RSM or processor C state Due to this erratum the corresponding overflow status bit in IA32 PERF GLOBAL STATUS MSR 38DH for an affected counter may not get cleared when expected If a corresponding counter is configured to issue a PMI performance monitor interrupt multiple PMIs may be signaled from the same overflow condition Likewise if a corresponding counter is configured in PEBS mode applies to only the general purpose counters multiple PEBS events may be signaled None identified For the steppings affected see the Summary Tables of Changes RDMSR of 1A32_ PERFEVTSEL4 7 May Return an Incorrect Result When CPUI D A EAX 15 8 reports 8 general purpose performance monitoring counters per logical processor RDMSR of IA32 PERFEVTSEL4 7 MSR 18AH 18DH may not return the same value as previously written Software should not rely on the value read from these MSRs W
58. nd Status intel PCI e Root port I nitiated Compliance State Transmitter Equalization Settings May be Incorrect If the processor is directed to enter PCle Polling Compliance at 5 0 GT s or 8 0 GT s transfer rates it should use the Link Control 2 Compliance Preset De emphasis field bits 15 12 to determine the correct de emphasis level Due to this erratum when the processor is directed to enter Polling Compliance from 2 5 GT s transfer rate it retains 2 5 GT s de emphasis values The processor may operate in Polling Compliance mode with an incorrect transmitter de emphasis level None identified For the steppings affected see the Summary Tables of Changes PCle Controller May I ncorrectly Log Errors on Transition to RxLOs Due to this erratum if a link partner transitions to RxLOs state within 20 ns of entering LO state the PCle controller may incorrectly log an error in Correctable Error Status Receiver Error Status field Bus 0 Device 2 Function 0 1 2 and Device 6 Function 0 offset 1DOH bit 0 Correctable receiver errors may be incorrectly logged Intel has not observed any functional impact due to this erratum with any commercially available add in cards None identified For the steppings affected see the Summary Tables of Changes Reception of Certain Malformed Transactions May Cause PCle Port to Hang Rather Than Reporting an Error If the processor receives an upstream malformed non posted pack
59. nfiguration requests from an endpoint Due to this erratum the processor may associate any Lane that has exited Electrical Idle even if it is beyond the width of the initial Link training Upconfiguration requests may result in a Link wider than the initially trained Link Endpoints must ensure that upconfiguration requests do not request a Link width wider than that negotiated during initial Link training For the steppings affected see the Summary Tables of Changes The Processor May Not Comply With PCI e Equalization Preset Reflection Requirements for 8 GT s Mode of Operation In endpoint initiated transitions to Polling Compliance at the 8 GT s transfer rate the processor must reflect in its ordered sets the Transmitter Preset requested by the endpoint regardless of preset legality Due to this erratum the processor will reflect the Transmitter Preset in use after an endpoint requests a reserved Transmitter Preset rather than the requested preset Endpoints requiring reserved Transmitter Presets to be reflected may be adversely affected Intel has not observed failures due to this erratum with any commercially available devices None identified For the steppings affected see the Summary Tables of Changes Processor May Issue PCI e EI EOS at Incorrect Rate When initiating a Secondary Bus Reset or Link Disable procedure while a PCle Link is in Recovery state the processor should send an EIEOS Electrical Idle Exit Ordered S
60. ntel VT d Remap Engine If software clears the F Fault bit 127 of the Fault Recording Register FRCD_REG at offset 0x208 in Remap Engine BAR by writing 1b through RW1C command Read Write 1 to Clear when the F bit is already clear then a spurious interrupt from Intel VT d Virtualization Technology for Directed 1 0 Remap Engine may be observed Due to this erratum spurious interrupts will occur from the Intel VT d Remap Engine following RW1C clearing F bit None identified For the steppings affected see the Summary Tables of Changes Malformed PCI e Transactions May be Treated as Unsupported Requests I nstead of as Critical Errors PCIe MSG MSG D TLPs Transaction Layer Packets with incorrect Routing Code as well as the deprecated TCfgRD and TCfgWr types should be treated as malformed transactions leading to a critical error Due to this erratum the integrated PCle controller s root ports may treat such messages as UR Unsupported Requests Legacy malformed PCle transactions may be treated as UR instead of as critical errors None identified For the steppings affected see the Summary Tables of Changes Reception of Certain Malformed Transactions May Cause PCIe Port to Hang Rather Than Reporting an Error If the processor receives an upstream malformed non posted packet for which the type field is IO Configuration or the deprecated TCfgRd and the format is 4 DW header then due to this erratum the integrated PCle controller ma
61. ntel Virtualization Technology for Directed I O Intel VT d enabled 6 Intel AES NI enabled 20 Specification Update intel Errata BVI Problem Implication Workaround Status BV2 Problem Implication Workaround Status BV3 Problem Implication Workaround Status The Processor May Report a TS Instead of a GP Fault A jump to a busy TSS Task State Segment may cause a TS invalid TSS exception instead of a GP fault general protection exception Operation systems that access a busy TSS may get invalid TSS fault instead of a GP fault Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes REP MOVS STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with I nconsistent Memory Types may use an Incorrect Data Size or Lead to Memory Ordering Violations Under certain conditions as described in the Software Developers Manual section Out of Order Stores For String Operations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page boundaries from WB WC memory types to UC WP WT memory types may start using an incorrect data size or may observe memory ordering violations Upon crossing the page boundary the following may occur dep
62. od of time greater than 40 seconds with no wake events the value in the MSR PKG C12 3 6 7 RESIDENCY MSRs 60DH and 3F8H 3FAH will not be accurate Utilities that report C state residency times will report incorrect data in cases of long duration package C states It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes PCle Link May Not Enter Loopback Active When Directed When an endpoint directs the processor to enter loopback slave mode at 8 GT s via TS1 ordered sets with both the Loopback and Compliance Receive bits set the PCle link should directly enter Loopback Active state Due to this erratum the processor must achieve block alignment on all looped back lanes prior to entering Loopback Active The processor will not enter Loopback Active state as a loopback slave if any lane in a link cannot achieve block alignment None identified For the steppings affected see the Summary Tables of Changes Execution of VAESI MC or VAESKEYGENASSI ST With An Illegal Value for VEX vvvv May Produce a NM Exception The VAESIMC and VAESKEYGENASSIST instructions should produce a UD Invalid Opcode exception if the value of the vvvv field in the VEX prefix is not 1111b Due to this erratum if CRO TS is 1 the processor may instead produce a NM Device Not Available exception Due to this erratum some undefined instruction encodings may produce a NM instead
63. on Workaround Status BV25 Problem Implication Workaround Status BV26 Problem Implication Workaround Status 28 Changing the Memory Type for an In Use Page Translation May Lead to Memory Ordering Violations Under complex microarchitectural conditions if software changes the memory type for data being actively used and shared by multiple threads without the use of semaphores or barriers software may see load operations execute out of order Memory ordering may be violated Intel has not observed this erratum with any commercially available software Software should ensure pages are not being actively used before requesting their memory type be changed For the steppings affected see the Summary Tables of Changes Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Bits 53 50 of the IA32 VMX BASIC MSR report the memory type that the processor uses to access the VMCS and data structures referenced by pointers in the VMCS Due to this erratum a VMX access to the VMCS or referenced data structures will instead use the memory type that the MTRRs memory type range registers specify for the physical address of the access Bits 53 50 of the IA32 VMX BASIC MSR report that the WB write back memory type will be used but the processor may use a different memory type Software should ensure that the VMCS and referenced data structures are located at physical add
64. on Update 21 intel BV4 Problem Implication Workaround Status BV5 Problem Implication Workaround Status BV6 Problem Implication Workaround Status BV7 Problem Implication Workaround Status 22 Performance Monitor SSE Retired Instructions May Return Incorrect Values Performance Monitoring counter SIMD INST RETIRED Event C7H is used to track retired SSE instructions Due to this erratum the processor may also count other types of instructions resulting in higher than expected values Performance Monitoring counter SIMD INST RETIRED may report count higher than expected None identified For the steppings affected see the Summary Tables of Changes I RET under Certain Conditions May Cause an Unexpected Alignment Check Exception In IA 32e mode it is possible to get an Alignment Check Exception AC on the IRET instruction even though alignment checks were disabled at the start of the IRET This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code IRETs from CPLO 1 2 are not affected This erratum can occur if the EFLAGS value on the stack has the AC flag set and the interrupt handler s stack is misaligned In I A 32e mode RSP is aligned to a 16 byte boundary before pushing the stack frame In IA 32e mode under the conditions given above an IRET can get a AC even if alignment checks are disabled at the start of the IRET This
65. ormation nennen nnns 14 Errata X 21 Specification Changes i 53 Specification Clarifications i 54 Documentation Changes ii 55 Specification Update 3 Contents Specification Update Revision History Revision Description Date 001 Initial Release April 2012 Added Errata BV68 BV83 002 Updated Processor Identification Table May epis Added L 1 and N 0 steppings to errata summary table 003 Added L 1 and N 0 steppings to Component Identification using Programming June 2012 Interface table Updated Processor Identification Table 004 Added errata BV84 BV87 June 2012 Added Intel Pentium G2120 and G2100T Processors 005 Added Desktop 3rd Generation Intel Core i3 3220 i3 3220T i3 3225 i3 3240 i3 October 2012 3240T i5 3330 i5 33305 i5 3330P processors 006 Added errata BV88 BV91 November 2012 007 Added errata BV92 BV95 December 2012 008 Documentation Change January 2013 009 Added Errata BV96 BV97 March 2013 Added Errata BV98 me Updated the SKU table ABEL 2013 011 Added Errata BV99 BV100 BV101 May 2013 Added Errata BV102 BV103 BV104 BV105 012 Made changes to Erratum BV98 June 2013 Added new SKU s to SKU table 013 Added Erratum BV106 July 2013 014 Added Erratum BV107 BV108 August 2013 015 Adde
66. pon detection of a non zero bit in a reserved field an Intel VT d fault should be recorded Due to this erratum the processor does not check reserved bit values for Queued Invalidation descriptors Due to this erratum faults will not be reported when writing to reserved bits of Intel VT d Queued Invalidation Descriptors None identified For the steppings affected see the Summary Tables of Changes FP Data Operand Pointer May Be I ncorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode The FP Floating Point Data Operand Pointer is the effective address of the operand associated with the last non control FP instruction executed by the processor If an 80 bit FP access load or store uses a 32 bit address size in 64 bit mode and the memory access wraps a 4 Gbyte boundary and the FP environment is subsequently saved the value contained in the FP Data Operand Pointer may be incorrect Due to this erratum the FP Data Operand Pointer may be incorrect Wrapping an 80 bit FP load around a 4 Gbyte boundary in this way is not a normal programming practice Intel has not observed this erratum with any commercially available software If the FP Data Operand Pointer is used in a 64 bit operating system which may run code accessing 32 bit addresses care must be taken to ensure that no 80 bit FP accesses are wrapped around a 4 Gbyte boundary For the steppings affected see the
67. prevent the DDR I O buffers from entering a power gated state which may cause higher power consumption on VcclO and VccSA Intel has not observed any functional failure or performance impact due to this erratum A BIOS code change has been identified and may be implemented as a workaround for this erratum For the steppings affected see the Summary Tables of Changes REP MOVSB May Incorrectly Update ECX ESI and EDI Under certain conditions if the execution of a REP MOVSB instruction is interrupted the values of ECX ESI and EDI may contain values that represent a later point in the execution of the instruction than the actual interruption point Due to this erratum ECX ESI and EDI may be incorrectly advanced resulting in unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Specification Update BV85 Problem Implication Workaround Status BV86 Problem Implication Workaround Status BV87 Problem Implication Workaround Status Performance Counter Overflow Indication May Cause Undesired Behavior Under certain conditions listed below when a performance counter overflows its overflow indication may remain set indefinitely This erratum affects the general purpose performance counters 1A32_PMC 0 7 and the fixed function performance counters IA32 FIXED CTR 0 2 The erratu
68. resses that are mapped to WB memory type by the MTRRs For the steppings affected see the Summary Tables of Changes LBR BTM or BTS Records May have Incorrect Branch From Information After an EI ST T state S state C1E Transition or Adaptive Thermal Throttling The From address associated with the LBR Last Branch Record BTM Branch Trace Message or BTS Branch Trace Store may be incorrect for the first branch after a transition of e EIST Enhanced Intel SpeedStep Technology T state Thermal Monitor states e S state ACPI package sleep state CIE Enhanced C1 Low Power state Adaptive Thermal Throttling When the LBRs BTM or BTS are enabled some records may have incorrect branch From addresses for the first branch after a transition of EIST T states S states CIE or Adaptive Thermal Throttling None identified For the steppings affected see the Summary Tables of Changes Specification Update BV27 Problem Implication Workaround Status BV28 Problem Implication Workaround Status BV29 Problem Implication Workaround Status intel Fault Not Reported When Setting Reserved Bits of Intel VT d Queued Invalidation Descriptors Reserved bits in the Queued Invalidation descriptors of Intel VT d Virtualization Technology for Directed 1 0 are expected to be zero meaning that software must program them as zero while the processor checks if they are not zero U
69. riting these MSRs functions as expected None identified For the steppings affected see the Summary Tables of Changes VEX L is Not Ignored with VCVT 2SI Instructions The VEX L bit should be ignored for the VCVTSS2SI VCVTSD2SI VCVTTSS2SI and VCVTTSD2SI instructions however due to this erratum the VEX L bit is not ignored and will cause a UD Unexpected UDs will be seen when the VEX L bit is set to 1 with VCVTSS2SI VCVTSD2SI VCVTTSS2SI and VCVTTSD2SI instructions Software should ensure that the VEX L bit is set to O for all scalar instructions For the steppings affected see the Summary Tables of Changes Specification Update 45 BV88 Problem Implication Workaround Status BV89 Problem Implication Workaround Status BV90 Problem Implication Workaround Status BV91 Problem Implication Workaround Status 46 Concurrently Changing the Memory Type and Page Size May Lead to a System Hang Under a complex set of microarchitectural conditions the system may hang if software changes the memory type and page size used to translate a linear address while a TLB Translation Lookaside Buffer holds a valid translation for that linear address Due to this erratum the system may hang Intel has not observed this erratum with any commercially available software None identified Please refer to Software Developer s Manual volume 3 section Recommended Invalidation
70. s Gen3 Receiver Return Loss May Exceed Specifications The PCle Base Specification includes a graph that sets requirements for maximum receiver return loss versus frequency Due to this erratum the receiver return loss for common mode and differential mode may exceed those requirements at certain frequencies Under laboratory conditions Intel has observed violations of as much as 1 dB The PCI Express Gen3 Base Specification for receiver return loss may be exceeded No functional failures have been observed due to this erratum None identified For the steppings affected see the Summary Tables of Changes Direct Access Via VT d to The Processor Graphics Device May Lead to a System Hang Under a complex set of conditions while using VT d Virtualization Technology for Directed I O with the processor graphics device direct access to the virtualized processor graphics device can lead to a system hang or restart Systems providing direct access to processor graphics device via VT d may hang or restart Intel has not observed this erratum with any commercially available system VMM s should ensure that all processor graphics device interactions conform to guidance published in the Intel Open Source HD Graphics Programmer s Reference Manual and driver writers guide For the steppings affected see the Summary Tables of Changes An Event May Intervene Before a System Management I nterrupt That Results from IN or INS If an 1 O instruc
71. se the processor should use a page directory located at the 32 bit physical address specified in bits 31 12 of CR3 the upper 32 bits of CR3 should be ignored Due to this erratum the processor will use a page directory located at the 64 bit physical address specified in bits 63 12 of CR3 The processor may use an unexpected page directory or if EPT Extended Page Tables is in use cause an unexpected EPT violation This erratum applies only if software enters 64 bit mode loads CR3 with a 64 bit value and then returns to 32 bit paging without changing CR3 Intel has not observed this erratum with any commercially available software Software that has executed in 64 bit mode should reload CR3 with a 32 bit value before returning to 32 bit paging For the steppings affected see the Summary Tables of Changes Specification Update BV104 Problem Implication Workaround Status BV105 Problem Implication Workaround Status BV106 Problem Implication Workaround Status BV107 Problem Implication Workaround Status EPT Violations May Report Bits 11 0 of Guest Linear Address Incorrectly If amemory access to a linear address requires the processor to update an accessed or dirty flag in a paging structure entry and if that update causes an EPT violation the processor should store the linear address into the guest linear address field in the VMCS Due to this erratum the processor m
72. set For the steppings affected see the Summary Tables of Changes Specification Update BV98 Problem Implication Workaround Status BV99 Problem Implication Workaround Status Performance Monitor Counters May Produce Incorrect Results When operating with SMT enabled a memory at retirement performance monitoring event from the list below may be dropped or may increment an enabled event on the corresponding counter with the same number on the physical core s other thread rather than the thread experiencing the event Processors with SMT disabled in BIOS are not affected by this erratum The list of affected memory at retirement events is as follows MEM UOP RETIRED LOADS MEM UOP RETIRED STORES MEM UOP RETIRED LOCK MEM UOP RETIRED SPLIT MEM UOP RETIRED STLB MISS MEM LOAD UOPS RETIRED HIT LFB MEM LOAD UOPS RETIRED L1 HIT MEM LOAD UOPS RETIRED L2 HIT MEM LOAD UOPS RETIRED LLC HIT MEM LOAD UOPS MISC RETIRED LLC MISS MEM LOAD UOPS LLC HIT RETIRED XSNP HIT MEM LOAD UOPS LLC HIT RETIRED XSNP HITM MEM LOAD UOPS LLC HIT RETIRED XSNP MISS MEM LOAD UOPS LLC HIT RETIRED XSNP NONE MEM LOAD UOPS RETIRED LLC MISS MEM LOAD UOPS LLC MISS RETIRED LOCAL DRAM MEM LOAD UOPS LLC MISS RETIRED REMOTE DRAM MEM LOAD UOPS RETIRED L2 MISS Due to this erratum certain performance monitoring event may produce unreliable results when SMT is enabled None identified For the steppings affected see the Summary Ta
73. t 12 For the steppings affected see the Summary Tables of Changes Specification Update 33 BVAA Problem Implication Workaround Status BV45 Problem Implication Workaround Status BV46 Problem Implication Workaround Status BV47 Problem Implication Workaround Status 34 1A32 FEATURE CONTROL MSR May be Uninitialized on a Cold Reset IA32 FEATURE CONTROL MSR 3Ah may have random values after RESET including the reserved and Lock bits and the read modify write of the reserved bits and or the Lock bit being incorrectly set may cause an unexpected GP fault Due to this erratum an unexpected GP fault may occur and BIOS may not complete initialization It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is Followed by a REP MOVSB or STOSB Normally data breakpoints matches that occur on a MOV SS r m or POP SS will not cause a debug exception immediately after MOV POP SS but will be delayed until the instruction boundary following the next instruction is reached After the debug exception occurs DR6 B0 B3 bits will contain information about data breakpoints matched during the MOV POP SS as well as breakpoints detected by the following instruction Due to this erratum DR6 B0 B3 bits may not contain information about data
74. tate software should check whether the virtual NMIs and NMI window exiting VM execution controls are both 1 If they are software should clear NMI window exiting and inject an NMI as part of VM entry For the steppings affected see the Summary Tables of Changes Execution of I NVVPID Outside 64 Bit Mode Cannot I nvalidate Translations For 64 Bit Linear Addresses Executions of the INVVPID instruction outside 64 bit mode with the INVVPID type individual address invalidation ignore bits 63 32 of the linear address in the INVVPID descriptor and invalidate translations for bits 31 0 of the linear address The INVVPID instruction may fail to invalidate translations for linear addresses that set bits in the range 63 32 Because this erratum applies only to executions outside 64 bit mode it applies only to attempts by a 32 bit virtual machine monitor VMM to invalidate translations for a 64 bit guest Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes PCle Controller May Not Properly Indicate Link Electrical Idle Condition The processor supports a x16 PCle port which can be bifurcated into three independent links enumerated as Bus 0 Device 1 Function 0 2 Due to this erratum if the port is bifurcated and Function 1 or 2 is disabled the PCle controller may not properly indicate Link electrical idle condition to the Power Con
75. tion IN INS OUT or OUTS results in an SMI system management interrupt the processor will set the IO SMI bit at offset 7FA4H in SMRAM This interrupt should be delivered immediately after execution of the I O instruction so that the software handling the SMI can cause the I O instruction to be re executed Due to this erratum it is possible for another event e g a nonmaskable interrupt to be delivered before the SMI that follows the execution of an IN or INS instruction If software handling an affected SMI uses I O instruction restart the handler for the intervening event will not be executed The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I O port The SMM handler must not restart an I O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I O port address For the steppings affected see the Summary Tables of Changes Specification Update 37 intel BV59 Problem Implication Workaround Status BV60 Problem Implication Workaround Status BV61 Problem Implication Workaround Status BV62 Problem Implication Workaround Status 38 PCI e May Associate Lanes That Are Not Part of I nitial Link Training to LO During Upconfiguration The processor should not associate any lanes that were not part of the initial link training in subsequent upco
76. tput Mode Needs Zero De emphasis to be Supported in PCle BV62 X X X No Fix 5GT s Speed PCle Root port Initiated Compliance State Transmitter Equalization Settings May BV63 X X X No Fix ba Incorrec BV64 X X X No Fix PCle Controller May Incorrectly Log Errors on Transition to RxLOs BV65 x x x No Fix Reception of Certain Malformed Transactions May Cause PCle Port to Hang Rather Than Reporting an Error BV66 X X X No Fix PCle Link Width May Degrade After a Warm Reset BV67 X No Fix MSR PKG Cx RESIDENCY MSRs May Not be Accurate BV68 X X X No Fix PCle Link May Not Enter Loopback Active When Directed i Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for Bv69 x x d No Bi VEX vvvv May Produce a NM Exception BV70 X X X No Fix Unexpected UD on VZEROALL VZEROUPPER BV71 X No Fix PCle Root Port May Not Initiate Link Speed Change BV72 X X X No Fix Successive Fixed Counter Overflows May be Discarded BV73 X X X No Fix Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a NM Exception VM Exits Due to NMI Window Exiting May Not Occur Following a VM Entry to the BM x x 5 GNE Shutdown State Execution of INVVPID Outside 64 Bit Mode Cannot Invalidate Translations For 64 BVI x X DOE Bit Linear Addresses BV76 X X X No Fix PCle Controller May Not Properly Indicate Link Electrical Idle Condition BV77 X X X No Fix PCle Controller May Not Enter Loopback BV78 X X X No Fix Link Margin Characterization May Hang Link BV79 X X X No
77. trol Unit An incorrect Link electrical idle indication may prevent the processor from entering the lowest power mode which may cause higher power consumption on VcclO and VccSA Intel has not observed any functional failure or performance impact due to this erratum If Bus 0 Device 1 Function 1 or 2 is disabled do not configure the x16 port to allocate lanes to those functions For the steppings affected see the Summary Tables of Changes Specification Update BV77 Problem Implication Workaround Status BV78 Problem Implication Workaround Status BV79 Problem Implication Workaround Status BV80 Problem Implication Workaround Status intel PCle Controller May Not Enter Loopback The PCIe controller is expected to enter loopback if any lane in the link receives two consecutive TS1 ordered sets with the Loopback bit set Due to this erratum if two consecutive TS1 ordered sets are received only on certain lanes the controller may not enter loopback Intel has not observed any functional issue with any commercially available PCle devices None Identified For the steppings affected see the Summary Tables of Changes Link Margin Characterization May Hang Link The processor supports tools and mechanisms to characterize and measure margins for the PCIe interface Due to this erratum when performing link margin to failure characterization it is possible that a high b
78. uctures are modified to change a linear address from writable to non writable without software performing an appropriate TLB invalidation When a subsequent access to that address by a specific instruction ADD AND BTC BTR BTS CMPXCHG DEC INC NEG NOT OR ROL ROR SAL SAR SHL SHR SHLD SHRD SUB XOR and XADD causes a page fault or an EPT induced VM exit the value saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS register would have held had the instruction completed without fault or VM exit For page faults this can occur even if the fault causes a VM exit or if its delivery causes a nested fault None identified Although the EFLAGS value saved by an affected event a page fault or an EPT induced VM exit may contain incorrect arithmetic flag values Intel has not identified software that is affected by this erratum This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit If the handler of the affected events inspects the arithmetic portion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation For the steppings affected see the Summary Tables of Changes BO B3 Bits in DR6 For Non Enabled Breakpoints May be I ncorrectly Set Some of the BO B3 bits breakpoint conditions detect flags
79. um software may be unable to clear the PerfMon counter overflow status indication Software may avoid this erratum by clearing the PerfMon counter value prior to disabling it and then clearing the overflow status indication bit For the steppings affected see the Summary Tables of Changes GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions When a 2 byte opcode of a conditional branch opcodes OF8xH for any value of x instruction resides in 16 bit code segment and is associated with invalid VEX prefix it may sometimes signal a GP fault illegal instruction length gt 15 bytes instead of a UD illegal opcode fault Due to this erratum GP fault instead of a UD may be signaled on an illegal instruction None identified For the steppings affected see the Summary Tables of Changes I nterrupt From Local API C Timer May Not Be Detectable While Being Delivered If the local APIC timer s CCR current count register is 0 software should be able to determine whether a previously generated timer interrupt is being delivered by first reading the delivery status bit in the LVT timer register and then reading the bit in the IRR interrupt request register corresponding to the vector in the LVT timer register If both values are read as 0 no timer interrupt should be in the process of being delivered Due to this erratum a timer interrupt may be delivered even if the CCR is 0 and the LVT and IRR bits
80. upted Due to this erratum IA32 FIXED CTR1 MSR may be written with a corrupted value Software may avoid this erratum by writing zeros to the IA32 FIXED CTR1 MSR before the desired write operation For the steppings affected see the Summary Tables of Changes PCI e LTR I ncorrectly Reported as Being Supported LTR Latency Tolerance Reporting is a new optional feature specified in PCle rev 2 1 The processor reports LTR as supported in LTRS bit in DCAP2 register bus 0 Device 1 Function 0 offset Oxc4 but this feature is not supported Due to this erratum LTR is always reported as supported by the LTRS bit in the DCAP2 register None identified For the steppings affected see the Summary Tables of Changes Specification Update 31 intel BV38 Problem Implication Workaround Status BV39 Problem Implication Workaround Status BV40 Problem Implication Workaround Status 32 PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Under very specific timing conditions if software tries to disable a PerfMon counter through MSR IA32 PERF GLOBAL CTRL 0x38F or through the per counter event select e g MSR 0x186 and the counter reached its overflow state very close to that time then due to this erratum the overflow status indication in MSR IA32 PERF GLOBAL STAT 0x38E may be left set with no way for software to clear it Due to this errat
81. with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Specification Update 47 BV96 Problem Implication Workaround Status BV97 Problem Implication Workaround Status 48 1A32 MC5 CTL2 is Not Cleared by a Warm Reset IA32 MC5 CTL2 MSR 285H is documented to be cleared on any reset Due to this erratum this MSR is only cleared upon a cold reset The algorithm documented in Software Developer s Manual Volume 3 section titled CMCI Initialization or any other algorithm that counts the 1A32_MC5_CTL2 MSR being cleared on reset will not function as expected after a warm reset None identified For the steppings affected see the Summary Tables of Changes CPUID Instruction May Not Report the Processor Number in the Brand String for Intel Core i3 3227U and i5 3337U Processors When the CPUID instruction is executed with EAX 80000002H 80000003H and 80000004H the returned brand string may be incomplete it may be missing the processor number When this erratum occurs the processor may be missing the processor number in the brand string In addition if the affected processors are paired with the Intel 7 Series Chipset BD82UM77 chipset the BIOS may incorrectly report this combination as unsupported It is possible for the BIOS to contain a workaround for this erratum except if paired with the Intel 7 Series Chipset BD82UM77 chip
82. within the processor s family 3 The Processor Type specified in bits 13 12 indicates whether the processor is an original OEM processor an OverDrive processor or a dual processor capable of being used in a dual processor system 4 The Family Code corresponds to bits 11 8 of the EDX register after RESET bits 11 8 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the generation field of the Device ID register accessible through Boundary Scan 5 The Model Number corresponds to bits 7 4 of the EDX register after RESET bits 7 4 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the model field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See Table 1 for the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX register Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register Cache and TLB descriptor parameters are provided in the EAX EBX ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register The processor can be identified by the following register contents
83. y also result in a system hang causing an Internal Timer Error MCACOD 0x0400h to be logged in another machine check bank 1A32 MCi STATUS Uncorrectable errors logged in IA32 CR MC2 STATUS can further cause a system hang and an Internal Timer Error to be logged None identified For the steppings affected see the Summary Tables of Changes Specification Update BV21 Problem Implication Workaround Status BV22 Problem Implication Workaround Status BV23 Problem Implication Workaround Status GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code During a GP General Protection Exception the processor pushes an error code on to the exception handler s stack If the segment selector descriptor straddles the canonical boundary the error code pushed onto the stack may be incorrect An incorrect error code may be pushed onto the stack Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is Followed by a Store or an MMX Instruction Normally data breakpoints matches that occur on a MOV SS r m or POP SS will not cause a debug exception immediately after MOV POP SS but will be delayed until the instruction boundary following the next instruction is reach
84. y hang instead of reporting the malformed packet error or issuing an unsupported request completion transaction Due to this erratum the processor may hang without reporting errors when receiving a malformed PCIe transaction Intel has not observed this erratum with any commercially available device None identified Upstream transaction initiators should avoid issuing unsupported requests with 4 DW header formats For the steppings affected see the Summary Tables of Changes Clock Modulation Duty Cycle Cannot be Programmed to 6 25 When programming field T STATE REQ of the IA32 CLOCK MODULATI ON MSR 19AH bits 3 0 to 0001 the actual clock modulation duty cycle will be 12 596 instead of the expected 6 25 ratio Due to this erratum it is not possible to program the clock modulation to a 6 2596 duty cycle None identified For the steppings affected see the Summary Tables of Changes Specification Update BV34 Problem Implication Workaround Status BV35 Problem Implication Workaround Status BV36 Problem Implication Workaround Status BV37 Problem Implication Workaround Status Processor May Fail to Acknowledge a TLP Request When a PCle root port s receiver is in Receiver LOs power state and the port initiates a Recovery event it will issue Training Sets to the link partner The link partner will respond by initiating an LOs exit sequence Prior to transmitt
85. y new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals and so on Specification Update 7 intel Summary Tables of Changes The following tables indicate the errata specification changes specification clarifications or documentation changes which apply to the processor Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted These tables uses the following notations Codes Used in Summary Tables Stepping Page Status Row X No mark or Blank box Page Doc Plan Fix Fixed No Fix Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping This erratum is fixed in listed stepping or speci

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