Intel 8 LAN User's Manual
Contents
1. 02h Individual Address Byte Word 00 Word 01 Word 02 Byte Byte Byte Byte Byte Byte Manufacturer MAC Address 2 1 4 3 6 5 Intel original OOAAOOXXYYZZh AAh 00h XXh 00h Zzh YYh Intel new 00A0C9XXYYZZh AOh 00h XXh C9h ZZh YYh The Ethernet IA is byte swapped as listed in Table 2 The IA bytes read from the NVM are used by the ICH8 until an IA Setup command is issued by software The IA defined by the IA Setup command overrides the IA read from the NVM Reserved Word 03h Reserved Word 03h Bit Name Default Description 15 12 Reserved 0000b These bits are reserved and should be set to 0000b 11 IBA LOM 1b Must be set to 1b for Intel Boot Agent IBA to function correctly 10 0 Reserved Oh These bits are reserved and should be set to Oh m e n tel NVM Information Guide l CH8 1 4 3 Reserved Word O4h Table 4 Reserved Word 04h Bit Name Default Description 15 0 Reserved FFFFh These bits are reserved and should be set to FFFFh 1 4 4 I mage Version Information Word 05h Table 5 I mage Version Information Word 05h Bit Name Default Description 15 Reserved Ob This bit is reserved and should be set to Ob 14 12 NVM Major Version This field represents the LAN NVM major version number 11 4 NVM Minor Version This field repr2. 0003 D008 0800 6051 0000 FFFF FFFF 0015 0018 001A 001F 001F FFFF FFFF 6 E FFFF 8086 0000 0000 0000 0000 FFFF FFFF OEO2 2FAO 01B0 00D3 29E4 1606 1F40 1F60 F9EF 1780 1880 0000 0001 FFFF FFFF FFFF 7 F FFFF 0000 0D07 0000 0000 0000 FFFF FFFF 0012 OO1F 0010 001E 0010 0010 OO1F OO1F 0018 OO1F OO1F OO1F 0011 FFFF FFFF FFFF 25 26 82566MC NVM I mage with I CH8 0 8 8888 FFFF ODO1 0684 0000 0000 0100 FFFF 6100 2F40 8B24 0000 28A0 0000 B814 0065 3FBO 0210 0008 D918 0001 6100 FFFF FFFF 1 9 8888 FFFF 0000 0181 0000 0000 4000 FFFF 001F 001F 0011 0011 001F 001F 0011 0014 0012 0019 0016 0018 0019 O01F FFFF FFFF 2 A 8887 10C7 0000 0000 0000 0000 1228 FFFF 0404 9018 F8FO 20C0 O4CE 0140 012A 002A COFF 1880 1780 1860 1340 0400 FFFF FFFF Range Range 3 B 0800 0000 9605 0000 0000 0000 4007 FFFF 0010 001B 0012 O01F 0014 0000 0015 0015 0016 O01F OO1F O01F 0000 0010 FFFF FFFF 0x40 0x7F 4 C 5 D FFFF 2000 8086 104D 5020 3700 0000 0000 0000 0000 0000 0000 FFFF FFFF FFFF FFFF 6120 001F 0000 0012 2000 001F 249A 001D 2F60 001F 1F20 001F 0067 001E 002A 0016 0x80 OxBF 1DEC 0017 0003 0015 D008 0018 0800 001A 6051 001F 0
3. 10 Mb s 11 10 FSP 10b 100 Mb s 11b Not allowed All zeros indicate auto negotiate the current bit state Note that bit 12 is a don t care unless these bits are set Reserved 3 Reseved Set this bit to Ob Display Setup Message 8 DSM If this bit is set to 1b the Press Control S message appears after the title message The default for this bit is 1b 18 I CH8 NVM Information Guide 1 4 23 2 Bit 7 6 Name PT intel Description Prompt Time These bits control how long the Press Control S setup prompt message appears if enabled by DIM 00b 2 seconds default 01b 3 seconds 10b 5 seconds 11b 0 seconds Note that the Ctrl S message does not appear if 0 seconds prompt time is selected Reserved Reserved 4 3 DBS Default Boot Selection These bits select which device is the default boot device These bits are only used if the agent detects that the BIOS does not support boot order selection or if the MODE field of word 31h is set to MODE_LEGACY 00b Network boot then local boot 01b Local boot then network boot 10b Network boot only 11b Local boot only 1 0 Reserved PS Reserved Protocol Select These bits select the boot protocol 00b PXE default value 01b RPL protocol Other values are undefined Boot Agent Configuration Customization Options Word 31h Word 31h contains settings that can be programmed by an OEM or netw
4. 2 3 Jan 2007 Added ICH9 and 82567 NVM information 2 2 Oct 2006 Added device IDs for the 82562G and 82562GT 10 100 Mb s Platform LAN Connects 2 1 Julv 2006 Changed bit 1 of word 13h to Ob Initial public release 2 0 June 2006 Added new LAN Word Offset 19h description to Tables 1 and 17 Added new EEPROM images to Appendix A Updated bit defaults and descriptions to Tables 9 10 13 15 and 16 1 75 April 2006 Updated bit descriptions for words 13h 14h and 19h Initial Intel Confidential release Converted this to a stand alone document Previously it was AP 478 Addendum Added Section 1 1 NVM Programming Procedure Overview and Section 1 2 EEUPDATE Utility Updated the following sections Section 2 12 Shared Initialization Control Word 13h bits 10 and 0 Section 2 13 Extended Configuration Word 1 Word 14h bits 15 14 and 11 0 1 5 Feb 2006 Section 2 14 Extended Configuration Word 2 Word 15h bits 15 8 Section 2 15 Extended Configuration Word 3 Word 16h Section 2 16 LED 1 Configuration and Power Management Word 17h bit 7 Section 2 17 LED 0 and 2 Configuration Defaults Word 18h bit 7 Section 2 18 Future Initialization Word 1 Words 19h Section 2 20 Checksum Word 3Fh Appendix A 1 82566DM NVM Image with ICH8 Appendix A 3 82562V NVM Image with ICH8 Updated Section 2 12 Shared Initialization Control Word 13h Table 9 to add the
5. Automatic reduction enabled Dynamic Clock Gating 1b Dynamic Clock Gating Ob Disable 1b Enable 13 m e n tel NVM I nformation Guide l CH8 1 4 16 Extended Configuration Word 1 Word 14h Table 12 Extended Configuration Word 1 Word 14h Bit Name Default Description 15 Reserved Ob Reserved Must be set to Ob 1b ICH8 BO B1 stepping 14 R d 1 oe b Ob ICH8 A0 stepping 13 Reserved 1b Set this field to Ob OEM Write Enable Ob Disable 12 OEM Write Enable 1b 1b Enable Set this field to Ob Extended This field defines the base address in Dwords of the extended 11 0 Configuration 020h fi ti in the NVM It should Pointer configuration area in the It should equal a non zero value 1 4 17 Extended Configuration Word 2 Word 15h Table 13 Extended Configuration Word 2 Word 15h Bit Name Default Description This field identifies the size in Dwords of the extended PHY Extended PHY configuration area 15 8 37h Length For the 82566 PHY if the extended PHY configuration area is disabled the length must be set to 37h 7 0 Reserved 00h These bits are reserved and should be set to OOh 1 4 18 Extended Configuration Word 3 Word 16h Table 14 Extended Configuration Word 3 Word 16h Bit Name Default Description 15 0 Reserved 00h These bits are reserved and should be set to 00h
6. OCh Subsystem Vendor ID ODh Device ID OEh Vendor ID OFh Device REV ID 10h LAN Power Consumption 11 12h Reserved 13h Shared Initialization Control Word 14 16h Extended Configuration Words 17 18h LEDCTRL Words 19h Future Initialization Word 1 1Ah Future Initialization Word 2 1B 2Fh Reserved 30 3Eh PXE Software Region 3Fh Software Checksum 23 24 82566DM NVM I mage with I CH8 0 8 8888 FFFF ODO1 0684 0000 0000 0100 FFFF 6100 2F40 F8FO 20C0 04CE 0140 012A 002A 1DEC 0003 D008 1340 0000 6100 FFFF FFFF 1 9 8888 FFFF 0000 0301 0000 0000 4000 FFFF OO1F O01F 0012 O01F 0014 0000 0015 0015 0017 0015 0018 0000 O01F O01F FFFF FFFF 2 A 8887 10C7 0000 0000 0000 0000 1228 FFFF 0404 901B 2000 249A 2F60 1F20 0067 1F60 FOEF D918 1860 0001 1340 0400 FFFF FFFF Range Range 3 B 0800 0000 9605 0000 0000 0000 4007 FFFF 0010 001B 001F 001D 001F 001F OO1E O01F 0018 0018 001F 0019 0000 0010 FFFF FFFF 4 C FFFF 8086 5020 0000 0000 0000 FFFF FFFF 6120 0000 10BO 00D3 29E4 1606 1F40 3FBO 0210 1780 0800 2F40 6051 0000 FFFF FFFF 5 D 1030 104A 3700 0000 0000 0000 FFFF FFFF 0x40 0x7F 001F 0012 0010 001E 0010 0010 O01F 0012 0x80 OxBF 0019 O01F 001A O01F O01F O01F FFFF FFFF 6 E FFFF 8086 0000
7. 0000 0000 0000 FFFF FFFF OEO2 2FAO0 0000 28A0 0000 B814 0065 COFF 1880 0008 0000 9018 0001 FFFF FFFF FFFF 7 F FFFF 0000 8D07 0000 0000 0000 FFFF FFFF 0012 O01F 0011 O01F O01F 0011 0014 0016 001F 0016 001F 001B 0011 FFFF FFFF FFFF NVM Information Guide l CH8 I CH8 NVM Information Guide A 2 Note 82566MM NVM I mage with ICH8M For use with ICH8 B 1 stepping only Image has Intel ACBS enabled 0 8 8888 FFFF ODO1 0684 0000 0000 0100 FFFF 6100 2F40 8B24 0000 28A0 0000 B814 0065 3FBO 0210 0008 D918 0001 6100 FFFF FFFF 1 9 8888 FFFF 0000 0181 0000 0000 4000 FFFF 001F 001F 0011 0011 001F 001F 0011 0014 0012 0019 0016 0018 0019 001F FFFF FFFF 2 A 3 B 8887 0800 10C7 0000 0000 9605 0000 0000 0000 0000 0000 0000 1228 4007 FFFF FFFF 4 C FFFF 8086 5020 0000 0000 0000 FFFF FFFF 5 D 2000 1049 3700 0000 0000 0000 FFF FFF je ESSDGREe pen Range 0x40 0x7F 0404 0010 6120 001 9018 001B F8FO 0012 20CO OO1F OACE 0014 0140 0000 012A 0015 002A 0015 COFF 0016 1880 001F 1780 001F 1860 001F 1340 0000 0400 0010 FFFF FFFF FFFF FFFF 0000 2000 249A 2F60 1F20 0067 002A 0012 001 001D 001 001 F F F F F F 001E 0016 jue SSS Range 0x80 0xBF 1DEC 0017
8. Enable 1b Ob PHY Smart Power Down mode is disabled 1b PHY Smart Power Down mode is enabled LED1 Blink LED1 Invert Ob Ob This bit indicates the initial value of the LED1_BLINK field Ob LEDI is non blinking recommended 1b LEDI is blinking This bit indicates the initial value of the LED1_IVRT field Ob LEDI has an active low output 1b LED1 has an active high output LED1 Blink Mode Ob This bit defines the LED1 blink mode Ob Blink at 200 ms on and 200 ms off 1b Blink at 83 ms on and 83 ms off This field should be identical to LEDO Blink Mode Filtered ACT LED Ob Enable Filtered Activity LED while operating with the 82562V When set to Ob the activity LED is activated by the PHY When set to 1b the activity LED is driven by Tx activity or Rx traffic that match any of the MAC s MAC addresses For the 82566 this bit is reserved and should be set to Ob 3 0 LED1 Mode 0111b These bits represent the initial value of the LED1 MODE field which specifies the event state or pattern displayed on LED1 LINK 1000 output Table 16 defines the values for LED1 Mode A value of 0111b indicates that a 1000 Mb s link is established and maintained The following table lists the LED modes defined in bits 3 0 of this word 15 intel NVM Information Guide l CH8 Tabl
9. and OCh Ob Device loads the default PCI Vendor and Device IDs 1b Device loads the default values for PCI Vendor and Device IDs from the NVM words ODh and OEh 1 4 9 Subsystem I D Word OBh If Load Subsystem IDs bit of word OAh is set to 1b this word is read in to initialize the Subsystem ID The Subsystem ID default value is 0000h 1 4 10 Subsystem Vendor I D Word OCh If Load Subsystem IDs bit of word OAh is set to 1b this word is read in to initialize the Subsystem Vendor ID The Subsystem Vendor ID default value is 8086h 11 m e n tel NVM I nformation Guide l CH8 1 4 11 1 4 12 1 4 13 1 4 14 Table 10 12 Device I D Word ODh If the Load Vendor Device IDs bit in word OAh is set to 1b this word is read to initialize the Device ID of the LAN function Table 9 Device IDs for Intel Platform LAN Connects Device ID Adapter 1049h Intel amp 82566MM Gigabit Ethernet Controller 104Ah Intel 82566DM Gigabit Ethernet Controller 104Dh Intel 82566MC Gigabit Ethernet Controller 104Ch Intel amp 82562V 10 100 Mb s Platform LAN Connect Device Vendor I D Word OEh If the Load Vendor Device IDs bit in word OAh is set to 1b this word is read to initialize the Vendor ID The default Vendor ID value is 8086h Device Rev ID word OFh Bit Name Default Description 15 0 Reserved 00h Reserved LAN Power Consumption Word 10h This word is on
10. file and IA address file The EEUPDATE utility is flexible and can be used to update the entire GbE region image or only the IA address of the LAN controller In addition it also corrects the GbE component checksum field after the region is modified FTOOL does not have this ability For more information on how to use EEUPDATE refer to the eeupdate txt file that is included with the EEUPDATE utility To obtain a copy of this program contact your Intel representative Command Line Parameters The DOS command format is as follows EEUPDATE Parameter 1 Parameter 2 where Parameter 1 D or A D is used to update the entire GbE region image A is used to update just the Ethernet Individual Address Parameter 2 filename In Example 1 Parameter 2 is ilel eep which contains the complete NVM image in a specific format used to update the complete GbE region All comments in the eep file must be preceded by a semicolon EEUPDATE D filel eep In Example 1 Parameter 2 is ile2 dat which contains a list of IA addresses The EEUPDATE utility finds the first unused address from this file and uses it to update the NVM An address is marked used if it is followed by a date stamp When the utility uses a specific address a log file called eelog dat is updated with that address This updated file should be used as the dat file for the next update Appendix A provides an example of the raw GbE region contents Fast Ethernet 82562V
11. intel Intel 1 O Controller Hub 8 LAN NVM Map and Information Guide January 2008 evision INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights IMPORTANT PLEASE READ BEFORE INSTALLING OR USING INTEL PRE RELEASE PRODUCTS Please review the terms at http www intel com netco
12. present 11b Invalid NVM 13 11 Reserved 010b These bits are reserved and should be set to 010b 10 Reserved 1b Reserved Always set to 1b PHY PD Ena Reserved PHYT 1b Ob 00b For ICH8 designs that support an ACBS implementation using LAN Power Control LAN PHYPC this bit enables or disables PHY power down Ob PHY power down feature is disabled 1b PHY power down feature is enabled to power down at DMoff D3 without Wake on LAN This bit is loaded to the PHY Power Down Enable bit in the CTRL EXT register This bit is reserved and should be set to Ob This field indicates the PHY device type 00b 82566 PHY GLCI mode 01b Reserved 10b 82562V PHY PCle mode LCI mode 11b Reserved This field is reflected in the PHYTYPE field in the Status register Reserved FRCSPD Ob Ob Reserved Must be set to Ob Force Speed Enable Ob Normal operation 1b Use ICH8 speed FD Ob Force Duplex Ob Normal operation 1b Use ICH8 speed CLK_CNT_1_16 CLK_CNT_1 4 1b Ob This bit is loaded to the CTRL EXT EnaKumCK16 bit and enables the reduction of the internal JCLK to one sixteenth of the external NJ CLK at the GLCI interface in Gigabit Ethernet mode Ob Reduction is disabled 1b Reduction is enabled This bit enables the automatic reduction of DMA frequency It is mapped to STATUS 31 Ob Automatic reduction disabled 1b
13. 000 001F FFFF FFFF FFFF FFFF 6 E FFFF 8086 0000 0000 0000 0000 FFFF FFFF OEO2 2FAO0 O1BO 00D3 29E4 1606 1F40 1F60 FOEF 1780 1880 0000 0001 FFFF FFFF FFFF 7 F FFFF 0000 0D07 0000 0000 0000 FFFF FFFF 0012 O01F 0010 001E 0010 0010 001F 001F 0018 001F 001F 001F 0011 FFFF FFFF FFFF NVM Information Guide l CH8 I CH8 NVM Information Guide A 4 82562V NVM I mage with I CH8 0 8 8888 FFFF 0402 0684 0000 0000 0100 FFFF Xl X X xl XI ki ki i ti X XI aq 1 9 8888 FFFF 0000 0301 0000 0000 4000 FFFF X X ki a kl ki ki kl X X X Xl 2 A 8887 10C7 0000 0000 0000 0000 121C FFFF 0000 0000 FFFF X Xl Xl kal ki ki ki i Xl X X Xl Range 3 B 0800 0000 9687 0000 0000 0000 4007 FFFF 0000 0000 FFFF Xl Xl ki ki ki i l X X X a 4 C FFFF 8086 4020 0000 0000 0000 FFFF FFFF 0000 0000 X a X XI XI ki ki i Xl X X i 5 D 1002 104C 0000 0000 0000 0000 FFFF FFFF 0x40 0x7F 0000 0000 ti Xl Xl a ki ki ki a X i X ai 6 E FFFF 8086 0000 0000 0000 0000 FFFF FFFF 0000 0000 FFFF Ti Ti rj Hi Ti Ti rj j Ti Ti rj nj 7 F FFFF 0000 0
14. 007 0000 0000 0000 FFFF FFFF 0000 0000 FFFF FFFF FFFF FFFF FFFF FFFF 27 Note This page intentionally left blank 28
15. 1 0 Dec 2005 Ext Pwr Polarity bit Added the 82566 NVM image to A 1 82566DM NVM Image with I CH8 0 75 July 2005 Initial release Intel Secret I CH8 NVM Information Guide n tel 1 0 1 1 1 2 Non Volatile Memory NVM Introduction The document is intended for designs using the 10 100 1000 Mb s LAN controller that is integrated into the Intel 1 O Control Hub 8 ICH8 device The NVM space is used for hardware and software configuration It is also read by software to determine and configure specific design features Unless otherwise specified all numbers in this document use the following numbering convention Numbers that do not have a suffix are decimal base 10 Numbers with a suffix of h are hexadecimal base 16 Numbers with a suffix of b are binary base 2 NVM Programming Procedure Overview The LAN NVM shares space on an SPI Flash device or devices along with the BIOS Manageability Firmware and a Flash Descriptor Region It is programmed through the ICH8 This combined image is shown in Figure 1 The Flash Descriptor Region is used to define vendor specific information and the location allocated space and read and write permissions for each region The Manageability ME Region contains the code and configuration data for ME functions such as Intel Active Management Technology ASF and Advanced Fan Speed Control The system BIOS is contained in the BIOS Region The ME Region and BIO
16. 14 I CH8 NVM Information Guide 1 4 19 Table 15 intel LED 1 Configuration and Power Management Word 17h This field specifies the default values for the LEDCTL register fields controlling the LED1 LINK_1000 output behaviors and the OEM fields defining the PHY power management parameters loaded to the PHY_CTRL register LED 1 Configuration and Power Management Word 17h Bit Name Default Description 15 B2B Enable 1b This bit enables Smart Power Down in back to back link setup Ob B2B disabled 1b B2B enabled 14 GbE Disable Ob GbE Disable in all power states Ob GbE enabled 1b GbE disabled 13 12 Reserved 00b These bits are reserved and should be set to 00b 11 10 GbE Disable in non DOa LPLU Enable in non DOa LPLU Enable 1b 1b Ob GbE Disable in all power states except DOa Ob GbE enabled 1b GbE disabled The Low Power Link Up enables link at the lowest speed supported by both link partners in non DOa states This bit must be set if LPLU Enable bit is set Ob Low Power Link Up is disabled 1b Low Power Link Up is enabled in all non DOa states The Low Power Link Up enables link at the lowest speed supported by both link partners in all power states This bit enables a decrease in link speed in all power states Ob Low Power Link Up is disabled 1b Low Power Link Up is enabled in all power states SPD
17. 3 1 Command Line Parameters ccccccccccceee ec eee mee eene enne nnne aan n 7 1 4 LAN NVM Format and ContentS use eee ekk kk seuss emesh enema keen nennen nnn 8 1 4 1 Ethernet Individual Address Words OOh 02h eee nee n ena 9 1 4 2 Reserved Word 03h cissssssssse Ims ense ehh nenne a ena nna 9 1 4 3 Reserved Word 04h iicssssss III ee hene hne nene nane aa ene nnn 10 1 4 4 Image Version Information Word 05h Lok nnenn ken nn nnn rna kr mmm 10 1 4 5 Reserved Word 06h cicer ite ka ce E I RR CHECK C alia 10 1 4 6 Reserved Word O7b LAKE HEKK EF IEEE EE KEE EEI EE adea ne 10 1 4 7 PBA Low PBA High Words 08h and 09h 6 ennrennn nn rnn mmm 10 1 4 8 PCI Initialization Control Word OAh ccssssese Henn 11 1 4 9 Subsystem ID Word OBN LL nmm emen nnne nnn nnn 11 1 4 10 Subsystem Vendor ID Word OCH KKK KA KEE KE mmn nnns 11 1 4 11 Device ID Word ODh isssssss IH mme meme ene nennen nee an 12 1 4 12 Vendor ID Word OEN LAKE eme PEAR ANKE esee needs 12 1 4 13 Device Rev ID word OFh cc ccc cece KEEP eem he enean 12 1 4 14 LAN Power Consumption Word 10h sss mmm nnne 12 1 4 15 Shared Initialization Control Word 13h e eeennenenzannnnenzznnn ankra anna 13 1 4 16 Extended Configuration Word 1 Word 14h Lo ennnnnnnnnknnnnnnnknnkn nanna 14 1 4 17 Extended Configuration Word 2 Word 15h sss 14 1 4 18 Extended Configuration Word 3 Word 16h sssssssssssssssrrsse
18. BIOS is not compliant The BIOS boot order can be changed in the Setup Menu 010b Force BBS mode The agent assumes the BIOS is BBS compliant even though it may not be detected as such by the agent s detection code The BIOS boot order CANNOT be changed in the Setup Menu 011b Force PnP Int18 mode The agent assumes the BIOS allows boot order setup for PnP Expansion ROMs and hooks interrupt 18h to inform the BIOS that the agent is a bootable device in addition to registering as a BBS IPL device The BIOS boot order CANNOT be changed in the Setup Menu 100b Force PnP Int19 mode The agent assumes the BIOS allows boot order setup for PnP Expansion ROMs and hooks interrupt 19h to inform the BIOS that the agent is a bootable device in addition to registering as a BBS IPL device The BIOS boot order CANNOT be changed in the Setup Menu 101b Reserved for future use If specified treated as value 000b 110b Reserved for future use If specified treated as value 000b 111b Reserved for future use If specified treated as value 000b Reserved Reserved for future use These bits must be set to Ob DFU Disable Flash Update If set to 1b no updates to the Flash image using PROSet is allowed The default for this bit is Ob allow Flash image updates using PROSet DLWS Disable Legacy Wakeup Support If set to 1b no changes to the Legacy OS Wakeup Support menu option is allowed The default for this bit is Ob a
19. PXE base code is present default Ob The PXE base code is not present PXE base code is present in Flash 0 BC Ob The PXE base code is present 1b The PXE base code is not present default Checksum Word 3Fh The Checksum word NVM bytes 7Eh and 7Fh is used to ensure that the base NVM image is valid Its value should be calculated by adding all words 00h through 3Fh bytes OOh 7Eh including the Checksum word itself The sum including the Checksum should equal BABAh The initial value before the values are added together should be 0000h and the carry bit should be ignored after each addition If the OEM does not desire to calculate the checksum LAD programming tools and drivers will detect if the checksum is incorrect and fix it in the image The default image always has a checksum value of 0 The default image always has a checksum value of Ob The LAD programming tools EEUPDATE or LANCONF update the checksum when the image is programmed I CH8 NVM Information Guide intel Appendix A I CH8 NVM Contents and Sample Images This section contains a sample of raw NVM contents for the ICH8 All values for these images are hexadecimal Table 22 LAN NVM Contents Word Description 00 02h Ethernet Individual Address 03 04h Reserved 05h Image Version Information 1 06 07h Reserved 08 09h PBA Bytes OAh PCI Initialization Control Word OBh Subsystem ID
20. S Region are beyond the scope of this document and a more detailed explanation of these areas can be found in the Intel 1 0 Controller Hub 8 ICH8 Family External Design Specification ICH8 EDS This document describes the LAN image contained in the Gigabit Ethernet GbE region Fast Ethernet 82562V images are also described m e n tel NVM I nformation Guide l CH8 BIOS Region 1 GbE Region 3 Flash Descriptor Region Figure 1 LAN NVM Regions To access the NVM it is essential to correctly setup the following 1 A valid Flash Descriptor Region must be present Details for the Flash Descriptor Region are contained in the ICH8 EDS The FTOOL exe utility provides the easiest method of configuring this descriptor region This process is described in detail in the Intel Active Management Technology OEM Bring Up Guide FTOOL exe and the Intel Active Management Technology OEM Bring Up Guide can be obtained as part of the Intel Active Client Manager kit on ARMS https platformsw intel com or by contacting your local Intel representative 2 The GbE region must be part of the original image flashed onto the part 3 For Intel LAN tools and drivers to work correctly the BIOS must set the VSCC register s correctly This information is described in ICH8 EDS section 24 1 4 The GbE region of the NVM must be accessible To keep this region accessible the Protected Range register of the GbE LAN Mem
21. e 16 LED Modes dico s Selected Mode Source Indication Asserted when either 10 Mb s or 1000 Mb s link is established 0000b LINK 10 1000 and maintained 0001b LINK 100 1000 Asserted when either 100 Mb s or 1000 Mb s link is established and maintained 0010b LINK UP Asserted when any speed link is established and maintained Asserted when link is established and packets are being 0011b eer ty transmitted or received that passed MAC filtering 0100b LINK ACTIVITY Asserted when link is established and when there is no transmit or receive activity 0101b LINK_10 Asserted when a 10 Mb s link is established and maintained 0110b LINK 100 Asserted when a 100 Mb s link is established and maintained 0111b LINK 1000 Asserted when a 1000 Mb s link is established and maintained 1000b Reserved Reserved 1001b FULL DUPLEX Asserted when the link is configured for full duplex operation 1010b COLLISION Asserted when a collision is observed 1011b ACTIVITY Asserted when link is established and packets are being transmitted or received 1100b BUS_SIZE Asserted when the MAC detects a 1 lane PCle connection 1101b PAUSED Asserted when the MAC transmitter is flow controlled 1110b LED_ON Always asserted 1111b LED_OFF Always de asserted 1 4 20 LED O and 2 Configuration Defaults Word 18h This NVM word specifies the hardware defaults for the LEDCTL register fields controlling the LEDO LINK ACTIVITY and LED2 LINK_100 output behaviors Table 17 LED O and 2 Config
22. esents the LAN NVM minor version number 3 0 Image ID 2h This field represents the NVM image identification This field equals E 9 2h default for the 82562V PHY and Oh for the 82566 PHY 1 4 5 Reserved Word 06h Table 6 Reserved Word 06h Bit Name Default Description 15 0 Reserved FFFFh This field is reserved and should be set to FFFFh 1 4 6 Reserved Word 07h Table 7 Reserved Word 07h Bit Name Default Description 15 0 Reserved FFFFh This field is reserved and should be set to FFFFh 1 4 7 PBA Low PBA High Words 08h and 09h The nine digit printed board assembly PBA number used for Intel manufactured adapter cards are stored in a four byte field The dash and the first digit of the three digit suffix are not stored 1 4 7 1 PBA Example If the PBA Number is 123456 003 then word 08h 1234h and word 09h 5603h Through the course of hardware changes the suffix field byte 4 is incremented The purpose of this information is to enable customer support or any user to identify the exact revision level of a product The software device driver should not rely on this field to identify the product or its capabilities 10 I CH8 NVM Information Guide 1 4 8 PCI Initialization Control Word OAh This word contains initialization values that Set defaults for some internal registers Enable disable specific features Determine which PCI configuration space values are loaded from the NVM Table 8 PCI Initializa
23. images are also provided Table 1 LAN NVM Format and Contents NVM Information Guide l CH8 Table 1 lists the NVM maps for the LAN region Each word listed is described in detail in the following sections LAN NVM Address Map LAN NVM image Word Byte HI gh Byte Bits 15 8 Low Byte Bits 7 0 Used By Valua Offset Offset Ethernet Individual Address Ethernet Individual Address HW 00h 00 Byte 2 Byte 1 Shared IA 2 1 Ethernet Individual Address Ethernet Individual Address HW Olh 02 Byte 4 Byte 3 Shared he Ethernet Individual Address Ethernet Individual Address HW 02h 04 Byte 6 Byte 5 Shared IA 6 5 03h 06 Reserved SW 0800h 04h 08 Reserved SW FFFFh 05h 0A Image Version Information 1 SW 06h OCh Reserved SW FFFFh 07h OEh Reserved SW FFFFh 08h 10h PBA Low SW 09h 12h PBA High SW OAh 14h PCI Initialization Control Word HW PCI OBh 16h Subsystem ID HW PCI OCh 18h Subsystem Vendor ID HW PCI ODh 1Ah Device ID HW PCI OEh 1Ch Vendor ID HW PCI OFh 1Eh Device REV ID HW PCI 10h 20h LAN Power Consumption HW PCI 11h 22h Reserved 12h 24h Reserved 13h 26h Shared Initialization Control Word Hw Shared A HW 14h 28h Extended Configuration Word 1 Shared l HW 15h 2Ah Extended Configuration Word 2 Shared 16h 2Ch Extended Configuration Word 3 HW g Shared HW 17h 2Eh LEDCTL 1 Shared HW 18h 30h LEDCTL 0 2 Shared 19h 32h Future Ini
24. ing Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use See http www intel com products ht Hyperthreading more htm for additional information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 5937 Denver CO 80217 9808 or call in North America 1 800 548 4725 Europe 44 0 1793 431 155 France 44 0 1793 421 777 Germany 44 0 1793 421 333 other Countries 708 296 9333 Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2008 Intel Corporation All Rights Reserved m e NVM Information Guide l CH8 n tel Contents 1 0 Non Volatile Memory NVM c ccc cece mmm ener nennen 5 1 1 lintrodictlOPi 5 over Asics oe rc br rre Deka Vp CE pa eei e cr Ke Orne on ba Ca ada p E armies 5 1 2 NVM Programming Procedure Overview sss mme nemen nene 5 1 3 EEUPDATE Utility suriet i XRER ERR ERR RENE RARO ERA A ER BA MGR EUREN ERI RARE 7 1
25. llow Legacy OS Wakeup Support menu option changes DBS Disable Boot Selection If set to 1b no changes to the boot order menu option is allowed The default for this bit is Ob allow boot order menu option changes I CH8 NVM Information Guide 1 4 23 3 Table 20 Bit DPS Name intel Description Disable Protocol Select If set to 1b no changes to the boot protocol is allowed The default for this bit is Ob allow changes to the boot protocol DTM Disable Title Message If set to 1b the title message displaying the version of the boot agent is suppressed the Control S message is also suppressed This is for OEMs who do not want the boot agent to display any messages at system boot The default for this bit is Ob allow the title message that displays the version of the boot agent and the Control S message DSM Disable Setup Menu If set to 1b no invoking the setup menu by pressing Control S is allowed In this case the EEPROM can only be changed via an external program The default for this bit is Ob allow invoking the setup menu by pressing Control S Boot Agent Configuration Customization Options Word 32h Word 32h is used to store the version of the boot agent that is stored in the Flash image When the Boot Agent loads it can check this value to determine if any first time configuration needs to be performed The agent then updates this word with its versio
26. ly relevant when power management is enabled LAN Power Consumption Word 10h Bit Name Default Description ODh for 82566 The value in this field is reflected in the PCI Power Management 15 8 LAN DO Data Register of the LAN function for DO power consumption and l Power dissipation Data Select 0 or 4 Power is defined in 100 mW 04h for 82562V units and includes the external logic required for the LAN function 7 5 Reserved 000b These bits are reserved and should be set to 000b The value in this field is reflected in the PCI Power Management 00001b for 82566 Data Register of the LAN function for D3 power consumption and LAN D3 dissipation Data Select 3 or 7 Power is defined in 100 mW Power units and includes the external logic required for the LAN function 00010b for 82562V The most significant bits in the Data Register that reflects the power values are padded with zeros 4 0 I CH8 NVM Information Guide 1 4 15 Shared Initialization Control Word 13h This word controls general initialization values Table 11 Shared Initialization Control Word 13h Bit Name Default Description 15 14 SIGN 10b Valid Indication This is a 2 bit field indicating whether a valid NVM is present to the MAC If this field does not equal 10b the MAC does not read the NVM data and uses default values for device configuration 00b Invalid NVM 01b Invalid NVM 10b Valid NVM
27. mms prerelease_terms htm carefully before using any Intel pre release product including any evaluation development or reference hardware and or software product collectively Pre Release Product By using the Pre Release Product you indicate your acceptance of these terms which constitute the agreement the Agreement between you and Intel Corporation Intel In the event that you do not agree with any of these terms and conditions do not use or install the Pre Release Product and promptly return it unused to Intel Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details This document contains information on products in the design phase of development The information here is subject to change without notice Do not finalize a design with this information The I O Control Hub ICH8 may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Hyper Thread
28. n Some diagnostic tools to report the version of the Boot Agent in the Flash also read this word This word is only valid if the PPB is set to Ob Otherwise the contents might be undefined Boot Agent Configuration Customization Options Word 32h Bit Name Description 15 12 MAJ OR PXE boot agent major version The default for these bits is 0001b 11 8 MINOR PXE boot agent minor version The default for these bits is 0010b 7 0 BUILD PXE boot agent build number The default for these bits is 00101000b 21 m e n tel NVM I nformation Guide l CH8 1 4 23 4 Table 21 1 4 24 Note 22 I BA Capabilities Word 33h Word 33h is used to enumerate the boot technologies that have been programmed into the Flash It is updated by IBA configuration tools and is not updated or read by IBA I BA Capabilities Bit Name Description Signature These bits must be set to 01b to indicate that this word has 15 14 SIG been programmed by the agent or other configuration software 13 5 Reserved Reserved for future use All bits must be set to Ob SAN capability is present in Flash 4 SAN Ob The SAN capability is not present default 1b The SAN capability is present EFI UNDI capability is present in Flash 3 EFI Ob The RPL code is not present default 1b The RPL code is present 2 Reserved Reserved Must be set to Ob PXE UNDI capability is present in Flash 1 UNDI 1b The
29. n setup options stored in word 30h These options are those that can be changed by using the Control S setup menu or by using the IBA Intel Boot Agent utility Note that these settings only apply to Boot Agent software Table 18 Boot Agent Main Setup Options Bit Name Description PXE Presence Setting this bit to Ob Indicates that the image in the Flash contains a PXE image Setting this bit to 1b indicates that no PXE image is contained 15 PPB The default for this bit is Ob for backwards compatibility with existing systems already in the field If this bit is set to Ob EEPROM word 32h PXE Version is valid When EPB is set to 1b and this bit is set to Ob indicates that both images are present in the Flash EFI Presence Setting this bit to 1b Indicates that the image in the Flash contains an EFI image Setting this bit to Ob indicates that no EFI image is contained 14 EPB The default for this bit is Ob for backwards compatibility with existing systems already in the field If this bit is set to 1b EEPROM word 33h EFI Version is valid When PPB is set to Ob and this bit is set to 1b indicates that both images PXE and EFI are present in the Flash 13 Reserved Reserved for future use This bit must be set to Ob Force Full Duplex 12 FDP Set this bit to Ob for half duplex and 1b for full duplex Note that this bit is a don t care unless bits 10 and 11 are set Force Speed These bits determine speed 01b
30. nd 83 ms off Note This field initializes the GLOBAL_BLINK_MODE field in the LEDCTL register This bit is reserved and should be set to Ob 3 0 LEDO Mode 0100b These bits represent the initial value of the LEDO_MODE field which specifies the event state or pattern displayed on LEDO Link Activity output Table 16 defines the values for LEDO Mode Table 16 LED Modes above summarizes the LED modes defined in bits 3 0 of this word Future I nitialization Word 1 Words 19h Bit Name Default Description This field is loaded to bits 15 0 of the FEXTNVM register 15 0 Reserved X For the 82562V must be set to 301h For 82566 SKUs that include ACBS must be set to 181h For 82566 SKUs without ACBS must be set to 301h Future Init Word 2 Word 1Ah Bit Name Default Description Reserved This field is loaded to bits 15 0 of the FEXTNVM register 15 0 Reserved X For ICH8 set these bits to 0800h For I CH8M All 82566 SKUs that include ACBS must be set to 0803h All 82566 SKUs without ACBS must be set to 2803h 17 intel NVM I nformation Guide l CH8 1 4 23 PXE Words Words 30h 3Eh Words 30h through 3Eh bytes 60h through 7Dh have been reserved for configuration and version values to be used by PXE code 1 4 23 1 Boot Agent Main Setup Options Word 30h The boot agent software configuration is controlled by the NVM with the mai
31. ork administrator to customize the operation of the software These settings cannot be changed from within the Control S setup menu or the IBA Intel Boot Agent utility The lower byte contains settings that would typically be configured by a network administrator using the Intel Boot Agent utility these settings generally control which setup menu options are changeable The upper byte are generally settings that would be used by an OEM to control the operation of the agent in a LOM environment although there is nothing in the agent to prevent their use on a NIC implementation 19 Table 19 20 intel NVM I nformation Guide l CH8 Boot Agent Configuration Customization Options Word 31h Bit Name Description 15 14 SIG Signature These bits must be set to 01b to indicate that this word has been programmed by the agent or other configuration software 13 11 Reserved Reserved for future use All bits must be set to Ob 10 8 MODE Selects the agent s boot order setup mode This field changes the agent s default behavior in order to make it compatible with systems that do not completely support the BBS and PnP Expansion ROM standards Valid values and their meanings are 000b Normal behavior The agent attempts to detect BBS and PnP Expansion ROM support as it normally does 001b Force Legacy mode The agent does not attempt to detect BBS or PnP Expansion ROM supports in the BIOS and assumes the
32. ory Mapped Configuration registers must be set to their default value of 0000 0000h The GbE Protected Range registers are described in the ICH8 EDS 5 If you are using the 82566 the ICH8 soft strap for the GLCI interface must be set correctly Bit 19 of STRPO must be set to 1b as described in the ICH8 EDS For the 82562V this bit can be set to Ob since it does not use the GLCI bus I CH8 NVM Information Guide n tel 1 3 1 3 1 Example 1 6 The sector size of the NVM must equal 256 bytes 4 KB or 64 KB When a Flash device that uses a 64 KB sector erase is used the GbE region size must equal 128 KB If the Flash part uses a 4 KB or 256 byte sector erase then the GbE region size must be set to 8 KB The NVM image contains both static and dynamic data The static data is the basic platform configuration and includes OEM specific configuration bits as well as the unique Printed Circuit Board Assembly PBA The dynamic data holds the product s Ethernet Individual Address IA and Checksum This file can be created in a simple text editor and follows the format shown in Appendix A which provides examples of GbE Region NVM maps for I CH8 based designs Fast Ethernet 82562V images are also provided EEUPDATE Utility Intel has created an EEUPDATE utility that can be used to update the GbE region images during in circuit programming The tool uses two basic data files outlined in the following section static data
33. receeaueeeaess 12 10 LAN Power Consumption Word 10h ccecceee eee ee eee ee ene etree eee ener 12 11 Shared Initialization Control Word 13h ccccccceccceeecee Hem mem menn 13 12 Extended Configuration Word 1 Word lAb Lk mmm nnns 14 13 Extended Configuration Word 2 Word 15h mmm nennen nnns 14 m e n tel I CH8 NVM Information Guide 14 Extended Configuration Word 3 Word 16h sss nnne 15 LED 1 Configuration and Power Management Word 17h 16 LED Modes oo EUER ER EUER ERA signals MERE VR NGER E TRAET M KG Ro URGE 17 LED O0 and 2 Configuration Defaults Word 18h sssssssssseeen nemen 18 Boot Agent Main Setup Options nn eee ee eae nn 19 Boot Agent Configuration Customization Options Word 31h 20 Boot Agent Configuration Customization Options Word 32h 21 IBA Capabilities ii nere et ennt ren set d pcne ri E Ta puce 22 LAN NVM Contents Revision History Rev Rev Date Description 2 8 Jan 2008 Updated bit descriptions for words OFh 13h 14h 15h 16h 32h and 33h Updated NVM images in Appendix A 2 7 Oct 2007 Updated word 19h bit descriptions Removed section 1 5 2 6 April 2007 Updated Table 15 bits 13 12 description and Table 24 word OFh 2 5 April 2007 Removed all references to ICH9 Minor edit all sections 2 4 Jan 2007 Updated sections 1 2 1 4 6 1 4 13 1 4 14 1 4 19 and 1 4 20 Added sections 1 4 25 1 through 1 4 25 4 PXE words 30h through 33h
34. rrrrsrerrrrrrrrrene 14 1 4 19 LED 1 Configuration and Power Management Word 17h 15 1 4 20 LED 0 and 2 Configuration Defaults Word 18h sss 16 1 4 21 Future Initialization Word 1 Words 19h cssssse Hmm 17 1 4 22 Future I nit Word 2 Word 1Ah ssssssssesne Hehe eene enn 17 1 4 23 PXE Words Words 30h 3Eh isssssssssss n Hmm eene een 18 1 4 24 Checksum Word 3Fh ccccccccce cscs e cece IH em hehehe nennen needs 22 A ICH8 NVM Contents and Sample Images rr nr n nn 23 A 1 82566DM NVM Image with ICH8 LL ene nara ener 24 A 2 82566MM NVM Image with ICH8M LL eee neta nn mnn 25 A 3 82566MC NVM Image with ICHB L rr nnn eterna 26 A 4 82562V NVM Image with ICHB LL nee teenage 27 Tables 1 CAN NVM Address Map oett a a a reni ur Sai wena a tbv e Parra je 8 2 Ethernet Individual Address Words OOH 02h kr kr rkant nanna 9 3 Reserved Word 03h issssssssssee HH eme rese en ene aae aa eaae eaae ae nnn 9 4 Reserved Word 04h Lee eH Hehe meses emassa aenea aene nena nena nn 10 5 Image Version Information Word O5h Lee eter eee ee eee eee ene nnn 10 6 Reserved Word 06h ccccccccccccceeeeeeeeeeee Hehe hemina sek STEE R ERIE RE AERE eaae aa nena n 10 7 Reserved Word 07h Lee e Hee ehe KERA ANKE KAN ease adea ane eene nana 10 8 PCI Initialization Control Word Word OAN LK KEEA EE KE KEEP EN nen 11 9 Device IDs for Intel Platform LAN Connects cccccececeeccceceeececeececeuceeeucesaeee
35. tialization Word 1 HW 0000h Shared Wn ia HW 1Ah 34h Future Initialization Word 2 0000h Shared I CH8 NVM Information Guide 1 4 1 Table 2 Note 1 4 2 Table 3 LAN NVM Word Byte Offset Offset High Byte Bits 15 8 Low Byte Bits 7 0 Used By Image Value 2Fh 5Eh 1Bh to 32h to Reserved 30hto 60h to PXE Software Region PXE 3Eh 7Ch 3Fh 7Eh Software Checksum bytes 00h through 7Dh SW Notes l SW Software This is access from the network configuration tools and drivers 2 PXE PXE Boot Agent This is access from the PXE Option ROM code in BIOS 3 HW Shared Hardware Shared This is read on when the Shared Configuration is reset 4 HW PCI Hardware PCI This is read when the PCI Configuration is reset Ethernet I ndividual Address Words OOh 02h The Ethernet Individual Address IA is a six byte field that must be unique for each adapter card or LOM and unique for each copy of the NVM image The first three bytes are vendor specific For example these bytes equal 00 AA 00 or 00 AO C9 for Intel products The last three bytes must be unique for each copy of the NVM OEM versions of the product might be required to have non Intel ID s in the first three byte positions The value from this field is loaded into the Receive Address Register 0 RALO RAHO The Intel default is listed in Table 2 Ethernet I ndividual Address Words OOh
36. tion Control Word Word OAh Bit Name Default Description 15 13 Reserved 000b This field is reserved and should be set to 000b 12 Reserved 1b This field is reserved and should be set to 1b 11 8 Reserved 0000b These bits are reserved and should be set to 0000b AUX PWR 1b This bit is used as an auxiliary power indication It is used in conjunction with the PM Enable bit Ob D3cold wake up is not advertised 1b D3cold wake up is advertised in the PMC register of the PCI function if the PM Enable bit is also set PM Ena 1b This bit enables the assertion of a PME in the PCI function at any power state Ob PME functionality is disabled 1b PME functionality is enabled This bit affects the advertised PME_Support indication in the PMC register of the PCI function 5 3 Reserved 00b This bit is reserved and should be set to 00b APM Enable 1b When APM Enable is set both the PHY 82566 or 82562V and the MAC should be initialized to a functional state following power up Ob APM functionality is disabled 1b APM functionality is enabled Note This is a reserved bit for the ICH8 B1 stepping Load Subsystem IDs Load Vendor Device IDs 1b 1b Ob Device loads the default PCI Subsystem ID and Subsystem Vendor ID 1b Device loads its PCle Subsystem ID and Subsystem Vendor ID from the NVM words OBh
37. uration Defaults Word 18h Bit Name Default Description This bit indicates the initial value of the LED2 BLINK field 15 LED2 Blink Ob Ob LED2 is non blinking 1b LED2 is blinking This bit indicates the initial value of the LED2 IVRT field 14 LED2 Invert Ob Ob LED2 has an active low output 1b LED2 has an active high output This bit defines the LED2 blink mode Ob Blink at 200 ms on and 200 ms off 13 Rep Blink Mode 1b Blink at 83 ms on and 83 ms off Note This field should be identical to the LEDO Blink Mode 12 Reserved Ob This bit is reserved and should be set to Ob These bits represent the initial value of the LED2_MODE field which specifies the event state or pattern displayed on LED2 11 8 LED2 Mode 0110b LINK_100 output A value of 0110b causes this to indicate 100 Mb s operation 16 I CH8 NVM Information Guide Table 17 1 4 21 1 4 22 intel LED O and 2 Configuration Defaults Word 18h Bit Name LEDO Blink Default 1b Description This bit indicates the initial value of the LEDO BLINK field Ob LEDO is non blinking recommended 1b LEDO is blinking LEDO Invert Ob This bit indicates the initial value of the LEDO_IVRT field Ob LEDO has an active low output 1b LEDO has an active high output LEDO Blink Mode Reserved Ob Ob This bit define the LEDO blink mode Ob Blink at 200 ms on and 200 ms off 1b Blink at 83 ms on a
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