Intel 6300ESB ICH User's Manual
Contents
1. B3518 03 10 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i n e Product Overview 1 4 1 Memory Subsystem The memory subsystem is designed to support Double Data Rate2 DDR2 Synchronous Dynamic Random Access Memory SDRAM using the Intel R E7520 MCH The MCH provides two independent DDR channels which support DDR2 400 DIMMs The peak bandwidth of each DDR2 branch channel is 3 2 Gbyte s 8 bytes x 400 MT s with DDR2 400 The two DDR2 channels from the MCH operate in lock step the effective overall peak bandwidth of the DDR2 memory subsystem is 6 4 Gbyte s for DDR2 400 Table 2 shows all DIMM technology supported by the CRB Other DIMM types are not supported Table 2 Supported DIMM Module Types Technology Organization SDRAM Chips DIMM 8 Mbytes x 8 x 4 banks 8 256 Mbit 16 Mbytes x 4 x 4 banks 16 16 Mbytes x 8 x 4 banks 8 512 Mbit 32 Mbytes x 4 x 4 banks 16 32 Mbytes x 8 x 4 banks 8 1 Gbit 64 Mbytes x 4 x 4 banks 16 1 4 2 DIMM Placement DDR2 400 Table 3 DIMM Placement DDR2 400 DIMM Configuration DIMM1 DIMM2 1 Single Rank Empty Single Rank 1 Dual Rank Empty Dual Rank 2 Single Rank Single Rank Single Rank 1 Dual Rank 1 Single Rank Single Rank Dual Rank 2 Dual Rank Dual Rank Dual Rank NOTES 1 Populate DIMMs starting with the sockets farthest away from the MCH DIMM s2. h J4H6 J4J1 J J4J2 J4K1 J4K2 J3J1 J3J2 J4J7 J4J5 EZI J5F113 J8J1 B3520 03 32 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i ntel Debug Procedure Debug Procedure 6 The debug procedures in this section are used to determine baseline functionality for the Intel Xeon Processor with 800 MHz System Bus Intel E7520 Chipset and Intel 6300ESB ICH Development Kit This is a cursory set of tests designed to provide a level of confidence in the platform operation 6 1 Level 1 Debug Port 80 BIOS Refer to the steps in Table 6 when debugging a board that does not boot Table 6 Level 1 Debug Port 80 BIOS Item Test Pass Fail Criteria Cause of Failure 1 Verify SYSTEM PWRGD LED CR2H1 Green Power Sequence Failure go immediately to Level 2 debug Is PCI Reset LED decimalon Decimal on Port 80 display 2 2 DS1J2 illuminated Red PCI Reset Stuck go to Level 3 debug 3 Verify CPURST LED is off CR7K3 Off CPU Reset Stuck go to Level 3 debug System Hang Check BIOS go to level 3 debug Refer to AMI BIOS documentation for details Also refer to Schematic Page 68 Coord D5 Port 80 LEDs are posting 4 Verify Port 80 Posting boot codes and stopping Contact your Intel Representative for the latest BIOS 5 Check BIOS revision Latest BIOS installed image 6 Veri
3. 4 1 Jumpers Figure 4 depicts all jumpers on the CRB Table 4 illustrates the settings and usage of the jumpers Review Table 4 and Figure 4 before changing default setting of the jumpers on the CRB Figure 4 Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board Jumper J5E112 UU mtele p J5F1 6300ESB i SEP Users Controller J5F113 E s mm Oo Sa J4G5 ol 1a J4G6 J5H2 e J262 J4H1 J2G3 r1 J5H1 J4H5 J4ua lH J2H114 r Janan J5H3 J4J3 54 J5H6 waste J4J2 J3J1 J3J2 B B J4J7 J4J5 JAKA J4K2 D B3520 02 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 21 Jumpers and Headers Table 4 Jumper Settings Sheet 1 of 3 n Jumper Name Ref Des Description Settings Default Position 3 3V Aux Enable J1A1 Enables 3 3 V AUX 1 2 Enable 3 3 V AUX for wake events Open 3 3 V Operation Only 1 2 Enable PXH J2G2 Enable PXH 1 2 Enable Open Disable 1 2 No Reboot J2G3 Prevents the system from rebooting following a reset from Intel 6300ESB I O Controller 1 2 No Reboot Open Normal Open Enable Super I O Chip J2J1 Enable on SIO 1 2 Enable Open Disable 1 2 5V Aux Enable J3A1 Enables 5 V AUX 1 2 Enable 5 V VAUX for wake events Open 3 3 V Operation Only 1 2 CPUO Present O
4. Processors i 2 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 35 L Heatsink Assembly l ntel 7 1 Processor Heat Sink Installation Instructions Note Tools items needed include Phillips screwdriver disposable towels and isopropyl alcohol 1 Ensure the processor is firmly seated in the socket and the socket latch is closed See Figure 12 Figure 12 Inserting Processor in Socket 2 Clean the processor s top surface with a clean towel and isopropyl alcohol See Figure 13 Figure 13 Cleaning the Processor Surface 36 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual a l ntel Heatsink Assembly 3 Insert the processor heat sink back plate into the four mounting holes near the processor The back plate is assembled to the back side of the PCB See Figure 14 Figure 14 Installing the Processor Backplate 4 Remove the protective covers from the processor heat sink There is a cover that protects the fan and another that protects the preapplied thermal interface material on the bottom of the heat sink base See Figure 15 Figure 15 Removing the Protective Covers Remove plastic 5 Place the heat sink on top of the CPU and align the four screws to the threads of the backplate Intel Xeon Processor Intel E7520 Chipset Intel 6300E
5. 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 400 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 OFF 1 0 1 1 1 1 1 4750 30 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i ntel System Overview Table 5 Processor VRD Settings Sheet 2 of 2 0 1 1 1 1 1 OFF 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 31 System Overview 5 7 Figure 10 Miscellaneous Buttons Figure 10 below shows the location of the power buttons within the platform Power Buttons J2G3 o J2H114 r z J262 J5E112 o 4 o C Intel 6300ESB 1 0 Controller p J5F1 ses I Dd an Lij Jaso z J4G6 JsH2 JAH1 J5H1 J4H5 y4H3 O Janan J5H3 J4J3
6. STPCLK Inject J4J1 Ni peat dines Open Inject FORCEPR1 Signal FORCEPRI inject J4J2 eu ene a Open Override VRM disable if CPU1 is not present CPU1 Present Override J4J5 1 2 Override Open Open Normal Override VRM disable if BSELs do not match BSEL Match Override J4J7 1 2 Override Open Open Normal 1 2 VID 5 3 4 VID 4 5 6 VID 3 As CPU1 VID J4K1 7 8 VID 2 Required 9 10 VID 1 11 12 VID 0 Manual VID select CPU1 VID Override J4K2 1 2 Manual select Open Open CPU select Access to MCH SMbus Do not install Jumper MCH SMBus Header J5D3 1 MCH _SMBDAT Open 2 Ground 3 MCH_SMBCLK See MCH Documentation for alternative Gear PECON J5E112 Ratios for MCH FSB Memory Soon Intel 6300ESB I O Intel 6300ESB I O Controller Top Swap Controller Top Swap FWH J5F1 1 2 Top Swap Open Memory Swap Open Normal See MCH Documentation for alternative Gear FEES J5F113 Ratios for MCH FSB Memory SOR Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 23 Jumpers and Headers n Table 4 Jumper Settings Sheet 3 of 3 Jumper Name Ref Des Description Settings Default Position nigl 6300ESB l G i Intel 6300ESB I O Controller Safe Mode nte ontroller Safe Mode J5F3 1 2 Safe Mode Open Open Normal Mode Clears CMOS CMOS Clear J5H1 1 2 Normal 1 2 2 3 Configure cu Validation only Validation Onl J5H2 O mee d Do Not Install Jumper Per Ac
7. an application is reduced because the platform is returned to the same system state as when the preceding power off occurred Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual n 2 3 6 2 3 7 2 3 8 2 3 9 2 4 2 5 Note Platform Management S5 State This state is the normal off state whether entered through the Power Button or Soft Off All power is shut off except for the logic required to restart The system remains in the S5 State only while the power supply is plugged into the electrical outlet If the power supply is unplugged this is considered a Mechanical OFF or G3 Wake Up Events The types of wake up events and wake up latencies are related to the actual power rails available to the system in a particular sleep state as well as to the location in which the system context is stored Regardless of the Sleep State Wake on the Power Button is always supported except in a mechanical off situation When in a Sleep State the system complies with the PCI specification by supplying the optional 3 3 V standby voltage to each PCI slot as well as the PME signal This enables any compliant PCI card to wake up the system from supported sleep states except Mechanical Off Wake on USB Wake on PS 2 and Wake on LAN are not supported Wake Up from S1 Sleep State During S1 the system is fully powered permitting support for PCI Express Wake and Wake on PCI PME Wake U
8. attempts to gracefully put the system to sleep by first going into the processor C2 state 2 3 1 SO State This is the normal operating state even though there are some power savings modes in this state using processor Halt and Stop Clock processor C1 and C2 states SO affords the fastest wake up response time of any sleep state because the system remains fully powered and memory is intact Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 13 n Platform Management ntel 2 3 2 2 3 3 2 3 4 2 3 5 14 S1 State This state is entered via a processor Sleep signal from the I O controller processor C3 state The system remains fully powered with memory contents intact but the processors enter their lowest power state The operating system disables bus masters for uniprocessor configurations while flushing and invalidating caches before entering this state in multiprocessor configurations Wake up latency is slightly longer in this state than in S0 however power savings are improved from SO S2 State This state is not supported S3 State This state is called Suspend to RAM STR The system context is maintained in system DRAM but power is shut off to non critical circuits Memory is retained and refreshes continue All clocks stop except the RTC S3 is entered when the I O controller asserts the SLP_S3 signal to downstream circuitry to control 1 8 V power plane swi
9. nanna ke ka ana 27 8 SMBus Block Diagram ee ee R y An KER RE kan oer eee 28 9 IRO Routing Dire E 29 INE uei Ig I M 32 11 Components Requiring Heat Sink Assembly iu Ek kak kk kk eene 35 12 Inserting Processor in SOCKOL i 4li k kyk kiyanke ak bkan kar n k na vak an ba kaka kaban dk ki kn nawka ka b nennen nenne 36 13 Cleaning the Processor Surface ssssssssssssssessseeeeenen nennen AA AKA AA AA AKA AA AK A AA WAK KA 36 14 Installing the Processor Backplate iinlain naski lak ak k k ka kak a sna kena kaka aka ka akr a 37 15 Removing the Protective Covers i aldkdadkk dkldlaklkakkladkakakllkakalaklaklk naana kak kd dka a kalk ka kwa ak d k k aka 37 16 Installing ihe Heatsink ocurren ti tenerte trei cer Aker n w aeo n BER n e e uae Pk eee 38 Tables 1 Related DOCUMOM DD e ete terr tenete EE eee 7 2 Supported DIMM Module Types ll l ll Eka kak eene enne AA AK KA rene 11 3 DIMM Placement DDR2 400 4 i x an nk kck lyeak e xa a abl kaks s b kaks k la w ka kk de sten nnns 11 4 JUMPEr SCtINGS ics ECCE 22 5 Processor VRD Settings cerci nere ka a k na k n et ie d Ml n n Ah n DR kU buk r kn dene dr aA RAB K k 30 6 Level 1 Debug Port 80 BIOS ssssssssssseseseeee nennen enne nnns rn k r kd ad kaka W k 33 7 Level2 Debug Power Sequence esses eene nenne enn nn
10. registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2004 Intel Corporation 2 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual ntel Contents Contents 1 Product ONENEN m nr ww YY gt gt oa r o gm 7 1 1 iiec ETT 7 1 2 Product GContents x seed reci ned ctae lia da nn l n A annee ee dug eub n Ki a Weki e wande iE 7 to Products DN T D H DD E T 8 l BR de dbn II as rd r r r rrr 9 1 4 1 Memory Subsystein err reiten er kaye xwea KA ka ed Re lm er sya lav a la 11 1 4 22 DIMM Placement DDR2 1 y y xku cx 4kxxlakala nanek makllkakuk a klan khe ka R 11 1 5 Memory Population Rules and Configurations sene 12 2 Platform Management carissime Lectus caet su a z n yed kena selek ke ea rra ben k derd RENE AN b 13 2 1 aio i em 13 22 SOT OM eect C M 13 2 3 Sleep States Supported enciende Le edet ad du pd v c EY n 13 AL SOU SUAS E 13 Qi Sie DM UALS c dek 14 KIR Db T O 14 2 9 4 S9 Stalin e k l exu ken a cde aa ad anek anek dy d n Re cedit un 14 SR CE 14 e DO ICI PE 15 2 9 7 WKOD EVS Vr lb eii leb gpoxa gy gt o ERU Pedk ere ee E uEdE 15 2 8 8
11. the Intel 6300ESB I O Controller uses these segments e RQIA and 15 for IDE segment SERIRQ for SIOPIXRQ segment PCRIRQ for the PCI X segment PIRQ for the PCI 32 33 segment A Message Signalled Interrupt MSI scheme is used between the MCH and PXH over the PCI System Overview Express bus The PXH uses PAIRQ for the Channel A interface to PCI X 64 bit 100 MHz peripherals and PBIRQ for the Channel B interface to PCI X 64 133 MSI and Non Maskable Interrupt NMI are connected from the Intel 6300ESB I O Controller to CPUO and CPUI The platform also supports MSI for maskable and non maskable interrupts Figure 9 IRQ Routing Diagram PCI E 8x PCI X SLOT PCI X SLOT PCI X SLOT REQ GNT 0 REQ GNT 0 REQ GNT 1 IDSEL AD17 IDSEL AD17 IDSEL AD18 e 0 9 g 32 lt 2 x9 A 3j S o 0 PXH 1 lt S o2 x3 Ba o a 4 4 x 5 30 6 9 7 F PCI X SLOT Video REQ GNT 0 REQ GNT 1 IDE IDSEL AD16 IDSEL AD17 ABCD A IRQ14 15 AK 8 B J oE x PCI X SLOT PCI X SLOT T D j 9 REQ GNT 0 REQ GNT 1 Intel amp E IDSEL AD17 IDSEL AD18 6300 ESB Mar A BC D ABCD Controller G Hub H X o amp Cx SERIRQ D lt SIO
12. when applicable Drivers included on CD Red Hat 8 0 Compatible Driver Package Contents This operating system compatible driver package is available from http downloadfinder intel com scripts df Detail_Desc asp agr Y amp ProductID 1706 amp DwnldID 7249 esb_rh8 txt Release notes sources ac97 alsa driver 0 9 0rc5 bz2 alsa driver sources sources ac97 alsa lib 0 9 0rc5 bz2 alsa lib sources sources ac97 alsa util 0 9 0rc5 bz2 alsa util sources sources ac97 alsa xmms 0 9 9b tar gz alsa plugin for xmms sources ac97 xmms mpg123 1 2 7 13 i386 rpm mpeg plugin for xmms sources kernel linux 2 4 20 tar gz 2 4 20 kernel sources sources kernel config 2 4 20 p4 upapic i2c apm nooss UP Kernel Config File sources kernel config 2 4 20 p4 upapic i2c acpi nooss UP Kernel Config File sources kernel config 2 4 20 p4 smp i2c apm nooss MP Kernel Config File sources smbus i2c 2 7 0 tar gz latest l2C core driver sources sources smbus Im_sensors 2 7 0 tar gz latest smbus adapter sensor sources sources esbwdt LICENSElicense for Intel WDT driver sources esbwdt esbwdt doc txt Linux WDT Driver release notes sources esbwadt driver esbwdt c Linux WDT Driver source file sources esbwadt driver esbwdt h Linux WDT Driver header file sources esbwadt driver Makefile Linux WDT Driver Makefile sources esbwdt demoapp esbwdt demo c WDT driver demo application patches COPYING GPL v2 license for Intel patches patches ac97 alsa hr patch enables ESB AC97 AC in ALSA patches ac97 alsa
13. B2940 02 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 29 System Overview n 5 6 VRD VID Headers Provides for manual control of the processor core voltage regulator output level s Normally the processor should be run at its default VID voltage identification value as set during manufacturing However in the event the user needs to set a different VID value from the default value it can be accomplished through a jumper block found on the board Note that these headers are not populated by default The CPU 0 VID header is located at JOK2 CPU 1 VID header is located at J4K1 Table 5 provides the VID settings available via the VID headers Table 5 Processor VRD Settings Sheet 1 of 2 VID5 VID4 VID3 VID2 VID1 VIDO VID5 VID4 VID3 VID2 VID1 VIDO 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1
14. Intel Xeon Processor with 800 MHz System Bus Intel E7520 Chipset and Intel 6300ESB ICH Development Kit User s Manual September 2004 Reference Number 300281 003 Contents n INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL amp PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice This User s Manual as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be pr
15. SB ICH Development Kit User s Manual 37 n Heatsink Assembly l ntel Figure 16 Installing the Heatsink 38 Tighten screw 1 Tighten screw 4 f Tighten screw 3 7C L Tighten screw 2 6 Using a Phillips screwdriver tighten the screws in the pattern indicated in Figure 16 The screws are shoulder screws and will stop threading once completely tightened 7 Plug the fan connector into the nearest fan connector on the PCB 8 If applicable repeat this process for the second processor Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual
16. SMB SYS SMBus Driver SMB INF Install file for SMBus driver SMB CAT SMBus driver security catalog file STAC97 SYS AC 97 audio code driver provided by SigmaTel SLAoemisv1 doc Single user and OEM license for SigmaTel STA97 driver WDTDRVR SYS Watchdog Timer driver WDTDRVR INF Install file for Watchdog Timer driver WDT LICENSE TXT Generic Alpha license for Watchdog Timer components WDTDEMO EXE Demo program for exercising Watchdog Timer features Mfc42 dll Microsoft C runtime library Mfco42 dll Microsoft C runtime library Msvcrtd dll Mircosoft C runtime library wdtdemoAppSpec pdf WdtDemo App user documentation wdtdriverspec pdf Overview of Watchdog Timer driver Intelwdtapi pdf Watchdog Timer driver interface API document IWDTLIB DLL Watchdog Timer Interface Dynamic Link Library CWESB slx eXP Configuration file WESB log log of OS build for eXP eXP README DOC readme of eXP build infinst enu exe Intel INF update utility Third Party Drivers Included on the CD is software compatible with the ATI Rage Mobility M Graphics Accelerator 021112a 006561C ATI zip Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i ntel amp Jumpers and Headers Jumpers and Headers amp This section describes the platform component placement as well as configuration test and debug features of the Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board
17. Wake Up from S1 Sleep State eessessssssseeeeeeeen enitn nnne 15 2 8 9 Wake Up from S4 and S5 States seessssssssseee essent 15 24 POL EM SUP POM c 15 25 Plattorm Managemient Au alay n e capes e eyek E E 15 2 5 1 Processor Thermal Management sss nennen 16 2 0 System Fan Operallon ics cu tee E xele a baran kya en KE dane d E SE NAN ba n k 16 3 Equipment Required for CRB SAa JO i lll aa nklklak anka kla aka ka y d anan ka abal kk nennen nennen nnns 17 3 1 kc c EE 17 3 2 Driver and OS ReqUll ITIGIT S i ic y klkk ek anka s ka alakad basek ls nennen k da ak ntn nennen en 18 3 2 1 Drivers included on CD ee aeaea nkla dayik kaka d xewka alek naka snnt 18 4 Jumpers and g tel cnm 21 AN SUIT OT r Jer rar r 222 21 5 SYEICINESVISCIM M 25 5 1 Power Diagrama SM 25 TT JB cH le ku N r iere dte Peer entere s decere dte cred au TOE ORA 26 a Plationm RESCtS ics En 27 54 SMBUS f 28 6 0 Plattorm IRO RON j i lt 4cx4xx2 29 5 6 VRD VID Headers endete tine ae Mi uye dite tec n cad kuna dee d ka SEE Rea 30 5 7 Miscellaneous Buttons ssssisssesssesseeeeeseeeene kar kaka yak r kira deka ennt nennen 32 6 Deb g Procedure Po terre T E T 33 6 1 Level 1 Debug Port 80 BIOS aite credere e e
18. a pci irq hr ich5 patch integrated into the esb6300 amp ich5 southbridges patches Ispci pci ids hr patch adds esb dev ids to 2 4 9 e 24 pci ids patches Ispci pci ids hr ich5 patch adds ich5 dev ids to 2 4 9 e 24 pci ids patches smbus i2c hr patch enables esb smbus dev in i2c driver patches smbus i2c hr ich5 patch enables ich5 smbus dev in i2c driver patches smbus i2c 2 7 0 Makefile patch customizations for i2c 2 7 0 Makefile patches smbus Im sensors 2 7 0 Makefile patch customizations for Im sensors Makefile sources smbus Im sensors 2 7 0 Module mk patch patch to fix bld errs on rhas v21 patches smbus readme txt build install instructions for smbus utils debug ks cfg yyyy basic kickstart file to install from ftp to hda utils debug bldkernel pl script to build install esb enabled UP kernel utils debug bldsrcs pl script to build install esb enabled UP drivers utils debug readme txt BKM aka EASIEST way to install UP kernel amp drivers utils debug bldsmpkern pl script to build install esb enabled SMP kernel utils debug bldsmpdrivers pl script to build install esb enabled SMP drivers utils debug readme smp txt BKM aka EASIEST way to install SMP kernel amp drivers Windows Compatible Driver Package Contents This operating system compatible driver package is available from http downloadfinder intel com scripts df Detail_Desc asp agr Y amp ProductID 1706 amp DwnldID 7246 ESB windows Relnotes txt Release notes for Windows compatible drivers
19. cess to ICH SMBus Do not Install Jumper ICH SMBUS header J5H3 1 ICH_SMBDAT Open 2 Ground 3 ICH_SMBCLK 1 2 E S3 Enable J7F1 Se Enae 1 2 Open S3 Disable 1 2 Full Speed CPU1 Fan Override J7K1 1 2 k Open LM93 Controlled i 1 2 Full Speed CPUO Fan Override J8J1 1 2 u Open LM93 Controlled 4 2 2 Uni 1 2 ITP Configuration pis qii J9G3 1 2 Dual Processor 1 2 1 2 Oth t RSVD CPUO Boot Select JoH2 ef processor support SVD Open Open Intel Xeon support Manual VID select CPUO VID Override J9K1 1 2 Manual select Open Open CPU select 1 2 VID 5 3 4 VID 4 5 6 VID 3 As CPUO VID J9K2 i 7 8 VID 2 Required 9 10 VID 1 11 12 VID 0 24 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel System Overview System Overview 5 5 1 Figure 5 Power Diagrams Figure 5 shows the power distribution for the CRB Refer to the CRB schematics for details on the power distribution logic Contact your Intel field sales representative to obtain the schematics file Power Distribution Block Diagram Channel A Channel B DDR B sa CNTRL S3 Switch DDR A S3 Switch 0 8375 1 6000 V 0 8375 1 6000 V 100A 100A 650WSI EPS12V B3522 01 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 25 System Overview 5 2 Figure 6 In Platform Clocking The CRB uses
20. ct e t te inte tva eras 33 6 2 Level 2 Debug Power Sequence ik l x lkudcldlla d aklldldlllakllk lak buka lana dina k kar kw kane dad nenne 34 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 3 Contents j ntel 6 3 Level 3 Debug Voltage ReferenC S8 l iiii EEE EEE kk kK KAKA A AA AK KRA 34 7 Heatsink Assembly ze e rnmmmmmmrmrbmrrrrrmr rrrd 35 7 1 Processor Heat Sink Installation Instructions LLLL LEE EEE EEE kK KAS 36 4 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual ntel Contents Figures 1 Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board Block Diagram sse 9 2 Placement Top ViOW aL 10 3 DDR2 400 Memory DIMM Ordering kaka aka kaka kk KAK kk A AK A A AA AA A KA AA 12 4 Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board JUMPEL ccceeccccceeeeeneeceeenaeeeeeeeaaeeeceeeaeeeeeeenaaeeeeeeenaes 21 5 Power Distribution Block Diagram sess nennen nnne kk waa adkkika Waa 25 6 Clock Block Diagram y n nist ak nan da een cubes HU Bine d ka k n en Le ER ba ee a AWE na RN VE d 4 26 7 Platform Reset Diagram i ask akdak l l alla tanda dalenkanaaadayah aaawa nia aah cana aaakan xan n lena kan
21. el rhas21 q2u gold iso origin of RHAS Q2 03 updates sources smbus i2c 2 7 0 tar gz latest i2c core driver sources sources smbus Im_sensors 2 7 0 tar gz latest smbus adapter sensor sources sources esbwdt LICENSE license for Intel WDT driver sources esbwdt esbwdt doc txt esbwdt driver demoapp release notes sources esbwdt driver esbwdt c esbwat driver sources sources esbwdt driver esbwdt h esbwat driver header file sources esbwdt driver Makefile esbwat driver Makefile sources esbwdt demoapp esbwdt demo c esbwdt driver demo app patches COPYING GPL v2 license for Intel patches patches ac97 alsa hr patch enables ESB AC97 AC in alsa patches ac97 alsa hr ich5 patch enables ICH5 AC97 AC in alsa patches ide sata pci ids hr patchpatches to 2 4 9 e 24 ide driver patches ide sata pci ids hr ich5 patch patches to 2 4 9 e 24 ide driver patches ide sata piix c hr patch to enable support for pata amp sata storage interfaces patches ide sata piix c hr ich5 patch to enable support for pata amp sata storage interfaces patches ide sata ide pci hr patch integrated into the esb6300 amp ich5 southbridges patches ide sata ide pci hr ich5 patch integrated into the esb6300 amp ich5 southbridges patches ide sata pci irq hr patch integrated into the esb6300 amp ich5 southbridges Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 19 a Equipment Required for CRB Usage ntel 3 2 1 3 3 2 1 4 20 patches ide sat
22. emented Platform management involves e ACPI implementation specific details System monitoring control and response to thermal voltage and intrusion events BIOS security 2 1 Power Button The system power button is connected to the I O controller component When the button is pressed the I O controller receives the signal and transitions the system to the proper sleep state as determined by the operating system and software If the power button is pressed and held for four seconds the system powers off S5 state This feature is called power button override and is particularly helpful in case of system hang and system lock 2 2 Soft Off The I O controller incorporates a SLP_S4 output signal which routes to the power supply This signal has register access that allows software to deactivate the power supply When SLP_S4 goes active the power supply cuts main power but keeps 5 V auxiliary power rails available 5 V auxiliary voltage is active while the power supply receives AC power 2 3 Sleep States Supported The I O controller controls the system sleep states States SO S1 S3 S4 and S5 are supported The platform enters sleep states in response to BIOS operating system or user actions Normally the operating system determines which sleep state to transition into However a four second power button override event places the system immediately into S5 When transitioning into a software invoked sleep state the I O controller
23. es 3 MCH Hublink Vref R5F11 0 354 V Vref incorrect check resistor values 4 MCH Hublink Vswing R5F8 0 804 V Vswing incorrect check resistor values 5 ICH Hublink Vref R4G7 0 347 V Vref incorrect check resistor values 6 ICH Hublink Vswing R4G4 0 696 V Vswing incorrect check resistor values 7 ren ML awa E je kev Vref incorrect check resistor values g CPU1 VTT Vref R4U5 0 754 Vref incorrect check resistor values Back side of board R5V1 0 754 9 MCH VTT Vref R6F2 0 775 V Vref incorrect check resistor values 10 DIMM A DDR2 Vref R3M1 0 9 V Vref incorrect check resistor values 11 DIMM B DDR2 Vref R2M1 0 9 V Vref incorrect check resistor values 34 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel Heatsink Assembly Heatsink Assembly T This section provides heatsink assembly instructions for the Intel Xeon Processor with 800 MHz System Bus Intel E7520 Chipset and Intel 6300ESB ICH Development Kit Components requiring post secondary heat sink assembly are listed in Table 9 Table 9 Components Requiring Heat Sink Assembly Quantity per Heat Sink Component Board Manufacturer Part Number Comments Processors Up to 2 Cooler Master ESW N73CS M Active heat sink back plate See Figure 11 Figure 11 Components Requiring Heat Sink Assembly if he E p LU ILI Ea 227111
24. fan is controlled and monitored independently depending on the core temperature The LM 93 is dedicated to processor fan speed control and monitor and can be programmed with temperature limit values that allow it to speed up or idle the processor fans depending upon the input temperature Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel Equipment Required for CRB Usage Equipment Required for CRB Usage 3 The following components are required for the Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board CRB usage A 550 W SSI EPS 12 V power supply The CRB is shipped with the power supply At least two modules of DDR2 400 DIMM The CRB is shipped with 2 x 256 Mbytes of DDR2 400 Hard drive loaded with Operating System Monitor PS 2 mouse and keyboard Visually inspect the board and ensure that the MCH Intel 6300ESB I O Controller PXH and other components did not shake loose during shipment If the board has any loose or missing components contact your Intel representative Caution Powering up without all components installed correctly could lead to a power up failure that could damage the board Do not power up the board until the source of any loose component is determined and the component has been replaced on the board 3 1 Precautions The following precautions will reduce the chances of damaging the b
25. fy default Jumper settings See default settings Improper Jumper settings Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 33 Debug Procedure 6 2 Table 7 Level 2 Debug Power Sequence Check the items in Table 7 below if SYSTEM PWRGD is not illuminated Level 2 Debug Power Sequence Item Test Pass Fail Criteria Cause of Failure Measure voltage across C3K2 33V 1 Primar r l lt eke a External power supply failure imary power supply voltages C4K3 5 V p pply e C4K2 5V C4K5 12V 1 8 V C9E14 1 8 V DDR2 power supply failure 1 5V C5C5 1 5 V MCH PXH ICH core power supply failure 1 8 VSBY C9G5 1 8 V DDR2 standby power supply failure CPU VTT power supply C9H10 1 2 V CPU VTT power supply failure CPUO VRD L9J2 1 2 V 1 4 V CPUO VRD Failure CPU1 VRD L5J1 1 2 V 1 4 V CPU1 VRD Failure CO N 9 gt oO AJ WwW TI Verify SYSTEM PWRGD LED CR2H1 Green Power Sequence Failure 6 3 Level 3 Debug Voltage References Table 8 includes the first items to look at when debugging a board that does not boot Table 8 Level 3 Debug Voltage References Item Test Pass Fail Criteria Cause of Failure 1 MCH DDR2 Channel A Vref R6D4 0 9 V Vref incorrect check resistor values 2 MCHDDR2 Channel B Vref R6B3 0 9 V Vref incorrect check resistor valu
26. he dedicated PCI Express slots Memory Support Registered ECC DDR2 400 Each of the two memory channels on the Intel E7520 in this CRB supports a maximum of two DDR2 400 DIMMs per channel The maximum supported DDR2 400 memory configuration is 8 Gbyte using different combinations of single and dual ranked x4 1 Gbyte technology DIMMs limit of up to four ranks per channel 3 2 Gbytes s bus per channel bandwidth with DDR2 400 e T O slot support One PCI X 133 MHz slot from PXH Two PCI X 100 MHz slots from PXH One PCI Express x8 slot One PCI Express x4 slot One 5 V PCI 32 33 slot connected through the Intel 6300ESB I O Controller Two 3 3 V PCI X 64 66 slots connected through the Intel 6300ESB I O Controller Low Pin Count Bus National LPC 47M172 Super I O residing on LPC bus LPC card header for debug purposes only Firmware hub IDE ATA 100 support Two ATA 100 IDE connectors supported S ATA support Two S ATA connectors USB Support Four Channels Two USB 2 0 connectors Two USB 2 0 headers Back Panel I O 8 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i ntel e Product Overview Two RS 232 serial ports from the Intel 6300ESB I O Controller Two PS 2 connectors for mouse and keyboard On board VGA Video ATI Rage Mobility video controller Parallel port Dual Watchdog Timer Misce
27. hr ich5 patch enables ICH5 AC97 AC in ALSA patches ide sata pci ids hr patch enables ICH5 AC97 AC in ALSA patches ide sata pci ids hr ich5 patch patches to 2 4 20 IDE driver patches ide sata piix c hr patch to enable support for PATA amp SATA storage interfaces patches ide sata piix c hr ich5 patch to enable support for PATA amp SATA storage interfaces patches ide sata ide pci hr patch integrated into the ESB amp ICH5 Southbridges patches ide sata ide pci hr ich5 patch integrated into the ESB amp ICH5 Southbridges patches ide sata pci irq hr patch integrated into the ESB amp ICH5 Southbridges Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 3 2 1 2 Equipment Required for CRB Usage patches ide sata pci irq hr ich5 patch integrated into the ESB amp ICH5 Southbridges patches Ispci pciids 112202 patch patch to update 2 4 20 pci ids file patches Ispci pciids 112202 hr patch patch to add ESB dev IDs to pci ids patches Ispci pciids 112202 hr ich5 patch patch to add ICH5 dev IDs to pci ids patches ioapic irqbalance 2 4 20 MRC patch patch for use with P4 Hyper Threading patches smbus i2c hr patch enables ESB SMBUS dev in 12C driver patches smbus i2c hr ich5 patch enables ICH5 SMBUS dev in I2C driver patches smbus i2c 2 7 0 Makefile patch customizations for I2C 2 7 0 Makefile patches smbus Im sensors 2 7 0 Makefile patch customizations for Im sensors Makefile patches smbus readme txt build insta
28. ient temperature Additional processor thermal management requires the system to communicate to the processors when the VRD reaches a critical temperature The VR thermal monitor asserts FORCEPR_N signal to the processor The thermal monitor an LM26 is a 3 C precision thermostat used to sense high temperature conditions and drive a digital output active low This circuit works as an external PROCHOT event to further protect the processor during high current temperature conditions This forces the processor to activate a thermal protection circuit that reduces the current consumption of the processor System Fan Operation The system uses both the LM 93 and the National 87427 Super I O to monitor and control the fans in the system The LM93 uses pulse width modulated PWM outputs that can modulate the voltage across the fans providing a variable duty cycle to effect a reduced DC voltage from nominal 12 VDC The fan headers are the standard 12V three pin type used in previous Servers which support tachometer out The LM 93 also has four tachometer inputs that it can use to monitor the fans that it is controlling All fan tachometer data can be extracted from the controllers via the SMBus The system fan speed control circuit does not control the power supply fan Each PWM output has a bypass jumper that causes all fans to run at full speed and ignore the PWM control Each processor fan has its own dedicated PWM output and tachometer input so each
29. ion of power good and system reset However the glue logic within the SIO is also used to buffer reset to PXH MCH FWH and IDE Platform Reset Diagram PCI 32 EN EH PCI X PCI X Port 80 Hub SYS PWRGD 3V3 PCIRST1 FWH CPURST MCH PXH_PAPCIRST_N PCI E Li 2 i N a 6 ITP 700 SYS_RESET Intel 6300ESB y o VRM PWRGD Controller PXH_PBPCIRST_N X PCI X PCI X B2938 03 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 27 System Overview 5 4 SMBus Figure 8 below illustrates the routing of the SMBus signal among the components Figure 8 SMBus Block Diagram 3 3 VSBY Intel 6300ESB I O Controller Hub Z H tr PCI X 133 MHz avery E Slot Slot 1 3 PCI X 100 MHz Slot Slot 2 SMBus PCI X 100 MHz 09 Slot Slot 3 ITP XDP oo SMBus p PCI Express Master Only 3 3 V Slot Slot 4 Intel E7520 PCI Express Chipset SMBus Slot Slot 5 Repeater Ea remm S PCI X 66 MHz l i m DiMM A1 i Dimm B1 PROC E Addr 0xA0 Addr 0xA8 o p PCI X 66 MHz CK409B 2 Slot Slot 7 I p DIMM A2 DIMM B2 A Ao i PCI 32 bit i E T 33 MHz Slot 8 1 TRT HE DDR CH A DDR CH B B2939 03 28 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel 5 5 Platform IRQ Routing Figure 9 shows that
30. ll instruction for Im sensors binaries binaries tar gz pre build kernel and modules utils ks cfg raid015 hd acd raid0 1 amp 5 enabled kickstart file utils ks cfg noraid hda non RAID kickstart file utils debug readme up txt Instructions on using UP install scripts ks cfg noraid hda cdrom text interactiveinteractive kickstart file install bin pl script to automate UP pkg install bldsrcs pl script to automate UP pkg install readme smp txt instructions on using SMP install scripts bldsmpkernel pl script to automate SMP kernel bld install bldsmpdrivers pl script to automate SMP driver modules bld Red Hat Advanced Server 2 1 Compatible Driver Package Contents This operating system compatible driver package is available from http downloadfinder intel com scripts df Detail_Desc asp agr Y amp ProductID 1706 amp DwnldID 7248 esb_rhas txt Release notes sources ac97 alsa driver 0 9 0rc5 bz2 alsa driver sources sources ac97 alsa lib 0 9 0rc5 bz2 alsa lib sources sources ac97 alsa util 0 9 0rc5 bz2 alsa util sources sources ac97 alsa xmms 0 9 9b tar gz alsa plugin for xmms sources ac97 README build install instructions for ac97 sources kernel config 2 4 9 e 24 p4 smp i2c Optimized MP Kernel Config File sources kernel config 2 4 9 e 24 p4 upapic i2c Optimized UP Kernel Config File sources kernel install 2 4 9 e 24esb grub conf patch Patch to install UP kernel sources kernel install 2 4 9 e 24esbsmp patch Patch to install SMP kernel sources kern
31. llaneous National LM93 for fan control and temperature voltage monitoring Refer to Figure 1 for complete detailed features of the Intel Xeon Processor with 800 MHz system bus and Intel E7520 and Intel 6300ESB Customer Reference Board CRB 1 4 Block Diagram Figure 1 Intel Xeon Processor with 800 MHz System Bus and Intel E7520 and Intel 6300ESB Customer Reference Board Block Diagram ITP Intel Intel Xeon Xeon DDR2 400 PCI E spre wo w 6300ESB sm LPC Debug Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual Product Overview n Figure 2 Placement Top View oppy DODDPEPEBICOCICICHICCCOIOICICCODCOCOICCICCOCICCTPEEEIECOICOICE WENN NENN 7 Connector PXH Channel A PCI X 133 MHz TI rr Tr N NNN NNN Ni NNN Ni NNE iTENNNENNN CCCII Ti ooo Oooo PXH Channel B PCI X 100 MHz I lt ooo TEXT i ii ooo CECI 5 PXH Channel B PCI X 100 MHz TORO Oooo a NODDED OOOO 000000000000 OOOO Intel 6300ESB I O Controller PCI X 66 MHz D A OOOO D000 OOOO Inte 6300ESB I O Controller PCI X 66 MHz Foi DONADONI REC a PCI Express x8 Hi ODANIN Oe SS1 Power PCI Express x4 FILIIITITITI TIIITITITITITITIITITIITITITI c OOOK COCCOOCCOCOOOCOCOOOOOOCOCOO0 Intel 6300ESB I O Controller PCI 33 MHz 1 01 U09 09pIA QHA dO Slee Q v c e lt D s
32. lots A2 and B2 2 When populating both channels always place identical DIMMs in sockets that have the same position on channel A and channel B i e DIMM A2 should be identical to DIMM B2 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 11 Product Overview i ntel 1 5 Figure 3 12 Memory Population Rules and Configurations The system supports two DDR2 400 DIMM slots for Channel A and two DDR2 400 DIMM slots for Channel B The four slots are interleaved and placed in a row in the following order Al B1 A2 B2 with Al being closest to the MCH This design supports only registered ECC enabled DIMMs When populating both channels always place identical DIMMs in sockets that have the same position on Channel A and Channel B i e DIMM A2 should be identical to DIMM B2 In addition single rank DIMMs should be populated furthest when a combination of single rank and double rank DIMMs are used This recommendation is based on the signal integrity requirements of the DDR2 interface DDR2 400 Memory DIMM Ordering HERI z E ESR s ESA DIMM A2 DIMM B2 B3519 01 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual a ntel Platform Management Platform Management 2 The following sections describe how the system power management operates and how the different ACPI states are impl
33. ne nnne n teneret ka aa aka 34 8 Level3 Debug Voltage References sssssssesseeeeene nenne KAKA AKA KAKA AK KA AA 34 9 Components Requiring Heat Sink Assembly sssssseeeenee nennen 35 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 5 Contents Revision History 6 Date Revision Description Changed figures that referenced PCI X to PCI X 133 MHz August 2004 003 changed jumpers on Figure 4 made other miscellaneous changes July 2004 002 Changed code names to public names clarified illustrations December 2003 001 Initial release of this document Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual i ntel e Product Overview Product Overview 1 The Intel Xeon M Processor with 800 MHz System Bus Intel E7520 Chipset and Intel 6300ESB ICH Development Kit comprise an IA 32 based dual processor platform This platform serves as a reference for OEMs development platform This and other development kits from Intel provide a fully working product with range of performance options which can be modified or used immediately for product development 1 1 Related Documents Table 1 Related Documents Document Reference Title Source Document Number Inte E7520 Memory Controller Hub MCH Datasheet Intel E7520 Memory Controller Hub MCH Specification Update Intel Xeon Process
34. oard Ensure that a 550 W SSI EPV 12 V power supply is used to power up the CRB Refer to Section 5 1 Power Diagrams on page 25 for details on the SSI power supply interface on the CRB This platform supports DDR2 400 DIMMs ensure that the same speed DIMM is plugged in all slots of the platform Ensure that each processor has heat sinks attached before powering up the board Ensure that the heat sink is attached to the MCH and PXH before powering up the board Never attach a heat sink while the board is powered Use Table 4 to verify that all jumpers are in their default positions 1 Note The hard disk provided with the development kit is not pre loaded with any software Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 17 a Equipment Required for CRB Usage ntel 3 2 3 2 1 3 2 1 1 18 Driver and OS Requirements The required INF driver for the CRB supports the functionality of the Intel 6300ESB I O Controller and PXH The INF file will be included with Red Hat compatible drivers on the CD shipped with the kit The CRB supports these operating systems Microsoft Windows XP Windows Embedded XP 2000 Pro 2000 Server 2000 Advanced Server 2003 Standard Edition Red Hat Linux Advanced Server 2 1 Red Hat 8 0 on kernel 2 4 x Wind River VxWorks real time operating system QNX Neutrino real time operating system Customer operating systems
35. one CK409B Clock Synthesizer to generate the host differential pair clocks and the 100 MHz differential clock to the DB800 The DB800 then generates the 100 MHz differential pair clock for the PCI Express devices Figure 6 shows the CRB clock configuration Clock Block Diagram 14 318 MHz LGPUD BOLA BCLK EPUI BOLK y _BCLK IE BOK an DDRA CMDCLK 1 0 _ ri DDRA LM MCH BCLK MCH DDRB CMDCLK 1 0 DDRB MCH 66MHZ CLK PCI X ICH_USB_48MHZ_CLK z ze LPZ 14MHZ CLK Intel IcH_PX_PcLkott 0 gt G PCIX 6300ESB 2 ICH_33MHZ_CLK vO uU e ICH H166MHZ CLK Controller 2 x g T z Hub ET v j ICH_PX66MHZ_CLK i o J 5 2 2 9 2 T A r EE 5 a JE s 32 786 MHz 3 pui eae e SIO 33MHZ CLK l 100MHZ CLK LPC 14MHZ CLK p HI LAI LAI DB800 SRC 1 sana OT LAI_H1 EN tee ne EER CLK 29 499 MHz PCI 2 2 EXP_SLOT5_ 100MHZ_CLK iia e PCI Express Slot EXP SLOT6 o EE PCI Express Slot VIDEO 33MHZ CLK FWH 33MHZ CLK PORT80_33MHZ_CLK HE PCI SLOT6 33MHZ CLK DB800 B2937 03 26 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel 5 3 Figure 7 System Overview Platform Resets Figure 7 depicts the reset logic for the CRB The Intel 6300ESB I O Controller provides most of the reset following assert
36. or with 800 MHz System Bus Datasheet Intel 6300ESB I O Controller Datasheet Intel Xeon Processor Debug Port Design Guide Contact your Intel Sales Representative for access Extended Debug Port Design Guide for UP and DP platforms Schematics file Visit http ww w intel com platforms applied eiacomm reference configs htm for latest updates 1 2 Product Contents The Reference Board is shipped with the following components and features Two Intel Xeon processors 2 8 GHz and 3 2 GHz capable of 800 MT s e One 550 W SSI EPS12V power supply Two Heat sinks for the two processors Two pieces of DDR2 400 256 Mbytes Blank Hard drive CD with necessary drivers Red Hat 8 0 Compatible Driver Package Contents Red Hat Advanced Server 2 1 Compatible Driver Package Contents Windows Compatible Driver Package Contents ATI Rage Mobility M Graphics Accelerator Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 7 Product Overview i ntel 1 3 Products Feature List Processor Support Dual Intel Xeon Processors On board processor voltage regulators compatible with VRM EVRD 10 1 Design Guide Clocking CK409B clock synthesizer that generates all host clock and the PCI Express interface clock for the MCH PHY Layer DB800 generates the PCI Express differential pair clocks to the onboard PCI Express components and t
37. ovided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips CT Media Dialogic DM3 EtherExpress ETOX FlashFile i386 i486 i960 iCOMP InstantlP Intel Intel Centrino Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Create amp Share Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetBurst Intel NetMerge Intel NetStructure Intel Play Intel Play logo Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel Xeon Intel XScale IPLink Itanium MCS MMX MMX logo Optimizer logo OverDrive Paragon PC Dads PC Parents PDCharm Pentium Pentium Il Xeon Pentium IIl Xeon Performance at Your Command RemoteExpress SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside TokenExpress VoiceBrick VTune and Xircom are trademarks or
38. p from S4 and S5 States The power button is used to wake from S4 and S5 PCI PM Support This design holds the system reset signal low when in a sleep state The system supports the PCI PME signal and provides 3 3 V standby to the PCI and PCI Express slots This support allows any compliant PCI or PCI Express card to wake up the system from any sleep state except mechanical off The user and the operating system must configure the system carefully following the PCI power management interface specification because of the limited amount of power available on 3 3 V standby Platform Management The LM 93 monitors the majority of the system voltages The VID signals from the processors are also monitored by LM 93 AII voltage levels can be read via the SMBus Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual 15 n Platform Management ntel 2 5 1 2 6 16 Processor Thermal Management Each processor monitors its own core temperature and thermally manages itself when it reaches a certain temperature The system also uses the internal processor diode to monitor the die temperature The diode pins are routed to the diode input pins in the LM 93 The LM 93 can be programmed to force the processor fans to full speed operation when it senses the processor core temperature exceeding a specific value In addition the LM 93 has an on chip thermal monitor which allows it to monitor the incoming amb
39. tching Power must be switched from the normal 1 8 V rail to standby 1 8 V because the EPS 12V 550 W power supply does not directly supply a standby 1 8 V rail The sequence to enter Suspend to RAM is as follows The OS and BIOS prepare for S3 sleep state The OS sets the appropriate sleep bits in the I O controller The I O controller drives STPCLK to the processors The processors respond with a Stop Grant cycle passed over hub interface by MCH The I O controller indicates an S3 STR sleep mode to the MCH via Hub Interface A The MCH puts DDR memory into the self refresh mode The MCH drives DDR CMDCLK differential pairs and all DDR outputs low The MCH drives a completion message via Hub Interface A to the I O controller The I O controller turns off all voltage rails except Standby 5V from the main power supply by asserting the SLP S3 N signal When in the S3 state only the Standby 5 V rail is available from the power supply The board uses this standby source to generate 1 8 V standby rail to power the DIMMs The asserted SLP S3 N signal also controls the logic to switch the DIMM power source from main 1 8 V to standby 1 8 V S4 State This state is called Suspend to Disk From a hardware perspective it is equivalent to an S5 state The operating system is responsible for saving the system context in a special partition on the hard drive Although the system must power up and fully boot boot time to
40. verride J2H114 Override VRM disable if no CPUO installed 1 2 Override Open Normal Open Enable Video J4A1 Enable on Board video 1 2 Enable Open Disable 1 2 not populated ICH WDT Output J3J1 LED Control 1 2 Illuminate LED CR4J1 when EDT expires 1 2 J3J2 Reset Control 1 2 Reset board when WDT Expires 1 2 ICH VSWING Header J4G5 Access to ICH VSWING pin Do not Install Jumper Open ICH VREF Header J4G6 Access to ICH VREF pin Do not Install Jumper Open PCI SMBus Header J4H1 Access to PCI SMbus Do not install Jumper 1 PCI SMBDAT 2 Ground 3 PCI SMBCLK Open DDR SMBus Header J4H3 Access to DDR SMbus Do not install Jumper 1 DIMM SMBDAT 2 Ground 3 DIMM SMBCLK Open 22 Intel Xeon Processor Intel E7520 Chipset Intel 6300ESB ICH Development Kit User s Manual intel Table 4 Jumper Settings Sheet 2 of 3 Jumpers and Headers Default Jumper Name Ref Des Description Settings Position BSELO BSEL1 SPEED 1 2 1 2 Normal ESEN Beh BSELY dat 253 2 3 RSVD BSELO 1 2 V Host Clock Jumpers BSELO J4J3 2 3 Open 133 MHz BSEL1 1 2 Open Open 167 MHz Open 1 2 200 MHz Inject SMI Signal SMI Inject J4H5 Open m Do Not Install Jumper P Inject FORCEPRO Signal FORCEPRO inject J4H6 us is seriis Open Inject STPCLK Signal
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