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Intel 440GX User's Manual

1. 2 29 Motherboard Model WE 4 5 2 29 Motherboard Model MA A 14 0 4 DIMMS 2 29 Motherboard Model MA 12 11 9 018 MA B 14 13 10 4 DIMMs 2 30 Slot 3 2 GND amp Power Pin Definition 3 4 Processor Frequency 8 3 8 82443GX Connectivity 3 10 SLAPPING Optio Ms m 3 13 SDRAM Connectivity 3 14 PIIXAE Connectivity tette e tente ie rh 3 16 IDE Series 3 20 PIIXAE PWR amp GND eei tet tente ete ntn nnt inn 3 22 Non PIIX4E PCI Signals 3 23 Non PIIX4E ISA Signals ottenere 3 23 3 24 Flash Vpp 3 27 Simenniseum 5 1 Retention Mechanism Retention Mechanism Module Attach Sink SUppor sitter tentat btt 5 1 GTL Bus Slot 1 Terminator Cards 5 1 Voltage Regulator Modules 5 2 Voltage Regulator Control Silicon Vendors 5 2 C
2. GTL Quadrant Quadrant Pin 1 Corner 12 34 5 6 011 121314 15161718 19 20 21 22 23 000000000000000 000000000000000 000000000000000 J loooooo L looooo 552222 deseos 22223 000000 Quadrant 6 R looooo 00000 u looooo 000000 wj ooooo 000000 Y 0000000000 ABJOC OO 00 eoo0o0o0 000 0000 00000 aclooooo ADJO OOO 0000000 00000000 SDRAM Quadrant v001 Inte 440GX AGPset Design Guide 24 Motherboard Layout and Routing Guidelines intel b Figure 2 2 and Figure 2 3 show the proposed component placement for a single processor for both ATX and NLX form factor designs ATX Form Factor 1 The ATX placement and layout below is recommended for single UP Intel Pentium II processor Intel 440GX AGPset system design The example placement below shows 4 PCI slots 2 ISA slots 4 DIMM sockets and one AGP connector For an ATX form factor design the AGP compliant graphics
3. 2 30 2 9 4 PCI Bus Routing Guidelines 2 30 2 9 5 Decoupling Guidelines Intel 440GX AGPset Platform 2 31 2 9 6 Intel 440GX AGPset Clock Layout Recommendations 2 32 2 9 6 1 Clock Routing Spacing 2 32 2 9 6 2 System Bus Clock 2 32 219 6 3 PCI Clock iit ener teni 2 33 2 9 6 4 SDRAM Clock 2 33 2 9 6 5 AGP Clock Layout 2 34 Design Ghecklisb n eit A o ee te ee e a 3 1 3 1 OVeIVIQW izda 3 1 3 2 Pull up Pull down Resistor 5 3 1 3 3 Intel Pentium II Processor 3 2 3 3 1 intel Pentium Processor 3 2 3 3 2 Intel Pentium II Processor 8 3 5 3 3 3 Intel Pentium II Processor 8 8 3 5 3 3 4 Uni Processor UP Slot 1 3 7 3 3 5 Dual Processor DP Slot 1 3 7 3 3 6 Slot 1 Decoupling Capacitors 3 7 3 3 7 Voltage Regulator Module VRM 8 2 3 7 3 4 Intel 440GX AGPset A A eim du 3 8 3 4 44 CK100 100 MHz Clock
4. Processor Pin Pin Connection UP Connected to CK100 10K ohm series resistor to MAB 12 200 ohm pull up to 3 3V at 100 66 CK100 DP connect between CPUs Logic may be provided to detect a frequency match fre Leave as NC connect A 31 3 to 82443GX 31 3 A20M 150 ohm 330 ohm pull up to 2 5V ADS UP Connect to 82443GX DP Connect CPUs and 82443GX AERR Leave as NC AP 1 0 Leave as NC BCLK Connect to CK100 22 ohm series resistor BERR Leave as NC BINIT Leave as NC BNR UP Connect to 82443GX DP Connect CPUs and 82443GX BP 3 2 Leave as NC BPM 1 0 Leave as NC BPRI UP Connect to 82443GX DP Connect CPUs and 82443GX BREQ 1 0 4 UP Connect BREQO to 82443GX Leave BREQ1 as NC DP Connect BREQO of each CPU to BREQ1 of the other Connect one of these to 82443GX D 63 0 UP Connect to 82443GX DP Connect CPUs and 82443GX Inte 440GX AGPset Design Guide 3 2 intel Design Checklist Table 3 1 Slot Connectivity Sheet 2 of 3 Processor Pin Pin Connection DBSY UP Connect to 82443GX DP Connect CPUs 82443GX DEFER UP Connect to 82443GX DP Connect CPUs and 82443GX DEP 7 0 No connect DRDY UP Connect to 82443GX DP Connect CPUs 82443GX EMI Connect to GND FERRE UP Connect to PIIX4E 220 ohm pull up to 2 5V DP Connect CPUs and PIIX4E 220 ohm pull
5. 2 31 82443GX 2 31 Clock Trace Spacing 5 2 32 AGP Clock EayoUut eode diae tert 2 34 Pull up Resistor a 3 2 8 DCLKWR 3 9 Current Solution With Existing FET Switches 3 15 Series Resistor Placement for Primary IDE Connectors 3 21 Dual Footprint Flash Layouts 3 25 nterfacing Intel s Flash with PIIX4E in Desktop 3 26 Interfacing Intel s Flash with in Desktop 3 28 PWRGOOD amp PWROK 10 3 29 LAI Probe Input 4 3 440GX AGPset Design Guide Tables viii 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 3 1 3 2 3 4 3 5 3 7 3 8 3 10 3 11 3 12 3 13 5 1 5 2 5 3 5 4 5 6 5 7 Recommended Trace Lengths for Single Processor Design 2 7 Recommended Trace Lengths for Dual Processor Designs2 2 8 SET Trace Length Requirements 2 9 Recommended 100 MHz System Flight Time Specs 2 13 System Timing Requirements for Validating Setup Hold W
6. 5 3 5 3 Other Processor Components 5 4 5 3 1 Slot 1 5 4 53 2 Mechanical Support iine tt e e tret eae 5 4 5 3 9 HIG AL SINKS uccisi tet doadne 5 4 5 3 4 Heat sink attachment Rivscrews and associated tools 5 4 5 3 5 Thermal interface materials 5 4 Intel 440GX AGPset Platform Reference A 1 Inte 440GX AGPset Design Guide intel Figures 2 1 2 2 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 12 2 13 2 14 2 15 2 17 2 19 Intel Pentium II Processor Intel 440GX AGPset System Block 1 4 Major Signal Sections 82443GX 2 1 Example ATX Placement for a UP Pentium II processor Intel 440GX AGPset Design 2 2 Example NLX Placement for a UP Intel Pentium II processor Intel 440GX DO 2 3 Four Layer Board 2 4 Six Layer Board Stack up With 4 Signal Planes and 2 Power Planes 2 4 Six Layer Board Stack up With Signal Planes and 3 Power Planes 25 Recommended Topology for Single Processor Design 2 6 Solution Space for Single Processor Design Based on Results of Parametric 2 7 Recommended Topology for Dual Processor
7. 3 8 3 4 2 CKBF SDRAM 1 to 18 Clock 3 9 3 43 and DCLKWR Connection seen 3 9 3 5 82443GX Host Bridge 3 10 3 5 1 82443GX 3 10 3 5 2 82443GX GTL Bus Interface 3 12 3 5 3 82443GX PCI 3 12 3 5 4 82443GX AGP Interface 3 13 3 6 Intel 440GX AGPset Memory Interface 3 14 3 6 1 SDRAM 5 3 14 3 6 2 DIMM Solution With FET Switches 3 15 3 6 3 Registered SDRAM 3 15 Intel 440GX AGPset Design Guide 3 7 8237 1EB PIIX4E ette uite Mi eed ele 3 16 3 7 4 PIIX4E 3 16 3 7 2 IDE Routing 5 3 20 3 7 2 1 Gabling 1i eret De t d 3 20 3 7 2 2 Motherboard 3 20 3 7 3 PIIX4E Power And Ground Pins 3 22 3 8 PCI Bus Signals iia lr Doi 3 22 3 9 ISA SONS 2 A cbe tire reus 3 23 3 10 ISA and X Bus Signals imise aii dai 3 23 3 11 USB Interface Eee dee pia edis 3 24 3 12 IDE Interface cocinada een dt etes 3 24 3 13 gt Flasti6sigri e Ie dette itor es 3 25 3 13 1 Dual Footprint Flash Design 3 25 3 13 2 Flash Design Consideratio
8. 82443GX 4 2 9 5 Decoupling Guidelines Intel 440GX AGPset Platform Decoupling caps should be placed at the corners of the 443GX BGA Package A minimum of four 0 1uF and four 0 01 uF are recommended The system bus AGP PCI and DRAM interface can break out from the BGA package on all four sides Additional caps will also help reduce EMI and cross talk Figure 2 29 82443GX Decoupling 0 1uF r3 r0 1uF 0 01uF Co ra 0 01uF 82443GX Host Bridge Controller 492 BGA 0 1uF CoO E 0 1uF 0 01uF RIDE v006 Note There are other discrete components for Vyr Ref Voltages that must be also considered when routing around the 82443GX Inte 440GX AGPset Design Guide 2 31 Motherboard Layout and Routing Guidelines intel 5 2 9 6 2 9 6 1 Intel 440GX AGPset Clock Layout Recommendations Clock Routing Spacing A Intel Pentium II processor Intel 440GX AGPset platform requires a clock synthesizer for supplying 100 MHz system bus clocks PCI clocks APIC clocks and 14 MHz clocks These clocks are supplied by a CK100 clock synthesizer as defined by the CK97 clock driver specification The 100 MHz SDRAM DIMM clocks are generated from an I2C controlled clock buffer CKBF which produces 18 DIMM clock outputs from a single DCLK output provided by the 82443GX To minimize the impact of crosstalk a minimum of 0 014 spacing should be maintained between the clock traces an
9. Inte 440GX AGPset Design Guide 3 34 Design Checklist 3 18 4 On LAN WOL Header A 3 pin WOL header interconnects the NIC and motherboard and requires a 5VSB to pinl The WOL supports the Wakeup pulse allowing it to turn on the system via a signal pulse The LID input on the requires a 16ms debounce signal The MP Wakeup signal to the PIIX4E LID pin requires a 5V to 3V translation NOTE The LID pin will be configured as an active high signal through BIOS for this specific implementation If other logic is used for the 5V to 3V translation make sure BIOS configures the LID pin appropriately Maximum current provided by the power supply should be no less than 600mA BIOS support for boot from LAN BIOS Boot Spec if required See Wake on LAN Leader Recommendations order number 712940 3 19 Software BIOS See the Intel Pentium Pro Processor BIOS Writers Guide for details regarding the following responsibilities of the BIOS The Intel Pentium II processor L2 cache must be initialized and enabled by the BIOS The BIOS must load the BIOS Update to the Intel Pentium II processor as early as possible in the POST during system boot up The BIOS update signature mechanism should be used to validate that the BIOS Update has been accepted by the processor It is recommended that the BIOS implement the minimum update API interface to allow the BIOS Update stored in BIOS to be updated Of the two Intel
10. 4 component Interrupts USB DMA power management X Bus and GPIO interfaces Also shown is the CLOCKRUN pull down and the external logic needed to handle a power loss condition IOAPIC Component 19 This sheet shows the connection for the IOAPIC controller to the various 4 and processor interrupts Inte 440GX AGPset Design Guide Intel 440GX AGPset Platform Reference Design Ultra I O Component 20 This page shows the Ultra I O component The RTC may optionally be used An Infra Red Header Port is also optional AGP Connector 21 This page shows the AGP connector In this design AGP INTA and INTB are connected to the PCI INTA and INTB through a buffer driver The interrupt signals are open collector and pulled up to Vcc3 3 PCI Connectors 22 23 These pages show the PCI connectors In this design four PCI connectors are used AD 26 27 29 and 31 are the preferred lines for the PCI slot IDSELs ISA Connectors 24 This page shows the ISA connectors PCI IDE Connectors 25 This page shows the IDE Connectors No special logic is required to support Ultra DMA 33 hard drives USB Headers 26 This page shows the USB Headers Note the voltage divider on the open circuit signals provides logic level transitions for the PIIX4E Note the placement requirements for the capacitors and series resistors at the bottom left Flash BIOS Component 27 This page shows the 28F002BC T Flash BIOS component which provides 12
11. sse 3 38 3 24 X Applications and Add in Hardware see 3 38 3 24 1 Design Consideration sss 3 38 Debug Recommendations 4 1 4 1 Slot Test Tod Sicario irlanda 4 1 4 2 Debug Simulation 4 1 4 2 1 Logic Analyzer Interface 1 4 1 4 2 2 In Target Probe 4 1 4 2 3 Bus Functional Model BFM see 4 2 4 2 4 WO Buffer ennemis 4 2 4 2 5 JFEOTHERM MOdel 5 indeed 4 2 Intel 440GX AGPset Design Guide vi 4 3 Debug Features eaei a aE N N eA EA 4 2 4 3 1 Intel Pentium II Processor LAI Issue 4 2 4 3 2 Debug Logic 4 4 4 3 2 1 Debug Considerations 4 5 4 3 3 Debug Layout 4 5 4 3 3 1 Design Considerations 4 5 4 3 4 Debug 5 4 5 Third Party Vendor Information 5 1 5 1 O cott Ste 5 1 5 1 1 Voltage Regulator Modules 5 2 5 1 2 Voltage Regulator Control 5 5 2 52 Intel 440GX AGPset AAA A nate ee 5 3 5 241 Olock Drivers cuides 5 3 5 2 2 Power Management Components 5 3 5 2 3 FET Switches 4 DIMM FET
12. 10 516 Connected to ISA slots 1K ohm pull up to VCC IOR Connected to ISA slots Ultra I O LM79 8 2K ohm pull up to VCC lOW Connected to ISA slots Ultra I O LM79 8 2K ohm pull up to VCC IRDY 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 82443GX PCI slots and IRQO GPO14 No connect DP Connected to INTIN2 of IOAPIC IRQ8 8 2K ohm pull up to 3VSB DP Connected to IOAPIC through tri state buffer IRQ 1 3 7 8 2K ohm pull up to VCC Connected to ISA slots and Ultra I O DP Connected to IOAPIC IRQ 15 14 Connected to ISA slots Ultra I O IDE 8 2K ohm pull up to VCC DP Connected to IOAPIC IRQ 9 12 Connected to ISA slots Ultra I O 8 2K ohm pull up to VCC DP Connected to IOAPIC KBCCS GPO26 No Connect LA 17 23 Connected to ISA slots 8 2K ohm pull up to VCC LID GPI10 8 2K ohm pull down if LID is not used Connect to wake on LAN Header if used MCCS No connect MEMCS16 Connected to ISA slots 1K ohm pull up to VCC Connected to ISA slots Flash 8 2K ohm pull up to VCC MEMW DP Connected to IOAPIC NMI Part of CPU bus frequency circuit 2 7K ohm pull up to 3V OCx Driven by USB overcurrent detection voltage divider OSC Connect to CK100 PAR Connect to PCI slots and 82443GX PCICLK Connect to CK100 PCIRST Connect to AGP PCI and 82443GX PCI_STP GPO18 No connect or connected to CK100 with 10K ohm pull up to 3VSB PCS1 Connecte
13. GND layer GND plane 3 3v VCC layer 3 3v power plane Adding Additional Decoupling Capacitor Another way to provide a low inductance path for return currents is to provide additional decoupling capacitors next to signal vias It is not possible to route all the MD lines on a single layer As a result some of the MD lines will transition between signal layers through vias The return currents associated with these signals also require a low inductance path between Vcc and ground This low inductance path is provided by decoupling capacitors between Vcc and ground These decoupling capacitors should be placed as close as possible to the signal vias Intel 440GX AGPset Design Guide 2 23 Motherboard Layout and Routing Guidelines H Figure 2 18 Matching the Reference Planes and Adding Decoupling Capacitor 2 9 1 3 2 9 2 MDx line with GND reference plane BX BGA Substrate Portary Espral Lays Decoupling cap PAR Primary Signal Layer Ground Plane Power Plane Secondary Signal Layer MDx line with Vcc3 reference plane Trace Width vs Trace Spacing To minimize the crosstalk a 1 2 trace width vs trace spacing routing e g 6 mils on 9 mils or 5 mils on 10 mils should be used for all memory interface signals Memory Layout amp Routing Guidelines Figure 2 19 4 DIMMs Single or Double Sided 2 24 CS_A 7 6 CS_B 7 6 CS_A 5 4 CS_B 5 4 CS_A 3 2 CS_B 3
14. cu 5 mils PREPREG Z 600hms Secondary Signal Layer 1 2 oz cu Total board thickness 62 6 The top and bottom routing layers specify 1 2 oz cu However by the time the board is plated the traces will end about 1 oz cu Check with your fabrication vendor on the exact value and insure that any signal simulation accounts for this value A thicker core may help reduce board warpage issues For a dual processor Intel 440GX AGPset design a 6 layer stack up is recommended Two examples are shown below Figure 2 5 has 4 signal plane layers and 2 power plane layers Figure 2 6 shows 3 signal plane layers and 3 power plane layers The second option makes it easier to accommodate all of the power planes required in a Intel 440GX AGPset design If a 6 layer stack up is used then it is recommended to route most of the GTL bus signals on the inner layers The primary and secondary signal layer can be used for GTL signals where needed Routes on the two inner layers should be orthogonal to reduce crosstalk between the layers Figure 2 5 Six Layer Board Stack up With 4 Signal Planes and 2 Power Planes Z 66ohms OHHH Primary Signal Layer 1 2 oz cu 6 mils PREPREG nmm Ground Plane 1 oz cu 18 mils CORE z 78ohms Inner Layer 1 1 oz 6 mils PREPREG Inner Layer 2 1 oz cu 18 mils CORE Power Plane 1 oz cu 6 mils PREPREG Z 66ohms Secondary Signal Layer 1 2 oz
15. 0 15 0 NA Clock chip 440GX 7 3 1 0 15 0 NA SDRAM Clock Layout Series Termination No series termination is required for the SDRAM clocks between the CKBF and the DIMMs For DCLKO between 82443GX and two termination resistors are required A 22 Ohm series resistor located at the driver and a 47 Ohm series resistor located at the receiver Layout guidelines Net Trace Length Min Max Cap 440GX CKBF DLKO NA 1 0 10 0 NA CKBF DIMM SDRAM Clocks A 1 0 3 0 NA CKBF 82443GX DCLKWR A 2 5 3 5 5 5 20pF A single clock output from CKBF is used to drive DCLKWR at the 82443GX The single clock net should be T d as close as possible to the 82443GX An additional capacitive load of 20pF is also required The capacitor should also be located as close to the 82443GX as possible The 82443GX does not have an internal connection for pin AB22 Existing designs connected DCLKWR amp AB22 nets on the motherboard Since the 82443GX does not have an internal connection for pin AB22 it will cause a slightly reduced load capacitance on the net To avoid additional clock skew on existing designs a discrete capacitor larger than the 20pF capacitor recommended may be required 2 33 Motherboard Layout and Routing Guidelines intel 5 2 9 6 5 AGP Clock Layout Series Termination 22 Ohm series termination should be used for the AGP clocks Layout g
16. 2 7K ohm pull up to 5V Connected to PCI bus SRAS B A Each connected to up to 2 DIMMs ST 2 0 Connected to AGP connector STOP 2 7K ohm pull up to 5V Connected to PCI bus SUSTAT 10K ohm pull up to 3 3V Connect to PIIX4E for POS implementation TESTIN 8 2K ohm pull up to 3 3V which may be removed if validation permits Inte 440GX AGPset Design Guide intel Design Checklist Table 3 4 82443GX Connectivity Sheet 3 of 3 SIGNAL CONNECTION TRDY 2 7K ohm pull up to 5V Connected to PCI bus VTTA VTTB GTL threshold voltage for early clamps WE B Al Each connected to up to 2 DIMMs WSC UP Leave as a NC DP Connected to IOAPIC No pull up resistor is needed GTLREF x pins are driven from independent voltage dividers which set the GTLREFx pins to VTT 2 3 using a 75 ohm and 150 ohm resistor ratio The 82443GX GTL_REF B A pins should be adequately decoupled The 82443GX component is a 3 3V component All pins labeled as VDD should be connected to VCC 3 VDD_AGP pins have been changed to VDD pins The VSSA pin has been changed to VSS The 82443GX REFVCCS pin can be connected to the same power sequencing circuit used by the PIIX4E See the PIIX4E section for further information on sharing this circuit The 82443GX AGPREF pin is required to be 0 4 of VCC this can be performed by a voltage divider The 82443GX GX_PWROK can be connected to the PUX4E PWROK pin The 22 ohm serie
17. A Note This section describes the DP Intel 440GX AGPset 4 DIMM Reference Design Schematics The description of each schematic page is named by the logic block shown on that page The numbers after the schematic page name list the page number of the dual processor design Cover Sheet 1 The Cover Sheet shows the Schematic page titles page numbers and disclaimers Block Diagram 2 This page shows a block diagram overview of the Intel Pentium II Intel 440GX AGPset system design Also included is a device table listing every major component in the design its reference designator and location Intel Pentium II Slot 1 processor connector part 1 3 and 5 This page shows the first part of the Slot 1 connector up to the key SLP connection comes directly from the PITX4E Intel recommends placing 0 ohm resistors on the EMI signals A thermal sensor the MAX 1617 ME which connects to an internal processor diode has been included to monitor processor temperature Intel Pentium Slot 1 processor connector part 2 4 and 6 This page shows the remaining part Slot Iconnector Also shown are the optional connections for overriding the VID pins from the processor Clock Synthesizer and ITP connector 7 This page shows the new clock synthesizer component the CK100 plus recommended decoupling The clock synthesizer components must meet all of the system bus PCI and other system clock requirements Several vendors offer components
18. CKE1 Dane 2D6 206 The capacitors must be placed close to the 2D7 207 2D7 2D8 KE node where the clock signals are T ed AI CKE0 A 2D8 208 The capacitor values are shown AAA v007 NOTES 1 The above circuitry only applies to unbuffer DIMMS GCKE needs to be disabled for register DIMMS 2 Pin AB22 has been changed to a no connect NC The 82443GX does not have an internal connection for pin AB22 Existing designs connected DCLKWR amp AB22 nets on the motherboard Since the 82443GX does not have an internal connection for pin AB22 it will cause a slightly reduced load capacitance on the net To avoid additional clock skew on existing designs a discrete capacitor larger than the 20pF capacitor recommended may be required Intef 440GX AGPset Design Guide 3 9 X Design Checklist intel 3 5 82443GX Host Bridge 3 5 1 82443GX Interface Table 3 4 82443GX Connectivity Sheet 1 of 3 SIGNAL CONNECTION AD 31 0 Connected to PCI bus ADS Connected to CPUs AGPREF Connected to be 0 4 of Can be performed by a voltage divider BNR Connected to CPUs BPRI Connected to CPUs BREQO Connected to CPUs GXPWROK Connected to PIIX4E PWROK pin C BE 3 0 Connected to PCI bus FENA 4DIMM Design Connected to FET switches as an enable pin GCKE needs to be disabled for register DIMMS GCKE GCKE is a NC unless connected to SN74ALVCH16374 16 bit D flip flop See reference schematic
19. DMI 2 0 Service Provider Software Development Kit SDK provides a DMI Service Provider and binaries that support DMI Version 2 00 This kit is available at http developer intel com ial WfM tools sdk index htm Intel s LANDesk Client Manager product includes the Service Provider and component instrumentation Information regarding this product can be found at http developer intel com ial WfM tools ldcm index htm The WfM Baseline Instrumentation specification identifies specific DMI standard groups including event generation groups that must be instrumented for a Baseline compliant platform This reference design provides support for the SMBIOS revision 2 0 specification which along with appropriate component instrumentation will supply some of the required data in the specified DMI 2 0 groups This reference design also provides additional optional instrumentation hardware support with the LM79 and Maxim MAX1617 components Remote Service Boot The WfM Baseline specifies the protocols by which a client requests and downloads an executable image from a server and the minimum requirements on the client execution environment when the downloaded image is executed The Baseline specification includes a set of APIs for the particular network controller used The code supporting the Preboot eXecution Environment PXE and the network controller is provided on the EtherExpress PRO 100 WFM adapters Option ROM Two implementation options are
20. Jack Hou 886 2 268 3466 x376 Molex Jim McGrath 708 527 4037 Table 5 2 Retention Mechanism Retention Mechanism Module Attach Sink Suppor Supplier Contact Phone AAVID Thermal Products Inc Chapman 603 223 1721 AMP Incorporated Mike Mullen 717 592 2352 Foxconn USA Julia Jiang 408 749 1228 x232 Hon Hai Precision Ind Co LTD Taiwan Jack Hou 886 2 268 3466 x376 InteSys Technologies Inc Steve Daniggelis 602 497 3178 Molex Jim McGrath 708 527 4037 Table 5 3 GTL Bus Slot 1 Terminator Cards Supplier Contact Phone AMP Incorporated Ron Mcdowell 717 592 3468 Inte 440GX AGPset Design Guide 5 1 5 1 2 Voltage Regulator Modules Third Party Vendor Information The following vendors are developing DC DC converter modules for Intel Pentium II processor voltage and current requirements per the VRM 8 2 DC DC Converter Design Guidelines Table 5 4 Voltage Regulator Modules Supplier Intel CNDA Contact Phone Celestica Dariusz Basarab 416 448 5841 Corsair Microsystems John Beekley 408 559 1777 Delta Electronics North America Delta Products Corp Colin Weng Maurice Lee 886 2 7164822 x233 Taiwan 510 770 0660 x111 LinFinity Andrew Stewart 714 372 8383 Raytheon Hubert Engle Brechten 415 962 7982 semtech Alan Moore 805 498 2111 x291 European CNDA VXI Electronics Jo
21. PITX4E directly to 3VSB voltage With the exception of all unused GPIx inputs on the PITX4E should be tied high through pull up resistors 8 2K ohm 10K ohm to a power plane Tying directly to the power plane is also acceptable if not used should be tied to 3VSB through an 8 2K ohm resistor If GPI is left floating this will violate ACPI compliance by preventing the GPI STS bit register base bit 9 from functioning properly Note that GPI1 is tied to the resume well To maintain RTC accuracy the external capacitor values for the RTC crystal circuit should be chosen to provide the manufacturer s specified load capacitance for the crystal when combined with the parasitic capacitance of the trace socket if used and package which can vary from OpF to 8pF When choosing the capacitors the following equation can be used Specified Crystal Load Cap1 Cap2 Cap1 Cap2 parasitic capacitance The reference board uses 18pF capacitors and an Ecliptek EC38T crystal which has a specified load 12 5pF When the PIIXA PIIXAE internal RTC is used ensure that the VBAT pin of the SMC Ultra IO device FDC37932FR is connected to ground through a pull down resistor between and 0 ohms Consult your IO device vendor for implementation guidelines for this or other IO devices Recommendations for New Board Designs to minimize ESD events that may cause loss of CMOS contents Provide a luF X5R dielectr
22. Signals Dual termination 56 ohm to Vtt of the GTL bus is required if the trace length restrictions of a SET single ended termination environment cannot be met THERMTRIP must be pulled up to Vcc 5 150 ohm to 10K ohm if used by system logic The signal may be wire OR ed and does not require an external gate It may be left as NC if it is not used See the Debug Recommendations for further information that may affect the resistor values The FERR output must be pulled up to Vcc2 5 150 ohm to 10K ohm and connected to the PIIXAE The reference schematics uses 220 ohms See the Debug Recommendations for further information that may affect these resistor values PICD 1 0 must have 150 ohm pull ups to Vcc2 5 even if an I O APIC is not being used See the Debug Recommendations for further information that may affect these resistor values All CMOS inputs should be pulled up to Vcc2 5 150 ohm to 10K ohm See the Debug Recommendations for further information that may affect these resistor values Be sure the Slot 1 inputs are not being driven by 3 3V or 5V logic Logic translation of 3 3V or 5V signals may be accomplished by using open drain drivers pulled up to Vcc2 5 The PWRGOOD input should be driven to the appropriate level from the active high AND of the Power Good signals from the 5V 3 3V and supplies The output of any logic used to drive PWRGOOD should be 5 level to the processor No sh
23. The specifications define requirements for Intel Pentium I processor based systems with Intel 440GX AGPset Intel tests some clock devices to verify the ability of the industry to meet the Intel specification there is no formal component qualification Clock Driver Vendors Supplier Intel CNDA Phone Contact Capella Microsystems Brian Kuo 408 260 3400 Cypress John Wunner 206 821 9202 x325 ICS Raju Shah 408 925 9493 IC Works Sales 408 922 0202 Integrated Device Technology Val Liva 408 654 6479 IMI Elie Ayache 408 263 6300 x235 Motorola Carlos Obregon 602 732 3248 Texas Instruments Murali Kadiyata 972 480 4834 Power Management Components The following vendors are developing hardware monitors LM79 75 and thermal sensors MAXIM1617 for the Intel 440GX AGPset reference designs with a Intel Pentium II processor The thermal sensors will be used to monitor processor and board temperature In addition the hardware monitor will be used to monitor voltage regulation and fan RPM Power Management Component Vendors Supplier Intel CNDA Phone Contact 503 968 1285 408 737 7600 National Semiconductor MAXIM Jorge E Moguel Bruce Moore FET Switches 4 DIMM FET Design Intel is recommending that OEMs contact the particular vendor for pricing and availability of sample and production units FET Switch Vendors Supplier Intel C
24. The system reset button has typically been connected indirectly to the PWROK input of the PIIX4 PIIXAE This technique will not reset the suspend well logic which includes the SMBus Host and Slave controllers To reset the hardware in the suspend well the reset button should be connected to the RSMRST input of the PIIXA4 PIIXAE Assertion of RSMRST via a reset button will result in a complete system reset RSMRST assertion will cause SUS A C to assert which results in the deassertion of PWROK if SUS A C controls the power supply PS ON control signal The deassertion of PWROK will cause the PIIX4 PITX4E to assert PCIRST RSTDRV and CPURST In the reference schematics 3VSB is generated from 5VSB on the power supply connector The Zener diode MMBZ5226BL acts as a voltage regulator which clamps the standby voltage at 3 3V The 0 1uF and 10uF caps are for noise decoupling and the 56 ohm series resistor is used for current limiting This Zener diode and 56 ohm resistor should be validated to make sure the standby voltage is clamped to 3 3V The series resistor may need to be tuned based on the standby current requirements of the board As the 3VSB is required to supply more current the voltage will drop slightly Also note that the Zener being used requires approximately 20mA to sustain 3 3V however a different Zener diode requiring less current may be used Refer to the schematics for implementation details RI can be connected to the modem
25. and North American Philips Corporation Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1999 Third party brands and names are the property of their respective owners Intel 440GX AGPset Design Guide intel Contents 1 1 1 1 1 About This Design 1 1 1 2 Referentes 1 2 1 3 Intel Pentium II Processor Intel 440GX AGPset Overview 1 3 1 3 1 Intel Pentium II 1 3 1 3 2 Intel 440GX 1 4 1 3 2 1 System Bus 1 5 1 3 2 2 DRAM Interface 1 5 1 3 2 3 Accelerated Graphics Port 1 5 1 3 24 PCI Interface oo cece 1 6 1 3 2 5 System 1 6 1 3 3 PCl to ISA IDE Xcelerator 1 6 1 3 3 1 Instrumentation oon il tetera dio 1 7 1 3 3 2 Remote Service 1 7 1 3 3 3 Remote Wake Up sese 1 8 1 3 3 4 Power Management sse 1 8 1 4 Design Recommendations esee nennen 1 8 1
26. at the end of the cable If a second drive is placed on the same cable it should be placed on the next closest connector to the end of the cable 6 from the end of the cable Grounding Provide a direct low impedance chassis path between the motherboard ground and hard disk drives Motherboard 1 2 PITX4E Placement The should be placed as close as possible to the ATA connector s Resistor Location When the distance between the PILX4E and the ATA connectors exceeds 4 inches the series termination resistors should be placed within 1 inch of the PITX4E Designs that place the PIIXAE within 4 inches of the ATA connectors can place the series resistors anywhere along the trace PC97 requirement Support Cable Select for master slave configuration is a system design requirement for Microsoft PC97 CSEL signal needs to be ground at host side by using a 470 ohm pull down resistor for each ATA connector Capacitance The capacitance of each pin of the IDE connector on the host should be below 25 pF when the cables are disconnected from the host Series Termination The following resistor values are the current recommendations Table 3 8 IDE Series Termination Inte 440GX AGPset Design Guide Signal Resistor Signal Resistor PDD 15 0 33 ohm SDD 15 0 33 ohm PDA 2 0 33 ohm SDA 2 0 33 ohm PDIOR 33 ohm SDIOR 33 ohm PDIOW 33 ohm SDIOW 33 ohm PDDREQ
27. control signals less than 8 5 inches can be routed 1 1 while control signals greater than 8 5 inches should be routed 1 2 Table 2 16 Control Signal Line Length Recommendations Width Space Board Trace Line Length Pull up Stub Length 1 1 Motherboard ratte 1 0 in lt line length lt 8 5 in lt 0 5 in Strobes lt 0 1in 1 2 Motherboard roe 1 0 in lt line length lt 12 5 lt 0 5 Strobes lt 0 1 1 2 1 4 to Strobe Motherboard Clock Inte 440GX AGPset Design Guide 2 21 Motherboard Layout and Routing Guidelines intel o 2 9 2 9 1 Note Some of the control signals require pull up resistors to be installed on the motherboard AGP signals must be pulled up to using 8 2K to 10K ohm pull up resistors refer to Section 3 5 1 82443GX Interface on page 3 10 Pull up resistors should be discrete resistors as resistor packs will need longer stub lengths and may break timing The stub to these pull up resistors needs to be controlled The maximum stub length on a strobe trace is lt 0 1 inch The maximum stub trace length on all other traces is lt 0 5 inch Under certain layouts crosstalk and ground bounce can be observed on the AD_STB signals of the AGP interface Although Intel has not observed system failures due to this issue we have improved noise margin by enhancing the AGP buffers on the 82443GX For new designs additional margin can be obtained by following th
28. cu Total board thickness 62 4 Inte 440GX AGPset Design Guide intel Motherboard Layout and Routing Guidelines Figure 2 6 Six Layer Board Stack up With 3 Signal Planes and 3 Power Planes 2 3 z 60ohms CoCr Primary Signal Layer 1 2 oz cu PREPREG Ground Plane 1 oz cu Z 59onms Inner Layer 1 1 oz cu 8 mils PREPREG Power Plane 1 1 oz cu 18 mils CORE Power Plane 2 1 oz cu mils PREPREG 2 60 66000 Secondary Signal Layer 1 2 oz Total board thickness 62 4 Additional guidelines on board buildup placement and layout include For a 4 layer single processor design double ended termination is recommended for GTL signals One termination resistor is present on the processor substrate and the other termination resistor is needed on the motherboard It may be possible to use single ended termination if the trace lengths can tightly be controlled to 1 5 minimum and 4 0 maximum e For a 6 layer dual processor design no termination is required on the motherboard for GTL signals as each end of the GTL bus is terminated on each processor If a single Slot 1 is populated in a DP design the second Slot 1 must be populated with a termination card The termination resistors on the GTL bus should be 56 ohms The board impedance Z should be between 50 and 80 ohms 65 ohms 20 FR 4 material should be used for the board fabrication The gr
29. defined update APIs it is recommended that the full real mode INT15h interface be implemented An API calling utility and test tool is available for this interface Contact your local Intel Field Sales representative for a copy Before starting a Flash update routine use the MTRRs to disable caching or only allow WT mode This prevents a WBINVD instruction from writing stale data to the Flash memory MTRR 6 amp 7 must be left unprogrammed and are reserved for Operating System use 3 19 1 USB and Multi processor BIOS Initialize the USB function properly in the PITX4E component if USB connectors are provided Enable USB interrupt routing to one of the IRQ inputs This should be set to Level Trigger Mode When running Virtual Wire mode configure this through the I O APIC See page 3 10 of the MultiProcessor Specification 1 4 DP systems must construct an MPS table see the MultiProcessor Specification 1 4 for details Inte 440GX AGPset Design Guide 3 35 Design Checklist intel 3 19 2 Design Considerations For UP systems to support both the current Intel Pentium processor and future processors it is highly recommended that storage space for two or more BIOS Updates be provided This will allow manufacturing flexibility to install either processor the BIOS should detect the processor and load the correct BIOS Update For DP systems it is recommended that storage for two or more BIOS Updates be reserved fo
30. device can be either on the motherboard device down option or on an AGP connector up option The trace length limitation between critical connections will be addressed later in this document The figure below is for reference only and the trade off between the number of PCI and ISA slots number of DIMM socket and other motherboard peripherals need to be evaluated for each design Figure 2 2 Example ATX Placement for a UP Pentium II processor Intel 440GX AGPset Design 1 0 Ports O AGP PCI1 Pentium II Slot 1 Host Interface PEUT ERE E PCI Interface E e Weal gt 82443GX E ef OT AGP Interface wuy ASE Interfaco CK rat psoram Interface CK100 0 SDRAM DIMMs IDE 0 1 v002 Inte 440GX AGPset Design Guide Figure 2 3 Example Placement for a UP Intel Pentium II processor Intel 440GX Design 2 2 Inte 440GX AGPset Design Guide NLX Form Factor 1 Motherboard Layout and Routing Guidelines The example placement below shows one Slot connector 4 DIMM sockets and an AGP compliant device down The trace length limitation between critical connections will be addressed later in this The NLX placement and layout below is recommended for a single UP Intel Pentium II processor Intel 440GX AGPset system design For an N
31. edge of the standby power supply voltage A Schmitt trigger circuit is recommended to drive the RSMRST signal To provide the required rise time the millisecond delay should be placed before the Schmitt trigger circuit The reference design implements a 20ms delay at the input of the Schmitt trigger to ensure the Schmitt trigger inverters have sufficiently powered up before switching the input Also ensure that voltage on RSMRST does not exceed VCC RTC Refer to schematics for implementation details If 3 28 Design Checklist standby voltage is not provided by the power supply then tie PWROK signal on the 4 to the RSMRST signal e Ifan 8 2K ohm resistor divider is used to divide the RSMRST signal down to a 3V level for input to the PIIX4E the rise time of this signal will be approximately 170ns based on the input capacitance of the PITX4E which is within the maximum 250ns requirement of the PIIX4E It is important that if any other components are connected to RSMRST the resistor divider values may need to be adjusted to meet a faster rise time required by the other devices and increased loading 3V driving devices such as an 74LVC14 could also be used as a replacement for the voltage divider e It is important to prevent glitches on the PWROK signal while the core well is being powered up or down To accommodate this the reference schematics shows a pull up resistor to 3VSB in the last stage of this circuitry to keep P
32. encompasses other effects besides board coupling such as processor and package crosstalk and ground return inductances In general the additional delay introduced by coupled simulations should be less than 400 ps Validation Flight Time Measurement The timings for the Intel Pentium processor are specified at the processor edge fingers In systems the processor edges fingers are not readily accessible In most cases measurements must be taken at the system board solder connection to the Slot 1 connector To effectively correlate delay measurements to values at the Pentium II processor edge fingers the Slot 1 connector delay must be incorporated Flight time is defined as the difference between the delay of a signal at the input of a receiving agent measured at and the delay at the output pin of the driving agent when driving the reference load However the driver delay into the reference load is not readily available thus making flight time measurement unfeasible There are three options for dealing with this limitation The first option is to subtract the delay of the driver in the system environment at the Slot 1 connection to the board from the delay at the receiver Such a measurement will introduce uncertainty into the measurement due to differences between the driver delay in the reference and system loads If simulations indicate that your design has margin to the flight time specifications this app
33. if this feature is used To implement ring indicate as a wake event the source driving the RI signal must be powered when the PIIX4E suspend well is powered SUSC is connected to PS ON pin 14 of the power supply connector through an inverter to control the remote off function PCIREQ 3 0 is connected between the PITX4E and the PCI bus Bus master request are considered as power management events Connect SMBCLK and SMBDATA to 2 7K ohm approximate pull up resistors to VCC3 and route to all DIMM sockets PUX4E CKBF LM79 LM75 and MAX1617 The 2 7K pull up may not be sufficient for all these loads and their associated trace lengths This needs to be considered on a design by design basis SMBALERT is pulled up to 3VSB with an 8 2K ohm approximate resistor 3 15 1 Power Button Implementation The items below should be considered when implementing a power management model for a desktop system The power states are as follows S1 POS Power On Suspend CPU context not lost 52 POSCCL Power On Suspend CPU Context Lost S3 STR Suspend To RAM 54 STD Suspend To Disk S5 Soft off Wake Pressing the power button wakes the computer from 51 55 Sleep Pressing the power button signals software firmware in the following manner If SCI is enabled the power button will generate an SCI to the OS The OS will implement the power button policy to allow orderly shutdowns Do not override this with additional hardware
34. of an external I O Advanced Programmable Interrupt Controller APIC and Serial Interrupts Chip select decoding is provided for BIOS Real Time Clock Keyboard Controller second external Microcontroller as well as 2 Programmable Chip Selects The PITX4E provides full Plug and Play compatibility The PITX4E can be configured as a Subtractive Decode bridge or as a Positive Decode bridge The PIIXAE supports two IDE connectors for up to four IDE devices providing an interface for IDE EIDE hard disks and CD ROMs Up to four IDE devices can be supported in Bus Master mode The PIIX4E contains support for Ultra DMA 33 synchronous DMA compatible devices The PITX4E contains a Universal Serial Bus USB Host Controller that is Universal Host Controller Interface UHCI compatible The Host Controller s root hub has two programmable USB ports The PITX4E supports Enhanced Power Management including full Clock Control Device Management for up to 14 devices and Suspend and Resume logic with Power On Suspend Suspend to RAM or Suspend to Disk It fully supports Operating System Directed Power Management via the Advanced Configuration and Power Interface ACPI specification The PIIXAE integrates both a System Management Bus SMBus Host and Slave interface for serial communication with other devices For more information on the PIIXAE please refer to thePIIX4 datasheet 1 3 4 Wired for Management Initiative Wired for Management WfM is an
35. of manufacturing variation Intel Pentium II processor models include the I O buffer models core package parasitics and substrate trace length impedance and velocity Intel 440GX AGPset models include the I O buffers and package traces Termination resistors should be controlled to within 5 2 3 11 Simulation Methodology Pre layout simulation allows the system solution space that meets flight time and signal quality requirements to be understood before any routing is undertaken Determining the layout restrictions prior to physical design removes iteration cycles between layout and post layout simulation as shown in Figure 2 13 Intef 440GX AGPset Design Guide 2 13 Motherboard Layout and Routing Guidelines intel o The methodology that Intel recommends is known as Sensitivity Analysis In sensitivity analysis interconnect parameters are varied to understand how they affect system timing and signal integrity Sensitivity analysis can be further broken into two types of analysis parametric sweeps and Monte Carlo analysis which are described below Figure 2 13 Pre layout simulation process 2 4 2 5 2 14 Interconnect Simulations Transmission Line an fut nA Y y y y Sensitivity Analyses M Performance as function of Length Monte Carlo flight time signal quality etc pass fail as function of length Sol
36. ohm pull up to 3VSB CONFIG2 8 2K ohm pull down CPURST Leave as a NC CPU STP GPO17 No connect or connected to CK100 with 10K ohm pull up to 3VSB DACK H 7 0 Connect to ISA slots DACK 3 0 also connect to SIO DEVSEL 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 82443GX PCI slots and DREQ 7 0 Connected to ISA slots 5 6K ohm pull down EXTSMI Connected to LM79 8 2K ohm pull up to 3VSB FERR Connect between CPUs 220 ohm pull up to 2 5V 2 7K ohm pull up to 5V or 10K ohm pull up to Connect between 82443GX PCI slots and GNT C A GPO 1 1 9 No connect GPH Used as PCI PME 8 2K ohm pull up to 3VSB Pull up to 3VSB is also required when not using this pin GPI x y Unused 2 7K ohm pull up to VCC3 GPO x y Unused No connect IDSEL 100 ohm resistor to AD18 IGNNE Part of CPU bus frequency circuit 2 7K ohm pull up to VCC3 INIT Connected to CPUs 330 ohm pull up to 2 5V Part of CPU bus frequency circuit 2 7K ohm pull up to VCC3 DP Connected to IOAPIC INTR Inte 440GX AGPset Design Guide 3 16 Design Checklist intel Table 3 7 PIIX4E Connectivity Sheet 2 of 4 Signal Names Connection IOCHCK Connected to ISA slots 4 7K ohm pull up to VCC IOCHRDY Connected to ISA slots and Ultra I O 1K ohm pull up to VCC
37. pipelining of up to 4 outstanding transaction requests on the system bus For system bus to PCI transfers the addresses are either translated or directly forwarded on the PCI bus depending on the PCI address space being accessed If the access is to a PCI configuration space the processor I O cycle is mapped to a PCI configuration space cycle If the access is to a PCI I O or memory space the processor address is passed without modification to the PCI bus Certain memory address range later referred in a document as a Graphics Aperture are dedicated for a graphics memory address space If this space or portion of it is mapped to main DRAM then the address will be translated via the AGP address remapping mechanism and the request forwarded to the DRAM subsystem A portion of the graphics aperture can be mapped on AGP and corresponding system bus cycles that hit that range are forwarded to AGP without any translation Other system bus cycles forwarded to AGP are defined by the AGP address map DRAM Interface The 82443GX integrates a main memory controller that supports a 64 72 bit DRAM interface which operates at 100 MHz The integrated DRAM controller features supports up to 4 double sided DIMMs 8M to 256M using 16Mbit technology 1 GB using 64Mbit technology and 2 GB using 128M or 256M technology two copies of MAxx are provided for optimized timing and ECC with hardware scrubbing Accelerated Graphics Port Interface The 82443GX suppo
38. power up This pull down resistor allows the BIOS to recognize the absence of an IDE slave device Without this pull down some BIOSs may take up to 30 seconds to recognize that there is no slave device or some BIOSs may hang the system If no IDE is implemented with the PIIXAE the input signals XDREQ and xIORDY can be grounded and the output signals left as no connects Unused ports can be tri stated using the General Configuration Register address offset BOh B3h function 0 Inte 440GX AGPset Design Guide 3 24 3 13 3 13 1 Design Checklist Flash Design Dual Footprint Flash Design New features are coming to the PC continue to increase the size of BIOS code pushing the limits of the 1 Mbit boundary OEMs have already converted many PC designs to 2 Mbit BIOS and higher and more will follow Since it is difficult to predict when BIOS code will exceed 1 Mbit OEMs should design motherboards to be flexible Design in a dual footprint on the motherboard that accepts both Intel s 1 Mbit flash chips and 2 Mbit boot block chips This will make the 1M to 2M transition easier by removing the need for PCB changes to accommodate higher density components Intel provides various layout tools to help OEMs design in the dual footprint These tools are available from Intel s BBS WWW http www intel com design flcomp devtools flas4 html and literature distribution center Look for Application Note AP 623 Multi Site Layout Planning wit
39. successful they are not a substitute for correct design practices nor are they a substitute for other Intel references Slot 1 Test Tools The Slot 1 Test Kit consists of the following test tools The Slot 1 Electrical Mechanical Thermal EMT Test Tool which provides mechanical thermal and voltage transient testing capabilities The Slot 1 Continuity Test Tool CTT which provides continuity testing capabilities for the Slot 1 connector See the Slot 1 Test Kit User s Guide for more information on these tools Debug Simulation Tools Logic Analyzer Interface LAI Logic analyzer interface modules provide a way to connect your logic analyzer to signals on the processor system bus They are available from two logic analyzer vendors Hewlett Packard Co for their HP 16500B series logic analyzers Contact your local Field Sales representative to set up a three way non disclosure agreement to begin discussions with Hewlett Packard on their product This product is purchased directly from Hewlett Packard Tektronix for their DAS NT DAS XP and TDS 700 series logic analyzers Contact your local Field Sales representative for availability of LAI565T interface module for the Intel Pentium II processor from Intel The LAI562T interface module is designed for the Intel Pentium II processor The DAS software is available directly from Tektronix Contact your local Intel Field Sales representative to complete the proper
40. supported on the motherboard See the PCI Specification Rev 2 1 Section 4 3 3 for more information Inte 440GX AGPset Design Guide 3 12 Design Checklist TMS connector pin A3 and TDI connector pin A4 should be independently bussed and pulled up with 5K ohm approximate resistors TRST connector pin 1 connector pin B2 should be independently bussed and pulled down with 5K ohm approximate resistors TDO connector pin B4 should be left open 3 5 4 82443GX AGP Interface The following will help reduce the AGPREF margin needed when data is being written or read via the AGP bus interface Use only two 1 resistors for the AGPREF voltage divider on the 82443GX boards This will limit the AGPREF margin needed to 100mV below 40 of Vcc If 5 resistors are used the AGPREF margin needed would be 160mV Have at least 2x spacing around Strobe A and B to decrease crosstalk inductive coupling from adjacent GAD signals This could reduce crosstalk by as much as 100 300 mV The AGP interface is designed for a 3 3V operating environment and both the master and target AGP compliant devices must be driven by the same supply line No external termination for signal quality is required by the AGP spec but can be added to improve signal integrity provided the timing constraints are still satisfied AGP interrupts may be shared with PCI interrupts similar to the recommendations in the PCI 2 1 sp
41. that can be used in this design This page also shows the In Target Probe ITP Connector The ITP connector is recommended in order to use the In Target Probe tool available from Intel and other tool vendors for Intel Pentium II Processor based platform debug Some logic analyzer vendors also support the use of the ITP connector This connector is optional It is recommended to design these headers into the system for initial system debug and development and leave the connector footprints unpopulated for production Inte 440GX AGPset Design Guide A 1 Intel 440GX AGPset Platform Reference Design intel 82443GX Component System bus and DRAM Interfaces 8 This page shows the 82443GX component System bus and DRAM Interfaces The 82443GX connects to the lower 32 bits of the CPU address bus and the CPU control signals and generates DRAM control signals for the memory interface In this design the 82443GX is configured to interface to a memory array of 4 DIMMs for a DP design The CKBF is also shown on this page The 82443GX delivers a single SDRAM clock to the CKBF which is a 18 output buffer with an 12C interface which may be used to disable unused clock outputs for EMI reduction It outputs 4 clocks to each DIMM socket and 1 back to the 82443GX for data timings The last clock is used for the Global Clock Enable GCKE logic 82443GX Component PCI and AGP Interfaces 9 This page shows the 82443GX component PCI and AGP Interf
42. 0 Figure 2 11 Solution Space for Single Processor Designs With Single End Termination SET 2 5 SUBSTRATE 2 0 TRACE LENGTH IN 1 5 3 0 L1 in Inte 440GX AGPset Design Guide 2 9 Motherboard Layout and Routing Guidelines intel o 2 3 6 Additional Guidelines 2 3 6 1 Minimizing Crosstalk The following general rules will minimize the impact of crosstalk in the high speed GTL bus design Maximize the space between traces Maintain a minimum of 0 010 between traces wherever possible It may be necessary to use tighter spacings when routing between component pins Avoid parallelism between signals on adjacent layers Since GTL is a slow signal swing technology it is important to isolate GTL signals from other signals by at least 0 025 This will avoid coupling from signals that have larger voltage swings such as 5V PCI Select a board stack up that minimizes the coupling between adjacent signals Route GTL address data and control signals in separate groups to minimize crosstalk between groups The Pentium II processor uses a split transaction bus In a given clock cycle the address lines and corresponding control lines could be driven by a different agent than the data lines and their corresponding control lines 2 3 6 2 Practical Considerations Distribute VTT with a wide trace A 0 050 minimum trace is recommended to minimize DC losses Ro
43. 2 CS_A 1 0 CS_B 1 0 Group 0 Group 1 SRAS_A SRAS_B SCAS_A SCAS_B DQM_A 1 5 DQM_A 7 6 4 2 0 DQM_B 1 5 WE B MAA 14 0 MAB 12 11 9 0 MAB 14 13 10 MD 63 0 f 16212 MECC 7 0 16212 DIMM_CLK 3 0 DIMM CLK 7 4 DIMM CLK 11 8 DIMM CLK 15 12 SMB CLK SMB DATA Layout Guidelines All signals require careful routing for both min and max trace lengths Intef 440GX AGPset Design Guide intel Table 2 18 FET Switch DQ Route Example Motherboard Layout and Routing Guidelines 82443GX 1 1 2 0 e 0 6 gt 5 0 6 gt i 2999 0000 jogos 999 0040 al Soto So a v004 82443GX DIMM Module 2 DIMM Module 1 DIMM Module 3 0 6 DIMM Module 4 Inte 440GX AGPset Design Guide 2 25 Motherboard Layout and Routing Guidelines Figure 2 21 Motherboard Model DQMA 0 2 4 6 7 4 DIMMs 1 0 3 25 82443GX DIMM Module 1 DIMM Module 2 DIMM Module 3 DIMM Module 4 Figure 2 22 Motherboard Model DOM 51 4 DIMMs 1 0 3 25 82443GX DIMM Module 1 DIMM Module 2 Figure 2 23 Motherboard Model DQM_A 1 5 4 DIMMs 82443GX DIMM Module 3 DIMM Module 4 2 26 Intef 440GX
44. 2 8 Topology for Single Processor Designs With Single End Termination 8 2 9 Solution Space for Single Processor Designs With Single End RE hnruengizE 2 9 Design ProGess oai ceret eee ieee ee 2 12 Pre layout simulation 2 14 AGP Connector Layout 5 2 19 On board AGP Compliant Device Layout Guidelines 2 21 FET Switch Example cios 2 22 Registered SDRAM DIMM Example sse 2 23 Matching the Reference Planes and Adding Decoupling Capacitor 2 24 4 DIMMs Single or Double Sided 2 24 Motherboard Model Data 4 5 2 25 Motherboard Model DQMA J0 2 4 6 7 4 1 5 2 26 Motherboard Model DQM_AJ1 5 4 5 2 26 Motherboard Model DQM_AJ1 5 4 5 2 26 Motherboard Model DQM_B 1 5 4 5 2 27 Motherboard Model CS_AH CS_BH 4 5 2 27 Motherboard Model SRAS_A 4 2 27 Motherboard Model Data Lines 4 DIMMs FET 2 30 PCI Bus Layout
45. 33 ohm SDDREQ 33 ohm PDCS1 33 ohm SDCS1 33 ohm PDCS3 33 ohm SDCS3 33 ohm PDDACK 33 ohm SDDACK 33 ohm IRQ14 22 47 ohm IRQ15 22 47 ohm RESET 22 47 ohm 3 20 Design Checklist intel One resistor per IDE connector is recommended for all signals For signals labeled as 22 47Q the correct value should be determined for each unique motherboard design based on signal quality Figure 3 4 Series Resistor Placement for Primary IDE Connectors 74HCT14 22 47 ohm RSTDRV Reset 10K ohm PDD 15 0 PDA 2 0 PDCS1 PDCS3 PDIOR PDIOW 5 PDDACK o IRQ14 a PDDREQ wo 5 6k ohm x PIORDY 470 ohm CSEL PIIX4E Pin32 34 v010 RESET comes from the PIIX4E RSTDRV signal through a Schmitt trigger The design consideration shown above illustrates the series resistor placement for trace lengths not exceeding 4 inches Note that if the trace length between the PIIX4E and the IDE header exceeds 4 inches the series resistors should be placed within 1 inch of the PITXAE The series termination resistors are required in either design Inte 440GX AGPset Design Guide 3 21 intel 3 7 3 Design Checklist PIIX4E Power And Ground Pins e Vcc Vcc RTC Vcc SUS and Vcc USB must be tied to 3 3V Vggp must be tied to 5V in a 5V tolerant system This signal must be power up before simultaneous to Vcc and it must be power down after or simultaneous to Vcc For the layout guidel
46. 4 1 Voltage 1 8 1 4 2 General Design Recommendations 1 9 1 4 3 Transitioning from Intel 440BX AGPset to Intel 440GX AGPset 1 9 2 Motherboard Layout and Routing Guidelines 2 1 2 1 BGA Quadrant Assignment sss eere 2 1 2 2 Board Description cedet ccrte retenti acer EREE 2 3 2 3 Routing 5 2 5 231 GTL eaae even ata a dt sa da 2 6 2 3 2 GTL Layout Recommendations sese 2 6 2 3 3 Single Processor 5 2 6 2 3 3 1 Single Processor Network Topology and Conditions 2 6 2 3 3 2 Single Processor Recommended Trace Lengths 2 7 2 3 4 Dual Processor 2 8 2 3 4 1 Dual Processor Network Topology and Conditions 2 8 2 3 4 2 Dual Processor Recommended Trace Lengths 2 8 2 3 5 Single Processor Systems Single End Termination SET 2 8 2 3 5 1 Set Network Topology and Conditions 2 8 2 3 5 2 Trace Length Requirements 2 9 2 3 6 Additional Guidelines sse 2 10 2 3 6 1 Minimizing Crosstalk essen 2 10 2 3 6 2 Practical 2 10 2 8 7 D
47. 8K bytes of BIOS memory A jumper is used to provide the option for allowing the BIOS to be programmed in the system for BIOS upgrades and or for programming plug and play information into the Flash device Note that a 2 Meg Flash device may be required for certain applications motherboard devices such as graphics SCSI or LAN Parallel Port Serial and Floppy Keyboard amp Mouse 28 30 Nothing new here VRM 31 The top of this page shows the voltage regulator modules VRM 8 2 connectors The VRM 8 2 module provides 5V to VCCcore voltage conversion for the processor The bottom of this page shows two voltage regulators one for generating the 1 5 terminating voltage the other is a 2 5V regulator The generation circuit must be able to provide about 5 0 amps of current under worst case conditions Note that two LT1587 1 5s 9 3A are recommended Intef 440GX AGPset Design Guide A 3 Intel 440GX AGPset Platform Reference Design intel Power Connectors Front Panel Jumpers 32 This page shows the system ATX power connector hardware reset logic and standard chassis connectors for the hard disk power LEDs and speaker output Included on this page are the dual color LED circuit required to indicate the system state either ON OFF or any of the suspend states the 6 pin optional ATX connector and the Wake On LAN header Note a CPU Fan Header is required for the Intel Boxed processor The dual color LED circ
48. ACPI BIOS needs to report to the OS which interrupt is used to generate an SCI In a PIC enabled OS like Windows 98 the platform would use the internal IRQ9 In an APIC enabled OS like NT the platform would use INTIN20 for example The ACPI BIOS has the job of telling the OS which one to use but the BIOS does not know which OS will load If the platform only supports an APIC enabled OS Windows NT only there is no issue since the BIOS will just report IRQ20 If the platform needs to support both PIC and APIC operating systems NT amp Windows 98 the BIOS will require a setup screen option that selects between APIC OS IRQ20 and PIC OS IRQO9 so the BIOS can properly report to the OS which interrupt is assigned to the SCI The SMI signal from the PITX4 PITX4E should be connected directly to both processors in a DP system The option to generate an SMI using the SMIOUT signal from the IOAPIC is not recommended because of timing delays through the IOAPIC 3 18 Manageability Devices 3 18 1 Max1617 Temperature Sensor Sensing temperature on the Slotl processor is provided by the THRMDP and THRMDN signals These are connected to a thermal diode on the processor core Consult the MAX1617 data sheet for the manufacturer s specifications and layout recommendations for using this device e D and D are used to connect to the Slot 1 pins B14 and B15 respectively The MAX1617 measures changes in the voltage drop across t
49. AGPset Design Guide intel Motherboard Layout and Routing Guidelines 5 Figure 2 24 Motherboard Model DOM B 1 5 4 DIMMs 82443GX DIMM Module 3 DIMM Module 4 Figure 2 25 Motherboard Model CS AZ CS 4 DIMMs 82443GX Figure 2 26 Motherboard Model SRAS 4 DIMMs 82443GX DIMM Module 2 DIMM Module 1 Intef 440GX AGPset Design Guide 2 27 Motherboard Layout and Routing Guidelines 2 28 Table 2 19 Motherboard Model SRAS_B 4 DIMMs 82443GX DIMM Module 3 DIMM Module 4 Table 2 20 Motherboard Model SCAS_A 4 DIMMs 82443GX DIMM Module 1 DIMM Module 2 Table 2 21 Motherboard Model SCAS_B 4 DIMMs 82443GX DIMM Module 3 DIMM Module 4 Inte 440GX AGPset Design Guide intel Motherboard Layout and Routing Guidelines 5 Table 2 22 Motherboard Model WE 4 DIMMs 82443GX DIMM Module 2 DIMM Module 1 Table 2 23 Motherboard Model WE 4 DIMMs 82443GX DIMM Module 3 DIMM Module 4 Table 2 24 Motherboard Model MA A 14 0 4 DIMMs 82443GX DIMM Module 1 DIMM Module 2 Inte 440GX AGPset Design Guide 2 29 Motherboard Layout and Routing Guidelines H tel o Table 2 25 Motherboard Model MA_B 12 11 9 0 MA_B 14 13 10 4 DIMMs 1 0 3 0 0 4 0 6 n OA 82443GX 10 KQ Max stub
50. AP 566 Thermal Application Note WWW order number 243331 e AP 587 Power Application Note WWW order number 243332 e AP 589 EMI WWW order number 243334 AP 524 Intel Pentium Pro Processor GTL Layout Guidelines order number 242765 AP 525 Intel Pentium Pro Processor Thermal Design Guidelines order number 242766 Multi Processor Specification 1 4 order number 242016 Processor Fan Heat Sink Target Specification Revision 1 0 or later e Slot 1 Test Kit User s Guide Revision 1 0 or later Slot 1 Processor Enabling Technologies Supplier Guide Revision 3 0 PCI Local Bus Specification Revision 2 1 Universal Serial Bus Specification Revision 1 0 Intef 440GX AGPset Design Guide 1 2 1 3 1 Introduction Intel Pentium II Processor Intel 440GX AGPset Overview The following is a list of features that a Intel Pentium processor Intel 440GX System will provide Full Support for up to two Intel Pentium processors with system bus frequencies of 100 MHz Intel 440GX AGPset 82443GX Host Bridge Controller GX 82371EB PCI ISA IDE Accelerator PITX4E 100 MHz Memory Interface A wide range of DRAM support including 64 bit memory data interface plus 8 ECC bits and hardware scrubbing SDRAM Synchronous DRAM Support 16Mbit 64Mbit 128Mbit and 256Mbit DRAM Technologies e 4 PCI Add in Slots PCI Specification Rev 2 1 Compliant 1 AGP Slot AGP Int
51. Axx address lines need to be routed to the two DIMM sockets closest to the 82443GX MABxx will be routed to the one or two DIMM sockets furthest from the 82443GX Selected MABxx lines will also require strapping options to properly configure the 82443GX 3 Can either be a FET or no FET solution A FET solution will require the use of six 56 pin FET switch multiplexers The most common FET switches available are of the 5V family A no FET solution must adhere to the strict no FET design layout guidelines 4 The MD MECC and the DQM lines require T routing for load balancing 5 Copies of SRAS SCAS WE should be evenly distributed throughout the memory array 6 MABxx pins except for MAB10 MAB13 and MAB14 are inverted for signal integrity reasons MAB10 MAB13 and MAB14 are not inverted to maintain correct SDRAM commands 7 Series termination resistors are not required on the motherboard for DIMM signals MD MA DQM CS etc 8 See the SDRAM Serial Presence Detect Data Structure specification for information on the EEPROM register contents 9 The PC SDRAM Unbuffered DIMM Specification Rev 1 0 dated Feb 1998 shows pin 81 of the DIMM module is the WP write protect pin for the SPD EEPROM The block diagrams show there is a 47K pull down resistor tied to the WP pin This allows the DIMM manufacturers to write SPD data to the EEPROM An OEM may wish to use the SPD EEPROM to write information into the DIMMs at production for syst
52. E 430 ohm pull up to 2 5V Connect CPUs and run to jumper on APC_SMI PX4_SMI IOAPIC 430 ohm pull up to 2 5V UP Connect to PIIX4E 430 ohm pull up to 2 5V STPCLK Connect CPUs 430 ohm pull up UP 1K ohm pull up to 2 5V 47 ohm series resistor to ITP Separate series resistors then hooked together to ITP 1K ohm pull up to 2 5V Inte 440GX AGPset Design Guide 3 3 intel Design Checklist Table 3 1 Slot Connectivity Sheet 3 of 3 Processor Pin Pin Connection TDO UP Connected to ITP 150 ohm pull up to 2 5V DP Connected to jumpers between ITP and CPU signals See DP schematics for details TDI UP Connected to ITP 150 ohm 330 ohm pull up to 2 5V DP Connected to jumpers between ITP and CPU signals See DP schematics for details TESTHI UP 4 7K ohm pull up to 2 5V DP Connect CPUs and 4 7K ohm pull up to 2 5V THERMTRIP UP NC if not used 220 ohm pull up to 2 5V if used DP Connect CPUs and 220 ohm pull up to 2 5V TMS UP 1K ohm pull up to 2 5V 47 ohm series resistor to ITP DP Separate 47 ohm series resistors then hooked together to ITP 1K ohm pull up to 2 5V TRDY UP Connect to 82443GX DP Connect CPUs and 82443GX TRST UP Connect to ITP 680 ohm pull down DP Connect CPUs and 680 ohm pull down VID 4 0 8 2K ohm pull up to 5V is the default for VRM use Optio
53. IRST signal when it is lightly loaded This glitch may occur as a result of VCC droop caused by simultaneous switching of most all AD 31 0 signals from 0 to 1 This glitch can in some designs be low enough below 1 7V to interfere with proper operation of the Host PCI Bridge Controller component This sensitivity manifests itself on designs where PCIRST is lightly loaded with less than approximately 5OpF or is not driving the entire PCI bus Design features that could aggravate the problem are an in line active component on the PCIRST signal such as an AND gate or lack of a series termination resistor on the PCIRST signal at the PITX4 or PITXAE There are several improvements that can be implemented individually or in any combination First a series termination resistor between 22 and 33 ohms placed close to the will help reduce the glitch Second an external capacitor of approximately 47pF will help reduce the glitch Intef 440GX AGPset Design Guide 3 22 Design Checklist intel Third if the design currently uses an in line active gate buffer on PCIRST to drive the PCI bus consider removal of this gate buffer entirely The PIIX4 PIIX4E is designed to drive the entire PCI bus Table 3 10 Non PIIX4E PCI Signals SIGNAL CONNECTION ACK64 5V PCI environment 2 7K ohm pull up resistors to 5V PERR 3V PCI environment 10K ohm pull up resistors to 3 3V ie PERR and PLOCK can be connect
54. IX4E should be located at close as possible to the IDE headers to allow the IDE cable to be as long as possible 3 23 2 Design Consideration The BCLK trace to the ITP562 connector is not required to have a matched trace length to the other BCLK signals to the Slot 1 connector or AGPset 3 24 Applications and Add in Hardware 3 24 1 Design Consideration See the MMX Technology Developer s Guide for information on the definition and use of Intel s MMX technology instruction set extension This guide provides optimization guidelines for developers of software utilizing the performance enhancement the instruction set offers Contact your local Intel field sales representative for information on IHVs and ISVs utilizing Intel s MMX technology Contact your local Intel Field Sales representative for information on utilizing Intel s latest AGP technology Inte 440GX AGPset Design Guide 3 38 intel Debug Recommendations intel Debug Recommendations Debug Recommendations 4 4 1 4 2 4 2 1 4 2 2 This chapter provides tool information logic suggestions technical support options and a summary of the problems which have been found to be associated with system debug Although not comprehensive in scope the recommendations are included to preclude unnecessary expenditures of time and effort during the early stages of debug While the methodologies suggested are those which Intel believes are most likely to be
55. If SCIis not enabled Enable the power button to generate an SMI and go directly to soft off or a supported sleep state Intef 440GX AGPset Design Guide 3 30 3 16 Design Checklist Poll the power button status bit during POST while SMIs are not loaded and go directly to soft off if it gets set Always install an SMI handler for the power button that operates until ACPI is enabled Emergency Override Pressing the power button for 4 seconds goes directly to S5 This is only to be used in EMERGENCIES when software is locked up This will cause user data to be lost in most cases Do not promote pressing the power button for 4 seconds as the normal mechanism to power the machine off this violates ACPI To be compliant with the latest PC97 Specification machines must appear off to the user when in the 51 54 sleeping states This includes All lights except a power state light must be off The system must be inaudible Silent or stopped fan drives are off Note Contact Microsoft for the latest information concerning PC97 and Microsoft Logo programs Miscellaneous The 32 kHz oscillator is always required by even if the internal RTC is not used Also if the internal RTC in the is not used an on board battery is not required at the PITX4 PITX4E but is required for an external implementation of the RTC e g RTC in the Super I O In this case connect VCC RTC pin of the PITX4
56. If a design is going to support registered DIMMs the DIMM spacing may need to be evaluated based on mechanical and cooling issues REGE pin 147 on all the DIMMs needs a 0 ohm pull up to enable registered DIMMs Data lines are directly connected to the SDRAM components while all address and control signals are registered The clock signal is routed via a PLL to all the SDRAM devices Access to registered DIMMs requires an additional clock of leadoff latency programmable in the 82443GX Inte 440GX AGPset Design Guide 3 15 Design Checklist intel 3 7 82371EB PIIX4E 3 7 1 PIIX4E Connections Table 3 7 PIIX4E Connectivity Sheet 1 of 4 Signal Names Connection 48MHz Connect to CK100 through a 22 ohm series resistor A20GATE Connected to SIO 8 2K ohm pull up to VCC3 A20M Part of CPU bus frequency circuit 2 7K ohm pull up to VCC3 AD 31 0 Connect to PCI slots and 82443GX AEN Connect to SIO and ISA slots APICACK GPO12 UP Leave as a NC DP Connect to IOAPIC APICCS GPO13 UP Leave as a NC DP Connected to IOAPIC 8 2K ohm pull up to VCC3 APICREQ GPO15 8 2K ohm pull up to VCC3 DP Connected to IOAPIC BALE Connect to ISA slots BATLOW GPI9 8 2K ohm pull up to 3VSB if BATLOW is not used BIOSCS Connect to Flash C BE 3 0 Connect to PCI slots and 82443GX CLOCKRUN 100 ohm pull down CONFIG1 8 2K
57. Intel initiative to improve the manageability of desktop and server systems The goal of WfM is to reduce the Total Cost of Ownership TCO through improved manageability in the following four technology areas Instrumentation Remote Service Boot Remote Wake Up Power Management Intef 440GX AGPset Design Guide 1 6 1 3 3 1 1 3 3 2 Introduction Manageability features in each of these four technology areas combine to form the Wired for Management Baseline Specification A copy of the Wired for Management Baseline Specification can be obtained from ftp download intel com ial wfm baseline paf An on line Design Guide is available at http developer intel com ial WfM design index htm Future versions of the specification which preserve today s investments will be available at this site Instrumentation A component s instrumentation consists of code that maintains attributes with up to the minute values and adjusts the component s operational characteristics based on these values By providing instrumentation the platform provides accurate data to management applications so those applications can make the best decisions for managing a system or product The WfM 1 1a Baseline requires that compliant desktop and mobile platforms utilize the DMI Version 2 00 Management Interface MI and Component Interface CI application programming interfaces and host a DMI v2 00 Service Provider as defined by the DMTF Intel s
58. LX form factor design the AGP compliant graphics device may readily be integrated on the motherboard device down option Figure 2 3 is for reference only and the trade off between the number of DIMM sockets and other motherboard peripherals need to be evaluated for each design 82443GX PCI Interface SDRAM DIMMs ee eNO cette o o TR AGP S O o SDRAM Interface AGP Interface E CKBF 4 Host Interface 1 Pentium II Slot 1 PIIX4E gt PCIO ISA Riser 1 0 Ports v003 Board Description For a single processor Intel 440GX AGPset motherboard design a 4 layer stack up arrangement is recommended The stack up of the board is shown in Figure 2 4 The impedance of all the signal layers are to be between 50 and 80 ohms Lower trace impedance will reduce signal edge rates over amp undershoot and have less cross talk than higher trace impedance Higher trace impedance will increase edge rates and may slightly decrease signal flight times Motherboard Layout and Routing Guidelines intel 5 Figure 2 4 Four Layer Board Stack up Note Note Z 60onms Primary Signal Layer 1 2 oz cu 5 mils PREPREG es Ground Plane 1 oz cu 47 mils CORE Power Plane 1 oz
59. NDA Contact Phone Pericom Kay Annamalai 408 435 0800 x279 IDT Stan Hronik 408 492 8408 Fairchild Semiconductor Myron Miske 207 775 8722 5 3 Third Party Vendor Information H intel 5 3 5 3 1 5 3 2 5 3 3 5 3 4 5 3 5 Other Processor Components Slot 1 Connector Public information see Intel Pentium II Processor Support Components Web page http developer intel com design Pentiumll components index htm Mechanical Support Public information see Intel Pentium Processor Support Components Web page These components include the Slot 1 retention mechanism dual retention mechanism retention mechanism attach mount and heat sink supports Heat sinks Public information see Intel Pentium Processor Support Components Web page Mechanical dimensions are public an MP CITR is required to discuss Intel Pentium processor power levels Heat sink attachment Rivscrews and associated tools Public information see Intel Pentium Processor Support Components Web page http developer intel com design Pentiumll components index htm Thermal interface materials Public information see Intel Pentium Processor Support Components Web page http developer intel com design Pentiumll components index htm Inte 440GX AGPset Design Guide intel Reference Design Schematics intel Inte 440GX AGPset Platform Reference Design Intel 440GX AGPset Platform Reference Design
60. O x WP amp m SA 17 0 SA 17 0 Vcc MEMW WE 0 01 uf aN MEMR OEf l BIOSCS CE 3 14 3 15 Inte 440GX AGPset Design Guide System and Test Signals 8 2K ohm pull up resistor is recommended on the TEST pin of the PIIXAE Power Management Signals A power button is required by the ACPI specification PWRBTN is connected to the front panel on off power button The PIIX4E integrates 16msec debouncing logic on this pin All power button logic should be powered using 3VSB PS_POK from the ATX connector goes to AC power loss circuitry This circuitry allows control of whether the PIIX4E will power up after a power loss or remain off The 4 defaults to powering up the system which may cause system model implementation issues This circuit allows the user BIOS to determine what will happen when a system is plugged in See PIIX4E Application Note 7 System Power Control for details It is highly recommended that the PS_POK signal from the power supply connector not be connected directly to logic on the board without first going through a Schmitt trigger input to square off and maintain its signal integrity PS_POK logic from the power supply connector can be powered from the core voltage supply RSMRST logic should be powered by a standby supply making sure that the input to the PIIX4E is at level The RSMST signal requires a minimum time delay of 1 millisecond from the rising
61. OAPIC if it is not powered For this reason a 74 C125 buffer is included in the schematics to isolate the IOAPIC s INTIN8 signal from the PITX4E s IRQ8 signal when the system is suspended System Timer Interrupt When an IOAPIC is enabled the IRQO output signal reflects the state of the system timer interrupt This signal should be connected to INTIN2 on the IOAPIC with no pull up SCI and SMB Interrupts The IRQ9OUT output signal on the PITX4E reflects the state of the internally generated IRQ9 interrupt The SCI and SMB interrupts are hardwired to IRQ9 in the Intef 440GX AGPset Design Guide 3 32 Design Checklist intel PIIX4E For ACPI compliance this signal must be connected to the IOAPIC There are two different routing options INTIN9 IRQ9OUT can be connected to INTIN9 on the IOAPIC The ACPI BIOS will report to the OS that the SCI uses IRQ9 for both PIC and APIC enabled platforms However for this solution ISA IRQ9 must be left unconnected The could create an ISA legacy incompatibility with ISA cards that must only use IRQ9 Note that this conflict exists in all PIC enabled systems The PIIX4E automatically masks ISA IRQ9 when SCI EN is set INTIN20 INTIN22 IRQ9OUT can be connected to any available IOAPIC interrupt e g INTIN20 INTIN22 or INTIN13 This solution eliminates the IRQ9 ISA legacy conflict described in the INTINO routing option However this routing option creates a new issue The
62. REQO signal i e BREQO should be tied to BREQ1 on the other processor No onboard termination is required because termination is provided on the Intel Pentium II processor FRCERR may be left as a no connect for a DP design if FRC mode is not supported On board termination resistors are not required since they are provided on the Intel Pentium II processors Each processor site should have an isolated power plane Contact your vendor for availability of VRMs with current sharing capabilities if desired The SLOTOCC signal can be used to block the system from booting if two sets of GTL termination resistors are not present The Slot 1 VID lines from each of the connectors can be used to determine if a non functional processor core or terminator card is present The IOAPIC clock is T d and distributed to the CPUs through 22 ohm series resistors 3 3 6 Slot 1 Decoupling Capacitors Additional Vcccogg decoupling capacitance high frequency or bulk may be required for a properly designed Slot 1 power delivery plane and VRM For designs utilizing a local regulator on the motherboard adequate bulk decoupling is required This bulk decoupling is dependent upon the regulator reaction time Contact your regulator vendor for bulk decoupling recommendations that will meet the VRM 8 2 DC DC Converter Specification Decoupling capacitor traces should be as short and wide as possible 3 3 7 Voltage Regulator Mod
63. Soft off is usually provided by a user accessible switch that will send a soft off request to the system The 4 provides the power button input for this purpose and implementation details are described in the schematics A second optional override switch located in a less obvious place or removal of the power cord stops current flow forcing the platform into the mechanical off state without OS consent Note that a second override switch is required for legal reasons in some jurisdictions for example some European countries The BIOS may support the power management requirement either through the APM revision 1 2 or ACPI revision 1 0 specifications This reference design s BIOS implementation incorporates both interfaces The PIIX4 provides hardware level register support for both the APM and ACPI specifications See Intel s web site for additional information http developer intel com ial WfM design pmdt index htm Design Recommendations Voltage Definitions For the purposes of this document the following nominal voltage definitions are used 5 0V Vcc3 3 3V VeccorE Voltage is dependent on the five bit VID setting Vcc 5 2 5V VTT 1 5V VREF 1 0V Inte 440GX AGPset Design Guide 1 8 Introduction 1 4 2 General Design Recommendations 1 Intel recommends using an industry standard programmable Voltage Regulator Module installed in a header or an onboard programmable voltage regulator desi
64. THERM Model A FLOTHERM Model is available for the Intel Pentium II processor Debug Features These suggestions are for debug purposes only on initial prototype systems and are not required for production level systems Some of these features may be desirable test functions that you may incorporate onto production boards Intel Pentium II Processor LAI Issue If the LAI562 tool is not being used this issue can be ignored However be aware that if you send a system to Intel for debug the absence of the required workarounds will prohibit debugassistance from Intel To maintain backward compatibility with Intel Pentium II processor Intel suggests the following circuitry to be considered The LAI562 integration tool has been designed such that an extra load will be presented on the CMOS signals connected to the Slot 1 connector The following list of signals are affected PREQ TCK TDI TDO TMS TRST INIT FLUSH STPCLK PICCLK PICD 1 0 LINT OJ INTR LINT 1 NMI IERR SMI PVRGOOD THERMTRIP SLP FERR IGNNE and A20M Figure 4 1 describes the CMOS probe signals of the LAI562 Inte 440GX AGPset Design Guide 4 2 intel Debug Recommendations Figure 4 1 LAI Probe Input Circuit 500 Ohms 68 Ohms From Target 100 nH 100 Ohms Vtt CMOS 1 04V The extra loading of the LAI562 requires stronger pull up values on the target system However due to the current limitations of some si
65. TLREFB GTL buffer voltage reference input 1 0V 2 3 vit 31 3 Connected to CPUs HCLKIN Connected to CK100 through 22 ohm series resistor HD 63 0 Connected to the CPUs HIT HITM Connected to CPUs HLOCK Connected to CPUs HREQ 4 0 Connected to CPUs HTRDY Connected to CPUs IRDY 2 7K ohm pull up to 5V Connected to PCI bus MAA 14 0 Connected to DIMMO and DIMM1 MAE Connected to DIMM2 and DIMMS MD 63 0 MECC 7 0 Connected to each DIMM FET Switch Design Connected to FET switches PAR Connected to PCI bus PCIRST Connected to PIIX4E AGP connector and PCI connectors PCLKIN Connected to CK100 through 22 ohm series resistor PGNT 4 0 8 2K ohm pull ups to 3 3V Connected to PCI connectors PHLDA 8 2K ohm pull up to 3 3V Connected to PIIX4E PHOLD 8 2K ohm pull up to 3 3V Connected to PIPE 8 2K ohm pull ups to 3 3V Connected to AGP connector PLOCK 2 7K ohm pull up to 5V Connected to PCI connectors PREQ 4 0 2 7K ohm pull ups to 5V Connected to PCI connectors except PREQ4 RBF 8 2K ohm pull up to 3 3V Connected to AGP connector REFVCC5 PCI 5V reference voltage for 5V tolerant buffers RS 2 0 Connected to CPUs SBA 7 0 Connected to AGP connector SBSTB 8 2K ohm pull up to 3 3V Connected to AGP connector SCAS B A E Each connected to up to 2 DIMMs SERR
66. WROK from glitching when the core supply goes out of regulation All logic and pull ups in the path of PWRGOOD to the CPU PWROK to the PITX4E with the above exception can be powered from the core supply The PWROK signal to the chipset is a 3V signal The core well power valid to PWROK asserted at the chipset is a minimum of Imsec PWROK to the chipset must be deasserted a minimum of Ons after RSMRST PWRGOOD signal to CPU is driven with an open collector buffer pulled up to 2 5V using a 330 ohm resistor Below is a simplified diagram of the PVRGOOD and PWROK logic which is connected to the CPU slots and PIIXAE respectively in a DP system The circuitry checks for both slots occupied both CPU VRMs powered up and the 5 signal from the ATX power supply connector before asserting PWRGOOD and PWROK to the CPU and PIIXAE A reset button override pull down is also included causing the PWRGOOD and PWROK signals to get deasserted when pressed Figure 3 8 PVRGOOD amp PWROK Logic PWRGOOD PWROK generation logic VCC3 A SLOTOCC PWRGOOD to CPU B SLOTOCC gt 2 5V VRM1_PWRGD VRM2_PWRGD ITP_RESET ATX_PS_POK PWROK to PIIX4E 3 3V Note The polarities have been altered to simplify drawing v011 The following should be considered when implementing a RESET BUTTON for desktop based systems Intef 440GX AGPset Design Guide 3 29 Design Checklist
67. aces The definition of pin AF3 has been changed from SUSCLK to GX PWROK Like 4 PWROK it is connected to the PWROK logic from the Power Connector page Page 32 Note the GCLKIN and GCLKOUT trace length requirements on the AGP interface 82443GX Component Memory and System Data Bus Interfaces 10 This page shows the 82443GX component Memory and System Data Bus Interfaces GTL_REF signal are also shown on this page Ideally the GTL_REF signals should be decoupled separately and as close as possible to the 82443GX component but this is not a requirement The GCKE shift register circuit is also shown FET Switch Component 11 and 12 These FET switches are used for a 4 DIMM memory configuration 500 ohm series resistors have been added to all of the grounded xA2 input pins DIMM Connectors 0 1 2 and 3 for the DP 4 DIMM schematics 13 16 These three pages show the DRAM interface connections from the 82443GX to the DRAM array The serial presence detect pins are addressed as 1010 000 001 011 respectively 82443GX strap pull up pull downs will be located on selected MAB lines REGE pin 147 on each DIMM socket should be pulled high to enable registered DIMMs PIIX4E Component 17 This page shows the PIIX4E component The component connects to the PCI bus dual IDE connectors and the ISA bus This reference design supports a subset of the power management features of the PIIXAE PIIX4E Component 18 This page shows the
68. als should be connected in a daisy chain keeping transmission line stubs to the Intel 440GX AGPset under 1 5 inches Intel Pentium II processors should be placed at the end of the bus to properly terminate the GTL signals For a single Intel Pentium II processor design Intel recommends that termination resistors be placed at the other AGPset end of the bus This provides the most robust signal integrity characteristics and maximizes the range of trace lengths that will meet the flight time requirements The recommended termination resistor value is 56Q 5 For dual Intel Pentium II processor based designs a termination card must be placed in the unused slot when only one processor is populated This is necessary to ensure that signal integrity requirements are met Refer to Slot 1 Bus Termination Card Design Guidelines for details Pre Layout Simulation Sensitivity Analysis After an initial timing analysis has been completed simulations should be performed to determine the bounds on system layout The layout recommendations in Section 4 Debug Recommendations on page 4 1 are based on results of pre layout simulations conducted by Intel interconnect simulations using transmission line models are recommended to determine signal quality and flight times for proposed layouts Recommended parameter values can be obtained if your supplier s specific capabilities are known The corner values should comprehend the full range
69. ations for Existing Board Designs to minimize ESD events that may cause loss of CMOS contents The effectiveness of adding a luF capacitor as identified above needs to be determined by examining the routing and placement For example placing the capacitor far from the PILX4 reduces its effectiveness 82093AA IOAPIC An I O APIC is required for a DP system and is optional for a UP system The I O APIC is a 5V device Vcc pins must be connected to SV Pins 19 51 and 64 are 5V power and pins 1 33 and 52 are ground pins APICCLK may be at 2 5V 3 3V or 5V levels If it is shared with the Slot 1 PICCLK then it must be 2 5V The maximum frequency is 16 666 MHz while the minimum is 14 3 MHz APICACK2 pin 8 This pin is connected to the Intel 440GX AGPset WSC signal CLK is compatible with 2 5V 3 3V or 5V input levels It is typically connected to the APIC clocks that are 2 5 V The maximum frequency is 33 MHz while the minimum is 25 MHz SMI support The option to route SMI through the IOAPIC in a Dual Processor system is not recommended due to timing constraints between the PIIX4E and the Slot 1 processors RTC Alarm Interrupt When an IOAPIC is enabled the IRQ8 output signal on the PITX4E reflects the state of IRQ8 IRQ8 resides in the PITX4E suspend well and connects to INTIN8 on the IOAPIC If the system is put in a STD SOFF state the PIIX4E will continue to drive IRQS to the IOAPIC which could damage the I
70. available 1 NIC with Option ROM and Wake on LAN Header or 2 aLAN on Motherboard implementation For the second option the Preboot execution environment and the network controller code must be incorporated into the system BIOS In addition the BIOS must provide the SYSID and _UUID_ data structures The details of the BIOS requirements can be obtained from the Intel web site http developer intel com ial WfM design pxedt index htm Inte 440GX AGPset Design Guide 1 7 1 3 3 4 1 4 1 4 1 Introduction Remote Wake Up If a PC supports a reduced power state it must be possible to bring the system to a fully powered state in which all management interfaces are available Typically the LAN adapter recognizes a special packet as a signal to wake up the system This reference design utilizes a Wake on LAN WOL Header to provide standby power to the NIC and the interface for the wake up signal The physical connection to the NIC and motherboard is via WOL Cable provided with the design kit See the WOL Header Recommendations document at ftp download intel com ial wfm wol_v14 pdf The system BIOS must enable the wake event and provide wake up status The details of the BIOS requirements can be obtained from the Intel Corporation web site http developer intel com ial WfM design rwudt index htm Power Management WIM Baseline compliant systems have four distinct power states Working Sleeping Soft Off and Mechanical Off
71. d ISA slots TEST 8 2K ohm pull up to 3VSB THERM GPI8 Connected to LM75 8 2K ohm pull up to VCC3 TRDY 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 82443GX PCI slots and PIIX4E USBPx 47pF cap to ground with 27 ohm series resistor to USB port These should be placed as close as possible to the PIIX4E VBAT Connect to battery circuit Connect to 82443GX and power supply sequencing circuit See PIIX4E data REF sheet XDIR GPO22 Connect to SIO XOE GPO23 Connect to SIO ZEROWS Connected to ISA slots 1K ohm pull up to VCC 27 GPO19 Inte 440GX AGPset Design Guide 3 19 3 7 2 1 3 7 2 2 Design Checklist IDE Routing Guidelines This section contains guidelines for connecting and routing the PIIXAE IDE interface The 4 has two independent IDE channels This section provides guidelines for IDE connector cabling and motherboard design including component and resistor placement and signal termination for both IDE channels The current recommendations use 33 ohm resistors on all the signals running to the two ATA connectors while the remaining signals use resistors between 22 and 47 ohm resistors Cabling 1 2 3 Length of cable Each IDE cable must be equal to or less than 18 inches Capacitance Less than 30 pF Placement A maximum of 6 inches between drive connectors on the cable If a single drive is placed on the cable it should be placed
72. d for hardware design engineers who are experienced in the design of PC motherboards or memory subsystem This document is organized as follows Chapter 1 Introduction This chapter provides an overview of the features on reference design Chapter 1 also provides a general component overview of the Intel Pentium II processor and Intel 440GX AGPset The Wired for Management Initiative is also discussed which is an Intel initiative to improve the manageability of desktop mobile and server systems This chapter also provides design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segment Chapter 2 Motherboard Layout and Routing Guidelines This Chapter provides detailed layout routing and placement guidelines for the motherboard and memory subsystem Design guidelines for each bus Host GTL PCI DRAM and AGP are covered This chapter provides details on design methodology Timing analysis simulation and design validation Chapter 3 Design Checklist This chapter provides a design checklist that is intended to be used when reviewing your Intel 440GX AGPset design The checklist is based on the Intel 440GX AGPset reference design provided in this Design Guide Items which have been found to be incorrect on previous designs are provided as a tool to allow the quick debug of Intel Pentium II processor based systems Chapter 4 Debug Recommendations This chapter presents
73. d other traces A minimum spacing of 0 018 is recommended for serpentines Figure 2 30 Clock Trace Spacing Guidelines 2 9 6 2 2 32 System Bus Clock Layout System bus clock nets should be routed as point to point connections with a 22 Ohm series resistor that is to be placed as close to the output pins on the clock driver as possible 0 5 In a UP system clock skew between the 82443GX and the processor can be reduced by tying the clock driver pins together at the clock chip and driving the processor and 82443GX from this net with a 10 Ohm resistor at the driver for each Trace lengths still match the specs defined below Layout guidelines Match trace lengths to the longest trace Net Trace length min max Substrate Clock chip Processor H 1 0 9 0 3 25 Clock chip 82443GX H 3 25 1 0 12 0 NA Clock chip ITP H 4 00 1 0 13 0 NA Inte 440GX AGPset Design Guide 2 9 6 4 Note Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines PCI Clock Layout PCI clock nets should be routed a point to point connections with a 22 Ohm series resistor that is to be placed as close to the output pins on the clock driver as possible lt 0 5 Layout guidelines Match trace lengths to the longest trace Net Trace length min max Substrate Clock chip PCI connector H 4 8 1 0 12 5 2 5 Clock chip PIIX4E 7 3 1
74. d to IDE connector through 33 ohm series resistor PCS3 Connected to IDE connector through 33 ohm series resistor PDA 2 0 Connected to IDE connector through 33 ohm series resistors PDD 15 0 Connected to IDE connector through 33 ohm series resistors It is recommended that PDD 7 have a 10K ohm pull down resistor PDDACK Connected to IDE connector through 33 ohm series resistor PDIOR Connected to IDE connector through 33 ohm series resistor PDIOW Connected to IDE connector through 33 ohm series resistor PDREQ Connected to IDE through 33 ohm series resistor 5 6K ohm pull down on the PIIX4E side of the series resistor PGCS 0 No connect PGCS 1 8 2K ohm pull up to VCC3 Connected to LM79 Inte 440GX AGPset Design Guide 3 17 Design Checklist intel Table 3 7 PIIX4E Connectivity Sheet 3 of 4 Signal Names Connection PHLD Connected to 82443GX 8 2K ohm pull up to VCC3 PHLDA Connected to 82443GX 8 2K ohm pull up to VCC3 PIORDY Connected to IDE through 47 ohm series resistor 1K ohm pull up to VCC on the PIIX4E side of the series resistor 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 443GX PCI PIRQ D A slots and PIIX4E PIRQ A B also go to AGP DP PIRQ A D connected to IOAPIC PWRBT From power button circuitry PWROK Connect to 82443GX and power up logic RCIN 8 2K
75. debug recommendations that may assist in the development of the Intel Pentium II processor Intel 440GX AGPset and products utilizing them This chapter also provides tool information logic suggestions technical support options and a summary of the problems which have been found to be associated with system debug Chapter 5 Third Party Vendor Information This chapter includes information regarding various third party vendors who provide products to support the Intel 440GX AGPset Appendix A Intel 440GX AGPset Reference Design Schematics This appendix provides the schematics used in the single processor and dual processor reference designs Intef 440GX AGPset Design Guide 1 1 intel 1 2 References Intel Pentium II Processor Datasheet Intel 440GX AGPset Datasheet WWW order number 290638 Intel 82371EB PCI to ISA IDE Xcelerator PIIX4 Datasheet WWW order number 290562 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture order number 243190 Intel Architecture Software Developer s Manual Volume 2 Instruction Set Reference order number 243191 Intel Architecture Software Developer s Manual Volume 3 System Programming Guide order number 243192 Intel Architecture MMX M Technology Developer s Guide order number 243006 AP 485 CPUID Application Note WWW order number 41618 e AP 585 Layout Application Note WWW order number 243330
76. e Chang 503 652 7300 Astec Tichard To 852 2411 7429 Switch Power Jeff Van Skike 408 871 2400 Voltage Regulator Control Silicon The following vendors are developing DC DC converter silicon and reference designs for Intel Pentium II processor voltage and current requirements Generally VRM 8 1 5 bit VID control silicon supports VRM 8 2 requirements Table 5 5 Voltage Regulator Control Silicon Vendors Supplier Intel CNDA Contact Phone Cherry Semiconductor Barbara Gibson 401 886 3895 Elantee Steve Sacarisen 408 945 1323 x345 Harris Dean Henderson 919 405 3603 International Rectifie Chris Davis 310 252 7111 Linear Technology Jim MacDonald 408 432 1900 x2361 LinFinity Andrew Stewart 714 372 8383 Maxim David Timm 408 737 7600 Micro Linear Doyle Slack 408 433 5200 Motorola Stan Livingston 503 641 6881 atheon Dave Mcintyre 415 962 7734 Semtech Alan Moore 805 498 2111 x291 Sharp See Sharp Web site Siliconix Howard Chen 408 567 8151 Unisem Reza Amirani 714 453 1008 Unitrode Larry Spaziani 603 424 2410 Inte 440GX AGPset Design Guide 5 2 5 2 5 2 1 Table 5 6 5 2 2 Table 5 7 5 2 3 Table 5 8 Inte 440GX AGPset Design Guide Third Party Vendor Information Intel 440GX AGPset Clock Drivers Intel has supplied specifications to clock driver vendors including the following
77. ec For example in a system with 3 PCI slots and one AGP slot interrupts should be connected such that each of the four INTA lines hooks to a unique input on the PITX4E It is recommended that the interrupts be staggered It is also recommended that each PIRQ be programmed to a different IRQ if possible It is the requirement of the motherboard designer to properly interface the AGP interrupts to the PCI bus In this reference design the AGP interrupts are pulled up to 3 3V and a buffer is used to isolate the 5V environment from the AGP bus To minimize the impact of any mismatch between the motherboard and the add in card a board impedance of 65 15 ohms is strongly recommended At each component that requires it AGP_Vref should be generated locally from the AGP interface Vddq rail Table 3 5 Strapping Options Signal Description Register Pulled to 0 Pulled to 1 MAB9 AGP Signals PMCR 1 AGP Enabled Default AGP Disabled MAB11 In Order Queue Depth Maximum Queue Depth MGXCFG 2 Non Pipelined Enabled Default MAB12 Host Frequency NGXCFG 13 Reserved 100MHz Default NOTES a w A MAB 9 is connected to internal 50K ohm pull down resistors MAB 12 11 are connected to internal 50K ohm pull up resistors Note that strapping signals are not driven by the 82443GX during reset sequence Proper strapping must be used to define logical values for these sig
78. ed together across PCI slots and pulled up by single resistor FEN Each REQ64 and ACK64 requires its own pull up GNT 3 0 Connected between PCI slots and 82443GX 8 2K ohm pull up to VCC3 IDSEL lines to PCI connectors 100 ohm series resistor recommended per the PCI spec SBO SDONE 5 6K ohm pull up to VCC 3 9 ISA Signals Table 3 11 Non PIIX4E ISA Signals SIGNAL CONNECTION OSC1 Connected to CK100 through 22 ohm resistor RMASTER 1K ohm pull up to VCC 3 10 ISA and X Bus Signals The PITX4E will support a maximum of 5 ISA slots XOE and XDIR are connected to the ULTRA I O device e If internal RTC is used RTCALE and RTCCS no connect or become general purpose outputs by programming the General Configuration Register GENCFG in the Function 0 offset BOh B3h The LM79 is connected to the X Bus due to the functionality of the PGCS 1 0 pins on the PIIXAE Intef 440GX AGPset Design Guide 3 23 intel Design Checklist 3 11 USB Interface Contact your local Intel Field Sales representative for the following Application Note 82371AB Application Note 1 USB Design Guide And Checklist Rev 1 1 This document discusses details of the PITX4 PIIX4E implementation of the Universal Serial Bus Included in the discussion are motherboard layout guidelines options for USB connector implementation USB clocking guidelines and a design checklist The AGP OVRCNT pin sh
79. el recommends using a value of 1 0 Q mil in for lossy simulations Higher values tend to increase the amount of ringback on the rising edge while smaller values tend to increase the amount of ringback on the falling edge It is not necessary to budget for variation if your simulations comprehend the expected manufacturing variation T O Buffer models for the fast corner correspond to the minimum T Slow corner buffers will be at least 500 ps slower Therefore it is only necessary to ensure that the minimum flight time is met when the network is driven by fast buffer models Buffer models for the slow corner correspond to the maximum Fast corner buffers will be at least 500 ps faster It is only necessary to ensure that the maximum flight time is met when the network is driven by slow buffer models as long as no ringback problems exist Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Design Methodology Intel recommends using the following design methodology when designing systems based on one or two Intel Pentium processors and one Intel 440GX AGPset The methodology from Intel s experience developing and validating high speed GTL bus designs for the Intel Pentium Pro and Intel Pentium II processors The methodology provides a step by step process which is summarized in Figure 2 12 The process begins with an initial timing analysis and topology definition Tim
80. em level checkout to identify the DIMM installed as being shipped with the system For this reason the OEM may wish to include some logic to control the level on pin 81 of the DIMM modules so that after the DIMM is tagged they can be write protected again If this pin is pulled high on the motherboard the DIMM SPD EEPROM is write protected Pin 81 of the DIMM sockets on the 82443GX dual processor reference schematics currently shows a NC no connects If an OEM wishes to write protect the SDRAM SPD EEPROMS then these pins should be pulled high Inte 440GX AGPset Design Guide 3 14 Design Checklist intel 3 6 2 DIMM Solution With FET Switches e With existing 64Mbit technology 512 MB 1 GB and 2 GB support for servers and workstations must have 4 double sided DIMMs 500 ohm IK ohm pull down resistors on each of the second inputs 1A2 2A2 etc are recommended on the FET switches 500 ohms is recommended based on simulation to prevent a direct short to ground while switching Figure 3 3 Current Solution With Existing FET Switches DQA 0 71 82443GX DOB 0 71 v009 vsd All 72 DQ lines are fed through the FET switch The current FET switch is Pericom PISC16212A package type A56 See third party vendor list for more FET switch vendors e 12 functional units per part requires 6 devices on motherboard 3 6 3 Registered SDRAM There may be power and thermal considerations for registered DIMMs
81. ended on the CPU PCI and IOAPIC clock outputs Ina UP system clock skew between the 82443GX and the CPU can be reduced by tying the clock driver pins together at the clock chip and driving the CPU and 82443GX from this net with a 10 Ohm resistor at the driver for each e 10K ohm pull ups to VCC are recommended on PCI_STP CPU_STP PWRDWN4 If POS is not supported connecting these signals to the PIIXAE is not required On reset SUSA connected to PVRDWNT is asserted which causes the clock outputs to stop This may cause problems with the ITP when connected Zero ohm stuffing options can be used to select the functionality Check with your clock vendor and the reference schematics for special layout and decoupling considerations The reference schematics implement an LC filter on the supply pins to reduce noise Intef 440GX AGPset Design Guide 3 8 intel Design Checklist 3 4 2 CKBF SDRAM 1 to 18 Clock Buffer A 4 7K ohm pull up to VCC3 3 on the OE pin is needed to enable the buffer Note that DCLKRD pin has been changed to a no connect NC The DCLKRD functionality has been combined with DCLKWR If desire to remove the trace going to DCLKRD pin the capacitor value should be adjusted to compensate for the capacitance change An interface is provided which allows the BIOS to disable unused SDRAM clocks to reduce EMI and power consumption It is recommended that the BIOS disable unused clocks No series ter
82. erface Specification Rev 1 0 Compliant AGP 66 133 MHz 3 3V device support Integrated IDE Controller with Ultra DMA 33 support PIO Mode 4 transfers PCI IDE Bus Master support Integrated Universal Serial Bus USB Controller with 2 USB ports Integrated System Power Management Support On board Floppy Serial Parallel Ports ISA Add in slots APIC device support for MP interrupt support Intel Pentium II Processor The Intel Pentium processor is a follow on to the Intel Pentium Pro processor This high performance Intel Architecture processor offers features that can be designed into products for the following market segments Desktop Home Market Segment Desktop Corporate Market Segment Workstation Market Segment Server Market Segment New applications and hardware add ins from third party vendors are being developed that take advantage of the MMX technology incorporated into the Intel Pentium processor Please contact your local Intel field sales representative for information on IHVs and ISVs utilizing Intel s MMX technology Inte 440GX AGPset Design Guide 1 8 intel Intel introduced the Intel Pentium II processor as 350 100 and 400 100 speeds with 512 KB L2 cache versions 1 3 2 Intel 440GX AGPset The Intel 440GX AGPset is the fourth generation chipset based on the Intel Pentium Pro processor architecture It has been designed to interface wi
83. eries resistor SERIRQ GPI7 2 7K ohm pull up to VCC3 SERR 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 82443GX PCI slots and SIORDY Connected to IDE through 47 ohm series resistor 1K ohm pull up to VCC on the PIIX4E side of the series resistor SLP Connected to CPUs 330 ohm pull up to 2 5V SMBALERT GPI11 Connect to MAX1617 8 2K ohm pull up to 3VSB Inte 440GX AGPset Design Guide 3 18 intel Design Checklist Table 3 7 PIIX4E Connectivity Sheet 4 of 4 Signal Names Connection SMBCLK Connect to all devices on SMBus 2 7K ohm pull up to VCC3 This value may SMBDATA need to be adjusted based on bus loading SMEMR SMEMW Connected to ISA slots 1K ohm pull up to VCC 430 ohm pull up to 2 5V This is an open drain output from PIIX4E UP Connected to CPU DP Connected to IOAPIC SPKR Connect to speaker circuit STOP 2 7K ohm pull up to 5V or 10K ohm pull up to 3V Connect between 82443GX PCI slots and PIIX4E STPCLK Connected to CPUs 430 ohm pull up to 2 5V This is an open drain output from the PIIX4E No connect or connected to CK100 power down control with 10K ohm pull up SUSA to VCC3 SUSB GPO15 No connect SUSC GPO16 Controls ATX power supply SUSCLK No Connect SUS_STAT 2 1 GPO 21 20 No Connect SYSCLK Connect to LM79 and ISA slots TC Connect to SIO an
84. ese AGP layout guidelines 82443GX Memory Subsystem Layout and Routing Guidelines 100 MHz 82443GX Memory Array Considerations Designing a reliable and high performance memory system will be challenging Careful consideration of motherboard routing and stackup topologies DIMM topology impedance and trace lengths must all be taken into account The 82443GX when configured with 4 double sided DIMMs have heavy DQ loading To offset the heavy loading on the DQ lines a FET switch mux is recommended to reduce the loading for memory driving the 82443GX and vice versa An alternative NO FET solution is also provided but this solution has more strict routing restrictions Figure 2 16 FET Switch Example 2 22 to 82443GX MDs amp MECCs to DIMM 1 0 DQs to DIMM 3 2 DQs To build large capacity DIMMs i e 512 MB using present day technology x4 SDRAM devices must be used The loading on the control lines MA GXx CS DQM CK etc are now twice the loading of a x8 device A DIMM which registers these control lines must be produced to meet 100 MHz timings note that a PLL must be added to the registered DIMM and the additional PLL jitter must be factored into the overall timing analysis Electrical thermal and layout topologies for these registered DIMMs can be founded at the following Web address http www intel com design pcisets memory index htm Inte 440GX AGPset Design Guide Motherboard Layout and Routin
85. esign Methodology 2 11 2 8 8 Performance Requirements 2 12 2 8 9 Topology Definition 2 13 2 3 10 Pre Layout Simulation Sensitivity Analysis 2 13 2 4 Placement Layout 2 14 2 5 Post Layout Simulation itt tne te Cr eade ehe ede tag 2 14 2 5 1 Crosstalk and the Multi Bit Adjustment 2 15 Inte 440GX AGPset Design Guide ii 2 6 Valida Mica EE 2 15 2 6 1 Flight Time Measurement 2 15 2 6 2 Signal Quality Measurement sse 2 16 2 7 Timing Analysis t pedi ERE pipi epe 2 17 2 8 AGP Layout and Routing Guidelines eene 2 19 2 8 1 AGP Connector Up Option Layout Guidelines 2 19 2 8 2 On board AGP Compliant Device Down Option Layout Guidelines 2 20 2 9 82443GX Memory Subsystem Layout and Routing Guidelines 2 22 2 9 1 100 MHz 82443GX Memory Array 5 2 22 2 9 1 1 Matching the Reference Planes 2 23 2 9 1 2 Adding Additional Decoupling Capacitor 2 23 2 9 1 3 Trace Width vs Trace Spacing 2 24 2 9 2 Memory Layout amp Routing Guidelines 2 24 2 9 3 4 DIMM Routing Guidelines NO
86. fied at the processor core which is not accessible Intel has found that there can be substantial miscorrelation between ringback at the edge finger versus the core The miscorrelation creates instances where a signal fails to satisfy ringback requirements at the edge finger but passes the ringback specification at the core For this reason signal integrity is specified at the core Ringback guidelines are supplied at the edge finger as shown in Table 2 6 Any measurement at the edge finger that violates the guidelines should be simulated to verify that it meets the specification at the core Table 2 6 Ringback Guidelines at the Intel Pentium II Processor Edge Fingers Guideline Processor Edge Edge Finger Spec 9 Processor Core Rising 1 29V 1 1241 Falling 0 71V 0 88V NOTE 1 Ringback specifications follow the methodology described in Inte Pentium II Processor at 233 MHz 266 MHz 300 MHz and 333 MHz Datasheet 2 16 Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Timing Analysis To determine the available flight time window perform an initial timing analysis Analysis of setup and hold conditions will determine the minimum and maximum flight time bounds for the host bus Use the following equations to establish the system flight time limits Table 2 7 Intel Pentium II Processor and Inte I 440GX AGPset System Timing Equations Driver Receiver Equation
87. for the Intel Pentium II processor and Intel 440GX AGPset are contained in Table 2 10 The timing specifications are contained in the Intel Pentium II processor and Intel 440GX AGPset Datasheets These timing are for reference only Intel Pentium II Processor and Intel 440GX AGPset 100 MHz Timing Specifications Timing Term Intel Pentium II Processor Intel 440GX AGPset NS 4 66 4 45 Ns 0 71 0 80 ns 1 97 3 00 Th ns 1 61 0 10 NS 0 77 Not applicable Ns 0 84 No applicable Recommended values for system timings are contained in Table 2 10 Skew and jitter values for the clock generator device come from the CK97 clock driver specification The PCB skew spec is based on the results of extensive simulations at Intel The value is based on Intel s experience with systems that use the Intel Pentium Pro processor and Intel Pentium processor Table 2 10 Recommended 100 MHz System Timing Parameters Timing Term Value Tskew cLk ns 0 18 Tskew PcB Ns 0 15 ns 0 25 Tagj ns 0 40 The flight time requirements that result from using the component timing specifications and recommended system timings are summarized in Table 2 11 All component values should be verified against the current specifications before proceeding with analysis Table 2 11 Recommended 100 MHz System Flight T
88. g Guidelines Figure 2 17 Registered SDRAM DIMM Example 2 9 1 1 Data Control Clock There are also population rules which need to be observed To properly adjust memory timings for 100 MHz operation it is asked of the OEM and end user to populate the motherboard starting with the DIMM located the furthest from the 82443GX Matching the Reference Planes Providing a good return path for the AC currents induced on the power and ground planes is critical to reducing signal noise The best way to provide a low inductance return path is to match the BGA and motherboard reference planes for a given signal For example MDO is routed on the BGA next to the ground plane To match the reference planes MDO should be routed on the Motherboard such that it is closest to the motherboard ground plane Routing the memory signals in this manner will provide the best possible path for the return currents Table 2 17 MDx lines Reference Planes Routing 2 9 1 2 82443GX BGA Motherboard ee Reference Layer Reference Plane MDO MD1 MD2 MD3 MD4 MD7 MD11 MD14 MD15 MD16 MD17 MD19 MD20 MD21 MD22 MD23 MD27 MD28 MD29 MD31 MD33 MD36 MD37 MD38 MD40 MD41 MD42 MD43 MD 44 MD45 MD48 MD49 MD52 MD53 MD55 MD56 MD 57 MD 58 MD61 MD62 MD63 6 0 MD5 MD6 MD8 MD9 MD10 MD12 MD13 MD18 MD24 MD25 MD26 MD30 MD32 MD34 MD35 MD39 MD46 MD47 MD50 MD51 MD54 MD59 MD60 MECC7
89. gnal drivers this stronger value may not be feasible Calculation of the correct pull up resistor value for each of the CMOS signals should include a load analysis based on the pull up voltage pull up voltage tolerance pull up resistor tolerance V IH and V IL specifications driver current rating input current leakage input timings etc The resulting values may conflict As a result of the extra loading the following compromise pull ups to Vcc 2 5 are recommended The actual value required by your system may vary depending on the logic connected and the drive strength of the signal to the Slot 1 connector Inputs to the Slot 1 connector from the ITP562 Port PREQ 150 330 ohm TDI 150 330 ohm TMS TCK 1 Kohm TRST 470 680 ohm A pull down is recommended but a pull up may be used Inputs to the Slot 1 connector from the 4 STPCLK 430 ohm 430 e SLP 150 330 ohm Outputs from the Slot 1 connector TDO 150 ohm THERMTRIP 150 220 ohm FERR 150 220 ohm Inte 440GX AGPset Design Guide 4 3 4 3 2 Debug Recommendations Inputs to the Slot 1 connector from system logic assuming a 14mA driver PWRGOOD 150 330 ohm INIT 150 330 ohm LINT O INTR 150 330 ohm e LINT 1 NMI 150 330 ohm IGNNE 150 330 ohm A20M 150 330 ohm Bi directional signal to from the Slot 1 connector e PICD O 150 ohm e PICD 1 150 ohm Inputs to the Slot 1 connector
90. gned for Intel Pentium I processors Systems should be capable of varying the system bus to processor core frequency ratio per the System Bus to Core Frequency Multiplier Configuration table of the Intel Pentium processor datasheet The Intel Pentium I processor uses the following signals to configure the internal clock multiplier ratio LINT O INTR IGNNE 20 LINT 1 NMI Follow the recommendations in this document to ensure that adequate hold times are met on the strapping signals Ensure the output of the strapping logic is a Vcc logic level for connection to the Slot 1 connector This can be accomplished using an open drain output driver with pull ups to Vcc 5 Please prepare for additional thermal margin for increases of 1 5W for higher performance or otherwise enhanced processor Motherboard designs targeted for system integrators should design to the Boxed Intel Pentium processor electrical mechanical and thermal specifications provided in the Intel Pentium processor datasheet most notably the required fan power header fan heatsink physical clearance on the motherboard Motherboard designs should incorporate a retention mechanism retention mechanism attach mount and heatsink support mounting holes and keep out areas for the Intel Pentium processor and boxed Intel Pentium processor 1 4 3 Transitioning from Intel 440BX AGPset to Intel 440GX AGPset Design 1 T
91. h Intel s Boot Block Flash Memory Order 292178 This document provides detailed information on flexible layouts Shown below are three of the reference layouts that Intel furnishes to customers These layouts are described in AP 623 and are available electronically Gerber and Postscript formats Note the small amount of extra board space needed to implement the dual footprint layouts Figure 3 5 Dual Footprint Flash Layouts 3 13 2 Rc E amp e e e un I oe en gt as cmm e A 9 i1 oe A oe 28FODIBX 321 PDIP to PBFOOZBC 40L PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40 Flash Design Considerations The Intel s flash devices GX BL BV B5 use an Address Transition Detection ATD mechanism to improve their performance When interfacing flash devices that employ the ATD mechanism the designer needs to make sure that the address transition time is not more than 10 ns while CE is active low If the address transition time is more than 10 ns invalid data can result on the data bus When flash devices are interfaced to the ISA bus they can be exposed to address transitions in excess of 10 ns Other types of interfacing considerations specific to flash can be referenced in Application Note AP 636 Prevent
92. he 82443GX supports 2GB using 128M or 256M memory technology The design guidelines for MAA14 and MAB14 are the same as MAA 13 and MAB 13 on the 82443BX 2 Intel 440GX AGPset supports 100 MHz system bus and 100 MHz SDRAM Memory only 3 There is no 3 DIMM support with the Intel 440GX AGPset Inte 440GX AGPset Design Guide 1 9 Introduction Inte 440GX AGPset Design Guide intel 2 Motherboard Design intel Motherboard Layout and Routing Guidelines Motherboard Layout and Routing Guidelines 2 2 1 Note This chapter describes layout and routing recommendations to insure a robust design Follow these guidelines as closely as possible Any deviations from the guidelines listed here should be simulated to insure adequate margin is still maintained in the design BGA Quadrant Assignment Intel assigned pins on the 82443GX to simplify routing and keep board fabrication costs down by permitting a motherboard to be routed in 4 layers Figure 2 1 shows the 4 signal quadrants of the 82443GX The component placement on the motherboard should be done with this general flow in mind This simplifies routing and minimizes the number of signals which must cross The individual signals within the respective groups have also been optimized to be routed using only 2 PCB layers The Intel 82443GX AGPset Datasheet contains a complete list of signals and Ball assignments Figure 2 1 Major Signal Sections 82443GX Top View
93. he diode and converts the drop into a temperature reading An external NPN transistor connected as a diode may be used on an external cable as well 3 18 2 LM79 Microprocessor System Hardware Monitor Consult the LM79 data sheet for the manufacturer s specifications and recommendations for using this device ISA bus interface signals allow access to internal status and control registers such as POST codes and RAM which stores A D information The LM79 internal registers are accessed by writing a register offset value to IO address 05h followed by a read of IO address 06h VID 4 0 These inputs allow storage of the voltage identification pin bits for Intel Pentium II processors to allow the BIOS to record voltage specification variations Faninputs can be used with system fans having tachometer outputs Inte 440GX AGPset Design Guide 3 33 3 18 3 Design Checklist Analog inputs feed inverting op amp stages useful for monitoring power supply regulation The LM79 is a 5V part however SMBus requires a 3 3V interface Level translation circuitry is required See the reference schematics for an example circuit CHASSIS INTRU FAN3 are pulled down and SMI_IN is pulled up with 10K ohm resistors The LM79 is connected to a programmable chip select on the PITX4E This assumes that the LM79 is tied to the X Bus See PIIX4 Datasheet for more details 82558B LOM Checklist Refer to Application Note 383 Intel 82558 LAN o
94. ic monolithic ceramic capacitor between the VCCRTC pin of the PIIX4 PIIXAE and the ground plane This capacitor s positive connection should not Intef 440GX AGPset Design Guide 3 31 3 17 Design Checklist be stubbed off the trace run and must be as close as possible to the PITX4 PITX4E The capacitor must be no further than 0 5 inch from the PITX4 PITX4E If a stub is required it should be kept to a few mm maximum length The ground connection should be made through a via to the ground plane with no or minimal trace between the capacitor pad and the via Place the battery 1K Ohm series current limit resistor and the common cathode isolation diode very close to the PITX4 PIIXAE If this is not possible place the common cathode diode and the Ohm resistor as close to the luF capacitor as possible Do not place these components between the capacitor and the PIIX4 The battery can be placed remotely from the PITX4 PITX4E On boards that have chassis intrusion utilizing external logic powered by the VCCRTC pin place the inverters as close to the common cathode diode as possible If this is not possible keep the trace run near the center of the board Keep the PITX4 PITX4E VCCRTC trace away from the board edge If this trace must run from opposite ends of the board keep the trace run towards the board center away from the board edge where contact could be made by people and equipment that handle the board Recommend
95. ified 2 7 3V 5V Design Considerations Following are general layout guidelines for the Intel s Smart Voltage S mart 5 boot block flash memory 2 4Mbit BV B5 in 3V or 5V designs Connect 2 7V 3V or 5V to and connect 5V or 12V to Vpp program erase levels for BV devices e Connect 5V only to Vcc and connect 5V 12V to Vpp program erase levels for B5 devices e If adding a switch on VPP for write protection switch to GND instead of VCC Connect WP to Vcc GND or a general purpose output GPO x control signal This pin should not be left floating WP pin replaces a DU pin and is used in conjunction with the Vpp and RP pins as detailed in the table below to control write protection of the boot block Inte 440GX AGPset Design Guide 3 26 Design Checklist WP pin not available on 8 Mbit 44 lead PSOP In this package treat as if the WP pin is internally tied low effectively eliminating the last row of the table below Use either A16 or A17 inversion for both the 2Mbit or 4Mbit to differentiate between recovery and normal modes If migrating a BV design to the lower cost B5 device Application Brief AB 65 Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash is available Order 292194 Table 3 13 Flash Vpp Recommendations VPP RP WP Write Protection VIL X X All Blocks Locked Programming 2 VPPLK VIL X All Blocks Locked All operations 2 VPPLK VHH X All Blocks Unlocked All o
96. ign Checklist 3 23 Layout Checklist 3 23 1 Routing and Board Fabrication 8 2 Support Is the Vcccogg trace power plane sufficient to ensure Vcccogg meets specification See the Intel Pentium II Datasheet for trace power plane resistance and length requirements should be routed with at least a 50 mil 1 25mm wide trace Veer traces should be isolated to minimize the chance of cross talk Vcccogg from the voltage regulator to Slot 1 should be an island as opposed to a trace Decoupling capacitor traces should be as short and wide as possible signals should follow the layout guidelines see AP 524 Intel Pentium Pro Processor GTL Layout Guidelines for further information If the recommendations are not followed simulations should be been run using the actual layout GTL lines should be spaced as far apart as possible at least 10 mils Running signals closer together 5 mils for less than 1 2 5cm is acceptable There should be no CMOS TTL signals running parallel to GTL signals If they must run in parallel separate them on different layers with a well decoupled power or ground plane If they must run parallel on the same layer then separate the traces by a minimum of 25 mils Proper operation of the IDE circuit depends on the total length of the IDE bus The total signal length from the IDE drivers pins to the end of the IDE cables should not exceed 18 Therefore the PI
97. ime Specs 2 18 Driver Receiver Titight min Titight max Inte Pentium II processor AGPset 0 36 2 13 Inte Pentium AGPset processor 0 37 1 76 Inte Pentium processor Inte Pentium 1 23 2 39 processor Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines AGP Layout and Routing Guidelines For the definition of AGP Interface functionality protocols rules and signaling mechanisms as well as the platform level aspects of AGP functionality refer to the latest AGP Interface Specification rev 1 0 and the AGP Platform Design Guide These documents focus only on specific Intel 440GX AGPset platform recommendations for AGP interface In this document the term data refers to AD 31 0 C BE 3 0 and SAB 7 0 The term strobe refers to AD_STB 1 0 and SB_STB When the term data is used it is referring to one of three groups of data as seen in Table 2 12 When the term strobe is used it is referring to one of the three strobes as it relates to the data in its associated group Table 2 12 Data and Associated Strobe 2 8 1 Data Associated Strobe AD 15 0 and C BE 1 0 AD_STBO AD 31 16 and 3 2 AD STB1 SBA 7 0 SB STB AGP Connector Up Option Layout Guidelines The maximum line length is dependent on the routing rules used on the motherboard These routing rules were created to give freedom for designs by ma
98. indows 2 16 Ringback Guidelines at the Intel Pentium II Processor Edge Fingers 2 16 Intel Pentium II Processor and Intel 440GX AGPset System Timing Equations sse eene 2 17 Intel Pentium II Processor and Intel 440GX AGPset System Timing 2 17 Intel Pentium II Processor and Intel 440GX AGPset 100 MHz Timing 2 18 Recommended 100 MHz System Timing 2 18 Recommended 100 MHz System Flight Time Specs 2 18 Data and Associated 5 2 19 Source Synchronous Motherboard Recommendations 2 20 Control Signal Line Length Recommendations 2 20 Source Synchronous Motherboard Recommendations 2 21 Control Signal Line Length Recommendations 2 21 MDx lines Reference Planes Routing ee 2 23 FET Switch DQ Route Example 2 25 Motherboard Model SRAS 4 5 2 28 Motherboard Model SCAS 4 5 2 28 Motherboard Model SCAS Bst 4 5 2 28 Motherboard Model WE 4 5
99. ines refer to the Pin Description section of the PITX4E datasheet The circuitry can be shared between 82443GX and the PITXAE If the circuitry is placed close to the PIIX4E then ensure that an extra luF capacitor is placed on the pin of the 82443GX STR support For systems implementing STR support a separate circuit must be used for each of the two devices since the PITX4E Core and the 82443GX Host Bridge should be supplied by the different power planes No STR support The V pg circuitry can be shared between 82443GX and the If the circuitry is placed close to the PITX4E then ensure that an extra luF capacitor is placed on the Vg gg pin of the 82443GX Use a Schottky diode in the circuit for a minimum voltage drop from VCC3 to VREF because there is an internal diode in parallel to the Schottky diode that does not have high current capability The Schottky diode will begin to conduct first therefore carrying the high current Voer can be tied to in a non 5V tolerant system Tie Vss and Vss USB to ground Table 3 9 PIIX4E PWR 8 GND 3 8 VCC VCC RTC VCC SUS VCC USB VSS USB VSS E9 F15 L16 N16 K5 J5 D10 L9 L12 E11 G6 R16 E7 M9 M12 E12 P15 E13 E16 R6 J9 J12 F5 R7 K9 K12 F6 R15 F14 T6 PCI Bus Signals A specific board sensitivity has been identified that may result in a low going glitch on a deasserted PC
100. ing BIOS Failures Using Intel s Boot Block Flash Memory Order 292192 on WWW Inte 440GX AGPset Design Guide 3 25 Design Checklist intel Following are general layout guidelines for using the Intel s boot block flash memories 28F001GX 28F002BC in the system Ifadding a switch on VPP for write protection switch to GND instead of VCC e Connect the DU pin of the 2Mbit devices to GND if anticipating to use the Intel SmartVoltage boot block flash memory family in the future e Use A16 inversion for 1Mbit devices and A17 inversion for 2Mbit devices to differentiate between recovery and normal modes For systems needing a 1Mb to 2Mb upgrade path A16 can be used for both devices alleviating the need for a board redesign Use a 0 01 mf 0 1mf ceramic capacitor connected between each and GND and between its Vpp and GND These high frequency inherently low inductance capacitors should be placed as close as possible to the package leads Figure 3 6 illustrates the recommended layout for using Intel s flash devices in desktop designs Figure 3 6 nterfacing Intel s Flash with PIIX4E in Desktop XD 7 0 12V 1 SD 7 0 a Ms 12V Vcc XDIR 1Mbit 2Mbit 13 1 Flash 1 12 RP PIIX4E 1Mbit uses SA16 3 2Mbit uses SA17 Vcc SA16 SA17 E MEMW ES MEMR 1 BIOSCS Mode Ji J2 OO Program 1 2 1 2 Normal 2 3 PnP 1 2 2 3 Non PnP 2 3 x Simpl
101. ing and topology recommendations are included in this section The heart of the methodology is structured around extensive simulations and analysis prior to board layout This represents a significant departure from traditional design methods The pre layout simulations provide a detailed picture of the working solution space for the design By basing the board layout guidelines on the solution space the need to iterate between layout and post layout simulation is minimized The methodology includes specific recommendations for analytical techniques and simulation conditions Following layout simulation with the extracted design database is used to verify that the design meets flight time and signal quality requirements prior to building hardware Finally validation verifies that the system meets 100 MHz timing and signal quality requirements with actual hardware Inte 440GX AGPset Design Guide 2 11 Motherboard Layout and Routing Guidelines intel 5 Figure 2 12 GTL Design Process Establish System Performance Requirements Timing Analysis Define Topologies Perform Pre Layout Simulations Sensitivity Analysis Define Routing Rules Place amp Route Board Perform Post Layout Simulations Verification Requirements Validate Design 2 3 8 Performance Requirements Prior to performing interconnect simulations establish the minimum and maximum flight time requirements Setup and hold
102. intel Intel 440GX AGPset Design Guide March 1999 Order Number 290651 001 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Inte 440GX AGPset may contain design defects or errors which may cause the products to deviate from published specifications Current characterized errata are available on request 12C is a two wire communications bus protocol developed by Philips SMBus is a subset of the bus protocol and was developed by Intel Implementations of the PC bus protocol or the SMBus bus protocol may require licenses from various entities including Philips Electronics N V
103. k Some of the control signals require pull up resistors to be installed on the motherboard AGP signals must be pulled up to VCC3 3 using 8 2K to 10K pull up resistors refer to Section 3 5 1 82443GX Interface on page 3 10 Pull up resistors should be discrete resistors as resistor packs will need longer stub lengths and may break timing The stub to these pull up resistors needs to be controlled The maximum stub length on a strobe trace is lt 0 1 inch The maximum stub trace length on all other traces is lt 0 5 inch On board AGP Compliant Device Down Option Layout Guidelines Routing guidelines for the device down option are very similar to those when the device is up Some modifications need to be made when placing the graphics device on the motherboard due to the various trace spacing Inte 440GX AGPset Design Guide intel Motherboard Layout and Routing Guidelines 5 Figure 2 15 On board AGP Compliant Device Layout Guidelines Always 1 2 Strobe Routing AGP Compliant Graphics 1 0 4 5 1 1 Data Routing Device 82443GX 1 12 1 2 Data Routing For trace lengths that are between 1 0 inch and 4 5 inches a 1 1 trace spacing is recommended for data lines The strobe requires a 1 2 trace spacing This is for designs that require less than 4 5 inches between the AGP device and the AGP target Longer lines have more crosstalk Therefore to mai
104. king trade offs between signal coupling trace spacing and line lengths These routing rules are divided by trace spacing In 1 1 spacing the distance between the traces air gap is the same as the width of the trace In 1 2 spacing the distance between the traces is twice the width of the trace Figure 2 14 AGP Connector Layout Guidelines Always 1 2 Strobe Routing AGP Compliant Graphics Device 1 0 4 5 1 1 Data Routing AGP Signal Bundle 82443CX 4 5 9 5 1 2 Data Routing AGP Connector For trace lengths that are between 1 0 inch and 4 5 inches a 1 1 trace spacing is recommended for data lines The strobe requires a 1 2 trace spacing This is for designs that require less than 4 5 inches between the AGP connector and the AGP target Longer lines have more crosstalk Therefore to maintain skew longer line lengths require a greater amount of spacing between traces For line lengths greater than 4 5 and less than 9 5 1 2 routing is recommended for all data lines as well as the strobes For all designs the line length mismatch must be less than 0 5 and the strobe must be the longest signal of the group Intef 440GX AGPset Design Guide 2 19 Motherboard Layout and Routing Guidelines intel o It is always best to reduce the line length mismatch wherever possible to insure added margin It is also best to separate the traces by as much as possible to reduce the amount of trace to trace co
105. l Pentium II processor substrate There is no termination present at the other end of the network Due to the lack of termination SET exhibits much more ringback than the dual terminated topology Extra care is required in SET simulations to make sure that the ringback specs are met under the worst case signal quality conditions In addition since there is only one pull up resistor per net the rising edge response is substantially degraded when using slow corner buffers This effect manifests itself as a degraded flight time which results in a reduced maximum trace length that meets the 100 MHz timing requirements This loss of design flexibility must be carefully weighed against the cost savings from removing the resistors Figure 2 10 Topology for Single Processor Designs With Single End Termination SET 2 3 5 2 L1 AGPset SET Trace Length Requirements Intel has performed sensitivity analysis on the SET topology The required trace lengths for operation at 100 MHz with the SET topology are based on the sensitivity analysis results and are listed in Table 2 3 Intel s SET simulations were performed assuming a four layer system board so that all traces used the microstrip propagation velocity range The slower propagation of stripline transmission line structures is not included in the recommendations of Table 2 3 Table 2 3 SET Trace Length Requirements Trace Minimum Length Maximum Length 1 1 50 4 0
106. lock Driver nennen 5 3 Power Management Component 5 3 FET Switch Vendors 5 3 Intel 440GX AGPset Design Guide Revision History Date Revision Description 3 99 001 Initial Release Intel 440GX AGPset Design Guide Intel 440GX AGPset Design Guide intel Introduction intel Introduction Introduction 1 1 1 Note This document provides design guidelines for developing Intel Pentium II processor Intel 440GX AGPset based systems Motherboard and memory subsystem design guidelines are covered Special design recommendations and concerns are presented Likely design issues have been identified and included here in a checklist format to alleviate problems during the debug phase One reference board design is presented Dual Processor DP 4 DIMM design These designs use the Intel Pentium II processor and Inte 440GX AGPset consisting of the 82443GX Host Bridge and the 82371EB PIIXAE The Intel Pentium II processor may be installed in a Slot 1 connector The Intel Pentium II processor will also be offered as an Intel boxed processor intended for system integrators who build systems from motherboards and other components Some hints for early debug problems are also included About This Design Guide This document is intende
107. mended trace lengths for dual processor designs are summarized in Table 2 2 Intel s simulations have shown that it is desirable to control the amount of imbalance in the network to meet ringback specifications at the Intel Pentium processor when the Intel 440GX AGPset drives This control is reflected in the recommendations of Table 2 2 Recommended Trace Lengths for Dual Processor Designs Trace Minimum Length Maximum Length L3 0 50 1 50 L41 1 50 4 00 L5 L4 1 00 but L4 L5 must be at least 4 00 L4 1 00 but not greater than 5 00 NOTES 1 14 amp L5 are interchangeable 2 It is possible to find working solutions outside the recommendations of Table 2 2 as the solution space plot show Intel strongly recommends that any traces that fall outside the recommended lengths be simulated to ensure they meeting timing and signal quality specs Single Processor Systems Single End Termination SET Set Network Topology and Conditions Removal of the termination resistors from the system board can reduce system cost at the expense of increased ringing and reduced solution space Intel has simulated this topology known as single end termination SET and found that it can work However the topology has some limitations which are discussed below Intef 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines In the SET topology the only termination is on the Inte
108. mination is required for the SDRAM clocks between the CKBF and the DIMMs DCLKO from the 82443GX to the CKBF should have a 22 ohm series resistor placed at the 82443GX and a 47 ohm series resistor placed at the This has been shown in simulations to improve the signal integrity of this signal Check with your clock vendor and the reference schematics for special layout and decoupling considerations The reference schematics implement an LC filter on the supply pins to reduce noise 3 4 3 GCKE and DCLKWR Connection See the diagram below for implementation of the 16 bit flip flop for CKE generation for 4 DIMMs GCKE trace length from the 82443GX to the flip flop is recommended to be 1 MIN to 4 MAX CKE trace lengths from the flip flop to the DIMMS is recommended to be 3 Figure 3 2 GCKE amp DCLKWR Connections GND CKBF TT NA 9 1 EN 2 EN C1 DCLKWR dd c2 NC 22 101 101 102 102 1D3 1D4 1D3 103 CKE6 1D4 104 0 105 106 20pF 1D5 1Q5 CKE5 82443GX 108 1081407 108 1D7 107 CKE4 V 1D8 74LVCH16374 108 2D1 2D2 2D1 201 CKE3 Clock signals fed back into 82443GX and 2D2 2Q2 2D3 2D4 D FF must T off with equal trace length 303 243 SCC KER and as close as possible to the 82443GX and 2D4 204 2D5 206 2D5 205
109. must be positioned within close proximity to the Slot 1 connector The Slot 1 connector signal SLOTOCC Pin B101 is a ground on the Slot 1 processor The presence of a CPU core can be determined from a combination of non zero VID signals all ones designates No Core and if the state of SLOTOCC is low ITPREQ 1 0 ITPRDY 1 0 can individually be hooked to either CPU The ITP inf file must match the connections DBRESET ITP Reset signal requires a 240 ohm pull up to VCC3 Intef 440GX AGPset Design Guide 3 6 Design Checklist 3 3 4 Uni Processor UP Slot 1 Checklist A UP system must connect BREQO of the Slot 1 connector to the 82443GX s BREQO signal This will assign an agent ID of 0 to the processor BREQ1 on the Slot 1 connector is left as a no connect For a UP design one set of GTL termination resistors 56 ohm are recommended on the motherboard dual ended termination The second set of terminations are provided on the Intel Pentium processor Single ended termination processor termination only may be achieved provided the trace lengths adhere to the very restrictive lengths given in the layout guidelines FRCERR may be left as a no connect for a UP design On board termination resistors are not required since they are provided on the Intel Pentium II processor 3 3 5 Dual Processor DP Slot 1 Checklist A DP system must cross connect BREQ 1 0 of the Slot 1 connector to the 82443GX s B
110. n Motherboard Design Guide for recommended PHY conformance testing i e IEEE testing and additional LOM design details The GOOD circuitry shown in Ap Note 383 should be implemented if the power supply dose not provide this signal Additional logic is needed to ensure that at least 4 clock cycles occur between ALTRST and ISOLATE assertion The distance between Magnetics i e Cat 3 or Cat 5 wire and RJ 45 connector should be kept to less than one inch Symmetrical 100 ohm traces should be used differential impedance for TDP TDN and RDP RDN The 82558 requires decoupling on the power pins At minimum 3 capacitors 2 x 0 1uF and 1 x 4 7uF should be implemented on each side High speed traces between the 82558 to magnetic or magnetic to RJ45 should be routed between layers to protect from EMI Pull up resistors and values are recommended for the following pins Pin Number Pin Name Resistor Value Comment 15 ZREF 10K 5 Required in both A and B stepping designs Pull down resistors and values are recommended for the following pins Pin Number Pin Name Resistor Value Comment 30 TEST 1K 5 153 FLD4 10K 5 Not required for B stepping designs 154 FLD3 10K 5 Not required for B stepping designs 171 RDP 49 9 1 172 RDN 49 9 1 180 VREF 220 5 181 RBIAS10 768 1 182 RBIAS100 634 1 187 TDN 49 9 1 204 AUXPWR 220 5
111. nal override could be used Also connect to optional LM79 Table 3 2 GND amp Power Pin Definition GND VcCconE Vtt 1 5V VCC3 3 3V Reserved NC Vcc 5V A2 A62 B13 B89 A1 B113 A16 B109 A6 A66 B17 B93 A3 B117 A47 A10 A70 B25 B97 B5 B121 A88 14 A74 B29 B105 B9 A113 A18 A78 B33 A116 A22 A82 B37 B12 A26 A86 B45 B20 A30 A90 B49 B112 A34 A94 B53 A38 A98 B57 A42 A102 B65 A46 A106 B69 A50 A110 B73 A54 A114 B77 A58 A118 B85 Inte 440GX AGPset Design Guide 3 4 intel Design Checklist 3 3 2 Intel Pentium II Processor Clocks Include a circuit for the system bus clock to core frequency ratio to the processor The ratio should be configurable as opposed to hard wired The bus frequency select straps will be latched on the rising edge of CRESET CRESET is used as the selection signal for muxing A20M f IGNNE INTR and NMI with the processor bus core frequency selection jumpers A 7244 buffer maybe used as a mux The outputs of the 244 device are fed to open collector buffers for voltage translation to the CPU See the reference board schematics for specific implementation PICCLK must be driven by a clock even if an I O APIC is not being used This clock can be as high as 33 3 MHz in a UP system A DP system utilizing Intel s I O APIC 82093AA has a maximum PICCLK frequency of 16 666 MHz 3 3 3 Intel Pentium II Processor
112. nals Default values provided by the internal pull up or pull down resistors can be overridden by an external resistor When AGP is disabled all AGP signals are tri stated and isolated They do not need external pull up resistors The AGP signals are PIPE SBA 7 0 RBF ST 2 0 GADSTBA GADSTBB SBSTB GFRAME GIRDY GTRDY GSTOP GDEVSEL GREQ GGNT GAD 31 0 FC BE 3 0 GPAR When AGP is disabled tie AGP_Vref to ground Inte 440GX AGPset Design Guide 3 13 Design Checklist intel 3 6 Intel 440GX AGPset Memory Interface 3 6 1 SDRAM Connections Table 3 6 SDRAM Connectivity 82443GX Pins Connection DIMM Pins Pin Function CKBF buffer outputs DCLK x y CK 3 0 4 DCLKs per DIMM Clock CS A 7 0 amp S 1 0 2 CS per DIMM Chip Select CS_B 7 0 S 3 2 2 CS per DIMM Chip Select GND A13 Address MAx 9 0 MAx10 A 10 0 Address MAx11 BAO Address Max12 BA1 Address MAA13 MAB13 11 Address MAA14 MAB14 A12 Address MDx 63 0 from FET MD 63 0 NO FET 7 0 CB 7 0 Error Checking and Correction ne SA 2 0 SMBus Address SMBDATA SDA SMBus Data SMBCLK SCL SMBus Clock SCASx CAS SDRAM Column Address Select SRASx RAS SDRAM Row Address Select WEx WEO Write Enable NOTES T Some of the pin ranges above are dependent on which DIMM is being reviewed x and y indicate signal copies 2 MA
113. nd the air intake that may preheat the air flowing into the fan heatsink e Ifa system fan other than the power supply fan is used have all recirculation paths been eliminated What is the air flow through the PSU system fan What is the maximum ambient operation temperature of the system 3 21 Mechanicals For the Intel Pentium II processor The physical space requirements of the processor must be met See the Intel Pentium Processor Datasheet for details For the Intel Pentium II processor The physical space requirements of your heat sink must be met For the Boxed processor The physical space requirements of the Boxed Intel Pentium Processor processor fan heatsink must be met See the Intel Pentium II Processor Datasheet for details Inte 440GX AGPset Design Guide 3 36 intel Design Checklist 3 21 1 Design Considerations The Intel Pentium II processor retention mechanism retention mechanism attach mount and heat sink support is an optional support structure for retaining the Slot 1 processor in the system during shock and vibration situations If these Intel enabled retention solutions are used the motherboard keep out zones and mounting hole requirements must be met See the Intel Pentium II Datasheet for details The Boxed Intel Pentium II processor requires the implementation of the heatsink support holes for the heatsink support structure as defined in the Intel Pe
114. non disclosure agreement required to receive the LAT In Target Probe ITP The ITP565 provides a software debug capability allowing the setting clearing of hardware software breakpoints assembly disassembly of code display modification of the processor register set display modification of system memory display modification of I O space and includes a macro language for custom debug procedure creation etc Contact your local Field Sales representative for availability of this tool from Intel Intef 440GX AGPset Design Guide 4 1 4 2 3 4 2 4 4 2 5 4 3 4 3 1 Note Debug Recommendations Contact your local Intel Field Sales representative to complete the proper software license agreement and non disclosure agreement required to receive the ITP Bus Functional Model BFM A bus functional model for the Intel Pentium II processor system bus is available from third party vendors and requires a special non disclosure agreement Contact your local Intel Field Sales representative for information on the bus functional model vendors and to complete the appropriate non disclosure agreements I O Buffer Models IBIS Models are available from Intel for Intel Pentium II processor QUAD only IBIS models TBD 82443GX IBIS Models PIIX4E PCI ISA IDE Xcelerator IBIS Models Contact your local Intel Field Sales representative for a copy of these models and to complete the appropriate non disclosure agreements FLO
115. ns 3 25 3 14 System and Test Signals 3 28 3 15 Power Management 8 5 3 28 3 15 1 Power Button 3 30 3 16 Miscellaneous ciini ii 3 31 3 10 82093AA IOAPIQ de ee glean 3 32 3 18 Manageability 5 3 33 3 18 1 Max1617 Temperature 3 33 3 18 2 LM79 Microprocessor System Hardware Monitor 3 33 3 18 3 82558B LOM Checklist essen 3 34 3 18 4 Wake On LAN WOL Header sse 3 35 3 19 Software BIOS qe iv a acia ae dde 3 35 3 19 1 USB and Multi processor BIOS 3 35 3 19 2 Design 3 36 3 20 Thermals Cooling Solutions 3 36 3 20 1 Design 3 36 3 21 Mechanical iria pela daar ias eaten deed 3 36 3 21 1 Design 3 37 3 22 lia Hate MER E ees 3 37 3 22 1 Design 3 37 3 23 Layout Checklist icta perte rl t rte ER eR 3 38 3 23 1 Routing and Board Fabrication 3 38 3 23 2 Design Consideration
116. ntain skew longer line lengths require a greater amount of spacing between traces For line lengths greater than 4 5 and less than 12 0 1 2 routing is recommended for all data lines and the strobes For all designs the line length mismatch must be less than 0 5 and the strobe must be the longest signal of the group In all cases it is best to reduce the line length mismatch wherever possible to insure added margin It is also best to separate the traces by as much as possible to reduce the amount of trace to trace coupling Table 2 15 Source Synchronous Motherboard Recommendations Width Space Trace Line Length Line Length Matching 1 1 Data 1 2 Strobe Data Strobe 1 0 in line length 4 5 in 0 5 in strobe longest trace 1 2 Data Strobe 1 0 in line length 12 0 in 0 5 in strobe longest trace The clock lines on the motherboard can couple with other traces It is recommended that the clock spacing air gap be at least two times the trace width to any other traces It is also strongly recommended that the clock spacing be at least four times the trace width to any strobes The clock lines on the motherboard need to be simulated to determine the their proper line length The motherboard needs to be designed to the type of clock driver that is being used and motherboard trace topology These clocks need to meet the loading of the receiving device as well as the add in trace length Additionally
117. ntium II Datasheet to properly support the Boxed Intel Pentium II processor fan heatsink 3 22 Electricals 3 22 1 Design Considerations It is recommended that simulations be performed on the GTL bus to ensure that proper bus timings and signal integrity are met especially if the layout guideline recommendations in this document are not followed It is recommended that simulations be performed to ensure proper timings and signal integrity is met especially if the non GTL CMOS layout guideline recommendations in this document are not followed Verify the voltage range and tolerance of your VRM or onboard regulator adequately cover the Veccorg requirements of the Slot 1 processor s is supported Verify the maximum current value your or on board regulator can support at This should meet the value specified by the VRM 8 2 DC DC Converter Specification Verify the voltage tolerance of your on board regulator at Vccc ogg This should meet the value specified by the VRM 8 2 DC DC Converter Specification Adequate 5V and or 3 3V decoupling should be provided for all components Vrer for the AGPset should be decoupled to VTT with 0 001 mF capacitors at each voltage divider It should be decoupled to ground to ensure an even better solution It is recommended that AC DC analysis be performed to determine proper pull up and pull down values Inte 440GX AGPset Design Guide 3 37 intel Des
118. ohm pull up to VCC3 Connect to SIO REFRESH Connected to ISA slots 1K ohm pull up to VCC REQ C A GPI 4 2 8 2K ohm pull up to VCC3 REQ 3 0 to corresponding REQ 3 0 signals on the Host Bridge 443GX and Cl connectors 8 2K ohm pull up to VCC RI GPI12 Connected to AGP connector AGP_PME pin 48 8 2K ohm pull up to 3VSB RSMRST From ATX connector buffer delay circuitry RSTDRV Connect to Ultra I O ISA slots and IDE through a Schmitt trigger RTCALE GPO25 No connect RTCCS GPO24 No connect RTCX1 Connect to RTC crystal RTCX2 Connect to RTC crystal SA 0 19 C d to ISA slots Ultra I O Flash LM79 8 2K ohm pull up to VCC DP onnected to IOAPIC SBHE Connect to ISA slots SCS1 Connected to IDE connector through 33 ohm series resistor SCS3 Connected to IDE connector through 33 ohm series resistor SD 0 15 Connected to ISA slots Ultra I O LM79 8 2K ohm pull up to VCC DP Connected to IOAPIC SDA 2 0 Connected to IDE connector through 33 ohm series resistors SDDACK Connected to IDE connector through 33 ohm series resistor SDD 15 0 Connected to IDE connector through 33 ohm series resistors It is recommended that PDD 7 have a 10K ohm pull down resistor SDIOR Connected to IDE connector through 33 ohm series resistor SDIOW Connected to IDE connector through 33 ohm series resistor SDREQ Connected to IDE through 33 ohm series resistor 5 6K ohm pull down on the PIIX4E side of the s
119. only pull up FLUSH 510 ohm Debug Logic Recommendations Debug Recommendations are intended to assist in the development of the Intel Pentium processor system and products utilizing it The following are strongly recommended for early prototype designs only Provide a push button reset circuit do not rely on power on reset from the power supply A push button reset usually results in more repeatable results when debugging initialization problems Include a Intel Pentium II processor debug port connector Intel cannot provide debug assistance without this connection See the Integration tools chapter of the processor datasheet for schematics and a signal checklist Be sure it is the proper 0 050 x 100 1 27mm x 4mm spacing connector Provide the capability to measure the processor s case temperature Tplate to ensure that the maximum temperature specification per processor Intel Pentium II Processor Datasheet Place an SMA style or similar coaxial connector on the power plane between the VRM Header or on board voltage regulator and Slot 1 connector so that power plane noise can be monitored on systems Note an SMA to BNC cable for an oscilloscope may be needed as well This component would only be placed during design evaluation For DP systems an empty Slot 1 connector is not allowed because one end of the bus termination would be missing The ITP565 requires a complete boundary scan chain For a DP s
120. ould be generated for the Intel Pentium II processor Veer 15 locally generated on the processor card Vtt must have adequate bulk decoupling based on the reaction time of the regulator used to generate Vtt It must provide for a current ramp of up to 8A uS while maintaining the voltage tolerance defined in the Intel Pentium II Processor datasheet If an on board voltage regulator is used instead of a Veccorg must have adequate bulk decoupling based on the reaction time of the regulator used to generate Veccorg It must provide for a current ramp of up to 30A uS while maintaining the VRM 8 2 DC DC Converter Specification The VID lines should have pull up resistors ONLY if they are required by the Voltage Regulator Module or on board regulator that you have chosen The pull up voltage used should be to the regulator input voltage 5V or 12V However if 12V is used a resistor divider should be utilized to lower the VID signal to CMOS TTL levels The VID signals may be used to detect the presence of a processor core pull up is not required unless the VID signals are Intef 440GX AGPset Design Guide 3 5 Design Checklist used by other logic requiring CMOS TTL logic levels The VID lines on the Slot 1 connector are 5V tolerant Vcc 45 should be provided to the Slot 1 signal Vcc pin B109 This power connection is not used by the Intel Pentium processor It is required for the Slot 1 EMT tool and may be required by fut
121. ould be pulled up with a 330K ohm resistor to 3 3V on the motherboard to prevent this line from floating when there is no add in card present 3 12 IDE Interface Table 3 12 Non PIIX4E IDE Pin Connection Pin 28 of IDE connector CSEL 470 ohm pull down Pin 19 2 22 24 26 30 40 of both ATA connectors Tie to Ground Pin 20 32 34of both ATA connectors Leave as a NC Support Cable Select CSEL is a PC97 requirement The state of the cable select pin determines the master slave configuration of the hard drive at the end of the cable Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15 Layout Proper operation of the IDE circuit depends on the total length of the IDE bus The total signal length from the IDE drivers to the end of the IDE cables should not exceed 18 Therefore the PIIX4E should be located at close as possible to the ATA connectors to allow the IDE cable to be as long as possible Use ISA reset signal RSTDRV from PIIXAE through a Schmitt trigger for RESET signals IDEACTP and IDEACTS each need a 10K ohm approximate pull up resistor to Vcc There is no internal pull up or down on PDD7 or SDD7 of the The ATA3 specification recommends a 10K ohm pull down resistor on DD7 Devices shall not have a pull up resistor on DD7 It is recommended that a host have a 10K ohm pull down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at
122. ound plane should not be split on the ground plane layer If a signal must be routed for a short distance on a power plane then it should be routed on a VCC plane not the ground plane Keep vias for decoupling capacitors as close to the capacitor pads as possible Routing Guidelines This section lists guidelines to be followed when routing the signal traces for the board design The order of which signals are routed first and last will vary from designer to designer Some designers prefer routing all of the clock signals first while others prefer routing all of the high speed bus signals first Either order can be used as long as the guidelines listed here are followed If the guidelines listed here are not followed it is very important that your design is simulated especially on the GTL signals Even when the guidelines are followed it is still a good idea to simulate as many signals as possible for proper signal integrity flight time and cross talk Inte 440GX AGPset Design Guide 2 5 Motherboard Layout and Routing Guidelines intel o 2 3 1 2 3 2 2 3 3 2 3 3 1 GTL Description is the electrical bus technology used for the Intel Pentium Pro processor and Intel Pentium II processor system bus GTL is a low output swing incident wave switching open drain bus with external pull up resistors that provide both the high logic level and termination at the end of the bus The complete GTL specification i
123. p AGPset T cina 2 Tota Eco min ES Teme Tien PCB T right max lt i Tew PCB T Ti min AGPset gt Troia gt T onus ab Tier ES T kew PCB Tik min T ight max Joyce co max T Trew 7 T zew PCB gt Ti Lad max ada T right min 2 Troia s Tons T kew T ew PCB odds Du i T CLK T gt Ti T The terms used in the equations are described in Table 2 8 Table 2 8 Intel Pentium II Processor and Intel 440GX AGPset System Timing Terms Intef 440GX AGPset Design Guide Term Description Toycle System cycle time Defined as the reciprocal of the frequency Minimum system flight time Flight time is defined Section 4 Debug Recommendations on flight min page 4 1 Maximum system flight time Flight time is defined Section 4 Debug Recommendations on flight max page 4 1 Maximum driver delay from input clock to output data Tco min Minimum driver delay from input clock to output data T Minimum setup time Defined as the time for which the input data must be valid prior to the input su clock T Minimum hold time Defined as the time for which the input data must remain valid after the input clock Clock generator skew Defined as the maximum delay variation between output clock signals skew CLK f
124. perations 2 VPPLK VIH VIL Boot Block Locked Programming 2 VPPLK VIH VIH All Blocks Unlocked All operations NOTES 1 is specified at 1 5V maximum 2 is specified at logic low 3 is specified at logic high 4 is specified at 12V15 Use SUSA to drive the flash RP pin into the deep power down mode when system is in the suspend states SUSA Alternative Use system POWEROK or POWERGOOD signal to drive flash RP to keep device in deep power down during power up only write protection For systems not needing power saving modes Connect BYTE to GND for byte wide mode operation if x16 device is used Use 0 01 mf 0 1mf ceramic capacitor connected between each Vcc and GND and between its Vpp and GND These high frequency inherently low inductance capacitors should be placed as close as possible to the package leads Add information on how BIOSCS elevates the need for control logic and GPO x control on WE Add information on ISA load consideration and the reduction of the X bus drivers control Figure 3 7 illustrates the recommended layout for Intel s flash devices in desktop designs Inte 440GX AGPset Design Guide 3 27 intel Figure 3 7 Design Checklist Interfacing Intel s Flash with PIIX4E in Desktop SD 7 0 45V SD 7 0 DQ 7 0 Vpp PIIX4E E 0 01uf s 2 4Mbit BV B5 Flash SUSA RP GP
125. r the case where two different steppings of Slot processors are installed This will allow both processors to have BIOS Updates applied 3 20 Thermals Cooling Solutions For the Intel Pentium II processor an adequate heat sink and air ventilation must be provided to ensure that the processor TPLATE specification documented in the datasheet is met See the Intel Pentium II Processor Power Distribution Guidelines and Intel Pentium II Processor Thermal Design Guidelines for thermal design information For the Boxed processor the system must have adequate air ventilation to ensure that the air intake temperature to the fan heatsink is less than the maximum allowable fan preheat temperature TPH at the system maximum ambient temperature measured 0 3 above the center of the fan See the Intel Pentium Processor Datasheet for the TPH Specification Verify that all major components including the 82443GX can be cooled the way they are placed Contact your local Intel Field Sales representative for the following Application Note FW82443B X FW82443GX PCI AGP Controller Application Note 2 Thermal Design Considerations This thermal application note contains thermal specifications thermal solutions and the thermal test methodology for the 82443GX component 3 20 1 Design Considerations Could anything block the air flow to or from the processor card I O cards etc Is there anything between the processor a
126. requirements determine the flight time bounds for the host bus The system contains multiple paths which must be considered Intel Pentium II processor driving an AGPset component e AGPset component driving Intel Pentium II processor Intel Pentium II processor driving a Intel Pentium II processor dual processor systems only 2 12 Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Section 2 7 Timing Analysis on page 2 17 describes the timing analysis for the 100 MHz host bus in more detail Table 2 4 provides recommended flight time specifications for single and dual Intel Pentium processor systems Flight times are measured at the Intel Pentium II processor edge fingers See the Pentium II Processor Developer s Manual order number 243502 Chapter 8 GTL Interface Specifications for information on GTL timing measurements and signal quality specifications Table 2 4 Recommended 100 MHz System Flight Time Specs 2 3 9 2 3 10 Driver Receiver Tilight min ns Tilight max ns Intel Pentium II processor AGPset 0 36 2 13 Intel 440GX AGPset Intel Pentium processor 0 37 1 76 Intel Pentium II processor Intel Pentium II processor 1 23 2 39 Topology Definition GTL is sensitive to transmission line stubs which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state GTL sign
127. roach will allow you to verify that the design is robust The second option is to subtract the simulated reference delay from the delay at the receiver The limitation of this option is that there may be 1 ns or more of uncertainty between the actual driver delay and the results from a simulation This approach is less accurate that the first option The final option is to simply use the measured delay from driver to receiver T measured to validate that the system meets the setup and hold requirements In this approach the sum of the driver delay and the flight time must fit within the valid window for setup and hold The timing requirements for satisfying the valid window are shown below Inte 440GX AGPset Design Guide 2 15 Motherboard Layout and Routing Guidelines intel 5 Table 2 5 System Timing Requirements for Validating Setup Hold Windows Driver Receiver Equation Pentium 11 processor AGPset coma 2 T zew PCB ste ia er lt Ty T Ts T os e T ies PCE 7 T Ve si Pentium AGPset processor 2 3 T ew T kew PCB Toss rM lt T Tu E T iw gt T spew PCB Bi 7 Tu a T aan Pentium Pentium 11 l uel gud e BL processor processor measured hold skew CLK skew PCB E lt E T spew CLK T sE 7 T uj 2 6 2 Signal Quality Measurement Signal integrity is speci
128. rocedures When using an ITP565 In Target Probe for the processor a common error is that the boundary scan chain order in the ITP565 INI input file is not correct Check the file to ensure that the scan chain connections on your motherboard match the order provided the tool in this file This file needs to change based on what components are in the boundary scan chain In DP systems the processor with PREQO and PRDYO is considered processor 0 even if it is not the first one in the chain Processor 0 should be placed in its proper place in the order TCK noise may limit ITP speed or cause functional problems Observe this signal with an oscilloscope The TCK speed may be changed from 10MHz to 1250Hz using the keyword TCLK value in the Debug Port section of the ITP565 INI file See the ITP HELP menu Changing the TCLK Signal Frequency for the valid values If you are having difficulty initializing the ITP562 try slowing TCK ITP macros are available for the Intel 440GX AGPset to assist in debugging your system A number of macros are provided e g utilities to read write any PCI configuration register a macro display POST codes and stop on a specified code macros to dump the 82443GX and PIIX4E register sets as well as processor specific registers etc TDO out of each processor should have a 150 Q pull up PICDO and PICD1 should each have a 1500 pull up IERR might be asserted during the APIC MP message generation if an in
129. rom the system clock generator T PCB skew Defined as the maximum delay variation between clock signals due to system board skew PCB variation and Intel 440GX AGPset loading variation Tiit Clock jitter Defined as the maximum edge to edge variation in a given clock signal Multi bit timing adjustment factor This term accounts for the additional delay that occurs in the La network when multiple data bits switch in the same cycle The adjustment factor includes such adj mechanisms as package and PCB crosstalk high inductance current return paths and simultaneous switching noise Tuna Minimum clock substrate delay Defined as the minimum adjustment factor that accounts for the clk min delay of the clock trace on the Pentium Il processor substrate T Minimum clock substrate delay Defined as the maximum adjustment factor that accounts for the clk max delay of the clock trace on the Pentium Il processor substrate 2 17 Motherboard Layout and Routing Guidelines intel 5 Table 2 9 Notice that the timing equations include an extra term to account for the delay due to routing of the BCLK trace on the processor substrate from the processor edge fingers and the processor core Adding the BCLK adjustment to the timing calculations between processor and chipset guarantees host clock synchronization between the AGPset and processor core The minimum and maximum values for this term are contained in Table 2 9 Component timings
130. rts an AGP interface The AGP interface can reach a maximum theoretical 532 Mbytes sec transfer rate Inte 440GX AGPset Design Guide 1 5 1 3 2 5 1 3 3 Introduction PCI Interface The 82443GX PCI interface is 33 MHz Revision 2 1 compliant and supports up to five external PCI bus masters in addition to the I O bridge PIIXAE System Clocking The 82443GX operates the system bus interface at 100 MHz PCI at 33 MHz and AGP at 66 133 MHz The 443GX clocking scheme uses an external clock synthesizer which produces reference clocks for the system bus and PCI interfaces The 82443GX produces a single 100 MHz SDRAM clock output which is fed to a 1 to 18 clock buffer to support 1 to 4 DIMMs PCI to ISA IDE Xcelerator PIIX4E The PCI to ISA IDE Xcelerator 4 is a multi function PCI device implementing a PCI to ISA bridge function a PCI IDE function a Universal Serial Bus host hub function and an Enhanced Power Management function As a PCI to ISA bridge the PIIX4E integrates many common I O functions found in ISA based PC systems a seven channel DMA Controller two 82C59 Interrupt Controllers an 8254 Timer Counter and a Real Time Clock In addition to Compatible transfers each DMA channel also supports Type F transfers The PITX4E contains full support for both PC PCI and Distributed DMA protocols implementing PCI based DMA The Interrupt Controller has Edge or Level sensitive programmable inputs and fully supports the use
131. s contained in the Pentium II processor databook The specification defines Termination voltage Termination resistance e Maximum output low voltage and output low current Output driver edge rate when driving the GTL reference load e Receiver high and low voltage level Vy and Vip Receiver reference voltage as a function of the termination voltage Receiver ringback tolerance Refer to the 100 MHz GTL layout Guidelines for the Pentium II Processor and Intel 440GX AGPset for more details GTL Layout Recommendations This section contains the layout recommendations for the GTL signals The layout recommendations are derived from pre layout simulations that Intel has run using the methodology described in Section 2 3 7 Design Methodology on page 2 11 Results from the pre layout simulations are included in this section See the Intel Pentium II Processor Specification Update for workarounds for any errata that may be present on the particular stepping of the processor used Single Processor Design Single Processor Network Topology and Conditions The recommended topology for single processor systems is shown in Figure 2 7 In addition to the termination resistor on the Pentium processor substrate a termination resistor is placed on the system board The recommended value for the termination resistor is 560 5 Figure 2 7 Recommended Topology for Single Proces
132. s for details If not connected to the PIIX4E pull down through a 100 ohm resistor at both 82443GX PIIX4E CPURST Connected to CPUs and ITP 240 ohm series resistor CRESET 10K ohm pull up to 3 3V Controls the mux for the CPU strapping signals CSA 5 0 Connect to DIMMs two to each CSA 7 6 f Connect CSA 7 6 to DIMM 3 CSB 5 0 Connect to DIMMs two to each CSB 7 6 Connect CSB 7 6 to DIMM 3 DBSY DRDY Connected to CPUs DCLKO Connected to CKBF 22 ohm series resistor placed next to 443GX and 47 ohm series resistor placed next to CKBF eee Driven by single clock from CKBF See Clock section DEFER Connected to CPUs DEVSEL 2 7K ohm pull up to 5V Connected to PCI bus DQMA 7 0 Connected to all DIMMs DQMB5 DQMB1 4 DIMM Connected to DIMM2 and DIMMS FRAME 2 7K ohm pull up to 5V Connected to PCI bus ra GC Connected to AGP connector GCLKIN Connected to GCLKOUT through 22 ohm resistor GCLKOUT Connected to AGP connector through 22 ohm series resistor Inte 440GX AGPset Design Guide 3 10 In tel Design Checklist Table 3 4 82443GX Connectivity Sheet 2 of 3 SIGNAL CONNECTION GADSTBA GADSTBB GDEVSEL GFRAME GGNT GIRDY GREQ GSTOP GTRDY 8 2K ohm pull ups to 3 3V Connected to AGP connector GPAR 100K ohm pull down required Connect to AGP connector GTLREFA G
133. s resistors on GCLKOUT and GCLKIN should be placed next to the driver GCLKOUT CRESET is used to control the reset values of A20M IGNNE LINT 1 0 and determine the ratio of core and bus frequencies This signal is delayed to provide the two BCLK hold requirement A 10K ohm pull up to 3 3V is recommended TESTIN should be pulled up to VCC3 3 with an 8 2K ohm resistor The internal pull up may prove to be sufficient however the first rev of boards should include the external pull up to be safe 3 5 2 82443GX GTL Bus Interface The Intel 440GX AGPset does not support the entire Intel Pentium processor GTL bus For a UP design on board termination resistors are recommended for the following signals HD 63 0 A 31 3 HREQ 4 0 RS 2 0 HTRDY BREQ 0 BNR BPRI DBSY DEFER DRDY ADS HIT HITM HLOCK CPURST The second set of terminations are provided on the Intel Pentium II processor The Intel 440GX AGPset does not support the entire Intel Pentium II processor GTL bus For a DP design on board termination resistors are NOT required for the following signals HD 63 0 A 31 3 HREQ 4 0 RS 2 0 HTRDY BREQ 0 BNR BPRI DBSY DEFER DRDY ADS HIT HITM HLOCK CPURST The second set of terminations are provided on the second Intel Pentium processor or terminator card An empty Slot 1 connector is not allowed 3 5 3 82443GX PCI Interface If boundary scan is not
134. sor Design Inte 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines 2 3 3 2 Single Processor Recommended Trace Lengths Single processor trace length recommendations are summarized in Table 2 1 The recommended lengths are derived from the parametric sweeps and Monte Carlo analysis described in the following section Table 2 1 Recommended Trace Lengths for Single Processor Design Trace Minimum Length Maximum Length L1 1 50 6 75 L3 0 00 1 50 L4 0 00 2 50 2 NOTE 1 Refer to the Intel Pentium II Processor Specification Update order number 243337 Specifically erratum 42 workaround L1 4 5 Intel strongly recommends running analog simulations using the available I O buffer models together with layout information extracted from your specific design Simulation will confirm that the design adheres to the guidelines Figure 2 8 Solution Space for Single Processor Design Based on Results of Parametric Inte 440GX AGPset Design Guide Sweeps L3 in L2 in Motherboard Layout and Routing Guidelines intel 2 3 4 2 3 4 1 Dual Processor Systems Dual Processor Network Topology and Conditions Figure 2 9 Recommended Topology for Dual Processor Design 2 3 4 2 Table 2 2 2 3 5 2 3 5 1 Dual Processor Recommended Trace Lengths The recom
135. sufficient pull up is used Watch out for incorrect clock voltages BCLK PICCLK are all Vcc 5 signals PICCLK must be driven even if APIC is not used The APIC bus executes MP initialization even in a uni processor system APIC may be disabled in BIOS for initial debug by clearing bit 11 in the APIC base MSR 1Bh Be sure boundary scan chains are properly reset using the TRST pin of each device in the debug port chain Intef 440GX AGPset Design Guide 4 5 Debug Recommendations The Global Descriptor Table GDT must be aligned The must be located a DWord boundary or else setting the PE bit and branching will cause a SHUTDOWN transaction The ITP pins command may be used to check reset configuration pin states Be aware however that observing pin state during reset will not reveal anything about the stability or timing of the configuration signals around the reset edge You can expect the following processor system bus activity after reset BNR stops toggling approximately 2 8 million BCLKs after the deassertion of RESET if BIST is not configured to run If BIST is configured to run BNR will continue to toggle until BIST completion After BNR stops toggling the PICD 1 0 signals begin the MP initialization to determine the bootstrap processor In a single processor boot two 21 cycle short messages are transmitted on the APIC Refer to the Intel Pentium Pro Family Developer s Man
136. th the Intel Pentium processor s system bus at 100 MHz Along with its Host to PCI bridge interface the 82443GX host bridge controller has been optimized with a 100 MHz SDRAM memory controller and data path The 82443GX also features the Accelerated Graphics Port AGP interface The 82443GX component includes the following functions and capabilities Support for single and dual Intel Pentium II processor configurations 64 bit GTL based system data bus Interface 32 bit system address bus support 64 72 bit main memory interface with optimized support for SDRAM 32 bit PCI bus interface with integrated PCI arbiter AGP interface with up to 133 MHz data transfer rate Extensive data buffering between all interfaces for high throughput and concurrent operations Figure 1 1 Intel Pentium II Processor Intel 440GX AGPset System Block Diagram Pentium Processor Pentium 11 Processor I Host Bus VMI Video Capture 82443GX Host Bridge Device 100 MHz Graphics Local Memory SDRAM Support PCI Slots 2IDEPots NG 82371 Le Ultra DMA 33 rE d PIIX4E AM PCI to ISA Bridge A ISA Bus System BIOS Sys blk vsd Intef 440GX AGPset Design Guide 1 4 1 3 2 1 1 3 2 2 1 3 2 3 Introduction Figure 1 1 shows a block diagram of a typical platform based on the Intel 440GX AGPset The 82443GX s
137. to 10 KQ pullup pulldown at end ofline 0 2 MAB12 0 5 MAB 11 9 only applies to straps DIMM Module 3 DIMM Module 4 2 9 3 4 DIMM Routing Guidelines NO FET Figure 2 27 Motherboard Model Data MDxx Lines 4 DIMMs No FET 82443GX DIMM Module 1 DIMM Module 2 DIMM Module 3 DIMM Module 4 NOTE 1 Route using lt 6 mil trace and gt 12 mil spacing Route on outer layers Trace impedance Z 60 80 ohms Trace velocity 1 6 2 2 ns ft 2 9 4 PCI Bus Routing Guidelines The 82443GX provides a PCI Bus interface that is compliant with the PCI Local Bus Specification The implementation is optimized for high performance data streaming when the 82443GX is acting as either the target or the initiator on the PCI bus For more information on the PCI Bus interface refer to the Intel 440GX AGPset Datasheet An Intel 440GX AGPset PCI Bus design is basically the same as the Intel 440BX AGPset The Intel 440GX AGPset supports 5 PCI Bus masters excluding the Intel 440GX AGPset and PIIX4B by the support of 5 PREQ and PGNT lines 2 30 Inte 440GX AGPset Design Guide intel Motherboard Layout and Routing Guidelines 5 Because of the specifics of an ATX layout it is recommended that the PIIX4E component is at the END of the PCI bus as shown in Figure 2 28 This insures proper termination of the PCI Bus signals Figure 2 28 PCI Bus Layout Example
138. ual Vol III The following fields are expected and all others are don t care Note that PICD 1 0 are active low so the pin electrical levels will be the complement of the numbers presented here Interrupt Vector Ox4N for the first cycle and Ox1N for the second cycle Where N is the processor number DM 0 D3 D0 1111 all including self shorthand Trigger Mode edge Level 0 deasserted Delivery Mode 000 fixed Inte 440GX AGPset Design Guide 4 6 intel Third Party Vendors intel Third Party Vendor Information Third Party Vendor Information 5 This design guide has been compiled to give an overview of important design considerations while providing sources for additional information This chapter includes information regarding various third party vendors who provide products to support the Intel 440GX AGPset The list of vendors can be used as a starting point for the designer Intel does not endorse any one vendor nor guarantee the availability or functionality of outside components Contact the manufacturer for specific information regarding performance availability pricing and compatibility 5 1 Processors Table 5 1 Slot 1 Connector Supplier Contact Phone AMP Incorporated Mike Mullen 717 592 2352 Framatome Connectors Leonard Dore 717 767 8006 Foxconn USA Julia Jiang 408 749 1228 x232 Hon Hai Precision Ind Co LTD Taiwan
139. uidelines The feedback clock trace length equals the standard clock motherboard trace length plus the card trace length Figure 2 31 AGP Clock Layout GCLKOUT GCLKIN Card Trace Net Trace Length Min Max Length 22 Ohm resistor AGP connector A 0 5 12 3 3 22 Ohm resistor 82443GX feedback 3 3 0 5 15 3 NA Note One driver The signal splits at the 82443GX each half of the trace goes through a 22 Ohm resistor and then to their respective loads If the graphics chip is down on the motherboard the trace length to the graphics chip and the feedback trace length to the 82443GX will both be the same length 2 34 Inte 440GX AGPset Design Guide intel Design Checklist intel Design Checklist Design Checklist 3 3 1 3 2 Overview The following checklist is intended to be used for schematic reviews of Intel 440GX AGPset desktop designs It does not represent the only way to design the system but provides recommendations based on the Intel 440GX AGPset reference platform Pull up and Pull down Resistor Values Pull up and pull down values are system dependent The appropriate value for your system can be determined from an AC DC analysis of the pull up voltage used the current drive capability of the output driver input leakage currents of all devices on the signal net the pull up voltage tolerance the pull up pull down resistor tolerance the inp
140. uit is also used to reduce the voltage going to the power supply fan thus decreasing its speed and quieting the system Pull up and Pull down Resistors 34 35 These pages show pull up and pull down resistors for PCI signals Slot 1 CMOS ISA and AGP signals Also shown are spare gates Decoupling Capacitors 36 37 Decoupling Caps 38 These pages show de coupling capacitance used in these schematics as well as the voltage dividers used to provide the GTL reference voltage Hardware system manager 39 The LM79 is a hardware system monitor It monitors voltage regulation fan RPM and stores POST codes The device can be accessed via the X Bus bus or through the PITX4E SMBus interface Note the voltage level translation circuitry between the 5 Volt LM79 and the rest of the 3 3 Volt SMBus Revision History 40 Changes made to the schematics are listed here underneath the revision where they first appeared and by page number Inte 440GX AGPset Design Guide
141. ule VRM 8 2 Pin AS formerly a reserved pin is now 12VIN Pin B3 formerly a reserved pin is now 5VIN ISHARE can be used in a DP design using the same manufacturer s VRM to share the current load between the two VRMs VRM 8 2 is modified from VRM 8 1 to provide up to 18A of ICC for future processors VID voltage identification pins from the processor will determine the Veccopg output of the VRM Intef 440GX AGPset Design Guide 3 7 Design Checklist intel 3 4 Intel 440GX AGPset Clocks 3 4 1 CK100 100 MHz Clock Synthesizer The system clock which provides 100 MHz to the processor and the Intel 440GX AGPset and the clocks for the APIC must be 2 5V Ifimplemented in the clock chip pin 28 when strapped low provides a spread spectrum modulation effect which may help reduce EMI The modulation will be down spread only meaning that the nominal 100 66 MHz frequencies will be modulated 0 25 to 0 5 below 100 66 While this may help EMI testing performance will be impacted Check with your clock vendor for availability of this feature SEL pins on CK100 can be used to select special functionality using 8 2K ohm pull ups to V Table 3 3 Processor Frequency Select SEL100 66 SEL1 SELO Function 0 0 0 Tri state 1 0 0 Test Mode 0 1 1 Active 66MHz 1 1 1 Active 100MHz e Unused clocks should be terminated to ground with 22 ohm resistors 22 ohm series resistors are recomm
142. up to 2 5V FLUSH UP 510 ohm pull up to 2 5V DP Connect CPUs and 510 ohm pull up FRCERR Leave as NC HIT Connect between CPUs and 82443GX HITM Connect between CPUs and 82443GX IERR Leave as NC IGNNE UP 330 ohm pull up to 2 5V Connected to bus frequency strapping circuit DP Connect CPUs bus frequency strapping unit and 330 ohm pull up to 2 5V INIT UP Connect to PIIX4E 330 ohm pull up to 2 5V DP Connect CPUs and PIIX4E 330 ohm pull up to 2 5V UP 150 ohm 330 ohm pull up 2 5 DP Connect CPUs 150 ohm 330 ohm pull LINT 1 0 up to 2 5V LOCK UP Connect to 82443GX DP Connect CPUs 82443GX PICCLK Connect to CK100 22 ohm series resistor UP 150 ohm pull up to 2 5V DP Connect CPUs and IOAPIC and 150 ohm pull up to PICD 1 0 25 PRDY 240 ohm series resistor to ITP PREQ Connected to ITP 330 ohm pull up to 2 5V PWRGOOD UP Requires 330 ohm pull up to 2 5V DP Connect between CPUs REQ 4 0 UP Connect to 82443GX DP Connect CPUs and 82443GX RESETH UP Connect to 82443GX 240 ohm series resistor to ITP DP Connect CPUs and ITP with 240 ohm series resistor RP Leave as NC RS 2 0 UP Connect to 82443GX DP Connect CPUs 82443GX RSP Leave as NC UP Tie to GND SLOTOCC DP Part PWRGD logic 8 2K ohm pull up to 3 3V SLP UP 150 ohm 330 ohm pull up to 2 5V Connect to PIIX4E DP Connect CPUs and PIIX4E with 150 ohm 330 ohm pull up to 2 5V UP Connect to PIIX4
143. upling Table 2 13 Source Synchronous Motherboard Recommendations Width Space Trace Line Length Line Length Matching 1 1 Data 1 2 Strobe Data Strobe 1 0 in lt line length lt 4 5 in 0 5 in strobe longest trace 1 2 Data Strobe 1 0 in lt line length lt 9 5 in 0 5 in strobe longest trace The clock lines on the motherboard can couple with other traces It is recommended that the clock spacing air gap be at least two times the trace width to any other traces It is also strongly recommended that the clock spacing be at least four times the trace width to any strobes The clock lines on the motherboard need to be simulated to determine the their proper line length The motherboard needs to be designed to the type of clock driver that is being used and motherboard trace topology These clocks need to meet the loading of the receiving device as well as the add in trace length Additionally control signals less than 8 5 inches can be routed 1 1 while control signals greater than 8 5 inches should be routed 1 2 Table 2 14 Control Signal Line Length Recommendations 2 8 2 2 20 Width Space Board Trace Line Length Pull up Stub Length 1 1 Motherboard Control signals 1 0 in lt line length lt 8 5 in lt 0 5 in Strobes lt 0 1in 1 2 Motherboard Control signals 1 0 in lt line length lt 10 0 in lt 0 5 in Strobes lt 0 1 1 2 1 4 to Strobe Motherboard Cloc
144. ure Boxed processors The JTAG port must be properly terminated even if it is not used See the Debug Recommendations for further information that may affect these resistor values The EMI pins of the Slot 1 connector pins B1 B41 B61 B81 and B100 should be connected to system or chassis ground through zero ohm resistors The determination to install these resistors is design dependent and can be determined through empirical methods TRST must be driven low during reset to all components with TRST pins Connecting a pull down resistor to TRST will accomplish the reset of the port If two Vtt regulators are used one at each end of the bus Intel recommends connecting the two regulator outputs together with a wide trace that runs the along the same basic path as the GTL signals beware of crosstalk should be generated at each AGPset component from this combined Vyr This is simply a recommendation to minimize the effects of noise See AP 523 Intel Pentium Pro Processor Power Distribution Guidelines for more information A single regulator may be used For a UP system a simplistic calculation for maximum worst case current is 5 0A This takes into consideration that some signals are not used by the Intel 440GX AGPset Motherboards planning to support the Boxed Intel Pentium II processor must provide a matched power header for the Boxed Intel Pentium II processor fan heatsink power cable connector The power header
145. ut high low voltage specifications the input timing specifications RC rise time etc Analysis should be done to determine the minimum maximum values that may be used on an individual signal Engineering judgment should be used to determine the optimal value This determination can include cost concerns commonality considerations manufacturing issues specifications and other considerations A simplistic DC calculation for a pull up value is Rmax MIN lLeakage MAX Ruin lo MAX Since Ij eakage MAX is normally very small Ryax may not be meaningful Ryax is also determined by the maximum allowable rise time The following calculation allows for t the maximum allowable rise time and C the total load capacitance in the circuit including input capacitance of the devices to be driven output capacitance of the driver and line capacitance This calculation yields the largest pull up resistor allowable to meet the rise time t A simplistic AC calculation for a pull up value is Rmax t C In 1 MIN Vecpy MIN Inte 440GX AGPset Design Guide 3 1 intel Design Checklist Figure 3 1 Pull up Resistor Example Vccpy MIN Ruax Va MIN laa MAX VCCpy MAX Ruin V MAX Io MAX 3 3 Intel Pentium Processor Checklist 3 3 1 Intel Pentium II Processor Table 3 1 Slot Connectivity Sheet 1 of 3
146. ute the VTT trace to all components on the system bus Be sure to include decoupling capacitors Guidelines for VTT distribution and decoupling are contained in Intel Pentium II Processor Power Distribution Guidelines Place resistor divider pairs for Vggp generation at the Intel 440GX AGPset component No Vrer generation is needed at the processor s is generated locally on the processor Be sure to include decoupling capacitors Guidelines for distribution and decoupling are contained in P Intel Pentium Processor Power Distribution Guidelines There are six GTL signals that can be driven by more than one agent simultaneously These signals may require extra attention during the layout and validation portions of the design When a signal is asserted driven low by two agents on the same clock edge the two falling wave fronts will meet at some point on the bus This can create a large undershoot followed by ringback which may violate the ringback specifications This wired OR situation should be simulated for the following signals AERR BERR BINIT BNR HITM Lossless simulations can overstate the amount of ringing on GTL signals Lossy simulations may help to make your results less pessimistic if ringing is a problem Intel has found the resistivity of copper in printed circuit board signal layers higher than the value of 0 662 Q mil in that has been published for annealed copper Int
147. ution Space Placement amp Layout Once the pre layout simulation is completed route the board using the solution space resulting from the sensitivity analysis Post Layout Simulation Following layout extract the traces and run simulations to verify that the layout meets timing and noise requirements A small amount of trace tuning may be required but experience at Intel has shown that sensitivity analysis dramatically reduces the amount of tuning required The post layout simulations should take into account the expected variation for all interconnect parameters For timing simulations use a of 2 3 VTT 2 for both the Intel Pentium II processor and Intel 440GX AGPset components Flight times measured from the Pentium II processor edge fingers to other system components use the standard flight time method Inte 440GX AGPset Design Guide 2 6 2 6 1 Motherboard Layout and Routing Guidelines Crosstalk and the Multi Bit Adjustment Factor Coupled lines should be included in the post layout simulations The flight times listed in Table 2 4 apply to single bit simulations only They include an allowance for crosstalk Crosstalk effects are accounted for as part of the multi bit timing adjustment factor that is defined in Table 2 8 The recommended timing budget includes 400 ps for the adjustment factor Use caution in applying to coupled simulations This adjustment factor
148. ystem It is recommended that jumpers be placed on the motherboard to allow the boundary scan chain to bypass an empty processor slot TRST must be driven low during reset to all components with TRST pins Connecting a pull down resistor to TRST will accomplish the reset of the port Intef 440GX AGPset Design Guide 4 4 Debug Recommendations 4 3 2 1 Debug Considerations As technology drives better low power modes the current demand could approach 0 Amps This may cause a regulator to go out of regulation Place pads for a load resistance on the Veccore regulator in the event the regulator cannot approach 0 Amps After meeting the guidelines in the Intel Pentium II Processor Datasheet add as many extra high frequency and bulk decoupling capacitance sites as will fit near the processor slot Intel recommends using industry standard Voltage Regulator Modules designed for the processor However previous VRM modules may not support future processors for Slot 1 unless built to VRM 8 2 specifications 4 3 3 Debug Layout Pay close attention to the keep out zones for the Logic Analyzer Interface LAI These keep out zones are required to ensure that the LAI can be installed within a system 4 3 3 1 Design Considerations Plan as much space as possible for the Intel Pentium processor s This will allow for additional cooling or other requirements for early Intel Pentium processor s 4 3 4 Debug P
149. ystem bus interface supports up to two Intel Pentium II processors at the maximum bus frequency of 100 MHz The physical interface design is based on the GTL specification and is compatible with the Intel 440GX AGPset solution The 82443GX provides an optimized 72 bit DRAM interface 64 bit Data plus ECC This interface supports 3 3V DRAM technologies The 82443GX is designed to support the PIIX4E I O bridge The PITX4E is a highly integrated multifunctional component that supports the following functions and capabilities PCI Rev 2 1 compliant PCI to ISA Bridge with support for 33 MHz PCI operations ACPI Desktop Power Management Support Enhanced DMA controller and standard interrupt controller and timer functions Integrated IDE controller with Ultra DMA 33 support USB host interface with support for 2 USB ports System Management Bus SMB with support for DIMM Serial Presence Detect Support for an external I O APIC component System Bus Interface The Intel Pentium II processor supports a second level cache size of 512 KB with ECC All cache control logic is provided on the processor The 82443GX supports a maximum of 32 bit address or 4 GB memory address space from the processor perspective The 82443GX provides bus control signals and address paths for transfers between the processors bus PCI bus Accelerated Graphics Port and main memory The 82443GX supports a 4 deep in order queue i e it provides support for

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