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Inova PD00941013.001 User's Manual

1. 3 03 ICP PM Connector J1 and J2 Inova s ICP CM CPU board has been designed as a 32 bit or 64 bit system slot device able to operate in either 5V or 3 3V I O systems The CompactPCI backplane connector is keyed accordingly yellow for 3 3V and blue for 5V Note Do not remove the keys An 1 0 board operating at 5 0V and keyed accordingly will cause a 3 3V configured system to fail if the keys are removed Page 3 2 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Interfaces Table 3 03 32 Bit CompactPCI J1 Pin Assignment Pin Nr Row A Row B Row C Row D Row E J1 25 5V REQ64 ENUM 3 3V 5V J1 23 3 3V AD 4 AD 3 5V AD 2 J1 21 3 3V AD 9 AD 8 M66EN C BE O J1 19 3 3V AD 15 AD 14 GND AD 13 J1 17 3 3V IPMB SCL IPMB SDA GND PERR J1 15 GN D J1 13 KEY AREA J1 11 AD 18 AD 17 AD 16 GND C BE 2H J1 09 C BE 3 GND IDSEL AD 23 GND AD 22 J1 07 AD 30 AD 29 AD 28 GND AD 27 J1 05 RST GND GNTO J1 03 INTA INTB INTC 5V INTD J1 02 TCK TM TDO TD1 Coo fv se ew EE D Reserved for use for Inova s Uninterruptible Power Supply UPS Doc PD00941013 001 2004 Inova Computers GmbH Page 3 3 Interfaces ICP CM Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear I O D Pin Nr J2 22 J2 20 J2 18 J2 17 J2 16 J2 15 J2 14 J2 13 J2 12 J2 11 J2 10
2. 2 8 10016 2 50 EE Eechen ie der eee 2 8 2 6 Inova CM PCI Device List 2 9 Table 2 60 Legacy 1 0 Map ISA Compatible ss 2 9 2 7 Interrupt Configuration 2 10 Table 2 70 CompactPCI BUS Interrupls eer ot re ertet d het entente rene nes nn 2 10 2 8 Timer Counter sssssssssuuuss 2211 2 9 Watchdog 2 11 Doc PD0094101 3 001 2004 Inova Computers GmbH Page 2 1 Configuration ICP CM 2 0 Memory Map Figure 2 00 System Architecture FFFFFFFFEh Address Limit AGByte 1 FFFFFFFFh 1GByte 100000h 1MByte E4000h CCO00h C0000h Upper Memory B h Blocks 8000 UMBs B0000h A0000h 640kByte Conventional Memory 00000h Page 2 2 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Configuration Note 96kBytes are reserved for option ROM space USB Legacy 32kByte Ethernet Boot 16kByte PXE Boot 48kByte In addition 3rd party devices can also have their space here such as addi tional networking cards SCSI or FireWire etc The total available space cannot exceed 96kByte Doc PD0094101 3 001 2004 Inova Computers GmbH Page 2 3 Configuration ICP CM 2 1 1 O Mapped Peripherals The original PC XT and PC AT desktop computer ISA bus specification allows for 10 bit I O addressed peripherals This permits peripheral boards to be I O mapped from Oh to 3FFh CompactPCl systems permit the full 16 bit addressing cap
3. Users taking advantage of the CPU s rear 1 0 options are advised not to use the front panel interface ETH1 if the rear interface is being used Possible damage to the board could occur and data integrity cannot be assured Table 3 21 Ethernet Standards amp Connector Signals Standard Data Rate Cable Max Length IEEE802 3 10Base T Ethernet IEEE802 3u 100Base Tx Fast Ethernet 10Mbit 2 2 pair Cat 5 100m 100Mbit s 2 pair Cat 5 100m Signal Description Ethernet Fast Ethernet TXO TXO Doc PD0094101 3 001 2004 Inova Computers GmbH Page 3 9 Interfaces ICP CM 3 22 J17 VGA Interface J17 is available on the CPU front panel if this option is required and if this position is not already occupied by an AGP piggyback for PanelLink TFT or GigaST amp R communication The 15 pin high density D Sub connector forms the physical interface for the video on the ICP CM which is integrated within the chipset The amount of graphic memory allocated to the chipset video option is defined in BIOS Vesa resolutions up to 2048 x 1536 pixels with 32 bit colour depth are supported Hence the full VGA SVGA XGA SXGA UXGA HDTV and QXGA scales are covered 3 23 Graphic Features Chipset Table 3 23a highlights just some of the features of the standard integrated video controller Feature Description Supports single video windows with overlay function Supports RGB555 RGB565 YUV422 and YUV420 video
4. Note 10 A 3m length of 9 pin D Sub to DVI D cable is supplied with each CPU config ured with this graphic option Table E1 40 J1 Standard Front Panel VGA TMDS Pinout Pin No Analog CRT Signal Digital TMDS Signal TX2 TXO N C GND DDC_DAT DDC_DAT T VSYNC T ICP P4 PM CM Appendix E 2004 Inova Computers GmbH Page E 9 ND 5V N C GND USB_D x1 X0 xe 1 3 5 7 N C GND USB_D Er e 10 12 14 AGP R7000 Appendix E Table E1 41 J2 DIP Switch Settings Digital TMDS PanelLink or DVI D SW3 SW2 SW1 Resolution Comments OFF OFF OFF Disabled See Note Below 800 x 600 60Hz 1280 x 1024 Reserved Reserved Reserved Resolution Comments Reserved Reserved Reserved Reserved Note If an external DDC is found then the switch settings SW1 to SW3 have no effect This applies to the digital TMDS configuration only Page E 10 2004 Inova Computers GmbH ICP PA PM CM Appendix E Appendix E AGP R7000 Note If the AGP piggyback is installed the VGA connector associated with the chipset graphic must be removed For this reason the AGP piggyback is NOT available as an accessory to be added as an after thought E1 5 Rear I O VGA Interface Refer to the rear UO documentation for video interfacing connectivity ICP P4 PM CM Appendix E 2004 Inova Computers GmbH Page E 11
5. P amp USB USB PS 2 9 9 e 6 gege eee PageA 2 2004 Inova Computers GmbH ICP PM CM Appendix A Appendix A ICP HD 3 A1 2 IDE Carrier Board ICP HD 3 ND Figure A1 2 illustrates the construction of the integrated ICP HD 3 carrier board and the location of the interface connectors Table A1 2 gives a description of these interfaces Care should be exercised when attaching the LPT interface to this carrier board Here the connection is via a length of flex cable between J11 of the carrier and J13 on the LPT module Note Damage to the CPU hard disk carrier board or the LPT piggyback may result if the flex cable is positioned incorrectly Inova will not accept responsibility for negligent actions Position the blue side of the flex cable to the blue flanked connector shown below Figure A1 2 Interface Location of the ICP HD 3 ND Module LABEL4 LABEL J8 J6 J15 J5 j gt LABEL2 LABEL 3 J10 CF on CPU Slave Ji COMI RS485 J4 Reset J7 J2 COM2 RS485 Cl Z yit J3 ICP PM CM Appendix A 2004 Inova Computers GmbH PageA 3 ICP HD 3 Appendix A Table A1 2 Interface Description of
6. J2 09 J2 08 Row A GA4 CLK6 CLK5 GND LPT_STB COM1_TXD LPT_AFD FD_DENSEL COM1_CTS LPT_DO FD_INDEX COM1_RTS LPT_ERR FD_HDSEL COM1_DSR LPT_D1 FD_TRKO COM1_DTR LPT_INIT FD_DIR COM2_TXD LPT_D2 FD_WP COM2_RXD LPT_SLCTIN FD_STEP COM2_CTS LPT_D3 FD_RDATA COM2_RTS LPT_D4 FD_DSKCHG COM2_DCD LPT D5 FD MSENO COM2 DSR Row B GA3 ETH1_TXF GND ATA_AO Den IAE FD WRDATAZ ATA A2 COM1_RXD VGA_VSYNC PRST LPT_ACK DEG FAL FD_DR1 5V 1 5 Row C GA2 Row D GA1 Row E GAO ATA_CSO ATA_RST ETH1_TXF GND ETH1_RXF ETH1_RXF ATA_CS1 GNT6 KB_CLK GNT5 ATA_DO ATA_D2 ATA_D3 ATA D5 ATA D6 GND COM1_DCD GND LPT_SLCT FD_WGATE COM1_RI VGA_HSYNC ATA IOW amp USB4_D GND SMB_DAT ATA_IOR USB4_D PM_DAT V I O ATA IRQ15 ATA DMARQ ATA D9 V I O ATA D7 ATA D8 Page 3 4 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Interfaces Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear 1 0 D Contd Pin Nr Row A Row B Row C Row D Row E LPT_BUSY J2 07 FD_MTR1 PM_CLK SMB_CLK ATA_D10 ATA_D11 COM2_DTR LPT_D6 J2 06 FD DRATEO KB DAT ATA DMACK VGA B ATA D12 COM2 RI LPT D7 J2 05 FD MSEN1 64EN V I O ATA D13 ATA D14 J2 04 V I O SPEAKER GND ATA D15 J2 02 CLK2 CLK3 SYSEN GNT2 REQ3 Doc PD00941013 001 2004 Inova Computers GmbH Page 3 5 Interfaces
7. 1010 110 EEPROM RIO PANEL ID 1010 111 EEPROM Vital Product Data General Purpose 1101 001 ICS952001 Timing Hub Page 2 8 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Configuration 2 6 Inova CM PCI Device List Table 2 60 shows the available PCI devices both on board and off board CompactPCI backplane It should be noted that the interrupt routing assumes a standard Inova backplane configuration with a right hand system slot Table 2 60 Legacy 1 0 Map ISA Compatible Bus Device Function Device No Number Number Vendor ID Description IRQ 0x00 0x00 N A 0651 1039 SiS651 Host Bridge 0x02 0x00 N A 0008 1039 SiS962 LPC en 7001 1039 SiS962 USBO OHCI 0x03 0x01 N A 7001 1039 SiS962 USB1 OHCI fs om om mn ries NN 0x03 0x03 N A 7002 1039 SiS962 USBO EHCI 0x02 0x07 N A 7012 1039 SiS962 B S Audio nr 0900 1039 SiS962 LAN 0x08 0x00 INTA 0020 3388 PCI PCI Bridge a INTB 1229 8086 LAN 82551 Fast Ethernet 1 0x00 0x00 INTA 6325 1039 AGP 2 Ox0A INTC CompactPCI Slot 7 2 Ox0C INTA CompactPCI Slot 5 afo fme oeras 2 OxOE INTC CompactPCI Slot 3 EE CompactPCI Slot 2 next to Master Bus No 0 On board Bus No 1 AGP Bus No 2 CompactPCI Bus D CompactPCI backplane numeration is based on a 7 slot backplane and refers to the logical and not physical slot number Doc PD0094101 3 001 2004 Inova Computers GmbH Page 2 9 Configuration ICP CM 2 7 Interrupt C
8. 4 MOA GraDNICS cic 1 4 1 1 Specifications 1 5 1 2 Functional Overview 1 7 Figure 120 ICP CM Intertacifigu EE 1 7 Figure 1 21 ICP CM Board OVervieW i erst ttti erri eie ier reete se ee 1 8 1 3 Software ssnn2nn2222222222222222 1 9 1 31 Windows XP Professional Embedded ccccccsssssssseceeceeeeesssseeceenes 1 9 1 32 Windows 2000 Professional dir nn titane 1 9 TEINUR ou 1 9 Ne OA TR UT E LIT T NT 1 9 1 35 WiINdOWS CE m 1 10 EE en 1 10 US OST EE 1 10 E NEE 1 10 Wee 01 10 OT T 1 10 Doc PD00941013 001 2004 Inova Computers GmbH Page 0 1 Preface ICP CM 1 4 Hardware c nnn Rue eene 1 11 1 41 Block Dia ram nt tente diet rane ER 1 11 Figure 1 41 BlOCK DiGQIGI EE 1 11 1 42 Connector LOCAMON o eor iestidvnbds venus setae tertie remonte 1 12 Figure 1 42 Connector Locations Een aerae rte ik ae e D od aep beh 1 12 TAS Connector Descrip M 1 12 Table 143 Connector Descriptio esos eet tote etie etia rhe x ved eene 1 12 tabel AS CONNUE 2 P 1 13 E TRE Mee P 1 13 Table 1 44 td IJ R 1 13 Figure 1 44 Front Panel Options seen 1 14 1445 Interface POSIUONS e es 1 15 Figure 1 45 Intetf Ces fer geeiert e RP REUS 1 15 1 46 Construction 4HP Standard CPU us ette rere hts enero terere
9. 5 A2 2 Mouse amp Keyboard Interfaces ice ee RE EE Eege A 6 Figure A2 2 Mouse amp Keyboard Interface Pinout ss A 6 Table A2 2 Mouse amp Keyboard Connector Signals eese A 6 Table AZ 3 USB Connector SIGMOIS raai ment tinta Rete Pra eee ae mienne mit A 7 A2 3 USB 2 0 mterfa CES Mo NE A 7 FigureA2 3 Tee A 7 A2 A EIDE lr ne contrer EE ee EN EEEE EE A 8 A2 5 Slim Line Floppy DISK IER anne een A 8 B1 IPB FPE 12 CPU Extension BeBe eee B 2 B1 1 J13 Interface for EE eet eege B 2 B1 2 IPB FPE12 Front Panel 4HP or 12HP eee eere eren eror roro B 2 Figure B1 2 IPB FPE12 Stand Alone or Integrated with CDU B 2 B13 EPTTPIGOUDACR anne a moment B 3 Figure B1 3 LPT1 Piggyback Board IPB FPET2 ue B 3 Table BT 3 IPB EPET2 Connector DescriDlioh quiate idera R neta echte es aset este B 4 BVA CPTI Interface P B 4 Figure B1 4 LPTT Interface PINOUE auction rd rr E AEAEE N B 4 lable B14 LPTI Connector SIgHals sanyin eat ma ti eer ir RT P EE ERAT EET FEA B 4 Ca ITM RIO CPU Extension BEB Bee eee C 2 C1 1 ITM RIO D Configurations T C 2 Table CT 10 Valid Rear 1 O COntigurauons ssssssinntin eernstennenendtrennsrenentensernranintese C 2 Table CT 1 T ReardT O Module FUNCHONOIICY wesviossacaarsazansecectovonscadesspaetagsvats nk eo a Ta nate C 2 C1 2 ITM RIO Rear Panels 4HP or SHP inrer er tor ERE Er era Exin RERO E C 3 Figure C1 2 The rear Panels of the Inova ITM RIO D x eee C 3 CT I
10. 77F LPT1 ECP only CF8 PCI Configuration Address DWORD Access Only PCI Configuration Data ORE DWORD Access Only Note Denotes Plug n Play devices that are configured during the BIOS POST Values shown are ISA compatible 1 0 addresses for reference only Doc PD00941013 001 2004 Inova Computers GmbH Page 2 5 Configuration ICP CM 2 2 Memory Mapped Peripherals PC AT desktop computers ISA bus allow 24 bit memory addressed peripherals This decoding permits peripheral boards to be mapped in the Intel 80x86 memory map from Oh to OFFFFFFh Inova s CompactPCI systems allow the full 32 bit addressing capability of the Intel Pentium 4 range of processors so that memory mapped peripheral devices may be mapped locally to the processor board at any location in the memory map not being used by other devices e g system RAM The BIOS automatically assigns memory addresses required by peripheral boards and PCI devices at boot time based on the requirements of each device The assigned addresses can be deter mined by reading the configuration address space registers using PCI software tools Note Devices not located on the CPU side of the PCI PCI bridge are not normally accessible by DOS 2 3 Interrupt Routing The IBM compatible architecture includes one PC XT or two PC AT programmable interrupt controllers Intel 8259A compatible PICs configured to set the priority of interrupt reques
11. Computers GmbH Doc PD00941013 001 ICP CM Preface 2 7 Interrupt Configuration 2 10 Table 2 70 CompactPCI BUS Interrupts arsen res cose ertet aa exe rn Eniri 2 10 2 8 Timer Counter 2 17 e 9 Watchdog amp 7171 3 0 CompactPCI J1 J2 Connectors 3 2 3 01 CompactPCI Connector Naming aue uiuere entree 3 2 Figure 3 01 Naming Convention as per PICMG 2 0 R3 0 Specification esee 3 2 3 02 CompactPCI JI Connector ergeet 3 2 Figure 3 02 J1 32 Bit CompactPCI Bus Interface Connector sess 3 2 3 03 ICP PM Connector IT and nn eet See ee 3 2 Table 3 03 32 Bit CompactPCI J1 Pin Assignment nk 3 3 Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear 1 0 D sese 3 4 Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear I O D Contd 3 5 Table 3 05 Inova s ICP CM Rear 1 0 J2 CPU Integration 3 6 3 1 CompactPCI Backplane 3 7 Figure 3 10 Inova s 32 Bit CompactPCI 8 Slot Backplane RH System Slot 3 8 3 2 Irtertacees nennen NNN RN RN RN RN ARA NN 3 9 3 21 J6 amp AN PAS ET PR RER UN ET 3 9 Figure 3 21 RAS Pinout uiii erronee rune onesie seraient c epe HR eo n Vr 3 9 Table 3 21 Ethernet Standards amp Connector Signals cesses 3 9 3 22 J17 VGA Interface 2 bes come Dette tk euet n Eege due Eeer EE PEE E eR a in
12. Slave operation Table D1 2 IPM ATA HD Jumper Description CF Socket CompactFlash Jumper J6 or MicroDrive in J3 It should be noted that the secondary IDE channel from rear I O only is available for use by the IPM ATA HD the primary is on the CPU board itself Multi Master or multi Slave configurations are not supported and will not work Page D 4 2004 Inova Computers GmbH ICP P4 PM CM Appendix D Appendix D IPM ATA D1 3 IPM ATA CF The IPM ATA CF has provision for one or two standard Compact FLASH or MicroDrive devices Figure D1 3 illustrates the significant connectors for this device while Table D1 3 indicates the jumper settings for the various Master Slave device configurations Figure D1 3 IPM ATA CF Board Layout C150 Pi os prp pa J7 J8 J6 Table D1 3 IPM ATA CF Jumper Description CompactFlash or MicroDrive in J3 CompactFlash Jumper J6 or MicroDrive in J4 Jumper J7 It should be noted that the secondary IDE channel only from rear I O is available for use by the IPM ATA CF the primary is on the CPU board itself Multi Master or multi Slave configurations are not supported and will not work ICP P4 PM CM Appendix D 2004 Inova Computers GmbH PageD 5 IPM ATA Appendix D D1 4 IPM ATA PCMCIA The IPM ATA PCMCIA has provision for one standard ATA PCM
13. Wo D ers erg ov LLL SN JL SN J e zo eco ao oco Also visible on the upper side of this piggyback are three labels one Label 1 shows the name of the board the second shows the product bar code with manufacturing details lot number and ID number and the third Label 3 carries the revision number The board revision is also printed on the PCB ICP P4 PM CM Appendix E 2004 Inova Computers GmbH Page E 7 AGP R7000 Appendix E Table E1 30 J3 amp J5 Interface Pinout J3 Connector J5 Connector Pin No Signal Pin No Signal D22_R6 D23_R7 GND CLK Information on the GigaSTAR IPB GS MULTILINK can be found in the respective documentation Page E 8 2004 Inova Computers GmbH ICP PA4 PM CM Appendix E Appendix E AGP R7000 E1 4 J1 Front Panel VGA TMDS Interface Standard analog VGA or digital PanelLink monitors can be connected to the AGP R7000 via the 15 pin D Sub J1 interface A bank of DIP switches J2 enables the resolution of connected TFT or TMDS displays to be set or permits the system software to access the DDC data from standard analog or digital TMDS devices and set the resolution automatically Figure E1 40 shows the VGA TMDS connector signals for the front panel D Sub connector and tables E1 40 to E1 42 show the connector pinout and DIP switch settings respectively Figure E1 40 Standard Front Panel VGA TMDS Interface
14. YER eei Ris 3 12 3 25 J10 Hot Swap Interface ios rote cet einen 3 13 3 20 SWI Reset BUTOI e Ec Eain 3 13 3 27 J9 CompactHlash Interface oscar ne EE 3 13 3 28 Connecting the CM to the Inova ICP HD3 ND eene 3 13 3 29 Connecting the CM to the Inova IPB TPET2 sis escono et eessen eneen 3 13 3 30 Connecting the CM to a Slim Line Floppy Disk scsi 3 13 Doc PD00941013 001 2004 Inova Computers GmbH Page 3 1 Interfaces ICP CM 3 0 CompactPCl J1 J2 Connectors The CompactPCI standard is electrically identical to the PCI local bus standard but has been en hanced to support rugged industrial environments and up to 8 slots The standard is based upon a 3U board size and uses a rugged pin in socket hard 2mm connector IEC 1076 4 101 3 01 CompactPCI Connector Naming Figure 3 01 Naming Convention as per PICMG 2 0 R3 0 Specification rue Type B Pos 1 22 c m Type B tPos 1 22 H n Type AB Pos 1 22 3U COMPACT PCI REAR PANEL VO BOARD EN 3U COMPACT PCI FRONT PLUG IN BOARD Type A Pos 1 25 Type A Pos 1 25 c ki 3U COMPACT PCI BACKPLANE Si m 3 02 CompactPCl J1 Connector Figure 3 02 J1 32 Bit CompactPCI Bus Interface Connector 1 11 15 25
15. formats Video Accelerator Supports DVD sub picture playback overlay 2x 120x128 video playback line buffers to support 1920x1080 video Supports Direct Draw Drivers Built in 64x128 CRT FIFOs to support ultra high res graphics Programmable 24 bit true colour RAMDAC up to 333MHz pixel clk High Integration MPEG II video playback Built in TV encoder interface Supports 333MHz clock Resolution Colour amp Frame Rate Supports VESA standard super high resolution graphics modes Supports low resolution modes 320x240 512x384 400x300 Supports VESA Display Power Management Signalling Power Management Supports clock throttling for 2D engine and 3D engine Multimedia Application Supports RAMDAC snoop for multimedia applications Page 3 10 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Interfaces Figure 3 23 High Density D Sub VGA Interface Pinout 5 1 15 11 Table 3 23b Video Output Connector Signals Pin No Analog RED MEN GREEN Analog BLUE 4 N IC 5 6 7 8 CRT Ground DDC SDA E VSYNC E Doc PD0094101 3 001 2004 Inova Computers GmbH Page 3 11 Interfaces ICP CM 3 24 J19 USB Interface J19 is located as standard on the front panel All standard USB 2 0 and 1 1 compatible devices can be connected to this interface LT LT ats 1 2 3 4 Table 3 24 USB Connector Signals Figure
16. i e occupying either the system slot or the peripheral slot The PCI PCI bridge automati cally detects the CPU location within a system Note Older backplane revisions rev 2 11 cannot be used with Inova CPUs config ured for rear 1 0 D Attempting to do so will cause the boot sequence to fail When installing the CPU in environments where PXI peripheral boards are being used CPU versions without rear I O must be used Otherwise signal conflict will occur on the J2 interface Doc PD00941013 001 2004 Inova Computers GmbH Page 3 7 Interfaces ICP CM Figure 3 10 Inova s 32 Bit CompactPCI 8 Slot Backplane RH System Slot 97e4egecepereg 00000 o H o ee H H o o Zo Ao Bo Co DoEo ninen _O Note The logical slots are different to the physical slots The slot marked with the A is the System Slot and always as signed logical 1 The neighbouring slot is logical 2 Page 3 8 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Interfaces 3 2 Interfaces 3 21 J6 amp J7 Ethernet J6 is a Fast Ethernet interface from the SiS chipset while J7 ETH1 is an additional Fast Ethernet from the dedicated on board controller Both RJ45 interfaces are available as standard on the CPU front panel and provide support for 10BaseT and 100BaseTX twisted pair standards Figure 3 21 RJ45 Pinout Note
17. is the ideal choice for low power high peromance computing tasks In addition enriched performance scalability is assured through the latest Intel Celeron M processors and board feature set Conforming to the latest PICMG CompactPCI specification the ICP CM has a colourful feature set that includes rear UO options choice of graphic components and flexible mass storage expansion options Being of a true universal design both 5 0 and 3 3V I O signalling voltages are possible without board modification The auto detect mechanism in the PCI PCI bridge permits the same CPU to operate as a system Master controller or reside in a peripheral slot A Slave CM CPU is thus able to communicate with the host controller through the bridge via the CompactPCI backplane for high speed DMA for example or front panel TCP IP The standard Inova ICP CM configuration is ready to run straight from the box Utilizing the low power consumption and the high performance of the Celeron processor enables truly embedded ruggedized industrial applications to be engineered utilizing the latest software available today 512kByte of L2 cache backed by up to a 1GByte bank of soldered double data rate DDR SDRAM clocked at 266MHz ensures an efficient processor level data throughput exceeding that of any comparable product For hard core ruggedized applications and thanks to the miniaturisation of silicon components Inova s engineers have squeezed in a Compact FLASH
18. metet indt erede n a rio e a eu C 2 CT 2 ITM RIO Rear Panels 4HP ot SAP sers maine teres Ene eR etra ooo wean C 3 Figure C1 2 The rear Panels of the Inova ITM RIO D x eene nnne nnne C 3 CL S ITM RIO D x Transition MOIS C 4 Figure C1 3 Inova Rear I O Transition Module ITM RIO D x C 4 Table C1 3 ITM RIO D x Connector Description ss C 5 CIA COMTI ee EE C 6 Figure C1 4 COM1 amp COM2 Interface Pinout seen C 6 Table C1 4 COMI amp COM2 Connector Signals 2 terere tinet ee er ee x niiina C 6 WI ENT a ed eme ie ets C 7 Figure C1 S LPTT Interface e C 7 Table C 1 5 EPTT onnector SEI ennen rettet dae RP Pere YE EUH RUE Ae tendons AEN C 7 C1 6 Mouse amp Keyboard Interfaces oie msn C 8 Figure C1 6 Mouse amp Keyboard Interface Pinout C 8 Table C1 6 Mouse amp Keyboard Connector Signals ss C 8 7 VGA MMR ACS Me Cc nn ae a oo mn C 9 Figure C 1 7 VGA Interface PIROUL sot oot rri et mia een eed ceni ee indienne teen rene C 9 Table C1 7 Video Output Connector Signals sus C 9 C18 Fast Ethernet I WET ACE een cmt C 10 Figure C1 8 Fast Ethernet Interface PInOUL iusserit rond rrt i eerte C 10 Table C1 8 Fast Ethernet Connector Signals us iere tee tette eant eet rre ntt eee ne nnus C 10 C1 9 USB Interface USB tal nan EN eg Set Seege ge ee C 11 Figure C1 9 USB Interface PINOUE uisi itt ri eoe erroe et CEA EEA err euin as C 11 Table CI 9 USB Connector SINAIS iesu eren rera tnter eoe
19. tende on eae ndo at ewe de tee C 11 CVO EIDE cL enc eennn C 12 CIT Sim Bne Floppy Disk Interface nids C 12 CI TZ ITM RIO C amp D FHLU EXUDSIOD teen concis C 13 Figure C1 12 HMESRIO CGDOSEHEU anota rester hsc a tta P peer e SR rH EE Fa eher C 13 ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 1 ITM RIO Appendix G C ITM RIO CPU Extension The Inova Pentium 4 M Pentium M or Celeron M CPUs are more than just a computing platform they are a complete well thought out concept Nowhere is this more apparent than in the colourful rear I O selection With a choice of three full length 80mm plug in modules conform ing to the latest Inova rear I O D specification and the rear I O C1 options the major industrial requirements have been satisfied C1 1 ITM RIO D Configurations Rear I O D is the standard configuration for the Pentium 4 M Pentium M and Celeron M series of high performance CPUs Table C1 10 illustrates the configurations stemming from one single PCB layout with backward compatibility to some of the features provided in the Inova rear I O C boards Table C1 11 shows the functionality of the 4 Inova rear UO compatible modules Table C1 10 Valid Rear 1 0 Configurations Option RIO C1 leist Processor VGA No Yes Controller ASIE PM CH USB 1 1 Pattes romeo ve me em se feu LAN Networking Matrix Product VGA Fast USB O Mouse MERS Full Name Graphic Ethernet Keyboard Storag
20. twin engined Radeon based AGP piggyback graphic option should be used The single channel Fast Ethernet option in table C1 10 is either ETH1 or ETH 2 on the front panel depending on the computer platform If the rear I O option is used then the front panel connec tion must not be used Doing so will disrupt the communication leading to spurious results If the mouse keyboard and COM ports are used in rear I O applications then they should not be used from the front panel Communicating from both mouse and keyboard sources is physically possible but is not recommended ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 3 ITM RIO Appendix G C1 3 ITM RIO D x Transition Module Figure C1 3 illustrates the construction of the ITM RIO D x module The connections are straight forward and need little by way of explanation None of the connectors can be incorrectly inserted thanks to the mechanical keying of both plug and socket Table C1 3 explains the significance of the interfaces labelled in Figure C1 3 Note Care should be exercised when insert ing the cables linking the COM LPT EIDE and floppy etc Only those cables supplied by Inova Computers should be used Figure C1 3 Inova Rear I O Transition Module ITM RIO D x Page C 4 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix C ITM HRIO Table C1 3 ITM RIO D x Connector Description Connector Description CompactPCI rear I
21. warranty may in the event of any claim return the product at the earliest possible convenience together with a copy of the original proof of purchase a full description of the application it is used on and a description of the defect to the original place of purchase Pack the product in such a way as to ensure safe transportation we recommend the original packing materials whereby Inova undertakes to repair or replace any part assembly or sub assembly at our discretion or to refund the original cost of purchase if appropriate In the event of repair refund or replacement of any part the ownership of the removed or replaced parts reverts to Inova and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report returned from Inova with the repaired or replaced item Other than the repair replacement or refund specified above Inova will not accept any liability for any further claims which result directly or indirectly from any warranty claim We specifically exclude any claim for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time The extent of Inova s liability to the customer shall not be greater than the orig
22. were not being utilised and software stressed to 10096 To stress this CPU the following software was installed b Microsoft Windows XP SP1 gt DirectX 9 0b gt ATI Catalyst 3 9 video driver on a 20GByte HD mounted on the baseboard 8HP with HD carrier with 256Mbyte PC2100 memory and including the Radeon R7000 AGP piggyback with 32MByte video memory Figure 1 50 ICP CM Power Consumption Total Power Consumption BIDLE E 10076 L1BIOS Watt 600 MHz 1300 MHz Page 1 20 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 51 Thermal Considerations Being a passively cooled design a purpose built thermally optimized heat sink is all that removes the heat from the CPU The effective surface area of the radiator unit mounted on the single slot 4HP CPU version is less that of the 8HP CPU and therefore necessitates more airflow or air circulation to keep it cool As a guideline the figures published in table 1 51 show the minimum airflow required to maintain stable operation As the ambient temperature surrounding the CPU increases so the airflow must increase Conclusions that can be drawn from this table are gt Single slot CPUs should not be integrated in applications where the environmental temp ex ceeds 65 C P CPUs intended for use in applications running at high operational temperatures 85 C should be clocked at 600MHz At greater
23. 3 24 USB Interface Pinout 1 5V USB PO 2 3 USB PO 4 GND Page 3 12 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Interfaces 3 25 J10 Hot Swap Interface This PCB level interface is used for the front panel integrated micro switch and blue LED in ac cordance with the PICMG 2 1 R2 0 specifications 3 26 SW1 Reset Button The reset button allows the CPU to be reset in the event that it hangs Performing a reset in this manner is known as a warm start as power is not removed from the peripherals IDE etc 3 27 J9 CompactFlash Interface CompactFlash cards are designed with flash technology a nonvolatile storage solution that does not require a battery to retain data indefinitely CompactFlash storage cards are solid state meaning they contain no moving parts and their low power consumption means that they con sume only five percent the power required by small disk drives J9 is the standard CompactFlash interface and needs no further explanation 3 28 Connecting the CM to the Inova ICP HDS ND Appendix A provides more information on the ICP HD3 ND and its derivatives For the sake of completeness however the ICP HD3 ND must only be attached detached to from the CM base board without power applied i e with the CPU removed from the CompactPCI environment Since there aren t any flat band cables or similar installation is remarkably simple T
24. C1 6 and Table C1 6 respectively Note If the mouse keyboard ports are used in rear 1 0 applications then they should not be used from the front panel Communicating from both mouse and keyboard sources is physi cally possible but is not recommended Figure C1 6 Mouse amp Keyboard Interface Pinout Pin No 2 4 Page C 8 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix C ITM RIO C1 7 VGA Interface The VGA signals appearing on this interface are from the CPU chipset or AGP piggyback if config ured for rear I O signalling Figure C1 7 and Table C1 7 provide the pinout and signal description of this standard VGA interface respectively With an AGP video piggyback installed the video image appearing on this rear I O interface can be selected to be different to that appearing on the front panel This is possible through in this case the piggyback s dual independent Radeon 7000 graphics engines Note Using the chipset graphics for both front and rear 1 0 simultaneously is not advisable as the loading may be too great If both front and rear 1 0 VGA are required then the twin engined Radeon based AGP piggy back graphic option should be used 5 1 15 11 Table C1 7 Video Output Connector Signals Figure C1 7 VGA Interface Pinout CRT Ground 5V DDC CRT Ground DDC SDA HSYNC 14 VSYNC 15 DDC SCL ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 9 I
25. CIA device and one Compact FLASH or MicroDrive site Figure D1 4 illustrates the significant connectors for this device while Table D1 4 indicates the jumper settings for the various Master Slave device configurations Figure D1 4 IPM ATA PCMCIA Board Layout C150 ES E pa JI V8 J6 Table D1 4 IPM ATA PCMCIA Jumper Description CompactFlash or MicroDrive in J3 Jumper J8 PCMCIA Device in J5 Jumper J6 It should be noted that the secondary IDE channel only from rear I O is available for use by the IPM ATA PCMCIA the primary is on the CPU board itself Multi Master or multi Slave configura tions are not supported and will not work Note The PCMCIA device cannot and must not be removed during use To ex change or remove the device first power down the system PageD 6 2004 Inova Computers GmbH ICP P4 PM CM Appendix D Appendix D IPM ATA D1 5 Device Compatibility Because of the diversity of Compact FLASH devices available with different architectures and error recovery routines etc there is a strong possibility that some Master Slave combinations will fail to be recognised by the BIOS To help highlight the problem Inova have provided the test report shown in Table D1 5 which should be regarded as a guide when choosing to pick and mix de vices Should d
26. GP Piggyback Configurations J1 Front Rear I O J3 J5 CRT 1 TFT Option 1 CRT 1 CRT 2 TFT Option 3 TMDS CRT 1 Option 5 Note The front and or rear connected display devices may be configured to show the same or different independent video content to TFT units by configuring the driver software With the AGP installed the onboard chipset graphic is disabled Options 2 and 5 are preferred standard Option 3 although possible should only be selected if CRT 1 is permanently connected 1 OpenGL applications performed 83 faster with the AGP piggyback installed and memory efficiency increased by 14 PageE 2 2004 Inova Computers GmbH ICP P4 PM CMAppendix E Appendix E AGP R7000 E1 1 Specifications Interface AGP 4x 120 pin connector Video ATI Radeon with 32MByte RAM Controller Screen Options Resolution Colour Depth Refresh TFT amp VGA 1920 x 1200 32 bit 72Hz 1920 x 1200 16 bit 80Hz 2048 x 1536 16 bit 60Hz TMDS 1600 x 1200 24 bit 60Hz Configuration DIP switch for DDC data or fixed resolution User Interfaces 15 pin D Sub for front panel VGA or 15 pin D Sub for front panel TMDS PanelLink 2x27 pin ZIF connector for TFT GigaST R Options Front or rear panel VGA Front panel TMDS and rear panel VGA Software Windows 20009 Windows XP Support Power Req 3 3V 2W 5V 2W typically Mass 40g typically Oper Temp 0 C to 60 C Storage Temp 40 C to 85 C
27. Humidity 5 to 95 non condensing 40 C Warranty Three year limited warranty U Two VGA monitors can be connected simultaneously with identical video information on both the Radeon graphics engine must be configured accordingly An alternative is also available where the content appearing on the 2nd display is different to that of the first The disadvantage of this configuration is that if a monitor is not connected to the front panel CRT1 the video content cannot be displayed on CRT2 rear until the OS has been initialised and the video driver initialised If a BIOS upgrade is required or the settings need to be altered etc then without the CRT on the front panel the user will not see anything which makes the task almost imposible This is the only supported mode whereby independent video can be produced via the front DVI D and a rear connected analog CRT device 2 Both options support TFT video content can be selected to be the TMDS or CRT ICP P4 PM CM Appendix E 2004 Inova Computers GmbH PageE 3 AGP R7000 Appendix E E1 2 J4 Interface Communication to and from the host CPU is through J4 refer to figure E1 20 the AGP interface The video output as discussed earlier is hardware configured at time of purchase for different front and rear panel modes refer to table E1 00 The TFT option J3 J5 is always present The J4 AGP interface on the graphic piggyback is electrically identical to AGP but has
28. ICP CM Table 3 05 Inova s ICP CM Rear I O J2 CPU Integration RIO C1 RIO D VGA No Yes Fast Ethernet Intel 82551 Intel 82551 USB 1 1 Yes PS 2 Mouse amp Keyboard Keyboard Only 2nd IDE Channel Software Selectable Software Selectable One of Software Selectable Software Selectable The rear I O options described here do not detract from the latest PICMG 2 0 R3 0 specification 1 The VGA option in table 3 05 is from the chipset or mounted AGP piggyback chipset video should not be used in parallel with the front I O option Doing could cause possible damage to the CPU board If both front and rear VGA are required then the AGP piggyback graphic option should be used which may also permit different video information to be displayed 2 The single channel Fast Ethernet option in table 3 05 is ETH 1 on the front panel i e the dedicated Intel 82551 controller If the rear UO option is used then the front panel connection must not be used Doing so will disrupt the communication leading to spurious results 3 If the mouse keyboard LPT or COM ports are used in rear I O applications then they should not be used from the front panel Communicating from both mouse and keyboard sources is physically possible but is not recommended The front panel COM port connections are disabled If using the rear 1 0 COM port option 4 The CPU boasts a number of USB connection possibilities one USB 2 0 is on the front pa
29. ICP CM Intel Celeron M Low Power CPU Boards f 11 Ce 3 s D ES Ce ES e ei f e ES Gei ES z A A F F De y LA x Z 7 1 A 7 G AUS Sr USER S MANUAL Publication Number PD00941013 001 AB MAN ICP CM Inova Computers This user s manual describes a product that due to its nature cannot describe a particular applica tion The content of this user s manual is furnished for informational use only is subject to change without notice and should not be constructed as a commitment by Inova Computers GmbH Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user s manual Except as otherwise agreed no part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical recording or other wise without the prior written consent of Inova Computers GmbH Products or brand names are trademarks or registered trademarks of their respective companies or organisations ICP CM Preface Preface Contents Unpacking and Special Handling Instruc IL Uu Te TE ee Tee Te CE Ce ee ae Revision History rrr 7 Three Year Limited Warranty 8 7 0 ICP CM CDPU WD MO TRE q S 1 NEST T LE itente 1 4 1 02 PernpheralS MC 1 4 1 03 SO TE B Loi ed espe tte dta en DIE 1
30. IDE ribbon cable is used to connect rJ2 of the ITM RIO modules to the IPM s dedicated backplane The use of ribbon cable permits the mass storage device s to be positioned at any convenient location within the CompactPCI enclosure Figure D1 1b shows the complete configuration CompactPCI to IPM XXX Figure D1 1b The Complete Connection Picture KEY 1 IPM ATA carrier board 2 Dedicated backplane with standard IDE header and power cord interface 3 Y Cable for bringing the power from the CompactPCI backplane and to this and another device 4 Standard 80 strand ATA 5 UDMA 66 or higher IDE ribbon cable 30cm 5 Inova rear UO module ITM RIO with IDE connection Note The IDE cabling used should conform to at least ATA 5 standards 80 strand ICP P4 PM CM Appendix D 2004 Inova Computers GmbH Page D 3 IPM ATA Appendix D D1 2 IPM ATA HD The IPM ATA HD has provision for one standard notebook 2 5 EIDE device FLASH or hard disk and one Compact FLASH or MicroDrive site Figure D1 2 illustrates the significant connectors for this device while Table D1 2 indicates the jumper positions for the various Master Slave device configurations Figure D1 2 IPM ATA HD Board Layout C150 el ES EZ Pai 7 J8 J6 Ji Note The hard disk is jumpered seperately for Master
31. KEYBOARD Fast Ethernet SOUTH BRIDGE USB 1 2 0 USB 2 2 0 l PB RESET Pa Y SDRAM SiS651 D G ON BOARD bI 256Mbyte DDR 266 USB 3 2 0 USB 4 1 0 SiS962 Fast Ethernet D HoT swAP PCI Bus 32 bit 33MHz p REAR UO PCI PCI Q FRONT I O o REAR UO Connector No Master Slave Q EXTENDED FRONT I O OPTION J PIGGYBACK 182551 Inova s CPUs have been prepared for rear I O operation Currently RIO D is supported with VGA single channel Fast Ethernet second EIDE channel USB 1 1 mouse keyboard reset and loud speaker beeper and a software selectable choice between LPT1 COM1 amp COM2 or floppy drive Other rear I O options may also be available including customer specific but are not referred to in this user s handbook For OEM quantities and compatibility with existing 2 11 backplanes etc RIO C1 could be considered this is identical to rear 1 0 D except that the VGA COM and PS 2 mouse options are not available In order to take full advantage of the rear I O features the CompactPCI backplane needs to support them Inova provides two standard versions the first has the rear rP2 connector on the Master CPU slot only while the other has all slots fitted with rP2 connectors Be aware that boards using the PXI bus will experience signal conflict if used with any includes non Inova boards CPU offering rear I O Therefore in such cases always select a CPU board configuration without re
32. O connector Standard 3 5 IDE header Standard slim line floppy disk interface Beeper loudspeaker COM2 is configured for RS232 communication COM2 is configured for RS485 communication COM1 is configured for RS232 communication COM1 is configured for RS485 communication VGA physical interface COM1 USB physical interface USB 4 Fast Ethernet physical interface PS 2 mouse amp keyboard interface only keyboard on ITM RIO D 2 Note When setting up the rear I O D the following should be observed Either the LPT interface or the COM ports or the floppy disk interface can be used not combined Only the required device should be attached Installing or attaching hard ware that is not required will prevent the actual device from being configured Example if a FD is physically attached but the COM ports are required then these ports will not work even if they are correctly configured in BIOS ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 5 ITM RIO Appendix G C1 4 COM amp COME Interfaces The two COM ports feature a complete set of handshaking and modem control signals maskable interrupt generation and highspeed data transfer rates An 8HP rear panel Figure C1 2 brings out the physical COM1 amp COM2 interfaces Note If the COM ports are used in rear I O applications then they should not be used from the CPU front panel The front panel COM port connections are disabled automat
33. Product Overview 1 49 Power Requirements This CPU board is a high performance low power device and as such requires voltage current and power timing as defined in table 1 49 for correct operation The Inova gt 70W PSUs fulfil these requirements and reference should be made to this products data sheet and user s manual Table 1 49 ICP CM Power Reqirements Supply Voltages Voltage US 2 5A 600MHz 5 0V 5 3 5 2A 1300MHz 3 3V 5 3 1 8A 5 0V 5 3 or V 10 3 3V 5 3 Power Dissipation Frequency Pror Typ Pror Max 600MHz 13 7W 17 5W 1300MHz 19 5W 31 3W Power Sequencing This CPU needs both the 5V and 3 3V lines to be switched simultaneously within a max allowable skew of 2ms VI O is assumed to be connected to either the 5V or 3 3V directly Symbol tax Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 19 Product Overview ICP CM 1 50 Power Consumption The illustration provided in figure 1 50 is for reference only and serves to show the typical maxi mum power consumption of the ICP CM CPU Variations in processor manufacture and onboard silicon make accurate testing impossible and hence the figures shown in this illustration are sub ject to fluctuation Note There is no such thing as a typical application and so the CPU power consumption was measured with the processor in idle state in BIOS mode i e the OS power management features
34. Standard to all rear I O transition modules is the 3 5 EIDE hard disk header This has a standard commercial PC pinout and requires no further mention here Note To conform with the ATA 5 standard only suitable commercially available 80 strand ribbon cable should be used Failure to do so may result in data transmission errors or even cause the CPU to crash C1 11 Slim Line Floppy Disk Interface Standard to all rear I O transition modules is the slim line floppy disk header This has a standard commercial PC pinout and requires no further mention here Page C 12 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix C ITM RIO C1 12 ITM RIOCCGDDJ FHLU Extension To further enhance the I O and serviceability of their CPUs Inova have introduced a rear I O module figure C1 12 that connects to a CompactPCI connector on the rear of the Master Slot on the backplane All standard Inova backplanes are equipped with this R2 connector so that even if the rear I O functionality is not requested at time of order it can be implemented at a later stage One of the advantages of this module apart from its obvious size benefit is its ability to attach a 3 5 DE device or Inova IPM ATA Mass Storage Device without direct connection to the CPU base board This facilitates servicing and allows a CPU for example to be exchanged without touching the software stored on the HD Likewise a hard disk can be swapped without ha
35. TM RIO Appendix G C1 8 Fast Ethernet Interface Standard to all rear UO D transition modules is the Fast Ethernet connection Figure C1 8 and Table C1 8 provide the pinout and signal description of this standard Ethernet interface respec tively Although the LEDs feature on the Ethernet connector these are not physically connected to the rear I O interface board Instead if this interface is used communication traffic can still be observed on the front panel Ethernet connector Note The single channel Fast Ethernet option in table C1 10 is either ETH 1 or ETH 2 on the front panel depending on the computer platform If the rear 1 0 option is used then the front panel connection using the same controller must not be used Doing so will disrupt the communication leading to spurious results Figure C1 8 Fast Ethernet Interface Pinout Signal Description Ethernet Fast Ethernet Page C 10 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix C ITM RIO C1 9 USB Interface USB d Standard to all rear I O D transition modules is the peripheral USB 1 1 port Figure C1 9 and Table C1 9 provide the pinout and signal description of this standard Ethernet interface respec n ERE 1 Figure C1 9 USB Interface Pinout Table C1 9 USB Connector Signals ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 11 ITM RIO Appendix G C1 10 EIDE Interface
36. TM RIO D x Transition englescht C 4 Figure C1 3 Inova Rear I O Transition Module ITM RIO D x C 4 Table C1 3 ITM RIO D x Connector Description ss C 5 m Tae i Res MEM P m C 6 Figure 1 4 COMT S COM Interface PINOUT aei rita iore redo Ere LE eene HRS C 6 Table C1 4 COMI amp COM2 Connector Signals urnes C 6 eA aM ito cmm C 7 Figure CT 5 LPTI Interface PIDOUE 5oceeesoi ene ia peter tp t eege eege Let e pU este ne C 7 Table Cis LETI ele EE C 7 C1 6 Mouse amp Keyboard Interfaces ns ecrit C 8 Figure C1 6 Mouse amp Keyboard Interface Pinout ss C 8 Table C1 6 Mouse amp Keyboard Connector Signals essen C 8 MNA MMC M Q C 9 Figure cl e iere C 9 Table C1 7 Video Output Connector Signals sus C 9 C58 Fast Ethernet Inlet dee dun bone anis C 10 Figure C1 8 Fast Ethernet Interface PIN Out nn eo Lir toe art tet ren bd eor dede es C 10 Table C1 8 Fast Ethernet Connector Signals eee itae rote eer ri erae EST C 10 Page 0 4 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Preface C1 9 USB Interface USB EE C 11 Ejgute C EE C 11 Table Gl SUSE Connector e C 11 C110 EIDE Interface MD C 12 C1 11 Slim Line Floppy Disk Interface geegent nee EE C 12 C1 12 ITM RIO C amp D FHLU Extension uses C 13 Figure CT 12 TTM RIO C amp D FRIEU ugeet ter oniinn eeir Enn ETETE EDEN EE ey uer REP Rite vb rede C 13 D IPM ATA CPU Extension See ee eee D 2 DIL VIZ Interface rierr
37. a s ICP HD 3 carrier board as are the interfaces for the LPT and slim line FD The LPT interface is available on a dedicated panel shown to the right of Figure 1 44 Page 1 14 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 45 Interface Positions Figure 1 45 Interfaces CN D dt IPB FPE 12 gt 30GByte Hard Disk AGP Graphics Port 4x tFlash aM l Figure 1 45 shows the typical positioning of the front panel extension modules for mouse key board COM1 COM2 and LPT interfaces Note A hard disk if installed will generally be fitted to the piggyback containing the combined PS 2 mouse keyboard USB2 0 COM1 and COM2 interfaces Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 15 Product Overview ICP CM 1 46 Construction 4HP Standard CPU This standard CPU configuration comprises Passively cooled base with chipset VGA graphics dual Fast Ethernet and single USB 2 0 interface for mouse keyboard FD CD ROM etc The minimum airflow requirements must be compatible with the selected processor speed CPU damage could result otherwise Figure 1 46 Construction of CPU with Heat Sink Assembly Page 1 16 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 47 Construction S8HP Standard CPU This standard CPU configuration comprises L4 Passively cooled base with chipset VGA
38. a smaller form factor and uses a different connector Table E1 20 shows the pinout of this connector Figure E1 20 J4 on the Underside of the AGP R7000 Piggyback gt E zN sis 77g 3 42 l aie e 13 eco pere F ele RE 6N ERE EIS O Oo en i S By EE ER UK CH LO e N gt sl S r EE LES 3 J gt a 2 KI i lk PageE 4 2004 Inova Computers GmbH ICP P4 PM CMAppendix E Appendix E AGP R7000 Table E1 20 J4 Pinout Signal Pin No Signal 1 USB6 5 VCC3 3 SDATA_OUT AD24 VDDQ1 5 ICP P4 PM CM Appendix E 2004 Inova Computers GmbH PageE 5 AGP R7000 Appendix E Table E1 20 J4 Pinout Contd DEVSEL 102 106 109 110 113 VGA R 114 117 118 Page E 6 2004 Inova Computers GmbH ICP P4 PM CMAppendix E Appendix E AGP R7000 E1 3 J3 amp J5 IBP GS MULTILINK TFT Interfaces To address an almost unlimited number of cascaded digitally connected GigaST R TFT displays with optional CAN control and PanelLink Slave connectivity the Inova GigaSTXR transmitter pig gyback IPB GS MULTILINK needs to be installed adjacent to the AGP piggyback This connection is made through connectors J3 and J5 on the upper
39. ability of the Intel 80x86 processors from Oh to OFFFFh All Inova CPU boards include peripheral devices requiring I O address space on board and hence the BIOS automatically assigns the I O address required by peripheral boards and PCI devices at boot time based on the requirements of each device The assigned addresses can be determined by reading the configuration address space registers using special software tools Table 2 10 Legacy 1 0 Map ISA Compatible UO Address Description 020 021 8259 Master Interrupt Controller 040 043 8254 Programmable Interval Timer 1 060 8042 Keyboard Controller 064 8042 Keyboard Controller 070 071 CMOS RAM NMI Mask Reg RTC 080 Debug 081 08B Low DMA page registers 0A0 0A1 8259 Slave Interrupt Controller 0CO 0DF 8237 DMA Controller 2 0FO 0FF 170 177 Secondary Hard Disk Controller 1F0 1F7 Primary Hard Disk Controller 2F8 2FF Serial Port COM2 Page 2 4 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Configuration Table 2 10 Legacy I O Map ISA Compatible Contd 1 0 Address Description 376 377 Secondary Hard Disk Controller 378 37F Parallel Port LPT 1 Bi Directional 3F0 3F7 Floppy Disk Controller 3F8 3FF Serial Port COM1 3F6 3F7 Primary Hard Disk Controller 481 48B DMA High Page Register 4D0 4D1 Interrupt Unit Edge Level Control Registers 778
40. alth of familiar standard PC interfaces A2 1 COM amp COMO Interfaces The two COM ports feature a complete set of handshaking and modem control signals maskable interrupt generation and highspeed data transfer rates The selection between the RS232 and RS485 serial data communication standard is performed via J1 amp J2 COM1 COM2 illustrated in Figure A1 2 Note If the COM ports are used in rear I O applications then they should not be used from the CPU front panel The front panel COM port connections are disabled automatically if using the rear 1 0 COM port option Figure A2 1 COM amp COM2 Interface Pinout Table A2 1 COM1 amp COM2 Connector Signals Signal RS232 RS485 DCD RxD Pin No Note The standard CPU configuration has both COM ports set for RS232 communication However this device can be configured to observe a two wire non galvanically separated RS485 protocol The data direction is governed by controlling the UART S RTS signal ICP PM CM Appendix A 2004 Inova Computers GmbH PageA 5 ICP HD 3 Appendix A A2 2 Mouse amp Keyboard Interfaces The physical PS 2 mouse amp keyboard interface is brought out on this 8HP front panel Connector pinout and description are provided in Figure A2 2 and Table A2 2 respectively Note If the mouse and keyboard ports are used in rear I O applications then they should not be used from the front panel Communicating fr
41. ar I O Also for compatibility with older backplane revisions 2 11 rear 1 0 C should be selected if indeed rear I O is required CPUs configured with rear I O D will not work Doc PD0094101 3 001 2004 Inova Computers GmbH Page1 7 Product Overview ICP CM Figure 1 21 ICP CM Board Overview Socket mPGA47SM for GOOMIHz or 32 bit and rear I O 1 3GHz Celeron M Processor 256MB or 1GByte on board DDR SDRAM IDE USB 2 0 COM PS 2 Floppy LPT Interfaces CompactFlash Socket USB 2 0 Fast Ethernet Host Bridge Fast Ethernet AGP 4x Socket for Inova Graphic Module VGA GigaSTxR TMDS DVI or TFT etc Reset Button amp Hot Swap LED Page 1 8 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 3 Software 1 31 Windows XP Professional Embedded Windows XP Professional Embedded contains many new technologies and features designed for businesses of all sizes and for users who demand the most from their computers It integrates the strengths of Windows 2000 Professional such as standards based security manageability and reliability with Plug and Play convenience simplified user interfacing and innovative support services This combination creates the best desktop operating system for businesses Whether Windows XP Professional is installed on a single computer or deployed throughout a worldwide network this new operating system increases comp
42. d 3 10 3 23 Graphic Features CCIDSe dames nent etienne 3 10 Table 3 23a highlights just some of the features of the standard integrated video controller 3 10 Figure 3 23 High Density D Sub VGA Interface Pinout saire sroine soniais 3 11 Table 3 23b Video Output Connector Signals Vs 3 11 2 24 19 USB Interface EE 3 12 Figure EE 3 12 Table e 3 12 3 25 110 Hot Swap Interface ciim bre ados amen e 3 13 3 26 SVV Reset BUTON Pe 3 13 3 27 J9 CompactFlash ON ACS ideae terns ben toc current 3 13 3 28 Connecting the CM to the Inova ICP HD3 ND eene 3 13 3 29 Connecting the CM to the Inova IPB FPE12 geegent Eege E ekeeg 3 13 3 30 Connecting the CM to a Slim Line Floppy Disk sees 3 13 A1 ICP HD 3CND CPU Extension A 2 A1 1 ICP HD 3 ND Front Panels 8HP or 12HP eese A 2 Figure TT ICP HD 3 ND CPU Front Panels eot trit deer tentata Pi ics A 2 A1 2 IDE Carrier Board ICP HD 3 ND sisi A 3 Figure A1 2 Interface Location of the ICP HD 3 ND Module essere A 3 Table A1 2 Interface Description of the ICP HD 3 ND Module seen A 4 Doc PD00941013 001 2004 Inova Computers GmbH Page 0 3 Preface ICP CM Ag ICP HD SC ND Interfaces A 5 AZ COW Sr CONG IBtenfaces nd debit dei A 5 Figure A2 1 COMT amp COM2 Interface PINOUE i uero ee etit steer eaten punk nuoto Lada A 5 Table A2 1 COM1 amp COM2 Connector Signals ss A
43. d triangle Note Damage to the CPU hard disk carrier board or the piggyback may result if the flex cable is positioned incorrectly Inova will not accept responsibility for negligent actions Figure B1 3 LPT1 Piggyback Board IPB FPE1 2 J13 Blue Flank Towe Note The physical connection of the IPB FPE12 is electrically identical regard less of the nature of connection stand alone or integrated ICP P4 PM CM Appendix B 2004 Inova Computers GmbH PageB 3 IPB FPE 12 Appendix E Table B1 3 IPB FPE12 Connector Description Connector Description J13 LPT1 B1 4 LPT Interface The physical LPT1 interface is either integrated into a 12HP CPU front panel or available as a separate 4HP unit The piggyback located behind this interface connects to the hard disk carrier board ICP HD 3 mounted J13 connector Figure B1 4 LPT1 Interface Pinout 13 d Table B1 4 LPT1 Connector Signals Signal Pin No Signal 1 STROBE 2 PDO PD1 4 PD2 PD3 PD4 PD5 PD6 3 5 7 9 por 10 ACK 13 SLCT 14 AUTOFD 15 ERROR 16 INT 17 em 18 25 GND PageB 4 2004 Inova Computers GmbH ICP P4 PM CMAppendix B Appendix C ITM RIO ITM RIO ITM RIO Contents C1 ITM RIO CPU Extension G 2 C1 1 ITM RIQ D GEES sn eee C 2 Table C1 10 Valid Rear 1 O Configurations deene eege dd Eed de ei C 2 Table C1 11 Rear 1 0 Module Functionality ans ene rei tonta to ri
44. e Inova IPB FPE12 interface is a small piggyback available as a stand alone device with its own 4HP front panel or integrated with the CPU as in figure B1 2 Figure B1 2 IPB FPE12 Stand Alone or Integrated with CPU D je 9 Dk Je ee Note Although COM2 is shown on the left hand stand alone front panel this interface will not be present in the delivered module A dust cap replaces the 9 pin D Sub connector eoeeeoeee eee RU If an LPT or slim line FD configured to communicate via the rear I O RIO transition module then the LPT inter face cannot be used here Trying to do so will result in data corruption and possible damage to the logic compo nents alinova Computers eJ IO Page B 2 2004 Inova Computers GmbH ICP PA PM CM Appendix B Appendix E IPB FPEZ2 B1 3 LPT1 Piggyback Figure B1 3 illustrates the construction of the stand alone IPB FPE12 piggyback and the upperside location of the J13 connector The same mechanical construction applies to the integrated ver sion Care should be taken to ensure that pin 1 of J13 on the CPU base board is linked by an appropriate length of flex cable to pin 1 on the ICP HD 3 piggyback To help with the orientation the connector flanks that are blue indicate the blue face of the flex cable Unmarked flanks indi cate the metallic connection of the flex cable Also pin 1 has been highlighted by a re
45. e Length ITM RIO D 0 See Matrix 1 1 Both Header Yes 80mm ITM RIO D 1 See Matrix 1 1 Both Header Yes 80mm ITM RIO D 2 See Matrix 1 1 FD A Keyboard Header Yes 80mm ITM RIO FHLU None 1 1 Header No 25mm All transition modules have reset and beeper pins Auto configuration RIO D feature can be overridden in BIOS Settings MUST be made manually if equipped with RIO C Page C2 2004 Inova Computers GmbH ICP P4 PM CM Appendix C Appendix G ITM RIO C1 2 ITM RIO Rear Panels 4HP or 8HP As with front panel I O the physical interfaces from the ITM RIO D x rear I O module are brought out to a face plate rear panel Figure C1 2 illustrates the three standard formats available at time of press Figure C1 2 The rear Panels of the Inova ITM RIO D x alinova e a 29 CD e E Q Di 8 d KEYBOARD Ly C J o e 16 5 re CI m e a a te S ETHERNET USB4 ETHERNET USB4 We E t e e og G s e Le S S FD COM1 amp COM2 LPT 1 The rear I O options described here do not detract from the latest PICMG 2 0 R3 0 specification The VGA option in table C1 10 can be from either the chipset or the AGP piggyback option Using the chipset graphics for both front and rear I O simultaneously is not advisable as the loading may be too great If both front and rear I O VGA are required then the
46. e hard disks may be connected directly to the base board 2 slot and possess their own front panel offering COM ports and combined PS 2 style connector for mouse and keyboard 1 03 Software The following operating systems are compatible with Inova s CM 3U CompactPCI CPU Linux Windows 2000 Windows XP Windows NT amp VenturCom RTX Real Time Extension On request Windows CE On request Windows 9x On request Windriver VxWorks On request QNX On request Esmeralda Technology Jbed under development On request Solaris x86 On request All readily available application software designed for operation on the standard x86 architecture will execute without modification 1 04 Graphics Built in to the ICP CM chipset is an analog VGA interface with BIOS configurable video RAM allocation extracted from the system memory Inova have also developed a number of ATI Radeon R7000 based dedicated AGP plug in modules complete with video controller and RAM etc for graphic intensive applications or to provide greater display flexibility Depending on the selected module MPEG 2 decoding sound functions GigaST R for distrib uted display communication PanelLink or TFT flat panel connectivity can be easily implemented Page 1 4 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Product Overview 1 1 Specifications Processor Memory FLASH Socket Phoenix BIOS Ver 4 x Rel 6 0 Battery Hos
47. en I EN tubae Eur D 2 Figure D1 1a Dedicated IPM ATA Backplane sien D 2 SUR KAES D 3 Figure D1 1b The Complete Connection Picture sen D 3 RAA CDI E D 4 Figure DK2IPM ATAMD Board e D 4 Table D1 2 IPM ATA HD Jumper Description CF Socket D 4 BELL D ld m D 5 Figure D 123 IPM ATASCF RE D 5 Table D1 3 IPM ATA CF Jumper Description suisses D 5 ay IPM ATA PCMCIA nn rhume nr mit aiesees D 6 Figure Di IPM ATA PCMCIA Board Eayolt iius oa tare itte rn rendra terere dip uR ias D 6 Table D1 4 IPM ATA PCMCIA Jumper Description sus D 6 D1 5 Device COMPARE net one D 7 fable DTS Compatibil MEISE orenian inae i EERE nettes nie it ion D 7 E AGP R7OOOQ CPU Extension E 2 Table E1 00 AGP Piggyback Configurations us E 2 Neuss MEE E 3 BU PA CAC c Em E 4 Figure E1 20 J4 on the Underside of the AGP R7000 Piggyback seen E 4 Table E1 20 EE E 5 Table ET 20 4 Pinout Te GE E 6 EL3 J3 amp J5 IBP GS MULTIEINK TFT Interfaces voee or fortis poner nine E 7 Figure E1 30 J3 and J5 Topside Connectors for the Inova IPB GS MULTILINK eene E 7 Table ET 30 3 amp J5 Interface PINGUL ergeet ninaa bey egeo sept usan vu poa eegen E 8 E1 4 J1 Front Panel VGA TMDS Interface E 9 Figure E1 40 Standard Front Panel VGA TMDS Interface essen E 9 Table E1 40 J1 Standard Front Panel VGA TMDS Pinout essere E 9 Table E1 41 J2 DIP Switch Settings Digital TMDS PanelLink or DVI D en
48. ents B1 IPB FPE12 CPU Extension B 2 BIO J13 Interface for EPT eege tenes Fea Recta vete verdes B 2 BIZ IPB FPE12 Front Panel 4HP or T2FIP sirena ehe neue B 2 Figure B1 2 IPB FPE12 Stand Alone or Integrated with CPU ss nisiirissiisssissiissssinsiriossisorinessssesonass B 2 BL S CPTI IQ ACM xcs a EE B 3 Figure BT 3 LPTT Piggyback Board IPB FPEI 2e dame ttt enit tete tette eniro e nS B 3 Table B1 3 IPB FPET2 Connector DescHplloh x teint EE B 4 B14 CPTI Interface OUT Tm B 4 Figure BT 4 LPTT Interface PINOUE iie tremere rar DEEL DEER Seege B 4 labie BTA EPTT Connector SIGH GIS ue ak terasse Sepe et oe eros poe Det stet ones ert ane poo tide B 4 ICP P4 PM CM Appendix B 2004 Inova Computers GmbH PageB 1 IPB FPE 12 Appendix E B7 IPB FPEA12 CPU Extension The Inova IPB FPE12 adds LPT functionality to any Inova Pentium M Celeron M or Pentium 4 M CPU The piggyback is available as a stand alone device with its own 4HP front panel or integrated within a 12HP front panel The information documented here is valid regardless of the connection choice B1 J13 Interface for LPT1 The control of the LPT interface is performed through the J11 connector on the CPU s hard disk carrier board The location of this connector may be determined by referring to Appendix A of this User s Manual The flex cable connection and function of the LPT interface are discussed in this section B1 2 IPB FPE 712 Front Panel 4HP or 12HP Th
49. ents an error in one application from bringing down the entire system and genuine multitasking means that a bottle neck in one application does not hold up the entire system Linux also maintains a very clean separation between user processes and kernel processes While other server class operating sys tems use protected memory this feature is prone to failure if faulty applications are allowed to invade kernel space with their processes 1 34 VentureCom Hard real time scalability and embedded operation extensions are required for Windows NT by HAL modification for deterministic interrupt handling at multiple priority levels This approach achieves response times in the us range and reduces hardware resource requirements while main taining full compatibility with the enormous range of standard software and device drivers written for the Windows NT operating system Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 9 Product Overview ICP CM 1 35 Windows CE Microsoft Windows CE is an operating system designed for a wide variety of embedded systems and products from hand held PCs and consumer electronic devices to specialized industrial con trollers and embedded communications devices The Windows CE operating system has proved itself capable of handling the most demanding 32 bit embedded applications by bringing the full power of the Microsoft s 32 bit programming and operating systems technology to the embed ded systems des
50. evices other than those from the manufacturers indicated in the table be chosen then it may be prudent that Inova be contacted prior to commissioning Table D1 5 Compatibility List Test Position Compact FLASH Card Jumper Result IBM Microdrive DMDM 10340 Master Passed Empty M Systems 64MByte Compact FLASH Master Passed Empty IBM Microdrive DMDM 10340 Slave passed IBM Microdrive DMDM 10340 Master incl Strip Set Config J3 3 J4 J3 IBM Microdrive DMDM 10340 Slave 4 Passed J4 M Systems 64MByte Compact FLASH Master J3 5 J4 IBM Microdrive DMDM 10340 Master Failed M Systems not M Systems 64MByte Compact FLASH Slave detected in BIOS M Systems 64MByte Compact FLASH Master IBM Microdrive DMDM 10340 Slave Note This module only supports ATA PCMCIA cards memory and cannot be used with WLAN modem GPS etc PCMCIA devices If one configuration seems not to work try swapping Master and Slave ICP P4 PM CM Appendix D 2004 Inova Computers GmbH Page D 7 IPM ATA Appendix D This page has been left blank intentionally Page D 8 2004 Inova Computers GmbH ICP P4 PM CM Appendix D Appendix E AGP R7000 AGP R7OOO AGHP R7OOO E1 AGP R7000 CPU Extension E 2 Tabie E1 00 AGP Piggyback ee EE E 2 E1 1 Specifications Mame rcr a iets E 3 E12 J4 Interface a NORTE E 4 Figure E1 20 J4 on the Underside of the AGP R7000 Piggyback esee E 4 Table EE E 5 Tagle E1 20 ee e
51. ew generation of real time operating system Java based innovation provides unprecedented safety and ease of use without compromising resource efficiency native processor speed or hard real time performance In addition advanced features are implemented such as modularity hot updates deadline driven scheduling admission testing as well as a fast and pro ductive cross development Page 1 10 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 4 Hardware 1 41 Block Diagram Figure 1 41 Block Diagram VGA PanelLink GigaST R TFT 400MHz oni rane Extension DDR266 LPT1 EY COM 2 Floppy USB 2 0 USB 2 0 lt Mouse lt Keyboard AC97 LPC Primary IDE ei Mouse Si ondary Keyboard Keyboard 8HP Extension f l HD Carrier l l SS Ses USB 2 0 10 100 Mbit s Ethernet 10 100 Mbit s Ethernet PCI Bus 32 bit 33MHz This block diagram is applicable to all Inova s CM based CPUs Components and or functionality may change without notice Note 32 bit with or without Rear I O RIO configurations are possible User s of NI peripheral cards should check to see whether signal conflict is possible with the RIO option selected If in doubt select the CPU version without RIO The universal PCI PCI bridge allows the CPU to exist as a Master or Slave Recognition is au
52. graphics dual Fast Ethernet three USB 2 0 interfaces combined PS 2 mouse keyboard COM1 and COM2 interfaces Behind the extended front panel is a platform for any IDE HD or Flash device with additional interfac ing for FD and LPT refer to Appendix A for further information The minimum airflow requirements must be matched with the selected processor speed CPU damage could result otherwise Figure 1 47 Construction of CPU with Heat Sink Assembly Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 17 Product Overview ICP CM 1 48 Construction SHP Standard CPU with AGP This standard CPU configuration comprises MM Passively cooled base with AGP 4x Radeon R7000 based graphics dual Fast Ether net three USB 2 0 interfaces combined PS 2 mouse keyboard COM and COM 2 inter faces Behind the extended front panel is a platform for any IDE HD or Flash device with additional interfacing for FD and LPT refer to Appendix A for further information The minimum airflow requirements must be matched with the selected processor speed CPU damage could result otherwise Figure 1 48 Construction of CPU with Heat Sink Assembly Note The dedicated carrier board ICP HD 3 is mounted to the baseboard in exactly the same fashion as illustrated in figure 1 47 It has been omitted here for clarity Page1 18 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM
53. he whole module plugs into the mating J12 J13 and J14 connectors 3 29 Connecting the CM to the Inova IPB FPE12 Appendix B provides more detailed information on the IPB FPE12 module However for the sake of completeness the IPB FPE12 connects directly to the ICP HD3 ND module via a flex cable There isn t a direct connection possibility on the CPU base board itself 3 30 Connecting the CM to a Slim Line Floppy Disk Slim line floppy disks connect directly to the ICP HD3 ND via the standard header Doc PD00941013 001 2004 Inova Computers GmbH Page3 13 Interfaces ICP CM This page has been left blank intentionally Page3 14 2004 Inova Computers GmbH Doc PD00941013 001 Appendix A ICP HD 3 ICP HD S ICP HD 3 Contents A ICP HD 3 ND CPU Extension A 2 A1 1 ICP HD 3 ND Front Panels 8HP or 12HP ne A 2 Figure A1 1 ICP AD 3 ND CPU Front Panels eet niente tnter tne RR thee e rb monster tartes este A 2 A1 2 IDE Carrier Board ICP HD 3S SINEDI ess icieee piis ses A 3 Figure A1 2 Interface Location of the ICP HD 3 ND Module A 3 Table A1 2 Interface Description of the ICP HD 3 ND Module A 4 Ag ICP HD SCND Interfaces CREER A 5 A2 1 COM1 amp COM2 Interfaces en a den A 5 Figure A2 T COMIT amp COM Interface Pinout sauces rie oir riin nini er tere iio A 5 Table A2 1 COM1 amp COM2 Connector Signals dsciaeticesdenederceesqnaacdsmeraseeessenraecoausndaancessanaaeeeevsei A 5 A2 2 Mou
54. ically if using the rear 1 0 COM port option Figure C1 4 COM1 amp COM2 Interface Pinout 1 5 o Table C1 4 COM1 amp COM2 Connector Signals Signal RS232 RS485 RxD TxD RxD TxD Note The standard CPU configuration has both COM ports set for RS232 communication Pin No However this device can be configured J7 and J8 to observe a two wire non galvanically separated RS485 protocol The data direction is governed by control ling the UART s RTS signal DCD TxD GND RTS aa Page C 6 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix C ITM RIO C 1 5 LPT1 Interface The physical LPT1 interface of the rear I O panel illustrated in Figure C1 2 connects to J9 on the baseboard for Note If the LPT port is used in rear 1 0 applications then it should not be used from the front panel Communi cating from both sources is physically possible but is not recommended Figure C1 5 LPT1 Interface Pinout Paseo 25 14 Table C1 5 LPT1 Connector Signals PDO PD2 PD4 PD6 ACK PE AUTOFD D ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 7 ITM RIO Appendix G C1 6 Mouse amp Keyboard Interfaces The physical PS 2 keyboard interface is brought out on either a 4HP or 8HP rear panel the mouse interface is only available on the 8HP version Figure C1 2 Connector pinout and description are provided in Figure
55. igner Windows CE is actually a collection of operating system modules and com ponents that can be selected and configured to meet the needs of a specific embedded applica tion or product 1 36 VxWorks WindRiver s run time system solution is a high performance RTOS with a scalable microkernel and sophisticated networking facilities like TCP IP networking across various media The open architecture provides efficient support of PC based architectures Flexible intertask com munication us interrupt handling POSIX 1003 1b real time extensions fast and flexible I O sys tem etc are some of the many key features 1 37 OS 9 x86 Microware s real time operating system has a track record that has been proved in the industrial embedded market and has continued to provide reliable intelligence to sophisticated applica tions OS 9 x86 s flexibility modularity and reliability in conjunction with a rich driver structure allow its use in I O intensive applications 1 38 QNX This solution ports the Win32 API to a QNX kernel The Win32 API aims to define a standard for developing open systems applications that are optimized to run on Wintel platforms This oper ating system evolves around a small microkernel RTOS that produces a protected mode POSIX certified API Being fully modular and scalable this technology creates the smallest footprint that is beneficial to high end server applications 1 39 Jbed Esmertec s Jbed is a n
56. igure 3 01 Naming Convention as per PICMG 2 0 R3 0 Specification s s s 3 2 3 02 CompactPCI JI Connector eege soap ote nitentes en Een Karger ren 3 2 Figure 3 02 J1 32 Bit CompactPCI Bus Interface Connector eese 3 2 3 03 ICP PM Connector J1 and KE 3 2 Table 3 03 32 Bit CompactPCI JT PIN ASSIGEIEDL esst degen rrt reb vr em e bs IEEE a 3 3 Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear I O D esses 3 4 Table 3 04 32 Bit CompactPCI J2 Pin Assignment Std with Rear I O D Contd 3 5 Table 3 05 Inova s ICP CM Rear 1 0 J2 CPU Integration 3 6 3 1 CompactPCI Backplane 3 7 Figure 3 10 Inova s 32 Bit CompactPCI 8 Slot Backplane RH System Slot sssssesseeseseeeseeess 3 8 3 2 InterfaceS unnsnsnuunuun nunnunnnununnunnnnn 3 9 3 21 J6 amp JZ ERNE EE 3 9 Figure 3 21 EE 3 9 Table 3 21 Ethernet Standards amp Connector Signals fe tre erbe epe re rire as 3 9 3 22 J17 VGA Interface ege Reeg EE Eder brem ekUP EB Ee Fed Pen 3 10 2 29 Graphic Features e E 3 10 Table 3 23a highlights just some of the features of the standard integrated video controller 3 10 Figure 3 23 High Density D Sub VGA Interface Pinout seen 3 11 Table 3 23b Video Output Connector Signals ss 3 11 3 24 19 USB Interface ors Hocker vetere sce he ist 3 12 Figure 3 24 USB Interface PIQUE nettes eege dE dee Breu 3 12 Table 3 24 USB Connector Sigrials ier et rese mee hn eene ee ey me
57. inal purchase price of the item for which any claim exists Inova makes no warranty or representation either expressed or implied with respect to its prod ucts reliability fitness quality marketability or ability to fulfil any particular application or pur pose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains the purchaser s In no event will Inova be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or docu mentation even if we were advised of the possibility of such claims prior to the purchase of or during any period since the purchase of the product Please remember that no Inova employee dealer or agent are authorized to make any modification or addition to the above terms either verbally or in any other form written or electronically transmitted without consent Page 0 8 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Product Overview Product Overview Overview Contents 1 0 ICP CM CDPU 1 3 ES OHM Talc ei EE EU eos 1 4 UBA 1 4 BEE 1 4 OCR E 1 4 1 1 Specifications 1 5 1 2 Functional Overview 1 7 Figure 1 20 Re ee E 1 7 Figure 1 21 ICP CM Board OvernieW issssseisncasigeesiasecessvnidion EE enitn e HR ies EE ge 1 8 1 3 Software ssss2s222222222222222222 1 9 1 31 Windows XP Profes
58. le DEE EE E 6 E1 3 J3 amp J5 IBP GS MULTILINK TFT Interfaces ss E 7 Figure E1 30 J3 and JS Topside Connectors for the Inova IPB GS MULTILINK eese E 7 Tagle ET 30 30 tee E 8 E1 4 J1 Front Panel VGA TMDS Interface E 9 Figure E1 40 Standard Front Panel VGA TMDS Interface cesses E 9 Table E1 40 J1 Standard Front Panel VGA TMDS Pinout ss E 9 Table E1 41 J2 DIP Switch Settings Digital TMDS PanelLink or DVI D eene E 10 Table E1 42 J2 DIP Switch Settings TFT 24Bit TTLCMOA E 10 E1 5 Rear TO VGA Interface este E 11 ICP P4 PM CM Appendix E 2004 Inova Computers GmbH PageE 1 AGP R7000 Appendix E E1 AGP R7000 CPU Extension The AGP R7000 is an Inova AGP 4x ATI Radeon based graphic extension for use with the ICP P4 ICP P4 M ICP PM and ICP CM CPUs By utilizing the power of the ATI Radeon 7000 equipped with 32MByte of SDRAM a graphic performance improvement of some 50 can be expected when compared to the on board chipset solution Able to drive analog VGA or PanelLink com patible monitors directly or connect to the IBP GS MULTILINK GigaST R transmitter with CAN routing for long distance digital data transfer the AGP R7000 suits the demands of modern indus trial automation engineering applications It is fabricated in 2 basic versions Analog VGA or digital DVI D TMDS Connectors J1 J3 and J5 are explained later in this section Table E1 00 A
59. n E 10 Table E1 42 J2 DIP Switch Settings TFT 24Bit TTLiCMOA eren E 10 AE Rear VO VGA Interface ec E 11 Doc PD00941 013 001 2004 Inova Computers GmbH Page 0 5 Preface ICP CM Unpacking and Special Handling Instructions This product has been designed for a long and fault free life nonetheless its life expectancy can be severely reduced by improper treatment during unpacking and installation Observe standard antistatic precautions when changing piggybacks ROM devices jumper set tings etc If the product contains batteries for RTC or memory backup ensure that the board is not placed on conductive surfaces as these can cause short circuits damage the batteries or disrupt the conductive tracks on the board Do not exceed the specified operational temperature ranges of the board version ordered If batteries are present their temperature restrictions must be taken into account Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board re pack it as it was originally packed Before returning this product for repair please ask for an RMA Returned Material Authorization number by submitting an email and supply the following informa tion a Company name contact person shipping address and invoice address a Product name and serial number EI Failure or fault description a Clearly write the RMA number on the outside of the transpo
60. nel one USB 1 1 is just behind the panel for local device connection custom two USB 2 0 are embedded within the hard disk carrier and a final USB 1 1 port is routed to the rear I O panel Note 64 bit configurations cannot have rear 1 0 Version D is preferred and is there fore the standard configuration Transi tion modules connect to the backplane and provide the physical interfaces Page 3 6 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Interfaces 3 1 CompactPCI Backplane The form factor defined for CompactPCI boards is based upon the Eurocard industry standard Both 3U 100 mm by 160 mm and 6U 233 mm by 100 mm board sizes are defined A Com pactPCI system is composed of up to eight CompactPCI cards The CompactPCI backplane con sists of one System Slot and up to seven Peripheral Slots The System Slot provides arbitration clock distribution and reset functions for all boards on the bus The System Slot is responsible for performing system initialization by managing each local board s IDSEL signal Physically the System Slot may be located at either end of the backplane but Inova have placed theirs on the right to cater for physical expansion due to heat sink hard disk extended function ality etc The Peripheral Slots may contain simple boards intelligent slaves or PCI bus masters Note Inova s 3U CompactPCI Celeron M CPU boards can be used as either master or slave boards
61. nt panel with 2x USB 2 0 COMI COM2 combined PS 2 mouse amp keyboard 12HP panel has LPT USB USB 2x RJ45 Ethernet 9 15 pin D Sub Graphic piggyback or 15 pin high density D Sub VGA Universal transparent non transparent PCI PCI bridge for Master Slave operation PICMG 2 0 R3 0 32 64 bit 33MHz system slot interface with 7 Master DMA support gt Full Hot Swap according to PICMG2 1 R2 0 3U 100 x 160mm x 21 42mm 4TE 8TE Typ 15W Windows XP Windows 2000 Windows NT Windows 9x Linux VxWorks QNX OS9 220g 4TE gt 220 000 hours 20 C O C to 65 C Std 40 C to 85 C Opt Passive cooling requires refer to Table 1 51 for details 40 C to 85 C 5 to 95 non condensing Three year limited warranty PICMG 2 0 R3 0 CE Notes CPUs fitted with HD FD or CD ROM etc have a max operational temp of 50 C Rear I O D necessitates backplanes being PICMG 2 0 Rev 3 0 compatible Page 1 6 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Product Overview 1 2 Functional Overview Figure 1 20 ICP CM Interfacing LPT1 com1 amp COM2 N BIOS FLASH Compact gt 30GByte Floppy Disk 1MByte FLASH Notebook HD PHOENIX Socket Primary Software Selectable IDE ATA 133 VGA or TFT or TMDS DVI Optional Abe AGP Multimedia Graphic Piggyback AC97 SOUND 400MHz IDE SECONDARY 32 MByte RAM PS 2 MOUSE
62. nter rupt generated by the timer creates an interrupt request on IRQO of the programmable interrupt controller PIC which is serviced by the CPU as interrupt vector 08h In addition Timer 1 and Timer 2 are also initialised by the BIOS as necessary for the specific processor board functions Table 2 80 Timer and Counter Functions Timer Function Assignment Timer 0 System Timer Periodic Interrupt 55 ms Timer 1 SDRAM Refresh Speaker Frequency Generator 2 9 Watchdog Two independent watchdog timers are implemented in the ICP CM The first timer residing in the SiS962 South Bridge has a range from 4ms to 255 hours and can issue either a Reset or SMI System Management Interrupt upon expiry The second timer in the Super I O controller ranges from 1 minute to 255 minutes and issues either a Reset IRQ or SMI upon timeout Note An OS specific driver is required to configure the watchdog timer Please refer to the Inova WWW support pages http www inova computers de web support public index html for the latest versions or contact Inova hotline support directly for advice Doc PD0094101 3 001 2004 Inova Computers GmbH Page 2 11 Configuration ICP CM This page has been left blank intentionally Page2 12 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Interfaces Interfaces Interfaces Contents 3 0 CompactPCI J1 J2 Connectors 3 2 3 01 CompactPCI Connector NM nus 3 2 F
63. om both mouse and keyboard sources is physi cally possible but is not recommended Figure A2 2 Mouse amp Keyboard Interface Pinout Table A2 2 Mouse amp Keyboard Connector Signals Pin No Signal GE mm Ecc eem Keyboard 6 Geck Mouse PageA 6 2004 Inova Computers GmbH ICP PM CM Appendix A Appendix A ICP HD 3 Ag 3 USB 2 0 Interfaces Standard to all ICP HD 3 carrier board modules are the two USB 2 0 interfaces which are back ward compatible to USB 1 1 devices Figure A2 3 USB Interface Pinout Table A2 3 USB Connector Signals ICP PM CM Appendix A 2004 Inova Computers GmbH PageA 7 ICP HD 3 Appendix A A2 4 EIDE Interface Standard to all ICP HD 3 carrier board modules is the 3 5 EIDE hard disk header This has a standard commercial PC pinout and requires no further mention here Note To conform with the UDMA 66 or higher standards only suitable commercially available 80 strand ribbon cable should be used Failure to do so may result in data transmission errors or even cause the CPU to crash A2 5 Slim Line Floppy Disk Interface Standard to all ICP HD 3 carrier board modules is the slim line floppy disk header This has a standard commercial PC pinout and requires no further mention here PageA 8 2004 Inova Computers GmbH ICP PM CM Appendix A Appendix E IPB FPE12 IPB FPE 12 IPB FPE12 Cont
64. onfiguration The CompactPCI specification defines a total of six interrupt signals on the backplane INTA through INTD are used to route interrupts from the CompactPCI boards to the PIC on the proc essor board The interrupt request level generated by the device depends on the backplane slot number which the board is plugged into and the interrupt signal which is driven by the particular PCI device Note CompactPCI interrupts may be shared by multiple sources Table 2 70 CompactPCI Bus Interrupts CompactPCl Bus Interrupts INTA INTC INTP IRQ14 IRQ15 or Serialized INTS Interrupt Refer to BIOS ENUM Documentation Routed by BIOS Note Interrupts INTA through INTS and ENUM are System Master CPU inputs INTA and ENUM are outputs if the CPU is in Peripheral Mode Page 2 10 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Configuration 2 8 Timer Counter The IBM compatible architecture configures the programmable timer counter Intel 8254 com patible devices for system specific functions as shown in Table 2 80 The BIOS programs Timer 0 to generate an interrupt approximately every 55ms 18 2 times per second This interrupt known as the system timer tick updates the BIOS clock and turns off the floppy disk motor drive after a few seconds of inactivity for example The BIOS featured in Inova s CPUs programs the system timer tick for PC compatibility The i
65. p USB 3 9 Pin D Sub 9 Pin D Sub 25 Pin D Sub integrated within the 12HP panel only Standard notebook header for slim line floppy interface Note The ICP CM Hard Disk carrier ICP HD3 Refer to Appendix A has jumper selectable COM configurations either R 232 or R 485 Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 13 Product Overview ICP CM Figure 1 44 Front Panel Options Pm YV S EEN 41 USB USB2 A Je PS 2 ee hee J ei H d H o alinova alinova Computers Computers The front panels shown in Figure 1 44 show the tremendous flexibility built into Inova s CPU concept From left the standard CPU is ATE with dual Fast Ethernet USB 2 0 and VGA graphic connections If instead of VGA graphics PanelLink or GigaST R is required then an AGP piggy back is installed on J4 for this purpose TFT graphics are realised in a similar way except the front panel will be cut away to the right of the VGA connector to permit passage of the flat band ribbon cables If the application requires a PS 2 mouse PS 2 keyboard floppy COM or LPT ports or if the CPU is equipped with a hard disk IDE FLASH or an adapter that accesses other devices attached to this primary IDE channel then an 8TE front panel is selected Both COM ports jumper selectable to be RS232 or RS485 are installed on Inov
66. ription is D 5 DT IPMSATA PCMIIA E D 6 Figure DH IJPM ATA PCMCIA Board EGyout iussisset eie re eer e te te Ge ie D 6 Table D1 4 IPM ATA PCMCIA Jumper Description ss D 6 ARENS D 7 IS Ree TTT D 7 ICP P4 PM CM Appendix D 2004 Inova Computers GmbH Page D 1 IPM ATA Appendix D D1 IPM ATA CPU Extension Inova Plug In Module IPM offers the user the ability to exchange a hard disk for example with out having to remove the CPU from the CompactPCI enclosure and then dismantle it etc Cur rently three units exist that provide industry with hard disk Compact FLASH MicroDrive or ATA PCMCIA format mass storage capability D1 1 rJ2 Interface All IPM ATA modules possess rJ2 for data communication between the CompactPCI backplane and the mass storage unit s in question Figure D1 1a illustrates the dedicated IPM ATA backplane and connectors Note The IPM ATA modules can only be used in CompactPCI systems that have been prepared for rear 1 0 or have the IDE signals available on the rear rP2 connector that are in accordance with the specification for RIO In addition the rear rP2 CompactPCI connector must be present Figure D1 1a Dedicated IPM ATA Backplane cece p N JI H THEE PageD 2 2004 Inova Computers GmbH ICP PA PM CM Appendix D Appendix D IPM ATA D1 1 rJ2 Interfaces Contd Standard 80 pin
67. rtation carton Page 0 6 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Preface Flevision Flistory Revision History Manual Publication Number Issue Author Date of Issue PD00941013 001 AB 26 07 2004 Doc PD00941 013 001 2004 Inova Computers GmbH Page 0 7 Preface ICP CM Three Year Limited Warranty Inova Computers Inova grant the original purchaser of Inova products the following hardware warranty No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova Inova warrants their own products excluding software to be free from defects in workmanship and materials for a period of 36 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product This warranty does not cover products which have been modified altered or repaired by any other party than Inova or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence misuse incorrect handling servicing or maintenance or has been damaged as a result of excessive current voltage or temperature or has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty A customer who has not excluded his eligibility for this
68. se er Keyboard JOER Geer Ee ee A 6 Figure A2 2 Mouse amp Keyboard Interface Pinout seen A 6 Table A2 2 Mouse amp Keyboard Connector Signals esses eene A 6 Table A2 3 USB Connector Signals torte meret i ed iet ote dia Fue Ea Re die A 7 BD S USB 2 0 Interfat eS Loo eee waists n tbt co un Od ot bu ga cio Delle ceti A 7 Figure A2 3 USB le EE A 7 A2 4 EIDE Interface M rr gege eege eebe A 8 A2 5 Slim Line Floppy Disk Interface errors A 8 ICP PM CM Appendix A 2004 Inova Computers GmbH PageA 1 ICP HD 3 Appendix A A1 ICP FID 3CND CPU Extension Combined PS 2 mouse keyboard USB 2 0 COM ports LPT mass storage and slim line FD interfaces are supplied on the ICP HD 3 ND a CPU add on board Two versions exist one is supplied with a hard disk and one without Both versions are functionally identical The name extension ND refers to the No Disk version All communication between the ICP HD 3 and the host CPU is performed via rigid board connec tors there aren t any flex cables on the CPU board itself This concept eliminates the risk of incorrect device installation and ensures both mechanical and electrical stability A1 ICP HD 3C ND Front Panels BHP or 12HP The Inova ICP HD 3 ND interface is a mass storage carrier board that is only available as a CPU plug in device with either an 8HP or 12HP front panel as illustrated in figure A1 1 Figure A1 1 ICP HD 3 ND CPU Front Panels
69. side of the piggyback as shown in figure E1 30 Table E1 30 gives the pinout of these two connectors The settings of the DIP switch J2 are explained later Figure E1 30 J3 and J5 Topside Connectors for the Inova IPB GS MULTILINK Uu SH w g Sie 2 m 8 JARS on H mi E B E zs lt se DEXIA gt Se CH e al CE aea E a et Reco sov CL N Ol 2 8 IR S5 ca 3 C vv ele le SE pep EEE IE CH RBE L mea a oz Ka E a n ize EE RTE x a EJ lS SIS n 83 SG EC Ges slelis ER T cord GORE a DE y T 619 8913 e Ln A 183 e D g Fe oza To Sr i se rfe S tz e gt BST SES eed eo e 2 Hus org Si amea GO Borg Fe ma w Gi a sr S D qs q a iti CYN E Lyn e o e z O SO 2 We N JI2
70. sional Embedded ccccccessseeeeeceeceeeeeeseeeeeeenes 1 9 1 32 Windows 2000 Professional 1 9 DECOR UD c E 1 9 US Bii n T 1 9 US VMS E 1 10 US en 1 10 US SAS ER X86 cree ccc HH 1 10 ToS ONA E 1 10 US E EE E E E E 1 10 Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 1 Product Overview ICP CM 1 LI 4 Hardware CRW 71 41 1 I INL roc V 1 11 Figure 1 41 Block DIOGFIW eret ertet m erronee erp ee pie PH Re cepe REY 1 11 1 42 Connector LOCATON sei Cr p 1 12 Figure 1 42 Connector Locations o isset ee bete Etre e Saeed de EE dee Fre Ee Vl n nene OPE Fue EIUS 1 12 1 43 Connector Description m L 1 12 Table 1 43 Connector DescripliOn ieni secco investi ee eni rene o vere teneret 1 12 Table 1 43 CONNUE eror rom tede imn in Penes edem eei Aeddi ege eege deu 1 13 1444 Front Panel i C 1 13 Table 1 44 Front PANELS e oiopeieertit rite rit nier PE uev SUPERNE EY e PER PE UEM EIE te 1 13 Figure T 44 FrontsPanel DOES uide teret ete eth ente ette eee dr nene nene eeu Fein t PE eap nni 1 14 1 45 nterface POSItIONS m 1 15 Figure te RL 1 15 1 46 Construction 4HP Standard CPU nd setierens 1 16 Figure 1 46 Construction of CPU with Heat Sink Assembly 1 16 1 47 Construction 8HP Standard CPU 1 17 Figure 1 47 Construction of CPU with Heat Sink Assembl
71. socket suitable for use by all 3rd party Micro Drive devices or solid state FLASH that adhere to the interface standard Serviceability and user friendliness feature throughout the CPU design and is highlighted in the lack of on board cabling all interconnects are hard wired An optional dedicated hard disk carrier with integrated COM ports twin USB 2 0 and PS 2 mouse and keyboard interfaces connects directly to the base CPU Naturally for space critical applications these interfaces are available as rear I O effectively extending the standard 160mm card by a further 80mm Notebook hard disks are selected for their high capacity small footprint rugged operating conditions and higher operational temperature characteristics Doc PD00941013 001 2004 Inova Computers GmbH Page 1 3 Product Overview ICP CM 1 01 Interfacing To satisfy today s LAN hungry industrial applications Inova have implemented dual independent 100BaseTx LAN Fast Ethernet interfaces as standard on the CPU s front panel or fed to a rear I O transition module on the backplane Connectivity is further enhanced through the integration of the latest USB 2 0 serial interfaces that permit a number of readily available peripherals such as mouse keyboard floppy drives and even CD ROMs or printers to be utilized without compromizing front panel width 1 02 Peripherals The ICP CM supports standard PC peripherals floppy disk hard disk and CD ROM Notebook styl
72. speeds the volume of air required to cool the core becomes so great that conventional cooling fans cannot be used Table 1 51 ICP CM Airflow Requirements Ambient Air Temperature Frequency lt 55 C lt 65 C lt 75 C lt Re m E OHP AHE HP AHP without 0 15 0 4 0 5 0 75 iid o ns EXE mi 1300MHz 0 35 0 55 Ge mis m s S m s Key C Not recommended Note If the ambient temperature is greater than 50 C systems utilizing the benefit of this Celeron M CPU cannot operate with a standard hard disk floppy or CD ROM etc Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 21 Product Overview ICP CM This page has been left blank intentionally Page 1 22 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Configuration Configuration Configuration Con tents 2 0 Memory Map 2 2 Figure 2 00 System E 2 2 2 1 l D Mapped Peripherals 2 4 Table 2 T0 Legacy VO Map ISA Compatible 5 5 etta erento S Photon o rea perpe Piste erp eee PP ait 2 4 Table 2 10 Legacy I O Map ISA Compatible Contd su 2 5 2 2 Memory Mapped Peripherals 2 6 2 3 Interrupt Routing e 8 Table 2 30 PC AT Interrupt Definitions ive rere er iret ett e EE Pr E eR e RESP t SE ETUR 2 7 2 4 DMA Channel Descriptions 2 7 Table 2 40 DMA Channel DescripLIOn ses acoso einn terere red a ruv da ume eut ere dU Eu EE tas 2 7 2 5 Inova CM SMB Devices
73. t Bridge South Bridge Super 1 0 Graphic Option 600MHz or 1 3GHz Socket mPGA479M mobile Intel Celeron M with 400MHz PSB 512kByte L2 cache passive or active cooling Either 256MByte or 1GByte soldered 266MHz DDR SDRAM For CompactFlash devices Flash amp MicroDrives providing gt 4GByte mass storage capacity LAN Boot USB Boot b ACPI 2 0 b Quick Boot Multi Boot gt Quiet Boot Lithium cell for RTC NV RAM with a lifetime gt 10 years SiS651 North Bridge supporting gt 400 533MHz FSB to CPU 333MHz 64 bit DDR DRAM controller VGA interface 2048 x 1536 pixels AGP 4x interface Power management SiS962 P PCI Bus 32 bit 33MHz Mouse amp keyboard controller Fast Ethernet gt USB 2 0 b AC97 bus sound gt LPC bus to Super I O amp BIOS IDE Controller 2 independent IDE channels each supporting 2 devices Ultra DMA 133 support Real Time Clock Watchdog programmable up to 256 hours issues SMI or Reset Interrupt controller Power Management Unit PC87393 Floppy Disk Controller 1 Parallel Port ECP EPP 2 serial COM Ports Watchdog Onboard video controller chipset with BIOS selectable video RAM allocation Support for MPEG 2 video playback gt Support for VESA standard super high resolution graphics modes gt Support for low resolution modes 320x240 512x384 400x300 gt Supports VESA Display Power Management Signalling Supports Direct Dra
74. the ICP HD 3 ND Module Connector Description COM is configured for RS232 communication COM1 is configured for RS485 communication COM2 is configured for RS232 communication COM is configured for RS485 communication COM2 physical interface Reset shorting these pins causes the CPU to reset PS 2 mouse amp keyboard physical interface USB 2 0 physical interface USB2 COM physical interface Slim line floppy disk interface The CompactFlash on the CPU is Master The CompactFlash on the CPU is Slave Flex cable interface for LPT1 IPB FPE12 module Standard 3 5 EIDE interface 80 strand cable only USB 2 0 physical interface USB3 The accessibility maintainability of the mounted hard disk is ensured through the two fixing screw cutouts on the carrier board A mounted hard disk is thus unable to shift or become dis lodged in any direction Note Any notebook style IDE hard disk Flash device or similar mass storage unit can be connected here However Inova recommend only those devices from known manufacturers Connecting devices to both J9 and J12 simultaneously is not recommended A better configuration is to use Master and Slave devices connected to J12 only or use the Rear 1 0 feature PageA 4 2004 Inova Computers GmbH ICP PM CM Appendix A Appendix A ICP HD 3 Ag ICP HD S ND Interfaces The carrier board serves not just to mount an IDE mass storage device it also provides the user with a we
75. tomatic depending on the CPU s physical position within a CompactPCI system Doc PD0094101 3 001 2004 Inova Computers GmbH Page 1 11 Product Overview ICP CM 1 42 Connector Location Figure 1 42 Connector Locations 1 43 Connector Description Table 1 43 Connector Description Connector Description J1 J2 CompactPCI Interface Connector AGP 4x for Optional Inova Graphic Piggyback 10BaseT 100BaseTx Fast Ethernet Interface ETH2 SiS 900 chipset 10BaseT 100BaseTx Fast Ethernet Interface ETH1 i82551 CompactFlash Socket MicroDrive or Flash Page1 12 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Product Overview Table 1 43 Continued Connector Description J11 Internal USB 1 1 interface for additional USB devices USB 5 J12 J13 J14 Hard Disk module Mouse Keyboard COM FD USB 2 0 and LPT1 interfaces External USB 2 0 interface USB 1 VGA interface soldered D Sub for onboard Chipset or from AGP piggyback Reset button switch 1 44 Front Panel Features Table 1 44 Front Panels Interface Description amp Location Ethernet 2x RJ45 connector common to all CPU front panels USB 2 0 connector on all CPU front panels USB 1 VGA Space for 15 Pin high density D Sub connector on all CPU front panels Push button reset on all CPU front panels Extended Front Panel Options 8HP amp 12HP Mouse amp re Single PS 2 style connector Two USB 2 0 connectors USB 2 am
76. torta ken 1 16 Figure 1 46 Construction of CPU with Heat Sink Assembly sess 1 16 1 47 Constr ction 8HP Standard CPU esse editions 1 17 Figure 1 47 Construction of CPU with Heat Sink Assembly ssssseessseesseesesesssesssserisseresrrreseress 1 17 1 48 Construction 8HP Standard CPU with AGP 1 18 Figure 1 48 Construction of CPU with Heat Sink Assembh 1 18 1 49 Power REQUIDEINIGING acre etes etie Ri M Pasa dt nee benmon meteo 1 19 Table 1 49 ICP CM Power Regirements eene eot rtt erento rore erae 1 19 1 50 Ne ale 1 20 Figure 30 1CP CM Power CORSUMPDHON serre tee terrier nr i ue E dares 1 20 USA Ree En EE 1 21 Table 1 51 ICP CM Airflow Requirements us 1 21 2 0 Memory Map usua ui ioci aic RR RR KN 2 2 Figure 2 00 SYSTEM AC NETUN senken ines reperit weder p Eege ege 2 2 2 1 1 0 Mapped Peripherals 2 4 Table 2 10 Legacy 1 0 Map ISA Compatible eorr tierra retreat th ra aiana 2 4 Table 2 10 Legacy I O Map ISA Compatible Contd sees 2 5 2 2 Memory Mapped Peripherals 2 6 2 3 Interrupt Routing e 8 Table 2 30 PC AT Interrupt Definitions sise 2 7 2 4 DMA Channel Descriptions 2 7 fable 2 40 DMA Channel DeSCHDLION sarin ir pae vr ER rra mtd rat Pa a eT Pez d vds 2 7 2 5 Inova CM SMB Devices 2 8 et 2 8 2 6 Inova CM PCI Device List 2 9 Table 2 60 Legacy I O Map ISA Compatible sess 2 9 Page 0 2 2004 Inova
77. ts to the CPU In the PC AT architecture one PIC is programmed as the master with one input IRQ2 being the cascaded interrupt from the second slave PIC This configuration allows for a total of 15 interrupt sources to the CPU Table 2 3 shows the interrupts with their corresponding vectors and sources as defined for AT PCs Page 2 6 2004 Inova Computers GmbH Doc PD0094101 3 001 ICP CM Configuration Table 2 30 PC AT Interrupt Definitions Interrupt Request Interrupt Vector Function Assignment IRQO IRQ1 IRQ2 08h OAh OCH OEN Timer Keyboard Slave 8259 COM 1 Free for PCI IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 70h Real Time Clock IRQ9 Free for PCI IRQ10 Free for PCI IRQ11 Free for PCI 72h IRQ12 74h Mouse IRQ14 76h Hard Disk IDE 0 IRQ15 Hard Disk IDE 1 Entries may be reserved for ISA devices with the BIOS 2 4 DMA Channel Descriptions The ICP CM CPU can access the devices shown in table 2 4 through the specified DMA channels Table 2 40 DMA Channel Description DMA Channel Description Floppy LPT1 ECP only Doc PD00941 013 001 2004 Inova Computers GmbH Page2 7 Configuration ICP CM 2 5 Inova CM SMB Devices Table 2 50 shows the addressing of the SMB System Management Bus Devices Table 2 50 SMB Devices Address b 7 1 Device 0101 100 LM87 Temperature Monitor 1010 000 EEPROM SPD DDR Bank 0 1010 101 EEPROM TOP EXTENSION e g ICP HD 3 ID
78. uting power while lowering the cost of own ership for desktop computers 1 32 Windows 2000 Professional Windows 2000 is highly reliable and available 32 bit OS which provides support for USB devices and permits connection of peripherals without the need to reboot the system Unlike Windows NT 4 0 support is also provided for the IEEE1 394a FireWire devices Finally secure wireless commu nication between two Windows 2000 based computers is possible using the popular IrDA infrared protocol Removable storage devices such as DVD and Device Bay are supported as are new display devices such as Accelerated Graphics Port AGP multiple video cards and monitors OpenGL 1 2 DirectX 7 0 API and Video Port Extensions With Plug and Play automatic installation of new hardware is possible with only minimal configuration More than 12 000 devices support this functionality 1 33 Linux Being a modern operating system Linux executes a 32 bit architecture uses pre emptive multi tasking has protected memory supports multiple users and has rich support for networking including TCP IP Linux was originally written for Intel s 386 architecture but now runs on a wide variety of hardware platforms including the full x86 family of processors as well as Alpha SPARC and PowerPC Linux s architecture also creates a more reliable and inherently stable system through the use of protected memory and pre emptive multitasking Protected memory prev
79. ving to disassemble the CPU Two slim line notebook floppy interfaces are implemented allowing the module to be compatible with existing Inova PIII CPUs with RIO C as well as the P4 PM and CM family The integration of USB 1 1 with both the standard connector and notebook style internal con nector facilitates the integration of commercially available FDs or similar devices The signal de scription of the standard connector can be obtained by referring to page C 11 Figure C1 12 ITM RIO C amp D FHLU Behind the USB Connector USB Q Internal ICP P4 PM CM Appendix C 2004 Inova Computers GmbH Page C 13 ITM RIO Appendix G This page has been left blank intentionally Page C 14 2004 Inova Computers GmbH ICP P4 PM CMAppendix C Appendix D IPM ATA IPM ATA IPM ATA D1 IPM ATA CPU Extension D 2 DEP AIMONS oe ris terea vite ma ERE ERE EH ERE PU ROC PREX E Fi M Uca D 2 Figure D1 1a Dedicated IPM ATA Backplane ss D 2 D1 1 rJ2 Interfaces CON tm D 3 Figure DI 1b The Complete Connection PICture usines D 3 DA IPA TAHT Se none D 4 Figure D 1 2 JPM ATA HD Board Eayoul 5i etit reti vi etri ere rent D 4 Table D1 2 IPM ATA HD Jumper Description CF Socket D 4 PIA UE a p D 5 Figure EN JPM ATA CFP Board EGyOUL esci et tice eee lu e oti ter RR ve eee tt eng D 5 Table D1 3 IPM ATA CF Jumper Desc
80. w Drivers gt Supports single video windows with overlay function or AGP 4x Piggyback R7000 with 32MByte RAM 3D graphics DVD amp MPEG 2 support Multi Display PanelLink amp TFT support GigaST R support Sound support Dual View support under Microsoft Windows 9x Windows 2000 amp XP CRT TFT resolutions up to 2048x1536 www ww www Doc PD0094101 3 001 2004 Inova Computers GmbH Page1 5 Product Overview ICP CM Fast Ethernet PCI PCI On Board 1 0 Rear 1 0 Mass Storage Front Panels Connectors CompactPCI Mechanics Power Cons Software Sup port Mass MTBF Oper Temp Storage Temp Humidity Warranty Conformance Additional 82551 controller Universal bridge Master or Slave Serialized interrupts Universal 3 3 5 0V V 1 0 support 32 bit and Rear I O gt Dual 10 100 Mbit s Fast Ethernet gt 1x front panel 480Mbit s USB 2 0 1x rear panel 12Mbit s USB 1 1 VGA chipset or AGP Standard to all CPU variants is option D VGA chipset or AGP if installed P Fast Ethernet ETH 1 Intel 82551 gt USB 1 1 PS 2 mouse amp keyboard P 2 DE channel Master amp Slave gt Software configurable gt LPT1 or COMI amp COM2 or Floppy disk A or B BIOS selectable Reset amp Beeper 1 44MByte 3 5 floppy drive and EIDE standard 40 pin header 80 strand ATA 5 compatible supporting 2 pairs Master Slave hard disks or CD ROMs 8HP fro
81. y ssesssseeeeeeeeeresrreerrrrreerrrereerrrrreeers 1 17 1 48 Construction 8HP Standard CPU with AGP 1 18 Figure 1 48 Construction of CPU with Heat Sink Assembly 1 18 1 49 Power Requirements m 1 19 Table 1 49 ICP CM Power Regirements usines 1 19 1250 Power Ee E 1 20 Figure 1 50 JCP CM Power Cons E 1 20 1 51 Thermal Considerations seistes heard rro in Ebai praestes 1 21 Table 1 51 ICP CM Airflow Requirements is 1 21 Page 1 2 2004 Inova Computers GmbH Doc PD00941013 001 ICP CM Product Overview 1 0 ICP CM CPU Cutting edge technology makes the Inova Socket mPGA479M Celeron M single board compu ter the ideal controller for a wide range of embedded low power industrial automation military medical aerospace imaging telecommunications process control and embedded OEM applica tions Without altering the design Master or Slave ICP CM CPUs can be operated in an industrial environment through their ability to detect automatically the backplane system controller or pe ripheral slot In addition the ICP CM family can communicate at very high speed with up to 255 x 7 cascaded peripherals like graphics industrial I O or fast data acquisition modules on inter linked passive backplanes The powerhouse in any application Inova s Socket mPGA479M based high performance 3U Com pactPCI CPU is packed with a feature set unrivalled in industry on such a small scale Configured with up to 1GByte onboard 266MHz DDR SDRAM the ICP CM

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