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HP 8010A User's Manual

1. 16 31 1854 0329 TRANSISTOR SILICCN NPN A 10 32 1854 C215 TRANSISTOR SILICON NPN 2N3904 A 33 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 16 34 1853 0034 TRANSISTUR SILICUN PNP LG 35 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 14 36 1853 0036 TRANSISTOR SILICON PNP 2N3906 A 10 37 1854 0329 TRANSISTOR SILICCN NPN A 16 38 1853 0036 TRANSISTOR SILICON PNP 2N3906 A 18 1 0757 0726 R FLM 511 OHM 12 1 4W A 18 2 0757 0726 511 OHM 17 1 44 A 18 3 0757 0398 MET FLM 75 OHM 1 1 8W A 18 4 0698 4247 510 OHM 5 1 8W 18 5 0698 3441 FLM 215 UHM 17 1 8W A 18 6 0757 1097 R MET FLM 1200 OHM 1 1 8w A 18 7 0698 4265 R FLM 3000 OHM 54 1 8w A 1R 8 0757 0283 FXD FLM 2000 OHM 1 1 8W i A 18 9 0758 0070 R FLM 1200 OHM 5 1 4W A 18 10 0757 0433 R 3320 OHM 1 1788 A 18 11 0698 4254 R FLM 1000 OHM 5 A 12 0758 0086 R FLM 100 OHM 5 1 4W A LR 13 0698 4226 FLM 62 OHM 5 1 84 A 1 14 0757 0746 FLM 4750 OHM 1 1 4W A 18 15 0757 0746 MET 4750 OHM 1 1 44 A 1R 16 0698 4261 R FLM 2000 OHM 57 1 84 A 1R 17 0698 4254 R FLM 1000 OHM 5 1 84 A 1R 18 0698 3446 R
2. C O o o O 0 P p P P Q Q G Q P p p gt gt e gt gt P gt P P 2 20 0 0 x 9100 1651 9100 1630 9100 1630 9140 0118 9170 0029 9170 0029 9170 0029 1853 0090 1853 0090 1854 0091 1853 0001 1854 0307 1854 0053 1854 0005 1854 0260 1853 0203 1854 0019 1853 0203 1853 0097 1853 0097 1853 0097 1853 0097 1854 0329 1854 0039 1853 0090 1854 0329 1854 0307 1854 0307 1853 0012 1853 0012 5080 1032 5080 1032 5080 1032 5080 1032 1853 0090 1854 0053 1854 0053 0698 5330 0758 0002 0698 5891 0698 5891 0698 4278 0698 4278 0698 4278 Table 4 1 FXD 750 0 UH 5 COIL FXO 51 0 UH 57 CCIL FXD 51 0 UH 52 COIL 5 COKE FERRI CORE FERRI CORE FERRI TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR FXD FLM FXD FLM FXD FLM FXD FLM FXD FLM FXD FLM FXD FLM 00 UH 51 TE 8EAD TE BEAD TE BEAD SILICON SIL ICON SICICON SILICON SILTCON SILICON SILICON SILICON SILICON SILICON SILICON SILICON SIL
3. SECTION rma S 32 EN 10099 SCHEMATIC 05 90 2 DELAY MODE 25 Ww SWITCH 519 5 8 E 918 TO A204 20V 8 015 2 22 C38 ef C7 cii i T CRI9 FN ar 15 ra go 243 CR20 5 00 NN gt z REFERENCE DESIGNATIONS 017 9 CR8 C4 7 10 21 35 2 2 CRBS 17 20 BEAD 12 3 Q5 7 14 20 28 2 0 d 20V 2157 937 NO PREFIX Al2 R52 R18 J1 R1 2k 383 J3 S1 R54 470 CR12 CR11 CR13 CB 0 CRM R22 24K CR15 Figure 5 13 Rep Rate and Gate Input Circuit 4 65 CR9 GATE INPUT CR10 2 2820 R19 19K COPYRIGHT 1370 BY HEWLETT PACKARD GMBH amp 10A TIMING BOARD 958 3 igit 3 24 30 or fe x aii xS Sa Model 8010A Al TIMING BOARD 08010 66501 ee FROM REP RATE SWITCH A12 923 SQUARE 58 1 CHANNEL A SQUARE PIO 99 L 1 PULSE 26 CHANNEL B NOTE 1 LEAD COLOURS 9 3 4 AND 9 2 6 SHOWN TWICE FOR CLARITY ARE INFACT BOTH SINGLE LEADS 25V 25 25V 860 yas 25 m L5 1uH R76 100 25V C29 3880 25 560 5 4 4 R73 10K CR26 CR27 25V R74 10K 25V 20V 16 R61 2 2uH 390 1005 2100 430 9 022 25V 584 811 215
4. OHO Hwa IINE 08010 66509 Section V Figure 5 10 Assembly 9 Component Location Figure 5 10 Section V Figure 5 11 119 el OU we saa bag OL JO 08010 66511 Model 8010A 8010 4 13 Assembly 11 Component Location Figure 5 11 Section V yr Figure 5 12 1 TIMING BOARD 08010 66501 25 5 m 5 lt M 20V 20V 20V SCHMITT 5 E iM o TRIGGER 510 Al R99Q37 Q3 and Q4 p x 1 A TO REP RATE GEN C12 LK g 02 151 di 9 0 6 5 g w e d 2 m l 20V P O A12S1 C3 5 R12 4 100 10 WV m x 25V CT d R7 516 REFERENCE DESIGNATIONS g 5 E 1 235V 8010A TIMING BOARD 958 Figure 5 12 Trigger Input Circuit d Y il 5 15 Mod 1 8010A Section V Figure 5 13 20V R45 4 64K 9 C12 SCHMITT InF CR21 CR22 TRIGGER Q4 R47 R48 R46 1K 27K 56 2 25V 938 914 P O A12 O 1 H EXT gt LET R101 2 C42 25 Tm 25V 20V TRIGGER OUTPUT 25V R23 1K R40 R24 100 CR17 SQUAREWAVE 28 28 AE R97 S
5. 2V 2v BEAD BEAD R16 T o SWITCHING TRANSISTORS 22 96 97 FROM SCHMIT 22 22 TRIGGER CR2 25V R17 1 07 CR9 WOO OM 7 22 CR5 Ew mg 2 1 Leo 3 6K 79001 4 6002 AH mp SN 0 Z 3 28 REVERSE VOLTAGE 015 ADJ 9 R38 90 9 R42 R43 LJ 227 M 3 3K R39 25V 25V IK 25V 25V __ 32 _ REFERENCE DESIGNATIONS 19 No PREFIX GD GD I A AA be pE kla R16 17 21 22 24 29 ERAN E 1951 3 3 41 45 47 52 VERNIER R8B 5 L Lx MEE 7 ion NOTE RESISTOR R58 SHOWN 25V 2 25V ALSO ON SCHEMATIC NO 13 1951 1 COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 4 8010A INTEGR BRD 958 Figure 5 25 Integration Channel B Circuit 4 5 41 Model 8010A P O A5 INTEGRATOR BOARD 08010 66505 P O A7 OUTPUT AMPLIFIER BOARD 08010 66507 Emitter 20 HEP Followers 2 2 E a 25 Channel i FSi 90 RIO SN 820 I GJEN 04 27k 5 AJ 150K POSITIVE e as 828 4K y BASELINE 5 1K R22 12 1 R17 C6 C7 1 0 0 01 C11 12 821 1 1 2nF OK nf 110 R 4 818 2 2 RIE TO R39 R40 R26 0 9 TS CHANNEL 4 4 RII 2 923 MK RELAY 332
6. 0160 2146 CER 2 02 UF 580 202 100VDCw 0180 0228 TA ELECT 22 10 15VDCw 0180 0050 AL ELECT 40 675 109 50VDCw 0160 2146 CER 02 UF 5680 2059 lOOVUCW p p P gt gt 0180 0228 TA FLECT 22 UF 10 15VDCw 0160 2205 MICA 120 5 30CVDCw 0180 0094 AL ELECT 100 UF 15 10 25VDCw gt P 1901 0522 SILICON 100v PIV 1901 0522 SILICON 100V PIV 1901 0522 SILICON 100v PIV 1901 0522 SILICON 100V PIV 1902 0041 BREAKDOwN 5 11 5 400 1902 0173 BREAKDOWN 9 53 5 400 Mw 4 14 8010A Z Model 8010A Table 4 1 Reference Section IV Table 4 1 Reference Designation Index cont d Description m gt P P P P P P P P P gt P P P P P D P P p P P A A A A A 52051280 nono 1901 0522 1901 0522 1901 0522 1901 0522 1902 0041 1902 0113 1854 0307 1854 C090 1854 0329 1854 0035 1854 0039 1854 C090 1854 0329 0698 4254 0698 4266 0758 0124 0698 4278 0758 0043 0698 4261 0698 4260 2100 2795 0698 4254 0812 0017 0698 4254 0698 4266 0758 0124 0698 4218 0758 0043 0698 4261 0698 4260 CIODE SILI DICDE 5141 DIODE SILI SILI VINDE BREAKDOWN 5 11V 5 400 MW CIODE BREAKDOWN 9 53V 5 403 TRANSISTOR CON 100v PIV CON 100v PIV CON 100v PIV CCN 100V PIV SILICON NPN NCT ASSTGNED TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSESTOR TRANSISTOR
7. ASSIGNED SWITCH SQUARE PULSE CHA SWITCH SQUARE PULSE SWITCH OFFSET ON OFF CHA SWITCH OFFSET ON OFF CHR SWITCH SEP A B SWITCH PULSE POLARITY CHA SwITCH PULSE PCLARITY CHB SWITCH SYNCH NORM ASYN SWITCH MAN SWITCH PUSH ON OFF SWITCH LINE VULTAGE SWITCH DELAY MODE SWITCH SEPARATE TRIGGERING ON OFF CHB SWITCH SEPARATE TRIGGERING ON OFF CHA SWITCH NORM 5V PAR LOV STAND TILT DIAL INSERT FOOT ASSY FM KIY 7H RACK MOUNT COUPLER PLASTIC BRACKET SWEEP DIAL DIAL REP RATE DIAL PULSE DELAY OIAL PULSE WIDTH DIAL PULSE WIDTH Mode 8010A 3 0104 8010 Section Table 4 1 Table 4 1 Reference Designation Index cont d Reference m Designation Description 08005 04101 COVER HEAT SINK 08010 04004 CTAL OELAY WIDTH VERNIER 08010 04005 CIAL REP RATE VERNICR C8010 04006 DIAL VERNIER 08010 04007 EIAL FALL RISE TIME DIAL TRANSITIUN TIME DIAL AMPLITUDE TOP COVER ASSY L6LFM ATTENUATOR SET OF CCAX CABLES ASSY CABLE MAIN 08010 04008 08010 04009 08010 04101 08010 61602 08010 61603 ASSY CABLE DELAY SWITCH ASSY CABLE OELAY SWITCH CHA ASSY CABLE WIOTH SWITCH CHA ASSY CABLE WIDTH SWITCH CHA ASSY CABLE TIMING 08010 61605 08010 61606 08010 61607 08010 61608 08010 61610 DP ASSY CABLE SHLD POWER ASSY CABLE COAX ASSY KNCB REP RATE ASSY KNOB DELAY WIDTH CHA ASSY
8. 7 COPYRIGHT 1970 BY HEWLETT PACKA 8010A DELAY WIDTH BRD 958 Channel B TO Q17 RD GMBH Section Figure 5 22 5 35 Model 8010A Figure 5 23 Cora DELAY WIDTH BOARD 08010 66503 _ ev Width 2 be Channel 20V 92 20V DELAY MODE SER 519 dem 20V VERNIER x ee eg Sl i i C24 1651 g 2 20V l x l 5 826 E T INPUT FROM P COLLECTOR 08 9 910 20V R 72 Cu oe 52 4 3 1 1 CRI D 4 5 R38 C32 T LEX T tape 100 MINIMUM 9 WIDTH 2 016 REFERENCE DESIGNATIONS ADJ R43 6 R47 19 25 27 34 36 348 CR1 25V 6 2K INPUT FROM SCHMITT TRIGGER QI and Q2 014 7 18 R26 39 41 49 52 2 NOT ASSIGNED A3C26 35 R48 402 1889 EE EEE ETE TE ENE EE e EE 300 ur 2K COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 1 1 1 523 TO Al 33 8010A DELAY WI DTH BRD 958 Figure 5 23 Width Channel B Circuit 3 5 37 Model 8010A 5 INTEGRATOR BOARD B 08010 66505 C1 1 0nF FROM AL GD N 035 036 25V R7 1 21K 2 25V R6 2 61K R2 1 96K R3
9. 08010 61906 08010 61907 0180 0158 0180 0198 1250 0118 1250 0118 1250 0118 1250 0118 1250 0118 1251 2351 1854 0063 1854 0063 1853 0052 2100 2600 2100 2600 2100 21 6 2100 2146 2100 1577 522525 2100 1577 2100 1577 2100 1577 3101 0199 3101 0199 3101 0199 3101 0199 3101 0199 3101 0199 3101 0199 3101 0199 3101 0199 3101 1327 3101 0124 3101 1244 3101 0033 3101 0199 3101 0199 3101 0199 3101 0199 nn 1490 0030 5000 0479 5060 0767 5060 0776 01402 23201 01821 01205 08010 04001 08010 04002 08010 04003 08010 04003 4 16 Description ASSY TRANS TIME SWITCH A ASSY TRANS TIME SWITCH CH AL ELECT 1500 UF C FXO AL ELECT 1500 UF 50VDCw CONNECTOR GATE CONNECTOR TRIGGER INPUT CONNECTOR TRIGGER OUTPUT NSRP OF A 17 NSRP OF A 17 SEPARATE TRIGGERING SEPARATE TRIGGERING B AC LINE TRANSISTOR SILICCN NPN 2N3055 TRANSISTOR SILICCN NPN 2N3055 TRANSISTOR SILICON PNP 2N3740 VAR CERMET 100 OHM 20 2W VAR CERMET 100 OHM 207 2w CCMP LOK OHM 20 3 10w VAR COMP LOK OHM 20 3 10W VAR ww CUAL 1200 OHM 10 LIN VAR WW DUAL 1200 OHM 10 LIN VAR ww DUAL 1200 OHM 10 LIN VAR ww DUAL 1200 OHM 10 LIN NOT ASSIGNED SWITCH SINGLE DOUBLE PULSE SWITCH SINGLE DUUBLE PULSE NOT ASSIGNED NOT ASSIGNED ASSIGNED
10. of the signal driving A6Q12 A6Q15 3 56 output of the positive amplifier is passed by A6K3 relay contact to the VERNIER control This relay is operated when PULSE POLARITY is switehed to po sitive or whenever the SQUARE mode is selected Selec tion of the SQUARE mode turns on A6Q19 to operate the relay Additionally transistors A6Q17 and A6Q18 are brought into operation to offset the output symmetrically to ground 3 57 Negative Amplifier 3 58 negative output amplifier functions in the same manner as the positive Transistors A6Q29 A6Q30 form the current source controlled by A6Q28 which is switchable by the PULSE POLARITY switch to turn it on and off The polarity switch also controls the relay A6K1 which is energized in the negative position Operation in the SQUARE mode removes the ground connection from the relay and transistor A6Q28 making the negative am plifier inoperative 3 50 signal applied to the bases of A6Q24 A6Q27 controls the division of current between these transistors and 6012 6014 When all current is routed to the A6Q24 A6Q27 the base line is established The pulse top is formed when all the current is routed to A6Q12 A6Q14 Resistor AGR71 adjusts the base line by varying base voltage of A6012 A6014 The negative output is fed to the VERNIER control Model 8010A 3 60 DC OFFSET 3 61 With the OFFSET switch SLO in the OFF position A9Q6 and 908 bases are strapped togethe
11. 9 OE col 8010 3 5 8010 3 6 Assembly and Component Location NES Figure 5 5 Section V Figure 5 6 5 8 08010 66504 08010 66505 4 le ORE Eg E Figure 5 6 Assembly 4 and 5 Component Location on A5 only on A4 only on A4 only BO10A 3 8 9010 3 7 Model 80104 Section Figure ace x c t j 5s E NEMO o G 3 4 8 O LU ME E door OG ewe om OO HO Ma pss DE Kok 4 9 G od R87 R79 R78 08010 66506 B010A A3 9 Assembly A6 Component Location Figure 5 7 Model BULOA Section V Figure 5 8 08010 66507 10 E ale Mio ya olio ENG Assembly A7 Component Location Figure 5 8 OB o No F me Os 35 2 ET A I ca 85 7 ms enr cez EN 5 9 5 10 Section V Model 8010A Figure 5 9 08010 66508 EUN R11 L3 L2 L1 8010A A4 11 Figure 5 9 Assembly A8 Component Location Model 8010A b o OHHO
12. PRELIMINARY OPERATING AND SERVICE MANUAL MODEL 8010A PULSE GENERATOR This manual contains service information for instru ments with the serial number prefix G958 For supplementary information pertaining to instru mants with higher prefix numbers refer to the manual supplement for those instruments COPYRIGHT HEWLETT PACKARD GMBH 1970 703 B BLINGEN HERRENBERGER STR 110 WEST GERMANY 08010 90000 PRINTED AUG 1970 Table of Contents Section I V TABLE OF CONTENTS GENERAL INFORMATION 1 1 Introduction 1 5 Available Accessories 1 7 Identification 1 9 Ordering Information OPERATING INSTRUCTIONS 2 1 General 2 3 Internal Triggering Mode 2 5 External Trigger Mode 2 1 Manual Trigger Mode 2 9 Gating Modes 2 1 Delay Mode 2 13 Square Pulse Mode 2 15 Ten Volt Output 2 17 Pulse Output 2 19 Preparation for use 2 20 Power Source Requirements 2 22 Fuse Replacement 2 24 Power Cable 2 26 Temperature Requirements 2 28 Initial Turn On Procedure 2 30 Repacking PRINCIPLES OF OPERATION 3 1 Introduction 3 4 Rep Rate Generar 3 6 Free Running Mode 3 10 External Triggering 3 15 Manual Triggering 3 17 Gating 3 19 Asynchronous Gating 3 21 Synchronous Gating XE 3 28 Pulse Square Wave Switching 3 31 Pulse Delay 3 36 Width Circuit 3 41 Pulse Shaping 3 44 Integrator 3 48 Emitter Follower and Inverter 3 51 Output Amplifiers 3 53 Positive Amplifier 3
13. Section Model 80104 Mo Table 4 1 2 Table 4 1 Reference Designation index cont d Reference re 0761 0014 R FXO MET OX 180 UHM 57 lw 0698 4241 FLM 510 OHM 5 1 8W 0698 4286 FXO FLM 22K OHM 5 1 8W 0698 4261 R FLM 2000 CHM 5 1 94 0698 4247 FXD FLM 510 OHM 5 1 8W 0758 0086 100 OHM 53 1749 2100 2800 VAR CERMET 1K QHM 54 0698 4254 FXO FLM 1000 OHM 5 1 84 0698 4229 FXD FLM 75 OHM 5 1 8w 0698 4306 FLM 150K UHM 5 0698 4250 FXD FLM 680K OHM 5 1 8W 08010 66504 INTEGRATOR CH BeSAME AS A4 EXCEPT 0758 0068 R FXD FLM 100 OHM 5 1 8W P P 08010 66506 UUTPUT AMPLIFIER CH A TA ELECT 1 UF 10 35V0CW FXD CER 02 UF amp 80 20 100VDCw TA ELECT 6 8 UF 10 35VDCw TA ELECT 1 UF 10 35VDCW CER 01 UF amp 80 20 100VDCw 0180 0291 0160 2146 0180 0116 0180 0291 0150 0093 P P gt P P TA ELECT 1 UF 10 35VDCw CER 01 UF 680 207 LOOVNCW CER 220 E80 20 1 CER 01 UF 80 20 TA ELECT 1 UF 10 35VDCw 0180 0291 0150 0093 0160 2139 0150 0093 0180 0291 gt p P P FXO CER 2000 PF 680 20 1000 CER 1000 PF 600 0 01 UF 680 20 100VDCw MICA 200 PF 5 300VDCW 01 UF amp 80 20 190VDCw 0160
14. 0698 4254 0727 0445 gt gt p gt P OX 330 OHM 5 1 330 OHM 52 LW FXD FLM 820 OHM 5 1 8W FLM 2000 OHM 5 1 8W FXO FLM 5110 OHM 5 1 8w 0161 0054 0761 0054 0698 4252 0698 4261 0698 4271 P p P pP P e o o gt gt gt gt gt 2100 2741 R VAR VERMET 470 OHM 20 1 2W 0698 4261 R FLM 2000 OHM 5 1 8W 0698 4261 2000 OHM 5 1 8w NOT ASSIGNED 0698 4261 R FXD FLM 2000 OHM 5 1 8W P p P p Caran 5625 5255 0698 4268 FLM 3 9K OHM 5 1 8W 0698 4253 FLM 910 OHM 5 1 84 SELECTED TEST 2100 2600 R VAR CERMET 1000 202 2w 08010 66507 OUTPUT AMPLIFIER CH B SAME 5 6 EXCEPT 0490 0733 REED RELAY SPST 18VDCW P gt gt gt Lr 2100 2788 VAR CERMET 4 7K OHM 0698 5702 FLM 30 CHM 5 1 8w 0698 4238 FLM 160 OHM 5 1 8 2100 2741 VAR VERMET 470 OHM 2032 1 2W gt gt gt p MM NAN gt 08010 66508 ATTENUATOR ASSY CH 9170 0029 FERRITE BEAD 9170 0029 CORE FERRITE BEAD 9170 0029 CORE FERRITE BEAD 914C 0118 CCIL FXD 500 UH 5 A A A A reer 0757 0801 MET FLM 150 OHM 1 1 2w 0757 0172 37 4 OHM 1 1 2W 0751 0801 FLM 150 OHM 1 1 24 9751 0795 FLM 75 OHM 1 1 2 0757 0069 FLM 121 OHM 1 1 44 P P p
15. 310 REFERENCE DESIGNATIONS 01 3 5 81 11 13 15 59 R4 150 NOTE 1 F SCHMITT TRIGGER 01 and Q2 25V R8 1 5K 25V R9 619 R13 909 Ll 1 gt 1 Bm 7 1951 s im Cim GJ Cu on 3 RESISTOR R58 SHOWN ALSO ON SCHEMATIC NUMBER 14 TO RELAY RESISTOR R55 Figure 5 24 Pulse Shaping Channel Circuit Pulse Shaping Ch B 14 R16 V R cro TO SWITCHING E TRANSISTORS 5 06 and 07 815 LSK 25V COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A INTEGR BRD 958 13 Section V Figure 5 24 5 39 Section 5 5 95 Figure 5 29 Model 8010A 2 H LJ O LJ 1 I 5 INTEGRATOR BOARD 08010 66505 _ _ _ E o 2 D 108010 00309 _ 2 R7A 4 ptem Integration GD Channel 1 2K l 903 CR7 25V V R30 4 15V 25V 6 8 R58 1K NOTE 1 D R27 BK a 7 022 30 850 RN 2 4 Y N 24K 90 9 470 cde 072 010 0 01 1 15 XN REVERSE N R46 012 AJ VOLTAGE 470 PULSE TOP 74 Qu gt 27 7 5K C6 C7 C30 FG a od RA LO 2 A HA 3 6K 0 01 R25 C8 C9 43K 200 220pF 0 01 1 1 CR8 i
16. QD CD gt gt 20 gt 0757 0795 FLM 75 OHM 1 1 2W 0757 1005 MET FLM 61 11 OHM 253 172 0757 0071 FLM 247 5 OHM 1 1 44 0757 1005 MET FLM 61 11 UHM 25 1 2W 0698 4253 FXD FLM 910 QHM 5 1 8W P gt p gt p e 00 gt 0698 4268 R FLM 3 9K OHM 5 1 8w gt 3100 0530 SWITCH ROTARY 08010 66509 OFFSET ASSY 0180 0049 FXD ELECT 20 UF amp 15 10 50VDCw 0180 0291 FXD ELECT 1 UF 10 0180 0291 FXD ELECT 1 UF 103 35VDCh 0180 0049 FXD ELECT 20 UF 615 10 0180 0049 EXU ELECT 20 UF 615 104 0180 0291 FXD ELECT 1 UF 10 35V0CW 0180 0291 FXD ELECT 1 UF 104 35VDCM 0180 0049 FXD ELECT 20 UF 615 105 SOVDCW Section Table 4 1 Table 4 1 Reference Designation Index cont d Reference Designation Description 9170 0029 CORE FERRITE BEAD 9170 0029 CORE FERRITE 8EAD 9170 0029 CORE FERAITE BEAD 9170 0029 CORE FERRITE BEAD gt gt gt rrer 1853 0051 TRANSISTOR SILICON PNP 2N4037 1854 0329 TRANSISTOR SILICUN NPN 1894 0039 TRANSISTOR SILICON NPN 2N3053 1853 0090 TRANSISTOR SILICON PNP 1853 0051 TRANSISTUR SILICON PNP 2N4037 P gt P P P 00 O lt 0 O oO 1854 0329 TRANSISTOR SILICON NPN 1854 0039 TRANSISTOR SILICON NPN 2N3053 1853 0090 TRANSISTOR SILICCN PNP gt p FLM 470 OHM 5 1 4W FX
17. Sec Figure 5 1 13530 x Model 8010A 35109 18 0108 Jo mer3et 99014 71 6 9818399151 35 3svnos v ot 35104 3uvnos 8 35104 81 YL NdWY 8302181 1108100 8390181 981839913 435 BHONAS 9 HNAS vo 198812 ANANI 8359181 5 3 Section V Model 80104 Figure 5 2 Al TIMING BOARD 08010 66501 a A2 DELAY WIDTH BOARD A 08010 66502 INTEGRATOR BOARD 08010 66504 A6 OUTPUT AMP BOARD CH A 08010 66506 Ai OUTPUT AMP BOARD CH B 08010 66507 DC OFF SET 108010 66509 e FRONT PANEL Figure 5 2 Top View 5 4 Model 8010A Section V Figure 5 3 3 DELAY WIDTH BOARD CH B 08010 66503 A5 INTEGRATOR BOARD CH 8 08010 66505 A9 DC OFFSET 08010 66509 C Jasan cns 0800 6506 A7 OUTPUT AMP BOARD CH B 08010 66507 A6 OUTPUT AMP BOARD CH_A 08010 66506 FRONT PANEL Figure 5 3 Bottom View Section V Model 80103 Figure 5 4 DER a a ooo ole Qo O hn 9 CR2S R37 Figure 5 4 Assembly Al Component Location AG 8010A 4 ES Section V Figure 5 5 Model 8010A 08010 66503 08010 66502 DE TTE etr M Coe
18. a FROM CHANNEL B 25V 220pF 923 O INTEGRATION INPUT F FROM R20 150K C4 25V CR11 0 01 13V 1 REFERENCE DESIGNATIONS R7 8 10 35 98 Q4 20 R12 53 54 56 57 61 62 NOT ASSIGNED A6R9 A6 OUTPUT AMPLIFIER BOARD 08010 66506 _ R19 C8 360 220pF R20 3 z R21 8 7 aK POSITIVE 2 ADJ R22 12K C6 a R18 100 I I R17 100 T R98 R7 10 R8 R10 100 100 L1 750uH R15 1 24K 1 44K R13 100 25V R14 8 06 25V Figure 5 19 25V BASELINE Emitter b Followers 25V 55 Channel A R23 25V 5 1K C11 2nF 0 R11 R39 R40 332 1 812 2 21 C13 0 01 COPYRIGHT 1970 BY KARD GMBH 8010A INTEGR AN Emitter Followers Channel Circuit Section V Figure 5 19 5 29 id adel A6 OUTPUT AMPLIFIER BOARD 08010 66506 25V 25 R54 IA 921 4 NOTE SQUAREJ N PIO S8 25 R55 pus 15K 856 860 F 22K CONNECTED 923 00 Q2 TO AICR3OR71 R5 a 10K 27 N PULSE PO S13 POLARITY sage GID N SQUARE PULSE SWITCH S8 SEE R41 R42 R43 RIGHT HAND SIDE 681 681 681 SCHEMATIC INPUT FROM e Q9 EMITTER t HE x 1 K3 29 2 NOTE 1 THIS P O 58 ALSO SHOWN SCH
19. i 903 25V id 25V n 58 R27 4 2 022 15 TRIGGER CR2 25V EN R17 is CR9 3 22 d 3 22 010 R26 2 CB 1K 90 9 i UN L 9746 1 R23 ab 3 7 5k EG co 66 MR e 3 6 ins 1 5K 200 4 1 CR8 22 12 13 Lo 06 SWITCHING TRANSISTORS BEAD BEAD En i 2 VN Q6 and Q7 22 R18 R19 R20 A FROM SCHMIT a A 57 30 9V lt N 5 rs 7 CR6 220pF 360 32 0 01 AN C12 910 CR Fii VAY 6 4 x N 2 BEBO Ns 447 REVERSE 9 VOLTAGE 1 mb ADJ R42 R43 3K 3 3K 25V 25V R39 25V 25V Dn H 2 4 ES REFERENCE DESIGNATIONS A PREFIX 3 934 R6A 03 EB E E 6 B Bd 816 17 21 22 24 29 hm COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A INTEGR BRD 958 t 80 RISE 5 32 39 41 45 47 52 veRNIER 2 7 freg aid 55 58 3 bi 1 2K 25V 5 I NOTE 1 RESISTOR R58 SHOWN P O 1851 TRANSITION TIME ET ALSO ON SCHEMATIC NO 6 7 Figure 5 18 Integration Channel A Circuit 5 27 det BOLOA 4 INTEGRATOR BOARD 08010 66504 25V 25V 25V LOR CR10 18 2V NORM GV 4 2
20. 0180 1149 0180 1749 0180 0291 Model Table 4 1 Reference Designation Index ASSY TIMING BOARD ASSY DELAY wIDTH BOARD CHA ASSY DELAY WIDTH BOARD ASSY INTEGRATOR BOARD CHA A ASSY INTEGRATOR BOARD CHA ASSY OUTPUT AMPL BOARD CHA A ASSY OUTPUT AMPL BOARD ASSY ATTENUATOR BOARD CHA ASSY CC OFFSET BOARD CHA A CHA ASSY ATTENUATORS WITH DC OFFSET BOARD ASSY POwER SUPPLY BOARD ASSY REP RATE SWITCH ASSY DELAY SWITCH CHA A ASSY DELAY SWITCH CHA B ASSY WIOTH SWITCH CHA A ASSY WIOTH SWITCH CHA B ASSY ATTENUATOR ASSY TRANS TIME SWITCH CHA A ASSY TRANS TIME SWITCH CHA B ASSY TIMING BOARD FXD TA ELECT 1 UF 10 35VDCw FXD MICA 22 PF 5 500VDCw FXD TA ELECT 10 UF 10 20VDCw TA ELECT 1 UF 10 35 0 MICA 110 5 300VDCW C FXD CER 1000 PF 600VDCw FXO TA ELECT 1 UF 10 35VDCW NOT ASSIGNED NOT ASSIGNED FXD MICA 41 PF 5 300VDCW TA ELECT 1 UF 10 35VDCw CER 1000 PF 600VDCw VAR CER 9 35 PF FXO MICA 30 5 300VDCw CER 1000 600VDCw FXD MICA 820 PF 5 300VDCw FXD MICA 12NF 5 MIAL 0 15 UF 2 125V0CW TA ELECT 1 5 UF 5 35V0CW TA ELECT 15 UF 5 20VDCw TA 51 UF 5 15VDCw TA ELECT 1 UF 10 35VDCW MICA 100 5 300VDCw FXO MICA 100 PF 5 300VDCW MICA 33 PF 5 300VDCw TA ELECT 1 UF 10 35VOCw TA ELEC
21. 1 51 1 51 9 5 OnF zo Negative Output Amplifier Channel A Circuit R70 27K R71 470 2 7K ifier COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A OUTPUT AMP BRD 958 Section V Figure 5 21 Negative Output Ampl i Channel A A waq TO AMPLITUDE VERNIER PULSE POLARITY 1 1 1 0513 1 PULSE 58 ___ 1 5 R92 946 Ean p gt CONNECTION TO 5V R88R89 CONNECTION TO A6Q16 COLLECTOR 10 5 33 Mode 8010A DELAY WIDTH BOARD 08010 66503 ON 50 orr DELAY MODE o 519 FROM EMITTER 106 502 SER FROM DELAY_A GENERATOR 902 CR2 R9 240 C38 5 20V 92 20V 25V 235V f 1 Lim SI x 503 5 3 65K 274K SCHMITT TRIGGER 25V Q5 and Q6 TU Figure 5 22 VERNIER 1 1 PULSE DELAY 5K Al4R1 20V R4 392 R12 160 R59 10 MINIMUM DELAY ADJ belay Channel B Circuit R10 100 20V 20V ul 1 5pH SCHMI SWITCH Q7 R14 68 gt cu 07 9 35pF y R53 Delay TT TRIGGER Q1 and Q2 20V R2 1 5K 20V 20V 1 3 5 6 8 17 37 38 CR2 3 12 Q1 9 19 R1 22 24 25 50 5 53 54 59
22. 100VDCw 2 38 0150 0093 0 01 UF 80 20 100VDCw A 2 CR 1 1901 0040 CIOOE SILICON 30PIV 30 MA A 2 CR 2 1910 0016 DIODE GERMANIUM A 2 CR 3 1910 0016 DIUDE GERMANIUM A 2t 1 9100 1616 COIL 1 5 UH lt A 21 2 9100 1616 COIL FXD 1 5 UH i A 214 1 1853 0203 TRANSISTOR SILICON A 23 2 1853 0203 TRANSISTOR SILICON PNP A 2 Q 3 1853 0034 TRANSISTGR SILICON PNP A 24 4 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 20 5 1854 0215 TRANSISTOR SILICON 2N3904 20 6 1854 0215 TRANSISTOR SILICON 2N3904 A 20 1 1854 0019 TRANSISTOR SILICON NPN A 24 8 1853 0036 TRANSISTOR SILICON PNP 2N3906 21 5 1854 0215 TRANSISTOR SILICON NPN 2N3S04 A 2c 10 1854 0215 TRANSISTOR SILICON 2N3904 A 2Q 11 1853 0203 TRANSISTOR PNP A 24 12 1853 0203 TRANSISTOR PNP A 2C 13 1853 0034 TRANSISTOR SILICON PNP A 2 G 14 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 2Q 15 1854 0215 TRANSISTOR SILICON 2N3904 24 16 1854 0301 TRANSISTOR NPN A 2 17 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 2 18 1854 0215 TRANSISTOR SILICON NPN 2N3904 A 2C 19 1854 0215 TRANSISTOR SILICON NPN 2N3904 2R 1 0758 0127 R FLM 430 OHM 52 1 4W A 28 2 0757 0736 FLM 1500 OHM 1X 1744 A 28 3 0757 0433 FXO 3320 OHM 1 1 8W A 28 4 0157 0124 MET FLM 392 OHM 1 17 44 A 28 5 0757 0817 FLM 750 OHM 1X 172w A 28 6 0757 0405 FXO FLM 162 1 1 8M A 2R 7 0757 0338 MET FLM 1000 CHM 17
23. 15 0140 0200 FXO MICA 390 5 300VDCW 210 16 0150 0121 CER LUF 6805 2034 50VDCW 2C 17 0121 0046 VAR CER 9 35 PF av Section IV Model 801048 Table 4 1 1 Table 4 1 Reference Designation Index cont d Reference Designation Description A 2C 18 NUT ASSIGNED A 20 19 0180 0291 C TA ELECT 1 UF 10 35VDCw A 210 20 0150 0121 CER 1UF 580 20 50 A 20 21 0140 0145 C MICA 22 54 500V0Cw A 20 22 0150 0093 C 01 UF 80 20 100VDCw A 20 23 0160 0987 MICA 12 pF 5 500VDCW A 2C 24 FACTURY SELECTED A 20 25 0180 0294 FXD TA ELECT 390 UF 20 A 20 26 ASSIGNED A 20 21 0180 1955 C ELECT 47 UF 5 6VUCW A 2C 28 0180 1954 TA ELECT 47 UF 5 6VOCw A 2C 29 0170 0078 FXD MYLAR 47 UF 5 150VDCw A 20 30 0160 3165 C EXD MYLAR 047 UF 2 50VDCw A 20 31 0160 2127 MICA 4600 1 300V0CW A 2 32 0150 0093 CER 01 UF 80 204 100VDCw A 2C 33 0140 0177 MICA 400 PF 12 A 2 34 0150 0121 CER 1UF amp 80 20 SOVDCA A 2 35 NOT ASSIGNEO A 2C 36 0121 0061 CER 5 5 18 PF A 2 37 0150 0093 FXO CER 0 01 UF 80 20
24. 1749 A 28 0151 0417 FLM 562 OHM 1 1 8 A 28 9 0698 4240 FLM 240 OHM 5 1 8W A 2R 10 0757 0401 R FXD MET FLM 100 OHM 1 1 8W A 28 11 0757 0433 FLM 3320 OHM 1 1 8W A 2R 12 0698 4236 FLM 160 OHM 54 1 8W Mode 8010A Section IV Tabte 4 1 Table 4 1 Reference Designation Index cont d Reference em A 2R 13 0757 0738 R FLM 1820 1 1 4h A 2R 14 0698 4227 R 68 OHM 5 1 8 28 15 0698 4235 R 150 UHM 52 1 8W 2 16 0698 6746 8 43 OHM 5 1 8 A 2R 17 0757 0827 R FLM 2740 OHM 1 2R 18 0757 0354 R FLM 3650 OHM 1 A 2R 19 0698 4244 R 360 OHM 5 1 A 2R 20 0698 4236 R 160 OHM 5 1 8wW A 2R 21 0758 0066 R 620 OHM 5 1 4W A 2R 22 0698 3441 R FLM 215 OHM 1 1 8W A 2R 23 0698 4254 R 1000 OHM 5 1 8W 28 24 0698 4243 R 330 OHM 5 1 8W A 2R 25 0757 0401 R 100 OHM 1 1 84 A 2R 26 0698 4242 R 300 OHM 5 1 84 A 2R 27 0758 0127 R 430 OHM 57 1 4W A 2R 28 0757 0736 R FLM 1500 OHM 1 1 4W 2R 25 0757 0433 R FLM 3320 OHM 1 A 2R 30 0757 0724 4 FLM 392 OHM 1 1 4W A 2R 31 0757 0817 R FLM 750 OHM 1 1 2w A 2R 32 0757 0338 R FLM 1000 OHM 1 4W A 2R 33 0757 0417 R FLM 562 OHM 17 1 8W A 2R 34 0757 0405 R FLM 162 OHM 12 1 8W A 2R 35 0757 0216 61 9 OHM 1 1 A 28 3 0757 0433 R FLM 3320 OHM 1 1 89 2R 37 0698 4236 R FLM 160 OHM 5 1 A 2R 38 0757 0738 R FLM 1820 OHM 1 1 4W A 2R 39 0698 4227 F
25. 2143 0150 0050 0150 0093 0140 0198 0150 0093 P gt P P P CER 01 UF 880 207 100VDCw CER 1UF E80 20 5 FXD MICA 27 PF 5 300V0CW FXO TA ELECT 1 UF 10 35VDCw FXD TA ELECT 1 UF 107 35VDCw 0150 0093 0150 0121 0160 2306 0180 0291 0180 0291 P gt P P gt TA ELECT 1 UF 10 35VDCw FXD TA ELECT 6 8 UF 10 35VDCw CER 01 UF 580 202 LOOVDCW MICA 27 5 300VDCw TA ELECT 1 UF 103 35VDCw 0180 0291 0180 0116 0150 0093 0160 2306 0180 0291 P p P P P 0180 0291 C TA ELECT 1 UF 19 35VDCW NOT ASSIGNED 0160 2146 CER 02 UF E80 20 LOOVDCW Coe 1901 0044 DIODE SIL 50PIV 20 MA 1901 0044 DICOE SIL 50PIV 20 MA 1902 0031 DIODE BREAKDOWN 12 7V 1902 0556 DIODE BREAKDUwN 20 0V 1902 3140 BREAKDOWN 8 25 1902 0032 DIUDF BREAKDOWN 5 49V 1902 0579 DIODE BREAKDOWN 5 11V 1902 0579 DIODE BREAKDOWN 5 11V 1902 0579 DIODE BREAKDUwN 5 11V 1902 0579 DIODE BREAKDOWN 5 11V 0490 0733 REED RELAY SPST 18VDC 0490 0733 REED RELAY SPST 18VDC 0490 0733 REED RELAY SPST 18VDC 4 10 80107 gt gt r P p p p gt p p p gt P p P P P P P O
26. 57 Negative Amplifier 3 60 DC Offset 3 62 Output Switching and Attenuator 3 65 Power Supply bates d REPLACEABLE PARTS 4 1 Introduction 4 3 Ordering In CIRCUIT DIAGRAMS 5 1 Introduction 1 _ Pa oe eae 1 pm jp rad ad to 3 4 co 00 00 4 Model 8010A Model 8010A Number N FO TE P FT eo a PWN A 00 010 gt i w 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 5 31 Number 1 1 4 1 5 1 LIST OF ILLUSTRATIONS Title Instrument Controls and Connectors Repetition Rate and Trigger Input Block Rep Rate Generator Output Distribution Block Diagram Square Wave of Pulse Selection Block Diagram Delay Generator Block Diagram Width Generator Block Diagram Integrator Block Diagram Block Diagram of 8010A Top View Bottom View Assembly Al Component Assembly A2 and Component Location Assembly A4 and AS Component Location Assembly 6 Component Location Assembly A7 Component Location Assembly A8 Component Location Assembly A9 Component Location Assembly All Component Location Trigger Input Circuit Rep Rate and Gate Input Circuit Square Wave or Pulse Selection Circuit Delay Channel A Circuit Width Channel A C
27. A6Q11 is passed to the ne gative amplifier Diode AGCR5 changes the de level of the signal Differential amplifier A6Q3 A6Q7 inverts the ne gative output from 404 4020 and the emitter follow ers A6Q8 A6Q9 pass the signal to the positive output am plifiers The voltage source A6Q4 A6Q5 controls the col lector voltage on A603 setting the base line for the po sitive pulse 3 51 OUTPUT AMPLIFIERS 3 52 output amplifiers provide the necessary cur rent to make 5 volts from a constant 50 ohm source into 50 ohms CLIPPING DIODES TO EMITTER FOLLOWERS RAMP CAPACITOR 80023 5 4 Figure 3 6 Integrator Block Diagram Section IH Paragraphs 3 53 to 3 66 3 53 Positive Amplifier 3 54 Transistors A6Q22 A6A23 form a current source controlled by A6Q21 which is switchable by the PULSE POLARITY switch to turn it on and off In the SQUARE mode A6Q2 conducts to turn on A6Q16 This holds the current source on irrespective of the POLARITS etting as the positive amplifier provides the square wave output 3 55 signal applied to the bases of 5019 6015 controls the division of current between these transistors and 608 6011 When all the current is routed to 6012 6015 the base line is established The pulse top is formed when all current is routed to A6Q8 A6Q11 The base line is adjustable by A6R21 part of the inverting dif ferential amplifier voltage source which varies the dc level
28. B OFF OUTPUT AMPLIFIER 5 V NORM 2 30 2 31 The original shipping carton and packing material be used for reshipment The Hewlett Packard Salcs Service Office will also provide information and recom mendations material to be used if the original packing material is not available or damaged If the instrument is to be shipped to a Hewlett Packard Sales Service Office for repair attach a tag showing owner model serial num ber and repairs required 4 1 1 Model 8010 SECTION Section Paragraphs 3 1 to 3 5 PRINCIPLES OF OPERATION 3 1 INTRODUCTION This section describes the basic principles of op eration of the Model 8010A Pulse Generator The major blocks and switching functions are given by Figure 5 1 The repetition rate determined by either the internal ge nerator or external triggering controls both channels A and B Synchronous gating effectively turns the instru ment on and off and in the asynchronous mode the repe tition rate generator continues to run to provide a trigger output The delay generator produces a pulse delayed with respect to the repetition rate generator and hence the trigger output In the serial mode both delay generators are added making channel the reference for channel B Double pulses are not available in the serial mode The pulse width circuits set up the width of the output pulses and provide differentiated spikes
29. Block Diagram 3 1 Section Paragraphs 3 6 to 3 18 3 6 FREE RUNNING MODE 3 7 In this mode of operation the REP RATE is set to any of the 7 internal rate settings Assuming a point in the cycle when the selected range capacitor is discharged as in the ease when the instrument is first switched the emitter of A1Q18 is effectively 0 5 volts Transistor A1Q18 will start conducting because its base is initially held at approximately 0 2 volts by voltage divider A1R45 R46 As 1018 starts to conduct the voltage developed across 19 AICR20 and causes 1017 to conduct also AICR19 and 1 20 increase loop gain for low A1Q18 collector current Conduction by 1017 raises the base potential of A1Q18 which thus conducts more heavily Regeneration causes both transis tors to saturate When the current into the range capacitor is no longer sufficient to keep A1Q18 saturated it ceases to conduct and regeneration turns both 1017 and 1018 off current source A1Q19 does not draw enough current to keep A1Q18 saturated With both 1017 and 1018 off the range capacitor is discharged by current source 1019 until the emitter of 1018 falls again to about 0 5 volts Transistor 1018 then again turns on and the cycle is repeated The repetition rate is thus deter mined by the value of the range capacitance selected by 1251 and the current drawn by current source 1019 varied by vernier control A12
30. Electronic test equipment cables connectors adapters and other accessory items are available from Hewlett Packard l or more information on specific items consult the Hewlett Packard Catalog or Sales Service Office 1 7 IDENTIFICATION 1 8 The title page of this manual lists the serial prefix number of instruments to which the contents of this book apply directly For newer instruments with different ser ial prefix a manual change sheet will be included describ ing the changes necessary to update the manual For instruments having special electrical modifications the manual will include an insert sheet describing the particular modification If a change sheet or special information sheet is missing it can be supplied by Hewlett Packard Sales and Service Offices listed at the back of this manual 1 9 ORDERING INFORMATION 1 10 One manual is shipped with each pulse generator Additional manuals may bc purchased from your local Hewlett Packard field office see list at the rear of this manual for addresses Specify the model number com plete serial number prefix and HP stock number provided on the title page Model 8010A Section Paragraphs 2 1 to 2 18 SECTION OPERATING INSTRUCTIONS 2 1 GENERAL 2 2 Figure 2 1 indicates the location of and briefly explains the function of Model 8010A front panel controls adjustments switches and connectors 2 3 INTERNAL TRIGGERING MODE 2 4 Mod
31. FXD MET FLM 196 OHM 1 1 8w 3 A 1R 90 0698 4278 R FXD FLM 10K OHM 5 1 8W 3 A 1R 91 0698 4247 FLM 510 OHM 5 1 8 A LR 92 0698 4254 FLM 1000 OHM 52 1 84 A LR 93 0698 4238 R FXD FLM 200 OHM 5 1 8W E C A LR 94 0698 4254 R FLM 1000 OHM 52 1 8W 3 A 1R 95 0698 4246 R FLM 470 OHM 5 4 A 18 96 0698 4254 R FLM 1000 OHM 5 1 8W 3 A 1R 97 0698 4243 FXO 330 OHM 5 1 8W 3 A 1R 98 0698 4249 R FLM 620 OHM 5 1 8w 3 A 18 99 0698 4285 FLM 20K OHM 5 1 8W 7 A 1 100 0758 0125 R FLM 430 OHM 5 E A 1 101 0698 6745 MET 22 OHM 52 1 4W 9 A 1 8 102 0698 6745 MET FLM 22 OHM 5 1 4 A 1 R 103 0698 6745 R FLM 22 OHM 54 1 4W A 2 08010 66502 DELAY WIDTH A 2 1 0180 0291 TA ELECT 1 UF 10 35VDCw E A 2 2 0150 0121 CER 0 1 UF 80 20 50VDCw A 2 3 0140 0145 FXD MICA 22 PF 5 500VDCw A 2 4 0150 0093 01 UF E80 20 1QOVDCw A 2 5 0160 0987 MICA 12 5 A 2 6 FACTORY SELECTED 2 7 NOT ASSIGNED A 2C 8 0180 0294 FXD TA ELECT 390 UF 20 A 2 9 0180 1955 TA ELECT 47 UF 5 6VDCw A 210 10 0180 1954 TA ELECT 4 7 UF 5 2C 11 0170 0078 MYLAR 47 UF 5 150VDCw 2C 12 0160 3165 MYLAR 047 UF 2 50VDCw 26 13 0160 2127 MICA 4600 PF 1 A 2 C 14 0180 0291 TA ELECT 1 UF 104 35V0CW E 2
32. FXD MET FLM 383 UHM 1 1 8W A LR 19 0698 4278 FLM 10K OHM 57 1 8w A 18 20 0698 4254 R FLM 1000 OHM 5 1 8W A LR 21 0698 4278 R FXD FLM LOK OHM 5 1 8W A 18 22 0758 0034 R MET FLM 2 4K OHM 5 1749 A 18 23 0758 0086 R FLM 100 OHM 57 1 8 A 18 24 0758 0126 FLM 51 OHM 5 1 4w A 1 R 25 THRU R39 NOT ASSIGNED A 18 40 0757 0400 FLM 90 9 OHM 1 1 8W A 41 0757 0402 R FXD MET FLM 110 UHM 1 1 8W A LR 42 0757 0806 R FXO FLM 243 OHM 1 1728 A LR 43 0698 6744 FLM 20 OHM 5 1 8W A LR 44 0757 0036 MET FLM 626 OHM 1 1 72 A LR 45 0698 3155 FLM 4640 OHM 1 1 8W A 18 46 0757 0395 FLM 56 2 OHM 1 1 8W A 18 41 0698 4254 R FLM 1000 OHM 5 1 84 A LR 48 0758 0004 R FLM 2700 OHM 5 1 44 A 18 49 0698 5702 FLM 30 OHM 5 1 2w A 18 50 2100 2795 R VAR CERMET 470 OHM 5w A 18 51 NOT ASSIGNED A 18 52 0698 4261 FLM 2000 OHM 5 1 8W A 18 53 0698 6744 R FLM 20 OHM 5 1 4W 18 54 0698 4246 FXO FLM 470 OHM 5 1 8w A 18 55 0757 1022 MET 1780 OHM 1 1 44 A 18 56 0698 4268 R 3 9K OHM 5 1 A 18 51 0698 4239 FLM 220 OHM 54 1 8w A 1 R 58 2100 2739 R VAR VERMET 220 UHM 20 5W A LR 59 0698 4239 R FXD FLM 220 OHM 5 1 8W A 18 60 0698 3439 MET FLM 178 OHM 1 1 8W A 18 61 0698 4245 FXD FLM 390 OHM 5 1 8W 18 62 0698 4249 FLM 620 OHM 5 1 8W LR 63 069
33. Width lt 20 ns to 1 second in eight ranges Ver nier provides continuous adjustment between ranges Accuracy 10 of setting 2 of full scale 4 ns Maximum Duty Cycle gt 80 for repetition rates from 1 Hz to 1 MHz gt 50 from 1 MHz to 10 MHz Width Jitter lt 0 1 on any width setting Maximum Output 5 V separate or combined outputs 10 V channel B channel A no output Attenuator Seven step attenuator reduces output to 0 05 V in 5 2 5 1 sequence Vernier provides con tinuous adjustment between steps and reduces mini mum output to lt 0 02 V Accuracy 10 of setting 2 of full scale Pulse Outputs Sep Outputs Two outputs cach positive or nega tive selectable Comb Outputs Outputs of channel A and B inter nally added no loss of amplitude Outputs short circuit proof Source Impedance 50 22 10 shunted by typically 20 pF DC Offset 2 V aeross 50 2 load Independent of attenuator and vernier setting can be switched off Pulse Delay Parallel lt 80 ns to 1 second delay with respect to trigger output Eight ranges Vernier pro Model BULUA Specifications vides continuous adjustment between ranges Serial delay for channel can be doubled Accuracy 10 of setting 2 of full scale 4 ns Delay Jitter lt 0 1 on any delay setting REPETITION RATE AND TRIGGER Free Running 1 to 10 MHz in seven ranges Vernier provides continuous adjustment bet
34. are obtained for the duration of the gating signal 3 21 SYNCHRONOUS GATING 3 22 In the SYNCHR mode 1016 is at ground po tential so 107 is off and the A1Q6 functions as an am plifier However A1R17 is now conneeted to ground so that A1020 collector is at or below ground potential ALCR12 is forward biased and the repetition rate gene rator is held off A negative gating signal turns A1Q20 off raises its eollector voltage enough to reverse bias A1CR12 and the repetition rate generator functions normally for the duration of the gating signal FLIP FLOP FROM Q30 20 TO FLIP FLOP 024 025 FROM GENERATOR RAY CRIB Section HI Paragraphs 3 19 to 2 25 3 23 Since the gating takes place before the pulse width is established i c while the main signal is still in form of spikes the last output pulse before the gating signal is reinoved will always be completed even if the gating pulse is stopped immediately after the output pulse has started The gating function is always the same re sardless of whether the instrument is triggered internally or externally 3 24 The differentiated spikes at the junetion of Al R40 L2 are fed to the base of A1Q30 This transistor performs two functions Spikes are fed from the emitter to change the state of flip flop A1Q24 Q25 The output of the flip flop appears at the junction of diodes ALCR28 CR29 Spikes from the collector go to the junction of diodes A1CR34 3
35. fuse is located on the rear panel Fuse should be 2 ampere Slow Blow for 115 volt operation or l ampere Slow Blow for 230 volt operation 2 24 POWER CABLE 2 25 The Model 8010A is equipped with a 3 wire power cable which when connected to an appropriate re ceptaele grounds the instrument cabinet and panel To preserve tlie protection feature when operating the instru ment from another type of outlet without ground use an Section Paragraphs 2 19 to 2 31 appropriate adapter and connect the ground lead to ex ternal ground 2 26 TEMPERATURE REQUIREMENTS 2 27 HP Model 8010A uses solid state components and requires no special cooling The instrument operates within specifications when the ambient temperature is be tween 09C 32 F and 55 C 1319F The pulse generator may be stored between 40 C 40 F and 75 C 1679F 2 28 INITIAL TURN ON PROCEDURE 2 29 Turn the instrument on by pressing the LINE button For nominal operation set the 8010A controls as given below and where applicable for both channels REP XI PULSE DELAY 0 1M XI PULSE WIDTH 0 1M XI TRANSITION TIME 10 us RISE AND FALL AMPLITUDE 5 volts PULSE POLARITY A B OFFSET RA OFF DELAY MODE PAR SQUARE PULSE PULSE OUTPUT verk pa asan sa SEP OPER MODE NORM SEP TRIGGERING A
36. repetition rate generator to 1032 and 033 base re ceives the output of channel B circuit 3 31 PULSE DELAY 3 32 quiescent state of the delay circuit Figure 3 4 is as follows A2Q4 is off since its base is held at zero volts by 106 collector The operating state of A2Q19 and also A2Q4 is switchable With the SEPARATE TRIG SWITCHING Q23 INTEGRATOR Square Wave of Pulse Selection Block Diagram 3010A 1 23 CR30 3 func CR30 3 ovide 1ulta 4 1093 3 out 3 E ation E ough tter iples to inte 4 it of 3 2 re Model 8010A GERING switch in its off position ALCR3 is reverse biased and A2CR2 is forward biased In this condition 1 019 is held off and A104 is Conversely with the switch in ON position A1Q4 is off and A1Q19 is on awaiting an input from SEPARATE TRIGGERING connector J6 Bistable Schmitt trigger A2Q1 A2Q2 is in the state 201 off A2Q2 on The Schmitt trigger is bistable because the input is biased between the switching thresholds so that spikes exceeding the threshold limits will trigger the circuit into switching to the other state Transistor 207 is on holding A2Q5 almost at ground potential Schmitt trigger A2Q5 A2Q6 is thus in state 205 is off A2Q6 is on 3 33 positive spike from A1Q6 collector momen tarily turns on 204 This drops A2Q1 potential and switches Schmitt trigger A
37. ters and consequently there is no output from channel The 10 volt output is the absolute amplitude i c either 10 volts of pulse with zero de offset or a voltage com bination of pulse and de offset 2 17 PULSE OUTPUT 2 18 The AMPLITUDE of each channel output is se lectable by a seven step attenuator in conjunction with the VERNIER control A switch designated SEP A B per mits a choice of separate common outputs Inthe position both outputs are combined to appear at the OUTPUT connector With the rear panel OUTPUT PLIFIER switch set to PAR 10 and the front panel out put seleetor set to A B OUTPUT B provides a maximum output of ten volts The controls of CHANNEL B vary the pulse parameters and the AMPLITUDE control readings Section 11 Model 8010A Figure 2 1 200 r PASE GENERATOR i RISE VERNIER PULSE DELAY PULSE TRANSITION TIME AMPLITUDE VERNIER OFFSET O MASE POLARITY M grouse VERNER TRANSITION TIME VERNIER FALL VERNER DELAY MODE ay sce RE TRIGGER OUTPUT OUTPUT amp OUTPUT B 0 Q ian FRONT PANEL CONTROLS Group 1 Common to Both Channels Rep Rate Selector switch selects internally triggered repetition rate external positive or negative or manual triggering for both channels Setting indicates lower limit of ra
38. 000 OHM 5 1 8 FLM 7500 OHM 17 1784 FLM 3600 OHM 57 1 8W OX 200 OHM 5 0698 0084 0698 4254 0757 0440 0698 4267 0761 0049 P p D gt gt gt gt gt x FLM 90 9 OHM 19 1 2w FLM 5100 OHM 5 1 8W FLM 360 OHM 5 1 8W FLM 2000 OHM 5 1 8W FXO FLM 6800 OHM 5 1 84 0757 0797 0698 4271 0698 4244 0698 4261 0698 4274 25523521 4R 4R A GR A 4R 4R 2100 2795 0698 4258 0757 0440 0696 0084 0698 4254 VAR 470 OHM FLM 1500 OHM 5 1 84 FXO MET FLM 7500 OHM 1 1 8W FXO FLM 2150 GHM 1 1 Bw FLM 1000 OHM 5 1 84 gt Pp pP P P gt x gt gt gt FLM 3600 OHM 5 1 84 FLM 51 OHM 57 1 4W MET FLM 90 9 OHM 1 1 2w VAR CERMET OHM 5w OT ASSIGNED 0698 4267 0758 0126 0757 0797 2100 2800 gt gt P b P VAR CERMET 470 OHM 5 FLM 3000 OHM 5 FXO FLM 3300 OHM 5 1 84 FLM 910 OHM 5 1 8w FXO FLM 360 OHM 5 1 8W 2100 2795 0698 4265 0698 4266 0698 4253 0698 4244 DD DK 2 gt x PP p p P gt VAR CERMET 470 OHM 58 FLM 2400 OHM 5 1 8W FXD FLM 4300 OHM 5 1 84 FLM 360 OHM 5 1 8W FLM 2400 OHM 5 1 89 2100 2795 0698 4263 0698 4269 0698 4244 0698 4263 P P P P gt gt gt m 0761 0014 MET 180 OHM 5 1 gt
39. 01 UF 680 20 LOOVOCH 20 5 300VDCW 620 PF 57 30CVDCw POLYSTERENE 6 8 1 250V0C w C C C FXD MICA C C TA ELECT 47 UF 10 35VDCW C TA ELECT 390 UF 20 10 VDCg FXO ELECT 150UF 20 15V0CW SELECTED ON TEST SELECTED ON TEST FXD ELECT 56 UF 10 15VCCw FXO ELECT 5 6 UF 57 35VDCw ELECT 68 UF 52 35VDCk MYLAR 047 UF 5 80VDCw FXO CER 01 UF 5680 2015 LOOVLCUW MYLAR 015 UF 10 200VDCw SELECTED ON TEST TA ELECT 1 UF 10 35VDCw CER 220 PF 80 20 1000VNC 4 TA ELECT 60 UF 20 6VDCW FXD CER FXD CER FXD MICA CER BREA 01 680 207 100VDCw 1000 PF 600VDCW 220 PF 53 309V0CW 1000 PF 600VDCW KDOWN 9 09V 10 400 BREAKDOWN 17 4V 2 400 MW SILICGN 15PIV 750 MA SILICON 15PIV 750 BREA SIL BREA SILI KDDwN 30 9V 2 400 MW 50PIV 20 MA KDOWN 15V 5 400 MW CUN 15PIV 750 MA SILICON 15PIV 750 MA BREA BREA RELAY FXD lt CORE FERRI CORE FERRI CORE FERRI TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR TRANSISTOR KDCWN 18 2V 52 1 KDOWN 13V 5 1 SPST 18VDC 47 UH 20 TE BEAD TE BEAD TE BEAD SILICON PNP SILICON PNP SILICON NPN 2N3563 SILICCN NPN 2N3227 SILICON NPN PNP SELECTED SILICON NPN SILICON PNP SILICON PNP SILICCN NPN SILICON PNP SILI
40. 010 66510 _ _ SERIES REGULATOR 1 Ql 25V CR1 CR2 LS CR4 CR3 R3 55 a 03 i 1 R7 20V Te 1 8K R4 R8 25 10K 470 ADJ R9 1K t DCR5 51 t 1 1 SERIES REGULATOR x I 9 R20 0 2 1 1 CRI6 15 gsV 1 25V ADJ R14 10K 25V 20 ee R Lu gt 8010A POWER SUPPLY BRQ 958 Figure 5 31 Power Supply Circuit 5 53
41. 0K OHM 52 1 8 FLM 200 OHM 5 1 84 FLM OHM 5 1 8W 2100 2788 0698 4280 0698 4306 0698 4238 0698 4289 FLM 130 CHM 5 178w FLM 100 GHM 57 1744 FLM 5100 OHM 57 L 8W FLM 30K OHM 57 1 8 COMP 270K OHM 5 1749 0698 4234 0758 0086 0698 4271 0698 4289 0683 2745 gt gt gt gt x FLM 150 OHM 52 1 8 FLM 150 OHM 5 1784 FLM 100 OHM 5 1749 1800 OHM 51 1 44 7500 OHM 5 1 8 0698 4235 0698 4235 0758 0086 0758 0043 0698 4275 gt gt gt gt x 25232322 FLM 1000 OHM 5 1 8 CERMET 1000 OHM 5 CARB FLM 2 OHM 1 1724 FLM 91 CHM 52 1 8W FLM 1000 UHM 5 1 8W 0698 4254 2100 2800 0727 0445 0698 4231 0698 4254 gt gt gt gt 22520102 FLM 68 1 CHM 1 1 2 FLM 68 1 OHM 1 1 26 68 1 UHM 1 1728 FLM 68 1 OHM 1 1 24 FLM 68 1 OHM 1729 0757 0794 0757 0794 0757 0794 0757 0794 0757 0794 2522 FLM 68 1 OHM 1 1 24 FLM 68 1 OHM 1 1 24 FLM 68 1 OHM 1 1724 FLM 75 UHM 5 1 8 FLM 240 UHM 57 1 8 0751 0794 0751 0794 0757 0794 0696 4229 0698 4240 o o o DDD gt gt gt gt FLM 3000 OHM 52 1 84 MET FLM 3010 CHM 1 1 8w FLM 3320 OHM 19 1784 FLM 2430 OHM 1 1 8 FLM 7500 OHM 1 L 8W 0698 4265 0757 0273 0757 0433 0757 0431 0757 0440 C
42. 1 7 k PULSE 1 4 912 NOTE 1 THIS S9 ALSO SHOWN ON 59 SCHEMATIC NO 3 SOLE FOE 58 2 THIS P O S14 AND P O S9 ALSO 15 R89 SHOWN ON SCHEMATIC NO 17 x REFERENCE DESIGNATIONS SN Aj INOPREFIX P O 514 470 18 23 30 3 CR9 10 12 13 R90 K3 5 11K 13 7 CONNECTION Q2 12 23 31 34 v 25V POLARITY SV R5 6 36 60 86 91 COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 08010 OUTPUT AMPLIFIER BOARD 0967 Figure 5 27 Positive Output Amplifier Channel B Circuit 5 45 Model 8010A x 4 m Q d j R62 i 1K GATE FROM 00 01 R80 37 028 4 883 1K 82 2 43K C3 6 8 25V 25V OUTPUT AMPLIFIER BOARD 08010 66507 25N C24 R63 R64 R65 R66 27pF 681 68 1 681 68 1 Negative Output Amplifier Channel B TO AMPLITUDE VERNIER gt INGE d 4 2 i 1 R68 R69 51 1 51 1 R92 2 Pun RIS 816 240 120 5 B Q1 SN 872 R71 C5 R74 fr 7 ae RD 27K R84 R79 R7 1K NOTE 1 THIS P O S9 AND P O 514 15 ALSO SHOWN ON SCHEMATIC NO 16 25V COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A OUTPUT AMP BRD 958 Figure 5 28 Negative Output Amplifier Channel Circuit Section V Figure 5 28 PULSE POLARITY po PULSE OG 4 906 4 059 CO
43. 2Q1 A2Q2 Transistor switch A2Q7 is turned off and the selected range capacitor is charged by current source A2Q3 This action results in a positive ramp on 205 base the slope determined by the value of the range capacitor selected by DELAY switch 1381 and the current output of the current source A2Q3 determined by VERNIER setting A13R1 When the ramp voltage reaches about 4 volts Schmitt trigger A2Q5 Q6 switches thus raising the base potential of A2Q1 above the threshold Schmitt trigger A2Q1 Q2 switches back to its original state A2Q7 turns on and the range capacitor is PULSES DELAYED W R T REP RATE GENERATOR DIFFER ENTIAL AMPLIFIER PULSES SYNCHRONI SED WITH REP RATE GEN Q17 Q18 t Section 1H Paragraphs 3 33 to 3 37 discharged very fast The base voltage of A2Q5 drops back to zero volts and 205 200 switches to its original state 3 34 The overall result is a positive pulse at A201 col lector differentiated by A2LI and the positive spikes fed to the base of differential amplifier A2Q17 The negative pulsc at A2Q2 collector is inverted by A2Q9 differentiated by A2R19 L2 and the resulting negative spikes further in verted by A2Q8 bcfore being fed to A2Q10 The positive spikes arriving at the bases of A2Q10 A2Q17 are separated by the PULSE DELAY settings 3 35 The input to both channels is derived from the collector of A1Q6 except when the DELAY MODE switch is set to SER Then the delaye
44. 49 as CO 22 at ME COS 01 COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 923 TO Al Q23 8010A DELAY WI DTH BRD 958 TEE Md 5 Figure 5 16 Width Channel A Circuit Section V Figure 5 16 5 23 Section V jl BOLOA Figure 5 17 A4 INTEGRATOR BOARD CH A 08010 66504 E D Ss Ge Pulse Shaping Ch A 25V 25V 25V 25V i SCHMITT TRIGGER 01 and 02 Bex Esk FROMAL ___ Ya o e 5 QZ7Q29 N gt J 1 RI R2 619 RB NOTE 1 RESISTOR R58 SHOWN ALSO ON SCHEMATIC NUMBER 7 E 1K 1 96K 4 C2 R3 10 310 MS s E 200 14 BEAD R4 R16 mm 150 0 47 uH TRANSITION TIME i TO SWITCHING AES DE A 25V 25V CJ RIT E j E Un 1 1 5K dA E he 25V E oo 3 REFERENCE DESIGNATIONS i TO RELAY RESISTOR R55 2 mm COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A INTEGR BRD 958 Figure 5 17 Pulse Shaping Channel A Circuit 5 25 Section V BOLOA 1 Figure 5 18 5 XEM 3 3 E FALL VERNIER E 8 9 9 9 A4 INTEGRATOR BOARD 08010 6650 _ _ 2 2822 2 I 3 dra Integration 53 902 Ch 3 25V 25V anne X im roms
45. 5 Further signal flow is dependent upon REP RATE and SQUARE PULSE switch positions 3 25 In the internal PULSE mode the 20 volts sup plied via the repetition rate switch to the base of A1Q37 holds the transistor on which in turn holds 1028 off Hence A1Q31 and AICR34 are turned on reverse biasing A1CR35 so that no collector signal from 1030 can in fluence A1Q22 Diode 1 26 is reverse biased and the flip flop output is routed 29 to the base of tran sistor A1Q22 SWITCHING 022 Figure 3 2 Rep Rate Generator Output Distribution Block Diagram Section Paragraphs 3 26 to 3 32 3 26 internal SQUARE mode causes no change in the circuit condition as the cathode of either diode A1CR26 A1CR27 is at ground potential holding A1Q28 off In the external SQUARE mode A1Q37 is switched off Transistor 1028 does not change state as its base is grounded by AICR26 or 1 27 and each external trig ger pulse changes the state of the flip flop dividing the frequency by two 3 27 Selection of the external PULSE mode will change the circuit conditions Transistor A1Q37 is still off but A1028 conducts Diode A1CR28 is forward biased cre ating a eurrent path for the flip flop While 1 29 is reverse biased the saturated A1028 turns off A1Q31 to reverse bias A1CR34 and the output of the repetition rate generator is passed to the base of A1Q22 In this mode the trigger pulse by passes the flip flo
46. 7 Q7 3 65K ai 9 35pF SCHMITT TRIGGER gt Q5 and Q6 MINIMUM 43 DELAY It EE E El E E ADJ Figure 5 15 Delay Channel A Circuit Delay Channel A GE i SCHMITT TO Q17 REFERENCE DESIGNATIONS 1 3 5 6 8 17 37 38 20V R1 22 24 25 50 51 53 54 59 AD NO PREFIX R1 16 R19 12 360 L5uH J R21 54 010 Res INVERTERS Q8 and 09 COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 3010A DELAY WIDTH BOARD 958 902 SER PAR SWITCH CH B 5 21 yode BOLON 2 BV V 20V 92 20V 90 MODE E 7 519 i 20V 1 PULSE WIDTH 914 20 92 4 262 1 C24 Als 51 Nd x 20 15 s Al5 TSR 1 VERNIER 20V 932 us in 0 us n Sae Em INPUT FROM NQ i 430 392 COLLECTOR Q8 WwW R28 R29 20V 1 5K 3 3 A NN AFN E ab El N A Ww C20 t c2 5636 1 01 332K 1 x 1 1 162 5 10 R38 d OG REFERENCE DESIGNATIONS VN PAZ 2 MINIMUM C36 WIDTH Aa 55 18pF R43 3 65K 5 R41 Q10 14 17 18 RAT INPUT FROM 43 1 R26 39 41 49 52 NOT ASSIGNED A2C26 35 25V R Q1 and Q2 R48 C32 R
47. 8 3439 MET FLM 178 OHM 1 1 84 A LR 64 0698 3447 MET FLM 422 UHM 17 1 84 80104 8010 Section b 4 Table 4 1 b Table 4 1 Reference Designation Index cont d 1 HP Stock Description A 18 65 0698 3447 R FXD MET 422 OHM 1 1 8W LR 66 0698 3441 R FXD MET 215 UHM 1 1 84 E A 1 61 0698 3440 R FXD MET 196 UHM LY 1784 A 1R 68 0757 07 gt R FXD MET 1620 OHM 13 1 4w A 18 69 0757 0180 R 31 6 UHM 1 1 88 T A 18 7C 0751 0131 R FXO MET 1620 OHM 1 1 4W A LR 71 0698 4278 R LOK OHM 5 1 84 a A LR 72 0698 4278 R FLM LOK OHM 5 1 8M 4 A LR 73 0698 4278 R FLM 10K OHM 5 1 8M d A LR 0698 4278 R FXD FLM 10K 5 1 84 4 A 18 75 0698 4282 R FLM 15K OHM 5 1 84 A 18 76 0757 0401 R MET FLM 100 OHM 1 1 8W 4 A 18 77 0151 0407 R MET FLM 200 UHM 17 1784 A 78 0698 4282 R 15K UHM 53 1 84 A LR 79 0698 4278 R FLM LOK UHM 5 1 8W A 1R 80 0758 0002 R FXO FLM 560 OHM 5 1 48 A LR 81 0698 4249 R 620 OHM 5 1 8W A 18 82 0698 4241 FLM 510 OHM 5 1 84 A LR 83 0698 4249 FXO FLM 620 OHM 5 1 8W 1R 84 0698 4254 8 1000 OHM 5 1 84 3 18 85 0698 4238 R FLM 200 DHM 5 1 8W 3 A 18 86 0757 0416 R FXO MET FLM 511 OHM 1 1 8W A LR 87 0698 4278 R FXO FLM 10K OHM 52 3 A 18 88 0698 3440 196 OHM 17 1 84 3 A IR 85 0698 3440 R
48. CON NPN 2 1711 SILICON PNP SILICON NPN SILICON PNP Model 8010A Section IV Table 4 1 Table 4 1 Reference Designation Index cont d Description 1854 0053 TRANSISTOR SILICON NPN 1853 0051 TRANSISTOR SILICON PNP 2N4037 1854 0307 TRANSISTOR SILICCN NPN NCT ASSIGNED 1853 0203 TRANSISTOR SILICON PNP gt gt P p 1854 0307 TRANSISTOR SILICON NPN 1853 0001 TRANSISTOR SILICON PNP P P FLM 1000 CHM 5 1 8w FLM 1960 CHM 17 1 8W FLM 301 OHM 1 17949 FLM 150 OHM 5 1 8 MET FLM 200 OHM 17 1 44 0698 4254 0698 0083 0757 0334 0698 4235 0757 0718 P P p gt gt gt 2552 0032 FLM 2610 OHM 1 1 8w FLM 1210 1 1 44 MET FLM 1500 OHM 1 1 44 FLM 619 OHM 1 1 88 FLM 22 UHM 5 1 4 0698 0085 0757 0734 0757 0736 0757 0418 0698 6745 P p P b gt x 0 gt x gt gt gt 2400 OHM 54 1 4 FLM 150K OHM 5 1 8W FLM 909 OHM 1 1 2w 100 OHM 57 1 4W FLM 1500 OHM 5 1 8w 0758 0034 0698 4306 0757 0819 0758 0086 0698 4258 P P P Dp gt gt gt gt FLM 22 OHM 57 1748 FLM 22 OHM 5 1 4W COMP 5 1 OHM 5 1 COMP 5 1 OHM 5 1 COMP 5 1 UHM 57 1 44 0698 6745 0698 6745 0683 0515 0683 0515 0683 0515 P P p p MET FLM 2150 OHM 1 1 8W FLM 1
49. CONTACT 7 lt N COAX e s 03 07 8 81 R12 INTEGRATION 10K 2 21K INPUT R8 C9 FROM R 4 100 100 0 01 ii 25V 25 ae CR4 C15 oun 20V 0 01 7 uE 25V SR14 C13 4 8 06 0 01 25V 1 REFERENCE DESIGNATIONS C6 17 CR3 6 03 11 210 R7 8 10 35 98 i 12 53 54 56 57 283 EV 61 63 25V NOT ASSIGNED A6R9 COFYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A INTEGR AND AMP BRD 958 15 Section V Figure 5 26 Figure 5 26 Emitter Followers Channel B Circuit 5 43 Model BULUA Section V Figure 5 27 PIO 7 OUTPUT AMPLIFIER BOARD 08010 6650 __ Muir FEN Positive 25V 25V 5 25V 25V 25V 25 Output Amplifier Ch R54 CURRENT R57 R58 R36 R53 56 56 a 33K gt 022 023 E 4 Cue NOTE 1 856 N e ad PULSE 89 zi 22K K CRI PO 59 mi d Q2 RI2 PULSE POLARITY 85 10 CR13 NECTED 15 15 016 p ATER C23 R51 R50 R49 R52 6 l nF 3K 240 75 3 01K NOTE 2 2 859 510 5 PIO S14 i 906 1 RO ap NEGATIVE 211 842 R43 R44 R46 4 681 681 681 68 1 68 1 CONNECTION FROM E E R39 OF SCHEMATIC INPUT FROM 9 m F N Vag A N 15 AMPLITUDE VERNIER CRIO C19 CR9 C20 5 11V G 1 511V 4 I NE SQUARE POS9 _
50. California 94040 assembly motor battery capacitor coupler diode delav line lamp amperes automatic frequency control automatic gain control beat frequency oscillator beryllium copper binder head bandpass brass backward wave oscillator counter clockwise ceramic cabinet mount only coefficient common composition complete connector cadmium plate cathode ray tube clockwise deposited carbon drive electrolytic encapsulated external farads flat head fillister head fixed germanium ground ed IF IMPG INCD INCL INS INT k LH LIN LK WASH LOG LPF m M MET FLM MET OX MFR MINAT MOM MTG MY n N C Ne Ni PL N O NPO wow oy H w H H n HM H H own H NHM placement parts Table 4 1 lists parts in alpha numerical order of their reference designators and indicates the des cription and HP stock number of each part 4 6 Section IV Paragraphs 4 1 to 4 6 Hewlett Packard S A Rue du Bois du Lan 7 1217 Meyrin Geneva Switzerland Specify the following information for each part Model and complete serial number of instrument Hewlett Packard stock number Circuit reference designator Description To order part not listed in Table 4 1 give a complete description of the part and include its function and location REFERENCE DESIGNATORS fuse p filter Q heater R jack RT relay S inductor T meter TB micro circuit TP ABBREVIATIONS henri
51. DE SILICUN 30 MA DIODE SILICON 30PIV 30 DIODE GERMANIUM DIODE GERMANIUM DIODE BREAKDOWN 9 09V 2 400 DICOE BREAKDCwN 6 19 5 400 DIGOE GERMANIUM 25 PIV 100 MA GERMANIUM 25 PIV LOOMA DIGOE SILICON 30 MA GERMANIUM 25 PIV 100 SILICON 30PIV 30 CICOE SILICCN 30 CIGDE SILICGN 30PIV 30 MA NOT ASSIGNED DICDE SILICON 30PIV 30MA THRU CR39 REED RELAY SPST 18VDC CCIL FXD RF 323 UH COIL FXO 47 UH 20 CORE FERRITE BEAD COIL RF O 47uH COIL CCIL FXO RF COIL FXD RF CCIL FXD RF TRANSISTOR SILICON NPN 2N3904 TRANSISTUR SILICON NPN 2N3904 TRANSISTOR SILICON NPN 2N3904 TRANSISTOR SILICON NPN 2N3904 TRANSISTOR SILICON PNP 2N3906 TRANSISTOR SILICON PNP 2N3906 TRANSISTOR SILICON PNP 2N3906 THRU 913 NOT ASSIGNED TRANSISTOR SILICON PNP 2N3906 TRANSISTOR SILICCN NPN 2N3904 TRANSISTOR SILICON NPN 2N3904 TRANSISTOR SILICON PNP 2N3906 TRANSISTOR SILICON NPN 2N3227 TRANSISTOR SILICON NPN 2N2218 TRANSISTOR SILICON NPN 2N3227 TRANSISTOR SILICON PNP TRANSTSTOR SILICON NPN 2N3904 TRANSISTOR SILICON NPN 2N3904 TRANSISTOR SILICON NPN TRANSTSTOR SILICON NPN TRANSISTOR SILICON PNP TRANSISTOR SILICON NPN 2N3904 TRANSISTOR SILICON NPN TRANSISTUR SILICON PNP 2N3906 TRANSISTOR SILICON PNP 2N3906 Section IV 8010 Table 4 1 Table 4 1 Reference Designation Index cont d Reference
52. EMATIC NO 3 2 THIS 58 AND P O 513 ALSO SHOWN ON SCHEMATIC NO 10 REFERENCE DESIGNATIONS NO PREFIX C18 23 58 13 CRG 10 12 13 K3 13 7 Q2 12 23 31 34 R5 6 36 60 86 91 95 96 97 Section Figure 5 20 Positive Output m 05 08 25V 25 25 25 25V Amplifier Channel A 258 R36 E Q22 OG o N gt 47 CRI2 1 s CR13 2 R51 R50 R49 R52 lone 3 240 75 3 01K a 51uH 510 82 ITUDE TO AMPL VERNI PULSE POLARITY e es 3 CONNECTION TO PULSE POLARITY SWITCH S13 SEE LEFT HAND SIDE OF SCHEMATIC 25V 25V COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A OUTPUT AMP BRD 958 Figure 5 20 Positive Output Amplifier Channel A Circuit 5 31 3010A 4 PE JO VES 3 i A A6 OUTPUT AMPLIFIER BOARD 08010 66506 T3 gt 2 C24 R63 R64 R65 R66 _ 17 681 681 681 681 FROM 010 01 R77 12 210 SluH 0 R85 2 R80 Q29 i 881 8 I 7 5K WN R83 028 c4 Ww 1 2 R78 R79 R82 56 56 2 43K 25V C3 6 8 25V 25V 25V ov REFERENCE DESIGNATIONS NOTE 1 THIS P O 58 AND P O 513 15 ALSO SHOWN ON SCHEMATIC NO 9 QI 24 30 35 37 R61 85 92 Figure 5 21 035 Cano R67 R68 R69 51
53. FXD FLM FXD FLM FXD FLM FXD FLM FXD FLM FXD FLM VAR CERM FXD FLM DORR FXD FLM FXO FLM FXO FLM FXO FLM FXO FLM FXO FLM FXD FLM SILICUN NPN SILICON NPN SILICON NPN 2N3053 SILICON NPN 2N3053 SILICON NPN SILICCN NPN 1000 CHM 5 1 Bw 3300 CHM 5 1 8W 51 OHM 5 1 4w 10K OHM 5 1 8W 1800 OHM 5 1 4W 2000 OHM 5 1 8W 1800 OHM 5 1 84 ET 470 OHM 1000 OHM 5 1 8w 25 CHM 5 3w 1000 OHM 5 1 8w 3300 OHM 52 1 8w 51 OHM 5 1 4w OHM 5 1 8w 1800 OHM 52 1 4W 2000 OHM 52 1 8w 1800 OHM 5 1 8w 2100 2795 0698 4254 0812 0017 gt p p 0698 3229 0698 4244 0757 0437 0698 4285 PP P P P 08010 61901 2100 0225 08010 61902 2100 0225 08010 61903 2100 0225 08010 61904 2100 0225 08010 61905 2100 0225 08010 63401 CERMET 470 CERMET IK CHM FXD FLM 360 5 FLM 20K 52 ASSY REP RATE SWITCH R VAR 5 OHM ASSY DELAY SWITCH CH R VAR 5K OHM ASSY DELAY SWITCH CH R VAR 5K ASSY WIDTH SWITCH CH VAR SK OHM ASSY WIDTH SWITCH CH VAR SK OHM ASSY ATTEN CONTAINS ASSY S 9 FLM 1000 OHM 5 1 84 WW 25 CHM 5 3w 1 8w FXO FLM 4750 OHM 1 1 8W 1 8w ASSY S A8 A9 4 15 Section IV Table 4 1 Table 4 1 Reference Designation Index Reference Designation
54. ICON SILICON SILICON STLICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICCN SILICON SILICON SILICCN SILICON SILICON 100 DHM 2 2W PNP PNP NPN PNP NPN NPN NPN NPN PNP NPN PNP PNP PNP PNP PNP NPN NPN PNP NPN NPN NPN PNP PNP NPN NPN NPN NPN PNP NPN NPN Reference Designation Index cont d 2N2218 2N7C3 2 3227 2N3053 2N2 904A 2N2904A SELECTED SELECTED SELECTED SELECTED 2N2218 2N2218 560 GHM 5 1 4w 43 OHM 5 1 4w 43 OHM 5 1 5 1 8W LOK OHM 10K OHM 10K OHM 5 1788 5 1 8w Section IV Table 4 1 0757 0198 FLM 100 OHM 1 1 724 NCT ASSIGNED R FLM 100 OHM 1 1 2W re P P P gt 0757 0198 0757 0411 FXD MET FLM 332 OHM 12 1 8w 0757 0740 FLM 2210 OHM 1 1 4W 0751 0198 FLM 100 OHM 1 1 2w 0698 3332 FLM 80 6 OHM 1 1 72 0698 3223 FLM 1 24K CHM 1 1 8 P P P gt gt 0757 1095 FLM 1440 OHM 1 1 8w 0698 7032 FLM 100 OHM 2 0698 7032 FLM 100 OHM 2 1 gt p DDR Section Model 8010A lt lt i Table 4 1 32 Table 4 1 Reference Designation Index cont d Reference N ORDRE Bn 0698 4244 FLM 360 UHM 57 1 8W 0698 4264 FLM 2700 OHM 57 1 8W o gt CERMET 4000 OHM FLM 12K OHM 57 1 8W FLM 15
55. KNCB DELAY wIDTH CHA 08010 61611 08010 61612 08010 67401 08010 67402 08010 67403 ASSY KNGB TRANS TIME SwITCH CHA ASSY KNCB TRANS TIME SWITCH CHA 8 ASSY KNCB RISE FALL VERNTER CHA A ASSY KNOB RISE FALL VERNIER CHA B ASSY KNCR AMPLITUDE CHA A 08010 67404 08010 67405 08010 67406 08010 67407 08010 67408 08010 67409 08010 67410 08010 67411 ASSY KNCB AMPLITUDE CHA B ASSY VERNIER A ASSY KNCB VERNIER CHA 8 4 17 Model 8010 Section Paragraphs 7 1 and 5 2 SECTION V CIRCUIT DIAGRAMS 5 1 INTRODUCTION 5 2 This section contains the circuit diagrams and nance of the Model 8010A Table 5 1 lists notes which component location drawings necessary for the mainte apply to the schematic diagrams Table 5 1 Schematic Diagram Notes Refer to MIL STD 15 1 for schematie symbold not listed in this table Unless otherwise indicated Waveform test point capacitance in mircofarads with number inductance in microhenries resistance in ohins All switch positions shown cew Front panel marking indicates position Rear panel marking Avalanche zener diode Optimum value selected at factory Numbers in box indicate wire color using resis Indicates screwdriver adj tor color code e g WIT RED GRN Black Green Brown Blue Primary signal path Red Violet Orange Gray Feedback path Yellow White tion V
56. MK cp 20V C26 CR31 B 921 m C22 1 0 957 934 1 19 26 CP SQUARE A 58 PULSE CR28 CR29 xls 5 25V 25V R81 620 0 59 PULSE Br NOTE Figure 5 14 Square Wave or Pulse Selection Circuit 25V RE R88 10K 1 C30 CR37 915 926 1 iLSQuAmE I 1 934 2 R91 210 25V R62 620 2 R67 1 CR32 R102 22 17 2 2uH 25V R83 620 Q33 R89 1 25V CR38 R103 22 25V R72 10K 25V Abs C28 Hor RM R85 1K 200 Q29 25V 25V R90 1K 231 0 25V C32 8010A TIMING BOARD 958 Section V Figure 5 14 FROM 2011 CHANNEL A WIDTH OUTPUT TO SCHMITT TRIGGER A4C1 INTEGRATOR CHANNEL A FROM A3Q11 CHANNEL B WIDTH OUTPUT INTEGRATOR CHANNEL 3 im AE te Yodel 8010A N 1 m 20V 25V A2 DELAY WIDTH BOARD A 08010 66502 Section V Figure 5 15 925 92 20V R54 20V ORIGINATES C37 FROM A3 150 ibaa SEDE 1 RI SEPARA Me fb 340 pH I iE gt Q19 FROM EMITTER A106 TRIGGER R10 CRZ Q1 and Q2 100 R9 240 928 C38 EM ore CURRENT SOURCE 03 20V 332K 20V R6 162 of y SN R18 C1
57. NNECTION TO 0127 9 901 47Q16 COLLECTOR NOTE 1 REFERENCE DESIGNATIONS C2 5 CR7 8 Kl 12 91 24 30 35 37 R61 85 92 17 5 47 Section V Figure 5 29 Model 8010A 856 135330 04 0108 H8W9 03 4 1131 3 8 0 61 1 918 402 o 8l YOLVANALLY 8 OL dOIVINHLIV 01 AGZ A 1 TI TT 60699 01080 135330 20 6V 0 4 SNOI1VN91S30 328383434 Figure 5 29 DC Offset Circuit 5 49 Model 8010A 17 ATTENUATOR BOARD 08010 63401 BEAD BEAD 1 DC OFFSET FROM A9 1 Sl Channel I 1 10 FROM NEGATIVE ANPLIFIER FROM POSITIVE AMPLIFIER Channel B 1 934 DC OFFSET FROM A9 FR NE SAME SCHEMATIC AS ABOVE Ouse 1 R99 1 5 R5 REFERENC DESIGNATIONS 16 FROM POSITIVE RI 7 106 7 AMPLIFIER 100 1 4 6 99 COPYRIGHT 1970 BY HEWLETT PACKARD GMBH 8010A OUTPUTS AND 5 958 Figure 5 30 Output and Attenator Circuit Section V Figure 5 30 5 51 Model 8010A LINE F1 115V 2A 230V 1A 20V 25V Section V Figure 5 31 POWER SUPPLY BOARD 08
58. NTROLS 27 Output Amplitude PAR NORM 10 V 50 28 Separate Triggering A 29 Separate Triggering NOTE Model 8010A Switch selects square wave output symmetrical to ground or pulse output The rise and fall time and frequency are variable in square wave mode Pulse output characteristics are determined by front panel settings Adjusts the rise time of the pulse Clockwise rotation of the vernier control adjusts the rise time from the faster value to the slower value shown on the time range selector switch Adjusts the fall time of the pulses Clockwise rotation of the vernier control adjusts the fall time from the faster value to the slower value shown on the time range selector switch Selector switch selects the amplitude range Position selected is the upper limit of the amplitude range With 11 in position A B the selector switch of B controls the amplitude of the two added output pulses Adjusts the output pulse Counterclockwise rotation of the vernier control ad justs the amplitude from the limit selected to 1 5 0 2 of that value Switch selects polarity of output pulse Clockwise rotation of the offset control adjusts the base line of the output pulse from 2V to 2 V With 11 in position A the baseline is controlled from channel B Switch controls presence or absence of baseline shift in the output signal In the 10 V position a max output amplitude of 10 V is available from output B wi
59. O FLM 470 5 1 4 FLM 470 OHM 5 1 4 FXO FLM 1000 OHM 1 1 88 FXD 9090 OHM 13 1 84 0758 0029 0758 0029 0758 0029 0757 0280 0757 0288 PP p p gt 002020 gt gt gt gt gt gt gt x FLM 2000 UHM 5 1 8w FXO 510 OHM 5 1 8 FLM 510 UHM 5 1 8 FLM 2000 OHM 54 1 84 FLM 470 OHM 52 1 44 0698 4261 0598 4247 0698 4247 0698 4261 0758 0029 P p P gt gt x O O lt O gt gt gt gt gt x gt x x x gt 0758 0029 0758 0029 0757 280 0757 0288 0758 0029 FLM 470 OHM 5 L 4W FLM 470 OHM 5 1 4W FLM 1000 UHM 1 1 64 FLM 9090 UHM 12 L dw FLM 410 UHM 57 1 4W O00 00 7070 20 gt x FLM 470 OHM 5 1 4W ELM 470 OHM 52 1748 FLM 1000 OHM 12 1 8W FLM 9090 QHM 1 1 gw FLM 2000 OHM 5 1 84 0758 0029 0758 0029 0757 0280 0757 0288 0698 4261 P p p 0 OO gt x gt gt FLM 510 OHM 57 1 84 FLM 510 OHM 5 1 8 FLM 2000 UHM 5 1 4 FLM 470 OHM 9 1 4W FLM 470 OHM 5 1 4w 0698 4247 0698 4247 0698 4261 0758 0029 0758 0029 P pP P gt gt O O O O gt gt x FLM 470 UHM 5 1 44 FLM 1000 OHM 1 1 84 FLM 9090 OHM 1 1 84 LOK UHM 17 1 8w FLM LOK OHM 1 1 8w 0758 029 0757 0280 0757 0288 0757 0442 0757 0442 P p p gt 00000 gt Z gt gt gt 08010 66511 SUPPLY ASSY 0180 0050 AL ELECT 40 UF 575 102 50
60. OCO gt gt gt gt 2200 OHM 5 174w 56 CHM 57 lW 56 OHM 52 14 FLM 510 OHM 57 178w FLM 20K OHM 57 1 8W 0758 0044 0761 0041 0761 0041 0698 4247 0698 4285 gt gt FLM 200 OHM 5 1 8W FLM 1000 CHM 5 1 84 FLM 68 1 CHM 1 FLM 68 1 1 FLM 68 1 OHM 1 0698 4238 0698 4254 0751 0194 0757 0794 0757 0794 MET FLM 68 1 CHM 12 MET FLM 51 1 UHM 1 MET FLM 51 1 OHM 1 FLM 51 1 OHM 1 FLM 2700 UHM 5 1 84 0757 0794 0757 1000 0757 1000 0757 1000 0698 4264 CERMET 470 OHM 5 FLM 200 OHM 54 1 8W FLM 2700 OHM 5 FLM 3000 57 1 8W 240 OHM 5 1 8W 2100 2795 0698 4238 0698 4264 0698 4265 0698 4240 120 OHM 5 1 8w x D 0698 4233 4 12 Model 8010A Section IV Table 4 1 Table 4 1 Reference Designation Index cont d Description 510 OHM 5 1 84 56 OHM 5 MET 56 OHM 54 lw FLM 2200 OHM 5 1 4W 0698 4247 0761 0041 0761 0041 0758 0044 gt P P gt gt gt gt gt MET FLM 7500 OHM 1 1 80 FLM 2430 UHM 13 1 8h VAR CERMET 1000 OHM 20 FXD FLM 1000 OHM 5 1 8W CARB FLM 2 OHM 1 1 2 0757 0440 0757 0431 2100 2800
61. R 2000 680 20 1000VDCw A 4C 13 0160 0134 C MICA 220 PF 5 300VDCw Section Model 8010A Table 4 1 Reference Designation Table 4 1 Reference Designation Index cont d Description gt gt gt gt P gt P gt P P P P P P p gt p P b gt P P gt P P P P P gt P A A A A A P gt gt p P gt P p P p P gt gt p p gt gt gt gt gt gt PPR HHH HS SEALS 0150 0093 0160 0134 0180 0291 0150 0093 0160 2198 0150 2213 0160 3246 0180 0376 0180 0294 0180 1747 0180 0196 0180 1712 0180 1773 0160 2672 0150 0093 0160 0194 0180 0291 0160 2139 0180 0106 0150 0093 0150 0050 0160 0134 0150 0050 1902 0037 1902 3223 1901 0179 1901 0179 1902 3288 1901 0044 1902 3205 1901 0179 1901 0179 1902 0594 1902 0555 0490 0733 9100 1613 9170 0029 9170 0029 9170 0029 1853 0203 1853 0203 1854 0092 1854 0260 1854 0019 5080 1044 1854 0091 1853 0203 1853 0203 1854 0307 1853 003 1854 0003 1853 0090 1854 0307 1853 0090 FXD CER FXD MICA 01 UF 80 20 100VDCG w 220 57 300VDCw TA ELECT 1 UF 10 35VPCW FXD CER FXO MICA
62. R2 3 8 The result is a negative pulse at the emitter of 1017 that is coupled via transistor 1015 which keeps the source impedance constant to effect a quick transfer and then differentiated by LR The resulting negative spikes are fed to the square wave or pulse selection circuit In either PULSE or SQUARE mode negative spikes are applied to emitter follower 105 the output of which is inverted by A1038 and supplied as the positive trigger output as well as being passed by A1014 to differ ential amplifier 106 07 3 9 In the free running mode diodes and A1CR4 clamp the collectors of 1091 and 102 to ap proximately 11 volts determined by Zener diode A1CR7 This ensures that no other collector voltage is developed and no signal is passed to Schmitt Trigger A1Q3 Q4 should an external trigger signal be applied to J2 3 10 EXTERNAL TRIGGERING 3 11 In this mode of operation REP RATE switch 1251 is set to either EXT or EXT MAN With 1251 in the EXT position the Model 8010A is trig gered by the negative going slope of a negative trigger ap plied to J2 With A12S1 in the EXT position the instrument is triggered by the positive going slope of a positive trigger signal 3 2 Model 8010 3 12 Trigger signals applied to J2 are fed to differential amplifier A101 A102 Diodes ALCRS and pro tect the base emitter junctions of A1Q1 and 102 against excessive reverse voltages W
63. T 1 UF 107 35VDCw FXO MICA 110 PF 5 300VDCw CER 1000 600VDCW FXD TA ELECT 1 UF 10 35VDCw FXO TA ELECT 1 UF 10 35VDCw C FXO MICA 110 PF 5 300VDCw 55 ASSIGNED 51 UF 5 15VDCw TA 51 UF 5 15VDCW C TA ELECT 1 UF 10 35VDCW 8010A gt P gt gt rer P P p gt P P P P P P P P P p P NONDO gt P P gt NNEOO 0180 0291 0160 0291 0180 0291 0180 0291 0160 2204 19 1 040 1901 0040 1901 0040 1901 0040 1910 0016 1910 0016 1902 3150 1902 0049 1910 0034 1901 0034 1901 0040 1901 0034 1901 0040 1901 0040 1901 0040 1901 C040 0490 0733 9140 0111 9100 1613 9170 0029 9140 1613 9140 0096 9140 0098 9140 0098 9140 0098 1854 0215 1854 0215 1854 0215 1854 0215 1853 0036 1853 0036 1853 0036 1853 0036 1854 0215 1854 0215 1853 0036 1854 0260 1854 0053 1854 0260 1853 0034 1854 0215 1654 0215 1854 0215 1854 0215 1853 0034 1854 0215 1854 0329 1853 0036 1853 0036 Section IV Table 4 1 Table 4 1 Reference Designation Index cont d TA ELECT 1 UF 10 35VDC TA ELECT 1 UF 10 35V0CW TA ELECT 1 UF 10 35V0Ch TA ELECT 1 UF 102 35VDCW MICA 100 5 300VDCw SILICON 30 DINDE SILICON 30 MA DIC
64. XO FLM 68 OHM 5 1 8W A 2R 40 0757 0401 R FXO MET FLM 100 OHM 12 1 8W A 28 41 0698 6746 R 43 OHM 5 1 44 28 42 0751 0827 2740 OHM 1 1 2 28 43 0757 0354 R FXO FLM 3650 OHM 1 1 48 A 2R 44 0698 4249 FLM 620 OHM 5 1 8W A 28 45 0698 4273 FLM 6200 OHM 5 1 8w A 2R 46 0698 5703 FLM 33 OHM 5 1 8W A 2R 47 0698 3445 R FXO FLM 348 OHM 17 1 8W A 2R 48 0698 4242 FXO FLM 300 OHM 5 1 8W A 2R 49 0698 4261 R FXO FLM 2000 OHM 5 1 8W A 2R 50 0760 0024 R FXO OX 100 DHM 54 1 A 28 51 0160 0024 R OX 100 OHM 5 A 2R 52 0698 6802 10 OHM 5 1 8W 2 53 0698 6802 R FXO FLM 10 OHM 5 1 88 A 28 54 0698 4235 FXO FLM 150 OHM 5 1 8W A 3 08010 66502 DELAY WIDTH CH BySAME AS 4 08010 66504 INTEGRATOR CH A 4C 1 0150 0050 CER 1000 PF A 4C 2 0180 0291 C FXO TA ELECT 1 UF 10 35V0CW 4 3 0160 2206 FXO MICA 160 PF 5 A 4 0150 0093 C CER 01 UF 680 20 100 0 A 4C 5 0150 0093 01 UF 680 20 100VDCW 4C 6 0150 0121 CER LUF 5804 2012 50VDCw 4C 1 0160 2143 FXO CER 2000 PF 680 20 1000VO0CW A 4 8 0160 0134 MICA 220 5 300VDCw A 4 9 0150 0093 CER 041 UF 580 205 A 4C 10 0150 0093 C CER 01 UF 680 20 100VDCw A 4C 11 0150 0121 C CER 1UF 5804 20 50VDCW 4C 12 0160 2143 C CE
65. ce the trigger output is available NOTE In all modes of operation it is important that the width delay and rep rate be compatible i e the width plus delay must be smaller than the period determined by the REP RATE setting taking into account the maximum available duty cycle settings will not harm the in strument but the output may be wrongly interpreted 2 11 DELAY MODE 2 12 Model 80104 is delivered with a fixed delay of approximately 80 ns between the trigger output and the signal from the internal repetition rate generator With the DELAY MODE set to PAR the pulse is independently adjustable for both channels Switching to the SEP posi tion combines both generators making ehannel A delay the reference for channel In the SEP mode double pulses are not available 2 13 SQUARE PULSE MODE 2 14 The SQUARE mode seleetable for either channel produces an output with variable repetition rates rise and fall times and amplitude When operated in the external trigger mode maximum 10 the output frequency is half that of the input trigger As the square wave output is symmetrical to ground neither channel PULSE POLAR ITY switches have any effect 2 15 TEN VOLT OUTPUT 2 16 parallel driving channel A with channel rear panel control and adding them front panel control a maximum amplitude of 10 volts is available The controls of channel B become the master for varying the pulse parame
66. d output of channel A is fed as the trigger input to channel B 3 36 WIDTH CIRCUIT 3 37 In the SINGLE PULSE mode 2017 is cut off by A2Q18 Initially off A2Q10 turns on when the posi tive spike from A2Q8 delayed w r t the repetition rate generator output is applied to its base Figure 3 5 The preceding negative spike which is not delayed has no effect Bistable Schmitt trigger A2Q11 A2Q12 is in the state A2Q11 off 2012 on Transistor 2016 is on holding SWITCHING TRANSISTOR A1Q23 RRENT CU SOURCE Figure 3 4 Delay Generator Block Diagram Section Paragraphs 3 38 to 3 45 A2Q14 base almost at ground potential hence A2QL4 is off and A2Q15 is on 3 38 When A2Q10 turns on the base potential of A2 011 drops and switches Schmitt trigger A2Q11 A2Q12 Transistor switch A2Q16 is turned off and the selected range capacitor is charged by current source 2013 This results in a positive ramp on A2Q14 base the slope de termined by the value of the range capacitor selected by WIDTH switch A15S1 and the current output of the cur rent source 2013 determined hy VERNIER setting AI5R1 When the ramp voltage reaches about 4 volts Schmitt trigger A2014 Q15 switches thus raising the hase potential of 2011 Schmitt trigger 2011 2012 switches hack to its original level A2Q16 turns on and the range capacitor is discharged very fast The base voltage of A2014 drop
67. ed and regulated to provide dc outputs of 25 25 and 20 volts The two primary windings of transformer are switched in parallel for 115 V operation or in series 230 oper ation by S18 The regulator circuits for the 25 V and 25 V supplies are identical An error amplifier detects variations the output voltage The variations are in verted amplified and applied to a series regulator via driver The 20 volt output is obtained from the regu lated 25 volts by a bootstrapped voltage source osition nsistors the d VER dat the il about 3 equal current 3 3 n either M A907 3 attenu 3 source 3 pulses 4 E 9 4 3 1 4 heir 4 mode ig both 3 resis 2 iaintain 3 E BT ical re MEE ven fed n load 3 ield at 3 CP DL AFC AGC BFO BeCu BH BP BRS CER CMO COEF COM COMP COMPL CONN CRT cw DEPC DR ELECT ENCAP EXT FH FIL H FXD Ge GRD ution uw H f H H M M H H h HI u ut NH Model 8010A INTRODUCTION SECTION IV REPLACEABLE PARTS or in Western Furope to This section contains information for ordering re ORDERING INFORMATION To order a replacement part address the order or inquiry either to your authorized Hewlett Packard sales representative or to CUSTOMER SERVICE Hewlett Packard Company 333 Logue Avenue Mountain View
68. el 8010A will generate internally any re petition rate from 1 Hz to 10 Mllz The repetition rate is established by setting the REP RATE selector to any of the seven internal ranges and then adjusting the REP RATE VERNIER to the specific rate desired 2 5 EXTERNAL TRIGGER MODE 2 6 With the REP RATE selector set to EXT or EXT external signals may be used to generate pulses in the Model 8010A Trigger signals which will cause one pulse out for each trigger in may be sine waves or pulses of either positive or negative polarity up to 10 MHz Sine waves must be of at least 1 volt peak to peak amplitude and pulses at least 0 5 volt peak and 20 nanoseconds wide Maximum signal is 10 volts peak 2 7 MANUAL TRIGGER MODE 2 8 With the REP RATE selector set to the EXT MAN position a single output pulse is generated by the Model 8010A for two actions of the manual push button This is only true when both channels are in the PULSE mode 2 9 GATING MODES 2 10 front panel switch selects three modes of oper ation SYNCH NORM or ASYNCH In the NORM mode of operation the 8010A functions normally In the SYNCH mode the rep rate generator is turned off until a gate signal of at least 2 is applied to the GATE INPUT The gate signal turns the instrument on producing pulses determined by the front panel settings The ASYNCH mode functions in a similar manner except that the 8010A is turned off before the delay circuit and hen
69. es NPN hexagonal mercury NRFR NSR intermediate freq impregnated incandescent OBD include s OH insulation ed Ox internal 3 kilo 10 PC pF left hand linear taper PH BRZ lock washer PHL logarithmic taper PIV low pass filter PNP milli 10 3 P O meg 108 POLY metal film PORC metallic oxide POS manufacturer POT miniature PP momentary PT mounting PWV mylar RECT nano 10 9 RF normally closed RH neon nickel plate RMO normally open RMS negative positive zero RS zero temperature RWV coefficient plug transistor resistor thermistor switch transformer terminal board test point u f W w uonm on negative positive negative not recommended for field replacement not separately replaceable order by description oval head oxide peak printed circuit picofarads 10 12 farads phosphor bronze Philips peak inverse voltage positive negatlve positive part of polystyrene porcelain position s potentiometer peak to peak point peak working voltage HMH W W M rectifier radio frequency round head or right hand rack mount only root mean square recommended spares reverse working voltage n n H lt S B SCHEM Se SECT SEMICON Si SIL SL SPG SPL SST SR STL Ta TD TGL THD Ti TOL TQ TRIM TWT VAR VDCW wow og n on gon vacuum tube neon bulb photocell etc voltage regulator cable socket crys
70. for processing by the in tegrated circuits The input to the integrators is switch able selecting either the width output for normal pulses from the repetition rate generator to provide the square wave output The positive and negative pulses from the GATE INPUT POSITIVE DIFFEREN SCHMITT TIAL AMP 01 02 Figure 3 1 integrator separated by emitter followers and fed to their respective amplifiers Either of the two amplifiers per channel depending on the desired pulse polarity may be connected to the attenuator and hence to the output connector A rear panel switch is provided to parallel both output amplifiers and in the A B mode produce a 10 volt output at channel B connector A dc offset facility permits the base line of cach output to be set independently 3 3 following description cxplains the operation of channel A execpt where it is necessary to describe a common function 3 4 REP RATE GENERATOR 3 5 The mode of operation of the Model 8010A is established in this circuit i e internal external or manual triggering depending on the setting of REP RATE selector switch 1251 Refer to the schematics and the block diagram Figure 3 1 for the following discussion DIFFER TRIGGER OUTPUT FLIP FLOP SQUARE WAVE OR PULSE SELECTION TRIGGER AMPLIFIER Q38 FROM WIDTH GENERATORS AND B TO INTEGRATOR A AND B Repetition Rate and Trigger Input
71. ircuit Pulse Shaping Channel A Circuit Integration Channel A Circuit Emitter Followers Channel A Circuit Positive Output Amplifier Channel A Circuit Negative Output Amplifier Channel A Circuit Delay Channel B Circuit AM NES Width Channel B Circuit Pulse Shaping Channel B Circuit Integration Channel B Circuit Emitter Followers Channel B Circuit Positive Output Amplifier Channel B Circuit Negative Output Amplifier Channel B Circuit DC Offset Circuit p ui ee E i Output and Attenuator Circuit Power Supply Circuit LIST OF TABLES Specifications Reference Designation ides Schematic Diagram Notes List of Illustrations and Tables Id ts us 371 lt Q br e Section 1 Table 1 1 Table 1 1 PULSE CHARACTERISTICS with 50 Q load impedance Rise and Fall Times Sep Outputs lt 10 ns to second in eight ranges ranges are common for rise and fall times Inde pendent verniers provide scparate control of rise and fall times within each range up to a maximum ratio of 1 10 Combined Outputs lt 12ns to 1 second 10 V Output lt 20 ns to 1 second Accuracy 10 of setting 2 of full scale 4 ns Linearity For transition time gt 30 ns maximum am plitude deviation from a straight line between the 10 and 90 points is less than 4 of pulse am plitude Overshoot and Ringing lt 5 of pulse amplitude Pulse
72. ischarging time and the clamp voltage form the fall time and the approximate base line respectively Voltage source A4Q12 through A4Q14 and A4Q17 A4Q18 set the reverse voltage for A4CR3 and A4Q7 respectively during time t Transistors A4010 and 4015 stabilize the base voltage temperature drift of their respective current sources Lead inductance is reduced by using switching transistors A4Q8 A4Q9 to switch the ramp capacitors Likewise relay contact of A4K1 is open on the 10 n range to reduce stray capacitance caused by the lead to the range switch 47V VOLTAGE SOURCE CURRENT SOURCE Qu SWITCHING TRANSISTORS Q6 Q7 CR9 CR8 R16 i RI7 1 CURRENT SOURCE 016 13V VOLTAGE SOURCE Section Paragraphs 3 46 to 3 52 3 48 EMITTER FOLLOWER AND INVERTER 3 49 The emitter follower and inverter circuit isolate the positive and negative amplifiers After passing through emitter followers A4Q4 A4Q20 the negative pulses from the integrator are routed to the differential amplifier A6Q3 607 and emitter followers A6Q10 A6Q11 The integra tor output from ROL is switchable Rear panel switch OUTPUT AMPLIFIER set to its PAR 10 V position dis connects the output of channel A Integrator from the base of A6Q3 and connects channel A output amplifier to chan nel B integrator output This parallels both output ampli fiers to provide 10 volts at output B in the A B mode 3 50 output of A6010
73. ith 1251 in the EXT position AIR2 is connected to 20 volts so AICR 2 and AICR3 are reverse biased the collector of A1Q2 remains clamped at 11 volts When a negative trigger is applied 101 conducts less and the increase in 101 collector voltage is fed through AICRI to the base of A103 This causes Schmitt trigger A1Q3 A1Q4 to switch thereby gencrating a positive going spike across The negative going spike produced when Schmitt trigger A1Q3 A1Q4 switches back at the end of the trigger sig nal is blocked by 3 13 With 1251 in the EXT position is con nected to 20 volts so AlCR1 and are reverse biased the collector of 101 remains clamped at 11 V positive trigger signal raises the emitter voltage of A1Q1 and via A1R13 also raises the emitter voltage of A1Q2 Transistor A1Q2 thus conducts less and the increase in its collector voltage is fed through AICR2 to the base of A1Q3 The Schmitt trigger then behaves exactly as in the EXT mode described above 3 14 In either of the two EXTernal positions REP RATE selector switch 1251 connects A1 R48 to 25 volts This holds the base of A1Q18 at approximately 0 2 volt Thus rep rate generator A1Q17 A1Q18 is cut off current source 1019 draws all current through AICR32 from ground until a positive spike from Schmitt trigger A1Q3 A1Q4 momentarily reverse biases A1CR22 The base volt age of 018 then rises and the
74. k A4C3 R10 into the circuit to reduce the rise an fall time of the current switched in the integrator No net work is added on the 10 n range as this RC combination would slow down the rise and fall times 3 44 INTEGRATOR 3 45 The integrator circuit establishes the rise and fall time characteristics of the pulse and forms the pulse top SCHMITT TRIGGER DIFFERENTIAL 01 02 AMPLIFIER 2017 INVERTERS 08 09 RENT R SWITCH 07 PULSE DELAY Width Generator Block Diagram re de en 4 uit ol 02 22 or 4 et on 3 Model 8010A and base line The rise and fall times are produced by the charging and discharging of the selected ramp capacitors 3 46 output of the pulse shaping circuit is passed to the integrator switching transistors A4Q6 A4Q7 During the time t Figure 3 6 A4Q6 is off and the current from current source 14016 charges the ramp capacitor nega tively Voltage souree A4Q21 A4Q22 clamps the voltage the ramp capacitor at approximately 8 4 volts The charging time and the clamp voltage form the rise time and pulse top respectively 3 47 During the time 19 switching transistor A4Q7 is off and the current source A4Q16 flows through A4CR4 Concurrently A4Q6 is on diode A4CR3 is reverse biased and the ramp capacitor discharges through current source A4Q11 Diode A4CR9 clamps the voltage rise on the ramp capacitor at 0 7 volts The d
75. nge Rep Rate Adjusts internal repetition rate for both channels Clockwise rotation adjusts Vernier the frequency from the value selected by the rep rate switch to the next higher value on the rep rate selector switch MAN Push button provides a single pulse from both channels when rep rate selector switch is sct to the Ext MAN position Delay mode In PAR position of switch pulse delay is independently adjustable for each PAR SER channel In SER position delay of channel A is added to delay of channel making channel the reference for channel change in channel LINE Push ON OFF ON OFF switch Figure 2 1 Instrument Controls and Connectors 2 2 Model 8010A Section H Figure 2 1 SYNCHR NORM Three position switch selects synchronous asynchronous or normal operating ASYNCHR mode Gate Input Female BNC connector accepts gating signal 2 V applied with 6 in cither the synchr or asynchr position opens the gate permitting output pulses from channel A and channel B to pass Trigger Input Female BNC connector accepts external triggering signals Trigger Output Female BNC connector supplies positive trigger pulses Group 1 Separate for Each Channel 10 Output A Female BNC connector supplies channel A output pulses No output available in the A B mode 11 SEP A B Switch selects separate or combined outputs In A mode combined pulses are available at output B 12 Out
76. p and no frequency di vision takes place 3 28 PULSE SQUARE WAVE SWITCHING 3 29 The SQUARE PULSE switch position determines the operating conditions of switching transistors A1Q22 1023 Figure 3 3 Irrespective of the position selected a wave form from the repetition rate generator either di rectly or from the flip flop always appears on the base of A1Q22 Differentiated spikes from A1Q22 emitter are fed FROM REP RATE GENERATOR Figure 3 3 3 4 Model 1 to A1Q5 for further processing The base of AIQ23 3 ceives the output of the width generator Diodes ALCR30 through AICR33 on the emitters of A1Q22 A1Q23 func tion as switching paths In the PULSE mode AICR30 cathode is grounded forward biasing the diode to provide the signal path from A1Q22 emitter to ground Simulta neously the cathode of AICR32 is 25 volts and 1 is forward biased routing the signal from A1Q23 emitter to A1Q26 and connecting the width generator out put to the integrator In the SQUARE mode the position is reversed The signal from A1Q23 is routed through A1CR33 to ground and the waveform on 1022 emitter is fed via ALCR31 to A1Q26 Transistor A1Q26 couples the waveform which is differentiated A1R82 LT7 to emitter followers A1Q27 A1Q29 and hence to the inte grator The same process occurs for channel B 3 30 Switching transistor A1022 passes the output of the
77. phs 1 1 to 1 10 SECTION GENERAL 1 1 INTRODUCTION 1 2 The Model 8010A is dual channel pulse gene rator with a repetition rate of 1 112 to 10 MHz extendable in double pulse mode to 20 MHz Individual switching of channels A and B permits the application of an external trigger to one channel while the other remains internally triggcred Front panel controls facilitate complete regu lation of the pulse delay width rise and fall times ampli tude and dc offset With the exception of the dc offset all front panel controls are calibrated Complete specifi cations are given in Table 1 1 1 3 the normal delay mode parallel operation both pulses are referenced to the trigger output therefore op tiona delay of either pulse can be obtained while the other remains fixed Under these circumstances the output of A or B can be delayed from 50 ns to 1 s with respect to the trigger output Combining A and B in the series mode makes channel A the reference for channel B 1 4 Channel amplitudes are independently adjustable from 5 volts to 0 02 volts with consideration for the output impedance of 50 ohms a seven step attenuator reduces the output in a 5 2 5 and sequence A maximum of 10 volts output amplitude is readily available from Channel B by operation of a rear panel switch and the output combining switch The pulse parameters are consequently controlled through channel B INFORMATION 1 5 AVAILABLE ACCESSORIES 1 6
78. put B BNC connector supplies channel B output pulses In A B mode combined pulses are available at this connector attenuator B controls the amplitude of the combination with vernier still operational Pulse Delay Selector switch selects a time delay of the output pulse with respect to the trigger pulse Pulse Delay Adjusts the pulse delay Clockwise rotation of the vernier control adjusts the Vernier delay from the limit selected to the next larger value shown on the pulse delay selector switch Single Pulse Selects pulse mode when delay mode switch 2 is set to PAR in SER posi Double Pulse tion only single pulses are supplied In double pulse mode delay controls 13 and 14 determine spacing between the double pulses Pulse Width Switch selects the width of each output pulse Position selected is the smaller value of the width range Pulse Width Adjusts the width of the output pulse Clockwise rotation of the vernier con Vernier trol adjusts the width from the limit selected to the next larger value shown on the pulse width selector switch Time Range Selector switch selects the time range for both the rise and fall times of one channel Position selected is the lower limit of time range Figure 2 1 Instrument Controls and Connectors cont d Section 11 Figure 2 1 19 Square Pulse 20 Rise Vernier 21 Fall Vernicr 22 Amplitude 23 Vernier 24 Pulse Polarity 25 Offset 26 ON OFF REAR PANEL CO
79. r Transistors A9Q6 and 908 are off and no current flows to the at tenuator assembly With 510 in the ON position and VER NIER A9R4 set to such a position that R4 is tapped at the center all the voltages in the circuit are symmetrical about Collector currents from 905 and A9Q7 are equal and opposite so that they cancel and there is no current flow to the attenuator Any unbalanee of A6R4 in either direction causes a corresponding unbalance in A9Q5 A9Q7 collector currents and so a net current flows to the attenu ator and load The circuit is in fact a current source with a high source impedance so that the output pulses are not shunted 3 62 OUTPUT SWITCHING AND ATTENUATOR 3 63 In the SEP mode relay A7K2 is energized and is open Both channel outputs are fed via their re spective VERNIERS to the attenuators In the A B mode is energized A7K2 is de energized combining both outputs to the channel attenuator The 100 ohm resis tors A7RI as well as are disconnected to maintain the 50 ohm output impedance 3 64 attenuator consists of three symmetrical re sistive networks with attenuations of 2 5 and 10 when fed from a 50 ohm source and terminated with a 50 ohm load The networks are used individually or in series to yield at tenuations of 2 5 10 20 50 and 100 3 65 SUPPLY 3 66 Model 8010A operates from either 115 V or 230 ac which is stepped down rectifi
80. rep generator functions as in the internal mode for one cycle 3 15 MANUAL TRIGGERING 3 16 this mode of operation 1251 is set to EXT MAN When the MAN button is pressed A1C3 charges and the voltage at the base of A1Q3 rises causing Schmitt trigger A1Q2 A1Q4 to switch When the button is released A1C3 discharges A1Q3 base voltage falls and the Sclunitt trigger returns to its original state 3 17 GATING 3 18 With OPER MODE switch 515 in the NORM po sition 20 volts is connected to the anode of turning on Hence 1 11 and AICRI2 are always reverse biased the base of A1Q18 reaches a maximum of about 7 volts and gating signals do not interfere with the rep rate generator functions Transistor 1016 is also held off which in turn cuts off A1Q7 permitting A1Q6 to function as a normal amplifier res ed ritt Model 8010A 3 19 ASYNCHRONOUS GATING 3 20 With 515 in the ASYN position AICR13 is re verse biased together with AICR12 AICRII conducts This action permits the repetition rate generator to run and connects 1016 to the collector of A1020 Transis tor 107 thus conducts and effectively turns off amplifier 106 since it draws all available current from A1R95 A negative signal applied to 13 turns off A1Q20 which turn raises the collector voltage of 1016 to 20 volts Thus 107 is switched off A1Q6 functions normally and output pulses
81. s back to zero volts and A2Q14 A2Q 15 switches to its original state 3 39 In the DOUBLE PULSE mode 2018 is off per mitting A2Q17 to switch when a pulse is applied from 201 The positive spike corresponding to the start of the DELAY period turns A2Q17 on producing a negative spike at its collector to switch Schmitt trigger A2011 012 Thus output pulses are produced for both the beginning and end of the delay period and the DELAY may be ad justed to vary the spacing between thc pulses With the DELAY MODE set to the SER position the base potential EXTERNAL INVERTER Q19 INVERTER INTERNAL A1Q6 COLLECTOR Figure 3 5 DOE a C S UR OURCE Q3 Model 80 104 1 of 2018 is held at 20 volts turning off A2Q17 to prez vent the width generator functioning in a double pulse mode 3 40 output of the width circuit is applied to the base of switching transistor A1Q23 and from the differen ciating network AIR82 L7 to the pulse shaping circuit 25 when operated in the PULSE mode 3 41 PULSE SHAPING B 3 42 positive and negative spikes from emitter fol lower A1Q27 A1Q29 switch Schmitt trigger A4Q1 A4Q2 2 on and off to form positive pulses on the collector of A4Q2 Emitter follower A4Q5 passes each pulse to the integrator circuit Zencr diode A4CR2 establishes sufficient collecto E voltage for A4Q6 A4Q7 3 43 function of switch A4Q3 is to add the RC networ
82. tal slow blow schematic selenium section s semiconductor silicon silver slide spring special stainless steel split ring steel tantalum time delay toggle thread titanium tolerance total quantity trimmer traveling wave tube variabie dc working volts watts working inverse voltage wirewound without micro 10 8 optimum value selected at factory average value shown part may be omitted 4 1 Section Table 4 1 gt gt p p gt P P P P P A A A A A P gt P p gt gt gt gt gt gt p gt p gt gt p gt gt P P gt gt Pp gt p p gt p p p gt p p p gt gt p p P ANNAS 08010 66501 08010 66502 08010 66503 08010 66504 08010 66505 08010 66506 08010 66507 08010 66508 08010 66509 08010 63401 08010 66511 08010 61901 08010 61902 08010 61903 08010 61904 08010 61905 08010 63401 08010 61906 08010 61907 08010 66501 0180 0291 0140 0145 0180 0374 0180 0291 0140 0194 0150 0050 0180 0291 0160 2307 0180 0291 0150 0050 0121 0046 0160 2199 0150 0050 0160 2216 0160 2189 0160 3257 0180 2126 0180 2125 0180 1749 0180 0291 0160 2204 0160 2204 0160 2150 0180 0291 0180 0291 0140 0194 0150 0050 0180 0291 0180 0291 0140 0194
83. th 11 in position A Controls of channel will vary the pulse para meters no signal available from output A Slide switch to select channel A for external triggering channel B remains con nected to internal rep rate generator Slide switch to select channel for external triggering channel remains con nected to internal rep rate generator Both channel A and B may be selected for external triggering simultaneously Figure 2 1 Instrument Controls and Connectors cont d 2 4 0A UH Model 8010A have to be doubled No output is available from channel With the OFFSET switches set to ON the base line of the output pulses can be adjusted from 2 to 2 volts 2 19 PREPARATION FOR USE 2 20 Power Source Requirements 9 21 The Model 8010A may be operated from ac source of 115 or 230 volt 10 15 at 48 to 440 Hz Power dissipation is approximately 203 V A max When the instrument is shipped from the factory it is ready for 230 volt operation For 115 volt operation move the rear pancl slide switeh with the instrument power cable discon nected until the number 115 is visible narrow blade screwdriver may be used to operate this switch CAUTION Be sure that the number visible on the voltage slide switeh and the fuse corre spond to the line voltage used before op erating the instrument otherwise the in strument may be damaged 2 22 FUSE REPLACEMENT 2 23 The
84. wcen ranges 10 of setting 2 of full scale lt 0 1 Accuracy Period Jitter Square Wave 1 Hz to 10 MHz output symmetrical to ground rise and fall times variable 50 duty cycle Double Pulse Minimum pulse distance of lt 50 ns al lows maximum rep rate up to 20 MIlz External Triggering Repetition Rate 0 to 10 MHz Can be triggered with sines waves or pulses of either polarity For Square Wave Output frequency divided by a factor of 2 Trigger Input Sine waves 1 V p p Pulses 0 5 V peak at least 20 ns wide maximum 10 V Delay Approximately 30 ns between trigger input and trigger output Input Impedanee 1 0 Manual Push button for single pulse il Separate Triggering of channel Spikes 2 amplitude lt 50 ns width Input impedance 50 2 inputs on rear panel Trigger Output Amplitude lt 2 V across 502 from 509 Width 15 ns 10 ns GATING Synchronous Gating Gating signal turns generator on Asynchronous Gating Gating signal turns the output pulse Trigger output always available Gate Inputs At least 2 V enabling to 10 Operating Temperature Range 09C to 55 C GENERAL Power Requirements 115 V or 230 V 10 15 48 to 440 Hz Weight Net 23 45 Ib 10 7 kg Dimensions 16 3 4 wide 7 1 4 high 18 3 8 deep overall 425 x 184 x 466 mm UA See r nc Model 8010A Section I Paragra

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