Fujitsu MB3891 User's Manual
Contents
1. Value Parameter Symbol Pin Conditions Unit Min Typ Max 8 9 10 11 5 UVLO Sp I 20 42 43 BACKUP UVLO L T B IPA Shutdown supply 60 61 62 current 8 9 10 11 5 5 5 5 UVLO s 2 20 42 43 160 uA 60 61 62 BACKUP UVLO H 8 9 10 11 Standby supply a All circuit s On 20 42 43 400 60 61 62 No load All circuit s VSIM Operating ground 4 5 19 current lanp 32 59 On Max load on all 10 mA regulators 8 9 10 11 20 42 43 OUT1 ON 2 980 3 080 3 180 V UVLO threshold 60 61 62 voltage 8 9 10 11 Vra 20 42 43 OUT1 OFF 2 80 2 880 2 980 V 60 61 62 8 9 10 11 20 42 43 V BACKUP 2 980 3 080 3 180 V General BACKUP UVLO 60 61 62 threshold voltage 8 9 10 11 Vra 20 42 43 OFF 2 580 2 680 2 780 V 60 61 62 0 7 x Vin 16 56 57 OUTI OUT1 V 0 3 x Vit 16 56 57 0 OUTI V 0 7 x 14 15 44 VBAT VBAT V Input voltage m X Vit 14 15 44 0 VBAT V 0 7 x Vin 26 27 vessel VCC VSIM V 0 3 x Vit 26 27 0 V 17 15 kQ Pull up resistor 14 57 200 kQ Pull down resistor Rep 15 53 54 55 200 kQ Standard design value Continued MB38912. n ite pe cR 220 cC PC MU TM gt 5 2 5 1 MM gt 2 gt sssi sls r3 245 EM 1 Penos NG aeni n 77 bM gi VSIMOUT a VSIMOUT vi mm i 05 1 0 5 4 1 T T T T T T T T T T 1 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 t ms t ms Output voltage waveforms Output voltage waveforms VSIMOUT zio VSIMOUT Ta 425 C E Ta 425 C 1 gt VBAT VCC VSIM 86V TE 52 gt VCC SIM 3 6 V ere ere VSIM ON H VSIM ON E o o 3 f SIMPROG WEE TN F 41 5 VSIMOUT No load AEG u NM 5 VSIMOUT No load 14 AC COUPLED AM NM SE 204 Pai su ok loh v 20 AC COUPLED i gt Dh WE xb d gt 0 D D T E E 5 gt gt CN LL LIN DULL E T pestes hend sd ssi es tos die d amp 2 1 en nae rae S 2422 Cee Cre Ceo see teen 1 1 T T T T T T T T T 1 T T T T T T E 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 t us t us Continued 20 MB3891 Output voltage Vsimout mV Output voltage Vsiwour mV Output voltage Vsimio V Output voltage waveforms VSIMOUT Chargepump
3. Vc T i 4 JUov 1 th 777 77 77 Continued MB3891 eee Reference voltage vs power supply voltage Reference voltage vs ambient temperature 1 24 14 m VBAT 3 6 V gt 1 2 123 LL gt 10 gt 1 22 S 0 8 9 06 1 21 04 8 o 6 120 0 2 25 o VFIL 0 1 uF 00 EE 148 0 1 2 3 4 5 6 7 40 20 0 20 40 60 80 100 Power supply voltage Vear V Ambient temperature Ta C Power supply current vs power supply voltage Power supply current vs power supply voltage VSIMOUT Chargepump VSIMOUT Chargepump lt 100000 S 100000 VSIMOUT 510 2 2 VSIMOUT 510 Q gt 10000 gt 10000 2 2 5 1000 1000 t VSIMOUT No load 5 D 100 1 100 VSIMOUT No load gt gt a 25 2 Ta 25 5 10 VBAT 3 6 V 5 10 VBAT 3 6 V VSIM ON VSIM ON 1 SIMPROG 2 1 SIMPROG L 0 1 2 3 4 5 0 1 2 3 4 5 Power supply voltage Vcc vsim V Power supply voltage Vcc vsim V Output voltage vs power supply voltage VSIMOUT Chargepump 5 yeu qoe e SIMPROG 3 4 4 VSIMOUT No load 2 gt 3 r o SIMPROG L VSIMOUT No load 2 gt 5 2 1 25 C 6 VBAT 3 6 V VSIM ON H 0 1 2 3 4
4. EE CONTI d 4 I Y gt S8 24FE eK 0 5 5 2 5 25 29 I T 1 VBAT 36V 3 gt 0 5 OUT load jp 20 232 CONT6 OPEN 15 0 oa YA 19 RELOAD IL Dessen fl 25 09 059 e 1 ws WBATeSBY T OUT1 Dev e menn e SOUTISO 4 00 1 CONT6 OPEN 1 5 T T T I T T F T T T 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 t us t ms Waveform at rapid change of output load LDO1 Measurement diagram Se er a VBAT 3 6 V gt A qu 25 1 lt D Macbeth S Sese VBAT 36V jJ oO CONT1 L 1 1 225 V 1 40 peiecl amp eBe V Le 1 o IC internal 9 E 5 5 0 CONT6 OPEN J D E 1 OUT1 120 mA 054 1 25 nh 2 1 d 8 si x R ee y d 1 uF Wc 5 LR de ucc ecc iE m cL M cux 08 1 OUM 0A 120mA 1 gt Eaaaa Leder z 7771 0 10 20 30 40 50 60 70 80 90 100 t us Continued 15 MB3891 Waveform at rapid change of output load LDO1 5 S omg eerte et ee qe COS wo 05 29 5 2
5. 10 mA SIMPROG L Line regulation Load regulation 3 1 V lt VCC VSIM lt 5 5 V 50 uA gt VSIMOUT gt 10 mA Continued MB3891 Parameter VSIMOUT chargepump Ripple rejection AVCC VSIM AVSIMOUT Ta 25 C VBAT1 to VBAT4 VCC VSIM 3 6 V Conditions 217 Hz Output current GND current at no load 3 1 V VCC VSIM lt 5 5 V VSIMOUT 5 V 3 1 V VCC VSIM lt 5 5 V VSIMOUT 3 V VSIMOUT gt 50 uA Efficiency at max load VSIMOUT 10 mA VSIMOUT 5 V Output ripple voltage f 10 Hz to 1 MHz VSIMOUT 10 uF Shutdown sup ply current VSIM ON L GSM SIM logic level translation up interface Input voltage Output voltage uP IO max 20 HA uP IO max 1 mA Continued 11 MB3891 Continued Parameter SIM interface 5V SIMPROG H Output voltage 25 C VBAT1 to VBAT4 VCC VSIM 3 6 V Conditions RST 20 pA VSIMOUT 0 7 VSIMOUT RST max 200 pA 0 6 Rise time Fall time RESET IN RST 30 pF RESET IN RST 30 pF 400 400 Output voltage CLK max 20 uA 0 7 x VSIMOUT VSIMOUT CLK 200 pA 0 5 Rise time CLK IN CLK 30 pF 27 Fall time CLK IN CLK 30 pF 27 Output voltage SIM IO max 20 uA SIM IO m
6. FUJITSU SEMICONDUCTOR DATA SHEET DS04 27801 1E ASSP For Power Management Applications Mobile Phones Power Management IC for GSM Mobile Phone MB3891 DESCRIPTION 891 is intended to be used in future GSM phones Dual Band phones and Dual Mode phones It contains all the necessary functions to support all Digital Analog and RF blocks in these phones A Charge pump including a Logic Level Translation circuit is built in to support SIM card SmartCard of both and 5 Volt technology The circuit contains a charger for a rechargeable Lithium coin cell of a Real Time Clock A complex control circuit is built in to generate main reset and to turn on and off the different LDO s FEATURES Supply voltage range 3Vto5 5 V Low power consumption current during standby 400 uA MAX 6 channel low saturation voltage type series regulator 2 1 V 2 channels 2 8 V 3 channels 2 5 V 2 8 V switch Error prevention function during Low voltage Power on reset function 3 V 5 V SW for SIM Card SIM interface function Backflow prevention function for Battery Backup Temperature prevention function PACKAGE 64 pin plastic LQFP 64 03 MB3891 ss r PIN ASSIGNMENT TOP VIEW 2525 z 207 TE mamo o fbh is 25225055 7929 3999898598538 N C 49 32 GND VSIM 50 31 VCAP SW2 OUTPUT 51 30 VCAP SW2 INPUT 52 29
7. No load 8 150 SIMPROG H OUT1 No load gt 150 OUT2 No load gt OUT2 No load 100 OUT3 No load Q 100 OUT3 No load Q OUT4 No load OUT4 No load o 50 OUTS No load 50 OUTS No load x V BACKUP No load V BACKUP No load 0 VSIMOUT No load VSIMOUT load 5 4 a 0 1 2 3 5 0 1 2 3 4 5 Power supply voltage V Power supply voltage V Power supply current GND current vs power supply voltage Output voltage vs power supply voltage LDO1 3 0 lt 450 Ta 25 sC IBAT 450 A CONT OPEN CONT2 H lt 5 lt 350 LONT ud 350 5 NT4 OPEN 300 CONT5 OPEN HGND 30 gt 20 L DONIS LL 2507 9 3 P i e cu s Q OUT3 280 99905 Ta 25 C 5 100 1002 80 OUT1 1 HF o 56 Q E 1 p 50 V BACKUP 84 50 6 CON OPEN 2 4 VSIMOUT 510 9 0 0 6 H e 0 1 2 3 4 5 0 1 2 3 4 5 6 7 Power supply voltage Vear V Power supply voltage V Output voltage vs power supply voltage LDO1 Output voltage vs load current LDO1 _ 22 gt 55 OUTI 1 pF gt E CONT1 L E 8 CONT6 OPEN o gt 20 gt 2 0 9 15 8 10 NEU 5 25 05 8 18 VBAT 3 6 V o 6 CON
8. GND current at max load lenp 19 OUT2 50 mA 1 mA f 10 Hz to 1 MHz Output noise volt RMS Vsov 6 7 OUT2 1 uF 350 uV SW1 INPUT 2 8 V Gate Source 2 8 V General purpose Input Output resistance Rswe 51 52 170 2 Gate Source 2 8 V switches SW3 INPUT 2 8 V Gate Source 2 8 V BO s Continued Parameter Symbol Pin No MB3891 Ta 25 C VBAT1 to VBAT4 VCC VSIM 3 6 V Conditions Output voltage 50 uA gt OUT3 gt 100 mA Line regulation 3 1 V lt VBAT3 lt 5 5 V Load regulation 50 uA gt OUT3 gt 100 mA Ripple rejection AVBATS AOUTS Dropout voltage f 217 Hz OUT3 100 mA GND current at low load OUT3 gt 1 mA GND current at max load Output noise volt RMS OUT3 100 mA 10 Hz to 1 MHz OUT3 1 uF Output voltage 50 uA gt OUT4 gt 100 mA CONTA L 50 uA gt OUT4 gt 100 mA CONTA H Line regulation 3 1 V lt VBAT4 lt 5 5 V Load regulation 50 uA gt OUTA gt 100 mA Ripple rejection AVBAT4 OUT4 AOUT4 Dropout voltage f 217 Hz OUT4 100 mA GND current at low load OUT4 gt 1 mA GND current at max load OUT4 100 mA Output noise volt RMS f 10 Hz to 1 MHz OUT4 1 Output voltage 50 uA gt OUT5 gt 50 mA Line reg
9. M A 25 C VBAT1 to VBAT4 VCC VSIM 3 6 V Pin Value Parameter Symbol N Conditions Unit 0 Output voltage Vo 12 13 50 uA gt OUT1 gt 120mA 2 000 2 100 2 200 V Line regulation Line 12 13 3 1 V lt VBAT1 lt 5 5 V 10 mV Load reguration Load 12 13 50 uA gt OUT1 120mA 30 mV Ripple rejection LDO1 AVBAT1 AOUT1 R R 12 13 f 2 217 Hz 45 dB OUT1 Dropout voltage Voo 12 13 OUT1 120 mA 500 mV GND current at low load 19 gt 1 30 HA GND current at max load lenp 19 OUT1 2 120 mA 2 mA 10 Hz to 1 MHz Output noise volt RMS 12 13 OUT1 1 uF 500 uV 17 S OUT V XPOWER Output voltage GOOD V 17 m 0 Oix V RESET i OUT1 Hold time Txec 17 DELAYCAP 0 033 uF 10 25 40 ms Output voltage Vo 6 7 50 uA gt OUT2 gt 50 mA 2 700 2 800 2 900 V Line regulation Line 6 7 13 1 V lt VBAT1 lt 5 5 V 10 mV Load regulation Load 6 7 50pA gt 2 gt 50 30 mV Ripple rejection S LDO2 AVBAT1 AOUT2 R R 6 7 f 217 Hz 45 dB OUT2 Dropout voltage 6 7 OUT2 50 mA 250 GND current at low load 19 2 gt 1 30 HA
10. VSIMOUT SW1 ON 53 28 0SC SW2 ON 54 27 SIMPROG SW3 ON 55 26 VSIM ON 56 25 VCC VSIM CONT5 57 24 REF OUT OUT5 58 23 VFIL GND5 59 22 VREF VBAT3 60 21 VBATS 61 20 VBAT2 VBATS 62 19 GND1 N C 63 18 DELAYCAP 64 17 XPOWERGOOD E 282 2 c 8 8 55855 6 64 03 MB3891 PIN DESCRIPTION 3 4 Descriptions Non connection LDOS output pin 5 ground pin 6 7 LDO 2 output pin 8 9 10 11 Battery voltage input pin for LDO1 and LDO2 12 13 LDO 1 output pin 14 CONT6 Power on input from keypad Active low Pulled up to VBAT2 6 input from digital system uP Active high CONT2 External accessory supply voltage Enable Active high XPOWERGOOD Generates the main reset Active low when OUT1 is out of regulation DELAYCAP Timing capacitor for XPOWERGOOD delay GND1 LDO1 LDO2 V BACKUP Reference and System ground pin VBAT2 V BACKUP Battery voltage input pin for both UVLO s Reference and V BACKUP LDO Supply voltage for Charger for rechargeable Lithium coin cell VREF Supply voltage for Reference VFIL Reference voltage Filter REF OUT Reference output voltage Present when BACKUP UVLO is high VCC VSIM Input voltage for charge pump Supplied by 1 VSIM ON SIMP
11. are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection a
12. us Output voltage vs input voltage SIM Interface 2 5 2 0 1 5 Ta 25 C 140 VBAT VCC VSIM 3 6 V VSIM ON 0 5 SIMPROG CONT1 L CONT6 OPEN 0 0 1 a Input voltage Vsimio V Continued 21 MB3891 ua x ua www Continued Output voltage vs ambient temperature Output voltage vs ambient temperature SIM Interface SIM Interface 3 10 r r r r 5 00 m VBAT VCC VSIM 3 6 V P VBAT VCC VSIM 3 6 V 305 VSIM ON 495 VSIM ON H 1 5 SIMPROG L E SIMPROG H 2 300 490 2 2 gt gt 2 95 4 85 9 9 5 5 5 290 5 4 80 gt gt a 2 85 475 O 2 80 O 4 70 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100 Ambient temperature Ta C Ambient temperature Ta C Power dissipation vs ambient temperature 1000 t 800 a 5 600 D 400 LY gt 200 0 40 20 0 20 40 60 80 100 Ambient temperature C 22 MB3891 FUNCTIONAL DESCRIPTION 1 MAIN UVLO BACKUP UVLO Transient power on surge states or sudden drops in supply voltage VBAT2 can cause an IC to operate abnor mally leading to destruction or damage to system elements To prevent this type of f
13. 40 4 20 4 0 20 25 S VBAT VCC VSIM 3 6 V 40 1 VSIM ON H SIMPROG L VSIMOUT 510 Q AC COUPLED T T T T T T T T T 1 0 2 4 6 8 10 12 14 16 18 20 t us Output voltage waveforms VSIMOUT Chargepump AG esta sss r see 20 Ep 4 0 VBAT VCC VSIM 3 6 Vi liu CSS DIE VSIM ON SIMPROG A GA VSIMOUT 510 Q AC COUPLED T I T I T T T T 0 2 4 6 8 10 12 14 16 t us 1 18 20 Output voltage vs input voltage SIM Inter SIMPROG H 4 3 2 Ta 425 C VBAT VCC VSIM 3 6 V 1 VSIM ON H CONTI L i 6 OPEN 0 0 0 5 1 0 1 5 2 0 2 5 Input voltage Vurio V Output voltage Vsimout mV Output voltage mV Output voltage Vurio V 60 4 40 20 0 4 eee Ta 25 C VBAT VCC VSIM 3 6 V 4 VSIM ON SIMPROG H 1 VSIMOUT 55 1 kQ 1 AC COUPLED 1 Output voltage waveforms VSIMOUT Chargepump k Ta 25 C 4224274 e BAT VCC VSIM 36V emos sss S OSVSIM ON SSIMPROG L 5 VSIMOUT 5 1 AC COUPLED ae ee oe 0 2 4 6 8 10 12 14 16 18 20 t us Output voltage waveforms VSIMOUT Chargepump T T TT 0 2 4 6 8 10 12 14 16 18 20 t
14. 5 6 7 Power supply voltage Vcc vsim V Continued 17 18 MB3891 Output voltage vs load current VSIMOUT Chargepump Output voltage vs load current VSIMOUT Chargepump _ 3 00 5 00 gt I 24 VSIM ON 495 FVSIM ON H 2 2 98 VCC VISM 5 5 V SIMPROG 471 5 H os g 490 SIMPROG H voc vism 5 5 V gt 2 96 ate gt 4 85 295 _VCC VISM 3 1 V 480 294 VCC VISM 3 6 V J S 475 gt 2 93 gt 4 70 2 92 5 amp 465 29 4 2 90 460 0 5 10 15 20 0 5 10 15 20 Load current mA Load current mA Ripple rejection vs frequency Ripple rejection vs frequency VSIMOUT Chargepump VSIMOUT Chargepump 0
15. Em Hus E Ta 25 C m VBAT VCC VSIM 3 6 V 20 2 20 VSIM ON oc c SIMPROG H oc VCAP 0 1 uF 40 40 VSIMOUT 10 uF 9 Ta 25 C 60 VBAT VCC VSIM 3 6 V 60 VSIM ON 9 SIMPROG H o 80 VCAP VCAP 0 1 uF 80 VSIMOUT 10 uF T ioo VSIMOUT 510 Q i86 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency f Hz Frequency f Hz Ripple rejection vs frequency Ripple rejection vs frequency VSIMOUT Chargepump VSIMOUT Chargepump 0 9 25 m m VBAT VCC VSIM 3 6 V _20 VSIM ON cc oc SIMPROG L VCAP VCAP 0 1 uF 40 c 30 VSIMOUT 10 uF 2 25 C 60 VBAT VCC VSIM 3 6 V 40 VSIM ON SIMPROG L 80 VCAP VCAP 0 1 uF 2 7580 2 VSIMOUT 10 uF VSIMOUT 510 0 100 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency f Hz Frequency f Hz Continued MB3891 Efficiency vs power supply voltage Efficiency vs power supply voltage VSIMOUT Chargepump VSIMOUT Chargepump 25 100 25
16. VSIMOUT 510 Q T I T I w T T T FI 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0 0 0 5 1 0 1 5 20 2 5 3 0 3 5 4 0 4 5 5 0 t ms t ms Continued 19 MB3891 Output voltage rising waveforms VSIMOUT Output voltage falling waveforms VSIMOUT Chargepump E E SIMPROG T A Input voltage Vsiwenoc V Input voltage V T A gt gt 5 5 E E gt VSIMOUT 2 F aa 28 TREAT SERE TEE a det 42 Pantesan a pat ca b beats es 1 128 F gt IVBAT VCCNSM 36V L l1 1 VBAT VCC SIM 3 6 a VSIMOUT 510 Q 4 05 VSIMOUT 510 Q JL o VSIM ON H 109 VSIM ON T T T T I m T T T 5 T T T T T T I 0 0 0 5 1 0 1 5 2 0 2 5 3 0 35 4 0 4 5 5 0 0 0 0 5 1 0 1 5 2 0 25 3 0 3 5 4 0 4 5 5 0 t ms t ms gt Output voltage falling waveforms Output voltage falling waveforms basna Chargepump VSIMOUT UM z I 51 21 774219576 510 4219557 VCC VSIM 3 6 v VCC VSIM 36 V E SIMPROG H ao 4 SIMPROG 1 l ___ VSIMOUT 510 2 59 VSIMOUT 510 0 5 VSIM ON 5 9 VSIM ON 8
17. voltage is generated from the VSIMOUT terminal pin 29 as a power supply for the SIM card 14 SIM Interface 3 V SIMPROG L When an L level signal is input to the SIMPROG terminal pin 27 3 0 V typ voltage is generated from the VSIMOUT terminal pin 29 as a power supply for the SIM card SETTING THE XPOWERGOOD TIME When the OUT1 terminal pin 12 13 voltage exceeds 2 0 V typ the capacitor connected to the DELAYCAP terminal pin 18 starts charging the XPOWERGOOD terminal pin 17 voltage rises The XPOW ERGOOD terminal voltage rising time XPOWERGOOD time can be set by a capacitor connected to the DELAYCAP terminal XPOWERGOOD time s 0 8 x MB3891 OPERATION TIMING CHART Input VBAT1 to VBAT4 VCC VSIM CONTI CONT6 CONT5 C CONT2 CONT3 SW1 ON SW2 ON SW3 ON C VSIM ON SIMPROG Output REF OUT OUT6 C OUT1 XPOWERGOOD OUTS OUT L L L OUT3 OUT4 SW1 OUTPUT SW2 OUTPUT SW3 OUTPUT VSIMOUT 5 V Sy Hmm eram mm bm nm a ios uo n Ree eee eee eel VSIMOUT d 2 G9 9 amp 10 f 12 1 14 15 6 17 1 Battery controlled b OUT1 hold 2 BACKUP UVLO ON 6 to 12 uP controlled 3 phone turned on 14 Main UVLO off 4 XPOWERGOOD on 16 BACKUP UVLO off 25 MB3891 snT F APPLICATION EX
18. 3 6 20 FOUTI 1 uF 1 L 40 OPEN 60 80 100 10 100 1k 10k 100k 1M Frequency f Hz Output voltage vs ambient temperature LDO1 2 13 r VBAT 3 6 V CONT1 OPEN l CONT6 H 2 11 2 10 2 09 2 08 40 20 0 20 40 60 80 100 Ambient temperature C MB3891 gt T Output voltage falling waveforms LDO1 Output voltage falling waveforms LDO1 2 4 m 2 Ta 25 C 1 a Ta 25 C D gt Bed i i OUTA load 1 SD i e 04 x j 5 10 2 1 1 1 CONT6 OPEN J gt 2 Sa s ass CONT6 OPENI lt gt Ne eee E umo Qi ss icol Res TEN T 0 2 fsa s VBAT gg 3 2 oH 2 gt 2 gt rig 2 Fl 8 a oo Lo 5 Lo 5 5 BENS Xe eee cms eee Ge ee es ws 2 2 6 6 T T T T T T T T T T T T T T T T T T 1 0 50 100 150 200 250 300 350 400 450 500 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 16 18 2 0 t ms t gt Output voltage rising waveforms LDO1 Output voltage falling waveforms LDO1 2 5 40 PO de vie 45 220 20 Ao me ud
19. 5 5 di VBAT 36V 115 CONT1 L 4102 6 j 6 1 120 0 j 2 171 7171773 0 0 0 5 1 0 1 5 2 0 25 3 0 3 5 4 0 45 5 0 t ms Waveform at rapid change of output load LDO2 S 30 Boo zem SEM 25 Z gt 20 1 VBAT 3 6 V 2 1 L 1 5 1 2 Ubi d aul CONT6 OPEN gt 1 0 h 29 oe Be s 5 t amp 0 5 1 8 00 410 0 2 0 50 mA 1 RENE z T T T T T T T 4 0 10 20 30 40 50 60 70 80 90 100 t us Waveform at rapid change of output load LDO2 S 304 25 gt 20 gt 15 4 gt 1 0 4 HH 29 5 25 u 05 3 6 15 CONTI L dE 2 H 05 CONTEC OPEN 00 2 50 0 z T T T T T T T T 1 0 10 20 30 40 50 60 70 80 90 100 t ms Measurement diagram VBAT 3 6 V VREF 1 225 V 1 internal QUT 120 mA zh 1 uF Vc 1 1 4V Measurement diagram VBAT 3 6 V 8 VREF 1 225 V IC internal E 1 uF A 4V JL ov Measurement diagram VBAT 3 6 V VREF 1 225 V IC internal QUT2 50 mA 1
20. 90 VSIM ON 90 VSIM ON p 80 SIMPROG L 80 SIMPROG gt 5 9 70 9 70 60 E 60 2 50 50 2 40 40 gt 30 30 20 10 10 0 0 3 0 3 5 4 0 4 5 5 0 5 5 3 0 3 5 4 0 4 5 5 0 5 5 Power supply voltage Vcc vsim V Power supply voltage Vcc vsim V Efficiency vs load current Efficiency vs load current VSIMOUT Chargepump VSIMOUT Chargepump 100 r 100 90 25 C 90 VBAT VCC VSIM 3 6 V 5 80 VSIM ON H 80 VCC VSIM 3 1 70 SIMPROG L rne 100 VCC VSIM 5 5 V m BD Er gr rece m VSIM 5 5 VCC VSIM 3 6 V 30 30 25 5 VCC VSIM 3 1 V VBAT VCC VSIM 3 6 V VSIM ON H x p SIMPROG H 0 5 10 15 20 0 5 10 15 20 Load current mA Load current mA Output voltage rising waveforms Output voltage rising waveforms VSIMOUT Chargepump gt VSIMOUT Chargepump 2 510 9 10 gt 1 gt 5 ms o 52 8 Em gt 0 2 1 22 2524 221 2220 ce Re gt X QI E r LLL EAE T gt gt 25 VSIMOUT 5 Q 1 2 4 37 Peter ees 4 A 3 gt Oo D s IL x 25 a ccu T RR Ta 25 C iL 19 VBAT VCC VSIM 3 6V 4 VBAT VCC VSIM 3 6 v4 SIMPROG JLo 8 2222 G SIMPROG 17 02 VSIMOUT 510 Q 1
21. AMPLE KEYPAD VBAT2 VBAT1 PT uP T 0 14 CONT1 15 CONT6 OUT d8 1 1 uF 16 CONT2 R1 XPOWERGOOD 17 200 63 5 1 DELAYCAP 18 64 SW2 ON 9 i 777 65 SW3 ON T2 6 CONT3 2 1 uF 200 67 5 SW2 INPUT 62 HP CONT4 R3 SW2 OUTPUT 6 200 VREF SW3 INPUT 48 Sr 3 VEIL SW3 OUTPUT 47 4 0 1 uF 4 REF OUT 2 C13 6 VSIM ON VBATS 6 1 uF R4 6 ap 200 SIMPROG OUT3 gt 200 4 ee 83 RESET IN T t 84 CLK IN GND3 5 H TIT E SW1 INPUT 46 SW1 OUTPUT 45 1 VCC VSIM OUTS 68 8 OSC C5 1 uF GND5 69 9 VSIMOUT TE col 4 4 cur 80 VBAT4 5 L c14 0 1 T 6 VCAP 777 px ed 40 OUT4 gt L C6 I 66 RST 41 T L SM i 87 CLK GND4 69 88 SIM IO V BACKUP 01 i 32 GND VSIM In T 1 1 u N C Pin 1 2 49 50 63 64 26 MB3891 USAGE PRECAUTIONS Printed circuit board ground lines should be set up with consideration for common impedance Take appropriate static electricity measures Containers for semiconductor materials should have anti static protection or be made of conductive material After mounting printed circuit boards should be stored and shipped in conductive bags or Containers Work platforms tools
22. ROG VSIM supply Enable Active high VSIM programming Low 3 V SIM High 5 V SIM OSC Oscillator output pin VSIMOUT Supply voltage for 3 or 5 V SIM Card SmartCard VCAP Positive side of boost capacitor VCAP Negative side of boost capacitor GND VSIM RESET IN 3 or 5 V SIM Card SmartCard ground pin Non level shifted SIM reset uP side CLK IN Non level shifted clock uP side Non level shifted bi directional data input output uP side RST Level shifted SIM reset SmartCard side CLK Level shifted SIM clock SmartCard side SIM IO Level shifted bi directional SIM data input output SmartCard side GND4 LDO4 ground pin OUT4 LDO4 output pin Continued MB3891 eee Continued VBAT4 Descriptions Supply voltage for LDO4 CONT4 output voltage selection L 2 8 2 5 SW1 OUTPUT Output of general purpose switch number 1 Drain SW1 INPUT SW3 OUTPUT Input of general purpose switch number 1 Source Output of general purpose switch number 3 Drain SW3 INPUT Input of general purpose switch number 3 Source N C Non connection SW2 OUTPUT Output of general purpose switch number 2 Drain SW2 INPUT Input of general purpose switch number 2 Source SW1 ON General purpose switch number 1 Enable Active
23. TI 1 di is 6 OPEN 0 1 2 3 4 5 0 100 200 300 400 500 600 700 800 Power supply voltage V Load current Continued 13 14 MB3891 a ua awu Ripple rejection R R dBm Dropout voltage V Power supply voltage Vaar Ripple rejection vs frequency LDO1 20 40 25 60 VBAT 3 6 V OUT1 1 uF 80 OUT1 18 Q 1 L 6 OPEN 100 10 100 1k 10k 100k 1M Frequency f Hz Dropout voltage vs load current LDO1 06 2 E 5 CONT OPEN 485 J CONT6 H ar ur 0 4 0 3 0 2 0 1 0 0 0 50 100 150 200 Load current ILoap mA Output voltage rising waveforms LDO1 10 0 zd 2 0 5 L 1 5 TIL II 10 hind L 0 5 s 1 T 771777 6 t ms T T T T T I T 1 0 0 0 5 1 0 1 5 20 25 3 0 35 40 45 5 0 Ripple rejection R R dBm Output voltage Vout V Output voltage Vout V Ripple rejection vs frequency LDO1 25 C VBAT
24. and instruments should be properly grounded Working personal should be grounded with resistance of 250 kO to 1 MO between body and ground Do not apply negative voltages The use of negative voltages below 0 3V may create parasitic transistors on LSI lines Which can cause abnormal operation ORDERING INFORMATION 64 pin Plastic LQFP 27 MB3891 eee PACKAGE DIMENSION 64 pin plastic LQFP FPT 64P M03 Note Pins width and pins thickness include plating thickness 12 00 0 20 472 008 SQ 10 00 0 10 394 004 SQ ed amp J0 08 003 Details of A part 1 500 059 0 Mounting height C OE j 0 8 LEAD No 1 f Im 0 50 0 08 0 18 003 0 145 0 055 i BEN 020 003 007 252 008 00 006 002 0 10 0 10 007 0 50 0 20 004 004 020 008 Stand off 0 45 0 75 0 25 010 018 030 L 4 1998 FUJITSU LIMITED F64009S 30 6 Dimensions in mm inches MB3891 rr wv FUJITSU LIMITED All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and
25. ault the undervoltage lockout circuits UVLO Backup UVLO will shut off the output from OUT1 to V BACKUP if the supply voltage falls below the UVLO circuit threshold voltage 3 0 V 2 8 V typ System operation is restored as soon as the supply voltage rises above the UVLO circuits threshold voltage 3 2 V typ 2 LDO1 The LDO 1 circuits uses the reference voltage supply and generates an output voltage 2 1 V typ at the OUT1 terminal pin 12 13 Power can be drawn from the OUT1 terminal for external use up to a maximum load current of 120 mA 3 XPOWERGOOD RESET When the OUT1 terminal pin 12 13 voltage exceeds 2 0 V typ after a delay interval set by a capacitor Cob amp LavcaP connected to the DELAYCAP terminal pin 18 the XPOWERGOOD terminal 17 goes to level and resets the microcomputer At the same time the LDO2 LDO3 and LDO4 output is controlled ON OFF 4 LDO2 LDO2 circuit uses the reference voltage supply and generates an output voltage 2 8 V typ at the OUT2 terminal pin 6 7 when the XPOWERGOOD terminal pin 17 voltage is at level and an level signal is input at the 2 terminal pin 16 Power can be drawn from the OUT2 terminal for external use up to a maximum load current of 50 mA 5 General Purpose switches Any of the OUT terminals can be connected to any SW INPUT terminal so that when the corresponding SW ON terminal is at H level the OUT termina
26. ax 1 mA VSIMOUT 0 4 Input voltage 0 7 x VSIMOUT VSIMOUT 0 8 Rise time SIM IO 30 pF 1 Fall time SIM IO 30 pF 1 SIM interface 3V SIMPROG L Output voltage RST max 20 uA RST max 200 pA 0 8 x VSIMOUT VSIMOUT 0 2 x VSIMOUT Rise time RESET IN RST 30 pF 400 Fall time RESET IN RST 30 pF 400 Output voltage CLK max 20 pA 0 7 x VSIMOUT VSIMOUT CLK 200 pA 0 2 x VSIMOUT Rise time CLK IN 30 pF 50 Fall time CLK IN CLK 30 pF 50 Output voltage SIM IO max 20 0 7 x VSIMOUT VSIMOUT SIM IO max 1 mA 0 0 4 Input voltage 0 7 x VSIMOUT VSIMOUT 0 2 x VSIMOUT Rise time SIM IO 30 pF 1 Fall time SIM IO 30 pF 1 MB3891 TYPICAL CHARACTERISTICS Power supply current vs power supply voltage Power supply current vs power supply voltage 400 350 S a tst Mam 350 CONT CONT2 m lt 300 CONT3 H lt CONT4 OPEN 250 CONT4 OPEN 250 5 OPEN 5 CONT6 OPEN 200 CONT6 H 200 LVSIM ON H VSIM ON H o SIMPROG H OUT1
27. high General purpose switch number 2 Enable Active high General purpose switch number 3 Enable Active high OUT3 OUT4 supply voltage Enable Active high OUTS5 supply voltage Enable Active high Output terminal of LDO5 60 61 62 LDO5 ground pin Supply voltage for LDO and 005 63 64 Non connection BLOCK DIAGRAM MB3891 VBAT2 CONT1 14 Over Temp Protection 6 15 2 16 46 SW1 INPUT SW1 ON 53 SW2 ON 64 SW3 ON CONT3 66 45 SW1 OUTPUT 92 SW2 INPUT 91 SW2 OUTPUT 48 SW3 INPUT 47 SW3 OUTPUT CONTS 67 CONTA 44 VREF 22 VREF AMP VFIL Q3 Wv VREF REF OUT 24 RESET IN 33 GSM SIM Logic Level Translation VSIMOUT 39 GND4 68 OUT5 99 GND5 1 V BACKUP Charge pump G0 VCAP 31 GND VSIM VSIMOUT N C Pin 1 2 49 50 63 64 MB3891 ABSOLUTE MAXIMUM RATINGS Parameter Conditions VBAT VCC VSIM Power supply voltage OUT OUT2 pin LDO regulator OUTS pin OUTA pin OUT5 pin VSIMOUT charge
28. l voltage can be drawn from the associated SW OUTPUT terminal 6 LDO3 The LDOS circuits uses the reference voltage supply and generates an output voltage 2 8 V typ at the OUT3 terminal 3 4 when the XPOWERGOOD terminal pin 17 voltage is at level and an level signal is input at the CONTS terminal pin 56 Power can be drawn from the OUTS terminal for external use up to a maximum load current of 100 mA 7 LDO4 LDO4 circuits uses the reference voltage supply and generates an output voltage 2 8 V typ at the OUT4 terminal pin 40 41 when the XPOWERGOOD terminal pin 17 voltage is at level and an level signal is input at the CONTS terminal pin 56 and an L level signal is input at the CONT4 terminal pin 44 When an H level signal is input at the CONTA terminal the output voltage at the OUTA terminal is 2 5 V typ Power can be drawn from the OUTA terminal for external use up to a maximum load current of 100 mA MB3891 8 LDO5 LDOS circuits uses the reference voltage supply and generates an output voltage 2 8 V typ at the OUT5 terminal pin 57 when the OUT1 terminal pin 12 13 is in output state and an H level signal is input at the CONT5 terminal pin 57 Power can be drawn from the OUT5 terminal for external use up to a maximum load current of 50 mA 9 LDO6 The LDO6 circuit uses the reference voltage supply and generates an outp
29. nd prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan F0007 FUJITSU LIMITED Printed in Japan
30. pump VSIMOUT pin Power dissipation Ta lt 25 C Storage temperature The packages are mounted on the dual sided epoxy board 10 cm x 10 WARNING Semiconductor devices be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings RECOMMENDED OPERATING CONDITIONS Parameter Conditions VBAT VCC VSIM LDO capacitor guarantee value Co OUT1 to OUT5 V BACKUP 4 capacitor guarantee Co REF OUT pin Power supply voltage 2277 capacitor guarantee Co VSIMOUT pin Operating ambient temperature Ta WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand MB3891 ELECTRICAL CHARACTERISTICS Ta 25 C 1 to VBAT4 VCC VSIM 3 6 V
31. ulation Load regulation 3 1 V lt VBAT3 lt 5 5 V 50 uA gt OUT5 gt 50 mA Ripple rejection AVBAT3 AOUT5 f 217 Hz Dropout voltage OUT5 50 mA GND current at low load 5 gt 500 uA GND current at max load OUT5 50 mA Output noise volt RMS f 10 Hz to 1 MHz OUT5 1 uF Continued MB3891 M A Ta 25 C VBAT1 to VBAT4 VCC VSIM 3 6 V Parameter LDO6 V BACKUP Output voltage Conditions 10 pA gt V BACKUP gt 250 pA Line regulation 3 1 V VBAT2 lt 5 5 V Load regulation 10 uA gt V BACKUP gt 250 uA Ripple rejection 2 GND current at low load f 217 Hz V BACKUP gt 10 pA GND current at max load V BACKUP 250 pA Output noise volt RMS f 10 Hz to 1 MHz V BACKUP 1 uF Reverse current VBAT2 0 V V BACKUP 3 0 V REF OUT Output voltage 0 uA gt REF OUT gt 50 uA Line regulation Load regulation 3 1 V lt VBAT2 lt 5 5 V 0 uA gt REF OUT gt 50 uA Ripple rejection 2 f 217 Hz Output noise volt RMS f 10 Hz to 1 MHz REF OUT 27 nF VSIMOUT chargepump 10 Output voltage 50 uA gt VSIMOUT gt 10 mA SIMPROG H 50 uA gt VSIMOUT gt
32. ut voltage 2 1 V typ at the V BACKUP terminal pin 21 Power can be drawn for external use from the V BACKUP terminal up to a maximum load current of 250 10 REF OUT This circuit uses the reference voltage generated by the reference voltage block 1 225 V typ to produce a temperature compensated reference voltage 1 225 V typ at the REF OUT terminal pin 24 by means of a voltage follower The reference voltage can also be drawn from the REF OUT terminal for external use up to a load current of 50 uA 11 VSIMOUT Chargepump The VSIMOUT charge pump uses the voltage from the battery and generates 5 0 V typ voltage at the VSIMOUT terminal pin 29 when an H level signal is input at the SIMPROG terminal pin 27 or 3 0 V typ voltage when an L level signal input at the SIMPROG terminal This voltage can also be drawn from the VSIMOUT terminal for external use up to a load current of 10 mA 12 GSM SIM Logic Translation uP Interface When a signal is input from the microprocessor to the RESET IN terminal pin 33 and CLK IN terminal pin 34 a level shifted voltage is output from the RST terminal pin 36 and CLK terminal pin 37 to the SIM card The uP IO terminal 35 and SIM IO terminal pin 38 are input output pins and carry signals between the microprocessor and SIM card 13 SIM Interface 5 V SIMPROG When an level signal is input to the SIMPROG terminal pin 27 5 0 V typ
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