Fujitsu 16LX User's Manual
Contents
1. San ttt ttn 888 San Jaa Sex Son 499 ARR ssa SAN SSR 200 S388 SER SEN 999 mam AAA mo mo mo mo mo mo mo mo mo mo mo mo mo ale alg a Fo el onl elgls zz elele elel gle 2 slol Z E E Z Sis sii B 25 2 gt 4 Z gt 2 ous zzz zzz zz ze EB 55 485 seb 202203206 E 4 5 DIN 41612 sam tee ttn 9o gaa SSS San SAN Sex Bee oon Nan NAN SAN dii 900 Sasa GEN ASS mam AAA mo mo mo mo mo mo mo mo mo mo2. 16 What is in This Guide What you ll find inside this guide and few words about its organization PU Board in its interface to the Devkit16 Mainboard is designed in such a way that it is possible to use different CPU boards with various members of the 16LX family with the same Mainboard This guide describes how to use the CPU board as a standalone board CPU board features and technical specification chapter provides necessary technical and operational information FLASH It chapter explains how to store final application in DevKit16 CPU or external FLASH CPU Board Description chapter provides explanation how to control the CPU board configuration and detailed description of CPU board including all DIP switches jumpers and connectors Power supply requirements chapter Revisions and errors list Appendix includes schematics of the CPU board and other technical references WHAT IS NOT INCLUDED IN THIS GUIDE This guide is not detailed manual for the CPU parts and software tools Please find more in the following resources Softune Workbench and tools FUJITSU Micros CD ROM Ver 3 0 or higher Processor Expert and tools DEVKIT16 Software CD ROM Parts and other HW components datasheets of their producers WHERE FIND NEWS OPTIONS OTHER BEANS OTHER CPU BOARDS LATEST FAQ AND SUPPORT Please vi
3. mo mo mo mo mo mo mo mo mo mo e slza sl ee e al zB ze iles is ze I 56 SS SZ zz zr see zlo ells Ez le oslo EE ERE sz cbe sss ZEE elele Fl Elole e alaja 4545 aaa 42 2 az 2 z amp 210 lols OV 222 zz zzz B E Sis sms E g 2 455 lt lt 458 mE 865 252 224 224 ce Re 2 aag aaa 22 aee aae aee 22 ze xS Sis SOUND J15 19 XOA SOHO JUMPER2 JUMPER2 E E BOO ADOO ca SDA 16 gu ADO s POWADOL PH SCKO 0 60 JUMPER2 TO 2 wawam POVADO PA2 SINO HRQ XIA XIAJ 1 p ADOS 88 ps BOAN INI ADOI 9 D 23 SCKT SK 129254nm POA ADO4 7 ADOS 90 24 som B2 45V POS ADOS PAS SOTI JUMPER2 3 ADO 91 25 Om ji nuin ADOT TAD W pa y p BOTIADOT 47 5 D6 9 J18 A P K A pi SIN2 IG JUMPER2 PIO ADOR PSO SIN2 Yd JUMPER2 154007 SMD 1N4007 SMD pete PSUINTA WES XI C 5 Acus neu s 2 di PI2 ADIO PS2 INTS 1 AE IN OUT UT Es PISADII P53 INT6 N4007 SMD 1N4007 SMD PIA ADI2 aN o Cis PIS ADIS PSS ADTG GNP 2 100N 10N BADIS 57
4. Figure 1 CPU board layout and default jumper settings 11 DEFAULT HW SETTINGS These jumpers come in the SHORT position as a default factory setting J2 The CPU is connected to the 5V power supply through this jumper J3 The CPU AVCC supply pin is connected 5V power supply through this jumper J4 The CPU AGND supply pin is connected to the GND through this jumper The CPU AVR pin is connected to the 5V voltage through this jumper J6 The AVR pin is connected to the OV voltage through this jumper J7 9 The CPU signals are connected to the K7 connector J13 The board is powered from the 5V from the power supply voltage regulator J19 The CPU HRQ pin is connected to the SDA Mainboard signal J20 The CPU HAK pin is connected to the SCL Mainboard signal 12 CPU Board Power Supply Requirements CPU board does not come with power supply please check if your power supply match the requirements before you plug it to the CPU board Power supply voltage 9V Power supply current CPU board MB90F543 with Main board connected Single chip CPU mode no external peripheral connected 290mA max External bus mode no peripheral connected 350mA External bus with keyboard connected 450 typical but can vary with the keyboard used most of modern AT keyboard uses max 100mA User should check his keyboard current requirements before connecting the keyboard to the DevKit16 Mainboard
5. CIO I GND PLI 35V cls 10 5 1 Reser r 100 25 2 16 2 0 2 3 AVES 3 OUTC VSBRESIN SOME GND GND EE y P2 A18 AVR GND voc Ax 3 1 23 19 GND MB5771 EL US A e 36 AVR SIND jen ES 7 5 21 AVR 23 8 37 AGND K7 BOXHEADER 5X2 lo SINO 9 K3 mo 19 EA LADO Bio Ano 16 HST POV ANI D MD 94 40 219 INI P32 WRLAAWR PO2 AN2 SERRES K SS 3 40 p ANRH l3 P63 AN3 gt on noe 2 HRQ 14 IN4148SMD 7 80 22 A23 INS 4 P6A ANA Swi 9 JUMER 80 E D a P65 ANS PBI720 9 SCKL RDY 16 GND WRL PPGI P3Q RDY POG AN6 voc GND mwa P67 AN7 H ee 5 GND O 0 RDY OUTI INTO ND UA SOTO p TOTI POO INTO PTO INO SCK0 597 0 17 180 or INTI SINO INTI INTZ PANI PAANI N 5 mE P92 INT2 2 Ten 7 JUMER Eo 4 Ua PO3 INT3 RST 100N n eee s S E POAITXO 7 5 260 p gt C SIN2 PAO TXI ERO EDO 4 EE INS any POO TXI PIGOUTZ ING 0 Se PTIOUTMIN7 HST le BERDERIK 77 RST PRO PPGO DES PSI PPGI 100N INTS INT7 PAO PR2 PPG2 alle me B B
6. keyboard VGA interface connected 650mA WE RECOMMEND USING 9V STABILIZED POWER SUPPLY WITH 1 5A MIN OUTPUT CURRENT IF THE POWER SUPPLY NOT DELIVER CURRENTS AS SPECIFIED IN THE SPECIFICATION ABOVE THE DEVKIT16 WILL NOT WORK PROPERLY THE BOARD WILL BE PERIODICALLY RESET BY THE MB3771 POWER SUPPLY SUPERVISOR Warning If the DevKitl6 is powered using the on board stabilizer the supply current must not exceed the 1A limit of the stabilizer Before connecting any peripheral to the DevKit16 please check that its power supply current requirements doesn t does not cause this limit to be exceeded 13 Warranty and Disclaimer To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for the DEVKIT16 and all its deliverables eg software application examples target boards evaluation boards etc its performance and any consequential damages on the use of the Product in accordance with 1 the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered 1 the technical descriptions and 11 all accompanying written materials In addition to the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and or reverse engineering a
7. want to use K7 also in that case remove the 3 4 5 6 jumpers on the J23 419 J20 software emulation jumpers These jumpers allow to use Mainboard s connector EEPROM memory even in the case when CPU itself doesn t provide the interface When both of these jumpers are SHORT the CPU s HRQ signal is connected to the Mainboard s SDA signal via J19 and signal is connected to SCL signal An user can then program the HRQ signals to behave as interface 415 J16 Low speed XTAL jumpers When short these jumpers connect the 32 768 kHz crystal to the Bus Interface connector pins 417 418 High speed XTAL jumpers When short these jumpers connect the 4MHz crystal to the Bus Interface connector pins SW1 Reset button This button can be used for reseting the CPU SW2 Hardware standby button While this button is pressed the CPU stays in the standby mode all oscillators are stopped all I O pins are set to high impedance state special purpose registers such as the accumulator are reset to their default values but content of internal RAM is preserved SW3 CPU switches 1 MDO 2 MDI 3 2 4 S R 5 S H 6 H R 7 AD00 8 ADOI 01 These switches should be used only when using the CPU board without Mainboard or with the FPGA disabled see the description of J29 in the Mainboard section 1 MD0 2 MD1 3 MD2 these switches are
8. 2 P50 A15 IN5 SDA B15 OUT2 IN6 SCL C15 OUTS IN7 PPGO A16 OUTO PPG1 B16 OUT1 TIN1 16 VCC VCC A17 OUT3 IN7 ADTG C17 OUT2 IN6 TOT1 C17 AVCC AVCC A18 AVR B18 AVR C18 AGND A19 AN0 B19 AN1 C19 GND C20 AN2 A21 AN3 C20 AN4 A21 AN5 B21 AN6 C21 AN7 A22 RST B22 HST C22 INTO A23 INT1 B23 INT2 C23 INT3 A24 INT4 B24 5 C24 6 25 INT7 B25 INO C25 IN1 A26 IN2 B26 INS C26 OUT2 IN6 A27 OUTS IN7 B27 NC SGO C27 17 NC SGA DIN Conn PIN Device Bus Interface Bus PIN NO CPU Pin Nr Function CPU PIN Nr SIGNAL 2nd Function A28 73 TXO P94 B28 74 95 28 75 TX1 P96 A29 76 RX1 P97 B29 79 X1AJ C29 80 A30 82 X0J 0 83 X1J C30 VCC A31 49 MDO B31 50 MD1 C31 NC A32 51 MD2 B32 NC C32 18 GND K2 DIN 41612
9. CPU Board Description This chapter provides detailed description of CPU board including all DIP switches jumpers and connectors CPU board can work standalone or in connection with the Mainboard If the Mainboard is in use please switch all switches on CPU board configuration DIP to OFF CPU BOARD OVERVIEW CPU board is designed as low cost board which provides compatibility on Interface Bus and the Device Bus level for different CPUs Additionally headers pin compatible to CPU pins are provided This part contains description of CPU board for MB90F543CPU Connectors Jumpers buttons and switches Board layout CONNECTORS K1 Bus Interface connector This connector serves for connecting the CPU board to the Mainboard K2 Device Bus connector This connector provides connection to CPU peripherals Note For the pinout of these connectors please see the attachments section of this manual K7 CPU Serial interface connector ADOO 1 o 2 ADOI MDO 4 MD2 SERRES 5 Mo 6 SIN SOT 7 SCK VCC 9 o oj 10GND The serial interface connector should be used only when the CPU board is not connected to the mainboard because mainboard connects its own serial RS232 interface to the UARTO and UARTI CPU signals To be able to use the K7 connector please refer to the description of J7 J8 J9 jumpers later in this section Warning if you want to use the K7 connector when Mainboard is connect
10. E wa P83 PPG3 sw2 GND MDO 49 AVRE P84 OUTO PBI720 sop 5 50 AGND PSS OUTI s i 8 o AN MD2 PSG TINI T m E SRD A sr 9 GND voc n LT d ANS C7 20pF 4MHz lt 5 ri voc i AN6 o I5 160 GND 20 Sd e r 1 2 at me pim T lt _ voc SW3 IK 5 z MDO i cM MDI pu xo 82 T UMER R 10K MDO 16 9 GND voc 2 R9 10K 15 3 4 HEADER 10 2 HEADER 10 2 4 5 6 22pF RIO 10K mem ena 2 7 RID 10K RST 4 13 SR S 10K Masa unos SERRES N GND HEADER6 vss SE wr RST G 10K Ex mo D3 32 768KHz MB90540 GND 100N 1004 10 25 RIA 10K LED 5mm Title G Devkit16 CPU Board SWDIPS GND GND Size Number Revision 1 Date 8 1999 Sheet DX puboardI3 ddb Drawn By 19
11. Version FUJITSU MICROELECTRONICS EUROPE Development tools for 16LX Family CPU Board User Guide DEVELOPMENT TOOLS FOR 16LX FAMILY CPU Board User Guide Table Content What is in TRIS IR 2 What is not included in this 2 Where to find news options OTHER beans OTHER CPU boards latest FAQ and support CPU Board Features and Technical Specification 4 posePPD 4 5 Overview the DevKit16 FLASH Programming Tool CPU BOTA DESCHIPUON ce M 6 CPU Doard oVerVieW s 6 HC DEREN 6 Jumpers buttons and switches Default HW settings ass 12 CPU Board Power Supply Requirements RR 13 Warranty and DIS CIOL ER sicssssssseesosssssossasescesnsnensssensncncnssssssisuesccesssssssdecsesessusesecedsdusdsnsedessdsdcteesssdsvsssvesssvabessuseseusuavesonsouss hctsctscensuekccesssssusussesscssssesectsssssessasais 14 Reyision a nd Error AR n cscs 15
12. ard s GND is connected to CPU s AGND pin 45 Analog Reference Voltage for CPU When SHORT board s VCC is connected CPU s AVR pin When removed the voltage at the AVR pin is set to 4V J6 Analog Reference Voltage for CPU When SHORT board s GND is connected to CPU s AVR pin When removed the voltage at the AVR pin is set to 0 9V J7 J8 J9 UARTOA selection for the K7 connector These jumpers select which of the two UARTO interfaces signals will be connected to the pins of the K7 connector If all of these jumpers are in 1 2 position the UARTI interface signals will be connected to the K7 2 3 position the UARTO interface signals will be connected to the K7 connector Default setting the signals are connected to the Note The J7 jumper selects between 5 and 5 J8 between SINI and SINO J9 between SOTI and SOTO Warning if you want to use the K7 connector when Mainboard is connected to the CPU board you have to disconnect the selected serial interface UARTO or UART1 from the RS232 drivers on the Mainboard achieve this remove jumpers on positions 3 4 5 6 from both the J21 and J22 headers on the Mainboard Also when the Mainboard is connected to the CPU board and the Async Serial programming mode is set on the Mainboard System control DIP switches the FPGA UART is connected to UARTO or UARTI depending on the setting of the UARTO 1 switch after reset If you
13. connected to CPU pins MDO MD1 MD2 In the ON position a switch pulls the signal connected to it to log 0 The setting of these switches affects the mode of the processor The description of all the modes 5 the following table MD2 MDI MDO AD00 ADOI Mode name Reset vector area External data 00 01 bus witdth ON ON ON OFF OFF External vector mode 0 External 8 ON ON OFF OFF OFF External vector mode 1 External 16 ON OFF ON OFF OFF External vector mode 2 External 16 ON OFF OFF OFF OFF Internal vector mode Internal Mode data OFF ON ON X X Reserved OFF ON OFF X X Reserved OFF OFF ON ON ON Async serial programming OFF OFF OFF X X Reserved 10 4 S R if ON this switch connects the RES pin of the K7 connector to CPU s RST signal 5 S H if ON this switch connects the RES pin of the K7 connector to the CPU s HST signal 6 H R if ON the RST and HST signals are connected together 7 AD00 8 AD01 if ON the ADOO POO and ADOI POI signals are pulled to log 0 level This setting must be done for bringing processor to the Serial programming mode Rel 1 5 CPU BOARD FOR MB90F543 TOP OVERLAY UNIS spol s o SH2 GND K2 SW1 32 gt lt o 5 X a Le e m Q cc en 2 Q gt 9 gt IC2 e 78 uartt 1 2 2 3
14. ectronics Europe GmbH disclaims all other warranties whether expressed or implied in particular but not limited to warranties of merchantability and fitness for a particular purpose for which the Product is not designated 4 To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH s and its suppliers liability is restricted to intention and gross negligence NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever including but without limitation consequential and or indirect damages for personal injury assets of substantial value loss of profits interruption of business operation loss of information or any other monetary or pecuniary loss arising from the use of the Product Should one of the above stipulations be or become invalid and or unenforceable the remaining stipulations shall stay in full effect 14 Revision and Error List The following bugs have been found with the board and need to be observed when working with this tool Date Revisions Errors Revised Version 05 11 1999 Version 1 2 is valid for CPU Board ver 1 3 V1 2 13 02 2000 The table Device Bus K2 and Interface Bus K1 connectors V1 21 pins pages 16 17 18 was not consistent with the schematics 1 List of found errors and revisio
15. ed to the CPU board you have to disconnect the serial interface selected by 77 79 from the RS232 drivers on the Mainboard To achieve this remove jumpers on positions 3 4 5 6 from both the J21 and J22 headers on the Mainboard Also when the Async Serial programming mode is set on the Mainboard System control DIP switches the FPGA UART RS232 driver is connected to UARTO or UARTI depending on the setting of the UART0 1 switch after reset If you want to use K7 also in that case remove the 3 4 5 6 jumpers on the J23 as well K9 power supply connector GND 9V Before applying the power to the Devkit16 check the polarity of your power chord plug the GND must be in the center while the 9V on the shell of the connector Even thought the DevKit16 power lines are protected by a diode on the power input do not ever apply power with the opposite polarity Also make sure that the power supply complies to the specifications in chapter CPU board Power Supply Requirements K4 5 CPU pins connectors K3 16 1 A18 3 A20 5 A22 7 ALE 9 GND 11 WRH 13 HAK 15 CLK 17 SCKO 19 SINI 21 FVCC 23 SOT2 25 o SOT2 25 00 0 000 00 00 0 0 INT4 25 VSS AD00 AD02 AD04 AD06 AD08 AD10 AD12 AD14 O O O O O O O O J10 connector 1 VCC 2 VCC 3 VCC 4 VCC J11 GND connect
16. n be used to program it OVERVIEW OF THE DEVKIT16 FLASH PROGRAMMING TOOL DevKitl FLASH Programming Tool provides standard operations check progranmy verify for CPU Internal FLASH memory Mainboard FLASH or both DevKit16 FLASH programming tool Se x ESH External FLASH 3 internal Flash 128kB extemal Flash 2008C Base address 0000 Start End Length Start End addr Length 0 0000 010000 004000 1 FF0000 FF FFF 008000 FC4000 FCSFFF 002000 2 FF8000 002000 002000 3 4 Esternal bus 4 Yes C No Select FLASH for programming FFA000 FFBFFF 002000 FC8000 FCFFFF 008000 FFFFFF 004000 FD0000 FDFFFF 010000 000 FEFFFF 010000 FF0000 FFFFFF 010000 COM port CPU Frequency 4 MHz Connect Help Action Progress 1 co c O Status of the previous action With the standalone CPU board it is possible to program only the internal FLASH The check box External bus free should be set to no this tells the SW not to use the FPGA UART The Flashtool will guide you to set the proper mode on the CPU board DIP switches The communication will run on 9600Bd only and only CPU FLASH can be programmed For further information please see the DevKit16 FLASH Programming Tool online Help
17. nd or disassembling Note the DEVKIT16 and all its deliverables are intended and must only be used in an evaluation laboratory environment 1 Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer Concerning the hardware components of the Product Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer 2 Should a Product turn out to be defect Fujitsu Microelectronics Europe GmbH 5 entire liability and the customer s exclusive remedy shall be at Fujitsu Microelectronics Europe GmbH s sole discretion either return of the purchase price and the license fee or replacement of the Product or parts thereof if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport However this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH 3 To the maximum extent permitted by applicable law Fujitsu Microel
18. ns for version V1 2 15 Appendix Here you will find Interface bus and Device Bus description and CPU board schematics Device Bus K2 and Interface Bus K1 connectors pins DIN Conn Device Bus Interface Bus PIN PIN NO CPU Pin Nr Function CPU PIN Nr SIGNAL 2nd Function A1 18 SOTO 85 ADOO 1 19 SCKO 86 ADO1 P01 C1 20 SINO 87 02 P02 A2 24 SOT1 88 B2 22 SCK1 89 AD04 P04 C2 21 SIN1 90 05 P05 91 P06 B3 92 AD07 P07 C3 93 AD08 P10 A4 94 AD09 P11 B4 95 AD10 P12 C4 96 AD11 P13 A5 97 AD12 P14 B5 AD13 P15 C5 AD14 P16 A6 AD15 P17 B6 A16 P20 C6 A17 P21 A7 A18 P22 B7 A19 P23 C7 A20 P24 A8 A21 P25 B8 A22 P26 C8 A23 P27 A9 ALE P30 B9 P31 C9 WRL P32 WRH P33 HRQ P34 16 DIN Conn PIN Device Bus Interface Bus PIN NO CPU Pin Nr Function CPU PIN Nr SIGNAL 2nd Function C10 15 35 A11 47 TINO 16 RDY P36 B11 48 TOTO 17 CLK P37 C11 GND GND GND A12 67 TIN1 18 SOTO P40 B12 68 TOT1 19 SCKO P41 C12 20 SINO P42 A13 24 SOT1 P45 B13 INO 22 SCK1 P44 C13 IN1 21 SIN1 P43 A14 IN2 25 SOT2 P46 B14 INS 26 SCK2 P47 C14 4 28 SIN
19. or 2 17 4 A19 6 A21 8 A23 10 RD 12 WRL 14 HRQ 16 RDY 18 SOTO 20 SINO 22 SCK1 24 5011 26 5 2 26 SIN2 26 INTS 82 X0 84 VCC 86 ADOI 88 AD03 90 AD05 92 07 94 AD09 96 AD11 98 ADI3 100 5 INT6 ADTG 31 33 35 AVss 37 ANI 39 AN341 43 AN6 45 TINO 47 49 MD2 INO IN2 IN4 OUT2 IN6 PPG0 PPG2 OUTO 51 53 54 57 59 61 63 65 TINI 67 INTO 69 INT2 71 TXO 73 75 RST 77 79 K4 000 00 00 0 K6 O 0 0 00 0 0 00 00 00 0 0 0 0 32 INT7 34 36 AVR 38 40 AN2 42 Vss 44 ANS 46 AN7 48 TOTO 50 MDI 52 HST 54 INI 56 IN3 58 INS 60 OUT3 IN7 62 PPGI 64 PPG3 66 OUTI 68 TOTI 70 INTI 72 INT3 74 RX0 76 78 80 X0A JUMPERS BUTTONS AND SWITCHES 413 Supply for the whole board When SHORT the 5V from the voltage regulator is connected to board This jumper must be removed when using an external 5V power supply to avoid current flowing back to the regulator 42 Supply for CPU When SHORT the VCC is connected to CPU s VCC pins Before removing this jumper remove the J3 AVCC to CPU jumper as well to completely disconnect the power from the CPU 43 Analog Supply for CPU When SHORT board s 15 connected to CPU s AVcc pin J4 Analog Ground for CPU When SHORT bo
20. sit DevKitl6 WEB site www processorexpert com devkitl6 for news and giveaways You can also register in order to obtain news by mail For MCUs and Fujitu technologies please visit FUJITSU WEB site http ww fujitsu fme com When you need additional CPU personality board please call your nearest FUJITSU subsidiary or authorised FUJITSU distributor You should specify version of CPU you need soldered or in socket Socket version is provided for users who want to use the FUJITSU emulator CPU Board Features and Technical Specification This chapter introduces features of CPU board and provides necessary technical and operational information for DevKit16 contains only few features and the rest is provided by the Dewvkit16 F Y he CPU board was designed as a replaceable part of the Devkit16 So it Mainboard FEATURES Position for a PQFP 100 processor or NQPACK socket connectors for all CPU pins Bus Interface connector for main board connection Device Bus connector apower supply supervisor IC with reset generation RST HST buttons DIP switch for setting the CPU mode High speed in socket and low speed quartzes Serial port connector power supply regulators 5V or 3 3V depending on CPU used power supply connector for external power source and DC power supply circuitry Flash It If the CPU mounted on the CPU board has a FLASH memory the DevKit16 FLASH Programming Tool ca
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