Fairchild HCPL-3700 User's Manual
Contents
1. 0 0 5 1 15 2 25 8 3 5 4 4 5 Time Minute 50 Ramp up 3C sec e Peak reflow temperature 225C package surface temperature e Time of temperature higher than 183C for 60 150 seconds e One time soldering reflow is recommended www fairchildsemi com J jdno30 d0 adej19 U 91607 0 A V 00ZE 1dDH Se oe FAIRCHILD eal SEMICONDUCTOR TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx HiSec Across the board Around the world j Lo ActiveArray ImpliedDisconnect Bottomless IntelliMAX Build it Now ISOPLANAR CoolFET MICROCOUPLER CROSSVOLT MicroPak CTL MICROWIRE Current Transfer Logic Motion SPM DOME MSX E CMOS MSXPro EcoSPARK ocx EnSigna OCXPro FACT Quiet Series OPTOLOGIC FACT OPTOPLANAR FAST PACMAN FASTr PDP SPM FPS POP FRFET Power220 GlobalOptoisolator Power247 GTO PowerEdge DISCLAIMER PowerSaver PowerTrench Programmable Active Droop QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect ScalarPump SMART START SPM STEALTH SuperFET SuperSOT 3 SuperSOT 6 SuperSOT 8 SyncFET TCM The Power Franchise TM TinyBoost TinyBuck TinyLogic TINYOPTO TinyPower2. TinyWire TruTranslation uSerDes UHC UniFET VCX Wire FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms 2 A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Datasheet Identificat
3. 1s rise time to the 1 5 V level on the leading edge of the output pulse Tp 4 propagation delay is measured on the trailing edges of the input and output pulse Refer to Fig 9 7 Common mode transient immunity in logic high level is the maximum tolerable positive dV dt on the leading edge of the common mode pulse signal Voy to assure that the output will remain in a logic high state i e Vo gt 2 0 V Common mode transient immunity in logic low level is the maximum tolerable negative dV dt on the trailing edge of the common mode pulse signal Vey to assure that the output will remain in a logic low state i e Vo lt 0 8 V Refer to Fig 10 8 In applications where dV dt may exceed 50 000 V s Such as static discharge a series resistor Rec should be included to protect the detector chip from destructive surge currents The recommended value for Rcc is 240V per volt of allowable drop in Vcc between pin 8 and Vcc with a minimum value of 2400 9 Device is considered a two terminal device Pins 1 2 3 and 4 are shorted together and Pins 5 6 7 and 8 are shorted together 10 The 2500 Vays 1 min capability is validated by a 3 0 kVpms 1 sec dielectric voltage withstand test 11 AC voltage is instantaneous voltage for VTH amp VTH 12 All typicals at T 25 C Vcc 5V unless otherwise specified 2005 Fairchild Semiconductor Corporation www fairchildsemi com HCPL 3700 Rev 1 0 1 4 491dn090 dO 29e419 U 9
4. 4 4 4 4 Unit m he aor oel 5 Logic LOW output level at pin 6 occurs when Vin 2 VtH and when Viy gt Vt H once Vy exceeds VrH Logic HIGH output level at pin 6 occurs when Viy lt VrH and when Vin lt Vry once Viy decreases below Vry 2005 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 3 www fairchildsemi com J jdno 90 d0 29eJ 19 U 21607 0 A V 00ZE 1d9H Switching Characteristics T 25 C Vcc 5 V Unless otherwise specified Symbol AC Characteristics Test Conditions TpHL Propagation Delay Time R 4 7KQ C 30pF to Output Low Level Tpiy Propagation Delay Time R 4 7kQ Q 30pF to Output High Level Output Rise Time 10 90 R 4 7kQ C 30pF S Output Fall Time 90 10 R 4 7kQ C 30pF ICM Common Mode Transient lin O MA R 4 7kQ Immunity at Output High Level Vo min 2 0 V Vow 1400V 7 8 ICM Common Mode Transient IN 3 11mMA R 4 7kQ Immunity at Output Low Level Vo max 0 8V Ven 140V 7 8 Package Characteristics T 0 C to 70 C Unless otherwise specified Symbol Characteristics Test Conditions Min Typ Max Unit Withstand Insulation Voltage Relative humidity lt 50 2500 VRMS Ta 25 C t 1 min lig lt 2AM 9 Capacitance input to output f 1MHz Vio 0Vdc 06 F Notes 6 Tp propagation delay is measured from the 2 5V level of the leading edge of a 5 0V input pulse
5. a MIN 0 ct He 30 0 4 Lead Spacing PIN 1 0 270 6 86 0 250 6 35 0 390 9 91 0 370 9 40 i 0 200 5 08 0 140 3 55 SEATING PLANE 0 154 3 90 0 120 3 05 _ 0 300 7 62 __ TYP ee _ maa f 0 MoE 0 100 2 54 TYP 9 309 0010 Recommended Pad Layout for Surface Mount Leadforms J mi 0 070 1 78 Ltt JC Hi 0 060 1 52 0 100 2 54 LJ 0 295 7 49 0 415 10 54 0 030 0 76 0 016 0 41 0 008 0 20 www fairchildsemi com J jdno 90 d0 29e419 U 91607 0 A V 00ZE 1d9H Ordering Information No Suffix HCPL3700 Shipped in Tubes Marking Information Fairchild logo Two digit year code e g 07 Two digit work week ranging from 01 to 53 Assembly package code VDE mark Note Only appears on parts ordered with VDE option See order entry table EE 2005 Fairchild Semiconductor Corporation www fairchildsemi com HCPL 3700 Rev 1 0 1 9 J jdno 90 d0 29ej19 U 21607 0 A V 00ZE 1d9H Carrier Tape Specifications 4 90 0 20 0 30 0 05 12 0 0 1 4 0 0 1 01 55 0 05 1 75 0 10 a 7 5 0 1 A 16 0 10 30 0 20 10 30 0 20 ae 01 6 0 1 User Direction of Feed gt Reflow Profile 2005 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 Temperature C iiki 215C 10 30 s 250 225C peak 200 150 J 100 Time above 183C 60 150 sec y
6. levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only 40 to 85 EMITTER Surge 3ms 120Hz Pulse Rate Transient 10us 120Hz Pulse Rate 500 Max Input Power Dissipation 230 Max Input Voltage Pins 2 3 0 5 Max Total Package Power Dissipation 305 Max DETECTOR Output Current Average Supply Voltage Pins 8 5 0 5 to 20 Output Voltage Pins 6 5 0 5 to 20 Pg Output Power Dissipation 210 Max Notes 1 Derate linearly above 70 C free air temperature at a rate of 1 8 mW C 2 Derate linearly above 70 C free air temperature at a rate of 2 5 mW C 3 Derate linearly above 70 C free air temperature at a rate of 0 6 mA C 4 Derate linearly above 70 C free air temperature at a rate of 1 9 mW C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to absolute maximum ratings Symbol Parameter min Waw Ums 2005 Fairchild Semiconductor Corporation www fairchildsemi com HCPL 3700 Rev 1 0 1 2 J jdno 90 d0 29e419 U 21607 0 A V 00ZE 1d9H Electrical Characteristics T 0 C to 70 C Unless otherwis
7. 1607 0 A V 00ZE 1d9H Typical Performance Curves Fig 1 Logic Low Supply Current vs Operating Supply Voltage Ico LOGIC LOW SUPPLY CURRENT mA Vcc OPERATING SUPPLY VOLTAGE V Fig 3 Input Current Low Level Output Voltage vs Temperature Vcc 5 0 V Vin 5 0V O j o Input Current liy mA Ta TEMPERATURE C Fig 5 Propagation Delay vs Temperature N f An T e bI 20 gt F P 7 eT A sere ee ee ee a ee ee a E 40 20 0 20 40 60 8 Ta TEMPERATURE C Tp PROPAGATION DELAY us 0 100 2005 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 VtH DC VOLTAGE THRESHOLD V IIN INPUT CURRENT mA Tr RISE TIME us Fig 2 Input Current vs Input Voltage DC Pins 1 2 shorted together pins 3 4 shorted together Vin INPUT VOLTAGE V Fig 4 Current Threshold Voltage Threshold vs Temperature Ta TEMPERATURE C Fig 6 Rise and Fall Time vs Temperature CURRENT THRESHOLD mA ItH DC Ta TEMPERATURE C FALL TIME us Tf www fairchildsemi com J jdno 0 d0 29e419 U 91607 0 A V 00ZE 1d9H HCPL 3700 AC DC to Logic Interface Optocoupler Fig 8 External Threshold Characteristics V V vs Rx Rx EXTERNAL SERIES RESISTOR KQ MT RTT M N T A AONT Ta TEMPERATURE C vs Temperature Fig 7 Logic High Supply Current vu LNSYYND AlddNS HDIH 01907 H99 www fairchildsemi com 200
8. 5 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 5V O Pulse duf Generator bypass Output Vo Sea ey Seer 40 YOO TTT TIT PrI l Vor aa 1 l I l l l t tp He ViN Pulse Amplitude 50 V Pulse Width 1 ms f 100 Hz T Ty 1 0 us 10 90 Fig 9 Switching Test Circuit Roc O 5V J jdno 90 d0 29e4 19 U 91607 0 A V 00ZE 1d9H Vem Output O Vo VFF Ce Vo lin 0 mA SEE NOTE8S N Vo Min CL IS 30 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE Switching Pos B lN 3 11 mA VoL CML Fig 10 Test Circuit for Common Mode Transient Immunity and Typical Waveforms 2005 Fairchild Semiconductor Corporation www fairchildsemi com HCPL 3700 Rev 1 0 1 7 Package Dimensions Through Hole 0 270 6 86 0 250 6 35 0 390 9 91 0 370 9 40 z S 0 070 1 78 0 045 1 14 0 200 5 08 0 020 0 51 MIN ui 0 140 3 55 dp 0 154 3 90 t 0 120 3 05 0 022 0 36 la f 0 016 0 40 0 016 0 41 0008 0 20 0 100 2 54 TYP Surface Mount 0 390 9 91 N 0 370 9 40 F PIN 1 A A ID L _ 0 270 6 86 0 250 6 35 0 070 1 78 0 045 1 14 cawi A a a 0 022 0 56 e 016 0 41 0 100 2 54 TYP Lead Coplanarity 0 004 0 10 MAX Note All dimensions are in inches millimeters 2005 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 0 045 1 i 0 315 8
9. e specified Symbol lTH Input Threshold Current ITH Vo 0 4 V lo 4 2mA Input Threshold Voltage VTH Very lt ra IHys Vuys Input Clamp Voltage Vinci Vo V3 V3 GND Lin 10 mA Pins 1 amp 4 connected to Pin 3 Vince IV Val yn 10mA Pins 2 amp 3 Open Vincs V2 V3 V3 GND lin 15mA Pins 1 amp 4 Open Vite Vo V3 V3 GND lin 10mA Input Current Vin Vo V3 5 0V Pins 1 amp 4 Open ViHCt ViHC2 VIHC3 ViLc liN VD1 2 VD3 4 VoL loH Cin loCL Logic LOW Supply Current V V3 5 0V Vo Open Vcc 5V ICCH Note Vin Vt Veco 4 5 V 1 96 Vin Vo V3 Pins 1 amp 4 Open DC Pins 2 3 Voc 4 5 V Vo 0 4V lo gt 4 2mA Vin Vo V3 Pins 1 amp 4 Open Voc 4 5 V Vo 2 4 V lo 2 100A AC IVin V4 V4l Pins 2 amp 3 Open Pins 1 4 Vcc 4 5 V Vo 0 4 V lo gt 4 2 MA IVin IV1 Val Pins 2 amp 3 Open Voc 4 5 V Vo 2 4 V lo lt 100A Hysteresis luys He ITH Vhys VtH VTH ii Logic LOW Output Voltage Vcc 4 5 V loL 4 2mA Logic HIGH Output Current Vou Vec 18V Logic HIGH Supply Current Vcc 18V Vo Open Input Capacitance f 1MHz Viy OV Pins 2 amp 3 Pins 1 amp 4 Open 3 11 l 2 E 3 o 7 i id yp 4 1 2 8 9 l 0 s TA 4 1 2 1 3 ns O T 2 5 3 7 0 0 1 os 86 50 20 3
10. ee M E FAIRCHILD E SEMICONDUCTOR April 2007 HCPL 3700 AC DC to Logic Interface Optocoupler Features Description m AC or DC input The HCPL 3700 voltage current threshold detection m Programmable sense voltage optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically cou pled to a high gain darlington output The input buffer chip is capable of controlling threshold levels over a wide m Optoplanar construction for high common mode range of input voltages with a single resistor The output immunity is TTL and CMOS compatible m UL recognized file E90700 m VDE certified ordering option V e g HCPL3700V m Logic level compatibility m Threshold guaranteed over temperature 0 C to 70 C Applications m Low voltage detection E 5V to 240 V AC DC voltage sensing m Relay contact monitor E Current sensing m Microprocessor Interface E Industrial controls Schematic Package TRUTH TABLE Positive Logic A 0 1 uF bypass capacitor must be connected between pins 8 and 5 2005 Fairchild Semiconductor Corporation www fairchildsemi com HCPL 3700 Rev 1 0 1 49 dn090 dO 29e4 19 U 91607 0 A V 00ZE 1d9H Absolute Maximum Ratings No derating required up to 70 C Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be operable above the recommended operating conditions and stressing the parts to these
11. ion Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor The datasheet is printed for reference information only 2005 Fairchild Semiconductor Corporation HCPL 3700 Rev 1 0 1 11 Rev 125 www fairchildsemi com 49 dn090 dO a9ej19 U 91607 0 A V 00ZE 1dDH
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