Epson SED 1520 Series User's Manual
Contents
1. See Figure 2 EPSON 2 15 SED1520 Series Set Column Address This command specifies a column address of the display data RAM When the display data RAM is accessed by the MPU continuously the column address is incremented by 1 each time it is accessed from the set address Therefore the MPU can access to data continuously The column address stops to be incremented at address 80 and the page address is not changed continuously RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 0 A6 A5 A4 A3 A2 A1 Ao OOH to 4FH This command loads the column address register Ae A5 A4 A3 A2 Ao Column Address 0 00000 0 0 0 00000 1 1 1 00 1 1 14 1 79 Read Status Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 0 1 BUSY ADC ON OFF RESET 0 0 0 0 Reading the command I O register A0 0 yields system status information The busy bit indicates whether the driver will accept a command or not Busy 1 The driver is currently executing a command or is resetting No new command will be accepted Busy 0 The driver will accept a new command The ADC bit indicates the way column addresses are assigned to segment drivers ADC 1 Normal Column address n gt segment driver n ADCzO0 Inverted Column address 79 u segment driver u The ON OFF bit indicates the current status of the display It is the inverse of the polarity of the di2. 5 V 10 unless stated otherwise Rating P arameter Symbol Condition Min Max Unit Signal System cycle time tcYce 1000 ns Address setup time tawe 20 ns A0 CS R W Address hold time tAH6 10 ns Data setup time 596 80 ns Data hold time _ tDH6 10 ns DO to D7 Output disable time tOH6 CL 100 pF 10 60 ns Access time tACC6 B P 90 ns Enable Read EW 100 ns E pulsewidth Write 80 ns Rise and fall time tr tf 15 ns Vss 2 7 to 4 5 V Ta 20 to 75 C Rating P arameter Symbol Condition Min Max Unit Signal System cycle time tcYce 2000 ns Address setup time tawe 40 ns CS R W Address hold time tAH6 20 ns Data setup time 596 160 ns Data hold time _ tDH6 20 ns DO to D7 Output disable time tOH6 100 pF 20 120 ns Access time tACC6 i P 180 ns Enable Read dew 200 ns E pulse width Write 160 ns Rise and fall time tr tr 15 ns Notes 1 tCYC6 is the cycle time of CS E H not the cycle time of E 2 24 EPSON SED1520 Series Display Control Signal Timing So N 7 FR Input Ta 20 to 75 deg C Vss 5 0 V 10 unless stated otherwise Rating A Parameter Symbol Condition Min Typ Max Unit Sign
3. SED1520 Series Slave chip M S CS CL Vss OSC1 OSC2 Open Master chip L M S CS CL OSC1 OSC2 FE 2 14 gt SE 1 If the parasitic capacitance of this section increases the oscillation frequency may shift to the lower frequency Therefore the Rf oscillation frequency must be reduced below the specified level 2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips MPU driven with an external clock Y driver CL2 SED1521FAA CL Reset Circuit Detects a rising or falling edge of an RES input and initializes the MPU during power on Initialization status Display is off Display start line register is set to line 1 Static drive is turned off Column address counter is set to address 0 Page address register is set to page 3 1 32 duty SED1520 or 1 16 duty SED1522 is selected 7 Forward ADC is selected ADC command DO is 1 and ADC status flag is 1 8 Read modify write is turned off oce EPSON The input signal level at RES pin is sensed and an MPU interface mode is selected as shown on Table 1 For the 80 series MPU the RES input is passed through the inverter and the active high reset signal must be entered For the 68 series MPU the active low reset signal must be entered As shown for the MPU interface reference example the RES pin must be connected to the Reset pin and reset at the s
4. 1 5 bias 1 16 duty 1 6 bias 1 32 duty VDD Vss VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 FR 7 N T e W 72 COMO COM1 COM2 COM3 COM4 COMS5 COM6 COM7 COM1 VpD V1 COM2 M V3 V4 V5 COM8 COM10 COM11 COM12 COM13 COM14 COM15 H H H H F VDD V1 SEGO V8 V4 V5 VDD V1 V2 V3 SEG1 V SEG3 SEG4 SEGO V5 V5 V4 v3 v2 COM0 SEGO V yi VDD V3 V4 V5 V5 V4 v3 v2 COMO SEG1 M Vpop V3 V4 V5 Figure 4 LCD drive waveforms example EPSON 2 13 SED1520 Series COMMANDS Summary Command Coda Functi AO 50 Dz Ds Ds Ds Ds Dz D Do rad DspyOnOFF 1 0 1 0 t o 1 3 2 on unsdispayonorofe 1 ON 0 OFF Display start line 01 10 1 1 0 Display start address 0 to 31 species RAM Mae corisspan ng fo op
5. 159 6108 37 SEG35 1701 159 71 SEG1 4641 4547 4 COMB8 159 5909 38 SEG34 1901 159 72 SEGO 4641 4789 5 COMO 159 5709 39 SEG33 2100 159 73 AO 4641 5048 6 COM10 159 5510 40 SEG32 2300 159 74 CS 4641 5247 7 COM11 159 5310 41 SEG31 2499 159 75 CL 4641 5447 8 COM12 159 5111 42 SEG30 2699 159 76 E RD 4641 5646 9 COM13 159 4911 43 SEG29 2898 159 77 R W WR 4641 5846 10 COM14 159 4712 44 SEG28 3098 159 78 Vss 4641 6107 11 COM15 159 4512 45 SEG27 3297 159 79 DBO 4641 6307 12 SEG60 159 4169 46 SEG26 3497 159 80 DB1 4641 6506 13 SEG59 159 3969 47 SEG25 3696 159 81 DB2 4295 6884 14 SEG58 159 3770 48 SEG24 3896 159 82 DB3 4095 6884 15 SEG57 159 3570 49 SEG23 4095 159 83 DB4 3896 6884 16 SEG56 159 3371 50 SEG22 4295 159 84 DB5 3696 6884 17 SEG55 159 3075 51 SEG21 4641 482 85 DB6 3497 6884 18 SEG54 159 2876 52 SEG20 4641 681 86 DB7 3297 6884 19 SEG53 159 2676 53 SEG19 4641 881 87 VpD 3098 6884 20 SEG52 159 2477 54 SEG18 4641 1080 88 RES 2898 6884 21 SEG51 159 2277 55 SEG17 4641 1280 89 FR 2699 6884 22 SEG50 159 2078 56 SEG16 4641 1479 90 V5 2499 6884 23 SEG49 159 1878 57 SEG15 4641 1679 91 V3 2300 6884 24 SEG48 159 1679 58 SEG14 4641 1878 92 V2 2100 6884 25 SEG47 159 1479 59 SEG13 4641 2078 93 1901 68
6. SEG26 D36 C4 L SEG27 D37 C L SEG28 Co 85 L SEG29 RES 40 gt SEG30 FRc L SEG31 V5 c L SEG32 V3 L SEG33 V2 90 L SEG34 c 35 L SEG35 V4 M SEG36 V1 L SEG37 COM 0 lt 4 L SEG38 COM 1 95 M SEG39 COM 2 Index 30 gt SEG40 COM 3 4 L SEG41 COM 4 o SEG42 COM 5 co L SEG43 COM 6 m m m a F SEG44 wo N N EE ZZZZZZzzzo0000000000000000 88888888895999o oOD000 00 000 Note This is an example of SED1520F pin assignment The modified pin names are given below Product Pin Pad Number Name 74 75 96 to 100 1 to 11 93 94 95 SED1520F0A OSC1 OSC2 COMO to COM15 M S V4 V1 SED1521Fo0A CS CL SEG76 to SEG61 SEG79 SEG78 SEG77 SED1522F0A OSC1 OSC2 COMO to 7 SEG68 to 61 M S V4 V1 SED1520FAA CS CL COMO to COM15 M S V4 V1 SED1521FAA CS CL SEG76 to SEG61 SEG79 SEG78 SEG77 SED1522FAA CS CL COMO to 7 SEG68 to 61 M S V4 V1 SED1520 Common outputs COMO to COM15 of the master LSI correspond to COM31 to COM16 of the slave LSI SED1522 Common outputs COMO to COM15 of the master LSI correspond to COM15 to COMB of the slave LSI EPSON 2 3 SED1520 Series PAD Pad Arrangement Chip specifications of AL pad package Chip size 4 80x7 04x0 400 mm Pad pitch 100x100 um Chip specifications of gold bump package Chip size 4 80x7 04x0 525 mm Bump pitch 199 um Min Bump height 22 5 um Typ Bump s
7. 2 lines 1 LCD 16x141 16 t 61 2 141 SEG SEG SED1520F SED1521F COM 1 32 duty 33 characters x 4 lines LCD 32x202 SEG SEG SED1520F SED1521 SED1520F COM COM The SED1521F can be omitted the 32x122 dot display mode is selected Note A combination of AB or AA type chip that uses internal clocks and OB or OA type chip that uses external clocks is NOT allowed EPSON 2 29 SED1520 Series Package Dimensions Plastic QFP5 100 pin Dimensions inches mm 1 008 0 016 25 6504 0 787 0 004 20 t 0 1 51 81 50 E m S m H E m t 5 o e m Index els e OS Min 9 _ LE T m o 100 N MULT eon 1 026 0 004 30 858 8 0 65 50 1 oo So H H H H 0 012 50 004 se 8h 0 30 501 Se 57 i Plastic QFP15 100 pin 0 630 3 9 016 16 0 0 4 0 551 30 004 14 9 0 1 75 51 N D e eo 0 551 0 004 44 9 0 1 0 630 50 016 16 0 10 4 Index TUUUUUUUUUUUU UC UUUUUUUUU Nm o E
8. AT ToLCDCOM SED1520F0A VoD n Master M S OSC1 OSC2 FR SED1520 Series ote z N ite ei m SED1520F0A To LCD COM 7 _ gt Slave M S Vss OSC1 OSC2 FR Be ANN SED1520FAA SED1520FAA SED1522FAA SED1522FAA A To LCD SEG i t To LCD SEG A gt SED1520FAA To LCD COM I Slave M S Vss 3 1 To LCD SEG SED1521F0A Slave OSC1 OSC2 FR A ee SED1520FAA Ni Master M S FR External clock SED1520FoA SED1522Fo0A SED1521Foa See note 1 t To LCD SEG lt ToLCDCOM SED1520F0A A Master OSC1 OSC2 FR Rt lc mc EPSON 2 27 SED1520 Series SED1520FAA SED1521FAA A To LCD SEG 1 To LCD COM SED1520FAA lt q VoD i M S CL FR i To LCD SEG A SED1521 FAA i External clock Notes 1 The duty cycle of the slave must be the same as that for the master 2 Ifasystem has two or more slave drivers a CMOS buffer will be required 2 28 EPSON SED1520 Series LCD Panel Wiring Example The full dot LCD panel displays a character in 6x8 dots 1 16 duty 10 characters x 2 lines 1 r LCD 16x61 8 16 dee 61 o SEG COM SED1520F 1 16 duty 23 characters x
9. DATA N gt N gt no nei Address set Dummy read Data read Data read atN atN at N 4 1 WR 4 4 RD Internal Lf 1 L oa XC Xa x os address a Bus hold DC N X n X n 1 X lt n 2 Figure 1 Bus Buffer Delay Busy flag Column Address Counter When the Busy flag is logical 1 the SED1520 series is executing its internal operations Any command other than Status Read is rejected during this time The Busy flag is output at pin D7 by the Status Read command If an appropriate cycle time tcyc is given this flag needs not be checked at the beginning of each command and therefore the MPU processing capacity can greatly be enhanced Display Start Line and Line Count Registers The contents of this register form a pointer to a line of data in display data RAM corresponding to the first line of the display COMO and are set by the Display Start Line command See section 3 The contents of the display start line register are copied into the line count register at the start of every frame that is on each edge of FR The line count register is incremented by the CL clock once for every display line thus generating a pointer to the current line of data in display data RAM being transferred to the segment driver circuits The column address counter is a 7 bit presettable counter that supplies the column address for MPU access to the display data RAM See Figure 2 The counter is incremented
10. i N a 7 Power Save Combination command The Power Save mode is selected if the static drive is turned ON when the display is OFF The current consumption can be reduced to almost the static current level In the Power Save mode a The LCD drive is stopped and the segment and common driver outputs are set to the VDD level b The external oscillation clock input is inhibited and the OSC2 is set to the floating mode c The display and operation modes are kept The Power Save mode is released when the display is turned ON or when the static drive is turned OFF If the LCD drive voltage is supplied from an external resistance divider circuit the current passing through this resistor must be cut by the Power Save signal O 9 VDD 5 V2 SED1520 gt Vs SED1522 V4 e V5 Power Save signal Y VssH If the LCD drive power is generated by resistance division the resistance and capacitance are determined by the LCD panel size After the panel size has been determined reduce the resistance to the level where the display quality is not affected and reduce the power consumption using the divider resistor EPSON 2 19 SED1520 Series SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage 1 Vss 8 0 to 0 3 V Supply voltage 2 V5 16 5 to 0 3 V Supply v
11. is connected Input Used as an input pin of read control signals if R W is high or write control signals if low f the 80 series MPU is connected Input Active low The WR signal of the 80 series MPU is entered in this pin A signal on the data bus is fetched at the rising edge of WR signal EPSON SED1520 Series 3 LCD Drive Circuit Signals Name Description CL Input Effective for an external clock operation model only This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges If the system has a built in oscillator this is used as an output pin of the oscillator amp and an Hf oscillator resistor is con nected to it FR Input output This is an I P pin of LCD AC signals and connected to the M terminal of common driver selection Common oscillator built in model Output if M S is 1 Input if M S is 0 Dedicate segment model Input SEGn Output The output pin for LCD column segment driving A single level of VDD V2 V3 and V5 is selected by the combination of display RAM contents and RF signal 1 0 FR signal 1 0 1 0 Data VDD V2 V5 V3 Output level foe oles COMn Output The output pin for LCD common low driving A single level of V1 Va and V5 is selected by the combination of common counter output and RF signal The slave LSI has the reve
12. o 1 25 0 020 0 004 9 07 0 004 0 5593 018201 0 055 0 004 1 4 0 1 PF 0 005 0 002 0 127 t 0 05 0 12 0 020 0 004 0 5 30 2 0 039 1 0 2 30 EPSON SED1520 Series 5996 0 S1 G4S OF 9 819 0 jeuonisod 15158 1epjog wwg 8z d18 Youd yonpoug urge 10 Jaddo9 onA o4199 3 0 19dd09 9 eseg edeus wayed jeulwsa 3ndino CIS5000 CT IS00BET 002 2l CIS200011 I5 0086 0026 Bunejd us 9 0 9 bp OFM 00022 1 E2 XO la eros SZ suoneoyioeds zoos 910 80 STXVW S TXVA o RI 2 le E e m z x TE e P e d O Ji A G a Qs QIS20ST TS 2 3 X C 3 m E i esse Bupueur PON POOIXYR 36 QU pU E x i a poob 10 9jou Suryound SIOXVN 0 G6 0 9EI 1L 4079 at Om sor O0 E2 1 18 x62 0a CaS 0ST OT CFDA S022 p1 2 31 EPSON
13. pad chip SED1522 18 Au bump chip SED1522F internal QFP5 100pin SED1522F external QFP15 100pin SED1522Toa TCP Dot matrix LCD displays 1 8 1 16 Extension driver is the SED1522 Al pad chip SED1521 SED1522 7 Au bump chip SED1522F external QFP5 100pin SED1522F QFP15 100pin SED1522TAA TCP SED1540 Al pad chip SED1540 1 3 1 4 pase Au bump chip Segment type displays SED1540F QFP5 100pin it Planning TCP Tape Carrier Package Supply voltage LCD voltage range V range V Display Microprocessor Frequency Application additional Part number SegmentCommon RAM bits interface KHz Package toatures SED1560 Al pad chip SED1560 Al pad chip SED1560 1 48 1 49 Au bump chip SED1560 1 64 1 65 Au bump chip SED1560To8 TCP SED1560TaA QTCP SED1561 Al pad chip Built in power circuit for LCD SED1561 166x65 Alpadchip Voltage tripler SED1560 o8 1 9 bias SED1561 bits Au bump chip SED1560 e 1 7 bias 1 24 1 25 Mis 132 138 A chip SED eb ee S Das SED1561T48 TCP SED1561TQA QTCP SED1562DoA Al pad chip SED1562 1 16 1 17 Au bump chip SED1562T 1 5bias TCP SED1562T 8 bit parallel QTCP SED1565 or Serial Au bump chip SED1565 Au bump chip SED1565 1 65 Au bump chip SED1565T0A 1 7 1 9 bias TCP SED1565T0B TCP SED1565T
14. panel capacitances 15 tR Reset time represents the time from the RES signal edge to the completion of reset of the internal circuit Therefore the SED1520 series enters the normal operation status after this tR EPSON 2 21 90 SION Ux SED1520 Series Relationship between fosc frR and Rt and operating bounds on Vss and V5 9 Relationship between oscillation frequency frames and Rf SED1520F0A SED1522F0A OSC1 Rf z OSC2 Same for 1 16 and 1 32 duties Ta 25 C Vss 5V Ta 25 C Vss 5V 40 200 N ND i 30 x o 20 100 o co 5 m 10 0 05 10 15 20 25 0 05 10 15 20 25 Rf MQ Rf M9 Figure 5 a Figure 5 b Relationship between external clocks fCL and frames SED1520FAA SED1522FAA duty1 32 EE duty1 16 200 duty1 8 P Pd L n A 100 d t Y uL oe O 0 1 2 3 fCL kHz Figure 5 c 10 Operating voltage range of Vss and V5 systems 15 S 10 Operating voltage range 1 gt 5 1 L 1 1 0 2 4 6 8 Vss V Figure 6 2 22 EPSON SED1520 Series AC Characteristics MPU Bus Read Write I 80 family MPU A0 CS 7 N T e W 7 t DH8 tDS8 DO to D7 WRITE t OH8 t ACC8 DO
15. to D7 READ Ta 20 to 75 deg C Vss 5 0 V 10 unless stated otherwise Rating Parameter Symbol Condition Min Max Unit Signal A 1 ddress hold time tAH8 10 ns A0 CS Address setup time taws 20 ns System cycle time 1000 ns WR BD Control pulsewidth tcc 200 ns Data setup time 1598 80 ns Data hold lime tDH8 10 ns DO to D7 RD access time tACC8 100 pF 90 ns Output disable time iCH8 p P 10 60 ns Rise and fall time tr tf 15 ns Vss 2 7 to 4 5 V Ta 20 to 75 C Rating Parameter Symbol Condition Min Max Unit Signal Address hold time tAH8 u 20 ns 0 CS Address setup time taws 40 ns System cycle time tcYca u 2000 ns WR BD Control pulse width tcc 400 ns Data setup time 5958 u 160 ns Data hold lime tDH8 20 ns DO to D7 RD access time tACC8 100 pF 180 ns Output disable time iCH8 z 20 120 ns Rise and fall time tr tf 15 ns EPSON 2 23 SED1520 Series MPU Bus Read Write II 68 family MPU gt A0 CS t DH6 DO to D7 WRITE t ACC6 t OH6 DO to D7 READ Ta 20 to 75 deg C Vss
16. 0H normal This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit board design See Figure 2 for a table of segments and column addresses for the two values of D Static Drive ON OFF __ RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 0 1 0 0 1 0 D A4H A5H Forces display on and all common outputs to be selected D 1 Static drive on D 0 Static drive off Select Duty Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 0 1 0 1 0 0 D A8H A9H This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F It is invalid for the SED1521F which performs passive operation The duty cycle of the SED1521F is determined by the externally generated FR signal SED1520 SED1522 D 1 1 32 duty cycle 1 16 duty cycle D 0 1 16 duty cycle 1 8 duty cycle When using the SED1520F0A SED1522Fo04 having a built in oscillator and the SED1521F0A continuously set the duty as follows SED1521Foa SED1520Fo0A 1 32 1 32 1 16 1 16 SED1522Fo0A 1 16 1 32 1 8 1 16 EPSON 2 17 SED1520 Series Read Modify Write RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 1 1 0 0 0 0 0 This command defeats column address register auto increment after data reads The current conetents of the column a
17. 69 8 1 8 1 16 Package code For example SED1520 SED1520T SED1520F PKG SED1520F A QFP5 100pin SED1520F c QFP15 100pin SED1520D Chipr SED1520D A Al pad SED1520D B Au bump EPSON 2 1 7 N T e W 7 SED1520 Series BLOCK DIAGRAM An example SED1520 AA gt COMo to COM15 SEGo to SEGeo VoD Vss iD 7 x e gt a z gt LCD drive circuit A Common counter Display data latch circuit Display data RAM 2560 bit Display start line register Line counter ir Line address decoder I O buffer Column address decoder B TT cL Display timing Column address counter FR generator id circuit register Column address register Command Status decoder Bus holder ME MPU interface c om 18 zeg e o c e uua as Ta oc 2 2 EPSON SED1520 Series PACKAGE OUTLINE QFP5 7 N T e W 7 QFP15 N EBZ 2 qnqeenaocr DIs9tes CDD CDD UD E D D t ujOO 0010000000000 00 00 00 00 0 00 00 0 0 0 0 Vss C4 R 8 8 8 50 gt SEG20 D30 L SEG21 D31 L SEG22 D32 c L SEG23 D33 80 L SEG24 D34 C 45 L SEG25 D35 L
18. 84 26 SEG46 159 1280 60 SEG12 4641 2277 94 V4 1701 6884 27 SEG45 159 1080 61 SEG11 4641 2477 95 V1 1502 6884 28 SEG44 159 881 62 SEG10 4641 2676 96 COMO 1302 6884 29 SEG43 159 681 63 SEGQ 4641 2876 97 COM1 1103 6884 30 SEG42 159 482 64 SEG8 4641 3075 98 COM2 903 6884 31 SEG41 504 159 65 SEG7 4641 3275 99 COMG3 704 6884 32 SEG40 704 159 66 SEG6 4641 3474 100 COMA 504 6884 33 SEG39 903 159 67 SEG5 4641 3674 34 SEG38 1103 159 68 SEG4 4641 3948 The other SED1520 series packages have the different pin names as shown Package Pad No 74 75 96 to 100 1 to 11 93 94 95 SED1520Do OSC1 OSC2 COMO to COM15 M S V4 V1 SED1522Do OSC1 OSC2 COMO to 7 SEG68 to 61 M S V4 V1 SED1522D OSC1 OSC2 COMO to 7 SEG68 to 61 M S V4 V1 SED1521Do CS CL SEG76 to SEG61 SEG79 SEG78 SEG77 SED1521 Da CS CL SEG76 to SEG61 SEG79 SEG78 SEG77 EPSON 2 5 SED1520 Series PIN DESCRIPTION 1 Power Pins Name Description VDD Connected to the 5Vdc power Common to the Vcc MPU power pin Vss 0 Vdc pin connected to the system ground V1 V2 V3 V4 V5 Multi level power supplies for LCD driving The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp and supplied These voltages must satisfy the following Voo 2 V1 V22 Va 2 V4 2 Vs 2 System Bus
19. Connection Pins D7 to DO Three state I O The 8 bit bidirectional data buses to be connected to the 8 or 16 bit standard MPU data buses Input Usually connected to the low order bit of the MPU address bus and used to identify the data or a command A020 DO to D7 are display control data A0 1 DO to D7 are display data RES Input When the RES signal goes 11 the 68 series MPU is initialized and when it goes the 80 series MPU is initialized The system is reset during edge sense of the RES signal The interface type to the 68 series or 80 series MPU is selected by the level input as follows High level 68 series MPU interface Low level 80 series MPU interface CS Input Active low Effective for an external clock operation model only An address bus signal is usually decoded by use of chip select signal and it is entered If the system has a built in oscillator this is used as an input pin to the oscillator amp and an Hf oscillator resistor is connected to it In such case the RD WR and E signals must be ORed with the CS signals and entered E RD f the 68 series MPU is connected Input Active high Used as an enable clock input of the 68 series MPU f the 80 series MPU is connected Input Active low The RD signal of the 80 series MPU is entered in this pin When this signal is kept low the SED1520 data bus is in the output status R W WR f the 68 series MPU
20. Dos Au bump chi Right si 132x65 8 bit parallel EAE s aa omon D1531Toa 24 6 Ge en Ter Common Both side D1532DoA Alpadchip SED1533 k8 D1532DeA 1 64 1 65 Al pad chip Left side D1532DoB Au bump chip no VREG D1532DBA Au bump chip D1532ToA TCP D1532T8A TCP D1535Do8 Au bump chip TCP Tape Carrier Package 2 SED1520 Series Contents OVERVIEW 2 1 FEATURES etienne MIA II III EDITI 2 1 BLOCK DIAGRAM ep 2 2 PACKAGE OUTLINE iets tieniti nee oerte endete eset dem eet ete cse deatur 2 3 EROR V REESE een Oe er 2 4 Pad AtranQemMent 2 4 2 5 PIN DESGRIPTION 2 6 UB Joi 2 6 2 System Bus Connection Pih 2 6 3 ECD Drive Circuit Signals oor titre err een eri tornei tee 2 7 BLOCK DESCRIPTION ca etuer EIGENS ARI 2 8 System eat 2 8 Display Start Line and Line Count Registers crier tein innen 2 9 Colum Address Counter ict ciis ee d Ce Wee n oec Deed epa iaceat 2 9 Page Reg
21. EPSON SEIKO EPSON CORPORATION NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson Seiko Epson reserves the right to make changes to this material without notice Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency Seiko Epson corporation 1998 All right reserved 18088 and 18086 are registered trademarks of Intel Corporation Z80 is registered trademark of Zilog Corporation V20 and V30 are registered trademarks of Nippon Electric Corporation CONTENTS Selection Guide 1 SED1510 Series 2 SED1520 Series 3
22. O to D7 Active low 68 series T T T T il Active high 80 series T RD WR T i Data transfer The SED1520 and SED1521 drivers use the AO E or RD and R W or WR signals to transfer data between the system MPU and internal registers The combina tions used are given in the table blow In order to match the timing requirements of the MPU with those of the display data RAM and control registers all data is latched into and out of the driver This introduces a one cycle delay between a read request for data and the data arriving For example when the MPU executes a read cycle to access display RAM the current contents of the latch are placed on the system data bus while the desired contents of the display RAM are moved into the latch This means that a dummy read cycle has to be executed at the start of every series of reads See Figure 1 No dummy cycle is required at the start of a series of writes as data is transferred automatically from the input latch to its destination Common 68 MPU EM 80 MPU E Function AO R W RD WR 1 1 0 1 Read display data 1 0 1 0 Write display data 0 1 0 1 Read status 0 0 1 0 Write to internal register command 2 8 EPSON WRITE SED1520 Series MPU DATA N N 1 Bus Internal timing hold N X WR READ N 1 RD MPU
23. SED152A Series 4 SED1526 Series 5 SED1530 Series 6 SED1540 Series 7 SED1560 Series 8 SED1565 Series 9 SED1570 Series SED1500 Series Selection Guide LCD drivers with RAM for small Ultra low power consumption and on chip RAM make this series ideal for compact and medium sized displays LCD based equipment SED1500 series Supply voltage LCD voltage Display Microprocessor Frequency Application additional Part number range V range V Segment Common RAM bits interface KHz Package features SED1510 pad chip SED1510 Au bump chip Small segment type LCD display Command and data SED1510 9 6 8 6 Serial 18 internal QFP12 48pin interface SED1510F QFP6 60pin SED1511 A pad chip eel segment type LCD dislays Data only interface SED1520 pad chip SED1520 18 Au bump chip SED1520F internal QFP5 100pin SED1520F extemal OFP15 100pin SED1520Toa ieee TCP Dot matrix LCD displays E i iver is th SED1520 Alpadohip cen driver is the SED1520 5 Au bump chip SED1520F external QFP5 100pin SED1520F QFP15 100pin SED1520TAA TCP SED1521 Al pad chip SED1521 Au bump chip SED1521F external QFP5 100pin SED1521F QFP15 100pin SED 1521 Toa TCP Extension driver for the SED1521 1 8 1 32 Alpadchip SED1520 and SED1522 SED1521 8 bit parallel Au bump chip SED1521F 2 QFP5 100pin SED1521F external QFP15 100pin SED1521TA TCP SED152A Al pad chip P substrate version of SED1521 SED1522 Al
24. WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 0 1 0 1 1 1 D AEH AFH This command turns the display on and off D 1 Display ON D 0 Display OFF Display Start Line This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COMO The display area begins at the specified line address and continues in the line address increment direction This area having the number of lines of the specified display duty is displayed If the line address is changed dynamically by this command the vertical smooth scrolling and paging can be used 0 RW Ao RD WR D7 De Ds D4 D3 D2 D1 Do 0 1 0 1 1 0 A4 A3 A2 A1 Ao COH to DFH This command loads the display start line register A4 A3 A2 Ao Line Address 0 0 0 0 0 0 0 0 0 0 1 1 144 4 1 3 See Figure 2 Set Page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU Any bit of the display data RAM can be accessed when its page address and column address are specified The display status is not changed even when the page address is changed 1 RW Ao RD WR D7 De Ds D4 D3 D2 D1 Do 0 1 0 1 0 1 1 1 0 A1 Ao B8H to BBH This command loads the page address register A1 Ao Page 0 0 0 0 1 1 1 0 2 1 1 3
25. al Low level pulsewidth tWLCL 35 us High level pulsewidth tWHCL 35 us CL Rise time tr 30 150 ns Fall time tf 30 150 ns FR delay time tDFR 2 0 0 2 2 0 us FR Vss 2 7 to 4 5 V Ta 20 to 75 C Rating z Parameter Symbol Condition Min Typ Max Unit Signal Low level pulse width tWLCL 70 us High level pulse width tWHCL 70 us CL Rise time tr E m 60 300 ns Fall time tf 60 300 ns FR delay time tDFR 4 0 0 4 4 0 us FR Note The listed input tDFR applies to the SED1520 and SED1521 and SED1522 in slave mode Output Ta 20 to 75 deg C Vss 5 0 V 10 unless stated otherwise m Rating Parameter Symbol Condition Min Typ Max Unit Signal FR delay time tDFR CL 100 pF LI 0 2 0 4 us FR Vss 2 7 to 4 5 V Ta 20 to 75 C Rating i Parameter Symbol Condition Min Typ Max Unit Signal FR delay time tDFR CL 100 pF 0 4 0 8 us FR Notes 1 The listed output tDFR applies to the SED1520 and SED1522 in master mode EPSON 2 25 SED1520 Series APPLICATION NOTES MPU Interface Configuration 80 Family MPU Vcc AO A1 to A7 MPU IOQR DO to D7 RD WR RES GND E a Decoder gt gt gt gt EPSON 2 26 dq RESET AO VDD CS SED1520FAA DO to D7 RD WR RES Vss V5 i LCD Drive Interface Configuration SED1520FoA SED1520F0A SED1522FoA SED1522F0A A To LCD SEG i
26. ame time as the MPU initialization If the MPU is not initialized by the use of RES pin during power on an unrecoverable MPU failure may occur When the Reset command is issued initialization 2 11 7 N T e W 7 Start line EPSON Figure 2 Display Data RAM Addressing SED1520 Series Example Response Page address DATA Less um Do L3 00H COM 0 Di 01 COM 1 Dz I 02 COM 2 D3 03 COM 3 D1 D2 0 0 Da Page 0 04 COM 4 Ds n 05 COM 5 De 7 06 COM 6 D7 f i eo 07 COM 7 Do E 08 COM 8 Di 09 COM 9 D2 0A COM 10 T Ds 0B COM 11 2 Da Page 1 0C COM 12 Ds 0D E COM 13 De COM 14 Dz EE OF COM 15 Do oy EE SE E 10 amp COM 16 Di 11 a COM 17 Dz 12 COM 18 i D3 Bases 13 COM 19 Da 14 COM 20 Ds 15 COM 21 De 16 COM 22 D7 TE 17 M 1 COM 23 Do 18 COM 24 Di 19 COM 25 De 1A COM 26 i Ds 1B COM 27 Da 1C COM 28 Ds 1D COM 29 De 1E COM 30 D7 1F COM 31 a lz ij 1ssssssss5 Sis 8 8 8 n ugggiese Sls5ls a c 9 e s ic r 0 E g 2 NININ 0 2 12 SED1520 Series
27. by one every time the driver receives a Read or Write Display Data command Addresses above 50H are invalid and the counter will not increment past this value The contents of the column address counter are set with the Set Column Address command Page Register The page resiter is a 2 bit register that supplies the page address for MPU access to the display data RAM See Figure 2 The contents of the page register are set by the Set Page Register command Display Data RAM The display data RAM stores the LCD display data on a 1 bit per pixel basis The relation ship between display data display address and the display is shown in Figure 2 EPSON 2 9 7 N T e W 7 SED1520 Series Common Timing Generator Circuit Generates common timing signals and FR frame signals from the CL basic clock The 1 16 or 1 32 duty for SED1520 or 1 8 or 1 16 duty for SED1522 can be selected by the Duty Select command If the 1 32 duty is selected for the SED1520 and 1 16 duty is selected for the SED1522 the 1 32 and 1 16 duties are provided by two chips consisting of the master and slave chips in the common multi chip mode SED1520 FR signal Master output Master Common 243 XaX 28 Slave Common SED1522 FR signal Master output Master Common a X Slave Common Display Data Latch Circuit This latch stores one line of display data fo
28. ddress register are saved This mode remains active until an End command is received Operation sequence during cursor display When the End command is entered the column address is returned to the one used during input of Read Modify Write command This function can reduce the load of MPU when data change is repeated at a specific display area such as cursor blinking Any command other than Data Read or Write can be used in the Read Modify Write mode However the Column Address Set command cannot be used Set Page Address Set Column Address Read Modify Write Dummy Read Read Data Write Data End __ RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 1 1 0 1 1 1 0 EEH This command cancels read modify write mode and restores the contents of the column address register to their value prior to the receipt of the Read Modify Write command Return Read Modify Write mode is selected End 2 18 EPSON SED1520 Series Reset RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 0 1 0 1 1 1 0 0 0 1 0 E2H This command clears the display start line register and set page address register to 3 page It does not affect the contents of the display data RAM When the power supply is turned on a Reset signal is entered in the RES pin The Reset command cannot be used instead of this Reset signal
29. istar omes ca oS N COEPI Ee ENE AEE 2 9 Display Data RAM MEE 2 9 Gommon Timing Generator CIFCUIL 5 co ent aa Ee a E aa e ies 2 10 Display Data Latch rn irre terreri ci rit eren 2 10 ECDDiver Circuito 2 10 Display Timing Generation rera tete ter Li entes 2 10 Oscillator Circuit SED1520 0A ONIY erret ta eite te irre Enti nee ta L 2 11 Reset eei 2 11 COMMANDS GINE DIDI IUE IP PIDE 2 14 IE 2 14 Command Description enata ere ree ether eee ten ce d vr eed cud adiu 2 15 ized gie ct 2 20 Absolute Maximum Ralirigs 2 20 Electrical Specifications oer rct crinis aad veel ole A eoe Me ced dd 2 20 APPEIGATIONANOTES aoi e pei aka o e MR LIAE 2 26 MPU Interface Configurations tem rrr 2 26 LCD Drive Interface Configuration odii dee ee exco ee de t La Cn ete 2 27 LGD Panel WiringEXample tin ene etant abe ben tct nid ide e cO ien denis 2 29 Package DIMENSIONS er crue Rex eue e EE sg puer en darehscenoctenscs EE ERIPEEENUI EE DE EPA RE XR EUR REF 2 30 7 N T e W 7 OVERVIEW The SED1520 family of dot matrix LCD drivers are designed for the display of characters and graphics The drivers generate LCD drive signals derived fr
30. ize 132x111 um 120 um for mushroom model 116x92 um 4 for vertical model 100 95 90 0 0 a x 7 04 mm 85 80 75 70 65 20 60 25 5 55 a eo e wo 30 5 35 40 45 50 Y 4 80 mm Note An example of SED1520DAA die numbers is given These numbers are the same as the bump package 2 4 EPSON SED1520 Series PAD ARRANGEMENT An example of SED1520DA pin names is given The asterisk can be A for AL pad package or B for gold bump package SED1520DasB Pad Center Coordinates S Pad Pin Pad Pin Pad Pin a No Name No Name No Name us 1 COMS 159 6507 35 SEG37 1302 159 69 SEG3 4641 4148 2 COME 159 6308 36 SEG36 1502 159 70 SEG2 4641 4347 3 COM7
31. oc TCP SED1566 Au bump chip ku 132x65 ee Built in power circuit for LCD SED1566 1 6 1 8 bias Au bump chip DC DCx4 SED1566T0A TCP SED1567 Au bump chip SED1567 ub Au bump chip SED1567 Au bump chip 1 5 1 6 bias SED1567T0B TCP SED1567Toc TCP SED1568Do8 1 55 1 6 1 8 bias Au bump chip SED1569Do8 1 53 Au bump chip SED1569T 1 6 1 8 bias TCP ou 1 64 1 200 pd 4 bit parallel Apad Built in self refreshing function SED1570Do8 bits Au bump chip SED1526D A Alpadchip Built in power circuit for LCD SED1526D s 1 8 1 9 Au bump chip ipler SED1526F a 1 6 1 17 QFP5 128pin VREG 3 5 D1526 e SED1526T Supply 8 bit parallel TCP n RC SED1528D A voltag 3 or Serial Al pad chip te of COMS SED1528D Au bump chip SED1528 0 SED1528F QFP5 i28pin SED1528 t SED1528T A TCP no VREG Application additional features Display Microprocessor Frequency KHz Package Supply voltage LCD voltage Part number range V range V Segment Common RAM bits interface SED1530Doa Al pad chip D1530DAA Al pad chip D1530DoB 1 32 1 33 Au bump chip D1530DaB Au bump chip D1530TAA TCP Built in power circuit for LCD D1531Doa Alpad chip Voltage quadrupler SED153 kox D1531
32. of display Setpageaddress 0 1 0 1 0 1 1 1 0 Page 0 to 3 Sel USB RAM page in page address register Set col i i et column 0 Column address 0 to 79 Sets display RAM address in segment address column address register Reads the following status BUSY 1 Busy 0 Ready ADC 1 CW output Read status 0 0 1 Busy ADC JON OFF Reset 0 0 0 0 0 CCW output ON OFF 1 Display off 0 Display on RESET 1 Being reset 0 Normal Write display data 1 1 0 Write data Writes data from data bus into display RAM Reads data from display RAM onto dat Read display data 1 0 1 Read data 7 SUPE eee Select ADC 01 0 1 0 1 0 0 0 0 0 1 0 CW output 1 CCW output tatis dri AUN i Statis drive olilo 1 0 1 0 011 0 n iis static driving operation ON OFF 1 Static drive 0 Normal driving Selets LCD duty cycle Select d 01 0 1 0 1 0 110 0 0 1 SRM A 4 12 0 116 Read Modify Write 0 1 0 1 1 1 0 010 0 0 Read modify write ON End 0 1 0 1 1 1 0 111 1 0 Read modify write OFF Reset 0 1 0 1 1 1 0 0 0 1 0 Software reset 2 14 EPSON SED1520 Series Command Description Table 3 is the command table The SED1520 series identifies a data bus using a combination of AO and R W RD or WR signals As the MPU translates a command in the internal timing only independent from the external clock its speed is very high The busy check is usually not required Display ON OFF 7 N T e W 7 Ao RD
33. oltage 3 V1 V4 V2 V3 V5 to 40 3 V Input voltage VIN Vss 0 3 to 0 3 V Output voltage Vo Vss 0 3 to 0 3 V Power dissipation PD 250 mW Operating temperature Topr 40 to 85 deg C Storage temperature Tstg 65 to 150 deg C Soldering temperature time at lead Tsol 260 10 deg C sec Notes 1 All voltages are specified relative to VDD 0 V 2 The following relation must be always hold Vpp2 V1 2 V22 V3 2 V42 V5 3 Exceeding the absolute maximum ratings may cause permanent damage to the device Functional operation under these conditions is not implied 4 Moisture resistance of flat packages can be reduced by the soldering process so care should be taken to avoid thermally stressing the package during board assembly Electrical Specifications DC Characteristics Ta 20 to 75 deg C VDD 0 V unless stated otherwise Parameter Symbol Condition Min de Max Unit Applicable Pin Operating Recommended 5 5 5 0 4 5 voltage 1 Vss V Vss See note 1 Allowable 7 0 2 4 Recommended Vs 13 0 3 5 V V5 Operating Allowable 13 0 See note 10 voltage 2 Allowable V1 V2 0 6xV5 VDD V V1 V2 Allowable V3 V4 V5 0 4xV5 V V3 V4 ViH Vss42 0 VDD See note 2 amp 3 High level input voltage Doe ve mu Vss 3V 0 2xVss VDD See note 2 amp 3 V
34. om bit mapped data stored in an internal RAM The drivers are available in two configurations The SED1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages These features give the designer a flexible means of implementing small to medium size LCD displays for compact low power systems The SED1520 which is able to drive two lines of twelve characters each The SED1521 which is able to drive 80 segments for extention The SEDI522 which is able to drive one line of thirteen characters each SED1520 Series FEATURES Fast8 bit MPU interface compatible with 80 and 68 family microcomputers Many command set Total 80 segment common drive sets Low power 30 uW at 2 kHz external clock Wide range of supply voltages VDD Vss 24 to 7 0 V VDD V5 3 5 to 13 0 V Low power CMOS 9 o Line up Product Clock Frequency Number Number Name Applicable Driver of SEG of CMOS Duty On Chip External Drivers Drivers SED1520 0x 18 kHz 18 kHz SED1520 0x SED1521 0 61 16 1 16 1 32 SED1521 0 18 kHz SED1520x0x SED15220 80 0 1 8 to 1 32 SED1522 0x 18kHz 18 kHz SED1522 k0x SED1521 k0x 69 8 1 8 1 16 SED1520 kAx 2 kHz SED1520 kAx SED1521 kAx 61 16 1 16 1 32 SED1521 kAx 2 kHz SED1520 kAx SED1522 kAx 80 0 1 8 to 1 32 SED1522 kAx 2 kHz SED1522 kAx SED1521 kAx
35. play fcL 2 kHz 15 4 5 Dynamic current dissipation V5 5V pA Vss 3V RF 1MQ 60 120 During access tc 200 kHz 300 500 lbo 2 Vss 3V pA See note 8 During access tcyc 200 kHz Pd 300 Input pin capacitance Ta 25 deg 6 f 1 MHz 5 0 8 0 pF All input pins 0 Rf 1 0 MQ 3296 15 18 21 Oscillation frequenc puc kHz See note 9 Rr210MQ 42 AE Vss 3 0V RES Reset time tR 1 0 uS See note 15 Notes 1 Operation over the specified voltage range is guaranteed except where the supply voltage changes suddenly during CPU access AO DO to D7 E or RD R W or WR and CS CL FR M S and RES DO to D7 FR AO E or RD R W or WR CS CL M S and RES When DO to D7 and FR are high impedance During continual write acess at a frequency of tcyc Current consumption during access is effectively proportional to the access frequency 9 See figure below for details 10 See figure below for details 11 Fora voltage differential of 0 1 V between input V1 V4 and output COM SEG pins All voltages within specified operating voltage range 12 SEDI520 Ax and SED1521 As and SED1522 A only Does not include transient currents due to stray and panel capacitances 13 SEDI520 0x and SEDI522 0x only Does not include transient currents due to stray and panel capacitances 14 SED1521 0x only Does not include transient currents due to stray and
36. r use by the LCD driver interface circuitry The output of this latch is controlled by the Display ON OFF and Static Drive ON OFF commands LCD Driver Circuit The LCD driver circuitry generates the 80 4 level signals used to drive the LCD panel using output from the display data latch and the common timing generator circuitry XKX 8X9 9 Display Timing Generator This circuit generates the internal display timing signal using the basic clock CL and the frame signals FR FR is used to generate the dual frame AC drive wave form type B drive and to lock the line counter and common timing generator to the system frame rate CL is used to lock the line counter to the system line scan rate If a system uses both SED1520s or SED1522 and SED1521s they must have the same CL frequency rating 2 10 EPSON Oscillator Circuit SED1520 0A Only A low power consumption CR oscillator for adjusting the oscillation frequency using Rf oscillation resistor only This circuit generates a display timing signal Some of SED1520 and SED1522 series models have a built in oscillator and others use an external clock This difference must be checked before use Connect the Rf oscillation resistor as follows To sup press the built in oscillator circuit and drive the MPU using an external clock enter the clock having the same phase as the OSC2 of mater chip into OSC2 of the slave chip MPU having a built in oscillator VDD
37. rse common output scan sequence than the master LSI 1 0 FR signal 1 0 1 0 Counter output V5 v4 Output level 5 Input The master or slave LSI operation select pin for the SED1520 or SED1522 Connected to VDD to select the master LSI operation mode or Vss to select the slave LSI operation mode uu When this M S pin is set the functions of FR COMO to COM15 OSC1 CS and OSC2 CL pins are changed M S FR COM output OSC1 OSC2 VDD Output COMO to COM15 Input Output Vss Input COM31 to COM16 NC Input SED1522F0A VDD Output COMO to COM7 Input Output Vss Input COM15 to COM8 NC Input The slave driver has the reverse common output scan sequence than the master driver EPSON 2 7 7 N T e W 72 SED1520 Series BLOCK DESCRIPTION System Bus MPU interface 1 Selecting an interface type The SED1520 series transfers data via 8 bit bidirec tional data buses DO to D7 As its Reset pin has the MPU interface select function the 80 series MPU or the 68 series MPU can directly be connected to the MPU bus by the selection of high or low RES signal level after reset see Table 1 When the CS signal is high the SED1520 series is disconnected from the MPU bus and set to stand by However the reset signal is entered regardless of the internal setup status Table 1 RES signal input level MPU type AO E R W CS D
38. splay ON OFF command ON OFF 1 Display OFF ON OFF 0 Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode RESET 1 Currently executing reset command RESET 0 Normal operation Write Display Data __ RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 1 1 0 Write data Writes 8 bits of data into the display data RAM at a location specified by the contents of the column address and page address registers and then increments the column address register by one 2 16 EPSON SED1520 Series Read Display Data RW Ao RD WR D7 De D5 D4 D3 D2 D1 Do 1 0 1 Read data Reads 8 bits of data from the data I O latch updates the contents of the I O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register After loading a new address into the column address register one dummy read is required before valid data is obtained 7 N T e W 72 Select ADC Ao RD WR D7 De D5 D4 D3 D2 Di Do 0 1 0 1 0 1 0 0 0 0 D AOH A1H This command selects the relationship between display data RAM column addresses and segment drivers D 1 SEGO lt column address 4FH inverted D 0 SEGO lt column address 0
39. ss 3V 0 2xVss VDD V i ul ve veo See note 2 amp 3 Low level input voltage VER Mis ov Vit Vss 3V Vss 0 85xVss See note 2 amp 3 Vss 3V Vss 0 8xVss loH 3 0mA Vss42 4 0562 loH 2 0 mA Vss42 4 V See note 4 amp 5 High level output voltage VORE on 120 pA QaxVss _ VoHT Vss 3V loH 2 MA 0 2xVss See note 4 amp 5 Vouci Vss 3V lOH 2 mA 0 2xVss V 0567 VoHC2 Vss 3V loH 50 pA 0 2xVss continued 2 20 EPSON SED1520 Series DC Characteristics Cont d Ta 20 to 75 deg C VDD 0 V unless stated otherwise Rating gt Parameter Symbol Condition Min Typ Max Unit Applicable Pin Volt 0 3 0 mA __ Vss 0 4 0SC2 S Voici lol 2 0 mA SNM Sd Es D Low level output voltage U A DM A m P 9 Vss 3V loL22mA 0 8xVss o Voici Vss 3V loL 2 Q 8xVss V 05C2 2 Vss 3V lo 50 pA 0 8xVss Input leakage current IL 1 0 1 0 pA See note 6 Output leakage current ILO 3 0 3 0 uA Seenote 7 V5 5 0V 5 0 1 5 SEGO to 79 LCD driver ON resistance Ron 254 0 6 COMOto 15 V5 3 5V 10 0 50 0 See note 11 Static current dissipation looo CS CL Vpp 0 05 1 0 pA VDD fcL 2 kHz 2 0 5 0 VDD vsccsoy Rema 95 150 p Seenote12 7 18kHz 5 0 10 0 13 amp 14 met During dis
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