ELANsat Tech EM78P156N User's Manual
Contents
1. 6 3 Device Characteristic The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only The device characteristic illustrated herein are not guaranteed for it accuracy In some graphs the data maybe out of the specified warranted operating range Vih Vil Input pins with schmitt inverter Vih max 40 C to 85 C Vih typ 25 C Vih min 40 C to 8 VihWil Volt Vil max 40 C to 85 C Vil typ 25 C Vil min 40 C to 85 C 25 3 35 4 45 5 55 VDD Volt Fig 17 Vih Vil of Port6 vs VDD This specification is subject to change without prior notice 40 07 29 2004 V1 2 M 7 4 T 886 3 5753170 WEE 7 EFEN 86 21 54151736 EM78P156N ER E es 86 755 83298787 Http www 100y com tw OTP ROM Vth Input thershold voltage of I O pins Max 40 C to 85 C Vth Volt Min 40 C to 85 C 25 3 35 4 45 5 55 VDD Volt Fig 18 Vth Threshold voltage of Port5 vs VDD This specification is subject to change without prior notice 41 07 29 2004 V1 2 Wed A oH 4 886 3 5753170 WEAR JJ R CEif 86 21 54151736 WE45 J HL GUI 86 755 83298787 EM78P156N OTP ROM Http www 100y com tw Voh Ioh 5V Voh Ioh 3V Min 85 C loh mA Ioh mA Min 40 C Min 40 C 15 2 25 3 35 4 45 5 Voh Volt Voh Volt Fig2. Me 44 7H 886 3 5753170 Wd JJ H i 86 21 54151736 EM78P156N WEA 7 E FERII 86 755 83298787 OTP ROM Http www 100y com tw EM78P156N 8 BIT MICRO CONTROLLER Version 1 2 EM78P156N OTP ROM Specification Revision History Version Content 1 0 Initial version 1 1 Change Power on reset content 07 01 2003 1 2 Add the Device Characteristic at section 6 3 07 29 2004 Application Note AN 001 EM78P156N v s EM78P156E on the DC Characteristics Ws d 2 A 88635753170 EE JJ HL 86 21 54151736 WEED HR 86 755 83298787 Http www 100y com tw This specification is subject to change without prior notice 2 07 29 2004 V1 2 EM78P156N OTP ROM 1 GENERAL DESCRIPTION EM78P156N is an 8 bit microprocessor designed and developed with low power high speed CMOS technology It is equipped with 1K 13 bits Electrical One Time Programmable Read Only Memory OTP ROM It provides three PROTECTION bits to prevent user s code in the OTP memory from being intruded 8 OPTION bits are also available to meet user s requirements With its OTP ROM feature the EM78P156N is able to offer a convenient way of developing and verifying user s programs Moreover user can take advantage of EMC Writer to easily program his development code te ae H oH 886 3 5753170 WERE HA f Eif 86 21 54151736 Wi 7J HA EI 86 755 83298787 Http www 100y com tw This specific
3. cu u cu fu oo fo o mesetandwor u u u u u o o o Wake Up from Pin Charge u u U U u P P P Beare SO IE E eset srawor e pepe pete pe tele Wake Up from Pin Charge P P P ep p Pe Pe P To jump address 0x08 or to execute the instruction which is next to the SLEP instruction X Not used U Unknown or don t care P Previous value before reset t Check Table 4 2 The Status of RST T and P of STATUS Register A RESET condition is initiated by the following events This specification is subject to change without prior notice 23 07 29 2004 V1 2 WE 4 7H 886 3 5753170 MEJ HL ie 86 21 54151736 WEA 7 FREYI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 1 A power on condition 2 A high low high pulse on RESET pin and 3 Watchdog timer time out The values of T and P listed in Table 4 are used to check how the processor wakes up Table 5 shows the events that may affect the status of T and P Table 6 The Values of RST T and P after RESET Reset Type S Te PW RESET during Operating mode VRESET wake up during SLEEP mde 1 0 WDT during Operatingmode 0 P WDT wake up during SLEEP mode 0 0 Wake Up on pin change during SLEEP mode 1 0 P Previous status before reset Table 7 The Status of T and P Being Affected by Events La eo OES WOTG instruction ARCEN PYA
4. 100y com tw Four conditions exist with the Operating Current ICC1 to ICC4 These conditions are as follows ICC1 VDD 3V Fosc 32K Hz 2 clocks WDT disable ICC2 VDD 3V Fosc 32K Hz 2 clocks WDT enable ICC3 VDD 5V Fosc 4M Hz 2 clocks WDT enable ICC4 VDD 5V Fosc 10M Hz 2 clocks WDT enable Typical ICC1 and ICC2 vs Temperature Typ ICC2 Current uA o w o v BG Temperature C Fig 26 Typical operating current ICC1 and ICC2 vs Temperature Maximum ICC1 and ICC2 vs Temperature 21 Curert uA o v Hk i Fig 27 Maximum operating current ICC1 and ICC2 vs Temperature This specification is subject to change without prior notice 46 07 29 2004 V1 2 Bed 4 oH f 886 3 5753170 VERE ETUE 86 21 54151736 WEF I E Y GHI 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM Typical ICC3 and ICC4 vs Temperature 3 5 25 E Typ ICC3 E 15 yp Q 1 0 5 0 40 20 0 20 40 60 80 Tarperdure C Fig 28 Typical operating current ICC3 and ICC4 vs Temperature Maximum ICC3 and ICC4 vs Temperature Current mA N w N U UJ U O amp Temperature C Fig 29 Maximum operating current ICC3 and ICC4 vs Temperature This specification is subject to change without prior notice 47 07 29 2004 V1 2 Wed OZ oH 4 886 3 5753170 n k A i i MEN Jy E FLEW
5. 65 C 15mins 150 C 15mins 10 cycles For SMD IC such as SOPO QFP SOJ etc Step2 bake 125 C TD durance 24 hrs Step3 soak 30 C 60 TD durance 192hrs btep4 IR flow 3cycles Pkg thicknessz 2 5mm or Pkg volumez 350mm 225 5 C Pkg thicknesss 2 5mm or Pkg volumes 350mm 240 5 C Temperature cycle test 65 C 15mins 150 C 15mins 200 cycles T4 121 C RH 100 pressure 2atm TD durance 96 Hrs wt High temperature highlT4A 85 C RH 85 TD durance 168 500 Hrs humidity test High temperature TA 150 C TD durance 500 1000Hrs DENM Pressure cooker test High temperature TA 125 C VCC Max operating voltage TD durance 168 500 1000Hrs TA 25 C VCC Max operating voltage 150mA 20V storage life operating life Latch up m ie 0 TA 25 C 33KV IP_ND OP_ND IO_ND IP_NS OP_NS IO_NS TA 25 C 300V IP_PD OP_PD IO_PD IP PS OP PS O PS VDD VSS VDD_VSS mode m CD I This specification is subject to change without prior notice 56 07 29 2004 V1 2 We OZ oH 8 886 3 5753170 Wi JJ H i 86 21 54151736 WE ey PREI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM gt Internal Tvd DOR Parameter Condition Power on reset time Vdd 5V 40 C to 85 C Tvd Vdd Voltage drop time Vdd 5V 40 C to 85 C hooey co tt EY Tvr M dVoegersetime
6. SLEP instruction Wake Up on pin change during SLEEP mode aa et a P Previous value before reset Oscillator Power on Reset Voltage Detector WDTE WDT WDT Timeoitt A Setup Time 9 RESET LA RESET LN Fig 9 Block Diagram of Controller Reset This specification is subject to change without prior notice 24 07 29 2004 V1 2 Med ZH 886 3 5753170 WERE JJ EFEN 86 21 54151736 EM78P156N Ji d JH HL 3I 86 755 83298787 OTP ROM Http www 100y com tw 4 6 Interrupt The EM78P156N has three falling edge interrupts listed below 1 TCC overflow interrupt 2 Port 6 Input Status Change Interrupt 3 External interrupt P60 INT pin Before the Port 6 Input Status Change Interrupt is enabled reading Port 6 e g MOV R6 R6 is necessary Each pin of Port 6 will have this feature if its status changed Any pin configured as output or P60 pin configured as INT is excluded from this function The Port 6 Input Status Changed Interrupt can wake up the EM78P156N from the sleep mode if Port 6 is enabled prior to going into the sleep mode by executing SLEP When the chip wakes up the controller will continue to execute the succeeding address if the global interrupt is disabled or branch to the interrupt vector 008H if the global interrupt is enabled RF is the interrupt status register that records the interrupt requests in the relative flags bits IOCF is an interrupt
7. ops OD2 ODi opo Bit 0 ODO Control bit is used to enable the open drain of P60 pin 0 Disable open drain output 1 Enable open drain output Bit 1 OD1 Control bit is used to enable the open drain of P61 pin Bit 2 OD2 Control bit is used to enable the open drain of P62 pin Bit 3 OD3 Control bit is used to enable the open drain of P63 pin Bit 4 OD4 Control bit is used to enable the open drain of P64 pin This specification is subject to change without prior notice 13 07 29 2004 V1 2 hie 4 H 4 4 886 3 5753170 WERE A EFEX 86 21 54151736 ERE I H FREJ 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw Bit 5 OD5 Control bit is used to enable the open drain of P65 pin Bit 6 OD6 Control bit is used to enable the open drain of P66 pin Bit 7 OD7 Control bit is used to enable the open drain of P67 pin OCC Register is both readable and writable 7 IOCD Pull high Control Register Bit 0 PHO Control bit is used to enable the pull high of P60 pin 0 Enable internal pull high 1 Disable internal pull high Bit 1 PH1 Control bit is used to enable the pull high of P61 pin Bit 2 PH2 Control bit is used to enable the pull high of P62 pin Bit 3 PH3 Control bit is used to enable the pull high of P63 pin Bit 4 PH4 Control bit is used to enable the pull high of P64 pin Bit 5 PH5 Control bit is used to enable the pull high of P65 pin Bit
8. 0110 OOrr rrrr RRCA R R 0 gt C C gt A 7 0 R n gt R n 1 0 0110 Oir rrr O6rr RRG R R 0 gt C C gt R 7 0110 10rr_rrrr RLCA R R n gt A n 1 C This specification is subject to change without prior notice 34 07 29 2004 V1 2 ME OZ oH d 886 3 5753170 WERE JJ CES 86 21 54151736 WE 7J HA 3I 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM e a n gt R n 1 0O 0110 1irr rrrr RLC R ae C 5 R 0 BETON TA gt A 4 7 0 0111 OOrr rrr SWAPA R R 4 7 gt A 0 3 R 0 3 lt gt R 4 7 PC 1 gt SP Page k gt PC Nong 1 OOkk kkkk kkkk 1kkk CALL k kA 1 1100 kkkk kkkk Top of Stack 2 PC 1 1101 kkkk kkkk 1Dkk SUB AK Z C DC PC 1 gt SP 1 1111 kkkk kkkk 1Fkk ADD A k Z C DC Note 1 This instruction is applicable to IOC5 1OC6 IOCB IOCF only Note 2 This instruction is not recommended for RF operation Note 3 This instruction cannot operate under RF This specification is subject to change without prior notice 35 07 29 2004 V1 2 he d H oH 886 3 5753170 WER HL 86 21 54151736 AE 7J Ha ZRH 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 4 13 Timing Diagrams AC Test Input Output Waveform 2 4 2 0 TEST POINTS 4 0 8 NZ on 0 4 AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timing measurements are made at 2 0V for logic 1 and 0 8V for logic
9. 6 PH6 Control bit is used to enable the pull high of P66 pin Bit 7 PH7 Control bit is used to enable the pull high of P67 pin OCD Register is both readable and writable 8 IOCE WDT Control Register WDTE EIS 4NN 7 ICOROC a 7 WW COP VN o x Bit 7 WDTE Control bit used to enable Watchdog timer 0 Disable WDT 1 Enable WDT WDTE is both readable and writable Bit 6 EIS Control bit is used to define the function of P60 INT pin 0 P60 bi directional I O pin 1 INT external interrupt pin In this case the I O control bit of P60 bit 0 of IOC6 must be set to uu When EIS is O the path of INT is masked When EIS is 1 the status of INT pin can also be read by way of reading Port 6 R6 Refer to Fig 7 a EIS is both readable and writable Bit 4 ROC ROC is used for the R option This specification is subject to change without prior notice 14 07 29 2004 V1 2 ER OZ oH 886 3 5753170 WE 7 HL 86 21 54151736 ERE 7J HAF VE HI 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw Setting the ROC to 1 will enable the status of R option pins P50 P51 that are read by the controller Clearing the ROC will disable the R option function If the R option function is selected user must connect the P51 pin or and P50 pin to VSS with a 430KQ external resistor Rex If the Rex is connected disconnected the status of P50 P51 is read as 0 1 Refer to Fig 8
10. Bits 0 3 5 Not used 9 IOCF Interrupt Mask Register NU ANY pm s Vu JOO MEX ICE a CIE c Bit 0 TCIE TCIF interrupt enable bit 0 disable TCIF interrupt 1 enable TCIF interrupt Bit 1 ICIE ICIF interrupt enable bit 0 disable ICIF interrupt 1 enable ICIF interrupt Bit 2 EXIE EXIF interrupt enable bit 0 disable EXIF interrupt 1 enable EXIF interrupt Bits 3 7 Not used Individual interrupt is enabled by setting its associated control bit in the IOCF to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Refer to Fig 10 OCF register is both readable and writable 4 3 TCC WDT amp Prescaler An 8 bit counter available as prescaler for the TCC or WDT The prescaler is available for either the TCC or WDT only at any given time and the PAB bit of the CONT register is used to determine the prescaler assignment The PSRO PSR2 bits determine the ratio The prescaler is cleared each time the instruction is written to TCC under TCC mode The WDT and prescaler when assigned to WDT mode are cleared by the WDTC or SLEP instructions Fig 5 depicts the circuit diagram of TCC WDT R1 TCC is an 8 bit timer counter The clock source of TCC can be internal or external clock input edge selectable from TCC pin If TCC signal source is from internal clock TCC will increase by 1 at every instruction cycle without prescaler Referring to Fig 5 CLK Fosc 2 or CLK
11. Fosc 4 application is determined by the CODE Option bit CLK status CLK Fosc 2 is used if CLK bit is 0 and This specification is subject to change without prior notice 15 07 29 2004 V1 2 he d H oH 886 3 5753170 WEJ He 86 21 54151736 WEE Dy V EN 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM CLK Fosc 4 is used if CLK bit is 1 If TCC signal source comes from external clock input TCC is increased by 1 at every falling edge or rising edge of TCC pin The watchdog timer is a free running on chip RC oscillator The WDT will keep on running even when the oscillator driver has been turned off i e in sleep mode During normal operation or sleep mode a WDT time out if enabled will cause the device to reset The WDT can be enabled or disabled any time during normal mode by software programming Refer to WDTE bit of IOCE register Without prescaler the WDT time out period is approximately 18 ms default CLK Fosc 2 or Fosc 4 Data Bus 0 Y TCC gt M Pin 5 U L SYNC J TCC RI 2 cycles x TE TS TCC overflow interrupt p IOCA WTE 4 in IOCE PAB 8 to 1 MUX PAB Initial value PSR0 PSR2 MUX PAB 8 bit Counter cs gt WDT time out Fig 5 Block Diagram of TCC and WDT 4 4 I O Ports The I O registers both Port 5 and Port 6 are bi
12. ICC3 VDD 5 0V Crystal type CLKS 0 output 2 0 mA at two cycles two clocks pin floating WDT enabled Operating supply current RESET High Fosc 10MHz ICC4 VDD 5 0V Crystal type CLKS 0 output 4 0 mA at two cycles four clocks pin floating WDT enabled These parameters are characterizes but not tested s nm P m P VOH1 IOH 12 0 mA e EN E d This specification is subject to change without prior notice 38 07 29 2004 V1 2 Bod H oH 4 886 3 5753170 ERED HE 86 21 54151736 PEH PRII 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 6 2 AC Electrical Characteristic Ta 25 C VDD 5V 5 VSS 0V Symbol Parameter Conditions Min Typ Max Unit Ddk Input CLK duty cyce 4 amp 5 55 Tins Instruction cycle time Cystaliype 10 be ns CLKS 0 RC type 500 ns TCC input period pa Tins 20 N aw ee Device reset hold time ue 16e 28 ome RESET pulse width Ta ae 2000 CST scam Watchdog timer period DE 25 C Ls pes za Lm Input pin setup time tns Thold Input pin hold time Tdelay Output pin delay time Cload 20pF ror a La os C N selected prescaler ratio These parameters are characterizes but not tested This specification is subject to change without prior notice 39 07 29 2004 V1 2 Me d 2 oH 886 3 5753170 WEAR H i 86 21 54151736 WEED HL FRI 86 755 83298787 EM78P156N OTP ROM Http www 100y com tw
13. SSOP 209mil EM78P156NAS This specification is subject to change without prior notice 4 07 29 2004 V1 2 EM78P156N OTP ROM 20 pin SSOP 209mil EM78P156NKM 99 9 single instruction cycle commands The transient point of system frequency between HXT and LXT is around 400KHz te 44 7M 4 886 3 5753170 Ji 7 ETUE 86 21 54151736 WE 45 r amp GUI 86 755 83298787 Http www 100y com tw This specification is subject to change without prior notice 5 07 29 2004 V1 2 te d H oH 886 3 5753170 WERT HLA C 86 21 54151736 ERE i RI 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw 3 PIN ASSIGNMENTS ps2 m 18 ps3 2 17 TCC 8 16 RESET 4 Z Z 15 Vss SANES E 14 POINT 6 13 pu 7 12 P62 8 T P63 9 10 P51 P50 OSCI OSCO VDD P67 P66 P65 P64 NC 1 w 20 NC P52 1 w 20 P51 P52 2 19 P51 P53 2 19 P50 P53 3 18 P50 TCC 3 18 OSCI TCC 4 z 17 OSCI RESET 4 S 17 OSCO RESET 5 5 16 osco vs s 58 16 VDD Vss 6 3 15 VDD Vss 6 3 15 VDD P60 INT 7 B a P67 P60 INT 7 2 14 P67 P61 8 13 P66 P61 8 13 P66 P62 9
14. circuit The same thing applies whether it is in the HXT mode or in the LXT mode Table 8 provides the recommended values of C1 and C2 Since each resonator has its own attribute user should refer to its specification for appropriate values of C1 and C2 RS a serial resistor may be necessary for AT strip cut crystal or low frequency mode C1 OSCI EM78P156N XTAL EI OSCO W V RS C2 Fig 12 Circuit for Crystal Resonator This specification is subject to change without prior notice 27 07 29 2004 V1 2 he ae H oH 886 3 5753170 EAE JJ HL _ ff 86 21 54151736 HER J HL es 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode C1 pF C2 pF 455 kHz 100 150 100 150 Ceramic Resonators HXT 2 0 MHz 20 40 20 40 LXT 4 0 MHz 10 30 10 30 32 768kHz 25 25 Crystal Oscillator 4 0MHz lt Note gt 1 The value of capacitors C1 C2 is for reference 3 External RC Oscillator Mode For some applications that do not need a very precise timing calculation the RC oscillator Fig 15 offers a lot of cost savings Nevertheless it should be noted that the frequency of the RC oscillator is influenced by the supply voltage the values of the resistor Rext the capacitor Cext and even by the operation temperature Moreover the frequency also changes slight
15. is considered the continuation of program execution and the global interrupt ENI or DISI being executed decides whether or not the controller branches to the interrupt 1 NOTE Vdd 5V set up time period 16 8ms 30 Vdd 3V set up time period 18ms 30 This specification is subject to change without prior notice 20 07 29 2004 V1 2 te 44 4 4 4 886 3 5753170 MEJI TR CEif 86 21 54151736 ERED HA Y GI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM vector following wake up If ENI is executed before SLEP the instruction will begin to execute from the address 008H after wake up If DISI is executed before SLEP the operation will restart from the succeeding instruction right next to SLEP after wake up Only one of Cases 2 and 3 can be enabled before entering the sleep mode That is a if Port 6 Input Status Change Interrupt is enabled before SLEP WDT must be disabled by software However the WDT bit in the option register remains enabled Hence the EM78P156N can be awakened only by Case 1 or 3 b if WDT is enabled before SLEP Port 6 Input Status Change Interrupt must be disabled Hence the EM78P156N can be awakened only by Case 1 or 2 Refer to the section on Interrupt If Port 6 Input Status Change Interrupt is used to wake up the EM78P156N Case a above the following instructions must be executed before SLEP MOV A 2xx0001 10b Select internal TCC clock CONTW CLR R1 Cle
16. mask register The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction When one of the interrupts enabled occurs the next instruction will be fetched from address 008H Once in the interrupt service routine the source of an interrupt can be determined by polling the flag bits in RF The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts The flag except ICIF bit in the Interrupt Status Register RF is set regardless of the status of its mask bit or the execution of ENI Note that the outcome of RF will be the logic AND of RF and IOCF refer to Fig 10 The RETI instruction ends the interrupt routine and enables the global interrupt the execution of ENI When an interrupt is generated by the INT instruction enabled the next instruction will be fetched from address 001H This specification is subject to change without prior notice 25 07 29 2004 V1 2 BR H oH 886 3 5753170 WEA f Cit 86 21 54151736 EM78P156N WE 45 HL GH 86 755 83298787 OTP ROM Http www 100y com tw vcc p R o N ad IRQn i IRQn cyp CLK 4 Ww X INT c a RFRD IROm RF e LA ENI DISI Q R D IOD 4 cO crwR rocr 9 E RESET d a IOCFRD RFWR Fig 10 Interrupt Input Circuit 4 7 Oscillator 1 Oscillator Modes The EM78P156N can be operated in t
17. 0 RESET Timing CLK 0 Instruction 1 NOP Executed Sik NY hoi RESET A Tdh ____p TCC Input Timing CLKS 0 lt Tins CLK M N Va TCC e zd m Ttcc This specification is subject to change without prior notice 36 07 29 2004 V1 2 Http te 4 H oH FH 886 3 5753170 ER ETUER 86 21 54151736 ERED FA GJI 86 755 83298787 www 100y com tw 5 ABSOLUTE MAXIMUNM RATINGS EM78P156N EM78P156N OTP ROM Items Rating Temperature under bias 40 C to 85 C Storage temperature 65 C to 150 C Working voltage 2 5 to 5 5V Working frequency DC to 20MHz Input voltage Vss 0 3V to Vdd 0 5V Output voltage Vss 0 3V to Vdd 0 5V These parameters are characterized but not tested This specification is subject to change without prior notice 37 07 29 2004 V1 2 We d 7 At T 886 3 5753170 Wd HA ie 86 21 54151736 HEKE 7 B TREI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 6 ELECTRICAL CHARACTERISTICS 6 1 DC Electrical Characteristic Ta 25 C VDD 5V 5 VSS 0V Symbol Parameter Condition Min Typ Max Unit eT fA ie tamale i two cocs f De Bo T Med XTALVDDio5V Twocydewihtwocloks DC 200 MHz IIL Input Leakage Current for input pins VIN VDD VSS pA VIHT I
18. 1 KHz 20 KHz Note 1 Measured on DIP packages 2 For design reference only 3 The frequency drift is about 430 4 8 CODE Option Register The EM78P156N has a CODE option word that is not a part of the normal program memory The option bits cannot be accessed during normal program execution Code Option Register and Customer ID Register arrangement distribution This specification is subject to change without prior notice 29 07 29 2004 V1 2 BR OZ OH 886 3 5753170 ERJ ETLN 86 21 54151736 WEE 7 i PREI 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM Word 0 Word 1 Bit12 BitO Bit12 BitO 1 Code Option Register Word 0 Bit 12 11 10 9 Not used Reserved The bit set to 1 all the time Bit 8 CLKS Instruction period option bit 0 two oscillator periods 1 four oscillator periods Refer to the section on Instruction Set Bit 7 ENWDTB Watchdog timer enable bit 0 Enable 1 Disable Bit 6 Not used Reserved The bit set to 1 all the time Bit 5 HLF XTAL frequency selection 0 XTAL2 type low frequency 32 768KHz 1 XTAL1 type high frequency This bit will affect system oscillation only when Bit4 OSC is 1 When OSC is 0 HLF must be 0 Note The transient point of system frequency between HXT and LXY is around 400 KHz Bit 4 OSC Oscillator type selection 0 RC type 1 XTAL type XTAL1 and XTAL2 B
19. 12 P65 P62 9 12 P65 P63 10 11 P64 P63 10 11 P64 Fig 1 Pin Assignment Table 1 EM78P156NP and EM78P156NM Pin Description Symbol MDD 14 Power supply P60 P67 6 13 O XTAL type Crystal input terminal or external clock input pin ERC type RC oscillator input pin XTAL type Output terminal for crystal oscillator or external clock input pin RC type Instruction clock output External clock signal input The real time clock counter with Schmitt trigger input pin must be tied to VDD or VSS if not in use Input pin with Schmitt trigger If this pin remains at logic low the controller will also remain in reset condition P50 P53 are bi directional I O pins P50 and P51 can also be defined as the R option pins P50 P52 can be pulled down by software P60 P67 are bi directional I O pins These can be pulled high or can be open drain by software programming P60 P63 can also be pulled down by software INT 6 External interrupt pin triggered by falling edge MSS 5 Grid TN FS This specification is subject to change without prior notice 6 07 29 2004 V1 2 Med oZ oH 886 3 5753170 HEJ Vi Y CE 86 21 54151736 EM78P156N WERE E YEH 86 755 83298787 OTP ROM Http www 100y com tw Symbol MBBS 1508 lPowere Bp COUP eg ee WY CO ow XTAL type Crystal input terminal or external clock input p
20. 19 Port5 and Port6 Voh vs loh VDD 5V Fig 20 Port5 and Port6 Voh vs loh VDD 3V Ws 44 H A 4 886 3 5753170 WERE EPLE 86 21 54151736 EM78P156N MEJI VR TREY 86 755 83298787 TE 5 7 HEL a OTP ROM Http www 100y com tw Vol lol 5V Vol lol 3V lol mA Vd Val Vol Vd Fig 21 Port5 Port6 Vol vs lol VDD 5V Fig 22 Port5 Port6 Vol vs lol VDD 3V This specification is subject to change without prior notice 43 07 29 2004 V1 2 Wed ZH 4 886 3 5753170 WERE JJ HL 86 21 54151736 Wee Hy t Rs 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM WDT Time out Max 85 C Typ 25 C WDT period 6 CUm ioc C Min 40 C VDD Volt Fig 23 WDT time out period vs VDD perscaler set to 1 1 te 44 4 4 4 886 3 5753170 id CE MEJ H i 86 21 54151736 EMTBP156N WERE ID Hf ey 86 755 83298787 Http www 100y com tw OTP ROM VDD Vat Fig 24 Typical RC OSC Frequency vs VDD Cext 100pF Temperature at 25 C ERC OSC Frequency vs Temp Cext 100pF Rext 5 1K F a 8 E Temperature C Fig 25 Typical RC OSC Frequency vs VDD R and C are ideal components This specification is subject to change without prior notice 45 07 29 2004 V1 2 ie 4 A 4 4 886 3 5753170 Ji 7 Hi Y Eif 86 21 54151736 EM78P156N WE 45 HAGE 86 755 83298787 OTP ROM Http www
21. 6 21 54151736 EM78P156N Ji Ha HI 86 755 83298787 Http www 100y com tw OTP ROM Two conditions exist with the Standby Current ISB1 and ISB2 These conditions are as follows ISB1 VDD 5V WDT disable ISB2 VDD 5V WDT enable Typical ISB1 and ISB2 vs Temperature 12 10 lt 8 2 2 6 5 H 5 S Typ ISB1 O 2 L aN aAA C ANN DAN 1 0 40 20 0 20 40 60 80 Temperature C Fig 30 Typical standby current ISB1 and ISB2 vs Temperature Maximum ISB1 and ISB2 vs Temperature 12 p e o 3 8 z 6 A Max ISB1 O 2 gp LN aae NN uL NN Lal 40 20 0 20 40 60 80 Temperature C Fig 31 Maximum standby current ISB1 and ISB2 vs Temperature This specification is subject to change without prior notice 48 07 29 2004 V1 2 Wed AH 4 886 3 5753170 MEJI Vl E3t 86 21 54151736 WE 453 H PREY 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM Operating voltage 0 C 70T Frequency M Hz 35 4 VDD Volt Fig 32 Operating voltage in temperature range from 0 C to 70 C Operating voltage 40 C 85T Frequency M Hz 35 4 4 5 VDD Volt Fig 33 Operating voltage in temperature range from 40 C to 85 C This specification is subject to change without prior notice 49 07 29 2004 V1 2 Wed oZ oH 5 886 3 5753170 WEAR JJ HAL 86 21 54151736 EM78P156N WEE 7 HL EI 86 755 83298787 OTP ROM Http www 100y com tw EM78P156N
22. J HXT V I 25 225 175 15 125 0 75 05 025 23 28 33 38 43 48 53 Voltage V Fig 34 Operating current range based on high Freq 225 C vs Voltage EM78P156N J LXT V I 35 30 25 20 3 B 10 5 0 23 28 33 38 43 48 53 Voltage Fig 35 Operating current range based on low Freq 25 C vs Voltage This specification is subject to change without prior notice 50 07 29 2004 V1 2 he dt H oH d 886 3 5753170 WERE HL 86 21 54151736 WEE I HR 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM EM78P156N G HXT V I 25 2 25 175 15 125 075 05 025 23 28 33 38 43 48 53 Voltage Fig 36 Operating current range based on high Freq 25 C vs Voltage EM78P156N G LXT V I 40 35 30 25 x g 15 10 5 0 23 28 33 38 43 48 53 VoltageV Fig 37 Operating current range based on high Freq 25 C vs Voltage This specification is subject to change without prior notice 51 07 29 2004 V1 2 EM78P156N OTP ROM APPENDIX Package Types OTP MCU Package Type Pin Count Package Size EM78P156NP DIP 18 300 mil EM78P156NM SOP 300 mil EM78156NAS SSOP 209 mil EM78156NKM SSOP 209 mil We 4 2 4 4 886 3 5753170 HEJJ Vl Y E9f 86 21 54151736 Wd I HE WEI 86 755 83298787 Http www 100y com tw This specification is subj
23. LK Fosc 4 instead of Fosc 2 as indicated in Fig 5 In addition the instruction set has the following features 1 Every bit of any register can be set cleared or tested directly This specification is subject to change without prior notice 33 07 29 2004 V1 2 Med oZ oH 886 3 5753170 WE JJ R Eit 86 21 54151736 WEA JJ PRRI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 2 The I O register can be regarded as general register That is the same instruction can operate on I O register The symbol R represents a register designator that specifies which one of the registers including operational registers and general purpose registers is to be utilized by the instruction b represents a bit field designator that selects the value for the bit which is located in the register R and affects operation k represents an 8 or 10 bit constant or literal value TP o 0000 0001 0000 0010 ENI Enabelnerp amp None 0 0000 0001 0011 0013 RETI Top of Stack PC Enable Interrupt 0 0000 0001 rr ootr IORR IOCR2A None lt Notet gt O 0010 00r rrr 02r ORAR AvR gt A OZ 0 0010 Oirr mr 02r ORRA AvR gt R 7 O 0010 f r mr 02r ANDAR A amp R gt A 7 Z C DC Z C DC Z Z 0101 10rr rrr DJZA R R 1 A skip if zero None 0101 tir rrr DJZ R R 1 5 R skip if zero None R n gt A n 1 0
24. M78P156N OTP ROM Http www 100y com tw Vdd e Vdd EM78P156N RI 40K R2 gt Fig 16 Circuit 2 for the Residue Voltage Protection 4 12 Instruction Set Each instruction in the instruction set is a 13 bit word divided into an OP code and one or more operands Normally all instructions are executed within one single instruction cycle one instruction consists of 2 oscillator periods unless the program counter is changed by instruction MOV R2 A ADD R2 A or by instructions of arithmetic or logic operation on R2 e g SUB R2 A BS C R2 6 CLR R2 In this case the execution takes two instruction cycles If for some reasons the specification of the instruction cycle is not suitable for certain applications try modifying the instruction as follows A Change one instruction cycle to consist of 4 oscillator periods B JMP CALL RET RETL RETI or the conditional skip JBS JBC JZ JZA DJZ DJZA commands which were tested to be true are executed within two instruction cycles The instructions that are written to the program counter also take two instruction cycles Case A is selected by the CODE Option bit called CLK One instruction cycle consists of two oscillator clocks if CLK is low and four oscillator clocks if CLK is high Note that once the 4 oscillator periods within one instruction cycle is selected as in Case A the internal clock source to TCC should be C
25. Vad 5v 40 ctoesrc T Tvdis the period of Vdd voltage less than POR voltage Tvr is the period of Vdd voltage higher than 5 5 volts Address Trap Detect An address trap detect is one of the fail safe function that detects CPU malfunction caused by noise or the like If the CPU attempts to fetch an instruction from a part of RAM an internal recovery circuit will auto started Until CPU got the correct function it will execute the following program This specification is subject to change without prior notice 57 07 29 2004 V1 2
26. Vdd to reached minimum operation voltage This circuit is used when the power supply has slow rise time Because the current leakage from the RESET pin is about 5yA it is recommended that R should not be greater than 40 K In this way the RESET pin voltage is held below 0 2V The diode D acts as a short circuit at the moment of power down The capacitor C will discharge rapidly and fully Rin the current limited resistor will prevent high current or ESD electrostatic discharge from flowing to pin RESET This specification is subject to change without prior notice 31 07 29 2004 V1 2 te d A oH 886 3 5753170 WEE HLSW 86 21 54151736 WEE 7 H PRRI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM EM78P156N Rin Fig 14 External Power Up Reset Circuit 4 11 Residue Voltage Protection When battery is replaced device power Vdd is taken off but residue voltage remains The residue voltage may trips below Vdd minimum but not to zero This condition may cause a poor power on reset Fig 18 and Fig 19 show how to build a residue voltage protection circuit e Vdd 33K EM78P156N A AN Q1 3b SN 196 s RESET VV Va ANNE 1N4684 7 Fig 15 Circuit 1 for the Residue Voltage Protection This specification is subject to change without prior notice 32 07 29 2004 V1 2 he d H oH 886 3 5753170 HEJ H i 86 21 54151736 MEt JI E FREYI 86 755 83298787 E
27. WR PDRD Fig 6 The Circuit of I O Port and I O Control Register for Port 5 0 INT PCRD mae mu mae e c x PDRD D LK PCWR PDWR T10 NOTE Pull high down and Open drain are not shown in the figure Fig 7 a The Circuit of I O Port and I O Control Register for P60 INT This specification is subject to change without prior notice 17 07 29 2004 V1 2 WE ZH 886 3 5753170 WE 7 HAE 86 21 54151736 EM78P156N WERE 7J E PREY 86 755 83298787 OTP ROM Http www 100y com tw PCRD D E CLK PCWR C P61 P67 c lt PORT gt a oR D n top CLK PDWR e v 0 gt M 1 U T x l TIN gt PDRD E P le D R Q gt CLK 4 L 9 NOTE Pull high down and Open drain are not shown in the figure Fig 7 b The Circuit of I O Port and I O Control Register for P61 P67 IOCE 1 D i Q N gt CLK k Interrupt t9 o RE 1 ENI Instruction Tio gt DRO TH S P Ew A CLK Q RD 9 i Q CLK P Q t TI7 gt T DISI Instruction EN N Interrupt fi Wake up from SLEEP ISLEP gt E Next Instruction Wake up from SLEEP Fig 7 c Block Diagram of I O Port 6 with Input Change Interrupt Wake up This specification is subject to change without prior notice 18 07 29 2004 V1 2 Ws dZ 886 3 5753170 WERE A ETUE 86 21 54151736 EM78P156N WE 7J E VI 86 755 83298787 OTP ROM Http www 100y com
28. ar TCC and prescaler MOV A xxxx1110b Select WDT prescaler CONTW WDTC Clear WDT and prescaler MOV A 0xxxxxxxb Disable WDT IOW RE MOV R6 R6 Read Port 6 MOV A 00000x1xb Enable Port 6 input change interrupt IOW RF ENI or DISI Enable or disable global interrupt SLEP Sleep NOP One problem user should be aware of is that after waking up from the sleep mode WDT would enable automatically The WDT operation being enabled or disabled should be handled appropriately by software after waking up from the sleep mode This specification is subject to change without prior notice 21 07 29 2004 V1 2 te 4 2 4 4 886 3 5753170 WEED H i 86 21 54151736 WERE 7 HAL EH 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM BtName X X X X 65 65 65 650 Lp iN Poweron NN Lo U eU u NISL an Lt MC T end WORN gf suet OY WY S SR ACT Wake Yng from Pin Change Leo Porn fa po 1 asser aO RESET and WDT ESen NE 5 5 ete Pe tee BiNam x NT TS TE PAB PSR2 PST PSRO Bw 3 fo f t fs LE E d mesTadwoT 1 0 1 1 t tj Wake Up fromPinChange P P P P Pp Pp Pe Pp er reser ree er er RESET and WDT Wake pl from Pin Change 0x03 PaO Lao 9 4 eee T z w5 c NY Ww uv u IR pu bases aei ron PER OTT TEL OE LRP RR eg Poweron o o o o u u uu u iu api WE o ve
29. ation is subject to change without prior notice 3 07 29 2004 V1 2 he 44 A A 886 3 5753170 WERE HLA C 86 21 54151736 EM78P156N WE45 JJ PEEHI 86 755 83298787 OTP ROM Http www 100y com tw 2 FEATURES Operating voltage range 2 5V 5 5V Operating temperature range 40 C 85 C Operating frequency rang base on 2 clocks Crystal mode DC 20MHz at 5V DC 8MHz at 3V DC 4MHz at 2 5V ERC mode DC 4MHz at 5V DC 4MHz at 3V DC 4MHz at 2 5V Low power consumption Less then 2 mA at 5V 4MHz Typically 20 uA at 3V 32KHz Typically 1 pA during sleep mode 1K x 13 bits on chip ROM One security register to prevent intrusion of OTP memory codes One configuration register to accommodate user s requirements 48x 8 bits on chip registers SRAM general purpose register 2 bi directional I O ports 5 level stacks for subroutine nesting 8 bit real time clock counter TCC with selective signal sources trigger edges and overflow interrupt Two clocks per instruction cycle Power down SLEEP mode Three available interruptions TCC overflow interrupt Input port status changed interrupt wake up from sleep mode External interrupt Programmable free running watchdog timer 8 programmable pull high pins 7 programmable pull down pins 8 programmable open drain pins 2 programmable R option pins Package types 18 pin DIP 300mil EM78P156NP 18 pin SOP 300mil EM78P156NM 20 pin
30. directional tri state I O ports Port 6 can be pulled high internally by software In addition Port 6 can also have open drain output by software Input status change interrupt or wake up function on Port 6 P50 P52 and P60 P63 pins can be pulled down by software Each I O pin can be defined as input or output pin by the I O control register IOC5 IOC6 P50 P51 are the R option pins enabled by setting the ROC bit in the IOCE register to 1 When the Note Vdd 5V set up time period 16 8ms 3096 Vdd 3V set up time period 18ms 30 This specification is subject to change without prior notice 16 07 29 2004 V1 2 WR OZ oH 4 886 3 5753170 WERE HL 86 21 54151736 WE 7J PREY 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM R option function is used it is recommended that P50 P51 are used as output pins When R option is in enable state P50 P51 must be programmed as input pins Under R option mode the current power consumption by Rex should be taken into the consideration to promote energy conservation The I O registers and I O control registers are both readable and writable The I O interface circuits for Port 5 and Port 6 are shown in the following Figures 6 7 a 7 b and Figure 8 PORT P6 lt PORT gt I abi f N A D ho peng 1 p Nr 4 PCRD PCWR NOTE Pull down is not shown in the figure Kaz PD
31. ect to change without prior notice 10 07 29 2004 V1 2 M oZ oH 4 886 3 5753170 Wd JJ ETUER 86 21 54151736 Wi 7J i HEI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 4 R3 Status Register LAwPUM SN l ONT a 2V C Lu y Ne Para CP GR GPN ov LPYW z WT DON QUYY Bit 0 C Carry flag Bit 1 DC Auxiliary carry flag Bit 2 Z Zero flag Set to 1 if the result of an arithmetic or logic operation is zero Bit 3 P Power down bit Set to 1 during power on or by a WDTC command and reset to 0 by a SLEP command Bit 4 T Time out bit Set to 1 with the SLEP and WDTC commands or during power up and reset to 0 by WDT time out Bits 7 GPO 2 General purpose read write bits 5 R4 RAM Select Register Bits 0 5 are used to select registers address 00 06 OF 3F in the indirect addressing mode Bits 6 7 are not used read only The Bits 6 7 set to 1 at all time e Z flag of R3 will set to 1 when R4 content is equal to 3F When R4 R4 1 R4 content will select as RO See the configuration of the data memory in Fig 4 6 R5 R6 Port 5 Port 6 R5 and R6 are I O registers Only the lower 4 bits of R5 are available 7 RF Interrupt Status Register 7 6 WNF COP YC pe eqs EXIF IN CIR CDN TCIE S 1 means interrupt request and 0 means no interrupt occurs Bit 0 TCIF TCC overflow interrupt flag Set when TCC overflows
32. ect to change without prior notice 52 07 29 2004 V1 2 Package Information 18 Lead Plastic Dual in line PDIP 300 mil Print lle 4q Le Wed 7H 886 3 5753170 WE II HAF 86 21 54151736 WERE HALEN 86 755 83298787 Http www 100y com tw This specification is subject to change without prior notice 53 EM78P156N OTP ROM PAN RSA Ar Tos 2 PR ZI oanu eae eas 370 T 2530 T 3 556 CT BERE PESE MCN 6 520 TLE PDIP LEL 300MIL PACKAGE OUTLINE DIMENSION 07 29 2004 V1 2 Wed HM 4 886 3 5753170 HEJ H i 86 21 54151736 WEED HA f 3I 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM L27 TYP SPIEL COMI PACKAGE OUTLINE DIMENSION Bdbon A Scale Free This specification is subject to change without prior notice 54 07 29 2004 V1 2 te d 4 Mt 4 886 3 5753170 Ji 7 ETLER 86 21 54151736 WERE I HA f 30 86 755 83298787 Http www 100y com tw EM78P1 56N OTP ROM 0 650 TYP LEON 4 LogqY This specification is subject to change without prior notice 55 07 29 2004 V1 2 Ws dM 886 3 5753170 ERE EFEX 86 21 54151736 WEE 7 t PREY 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw Quality Assurance And Reliability Test category Test conditions Remarks Solderability Solder temperature 245 5 C for 5 seconds up to the stoppe using a rosir type flux Pre condition
33. ents 1 Power on reset 2 RESET pin input low or 3 WDT time out if enabled The device is kept in a RESET condition for a period of approx 18ms one oscillator start up timer period after the reset is detected Once the RESET occurs the following functions are performed Refer to Fig 9 The oscillator is running or will be started The Program Counter R2 is set to all 0 All I O port pins are configured as input mode high impedance state The Watchdog timer and prescaler are cleared When power is switched on the upper 3 bits of R3 are cleared The bits of the CONT register are set to all 1 except for the Bit 6 INT flag The bits of the IOCA register are set to all 1 The bits of the IOCB register are set to all 1 The IOCC register is cleared The bits of the IOCD register are set to all 1 Bit 7 of the IOCE register is set to 1 and Bits 4 and 6 are cleared Bits 0 2 of RF and bits 0 2 of IOCF register are cleared The sleep power down mode is asserted by executing the SLEP instruction While entering sleep mode WDT if enabled is cleared but keeps on running The controller can be awakened by 1 External reset input on RESET pin 2 WDT time out if enabled or 3 Port 6 input status changes if enabled The first two cases will cause the EM78P156N to reset The T and P flags of R3 can be used to determine the source of the reset wake up The last case
34. hree different oscillator modes such as External RC oscillator mode ERC High XTAL oscillator mode HXT and Low XTAL oscillator mode LXT User can select one of them by programming OSC and HLF in the CODE option register Table 6 depicts how these three modes are defined The up most limited operation frequency of crystal resonator on the different VDDs is listed in Table 7 Table 8 Oscillator Modes Defined by OSC and HLP O Mede sNN T awoSC 45 HE NIV Lp Y ERC External RC oscillator mode 0 x x HXT High XTAL oscillator mode LXT Low XTAL oscilator mode 1 0 0 Note 1 X Don t care 2 The transient point of system frequency between HXT and LXY is around 400 KHz This specification is subject to change without prior notice 26 07 29 2004 V1 2 he d H oH 886 3 5753170 ERR II H t 86 21 54151736 ERE JJ HA VE HI 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM Table 9 The Summary of Maximum Operating Speeds Conditions Fxt max MHz 8 0 Two cycles with two clocks 2 Crystal Oscillator Ceramic Resonators XTAL EM78P156N can be driven by an external clock signal through the OSCI pin as shown in Fig 11 below OSCI OW CON Ext Clock OSCO EM78P156N Fig 11 Circuit for External Clock Input In the most applications pin OSCI and pin OSCO can connected with a crystal or ceramic resonator to generate oscillation Fig 12 depicts such
35. in ERC type RC oscillator input pin XTAL type Output terminal for crystal oscillator or external clock input pin RC type Instruction clock output External clock signal input The real time clock counter with Schmitt trigger input pin must be tied to VDD or VSS if not in use Input pin with Schmitt trigger If this pin remains at logic low the controller will also remain in reset condition P50 P53 are bi directional I O pins P50 and P51 can also be defined as the R option pins P50 P52 can be pulled down by software P60 P67 are bi directional I O pins These can be pulled high or can be open drain by software programming P60 P63 can also be pulled down by software INT NV AM Y p External interrupt pin triggered by falling edge Table 3 EM78P156NKM Pin Description Symbol 1516 Powersupply XTAL type Crystal input terminal or external clock input pin ERC type RC oscillator input pin XTAL type Output terminal for crystal oscillator or external clock input pin RC type Instruction clock output External clock signal input The real time clock counter with Schmitt trigger input pin must be tied to VDD or VSS if not in use Input pin with Schmitt trigger If this pin remains at logic low the controller will also remain in reset condition P50 P53 are bi directional I O pins P50 and P51 can also be defined as the R option pins P50 P52 ca
36. inene 5 NN Poweron o x02 a sop GP2 G o oo MM NY mesrawwor o o Wake UpfromPinChange o o o o P P P J P 06 BiName sr Poo Pos Poa Poa Poz Pe Poo This specification is subject to change without prior notice 22 07 29 2004 V1 2 Ws 44 2 Hf FH 886 3 5753170 WEAR A HL fs 86 21 54151736 MEJ HL EH 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM Address Name Reset Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito JREETadWDT P P P P P P P P WakeUpfomPiChage P P P P Pp Pp Pp P Bam X X X X X_ exe io Tor m ahd Power On NN X WOT UU u NM 0s o eb mesetanawot u u u vu vu e el o Wake Up from PinChange u u U U u e Pe P O BiName SS en SE LOM Poweron Lit OMT qo a Yt GO esetandwor o 3 ft a ft ft ft Wake Up from PinChange P P P P P P P Wake Up from Pin Change P P P P U P P EUECICONA Ts E Power On Fmeserad wR o 59 ono ao 97 8 1 WakeUpfromPinChage P P P P Pp ep Pp Pp uw Poweron oN t o1 RNC FOMT go a Law METTI a a CES SOME tat 1 NETS Wake CURT from Pin Change P rms Dupre es PROGR RO WoW ony COT aw o wo do uu uw esetandwor 1 o u o vu vu u Wake Up from Pin Change 1 P u P u U U U Pwro wu
37. ions of a page All instruction are single instruction cycle fclk 2 or fclk 4 except for the instruction that would change the contents of R2 Such instruction will need one more instruction cycle Reset Vector OOOH 4 PG ARwAB COM AN interrupt Vector OOBH On chip Program Stack Level 1 Memory Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 3FFH v eoeds oway sN Fig 3 Program Counter Organization This specification is subject to change without prior notice 9 07 29 2004 V1 2 Ws dH 4 886 3 5753170 WERE I H i 86 21 54151736 WEE EREI 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM Address R PAGE registers IOC PAGE registers 00 RO IAR Reserve 01 R1 TCC CONT Control Register 02 R2 PC Reserve 03 R3 Status Reserve 04 RA RSR Reserve 05 R5 Port5 lOC5 I O Port Control Register 06 R6 Port6 lOC6 I O Port Control Register 07 Reserve Reserve 08 Reserve Reserve 09 Reserve Reserve 0A Reserve IOCA Prescaler Control Register 0B Reserve IOCB Pull down Register 0C Reserve lOCC Open drain Control oD Reserve IOCD Pull high Control Register 0E Reserve IOCE WDT Control Register OF RF Interrupt Status IOCF Interrupt Mask Register 10 General Registers 3F Fig 4 Data Memory Configuration This specification is subj
38. it 3 HLP Power selection 0 Low power 1 High power Bit 2 0 PR2 PRO Protect Bit PR2 PRO are protect bits protect type as following PR2 PR1 PRO Protect 0 0 0 Enable 0 0 1 Enable 0 1 0 Enable This specification is subject to change without prior notice 30 07 29 2004 V1 2 M 4 7 o 886 3 5753170 WERE ETUE 86 21 54151736 WEE HEI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 0 1 1 Enable 1 0 0 Enable 1 0 1 Enable 1 1 0 Enable 1 1 1 Disable 2 Customer ID Register Word 1 Bit 12 Bit 0 XXXXXXXXXXXXX Bit 12 0 Customer s ID code 4 9 Power On Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its steady state EM78156N POR voltage range is 1 2V 1 8V Under customer application when power is OFF Vdd must drop to below 1 2V and remains OFF for 10us before power can be switched ON again This way the EM78156E will reset and work normally The extra external reset circuit will work well if Vdd can rise at very fast speed 50 ms or less However under most cases where critical applications are involved extra devices are required to assist in solving the power up problems 4 10 External Power On Reset Circuit The circuit shown in Fig 16 implements an external RC to produce the reset pulse The pulse width time constant should be kept long enough for
39. ith a value This specification is subject to change without prior notice 8 07 29 2004 V1 2 te d H oH d 886 3 5753170 WEED HL 86 21 54151736 Wi JJ HL EI 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 3 R2 Program Counter amp Stack Depending on the device type R2 and hardware stack are 10 bits wide The structure is depicted in Fig 3 Generating 1024x13 bits on chip OTP ROM addresses to the relative programming instruction codes One program page is 1024 words long e R2 is set as all O s when under RESET condition e JMP instruction allows direct loading of the lower 10 program counter bits Thus JMP allows PC to go to any location within a page CALL instruction loads the lower 10 bits of the PC and then PC 1 is pushed into the stack Thus the subroutine entry address can be located anywhere within a page RET RETL k RETI instruction loads the program counter with the contents of the top level stack ADD R2 A allows the contents of A to be added to the current PC and the ninth and tenth bits of the PC are cleared MOV R2 A allows to load an address from the A register to the lower 8 bits of the PC and the ninth and tenth bits of the PC are cleared e Any instruction that writes to R2 e g ADD R2 A MOV R2 A BC R2 6 will cause the ninth and tenth bits A8 A9 of the PC to be cleared Thus the computed jump is limited to the first 256 locat
40. ly from one chip to another due to the manufacturing process variation In order to maintain a stable system frequency the values of the Cext should not be less than 20pF and that the value of Rext should not be greater than 1 M ohm If they cannot be kept in this range the frequency is easily affected by noise humidity and leakage The smaller the Rext in the RC oscillator the faster its frequency will be On the contrary for very low Rext values for instance 1 KO the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly Based on the above reasons it must be kept in mind that all of the supply voltage the operation temperature the components of the RC oscillator the package types the way the PCB is layout will affect the system frequency This specification is subject to change without prior notice 28 07 29 2004 V1 2 ie 4 2 4 886 3 5753170 HEEJ EPLENE 86 21 54151736 WEJ E PREY 86 755 83298787 Http EM78P156N OTP ROM www 100y com tw e Vcc Rext OSCI EM78P156N Fig 13 Circuit for External RC Oscillator Mode Table 11 RC Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 3 92 MHz 3 65 MHz 2 67 MHz 2 60 MHz 20 pF 139MHz 140 MHz 100k 149 KHz 156 KHz 1 39 MHz 1 33 MHz 940 KHz 900 KHz 100 pF 480 KHz 475 KHz 100k 52 KHz 50 KHz 595 KHz 560 KHz 400 KHz 390 KHz 200 KHz 200 KHz 100k 2
41. n be pulled down by software P60 P67 are bi directional I O pins These can be pulled high or can be open drain by software programming P60 P63 can also be pulled down by software NT 7 Externalinterrupt pin triggered by falling edge MSS 56 fGliund SUNN OM This specification is subject to change without prior notice 7 07 29 2004 V1 2 Ws dM 4 886 3 5753170 WEED HL 86 21 54151736 WE JJ HE VII 86 755 83298787 Http www 100y com tw EM78P156N OTP ROM 4 FUNCTION DESCRIPTION OSCO OSCI RESET d dE Oscillator Timing IOCA Interrupt Instruction Instruction Decoder RI TCC DATA amp CONTROL BUS P60 INT P61 P62 P63 P64 P65 P66 P67 Fig 2 Function Block Diagram 4 1 Operational Registers 1 RO Indirect Addressing Register RO is not a physically implemented register Its major function is to perform as an indirect addressing pointer Any instruction using RO as a pointer actually accesses data pointed by the RAM Select Register R4 2 R1 Time Clock Counter Increased by an external signal edge which is defined by TE bit CONT 4 through the TCC pin or by the instruction cycle clock Writable and readable as any other registers Defined by resetting PAB CONT 3 The prescaler is assigned to TCC if the PAB bit CONT 3 is reset The contents of the prescaler counter will be cleared only when TCC register is written w
42. nputHigh Voltage VDD 5V Porns56e 20 PER n er c ep po VIHT1 Input High Threshold Voltage VDD 5V RESET TCC Schmitttrigger 20 VET Input Low Threshold Voltage VDD 5V RESET TCC Sehmi megen 06 VIHX1 Clock Input High Voltage VDD 5V 1 OSCI 85 N V LXI eee rt Low Voltage VDD OS VIH2 Input High Voltage VDD 3V Pots56 15 ve input Lan Votage ODN ose O oa VIHT2 Input High Threshold Voltage VDD 3V RESET TCC Schmitttrigger 15 Vit input Low Threshold Voltage IVDD 3V RESET TCC Schmit magen VIHX2 Clock Input High Voltage VDD 3V 1 OSCH 4 21 VILX2 Clock Input Low Voltage VDD 3V OSCH Output High Voltage Ports 6 Schmitt trigger Output Low Voltage Ports 6 VOL1 Schmitt trigger E eme ow dd Pull high current Pull high active input pin at VSS 50 70 240 wA IPD Pull down current Pull down active input pin at VDD 2 All input and I O pins at VDD ISB Power cowie output pin floating WDT disabled pA All input and I O pins at VDD Operating supply current RESETS High Fosc 32KHz ICC1 VDD 3V Crystal type CLKS 0 output 15 20 30 m at two cycles four clocks pin floating WDT disabled Operating supply current RESET High Fosc 32KHz ICC2 VDD 3V Crystal type CLKS 0 output 25 35 uA at two cycles four clocks pin floating WDT enabled Operating supply current RESET High Fosc 4MHz
43. reset by software Bit 1 ICIF Port 6 input status change interrupt flag Set when Port 6 input changes reset by software Bit 2 EXIF External interrupt flag Set by falling edge on INT pin reset by software Bits 3 7 Not used This specification is subject to change without prior notice 11 07 29 2004 V1 2 te d H oH 886 3 5753170 WEAR H i 86 21 54151736 EM78P156N WEF 7J E FRESI 86 755 83298787 OTP ROM Http www 100y com tw RF can be cleared by instruction but cannot be set OCF is the interrupt mask register Note that the result of reading RF is the logic AND of RF and IOCF 8 R10 R3F All of these are 8 bit general purpose registers 4 2 Special Purpose Registers 1 A Accumulator Internal data transfer or instruction operand holding It cannot be addressed 2 CONT Control Register ee WPS COPS Le 4 WS WOO ew ANNO al Pot NT TS TE PAB PSR2 PSR PSRO Bit 0 PSRO Bit 2 PSR2 TCC WDT prescaler bits Bit 3 PAB Prescaler assignment bit 0 TCC 1 WDT Bit 4 TE TCC signal edge 0 increment if the transition from low to high takes place on TCC pin 1 increment if the transition from high to low takes place on TCC pin Bit 5 TS TCC signal source 0 internal instruction cycle clock 1 transition on TCC pin Bit 6 INT Interrupt enable flag 0 masked by DISI or hardware interrupt 1 enabled by ENI RETI instructions Bit 7 No
44. t used This specification is subject to change without prior notice 12 07 29 2004 V1 2 M A oH 886 3 5753170 MEJ HAE 86 21 54151736 EM78P156N MER J FERII 86 755 83298787 OTP ROM Http www 100y com tw CONT register is both readable and writable 3 IOC5 IOC6 I O Port Control Register e 1 put the relative I O pin into high impedance while 0 defines the relative I O pin as output Only the lower 4 bits of IOC5 can be defined OC5 and IOC6 registers are both readable and writable 4 IOCA Prescaler Counter Register IOCA register is readable The value of IOCA is equal to the contents of Prescaler counter Down counter 5 IOCB Pull down Control Register PD7 PD6 PD5 PD4 PD2 PDi PDO Bit 0 PDO Control bit is used to enable the pull down of P50 pin 0 Enable internal pull down 1 Disable internal pull down Bit 1 PD1 Control bit is used to enable the pull down of P51 pin Bit 2 PD2 Control bit is used to enable the pull down of P52 pin e Bit 3 Not used Bit 4 PD4 Control bit is used to enable the pull down of P60 pin Bit 5 PD5 Control bit is used to enable the pull down of P61 pin Bit 6 PD6 Control bit is used to enable the pull down of P62 pin Bit 7 PD7 Control bit is used to enable the pull down of P63 pin e IOCB Register is both readable and writable 6 IOCC Open drain Control Register OD7 oDe obs OD4
45. tw Table 4 Usage of Port 6 Input Change Wake up Interrupt Function Usage of Port 6 input status changed Wake up Interrupt I Wake up from Port 6 Input Status Change Il Port 6 Input Status Change Interrupt a Before SLEEP 1 Read I O Port 6 MOV R6 R6 1 Disable WDT using very carefully 2 Execute ENI 2 Read I O Port 6 MOV R6 R6 3 Enable interrupt Set IOCF 1 3 Execute ENI or DISI 4 F Port 6 change interrupt 4 Enable interrupt Set IOCF 1 Interrupt vector 008H 5 Execute SLEP instruction b After Wake up 1 IF ENI Interrupt vector 008H 2 IF DISI 2 Next instruction PCRD R vcc oc Ly A E Q E D Weakly X 9 lt sf ha Pull up d CLK PCWR Q C E L PORT gt m e s o DL NW 10D Ls PDWR wt T PDRD v 9 M S a CU J X N pu The Rex is 430K ohm external resistor Fig 8 The Circuit of I O Port with R option P50 P51 1 NOTE Software disables WDT watchdog timer but hardware must be enabled before applying Port 6 Change Wake Up function CODE Option Register and Bit 11 ENWDTB set to q y This specification is subject to change without prior notice 19 07 29 2004 V1 2 he d A oH 886 3 5753170 WERE t Eif 86 21 54151736 WE JJ HL FERII 86 755 83298787 EM78P156N Http www 100y com tw OTP ROM 4 5 RESET and Wake up 1 RESET A RESET is initiated by one of the following ev
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