Dell PowerEdge R630 Statement of Volatility
Contents
1. 0 gt per CPU DIMM Non Varies not factory Internal USB Key 7 Up to 1 N A 5 Volatile installed Trusted Platform Module Non 1 U_TPM 128 Bytes TPM Volatile CPU Volatile lor2 CPU1 CPU2 Various iDRAC DDR Volatile 1 U_IDRAC_MEM 256MByte i f 64 kbyte iDRAC Volatile U_IDRAC 1 registers 8x2 5 Backplane SEP internal flash Non 1 U3 Flash 32KB 4KB Volatile EEPROM 1KB 10x2 5 or 6x2 5 4x PCle SSD EXP Backplane NVSRAM memory Non 1 U1 1 Mb Volatile Flash memory Non 1 U2 32 Mb Volatile Expander FRU image Non 1 U5 512 Bytes Volatile BP FRU image Non 1 U15 256 Bytes Volatile 24x2 5 EXP Backplane NVSRAM memory Non 1 U3 1 Mb Volatile Flash memory Non 1 U2 32 Mb Volatile Expander FRU image Non 1 U7 512 Bytes Volatile BP FRU image Non 1 U3 256 Bytes Volatile H730 H830 PERCs Item Non Quantity Reference Designator Size Volatile or Volatile NVSRAM Non 1 U1033 128KB volatile FRU Non 1 U1019 256B volatile 1 Wire EEPROM Non 1 U1004 128B volatile SPD Non 1 U22 256B volatile SBR Non 1 U1020 8KB volatile Flash Non 1 U1031 16MB volatile ONFI Backup Flash Non 1 U1059 4GB volatile SDRAM Volatile 5 U1043 U1047 512MB 1GB H330 H330M PERC NVSRAM Non 1 U1033 128KB volatile FRU Non 1 U1019 256B volatile 1 Wire EEPROM Non 1 U1004 128B volatile SBR Non 1 U1020 8KB volatile Flash Non 1 U3 16MB volatile PCle SSD Extensi2. Statement of Volatility Dell PowerEdge R630 The Dell PowerEdge R630 contain both volatile and non volatile NV components Volatile components lose their data immediately upon removal of power from the component Non volatile components continue to retain their data even after the power has been removed from the component Components chosen as user definable configuration options those not soldered to the motherboard are not included in the Statement of Volatility Configuration option information pertinent to options such as microprocessors remote access controllers and storage controllers is available by component separately The following NV components are present in the PowerEdge R630 servers Item Non Quantity Reference Designator Size Volatile or Volatile Planer Non PCH Internal CMOS RAM 1 U_PCH 256 Bytes Volatile Non BIOS Password 1 U_PCH 16 bytes Volatile Non BIOS SPI Flash 1 U_SPI_BIOS 8 MB Volatile Non iDRAC SPI Flash l 1 U_IDRAC_SPI 4 MB Volatile Non BMC EMMC 1 U_EMMC 4 GB Volatile T Non CPU Vcore Regulators i 2 U8003 U8043 512 Bytes Volatile Non Vmem Regulators 7 2 U8011 U8051 512 Bytes Volatile System CPLD RAM Volatile 1 U_CPLD 1KB 02 2013 Item Non Quantity Reference Designator Size Volatile or Volatile Up to 12 Up to 32GB per System Memory Volatile CPU lt 2 1 gt _CH lt 3 0 gt _D lt 2
3. artition LC service diags LC OS drivers USC firmware CPU Vcore ROM No Operational parameters Regulators Vmem Regulators ROM No Operational parameters System CPLD RAM RAM No Not utilized System Memory DRAM Yes System OS RAM Internal USB Key Flash Yes General purpose USB key drive Trusted Platform EEPROM Yes Storage of encryption keys Module TPM CPU Cache registers Yes Processor cache registers iDRAC DDR DRAM No iDRAC local memory iDRAC Cache registers No Processor cache registers 8x2 5 Backplane SEP internal flash Integrated No Firmware FRU Flash EEPROM 10x2 5 or 6x2 5 4x PCle SSD EXP Backplane Flash memory Flash No FW configuration data Firmware Item Type e g Flash PROM EEPROM Can user programs or operating system write data to it during Purpose e g boot code normal operation Expander FRU image 12C EEPROM No FRU BP FRU image 12C EEPROM No FRU 24x2 5 EXP Backplane NVSRAM memory Flash No FW configuration data Flash memory Flash No Firmware Expander FRU image 12C EEPROM No FRU BP FRU image 12C EEPROM No FRU H730 H830 PERCs NVSRAM NVSRAM No Configuration data FRU FRU No Card manufacturing information 1 Wire EEPROM 1 Wire EEPROM No Holds default controller properties settings SPD SPD No Memory configuration data SBR SBR No Bootloader Flash Flash No Card firmware ONFI Backup Flash ONFI Backup Flash No Holds cache da
4. e via PCH SPI interface via iDRAC SPI interface via iDRAC 12C interface via iDRAC N A Hardware strapping Hardware strapping Hardware strapping Not user clearable Not user clearable Not user clearable Not user clearable It also auto clears when power is applied K NOTE For any information that you may need direct your questions to your Dell Marketing contact 2014 Dell Inc Trademarks used in this text Dell the DELL logo and PowerEdge are trademarks of Dell Inc
5. guration in F2 system setup menu BIOS Password Keyboard N A Place shunt on J_ PSWD_NVRAM jumper pins 2 and 4 BIOS SPI Flash iDRAC SPI Flash SPI interface via iDRAC SPI interface via iDRAC Software write protected Embedded iDRAC subsystem firmware actively controls sub area based write protection as needed Not possible with any utilities or applications and system is not functional if corrupted removed Not completely user clearable however user data lifecycle log and archive SEL fw image repository can be cleared via Delete Configuration and Retire System accessible in Lifecycle Controller interface BMC EMMC NAND Flash interface via iDRAC Embedded FW write protected Not completely user clearable however user data lifecycle log and archive SEL fw image repository can be cleared via Delete Configuration and Retire System accessible in Lifecycle Controller interface CPU Vcore Regulators NA Not user clearable Vmem Regulators NA Not user clearable System CPLD RAM Not utilized Not accessible Not accessible System Memory System OS OS Control Reboot or power down system Internal USB Key USB interface via PCH Accessed via system Os No write protect Can be cleared in system OS Trusted Platform Module TPM Using TPM Enabled operating systems SW write protected F2 Setup option CPU Ho
6. on Card Switch Configuration EEPROM Non 1 U2 256B Volatile Item Non Quantity Reference Designator Size Volatile or Volatile IDSDM SPI Flash Non 1 U2 8Mb Volatile MCU Non 1 U6 512KB Volatile x8 Control Panel rSPI Flash Non 1 U3 32Mb Volatile x10 x24 Control Panel rSPI Flash Non 1 U6 32Mb Volatile iDRAC Quick Sync Non MCU MSP430 p 1 U_MSP430 128KB Volatile Item Type e g Flash Can user Purpose e g boot code PROM EEPROM programs or operating system write data to it during normal operation Planer PCH Internal CMOS Battery backed CMOS Real time clock and BIOS configuration o RAM RAM settings Battery backed CMOS 5 BIOS Password RAM Yes Password to change BIOS settings Boot code system configuration BIOS SPI Flash SPI Flash No information UEFI environment Flash descriptor ME Item Type e g Flash PROM EEPROM Can user programs or operating system write data to it during Purpose e g boot code normal operation iDRAC Uboot bootloader server management persistent store i e IDRAC MAC Address iDRAC boot variables iDRAC SPI Flash SPI Flash No i lifecycle log cache virtual planar FRU and EPPID rac log system event log JobStore iDRAC Secure boot code Operational iDRAC FW Lifecycle BMC EMMC eMMC NAND Flash No Controller LC USC p
7. ta during power loss SDRAM SDRAM No Cache for HDD I O H330 H330M PERC NVSRAM NVSRAM No Configuration data FRU FRU No Card manufacturing information 1 Wire EEPROM 1 Wire EEPROM No Holds default controller Item Type e g Flash PROM EEPROM Can user programs or operating system write data to it during normal operation Purpose e g boot code properties settings SBR SBR No Bootloader Flash PCle SSD Extension Card Switch Configuration EEPROM Flash SPI Flash EEPROM No No requires specialized SW Card firmware Configuration for PLX PCle switch setting registers IDSDM SPI Flash SPI Flash No Exclusively used by the controller MCU Embedded Flash FW can be Firmware updated via iDRAC which x8 Control Panel rSPI Flash x10 x24 Control Panel rSPI Flash iDRAC Quick Sync MCU MSP430 SPI Flash SPI Flash Flash runs on Linux No No No restored SPI restored SPI iDRAC Quick Sync Communicate Protocol PCH Internal CMOS RAM How is data input to this memory How is this memory write protected N A BIOS only control How is the memory cleared 1 Set NVRAM_CLR jumper to clear BIOS configuration settings at boot and reboot system 2 AC power off system remove coin cell battery for 30 seconds replace battery and power back on 3 restore default confi
8. tion data to Host Processor tools available to the customer NVSRAM FRU Programmed at ICT Not WP Cannot be cleared with existing during production tools available to the customer 1 Wire EEPROM ROC writes data to this memory Pre programmed before assembly Not WP Not visible to Host Processor Not WP Not visible to Host Processor Cannot be cleared with existing tools available to the customer Cannot be cleared with existing tools available to the customer PCle SSD Extension Card Switch Configuration EEPROM Pre programmed before assembly Can be updated using Dell LSI tools The EEPROM image is pre loaded at factory before assembly Once assembled on the card data can be entered Not WP Not visible to Host Processor Device can be write protected via hardware pin Alternatively device contents can be write protected via Cannot be cleared with existing tools available to the customer System is not functional as intended if corrupted removed SPI Flash How is data input to this memory via PLX Device Editor or PLX EEP DOS based tool SPI interface via iDRAC How is this memory write protected WPEN bit in status register Hardware strapping How is the memory cleared Not user clearable MCU x8 Control Panel rSPI Flash x10 x24 Control Panel rSPI Flash iDRAC Quick Sync MCU MSP430 USB3 0 interfac
9. w is data input to this memory Various How is this memory write protected Various How is the memory cleared Power off iDRAC DDR iDRAC Firmware NA Power off iDRAC iDRAC Firmware NA Power off 8x2 5 Backplane SEP internal flash 12C interface via iDRAC 10x2 5 or 6x2 5 4x PCle SSD EXP Backplane NVSRAM memory Common Flash memory Interface CFI Program write protect bit Hardware strapping Not user clearable Not user clearable Flash memory Common Flash memory Interface CFI Hardware strapping Not user clearable Expander FRU image 12C interface via iDRAC Hardware strapping Not user clearable BP FRU image 24x2 5 EXP Backplane NVSRAM memory 12C interface via iDRAC Common Flash memory Interface CFI Hardware strapping Hardware strapping Not user clearable Not user clearable Flash memory Common Flash memory Interface CFI Hardware strapping Not user clearable Expander FRU image 12C interface via iDRAC Hardware strapping Not user clearable BP FRU image 12C interface via iDRAC Hardware strapping Not user clearable H730 H830 PERCs NVSRAM ROC writes configuration data to NVSRAM Not WP Not visible to Host Processor Cannot be cleared with existing tools available to the customer Programmed at ICT during production Cannot be cleared
10. with existing tools available to the customer 1 Wire EEPROM SPD ROC writes data to this memory Pre programmed before assembly Not WP Not visible to Host Processor Not WP Not visible to Host Processor Cannot be cleared with existing tools available to the customer Cannot be cleared with existing tools available to the customer Item SBR How is data input to this memory Pre programmed before assembly Pre programmed before assembly Can be updated using Dell LSI tools How is this memory write protected Not WP Not visible to Host Processor Not WP Not visible to Host Processor How is the memory cleared Cannot be cleared with existing tools available to the customer Cannot be cleared with existing tools available to the customer ONFI Backup Flash FPGA backs up DDR data to this device in case of a power failure Not WP Not visible to Host Processor Flash can be cleared by powering up the card and allowing the controller to flush the contents to VDs If the VDs are no longer available cache can be cleared by going into controller bios and selecting Discard Preserved Cache H330 H330M PERC ROC writes to this memory using it as cache for data IO to HDDs Not WP Not visible to Host Processor Cache can be cleared by powering off the card NVSRAM ROC writes Not WP Not visible to Cannot be cleared with existing configura
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