Dell PowerEdge 7250 Error Reference Guide
Contents
1. 3 4 SR870BN4 Machine Check Error Handling 7 4 1 Glassification of EFTOIS a ala assia 7 nn iz eU Ic 7 4 1 PRON SalI initiis Rete cette taba te uei teen 7 4 2 Error Reporting oido OE RR e Ur e selben utet intu e prepa t et 8 4 3 onde tea tete ta tSt e a tte A u gs 9 4 4 SEL Event Log Format for Machine Check 9 b SR870BN4 PCI Device 12 6 BIOS POST Error Codes 13 f POST Codes ASS E E wei ues P RN OR 18 7 1 North and South Port 80 81 Cards EID ase eh ate At 18 5 2I POST Code suyun CMM 18 7 2 1 POST Codes Module eee nnne nnne 18 7 2 2 Specific POST code Modules sse 20 7 3 JRBecovery Port S0 CodeS ie cett bacc bes ausu dard Rates ea e usu 30 8 B ep Codes uu u 31 6 121 Merniory Test Falle ineo secet 31 8 1 2 Recovery Beep Codes e 32 8 1 3 BMC Beep Code 2 21 2 1 0 002 000 0000000000000000000000000000000002. 28 Table dT T ACPIHPOSPIGSOd8S Q NSS eoe o Ede 29 Table 12 SAL Runtime POST Codes 29 Table 13 Recovery POST Codes te ier pe ERRARE Lori Uer Re deer 30 Table 14 Error Beep Codes thc a guau a Eoo Edi da ERE Ru dn 31 Table 15 POST Memory Beep Error Codes Debug Port Encoding List 31 Table 16 Recovery Mode Beep 32 Table 17 BMG Beep Codes isa Fade Hoe I eR REA YER HU D FA 32 Revision 1 0 M SR870BN4 Error Reference Guide Introduction 1 Introduction This document is an error reference guide for the SR870BN4 server system 1 1 Document Organization Section 1 An introduction to the SEL Section 2 A brief introduction to the EFl based SEL Viewer utility Section 3 SEL Data Tables Section 4 MCA Error Handling including SEL event format for machine check events Section 5 5 870 4 PCI Device IDs Section 6 BIOS POST error codes and messages These error codes and messages appear on the video and are also logged in the system event log Section 7 SR870BN4 BIOS POST codes port 80 81 card is required to view these codes Section 8 A list of beep codes generated by the SR870BNA platform Appendix A Glossary Appendix B
3. pa gt Displays SEL properties from BMC Figure 1 SEL Viewer Utility 2 Revision 1 0 SR870BN4 Error Reference Guide SR870BN4 SEL Data Tables 3 SR870BN4 SEL Data Tables The tables in this section provide information on the data provided by the SEL Viewer utility 3 1 SR870BN4 Generator ID Codes Generator ID 0x31 00 Ox3F 00 System BIOS or System SW 3 2 SR870BN4 Sensor Codes a Type Number Sensor Name 308 1 0271 271 1O Board Temp4 0 O 33h IO Board SIOH Temp O 34h lOBoadTemp3 S O 3 98h 99h 9Ah 9Bh a QNM Revision 1 0 3 SR870BN4 SEL Data Tables SR870BN4 Error Reference Guide Tach Fan 1 Tach Fan 2 Tach Fan 3 Tach Fan 4 Fan 1 Present Fan 2 Present Fan 3 Present Fan 4 Present 4 Security Violation Attempt 04h Platform Security Violation 07 YU U Processor 90h Proc 1 Status 91h Proc 2 Status Proc 3 Status Proc 4 Status Power Supply 4 Revision 1 0 SR870BN4 Error Reference Guide SR870BN4 SEL Data Tables ee es Ew Type Number Sensor Name Board 5 D2D 2 Processor Board 3 3V D2D 1 Processor Board 2 5V D2D 1 Processor Board 2 5V D2D 2 Memory Board 1 1 25V D2D 7Ch Memory Board 2 1 25V D2D a Power Unit Status 02h Power Unit Redundancy Hot Swap Drive System Firmware Progress POST Error Event Logging Event Logging Disabled
4. Critical Interrupt 07 FP Diag Interrupt Front Panel Diag Interrupt tuy Board U U U MP Slot Connector PHP Slot 4 PHP Slot 5 Revision 1 0 5 SR870BN4 SEL Data Tables SR870BN4 Error Reference Guide Sensor Sensor Type Number Sensor Name Watchdog 03h BMC Watchdog2 Fan Boost Memory Board 1 Temp Fan Boost Memory Board 2 Temp Fan Boost IO Board Temp 1 Fan Boost IO Board SIOH Temp Fan Boost IO Board Temp 3 Fan Boost CPU Board Ambient Temp Fan Boost CPU Board SNC Temp Fan Boost Proc 1 Temp Fan Boost Proc 2 Temp Fan Boost Proc 3 Temp Fan Boost Proc 4 Temp 6 Revision 1 0 SR870BN4 Error Reference Guide SR870BN4 Machine Check Error Handling 4 5 870 4 Machine Check Error Handling This section gives an overview of the implementation of machine check error handling on the SR870BN4 server system For additional details about Itanium based system error generation and error handling refer to the tanium Processor Family Error Handling Guide document number 249278 002 and the tanium System Abstraction Layer Specification document number 245359 005 Both documents can be downloaded from the web at developer intel com 4 1 Classification of Errors Error events are classified by the processor and platform into three basic groups This section provides a summary of the different error types and signaling methods defined by the IPF Machine Check architecture and i
5. 32 AppendbcA GIOSSALY errat enar ona o Yea kae E FERE ERN RERKNER KRe RR XXE EY EFXEEEEEEE REREDERNRRRYYE EE NER Appendix B Reference Documents IV V Revision 1 0 iii List of Figures SR870BN4 Error Reference Guide List of Figures Figure 1 SEE Viewer 2 iv Revision 1 0 SR870BN4 Error Reference Guide List of Tables List of Tables table SAL 3 0 MCA Records uuu m u u I e Pene oreet ano tana La oM de eaae ed A ER ERE 8 Table 2 SEL Event Logs for Machine Check Errors 10 Table 3 Onboard PCI Devices and Slots a 12 Table 4 Error Code Classification 13 Table 5 General POST Code Module Numbers for Itanium Based Platforms 19 Table POST Codes BSP Only uuu uu ua Duda MOS EXER OG RR RE 20 Table SAE B POST CodeS edu o Oe ada d lee ease 21 fable SALE POST SNI A SGS gA 24 Table oO IA 32 POST saisie u uD umu aD ia 25 DEM
6. 0x002C All necessary processing before passing control to the video ROM is done Look for the South video ROM next and pass control to it 0x002D The video ROM has returned control to BIOS POST Perform any required processing 26 Revision 1 0 SR870BN4 Error Reference Guide POST Codes after the video ROM had control 0x002E Complete post video ROM test processing If the EGA VGA controller is not found South perform the display memory read write test next 0x0037 The display mode is set Display the power on message next South 0x0038 Initialize the bus input IPL and general devices next if present South 0x0039 Late processor self test Display bus initialization error messages South 0x003A The new cursor position has been read and saved Displaying the Hit F2 message South 0x0053 The memory size information and the CPU registers are saved Entering real mode South 0 0054 Shutdown was successful The CPU is real mode Disabling the Gate A20 line and South parity next 0x0057 The A20 address line parity disabled Adjusting the memory size depending on South relocation and shadowing next 0x0058 The memory size was adjusted for relocation and shadowing Clearing the Hit F2 South message 0x0059 The Hit F2 message is cleared Starting the DMA and interrupt controller test next South 0x0060 The DMA page register test passed Performing the DMA Controller 1 base register South test next 0x0062 The DMA controller 1 ba
7. 0x87DD APs Setup for interrupt wakeup reinitialization of BSPSTORE and SP if South needed Wait for interrupt wakeup 0x87DC BSP only Switch to virtual address Control register programming SET in PSR bn 44 it 36 rt 27 dt 17 ic 13 Clear task priority register cr tpr Clear interruption function state register cr ifs Set legacy BIOS cs base and ss base Set es ds fs gs 0 with 4G limit Legacy BIOS module eip Give control at xxxx e05b to IA 32 code 7 2 2 3 SAL F Module Table 8 SAL F POST Codes Code Value BSP Meaning Display APs Both 0x87BF BSP First check point Check point in v6b00_83_ip2x Update EBDA entry inside South SST Create EFI memory descriptor Update SST checksum 0x87BE BSP Check point near 6600 83 5 Search FIT for ACPI module South SAL_C_module_17 and get size align scratch buff size Hang if ERROR 0x07BE 0x87BD Load image by module type sal c module 17 Use PELoader 0x07BD Hang if not found Get entry point and GP value 0x87BC Load image by module type sal c module 17 Flush cache 0x07BC BSP Hang on ERROR South Build MP amp ACPI table 0 87 Initialize memory 0 0 by to SAL C 24 Revision 1 0 SR870BN4 Error Reference Guide POST Codes 0x07BB BSP Hang on ERROR 0x87BA BSP Feed system information 0x1 with call to SAL_C South 0x07BA Hang on ERROR 0x87B9 Initialize MP table v1 4 0x2 with call to SAL C 0x07B9 Hang on ERROR 0x07
8. 7 4 3 0 ee Process Auto Scan Input Execute Auto scan C code OxAF 80 Reserved for SAL North MCA INIT PMI 0x7F to 0x60 SAL B codes SAL B SAL_C SAL_F Ox4F to 0x40 ACPI 7 2 2 Specific POST code Modules 7 2 2 1 SAL A Module The SAL A POST codes are defined in the following table Table 6 SAL A POST Codes BSP Only Code Number Weaning Ox8F70 Memory Initialization Entry Ox8F71 RAC Initialization Mem_DoRaclnitialization 20 Revision 1 0 SR870BN4 Error Reference Guide POST Codes Validate DIMMs Mem_ValidatelnstalledConfiguration Ox8F73 Program MIRs MITs Mem_DoMirMitProgram North Ox8AFO Reserved for MCA INIT PM North 0 8 80 DIMM path latency Calibration North to 0x8800 7 2 2 2 SAL B Module Table 7 SAL B POST Codes Code Number BSP APs Display Both Ox87FF BSP APs First check point Initialize South cr iva ar eflag ar cflg cr IrrO cr Irr1 cr ifa cr itir Ox87FE BSP only Initialize io base address CPUS health etc for CPU s Initialize Revision 1 0 21 POST Codes SR870BN4 Error Reference Guide And min_state_area for all CPU s BSP APs cpu_data_base cpu_bspstore_base cpu_health cpu_data_base points to min state save area TOM below and above 4G Allocate sal_mp_info_table data and sal_efi stack area and legacy_stack temp Initialize legacy stack top and bottom for temporary use during POST only INT_15 FN F788 in EM
9. POST Error Codes and Messages Revision 1 0 17 POST Codes SR870BN4 Error Reference Guide 7 POST Codes In order to indicate progress through BIOS POST and in special cases where errors are encountered during BIOS POST there are three common mechanisms which shall be employed by the SR870BN4 BIOS The first method is to display port 80 81 codes to a C adapter connected to the processor baseboard The second common method is the use of beep codes encoded beep sequences emitted by the PC speaker when an error is encountered Beep codes are employed only before the display screen is enabled and generally indicate fatal errors Beep codes are coupled with special port 80 error codes The final method is to display an error message to the display screen 7 1 North and South Port 80 81 Cards In the case of the SR870BN4 server this port 80 card is a custom device attached to I C ports in two different places on the server One port 80 device serves the north flash ROM and the other serves the south flash ROM 7 2 POST Codes 7 2 1 POST Codes Module Map The SR870BN4 server employs a novel post code scheme Post codes assigned make use of the fact that the SR870BNA utilizes port 80h and 81h This gives the SR870BNA 16 bits to encode The following rules apply to the post code encoding Bit 15 1 1A64 code being executed 0 IA 32 code being executed Bit 14 1 system stopped due to known failure O progress indication All
10. Posas B 00Vnznarsze Owamc O Peisa Dwamc PCs e ora size Omero Pose 1 Eense Owemc Posas Pes Omamc 12 Revision 1 0 SR870BN4 Error Reference Guide BIOS POST Error Codes and Messages 6 BIOS POST Error Codes and Messages The following error codes are relevant to the SR870BN4 server The system BIOS displays POST error messages on the video screen and are also logged in the SEL The SR870BN4 BIOS will prompt the user to press a key in case of serious errors Error Code Classification Red Critical events that require user interaction BIOS POST will pause with a message requesting to Press F1 F2 or ESC This error code type is indicated in the table below as a YES in the column heading Pause On Boot Yellow Non critical events BIOS POST will continue after a brief pause and does not require user interaction This error code type is indicated in the table below as a NO in the column heading Pause On Boot Table 4 Error Code Classification Pause on Boot Recommended User Action CMOS Battery Failure Yes Replace the battery CMOS Checksum Failure Yes Clear CMOS es dbi i Keyboard Stuck Key Yes user input required May appear after reboot if there was a keyboard error such as 0109 not being plugged in Could also be a timing problem with the keyboard 011B Date Time Not Set Yes user input required Enter BIOS setu
11. RS 232 base address Performing any required initialization South before the Coprocessor test next 0x009E Initialization after the Coprocessor test is complete Checking the extended keyboard South keyboard ID and Num Lock key next Issuing the Keyboard ID command 0x00A2 Displaying any soft errors 0x00A3 The soft error display has completed Setting the keyboard typematic rate 0x00A4 The keyboard typematic rate is set Programming the memory wait states next 0x00A5 Memory wait state programming is over Clearing the screen 0x00A7 Performing any initialization required before passing control to the adaptor ROM at South E000 next 0 00 Setting up DMI structures 0x0020 Talking to BMC 0x0022 Talking to BMC South 0 00 Uncompressing the DMI data and initializing DMI POST South Ox00AB Building the multiprocessor table 0x00AD Prepare INT10 image Update the necessary data in different modules 0 00 8 Initialization before passing control to the adaptor ROM at E000h completed Pass South control to the adaptor ROM at E000h 0x00A9 Returned from adaptor ROM at E000h control Performing any initialization required South after the E000 option ROM had control next 0x00AA Initialization after E000 option ROM control has completed Displaying the system South configuration 0x00B1 Copying any runtime code to specific areas South 0x0000 Code copying to specific areas is done Pass control to EFI South 7 2 2 5 EF
12. Reference Documents Appendix C Index 1 2 SEL Overview The System Event Log SEL is a non volatile repository for event messages Event messages contain information about system events and anomalies that occur on the server They can be triggered by BIOS event generators or sensors Some event messages are the result of normal happenings such as a normal server boot or possible minor problems like a disconnected keyboard Other events may indicate internal failures such as a component overheat condition where thresholds or ranges of acceptable values exist As with other system events if at any time a component crosses one of these defined thresholds an event message will be generated Regardless of the event the appropriate management controller generates an event message Event messages are passed to the Baseboard Management Controller BMC the primary management controller on Intel server systems The BMC passes the event message to the SEL where it becomes available for querying by an SEL Viewer utility The SEL Viewer provides an interface for the server administrator to view information in the SEL The SEL Viewer is available through the Intel Server Management ISM or the EFI based SEL Viewer utility The system administrator can use this information to monitor the server for warnings and potential critical problems Revision 1 0 1 EFI Based SELViewer Utility SR870BNA Error Reference Guide 2 EFl Based SELViewer Uti
13. code uses INT 8 timer tick for frequency calculation BSP APs Save ID EID Initialize BSPSTORE SP 0x87FD BSP only Search FIT for legacy BIOS 0x07FD BSP only Then hang if not found If found copy top 64K legacy boot block ROM at xxxx 0000 Search for legacy_nvm module sal legacy nvm module 1d 0x07FC BSP only Then hang if not found foe ieee Else continue by saving in RAM Search for efi module sal efi nvm module 1e 0x07FB BSP only Then hang if not found Else continue by saving in RAM WEE Reserve 128k memory for NVM emulation Search for acpi_dsdt module sal_acpi_data_module_16 Ask for South Address size type Ox07FA BSP only Then hang if not found South AEN OAM Else continue by saving in RAM 0x87F9 BSP only Search for addition information acpi_dsdt module South Ask for size align and scratch buff size 0 07 9 BSP only Then hang if not found South r ieee Else continue by saving in RAM 0x87F8 BSP only Search for addition information acpi_dsdt module South pee peer Initialize scratch buffer 0x07F8 BSP only Then hang if not found South pue EE Else continue by saving in RAM Ox87F7 BSP only Reserve ACPI 64 and ACPI 32 data area South Reserve MP table data area Save SAL data base amp size SAL shadow top PELoader SAL F 0x87F6 BSP only Cache flush after PELoader shadow South 0x07F6 BSP only Hang on ERROR South 0 87 5 BSP only Search for information on SAL_F module sal
14. com design servers ipmi System Management BIOS Reference Specification v2 3 http Awww dmtf org Jtanium Processor Family Error Handling Guide Doc Number 249278 002 http developer intel com Itanium System Abstraction Layer Specification Doc Number 245359 005 http developer intel com SR870BN4 BIOS External Product Specification Rev 0 87 Doc Number 11164 SR870BN4 Baseboard Management Controller BMC External Product Specification Rev 0 87 Doc Number 11365 IV Revision 1 0 SR870BN4 Error Reference Guide Appendix C Index Appendix C Index A ACPI 18 20 22 24 25 29 Address 22 AMI 25 AP See also Application Processor 23 24 B Baseboard Management Controller See also BMC 1 15 BIOS 1 3 9 13 14 15 18 22 24 25 26 27 28 29 31 32 BIST 14 BMC 1 3 5 8 9 14 15 28 32 BSP 19 20 21 22 23 24 25 30 31 Built in Self Test See also BIST 14 Bus Number See a so BUSN 12 Checksum 13 CMOS 13 26 31 Configuration 32 Controller 1 12 15 27 D DIMM 9 10 18 19 21 Direct Platform Control See also DPC 1 Direct Platform Control See DPC 1 DMI 28 DPC 1 DPC See also Direct Platform Control 1 Driver 29 ECC 7 18 Error 1 1 5 7 8 9 10 13 14 15 16 19 21 29 30 31 32 Event Message 1 Fan 4 5 6 Fault Resilient Booting See also FRB 14 Revision 1 0 Field Replaceable Unit See also FRU
15. other module bits remain unmodified Bit 13 1 fault or trap no change in module numbers 0 normal execution In case of fault or trap only bit 13 is set and other bits are left on modified This allows us to detect which module produces the fault Bit 12 Reserved Bit 11 4 Module type Bit 3 0 Sub module type The module number and sub module number are a in 4 bit boundary to allow us to decode quickly by the numbers The module number identifies the major module such as memory PCI ACPI etc The sub module identifies the sub function such as SPD read in progress ECC error and DIMM mismatch for memory module Module names and numbers are listed in the following tables 18 Revision 1 0 SR870BN4 Error Reference Guide POST Codes Secret Decoder Bit 11 8 OxF stack less code being executed OxD 0x0 memory is available Table 5 General POST Code Module Numbers for Itanium Based Platforms bits 11 4 shown below SUB MODULES BITS Memory Initialization 15 12 7 4 3 0 Ea 2j ia ia ET Levelization failed No Memory Found OxF6 Memory Test North OxF5 Platform Discovery North OxF4 F3 SBSP selection amp Platform Init North C Revision 1 0 19 POST Codes SR870BN4 Error Reference Guide Code Value bit 8 1 Display bits 11 4 shown below SUB MODULES BITS Memory Autoscan 15 12
16. with correct memory Verify the affected memory and replace with correct memory 15 BIOS POST Error Codes and Messages Error Code Error Message 8504 Persistent Single bit Error Detected Row1 Row 1 mapped out 8505 Persistent Single bit Error Detected Row2 Row 2 mapped out 8506 Persistent Single bit Error Detected Row3 Row 3 mapped out 8507 Persistent Single bit Error Detected Row4 Row 4 mapped out 8508 Memory Mismatch detected Row1 Row 1 mapped out 8509 Memory Mismatch detected Row2 Row 2 mapped out 850A Memory Mismatch detected Rows Yes Row 3 mapped out 850B Memory Mismatch detected Row4 Yes Row 4 mapped out 850C DIMM1 memory board 1 defective 850D DIMM2 memory board 1 defective 850E DIMM3 memory board 1 defective 850F DIMM4 memory board 1 defective 8510 DIMM5 memory board 1 defective 8511 DIMM6 memory board 1 defective 8512 DIMM7 memory board 1 defective 8513 DIMM8 memory board 1 defective 8514 DIMM1 memory board 2 defective 8515 DIMM2 memory board 2 defective 8516 DIMM3 memory board 2 defective 8517 DIMM4 memory board 2 defective 8518 DIMM5 memory board 2 defective 8519 DIMM6 memory board 2 defective 851A DIMM7 memory board 2 defective 851B DIMM8 memory board 2 defective 16 SR870BN4 Error Reference Guide Pause on Boot Yes Verify the affected memory and replace with correct memory Verify the affected memory and replace with corre
17. 8 FRB 14 Front Panel 5 Front Panel reset 19 20 Initialization 19 20 26 27 28 Install 28 29 Intel Server Control See also ISC v2 x See also ISC v3 x 1 Legacy 24 LPC 10 12 Management Controller 1 15 Memory iv 3 5 6 9 10 11 13 14 16 19 20 21 23 25 28 31 32 Message 1 13 NVRAM 28 29 Parity Error See also PERR 31 Password 13 PERR 8 9 10 11 PHP 5 POST 1 5 13 18 19 20 21 24 25 26 27 28 29 30 31 POST Code 18 19 20 21 24 25 28 29 30 Power Control 32 Power Unit 5 Power on Self Test See POST 1 5 13 18 19 20 21 24 25 26 27 28 29 30 31 Processor 4 7 8 9 10 14 15 19 20 29 31 32 Processor Failure 31 Appendix C Index R Recovery 20 21 30 32 Reset 19 20 s SBE 11 SCSI 4 5 12 27 Security 4 SEL 2 SEL See also System Event Log 1 2 3 8 9 10 13 15 32 Sensor 5 Sensor Event 1 2 5 7 8 9 10 11 15 30 Sensor Type 2 3 8 SERR 8 9 10 Server Management 1 Shadow 14 23 Shutdown 27 31 SMBIOS 8 9 10 SR460AC4 1 3 9 System Event Log See also SEL 1 15 VI SR870BN4 Error Reference Guide System Management BIOS 9 Temperature 3 5 U USB See also Universal Serial Bus 12 V VID See also Vendor Identification 32 Voltage 3 Watchdog Timer 28 Revision 1 0
18. B8 wi zi Hang on ERROR Initialize 64 ACPI v1 1 0x4 with call to SAL_C E 0x87B7 0x07B7 ai B 0x87B6 0x07B6 Hang on ERROR 0x87B5 Clear scratch memory OxFFF with call to SAL C B SP Hang on ERROR SP 0x07B5 Hang on ERROR South SP SP 0x87B4 B Search FIT for EFI module with call to PELoader Get Size align and scratch South buff size 0x07B4 Hang on ERROR Get entry point and GP value South 0x87B3 Load image by module type sal c module 17 0x07B3 Hang on ERROR Get entry point and GP value 0x87B2 Flush cache with PAL call 0x07B2 Hang on ERROR 0x87B1 Build EFI input parameter table Get EFI stack bspstore etc with EFI call 0x07B2 Hang on ERROR South BSP 0x87BO Build EFI input parameter table Get EFI stack bspstore etc with EFI call South Store EFI stack bspstore etc with EFI call Call EFI and that should be end 0x07BO Hang on ERROR if OK come back from EFI Initialize 32 1 64 ACPI v2 0 0x5 with call to SAL C 7 2 2 4 IA 32 Module The IA 32 POST codes all have the Most Significant Bit MSB cleared by the convention established above in this document Also the 32 POST codes don t fall into the module definition for Itanium based platforms above The codes shown here are consistent with the 7 0 AMI core Table 9 32 POST Codes 0 0000 Power on delay is starting Next the initialization code checksum will be verified 0x00D1 Initial
19. I Module The EFI POST codes have been redefined relative to previous platform implementations Note the addition of the module number and that bit 15 is set indicating code for Itanium based platforms Table 10 EFI POST Codes Wo Fr Memory map installed 0 85 Basic EFI services are now functional Although no devices or variable store support is South on line InitializeLib 0x85F4 Init Watchdog Timer Initialize support for calling BIOS functions Initialize Bios Int Caller South Install base devices This would at least include a global IO device all NV ram store device s and the timer tick It may optionally include other IO devices Install Base Devices 0 85 5 Nv Store installed Ox85F6 Install consoles device and notify EFI FW to pick and enable a console Ox85F7 Consoles installed 28 Revision 1 0 SR870BN4 Error Reference Guide POST Codes 0x85F8 Print banner with entry address to make it easy to debug with symbols Install any South devices that are integrated system volume devices 0x85F9 System volumes installed South 0x85FA Init Nv Var Store Mem Set EFIDebug based on NVRAM variable Set default console South environment variables if they are not already set Install Console Splitter Print Banner with entry address to make it easy to debug with symbols Install any other integrated device support No need to inform FW as devices appear Create an event to be signaled when ExitBootSer
20. Interrupt None Bus Correctable error Bus Uncorrectable error 8 Revision 1 0 SR870BN4 Error Reference Guide SR870BN4 Machine Check Error Handling PCI Component Critical Interrupt PCI Bus Device Function info PERR SERR Memory Device Memory Error SMBIOS 16 0 based index Correctable SMBIOS Type 17 0 based index Uncorrectable Critical Interrupt Bus Correctable error Bus Uncorrectable error 4 3 Thresholding MCA classifies errors into one of three categories corrected recoverable and fatal In general corrected errors will not affect the operation of the sytem and therefore may occur repeatedly fatal and most recoverable errors result in a system reset In some cases such as a stuck bit in a memory DIMM a corrected error may occur with a very high frequency In this scenario the system may experience a performance degredation due to excessive amounts of time spent in the error logging routines In addition the BMC SEL has a finite size and may be quickly filled with duplicate errors To help alleviate this problems a thresholding agorithm has been applied to the BMC SEL logging routines If the threshold is crossed a special event disabled SEL entry will be created and the the BMC SEL logging code will not attempt to send future platform event message commands for that error type to the BMC This greatly reduces the amount of time spent in the SEL logging routines and avoids overrunning the BMC SEL log storage
21. M specific Bit 7 6 Index to SMBIOS Type16 record Uncorrectable Bit 5 0 Index to SMBIOS Type 17 record Bit 7 6 Index to SMBIOS Type16 record Bit 5 0 Index to SMBIOS Type 17 record PCI Device Specific Bit 7 3 DEV PCI Bus Bit 2 0 Func Bit 7 3 DEV PCI Bus Bit 2 0 Func 0x31 0 4 PCI Bus 0x31 0 4 PCI Bus Processor Bus LPC Bus SP port HL Bus non specific Bus Errors Uncorrectable 0x31 0 4 0x13 N A Ox6F Correctable 0x31 0 4 0x13 N A Ox6F 10 Revision 1 0 SR870BN4 Error Reference Guide SR870BN4 Machine Check Error Handling Event Logging Disabled Bus Correctable Logging Disabled Proc Correctable Logging Disabled PCI PERR Logging System Event MCA Event Indicator 0x31 0 4 0 12 Ox6F OxC3 0x20 0x31 0 4 0 12 Ox6F OxC3 0x00 Revision 1 0 11 SR870BN4 PCI Device IDs SR870BN4 Error Reference Guide 5 SR870BN4 PCI Device IDs The SR870BN4 server has the following PCI devices and slots on the I O board Table 3 Onboard PCI Devices and Slots Device Description PCI Bus Bus Number Device ID Function Number OFF 0 2 1 2 IDE Controller TE orate Fass cit 70 a a 99 2 DW mew 39 Me j oea UNUM UN RN aeee Uma j embedded SCSI Pos BUOM
22. SR870BN4 Error Reference Guide Revision 1 0 n October 2003 5 Enterprise Platforms amp Services Marketing Revision History SR870BN4 Error Reference Guide Revision History Revision Modifications Number 01 2002 Initial Release 04 2002 oe Update Machine Check Error Handling section update SEL data tables 10 2003 Updated sensor and beep code tables Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This documen
23. T Design for Test DFT is a set of design rules whose purpose is to improve platform and system testability Direct Memory Access Differentiated System Description Table An OEM must supply DSDT to an ACPI compatible OS The DSDT contains the Differentiating Definition Block which supplies the implementation and configuration information about the base system DTLB Distributed Translation Lookaside Buffer DWORD Double Word a 32 bit quantity EEPROM Electrically erasable programmable read only memory Error Correction Code Refers to a memory system that has extra bit s to support limited detection correction of memory errors 1024 MB Revision 1 0 l Appendix A Glossary SR870BN4 Error Reference Guide LO Intelligent An open architecture for the development of device drivers in network system environments Intelligent Platform Management Bus Name for the architecture protocol and implementation of a special bus that interconnects the baseboard and chassis electronics and provides a communications media for system platform management information abstracted interfaces to platform management hardware Local Area Network A data communications system which allows a number of independent devices to communicate with each other within a moderate size geographic area Logical Block Address An addressing scheme for accessing sectors on hard drives and other storage devices The LBA method is preferred over the CHS me
24. This thresholding in no way affects the ability of the OS to receive notification and service CPEls or CMCls nor does it disable any error correction logic in the chipset Any disabled event reporting will be re enabled on the next reboot Corrected errors are grouped into four categories Processor Memory PCI PERR and Generic Bus History for each category is maintained separately Recoverable and fatal errors are not thresholded only corrected errors On the SR870BN4 the maximum number of errors that can occur for each category is 10 within one hour If this threshold is crossed a special Event Logging Disabled SEL entry will be logged 4 4 SEL Event Log Format for Machine Check Errors The following table shows the machine check errors that will be logged for the SR870BN4 and the corresponding SEL Event Log format For details on System Management BIOS SMBIOS Type 4 Type 16 and 17 refer to the System Management BIOS Reference Specificaton available on www dmtf org Revision 1 0 9 SR870BN4 Machine Check Error Handling SR870BN4 Error Reference Guide Table 2 SEL Event Logs for Machine Check Errors GenID Sen Data 1 Processor Specific Fatal Index to SMBIOS 0x31 0 4 Type4 record Severity 0x01 Uncorrectable Index to SMBIOS 0x31 0 4 4 Severity 0x00 Correctable Index to SMBIOS 0x31 0 4 4 Severity 0x02 Memory DIM
25. _f_module_12 South By size align and scratch buff size 0 07 5 BSP only Then hang if not found or Information ERROR SAL shadow bottom PELoader SAL_F Find SAL_F page size Align to next 32K boundary and save address and size 0 87 4 BSP only Search for addition information SAL_F module Initialize scratch buffer 0x07F4 BSP only Then hang if not found Else continue by saving in RAM 0x87F3 BSP only Cache flush after SAL shadowed 2 22 Revision 1 0 SR870BN4 Error Reference Guide POST Codes 0x07F3 BSP only Hang on ERROR 0x87F2 BSP only Initialize sal data top address South Physical equals to virtual for runtime use and above 4G Load Call backs for byte word checkpoint display entry and Address SAL PMI address EFI to SAL call back address SAL procedure address SAL SST base and address SAL procudure entry base inside SST Buildtime address where SAL PROC entry is stored Buildtime GP Runtime GP SAL SST size Ox87F 1 BSP only Load PAL module 0x87F0 BSP APs BSP Shadow PAL module initialize PAL shadow base size proc ptr initialize PAL procedure address entry amp checksum AP s PAL PMI base will be set Find of CPU s present in the system of CPU of IOAPIC 0x87EC BSP only Search for addition information EFI module sal efi module 15 South size align and scratch buff size Initialize scratch buffer Ox07EC BSP only Hang if ERROR 0x87EB BSP only Save max
26. case the error is contained i e data poisoning and the platform can still function reliably One example of an uncorrected error is a 2XECC error detected on a write to memory e Machine Check Events A processor machine check occurs when the processor detects a fatal or recoverable error during execution of instructions or when the processor is signaled by the platform to enter machine check Revision 1 0 7 SR870BN4 Machine Check Error Handling SR870BN4 Error Reference Guide There are two types of machine check events local and global A local MCA is when an individual processor enters machine check Some examples of local machine checks include a Distributed Translation Lookaside Buffer DTLB data parity error or when the processor consumes data with an uncorrectable error A machine check is global when all processors enter machine check On the SR870BN4 platform the method used to get all processors into machine check are the BINIT and BERR signals When a processor takes a local machine check it may escalate the error to a global machine check to transition other processors to a known state and or for error containment For example the processor may assert BINIT in response to a transaction time out event The SR870BN4 platform does not assert BINIT only BERR BERR Z is asserted for platform fatal errors and when an uncorrectable error is detected on outbound data For more information on the SR870BN4 implementation
27. ct memory Verify the affected memory and replace with correct memory Verify the affected memory and replace with correct memory Yes Verify the affected memory and replace with like memory Yes Verify the affected memory and replace with like memory Verify the affected memory and replace with like memory Verify the affected memory and replace with like memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Verify the affected memory and replace with good memory Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes es Y Revision 1 0 Recommended User Action SR870BN4 Error Reference Guide BIOS
28. imum PAL EFI shadow size and alignment Save South PAL ia32y EFI shadow top address size alignment EFI module shadow base address virtual Physical size bottom address DATA SAL PAL EFI Update virtual address entries in translation register descriptor addresses in MDT 0x87E8 BSP APs PAL call for PAL test pal_test_proc_ 102 South Ox07E8 BSP APs Hang if late self test ERROR South NOTE this can be skipped by a build switch PAL Call for pal_bus_get_features function pal_bus_get_features_09 0 07 7 BSP APs Hang if ERROR 0x87E6 BSP APs Set buslock mask 1 non atomic South By PAL Call PAL Bus Set Feature pal bus set features 0 07 6 BSP APs Hang if ERROR Revision 1 0 23 POST Codes SR870BN4 Error Reference Guide 0 87 5 BSP APs Set PMI entry point South pen ET 0 87 2 BSP APs pal_mc_register_mem_1b find CPU min state pointer South Should be able now to initialize health bsp ap cache size line size sapic ver and cpuid Set minimal state save area BSPSTORE and SP 0 87 1 BSP APs Cache flush shadow 0x07E1 BSP APs Hang if ERROR 0x87E0 BSP APs Program IVA ITR 0 for PAL SAL runtime code amp data area South cr iva cr ifa cr itir itr rO 0x87DF BSP APs Clear semaphore and wait for all CPUs to synchronize 0x87DE BSP APs Sort CPU health Already sorted for 2nd level BSP selection Store South BSP AP flag for respective CPU
29. in this case 8 1 1 2 Mismatched DIMMs Within Single Row Populated This indicates that only a single row is populated and that row contains mismatched DIMMs preventing booting An SEL log entry will be made in this case Revision 1 0 31 Beep Codes SR870BN4 Error Reference Guide 8 1 2 Recovery Beep Codes Table 16 Recovery Mode Beep Codes 1 short medium tone BIOS Flash Update Started 2 short medium tone BIOS Flash Update Complete Repeating low tone BIOS Recovery Error Occurred 8 1 3 BMC Beep Code Generation The BMC generates beep codes upon detection of the failure conditions listed in Table 17 Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 17 BMC Beep Codes Reason for Beep 1 5 1 1 FRB3 failure processor failure 1 5 2 1 Processor Empty Slot 1 5 2 2 Processor No Processors 32 Revision 1 0 SR870BN4 Error Reference Guide Appendix A Glossary Appendix A Glossary ACPI Advanced Configuration and Power Interface ANSI American National Standards Institute ASCII American Standard Code for Information Interchange An 8 level code 7 bits plus parity check widely used in data processing and data communications systems ASIC Application specific integrated circuit BERR Bus Error Signal This signal can be driven by the platform to interrupt the processor that a platform MCA condition occurred The processor does not reset any internal sta
30. izing the Direct Memory Access DMA controller performing the keyboard South controller BAT test starting memory refresh and entering 4 GB flat mode next 0 0003 Starting memory sizing next 0 0004 Returning to real mode Executing OEM patches and setting up the stack next 0x00D5 Passing control to the uncompressed code in shadow RAM at E000 0000h The South initialization code is copied to segment 0 and control will be transferred to segment O 0 0006 Control is segment 0 If the system BIOS checksum is bad will next go to checkpoint South code EOh Otherwise going to checkpoint code D7h Revision 1 0 25 POST Codes SR870BN4 Error Reference Guide Cod vaue Mos dy 0 000 Next performing required initialization before the keyboard BAT command is issued 0x000C The keyboard controller input buffer is free Next issuing the BAT command to the South keyboard controller 0 000 The keyboard controller BAT command result has been verified Next performing any South necessary initialization after the keyboard controller BAT command test 0x000F The initialization after the keyboard controller BAT command test is done The South keyboard command byte is written next 0x0010 The keyboard controller command byte is written Next issuing the Pin 23 and 24 South blocking and unblocking commands 0x0011 Check for INS key pressed Get POST info 0x0012 Disable DMA controllers 1 and 2 and interrupt controller
31. lity The EFl based SEL Viewer utility is used to view the SEL records from Itanium based servers The SEL Viewer provides support for the user to perform the following Examine all SEL entries stored in the non volatile storage area of the server in text form or in hexadecimal Examine previously stored SEL entries from a file in text form or in hexadecimal Save the SEL entries to a file Clear the SEL entries from the non volatile storage area Sort the SEL records by various fields such as timestamp sensor type number event description and generator ID Five columns of SEL data can be viewed from the EFI SEL Viewer Utility Number of Event Time Stamp Sensor Type and Number Event Description Generator ID aL Co IS SEL Viewer Ver 2 0 File Help Sensor Type amp Number E Reload Clear SEL Voltage H0000000B Voltage H0000000B Uoltage H0000000B Voltage H0000000B Voltage O000000C Voltage H0000000C Voltage H0000000C Pre Init Time Stamp Voltage 0000000 Pre Init Time Stamp Uoltage 0000000D Pre Init Time Stamp Uoltage 0000000D Pre Init Time Stamp Voltage 0000000D Pre Init Time Stamp Voltage 0000000D Pre Init Time Stamp Uoltage 0000000E Pre Init Time Stamp Uoltage 0000000E Pre Init Time Stamp Uoltage 0000000E Pre Init Time Stamp Uoltage 0000000E Pre Init Time Stamp POST Error 00000005 Pre Init Time Stamp Watchdog 2 00000003 Ge TES GC m et lt a E lt
32. mplemented the SR870BN4 platform 4 1 1 Error Types e Fatal A fatal error is an error where the state has been corrupted and the error may or may not be contained The platform will signal a fatal error when the integrity of the platform or subsystem cannot be determined These errors cannot be corrected by hardware firmware or system software and a reset of the system or subsystem is required Recoverable Uncorrectable An error has been detected that cannot be corrected by hardware or firmware However the operating integrity of platform hardware and system state has been maintained These errors may or may not be recoverable determined by system software capabilities e Correctable An error has been detected and corrected by hardware or by processor platform firmware 4 1 2 Error Signaling Corrected Machine Check Interrupt Corrected processor errors are signaled as a CMCI to system software For example L1 tag parity errors on shared lines or thermal events are corrected by the processor logic or the PAL System software must insure that the interrupt handler for executes on the same processor that signaled the corrected error event Corrected Platform Event Interrupt CPEI These interrupts are signaled by the platform or the SAL These include errors that are corrected by the platform such as single bit ECC error in memory and errors that are not correctable by the platform In either
33. of machine check error handling refer to the SR870BN4 SAL Error Handling Specification 4 2 Error Reporting SR870BN4 machine check error handling allows enhanced error reporting of processor and platform errors These errors are prioritized and signaled to system hardware and software System software PAL SAL provides well defined APIs for application software to acquire information about system errors in the form of standard data structures These errors are logged to non volatile storage and or made available for consumption by application software during runtime These errors are the MCA records and they are based on the tanium System Abstraction Layer Specification Rev 3 0 On the SR870BN4 based on the MCA records system events related to Field Replaceable Units FRUS are logged in the BMC SEL Each MCA record results in the generation of one or more corresponding BMC SEL events In addition an auxiliary log entry event will be logged corresponding to each MCA record The SEL messages are IPMI 1 5 compliant platform event messages The following rules are applied to the translation of SAL 3 0 MCA records to IPMI 1 5 compliant platform event messages Table 1 SAL 3 0 MCA Records MCA SAL Record Section Type SEL Event Sensor Type SEL event Event Data Bytes Processor Processor IERR SMBIOS Type 4 0 based index Error Severity PCI Bus PERR SERR Critical Interrupt PCI Bus number PERR SERR PCI Bus Other Errors Critical
34. onveyed with the use of the speaker via encoded beeps coupled with post debug codes Since the duration of the display less POST execution is relatively short there are fewer beep codes than displayed error codes In order to extend the useful range of the beep codes without the need to have dozens of codes the beeps are classified and the distinction within class is made via the post debug card Table 14 Error Beep Codes Beeps Error message Description 3 Memory failure Memory test failure See table below for additional error information 4 System timer System timer is not operational 5 Processor failure Processor failure detected 7 Processor exception interrupt error The processor generated an exception interrupt 8 Display memory read write error The system video adapter is either missing or its memory is faulty This is not a fatal error 9 ROM checksum error System BIOS ROM checksum error 11 Invalid BIOS General BIOS ROM error Table 15 POST Memory Beep Error Codes Debug Port Encoding List Beep Debug port error code lower Code byte of North 2 debug display CF9Fh No valid memory was found in the system CF64h Mismatched DIMMs in a row and no valid memory to boot 8 1 1 Memory Test Failure 8 1 1 1 No Memory Found in the System This indicates that the memory test has found no valid memory in the system The system will not boot An SEL log entry will be made
35. p and set the date and time 0120 CMOS clear Yes user input required Move the CMOS switch to the inactive position 0121 Password clear Yes user input required Move the Password switch to the inactive position 0140 PCI Error Yes Remove add in cards individually to see where error stops If necessary replace I O board 0141 PCI Memory Allocation Error Remove add in cards individually to see where error stops If necessary replace board 0142 PCI IO Allocation Error Remove add in cards individually to see where error stops If necessary replace board 0143 PCI IRQ Allocation Error Remove add in cards individually to see where error stops If necessary replace board 0144 Shadow of PCI ROM Failed Remove add in cards individually to see where error stops If necessary replace board Revision 1 0 13 BIOS POST Error Codes and Messages SR870BN4 Error Reference Guide 0145 PCI ROM not found It can mean valid option ROM bar present but no actual physical option ROM present Informative no user action required Insufficient Memory to Shadow This is due to lack of option PCI ROM ROM space in the BIOS This error can be resolved by disabling all of the option ROMS on all devices except for the boot Error Code Recommended User Action Yes Yes device Processor 01 Internal error IERR Yes user input required Processor signal read by BMC and BIOS gets the information from BMC Indicates ha
36. rdware failure User should replace processor Processor 02 Internal error IERR Yes user input required Processor signal read by BMC and BIOS gets the information from BMC Indicates hardware failure User should replace processor Processor 03 Internal error IERR Yes user input required Processor signal read by BMC and BIOS gets the information from BMC Indicates hardware failure User should replace processor Processor 04 Internal error IERR Yes user input required Processor signal read by BMC and BIOS gets the information from BMC Indicates hardware failure User should replace processor Processor 01 Disabled Yes user input required Retest processor If error persists Replace processor 01 Processor 02 Disabled Yes user input required Retest processor If error persists Replace processor 02 Processor 03 Disabled Yes user input required Retest processor If error persists Replace processor 03 Processor 04 Disabled Yes user input required Retest processor If error persists Replace processor 04 Processor 01 failed FRB level 3 Yes user input required Retest processor If error timer persists Replace processor 01 Processor 02 failed FRB level 3 Yes user input required Retest processor If error timer persists Replace processor 02 Processor 03 failed FRB level 3 Yes user input required Retest processor If error timer persists Replace processor 03 Processor 04 failed FRB level 3 Yes
37. s 1 and 2 0x0013 The video display has been disabled Port B has been initialized Next initializing the chipset 0x0014 The 8254 timer test will begin next 0x0019 The 8254 timer test is over Starting the memory refresh test next 0x001A The memory refresh line is toggling Check the 15 second on off time next 0x0023 Read the 8042 input port and disable the MEGAKEY Green PC feature next Make the South BIOS code segment writable and perform any necessary configuration before initializing the interrupt vectors 0x0024 The configuration required before interrupt vector initialization has completed Interrupt South vector initialization is about to begin 0x0025 Interrupt vector initialization is done Clear the password if the POST DIAG switch is on 0x0027 Any initialization before setting video mode will be done next 0x0028 Initialization before setting the video mode is complete Configuring the monochrome South mode and color mode settings next 0x002A Bus initialization system static and output devices will be done next if present South Starting LAN redirection displaying redirection console message Note that there The convention for the DIM POST codes is as follows South will be 15 bit Port 80 OX2A heus UN Port 81 DIM Function number DI number indicate Device Initialization Manager sub codes 0x002B Passing control to the video ROM to perform any required configuration before the South video ROM test
38. se register test passed Performing the DMA controller 2 base South register test next 0x0065 The DMA controller 2 base register test passed Programming DMA controllers 1 and 2 South next 0 0066 Completed programming DMA controllers 1 2 Initializing the 8259 interrupt South controller next 0x007F TBD South 0x0080 Mouse initialization of PS 2 mouse to program the IRQ level to edge triggered or level South triggered The keyboard test has started Clearing the output buffer and checking for stuck keys Issuing the keyboard reset command next 0x0082 The keyboard controller interface test completed Write the command byte and South initializing the circular buffer next 0 0083 command byte was written and global data initialization has completed Checking South for a locked key next 0x0084 Locked key checking is over Identify ATAPI devices South 0x0089 The programming after Setup has completed Displaying the power on screen South message next 0 008 Init boot devices Check for reset mouse South Sup lO parameters TBD South 0x0098 The adaptor ROM had control and has now returned control to BIOS POST South Performing any required processing after the option ROM returned control Restoring INT10 vector 0x0008 Debugging code South Revision 1 0 27 POST Codes SR870BN4 Error Reference Guide 0x0099 Configuring the timer data area and printer base address 0x009B Returned after setting the
39. supported stepping Use processors with the same stepping e g CO C1 User information typically n and n 1 stepping mixes allowed Use processors that are the same speed CPUID has 3 fields gt stepping family and model If any of the fields mismatch then user would get this message User has to replace processor with the same kind 8196 Processor Models are Different Yes user input required Use processors that are the same speed and stepping 8197 Processor Speed mismatch 8300 Baseboard Management Controller failed to function 84F3 84FF System Event Log Full 8500 Multi bit Error Detected Row1 Row 1 mapped out 8501 Multi bit Error Detected Row2 Row 2 mapped out 8502 8503 Baseboard Management Controller in Update Mode Multi bit Error Detected Row3 Row 3 mapped out Multi bit Error Detected Row4 Row 4 mapped out Revision 1 0 Yes Yes user input required Use processors that are the same speed and stepping Try to reflash the BMC with the most current version that is compatible with your system configuration If problem persists may require board replacement The BMC recovery jumper is in the active position and the BMC can be reflashed After reflashing move the jumper to the inactive position Clear the SEL in BIOS setup Verify the affected memory and replace with correct memory Verify the affected memory and replace with correct memory Verify the affected memory and replace
40. t contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design The SR870BN4 may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Itanium and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Copyright Intel Corporation 2002 Other names and brands may be claimed as the property of others ii Revision 1 0 SR870BN4 Error Reference Guide Table of Contents Table of Contents 1 eret ieiueeE M 1 1 1 Document tpa Eres toolbar tia tte 1 1 2 em 1 2 EFl Based SELViewer hi ia Sc sU iu GE 2 3 SRS OBN4 SEL Data Tables in ER RYE 3 3 1 SR870BN4 Generator ID COdeS ix aeter pte 3 3 2 SR870BN4 S nsoriCodesvx u u u
41. te when it sees a BERR condition The signal causes a global MCA condition For further information see the Itanium Processor Family Error Handling Guide BINIT Bus Initialization Signal This signal can be driven by the processor or platform to indicate a fatal machine check condition The processor and platform will reset internal state in order to ensure the firmware code can be fetched and executed This signal causes a global MCA condition For further information see the tanium Processor Family Error Handling Guide BIOS Basic Input Output System BIST Built In Self Test Baseboard Management Controller Circuitry connecting one computer bus to another allowing an agent on one to access the other Boot Strap Processor C is Bri 2 Chassis Bridge Controller A microcontroller connected to one or more other CBCs Together they bridge the IPMB buses of multiple chassis Challenge Handshake Authentication Protocol Cylinder Head Sector An older addressing scheme for accessing physical sectors on hard drives and other storage devices See LBA CMCI Corrected Machine Check Interrupt CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the baseboard CPEI Corrected Platform Event Interrupt CVDR Configuration Values Driven on Reset A register in the chipset that is accessible by the BMC to control certain system parameters DF
42. thod see CHS because it can address more sectors RR Non maskable Interrupt The highest priority interrupt in the system after SMI This interrupt has traditionally been used to notify the operating system fatal system hardware error conditions such as parity errors and unrecoverable bus errors II Revision 1 0 SR870BN4 Error Reference Guide Appendix A Glossary Platform Event Filtering Platform Event Paging Parity Error A signal on the PCI bus that indicates a parity error on the bus Programmable Interrupt Device The PID is an interrupt controller that provides interrupt steering functions The PID interfaces include a PCI bus an APIC bus and serial IRQ interfaces and an interrupt input interface Processor Information ROM SEEPROM contained in the processor module Contains information about the processor such as the core ratio PLD Programmable Logic Device Platform Management Interrupt System Error A signal on the PCI bus that indicates a fatal error on the bus A two wire interface based on the 2 protocol The SMBus is a low speed bus that provides positive addressing for devices as well as bus arbitration Power on Self Test Simple Network Management Protocol Revision 1 0 Appendix B Reference Documents SR870BN4 Error Reference Guide Appendix B Reference Documents Intelligent Platform Management Interface Specification v1 5 2001 Intel Corporation http developer intel
43. user input required Retest processor If error timer persists Replace processor 04 Processor 01 failed initialization Yes user input required Retest processor If error on last boot persists hardware failure User should replace processor 14 Revision 1 0 SR870BN4 Error Reference Guide BIOS POST Error Codes and Messages Recommended User Action Processor 02 failed initialization on last boot 8151 8152 8153 Processor 03 failed initialization on last boot Processor 04 failed initialization on last boot Yes user input required Yes user input required Yes user input required Retest processor If error persists hardware failure should replace processor Retest processor If error persists hardware failure should replace processor Retest processor If error persists hardware failure should replace processor 8180 BIOS does not support current Yes User should replace processor stepping for Processor 01 with a supported stepping 8181 BIOS does not support current Yes User should replace processor stepping for Processor 02 with a supported stepping 8182 BIOS does not support current stepping for Processor 03 8183 BIOS does not support current stepping for Processor 04 8193 CPUID Processor Steppings are different 8194 CPUID Processor Families are different Yes user input required User should replace processor with a supported stepping User should replace processor with a
44. vices occurs Loop through boot South manager and boot maintenance until a boot option is selected Once the platform code is ready to boot the machine pass control to the boot manager 000 009 Init VGA Bios Device Path South Table 11 ACPI POST Codes Code Value Module Display Ox4F00 Reserved for ACPI South Ox4F Table 12 SAL Runtime POST Codes LIII D 1 OxAFEB Calling OS MCA for Machine Check error handling OxAFEA MCA successfully completed passing control back to PAL Resume OxAFEC Machine Check Handler Processing Rendezvous Request Revision 1 0 29 POST Codes SR870BN4 Error Reference Guide OxAFF4 Not a MP Platform MCA Init condition South OxAFF5 EM OS with no Init Handler or IA 32OS BSP detected Soft Rebooting South No OS Init Handle Registered Checking OS Type South OxAFFD Platform Error PMI Handler is in Control South OxAFFE Platform Flash Management PMI Handler is in Control South OxAFFF Platform Emulation PMI Handler is in Control South OxAF71 Recover Reliable Update verifies the bootblock checksum and corrects if possible South 7 3 Recovery Port 80 Codes Table 13 Recovery POST Codes DUE Value 30 Revision 1 0 SR870BN4 Error Reference Guide Beep Codes 8 Beep Codes During the course of executing POST there are occassions where fatal problems happen before video is enabled These fatal errors are c
Download Pdf Manuals
Related Search