Cypress VCXO CY24713 User's Manual
Contents
1. F CYPRESS CY24713 PERFORM Absolute Maximum Conditions Parameter Description Min Max Unit Vpp Supply Voltage 0 5 7 0 V Ts Storage Temperature 65 125 C Ty Junction Temperature 125 C Digital Inputs Vsg 0 3 Vpp 0 3 V Digital Outputs referred to Vpp Vss 0 3 Vpp 0 3 V Electrostatic Discharge 2000 V Analog Input 0 5 7 0 V Pullable Crystal Specifications Parameter Description Condition Min Typ Max Unit From Nominal crystal frequency Parallel resonance funda 27 MHz mental mode AT cut CiNom Nominal load capacitance 14 pF R4 Equivalent series resistance ESR Fundamental mode 25 Q R3 R4 Ratio of third overtone mode ESR to fundamen Ratio used because typical R4 3 a tal mode ESR values are much less than the maximum spec DL Crystal drive level No external series resistor as 0 5 2 0 mW sumed F35EPHI Third overtone separation from 3 FNoM High side 300 7 ppm F35EPLO Third overtone separation from 3 FNoM Low side 150 ppm Co Crystal shunt capacitance 7 pF Co C4 Ratio of shunt to motional capacitance 180 250 C Crystal motional capacitance 14 4 18 21 6 pF Recommended Operating Conditions Parameter Description Min Typ Max Unit Vpp Operating Voltage 3 135 3 3 3 465 V Ta Ambient Temperature 0 E 70 C CLoap Max Load Capacitance 15 pF tpu Power up time for all VDDs to reach minimum specified voltage power 0 05 500 ms ramps must be mono2. Features m Integrated phase locked loop PLL m Low jitter high accuracy outputs m VCXO with analog adjust m 3 3V Operation CY24713 Benefits m High performance PLL tailored for Set Top Box applications m Meets critical timing requirements in complex system designs m Large 150 ppm range better linearity m Meet industry standard voltage platforms m 8 pin SOIC m Industry standard packaging saves on board space Part Number Outputs Input Frequency Range Output Frequencies CY24713 3 27 MHz pullable crystal input 4 9152 MHz 13 5 MHz 27 MHz per Cypress specification Logic Block Diagram 9 CLK_C 27MHz gy CLK_A4 9152MHz Output Dividers CLK_B13 5MHz K K VDD VSS Pin Configuration Table 1 Pin Definition Figure 1 CY24713 8 Pin SOIC 3 CY24713 Name Number Description XIN 1 Reference Crystal Input VDD 2 3 3V Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLK_B 5 13 5 MHz Clock Output CLK_A 6 4 9152 MHz Clock Output CLK_C 7 27 MHz Clock Output xouTt 8 Reference Crystal Output Note 1 Float Xour if Xy is externally driven Cypress Semiconductor Corporation Document 38 07396 Rev A San Jose CA 95134 1709 408 943 2600 Revised May 22 2008 e 198 Champion Court Feedback J
3. 0 150 3 810 0 157 3 987 5 842 0 2301 0 244 6 197 7 1 DIMENSIONS IN INCHES MM MIN SS y S Ordering Information Ordering Code Package Type CY24713SCl 8 pin SOIC Commercial CY24713SCT4 8 pin SOIC Commercial Pb free CY24713SXC 8 pin SOIC Commercial 3 3V CY24713SXCTMI 8 pin SOIC Tape and Reel Commercial 3 3V CY24713KSXC 8 pin SOIC Commercial 3 3V 8 pin SOIC Tape and Reel Commercial 3 3V Figure 5 8 Lead 150 Mil SOIC S8 MAX 2 PIN 1 ID IS OPTIONAL ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3 REFERENCE JEDEC MS 012 4 PACKAGE WEIGHT 0 07gms PART 08 15 STANDARD PKG Z08 15 LEAD FREE PKG SEATING PLANE 0 189 4 800 0 196 4 978 H oosttt 543 l l 0 068 1 727 1 gt 0 004 0 102 0 050 1 270 BSC a 0 004 0 102 0 8 0 0098 0 249 m 0 0138 0 350 0 0192 0 487 Note 4 Not recommended for new designs Document 38 07396 Rev A eal E 2y Uo S Se T 0 016 0 406 0 035 0 889 51 85066 C 0 010 0 254 y 4go 0 016 0 406 0 0075 0 190 0 0098 0 249 Page 4 of 5 Feedback F Cypress CY24713 PERFORM Document History Page Document Title CY24713 Set top Box Clock Generator with VCXO Document Number 38 07396 REV ECN No Orig of Submission Description of Ch
4. ange Change Date en 333175 RGL See ECN New Data Sheet A 2440886 AESA See ECN Updated template Added Note Not recommended for new designs Added part number CY24713KSXC and CY24713KSXCT in ordering infor mation table Replaced Lead Free with Pb Free Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2005 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written a
5. greement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserve
6. s the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 07396 Rev A Revised May 22 2008 Page 5 of 5 All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
7. tonic DC Electrical Characteristics Parameter Description Conditions Min Typ Max Unit loH Output High Current Vou Vpp 0 5 Vpp 3 3V 12 24 mA lot Output Low Current VoL 0 5 Vpp 3 3V 12 24 mA Cin Input Capacitance 7 pF liz Input Leakage Current 5 7 LA faxo VCXO pullability range 150 at ppm Vvcxo VCXO input range 0 Vpp V lypp Supply Current 25 30 mA Note 2 Rated for 10 years Document 38 07396 Rev A Page 2 of 5 F CY24713 AC Electrical Characteristics Vpp 3 3V Parameter Description Conditions Min Typ Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 3 50 of Vpp 45 50 55 ERo Rising Edge Rate Output Clock Edge Rate Measured from 20 to 0 8 1 4 Vins 80 of Vpp CLoap 15 pF Figure 4 EF Falling Edge Rate Output Clock Edge Rate Measured from 80 to 0 8 1 4 Vins 20 of Vpp CLoap 15 pF Figure 4 tg Clock Jitter Peak Peak period jitter maximum absolute jitter 200 250 ps tio PLL Lock Time 3 ms Figure 2 Test Circuit VDD CLK out 0 1 uF OUTPUTS T CLOAD GND Figure 3 Duty Cycle Definition DC t2 t1 t3 t4 Note 3 Not 100 tested Page 3 of 5 Document 38 07396 Rev A Feedback CYPRESS PERFORM Operating Range CY24713 Operating Voltage 3 3V 3 3V CY24713KSXCT Package Diagram PIN 1 ID A Di
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