Cypress STK22C48 User's Manual
Contents
1. V V Quantum Trap ae CAP 32 X 512 POWER As STORE CONTROL g Ag LLi a RECALL o STORE NN A d on RECALL gt HSB A a lt lt __ CONTROL s _P 32 X 512 As z Qo COLUMN I O 2 COLUMN DEC Q gt a i A elw 5 a r a Q5 fle Ao Ai Az A3 A4 A10 wy Q 6 t ST Q H H Bc CE WE Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document Number 001 51000 Rev Revised January 30 2009 Feedback CYPRESS STK22C48 Pin Configurations Figure 1 Pin Diagram 28 Pin SOIC Vcap 10 28 Vcc NC 2 7 WE A7 3 26 HSB As 4 25 Ag As 5 24 Ag cep 28 SOIC gt o i Top View 7 25 Ae a Not To Scale A Aio A 9 20 CE Ag 10 19 DO7 Dao 1 18 DO6 DO1 12 17 DQ5 DQ2 13 16 _ DO4 Vss 14 15 DQ3 Table 1 Pin Definitions Pin Name Alt IO Type Description Ao Aio Input Address Inputs Used to select one of the 2 048 bytes of the nvSRAM DQ DQ Input or Output Bidirectional Data IO Lines Used as input or output lines depending on opera2. tstor toer POWER UP BROWN OUT BROWN OUT BROWN OUT RECALL NO STORE AutoStore AutoStore NO SRAM WRITES NO RECALL NO RECALL Vcc DID NOT GO BELOW Vneser BELOW Vreser 12 tureca Starts from the time Vcc rises above VgwrrcH 13 CE and OE low for output behavior 14 CE and OE low and WE high for output behavior 15 HSB is asserted low for 1us when Vcap drops through Vswircu If an SRAM Write has not taken place since the last nonvolatile cycle HSB is released and no store takes place Document Number 001 51000 Rev Vcc DID NOT GO RECALL WHEN Vcc RETURNS ABOVE VSWITCH Page 10 of 14 Feedback CYPRESS STK22C48 PERFO Hardware STORE Cycle STK22C48 Parameter Alt Description Unit Min Max tonseg gt l ltagooveR tyHax Hardware STORE High to Inhibit Off 700 ns tpHsB tHLHx Hardware STORE Pulse Width 15 ns tuLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform HSB IN HSB OUT DQ DATA OUT Note Figure 12 Hardware STORE Cycle DATA VALID 16 tpusg is only applicable after tstore is complete Document Number 001 51000 Rev lt truse _ gt bse lt tstore gt lt ther gt HIGH IMPEDANCE HIGH IMPEDANCE lt toeLay gt K X DATA VALID Page 11 of 14 Feedback oF CYPRESS STK22C48 STK22C48 NF451TR Packagi
3. ae z CYPRESS PERFORM Features m 25 ns and 45 ns access times STK22C48 16 Kbit 2K x 8 AutoStore nv SRAM m Hands off automatic STORE on power down with external 68 uF capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software hardware or AutoStore on power down m RECALL to SRAM initiated by software or power up m Unlimited Read Write and Recall cycles m 1 000 000 STORE cycles to QuantumTrap m 100 year data retention to OuantumTrap m Single 5V 10 operation m Commercial and industrial temperatures m 28 pin 300 mil and 330 mil SOIC package m RoHS compliance Functional Description The Cypress STK22C48 is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory A hardware STORE is initiated with the HSB pin Logic Block Diagram
4. 40C005 859C 45VIo55V DC Electrical Characteristics Over the operating range Vcc 4 5V to 5 5V BI Parameter Description Test Conditions Min Max Unit loc1 Average Vcc Current trc 25 ns Commercial 85 mA tro 45ns 65 mA Dependent on output loading and cycle Industrial 90 mA rate Values obtained without output loads 65 mA lout 0 mA loce Average Vcc Current during All Inputs Do Not Care Vcc Max 3 mA STORE Average current for duration tstorE lcca Average Voc Currentattgo IWE gt Voc 0 2V All other inputs cycling 10 mA 200 ns 5V 25 C Typical Dependent on output loading and cycle rate Values obtained without output loads loca Average Vcap Current during All Inputs Do Not Care Voc Max 2 mA AutoStore Cycle Average current for duration tsTORE Iggi l Average Vcc Current trac 25 ns CE gt Viy Commercial 25 mA Standby Cycling TTL Input trc 45 ns CE gt Vi 18 mA Levels Industrial 26 mA 19 mA lego l Voc Standby Current CE gt Vcc 0 2V All others Viy lt 0 2V or gt Voc 0 2V 1 5 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHz liLK Input Leakage Current Voc Max Vss lt Vin lt Voc 1 1 HA lOLK Off State Output Leakage Voc Max Vss lt Vin lt Voc CE or OE gt Vip or WE lt Vi 5 5 A Current Vin Input HIGH Voltage 2 2 Veo V VIL Input
5. EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 51000 Rev Revised January 30 2009 Page 14 of 14 AutoStore and OuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
6. Junction to Case Figure 6 AC Test Loads R1 9630 R1 9630 For Tri state Specs 5 0V 5 0V Output Output 30 pF R2 5 pF R2 5120 5120 AC Test Conditions Input Pulse Levels eeeeeeeseeeeseeeeeeneeeseneeeeeeeeees OV to 3V Input Rise and Fall Times 10 to 90 lt 5ns Input and Output Timing Reference LevelsS 1 5V Note 5 These parameters are guaranteed by design and are not tested Document Number 001 51000 Rev Page 7 of 14 Feedback CYPRESS STK22C48 AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 45 ns Cypress Description p Unit Pa mor Alt Min Max Min Max tACE tELOV Chip Enable Access Time 25 45 ns tro Te tavay teELEH Read Cycle Time 25 45 ns taa 7 tavav Address Access Time 25 45 ns tpoE teLav Output Enable to Data Valid 10 20 ns TOHA UI taxax Output Hold After Address Change 5 5 ns tLZCE 8 tELOX Chip Enable to Output Active 5 5 ns tuzcE BI tEHOZ Chip Disable to Output Inactive 10 15 ns tLZOE Bl teLax Output Enable to Output Active 0 0 ns tuZ0E 8 teHaz Output Disable to Output Inactive 10 15 ns tpu D tELICCH Chip Enable to Power Active 0 0 ns tpp DI tEHICCL Chip Disable to Power Standby 25 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 7 lt trc gt A
7. LOW Voltage Vss 0 5 0 8 V VoH Output HIGH Voltage lout mA except HSB 2 4 V VoL Output LOW Voltage lout 8 mA except HSB 0 4 V VeL Logic 0 Voltage on HSB Output lgyr 3 mA 0 4 V Vcap Storage Capacitor Between Vcap pin and Vss 6V rated 68 UF 10 20 61 220 uF nom Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NVc Nonvolatile STORE Operations 1 000 K Notes 3 Voc reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made or Vcap if VCC is connected to ground 4 CE gt V p does not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 51000 Rev Page 6 of 14 Feedback CYPRESS STK22C48 Capacitance In the following table the capacitance parameters are listed 5 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 C f 1 MHz 8 pF Court Output Capacitance Vcc 0 to 3 0V T pF Thermal Resistance In the following table the thermal resistance parameters are listed Parameter Description Test Conditions 300 mil 350 mil Unit O Thermal Resistance Test conditions follow standard test methods TBD TBD C W Junction to Ambient and procedures for measuring thermal Ojc Thermal Resistance impedance per EIA JESD51 TBD TBD C W
8. 01 51000 Rev Page 12 of 14 Feedback lt l Cypress STK22C48 PERFORM Package Diagrams Figure 13 28 Pin 300 mil SOIC 51 85026 NOTE PIN TID 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE iT i i i i i i i i p 1 MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE a 3 DIMENSIONS IN INCHES MIN 0 291 7 39 MAX 4 PACKAGE WEIGHT 0 85gms 0 300 7 62 0 394 10 01 0 419 10 64 THHHUHTHHUHEHU d _ 28 L a 0 02610 66 528 3 STANDARD PKG 0 032 0 81 SZ28 3 LEAD FREE PKG 069711770 SEATING PLANE 0 713 18 11 f Y a 0 092 2 33 aN lj 0 105 2 67 JL J o o en ae E o o tJ o Oo tJ ian SSS sa gt 0 004 0 10 a L_ 0 0091 0 23 l l 0013033 0 004 0 10 0 015 0 38 0 0125 3 17 0 050 1 27 0 019 0 48 0 0118 0 30 0 050 1 27 Typ 51 85026 D Figure 14 28 Pin 330 mil SOIC 51 85058 PIN 1 ID DIMENSIONS IN INCHESLMMJ MIN MAX PACKAGE WEIGHT 0 79gms 0 460 11 6B4 0 480 12 192 0 338 8 585 PRTH _ _ D 346L8 788 SEATING PLANE 0 720018 298 D 728 18 491 0 094 e2 387 0110 2 794 5 U 0U4LO 1U ES 0050012701 _ __ 0
9. 014 0 355 onon 0 03000 762 __ 0 01200 304 TYP 0 02 000 508 ae 0 050L1 2701 51 85058 A Document Number 001 51000 Rev Page 13 of 14 Feedback CYPRESS STK22C48 PERFORM Document History Page Document Title STK22C48 16 Kbit 2K x 8 AutoStore nvySRAM Document Number 001 51000 ECN No Orig of Submission Rev Change Date Description of Change Gi 2625139 GVCH PYRS 01 30 09 New data sheet Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2006 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cy
10. DDRESS lt LYN I tona DQ DATA OUT DATA VALID gt lt lt Figure 8 SRAM Read Cycle 2 CE and OE Controlled ll tre ADDRESS o lt tace gt tro gt CE lt tizce gt ay OE toor N K tuzoe gt tizoe DQ DATA OUT lt DATA VALID lt tpu ACTIVE icc STANDBY Notes 6 WE and HSB must be High during SRAM Read cycles 7 Device is continuously selected with CE and OE both Low 8 Measured 200 mV from steady state output voltage Document Number 001 51000 Rev Page 8 of 14 Feedback gd cypress STK22C48 SRAM Write Cycle Parameter 25 ns 45 ns Cypress Description 7 Unit Parameter Alt Min Max Min Max twc tavav Write Cycle Time 25 45 ns tpwe WLWH tWLEH Write Pulse Width 20 30 ns tsce teLwu tELEH Chip Enable To End of Write 20 30 ns tsp DVWH DVEH Data Setup to End of Write 10 15 ns tub tWHDx tenpx Data Hold After End of Write 0 0 ns taw tavwu AVEH Address Setup to End of Write 20 30 ns tsa tavw_ taveL Address Setup to Start of Write 0 0 ns tua WHAX EHAX Address Hold After End of Write 0 0 ns tuzwe 2 twLoz Write Enable to Output Disable 10 14 ns tLZWE twHax Output Active After End of Write 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 10 11 I lt t
11. metimes reprogram these values Final NV patterns are Figure 5 Current Versus Cycle Time Write typically repeating patterns of AA 55 00 FF A5 or 5A The end product s firmware should not assume that an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration 80 cold or warm boot status and so on must always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system 60 manufacturing test to ensure these system routines work consistently 100 tive Current mA J 40 m Power up boot firmware routines should rewrite the ny SRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the 20 desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines and so on CMOS Average Ac 50 100 150 200 m The Vcap value specified in this data sheet includes a minimum Cycle Time ns and a maximum value size The best practice is to meet this requirement and not exceed the maximum Vcap value because Preventing Store the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger The STORE function is disabled by holding HSB high with a Vcap value to make sure there is extra store charge should drive
12. nce the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress Pull up this pin with an external 10K ohm resistor to Vcap if HSB is used as a driver SRAM Read and Write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the STK22C48 continues SRAM operations for tpe_ay During tpELAv Multiple SRAM Read operations take place If a Write is in progress when HSB is pulled LOW it allows a time tpg ay to complete However any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH During any STORE operation regardless of how it is initiated the STK22C48 continues to drive the HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK22C48 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Vcc lt Vnesegrv an internal RECALL request is latched When Vcc once again exceeds the sense voltage of Vswitcu a RECALL cycle is automatically initiated and takes tungcALL to complete Document Number 001 51000 Rev STK22C48 Data Protection The STK22C48 protects data from corruption during low voltage co
13. nditions by inhibiting all externally initiated STORE and Write operations The low voltage condition is detected when Vcc is less than Vewitcn If the STK22C48 is in a Write mode both CE and WE are low at power up after a RECALL or after a STORE the Write is inhibited until a negative transition on CE or WE is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK22C48 is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and Vss using leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduce circuit noise Hardware Protect The STK22C48 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage condi tions When Vcap lt Vswitcu all externally initiated STORE operations and SRAM Writes are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to Vcae This is the AutoStore Inhibit mode in this mode STOREs are only initiated_by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK22C48 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 4 shows the relationship between Io and Read or Write cycle time Worst case current consumption is
14. ng Option TR Tape and Reel Blank Tube Temperature Range Blank Commercial 0 to 70 C Industrial 40 to 85 C Speed 25 25 ns 45 45 ns Lead Finish F 100 Sn Matte Tin Package N Plastic 28 pin 300 mil SOIC S Plastic 28 pin 330 mil SOIC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 25 STK22C48 NF25TR 51 85026 28 pin SOIC 300 mil Commercial STK22C48 NF25 51 85026 28 pin SOIC 300 mil STK22C48 SF25TR 51 85058 28 pin SOIC 330 mil STK22C48 SF25 51 85058 28 pin SOIC 330 mil STK22C48 NF25ITR 51 85026 28 pin SOIC 300 mil Industrial STK22C48 NF25l 51 85026 28 pin SOIC 300 mil STK22C48 SF25ITR 51 85058 28 pin SOIC 330 mil STK22C48 SF25l 51 85058 28 pin SOIC 330 mil 45 STK22C48 NF45TR 51 85026 28 pin SOIC 300 mil Commercial STK22C48 NF45 51 85026 28 pin SOIC 300 mil STK22C48 SF45TR 51 85058 28 pin SOIC 330 mil STK22C48 SF45 51 85058 28 pin SOIC 330 mil STK22C48 NF45ITR 51 85026 28 pin SOIC 300 mil Industrial STK22C48 NF45l 51 85026 28 pin SOIC 300 mil STK22C48 SF45ITR 51 85058 28 pin SOIC 330 mil STK22C48 SF45l 51 85058 28 pin SOIC 330 mil All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Document Number 0
15. om the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM Read and Write operations are inhibited The STK22C48 supports unlimited reads and writes similar to a typical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The STK22C48 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ap_ 9 determines the 2 048 data bytes accessed When the Read is initiated by an address transition the outputs are valid after a delay of ta Read cycle 1 If the Read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later Read cycle 2 The data outputs repeatedly respond to address changes within the ta access time without the need for transi tions on any control input pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle The data on the common IO pins DOg_ are written into the memory if it has valid tgp before the end of a WE controlled Write or before the end of an CE c
16. ontrolled Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tuzwe_e after WE goes LOW AutoStore Operation During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswircu the part automatically disconnects the Vc Ap pin from Voc A STORE operation is initiated with power provided by the Vcap capacitor Figure 2 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor between 68 uF and 220 uF 20 rated at 6V should be Document Number 001 51000 Rev STK22C48 Figure 2 AutoStore Mode 10k Ohm NM 10k Ohm V T Vec 2 WE HSB 68 ur 20 6v gt O W F Bypass Vss In system power mode both Vcc and Vcap are connected to the 5V power supply without the 68 uF capacitor In this mode the AutoStore function of the STK22C48 operates on the stored system charge as power goes down The user must however guarantee that Vcc does not drop below 3 6V during the 10 ms STORE cycle To prevent unneeded STORE
17. operations automatic STOREs and those initiated by externally driving HSB LOW are ignored unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle An optional pull up resistor is shown connected to HSB This is used to signal the system that the AutoStore cycle is in progress AutoStore Inhibit mode If an automatic STORE on power loss is not required then Vcc is tied to ground and 5V is applied to Vcap Figure 3 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the STK22C48 is operated in this configuration refer ences to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered with the HSB pin It is not permissible to change between these three options on the fly Page 3 of 14 Feedback CYPRESS Figure 3 AutoStore Inhibit Mode TI Lf Vee Vcc WE HSB 0 10 F Bypass 10k Ohm 10k Ohm Vss Hardware STORE HSB Operation The STK22C48 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin is used to reguest a hardware STORE cycle When the HSB pin is driven LOW the STK22C48 conditionally initiates a STORE operation after tpgLAv An actual STORE cycle only begins if a Write to the SRAM takes place si
18. press products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND
19. r capable of sourcing 30 mA at a Voy of at least 2 2V discuss their Vcap size selection with Cypress because it must overpower the internal pull down device This Table 2 Hardware Mode Selection CE WE B A10 A0 Mode IO Power X Not Selected Output High Z Standby X Read SRAM Output Data Activelll X Write SRAM Input Data Active x Nonvolatile STORE Output High Z local x Ir r zr xx eee ee ee ep Notes a Se 1 I O state assumes OE lt Vi Activation of nonvolatile cycles does not depend on state of OE 2 HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle After the STORE If any completes the part goes into standby mode inhibiting all operations until HSB rises Document Number 001 51000 Rev Page 5 of 14 Feedback CYPRESS STK22C48 Maximum Ratings Voltage on DQo 7 or HSB ue 0 5V to Vcc 0 5V E di ti nr ful life of th Power Dissipation ccccceeeeeeeeeeeeeneeeeeeeeseeeeeeeeees 1 0W xceeding maximum ratings may shorten the useful life of the device Tce user guidelines a not tested DC Output Current 1 output at a time 1s duration 15 mA Storage Temperature eneenieeenn 65 C to 150 C Operating Range ae a ae 5 i o ATE EE R iA a _ o EU ae i me g Commercial 0 C to 70 C 4 5V to 5 5V oltage on Input Relative to Vss 0 6V to Vcc 0 5 Mndusria
20. shown for both CMOS and TTL input levels commercial temper ature range VCC 5 5V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the STK22C48 depends on the following items m The duty cycle of chip enable m The overall cycle rate for accesses m The ratio of Reads to Writes m CMOS versus TTL input levels m The operating temperature m The Vcc level m IO loading Page 4 of 14 Feedback Cypress STK22C48 Figure 4 Current Versus Cycle Time Read device drives HSB LOW for 20 ns at the onset of a STORE When the STK22C48 is connected for AutoStore operation 100 system Vcc connected to Vcc and a 68 uF capacitor on Vcap and Vcc crosses _Vswitcu on the way down the STK22C48 a attempts to pull HSB LOW If HSB does not actually get below Vi the part stops trying to pull HSB LOW and abort the STORE attempt A Average Active Current m Best Practices nvSRAM products have been used effectively for over 15 years T While ease of use is one of the product s main system values 20 experience gained working with hundreds of applications has resulted in the following suggestions as best practices o Saita m The nonvolatile cells in an nvSRAM are programmed on the 50 100 150 200 test floor during final test and quality assurance Incoming Cycle Time ns inspection routines at customer or contract manufacturer s g sites so
21. tion WE Ww Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Voc Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional Voap Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements NC No Connect No Connect This pin is not connected to the die Document Number 001 51000 Rev Page 2 of 14 Feedback CYPRESS Device Operation The STK22C48 nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or fr
22. we i ADDRESS X e tsce gt CE lt taw gt K tsa lt tewe gt WE lt tsp gt lt tho gt DATA IN DATA VALID gt _ lt tizwe gt l lt fone i HIGH IMPEDANCE DATA OUT PREVIOUS DATA Figure 10 SRAM Write Cycle 2 CE Controlled l 1 lt twe gt ADDRESS X 2 lt tsa ce gt lt tua CE lt tw WE N towe tsp gt lt tuo DATA IN DATA VALID DATA OUT HIGH IMPEDANCE Notes 9 If WE is Low when CE goes Low the outputs remain in the high impedance state 10 HSB must be high during SRAM Write cycles 11 CE or WE must be greater than Vj during address transitions Document Number 001 51000 Rev Page 9 of 14 Feedback gd E 7j CYPRES PERFO RM AutoStore or Power Up RECALL STK22C48 Parameter Alt Description S1K22C48 Unit Min Max tHRECALL 12 tRESTORE Power up RECALL Duration 550 us tstore 4 1 tHLHZ STORE Cycle Duration 10 ms DELAY tuLaz tBLOZ Time Allowed to Complete SRAM Cycle 1 us VswitcH Low Voltage Trigger Level 4 0 45 V VRESET Low Voltage Reset Level 3 6 V tvse ll Low Voltage Trigger VswircH to HSB Low 300 ns Switching Waveform Vec Figure 11 AutoStore Power Up RECALL Vaeser AutoStore POWER UP RECALL HSB DQ DATA OUT Notes lt tinecant tse
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