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Cypress Perform CY7C1515KV18 User's Manual

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1. i 333MHz 300MHz 250MHz 200 MHz 167 MHz in Gn Description Unit arameten aramerer Min Max Min Max Min Max Min Max Min Max Output Times tco tcHav CIC Clock Rise or K K in single 045 045 045 045 0 50 ns clock mode to Data Valid tDOH tcHax Data Output Hold after Output C C 0 45 0 45 0 45 0 45 0 50 ns Clock Rise Active to Active tccoo tcHcov C C Clock Rise to Echo Clock Valid 0 451 0 45 0 45 0 45 0 50 ns tcooH tcHcox Echo Clock Hold after C C Clock 0 45 045 045 0 45 0 50 ns Rise Loop tCOHOV Echo Clock High to Data Valid 0 25 0 27 0 30 0 35 0 40 ns tcoDoH tcoHox Echo Clock High to Data Invalid 0 25 0 27 030 0 35 0 40 ns tCOH toouca Output Clock CQ CQ HIGH 5 1251 14 175 225 275 ns tcoucau tcoHCOH CO Clock Rise to CO Clock Rise 125 14 175 225 275 ns rising edge to rising edge tcHz tcHoz Clock C C Rise to le Z 10451 1045 045 045 0 50 ns Active to High Zyl tcLz tcHOX1 Clock C C Rise to Low z 26 27 0 45 0 45 045 045 0 50 ns PLL Timing tke Var tkc Var Clock Phase Jitter 1020 0 20 020 020 0 20 ns Her lock Her lock PLL Lock Time K C 20 20 20 20 20 US tke Reset tkc Reset K Static to
2. Page 8 of 31 Feedback YPRESS PERFORM Ju WWW Single Clock Mode The CY7C1511KV18 is used with a single clock that controls both the input and output registers In this mode the device recognizes only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power on This function is a strap option and not alterable during device operation Concurrent Transactions The read and write ports on the CY7C1513KV18 operate independently of one another As each port latches the address inputs on different clock edges the user can read or write to any location regardless of the transaction on the other port If the ports access the same location when a read follows a write in successive clock cycles the SRAM delivers the most recent information associated with the specified address location This includes forwarding data from a write cycle that was initiated on the previous K clock rise Read access and write access must be scheduled such that one transaction is initiated on any clock cycle If both ports are selected on the same K clock rise the arbitration depends on the previous state of the SRAM If both ports are deselected the read port takes priority If a read wa
3. Depth expansion is accomplished with port selects which enables each port to operate independently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Freguency 333 300 250 200 167 MHz Maximum Operating Current x8 600 560 490 430 380 mA x9 600 560 490 430 380 x18 620 570 500 440 390 x36 850 790 680 580 510 Cypress Semiconductor Corporation Document Number 001 00435 Rev E e 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 30 2009 Feedback ie CY7C1511KV18 CY7C1526KV18 P CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Logic Block Diagram CY7C1511KV18 Dra EE Write Write Write Write Reg Reg gt Reg gt Reg Address Register Lei A20 0 Address Register ZN 21 A2010 GI Kev 9 X IZ ES Kev 8 X NZ Kew 8 X WZ Kew 8 X IZ Control Logic Write Add Decode Read Add Decode gt Read Data Reg Logic Block Diagram CY7C1526KV18 Den ae ae Write Write Write gt Reg gt Reg g
4. 0 50 085x 0 14 z w D s 6 5 4 3 D 0 15 C DES SEATING PLANE 0 36 Document Number 001 00435 Rev E 0 35 0 06 NOTES 1 eco000t00000d O 000000000 ooooooooooo ooooo6ooooo oooooo ooooo ooooooooooo oooooo9oooooo g a IE o gt 6 6 o 8 oooooo ooooo 7 ooooo ooooo ooooooooooo R oooooo ooooo ooooo6ooooo ooooooooooo 0000900008 A Sad Er 10 00 B 4C 18004010 5 0 15 4X SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 A Page 30 of 31 Feedback See CYPRESS PERFORM CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Mh Document History Page Document Title CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72 Mbit QDR II SRAM 4 Word Burst Architecture Document Number 001 00435 Rev ECN No SC ee NN Description of change KR 374703 SYT See ECN New Data Sheet A 1103823 NXR See ECN Updated Ipp spec Updated ordering information table B 1699083 VKN AESA SeeECN Converted from Advance Information to Preliminary C 2148307 VKN AESA SeeECN Changed PLL lock time from 1024 cycles to 20 us Added footnote 21 related to Ipp Corrected
5. CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Identification Register Definitions Value Instruction Field Description CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010011011000100 11010011011001100 11010011011010100 11010011011100100 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unigue 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110
6. Page 3 of 31 Feedback ae a CY7C1511KV18 CY7C1526KV18 Ef CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Pin Configuration The pin configurations for CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 and CY7C1515KV18 follow DI 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1511KV18 8M x 8 1 2 3 4 5 6 7 8 9 10 11 A ca A A WPS NWS K NC 144M RPS A A CO B NC NC NC A NC 288M K NWS A NC NC Q3 NC NC NC Vss A NC A Vss NC NC D3 D NC D4 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q4 VDDQ Vss Vss Vss Vppa NC D2 Q2 F NC NC NC Vino Vin Vss Vs Viena NC NC NC G NC D5 Q5 Vppa Von Vss VoD Vppa NC NC NC H DOFF VRer Vppo Vppa Von Vss VpDD Vppa Vppa VREF ZQ J NC NC NC VDDQ Von Vss Map Vppa NC Q1 D1 K NC NC NC VDDQ Von Vss Me VDDQ NC NC NC L NC Q6 D6 Vppa Vss Vss Vss Vppa NC NC Qo M NC NC NC Vss Vss Vss Vss Vss NC NC DO N NC D7 NC Vss A A A Vss NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1526KV18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WPS NC K NC 144M RPS A A CO B NC NC NC A NC 288M K BWS A NC NC O4 C NC NC NC Vss A NC A Vss NC NC D4 D NC D5 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q5 Vppa Vss Vss Vss Vppa NC D3 Q3 F NC NC NC Vppa Von Vss Ke Vppa NC NC NC G NC D6 Q6 VDDQ Vpp Vss VoD Vppa NC NC NC H DOFF VREF VDDQ VDDQ VDD Vss VD
7. 300MHz x8 560 mA x9 560 x18 570 x36 790 250 MHz x8 490 mA x9 490 x18 500 x36 680 Notes 17 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vu lt Vpp and Vppo lt Vpp 18 Output are impedance controlled lou Vppaq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 19 Output are impedance controlled Io Vppq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 20 Veer min 0 68V or 0 46Vppq whichever is larger Vggr max 0 95V or 0 54Vppq whichever is smaller 21 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 00435 Rev E Page 21 of 31 Feedback Ei CY7C1511KV18 CY7C1526KV18 Ef CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 114 Parameter Description Test Conditions Min Typ Max Unit Ibp 21 Vpp Operating Supply Von Max 200 MHz x8 430 mA E Di oa SC x18 440 x36 580 167MHz x8 380 mA x9 380 x18 390 x36 510 lsB14 Automatic Power Down Max VDD 333 MHz 8 290 mA Current Both Ports Deselected Vin gt Vin or Vin lt Vii x9 290 f fmax 1 tcyc x18 290 Inputs Static x36 290 300 MHz x8
8. Document Number 001 00435 Rev E CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 from the rising edge of the output clock C or C or K or K when in single clock mode To maintain the internal logic each read access must be allowed to complete Each read access consists of four 18 bit data words and takes two clock cycles to complete Therefore read accesses to the device cannot be initiated on two consecutive K clock rises The internal logic of the device ignores the second read reguest Read accesses can be initiated on every other K clock rise Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks C and C or K and K when in single clock mode When the read port is deselected the CY7C1513KV18 first completes the pending read transactions Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the positive output clock C This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the following K clock rise the data presented to D 47 oj is latched and stored into the lower 18 bit write data register provided Du Su o are both asserted active On the subseguent rising edge of the negative input clock K the information pres
9. Test ZO S T Slew Rate 2 V ns RQ e 2500 2500 a INCLUDING JIG AND b SCOPE Note 22 Unless otherwise noted test conditions are based on signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 2500 Vopa 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified Lo Iou and load capacitance shown in a of AC Test Loads and Waveforms Page 23 of 31 Document Number 001 00435 Rev E Feedback Ei CY7C1511KV18 CY7C1526KV18 ES CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Switching Characteristics Over the Operating Range 22 23 Cypress Consortium 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz SEENEN SE Min Max Min Max Min Max Min Max Min Max su tPOWER Vpp Typical to the First Access Di 4 1 1 1 1 ms tcyc tKHKH K Clock and C Clock Cycle Time 3 0 84 3 3 84 4 0 84 5 0 8 4 6 0 8 4 ns tkH tKHKL Input Clock K K C C HIGH 1 20 1 32 161 20 24 ns tkL tKLKH Input Clock KIK C C LOW 1 20 1 32 1 6 2 0 2 4 ns tkHKH tkHKH K Clock Rise to K Clock Rise and C 1 35 1 49 18 22 27 ns to C Rise rising edge to rising edge bauen amp HcH Jk Clock Rise to C C Clock Rise 0 1 30 0 1145 o 18 0 22 0 27 ns rising edge to rising edge Setup Times tsa tAVKH Address Setup to K Clock Rise 04 04 05 06 07 ns
10. 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250 x36 250 AC Electrical Characteristics Over the Operating Range Ha Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage Vner 0 2 V Vu Input LOW Voltage Vner 0 2 V Document Number 001 00435 Rev E Page 22 of 31 Feedback SS CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 PERFORM Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHZ Vpp 1 8V Vppo 1 5V 2 pF Co Output Capacitance 3 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters eee 165 FBGA R Parameter Description Test Conditions Package Unit Ou Thermal Resistance Test conditions follow standard test methods and 13 7 C W Junction to Ambient procedures for measuring thermal impedance in Em Thermal Resistance accordance with EIA JESD51 373 C W Junction to Case Figure 4 AC Test Loads and Waveforms VREF 0 75V Vaerl o 0 75V OUTPUT VREF F e 0 75V R 500 22 ALL INPUT PULSES Device R 500 OUTPUT 1 25V Test Under 5pF 0 25V j Vper 0 75V
11. All synchronous input timing is referenced from the rising edge of the input clocks K and K and all output timing is refer enced to the output clocks C and C or K and K when in single clock mode All synchronous data inputs Dr ml pass through input registers controlled by the input clocks tic and K All synchronous data outputs Op op pass through output registers controlled by the rising See of the output clocks C and C or K and K when in single clock mode All synchronous control RPS WPS BWS pcoj inputs pass through input registers controlled by the rising doe of the input clocks K and K CY7C1513KV18 is described in the following sections The same basic descriptions apply to CYT7C1511KV18 CY7C1526KV18 and CY7C1515KV18 Read Operations The CY7C1513KV18 is organized internally as four arrays of 1M X 18 Accesses are completed in a burst of four seguential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address presented to the address inputs is stored in the read address register Following the next K clock rise the corre sponding lowest order 18 bit word of data is driven onto the Qi17 0 using C as the output timing reference On the subse quent rising edge of C the next 18 bit data word is driven onto the Or47 j This process continues until all four 18 bit data words are dier out onto Onz op The requested data is valid 0 45 ns
12. Nibble Write Select 0 1 Active LOW CY7C1511KV18 Only Sampled on the rising edge of the K NWS Synchronous and K clocks when write operations are active Used to select which nibble is written into the device during the current portion of the write operations NWS controls Dag and NWS controls Dj7 4 All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device BWS Input Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks when BWS Synchronous write operations are active Used to select which byte is written into the device during the current portion BWS of the write operations Bytes not written remain unaltered BWS CY7C1526KV18 BWSp controls D g 0 CY7C1513KV18 BWSo controls Do and BWS controls Du ot CY7C1515KV18 BWSp controls Dio BWS controls Dr ei BWS controls D gt g 4g and BWS3 controls Dr35 27 All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device A Input Address Inputs Sampled on the rising edge of the K clock during active read and write operations These Synchronous address inputs are multiplexed for both read and write operations Internally the device is organized as 8M x 8 4 arrays each of 2M x 8 for CY
13. 00435 Rev E CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when reguired that is while the data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tristate mode The boundary scan register has a special bit located at bit 108 When this scan cell called the extest output bus tristate is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output O bus pins when the EXTEST is entered as the current instruction When HIGH it enables t
14. 6 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode 7 Ensure that when the clock is stopped K K and C C HIGH This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 8 If this signal was LOW to initiate the previous cycle this signal becomes a Don t Care for this operation 9 This signal was HIGH on previous K clock rise Initiating consecutive read or write operations on consecutive K clock rises is not permitted The device ignores the second read or write request Document Number 001 00435 Rev E Page 10 of 31 Feedback CY7C1511KV18 CY7C1526KV18 CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Write Cycle Descriptions The write cycle description table for CY7C1511KV18 and CY7C1513KV18 follows D 10 BWSy BWS SE K K Comments NWSp NWS L L L H During the data portion of a write sequence CY7C1511KV18 both nibbles Dr ol are written into the device CY7C1513KV18 both bytes Dial are written into the device L L LH During the data portion of a write sequence CY7C1511KV18 both nibbles Dro are written into the device CY7C1513KV18 both bytes Dio are written into the device L H L H During the data portion of a write sequence CY7C1511KV18 only the lower nibble Dr ol is written into the device Dr A remain
15. A Vss NC NC D1 P NC NC Q17 A A C A A NC DO Qo R TDO TCK A A A C A A A TMS TDI CY7C1515KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CO NC 288M A WPS BWS K BWS RPS A NC 144M CO B Q27 Q18 D18 A BWS K BWS A D17 Q17 Q8 e D27 Q28 D19 Vss A NC A Vss D16 Q7 D8 D D28 D20 Q19 Vss Vss Vss Vss Vss Q16 D15 D7 E Q29 D29 Q20 Vina Vss Vss Vss VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ Von Vss VER Bes D14 Q14 Q5 G D30 D22 Q22 Vena Von Vss Vor Vena Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 Von Vpp Vss Vpp Vane D12 Q4 D4 K Q32 D32 Q23 VDDQ Me Vss Vpp VDDa Q12 D3 Q3 L Q33 Q24 D24 Moes Vss Vss Vss Wna D11 Ou Q2 M D33 Q34 D25 Vss Vss Vss Vss Vss D10 Q1 D2 N D34 D26 Q25 Vss A A A Vss Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 DO QO R TDO TCK A A A C A A A TMS TDI Document Number 001 00435 Rev E Page 5 of 31 Feedback CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 PERFORM Pin Definitions Pin Name VO Pin Description Dix 0 Input Data Input Signals Sampled on the rising edge of K and K clocks when valid write operations are active Synchronous CY7C1511KV18 Do CY7C1526KV 18 Dm CY7C1513KV18 D 47 0 CY7C1515KV18 D g5 0 WPS Input Write Port Select Active LOW Sampled on the rising edge of the K clock When asserted active a Synchronous write operation is initiated Deasserting deselects the write port Deselecting the write port ignores Dop NWSo Input
16. Architecture Configurations CY7C1511KV18 8M x 8 CY7C1526KV18 8M x 9 CY7C1513KV18 4M x 18 CY7C1515KV18 2M x 36 Functional Description The CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 and CY7C1515KV18 are 1 8V Synchronous Pipelined SRAMs equipped with ODR II architecture ODR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations ODR II architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common IO devices Each port can be accessed through a common address bus Addresses for read and write addresses are latched on alternate rising edges of the input K clock Accesses to the ODR II read and write ports are independent of one another To maximize data throughput both read and write ports are equipped with DDR interfaces Each address location is associated with four 8 bit words CY7C1511KV18 9 bit words CY7C1526KV18 18 bit words CY7C1513KV18 or 36 bit words CY7C1515KV18 that burst seguentially into or out of the device Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds
17. C of the QDR II In the single clock mode CO is generated with respect to K The timings for the echo clocks are shown in the Switching Characteristics on page 24 ZO Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CG CO and O x 0 output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Allermatively this pin can be connected directly to Vopa which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timings in the PLL turned off operation differs from those listed in this data sheet For normal operation this pin is connected to a pull up through a 10 KO or less pull up resistor The device behaves in ODR I mode when the PLL is turned off In this mode the device can be operated at a freguency of up to 167 MHz with ODR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M N A Not Connected to the Die Can be tied to any voltage level NC 288M N A Not Connected to the Die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Reference measur
18. Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 00435 Rev E Page 18 of 31 Feedback Boundary Scan Order PERFORM CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Bit Bump ID Bit Bump ID Bit Bump ID Bit ff Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 OF 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number 001 00435 Rev E Page 19 of 31 Feedback ap a CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 PERFORM Power Up Sequence in QDR II SRAM
19. connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and can be performed when the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 00435 Rev E CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 16 Upon power up the instruction register is loaded with the IDCODE instruction lt is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data
20. embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited w
21. 01 00435 Rev E Page 28 of 31 Feedback PERFORM Table 2 Ordering Information continued CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Ordering Code CY7C1511KV18 167BZC CY7C1526KV18 167BZC CY7C1513KV18 167BZC CY7C1515KV18 167BZC Package Diagram 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Package Type CY7C1511KV18 167BZXC CY7C1526KV18 167BZXC CY7C1513KV18 167BZXC CY7C1515KV18 167BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Operating Range Commercial CY7C1511KV18 167BZI CY7C1526KV18 167BZI CY7C1513KV18 167BZI CY7C1515KV18 167BZI CY7C1511KV18 167BZXI CY7C1526KV18 167BZXI CY7C1513KV18 167BZXI CY7C1515KV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Industrial Document Number 001 00435 Rev E Page 29 of 31 Feedback PERFORM Package Diagram CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Figure 6 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW x PIN 1 CORNER D Kb 15 000 110 gt o Ss Er e Bt 13004010 0 5340 05 H 40 MAX 1025C BOTTOM VIEW PIN 1 CORNER i 9005MC oo2smER B
22. 7C1511KV18 8M x 9 4 arrays each of 2M x9 for CY7C1526KV18 4M x 18 4 arrays each of 1M x 18 for CY7C1513KV18 and 2M x 36 4 arrays each of 512K x 36 for CY7C1515KV18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C1511KV18 and CY7C1526KV 18 20 address inputs for CY7C1513KV18 and 19 address inputs for CY7C1515KV18 These inputs are ignored when the appropriate port is deselected Opco Outputs Data Output Signals These pins drive out the reguested data when the read operation is active Valid Synchronous data is driven out on the rising edge of the C and C clocks during read operations or K and K when in single clock mode On deselecting the read port Or o are automatically tristated CY7C1511KV18 Or o CY7C1526KV18 Ojg 0 CY7C1513KV18 O 17 0 CY7C1515KV18 Q735 0 RPS Input Read Port Select Active LOW Sampled on the rising edge of positive input clock K When active a Synchronous read operation is initiated Deasserting deselects the read port When deselected the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the C clock Each read access consists of a burst of four seguential transfers C Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board ba
23. A1 then data Q20 D10 O21 D11 Q22 D12 and Q23 D13 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 00435 Rev E Page 26 of 31 Feedback PERFORM Ordering Information CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 The following table lists all possible speed package and temperature range options supported for these devices Note that some options listed may not be available for order entry To verify the availability of a specific option visit the Cypress website at www cypress com and refer to the product summary page at http www cypress com products or contact your local sales representative for the status of availability of parts Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at http app cypress com portal server pt space CommunityPage amp control SetCommunity amp CommunityID 201 amp PageID 230 Table 2 Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 333 CY7C1511KV18 333BZC CY7C1526KV18 333BZC CY7C1513KV18 333BZC CY7C1515KV18 333BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1511KV18 333BZXC CY7C1526KV18 333BZXC CY7C1513KV18 333BZXC CY7C1515KV18 333BZXC 51 85180 165 Ball Fine Pit
24. D VDDQ VDDQ VREF ZQ J NC NC NC Vppa Vop Vss Mee Vppa NC Q2 D2 K NC NC NC Vppa Mag Vss Me Vppa NC NC NC L NC Q7 D7 VDDQ Vss Vss Vss Vppa NC NC Q1 M NC NC NC Vss Vss Vss Vss Vss NC NC D1 N NC D8 NC Vss A A A Vss NC NC NC P NC NC Q8 A A C A A NC DO OO R TDO TCK A A A C A A A TMS TDI Note 1 NC 144M and NC 288M are not connected to the die and can be tied to any voltage level Document Number 001 00435 Rev E Page 4 of 31 Feedback ae a CY7C1511KV18 CY7C1526KV18 Ef CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Pin Configuration continued The pin configurations for CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 and CY7C1515KV18 follow D 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1513KV18 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A CO NC 144M A WPS BWS K NC 288M RPS A A CO B NC Q9 D9 A NC K BWSg A NC NC Q8 c NC NC D10 Vss A NC A Vss NC Q7 D8 D NC D11 Q10 Vss Vss Vss Vss Vss NC NC D7 E NC NC Q11 Vena Vss Vss Vss Veen NC D6 Q6 F NC Q12 D12 Maes Von Vss Me Vena NC NC Q5 G NC D13 Q13 Vine Ve Vss Von Nope NC NC D5 H DOFF VRer Vppo Vppa Von Vss VpDD Vppa Vppa VREF ZQ J NC NC D14 Mea Vpp Vss Vpp VDDQ NC Q4 D4 K NC NC Q14 Moes Vpp Vss Man VDDa NC D3 Q3 L NC Q15 D15 Vna Vss Vss Vss VpDO NC NC Q2 M NC NC D16 Vss Vss Vss Vss Vss NC Q1 D2 N NC D17 Q16 Vss A A
25. HF LM SN device These user guidelines are not tested Latch up Current nn ek ee ee ee ee ee gt 200 mA Storage Temperature iese se ee ee 65 C to 150 C Operating Range Ambient Temperature with Power Applied 55 C to 125 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Range Temperature TA VpD Ha Vppo 17 Supply Voltage on Vppo Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 18 0 1V 1 4V to DC Applied to Outputs in High Z 0 5V to Vppa 0 3V Industrial 40 C to 85 C VDD DC Input Voltage 7 0 5V to Vpp 0 3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range 14 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V Vppa IO Supply Voltage 1 4 1 5 Vpp V VoH Output HIGH Voltage Note 18 Vppo 2 0 12 Vppol2 0 12 V VoL Output LOW Voltage Note 19 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lop 0 1 mA Nominal Impedance Vppa 0 2 VDDQ V Vouown Output LOW Voltage lon 0 1 mA Nominal Impedance Vss 0 2 V Vu Input HIGH Voltage Vner 0 1 Vppa t 0 3 V Vu Input LOW Voltage 0 3 Vner 0 1 V ly Input Leakage Current GND lt VI lt Vppq 5 5 HA loz Output Leakage Current GND VI lt Vppa Output Disabled 5 5 HA VREF Input Reference Voltage DT Typical Value 0 75V 0 68 0 75 0 95 V lbp 21 Vpp Operating Supply Von Max 333 MHz x8 600 mA ei SC o E x18 620 x36 850
26. K Document Number 001 00435 Rev E Page 15 of 31 Feedback ies CY7C1511KV18 CY7C1526KV18 3 CY7C1513KV18 CY7C1515KV18 PERFORM TAP Controller Block Diagram pm 0 Bypass Register B2170 mn Selection TDO p Selection TDI Instruction Register Circuitry Ee EA ee Circuitry m 34 30129393 12 1 0 gt Identification Register 2 1 0 gt l p gt 108 Boundary Scan Register it ft tt II TAP Controller TCK TMS p TAP Electrical Characteristics Over the Operating Range 12 13 14 Parameter Description Test Conditions Min Max Unit Mou Output HIGH Voltage lop 2 0 mA 1 4 V VoH2 Output HIGH Voltage lop 100 HA 1 6 V Vou Output LOW Voltage lon 2 0 mA 0 4 V VoL Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vu Input LOW Voltage 0 3 0 35Vpp V ly Input and Output Load Current GND lt Vi lt Vpp 5 5 uA Notes 12 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 13 Overshoot Viy AC lt Vppa 0 85V Pulse width less than tcyc 2 Undershoot VI AC gt 1 5V Pulse width less than tcyc 2 14 All voltage referenced to Ground Document Number 001 00435 Rev E Page 16 of 31 Feedb
27. N CLKIN or Source K ASIC Source Kit Delayed KAMMA Delayed K WN R R 50ohms Vt Vddq 2 Truth Table The truth table for CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 and CY7C1515KV18 follows Z 3 4 5 6 7 Operation K RPS wPs DO DO DO DO Write Cycle L H HIS L BI D A at K t 1 D A 1 at K t 1 D A 2 at K t 2 T D A 3 at K t 2 Load address on the rising edge of K input write data on two consecutive K and K rising edges Read Cycle LH L I x o A atC t 1 O A 1 at C t 2 A 2 at C t 2 T Q A 3 at C t 3 Load address on the rising edge of K wait one and a half cycle read data on two consecutive C and C rising edges NOP No Operation L H H H D X D X D X D X O High Z Q High Z Q High Z Q High Z Standby Clock Stopped Stopped X A Previous State Previous State Previous State Previous State Notes 2 X Don t Care H Logic HIGH L Logic LOW tT represents rising edge 3 Device powers up deselected with the outputs in a tristate condition 4 A represents address location latched by the devices when transaction was initiated A 1 A 2 and A 3 represents the address sequence in the burst 5 t represents the cycle at which a read write operation is started t 1 t 2 and t 3 are the first second and third clock cycles respectively succeeding the t clock cycle
28. PERFORM Features m Separate Independent Read and Write Data Ports mn Supports concurrent transactions m 333 MHz Clock for High Bandwidth m 4 word Burst for Reducing Address Bus Frequency m Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 666 MHz at 333 MHz m Two Input Clocks K and K for precise DDR Timing a SRAM uses rising edges only m Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches m Echo Clocks CO and CQ simplify Data Capture in High Speed Systems m Single Multiplexed Address Input Bus latches Address Inputs for Read and Write Ports m Separate Port Selects for Depth Expansion m Synchronous Internally Self timed Writes m QDR II operates with 1 5 Cycle Read Latency when DOFF is asserted HIGH m Operates similar to ODR I Device with 1 Cycle Read Latency when DOFF is asserted LOW m Available in x8 x9 x18 and x36 Configurations m Full Data Coherency providing Most Current Data m Core VpD 1 8V 0 1V IO VDDQ 1 4V to VpD a Supports both 1 5V and 1 8V IO supply m Available in 165 ballFBGA Package 13 x 15 x 1 4 mm m Offered in both Pb free and non Pb free Packages m Variable Drive HSTL Output Buffers m JTAG 1149 1 Compatible Test Access Port m Phase Locked Loop PLL for Accurate Data Placement Table 1 Selection Guide CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72 Mbit ODR M II SRAM 4 Word Burst
29. PLL Constraints m PLL uses K clock as its synchronizing input The input must ODR II SRAMs must be powered up and initialized in a have low phase jitter which is specified as tke var predefined manner to prevent undefined operations m The PLL functions at frequencies down to 120 MHz m If the input clock is unstable and the PLL is enabled then the Power Up Sequence PLL may lock onto an incorrect frequency causing unstable m Apply power and drive DOFF either HIGH or LOW All other inputs can be HIGH or LOW SRAM behavior To avoid this provide 20 us of stable clock to a Apply Vpp before Vppg relock to the desired clock freguency a Apply Vppo before VREr or at the same time as VREF a Drive DOFF HIGH m Provide stable DOFF HIGH power and clock K K for 20 us to lock the PLL Figure 3 Power Up Waveforms Fw I II AO AE E K K ul kk wl us y a EE E Unstable Clock gt 20us Stable clock gt Start Beet Operation Clock Start Clock Starts after Vpp Vppq Stable Ra Fix HIGH or tie to Ypo DOFF Page 20 of 31 Document Number 001 00435 Rev E Feedback a CY7C1511KV18 CY7C1526KV18 Sag CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Maximum Ratings Current into Outputs OW 20 mA Exceeding maximum ratings may impair the useful life of the EN B
30. PLL Reset 30 30 30 30 30 ns Notes 25 These parameters are extrapolated from the input timing parameters tcyc 2 250 ps where 250 ps is the internal jitter These parameters are only guaranteed by design and are not tested in production 26 tcuz tcLz are specified with a load capacitance of 5 pF as in b of AC Test Loads and Waveforms Transition is measured 100 mV from steady state voltage 27 At any voltage and temperature toyz is less than touz and touz less than too Document Number 001 00435 Rev E Page 25 of 31 Feedback CY7C1511KV18 CY7C1526KV18 CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Ju Wey C3 Switching Waveforms Figure 5 Read Write Deselect Sequence 28 29 30 NOP READ WRITE READ WRITE NOP 1 2 3 4 5 6 7 a a N RPS ar MTH CLL ws WMD TA VI TL A a Y lC Yl UU E 5 D LLL Wh e G O O01 Weer age O21 tco tCQDOH t La CHZ_ bel i eal tCLZ 1 i tKHCH 1 La 1 1 i i e et CCOO tcaqoH LI CCOO e LE i FAX SE t CQHCQH ee R a A AAAA DON T CARE NN UNDEFINED Notes 28 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO that is A071 29 Outputs are disabled High Z one clock cycle after a NOP 30 In this example if address A2
31. Y7C1515KV18 250BZC Package Diagram 51 85180 Package Type 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CYT7C1511KV18 250BZXC CY7C1526KV18 250BZXC CY7C1513KV18 250BZXC CY7C1515KV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Operating Range Commercial CY7C1511KV18 250BZI CY7C1526KV18 250BZI CY7C1513KV18 250BZI CY7C1515KV18 250BZI CY7C1511KV18 250BZXI CY7C1526KV18 250BZXI CY7C1513KV18 250BZXI CY7C1515KV18 250BZXI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Industrial 200 CY7C1511KV18 200BZC CY7C1526KV18 200BZC CY7C1513KV18 200BZC CY7C1515KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1511KV18 200BZXC CY7C1526KV18 200BZXC CY7C1513KV18 200BZXC CY7C1515KV18 200BZXC CY7C1511KV18 200BZI CY7C1526KV18 200BZI CY7C1513KV18 200BZI CY7C1515KV18 200BZI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C1511KV18 200BZXI CY7C1526KV18 200BZXI CY7C1513KV18 200BZXI CY7C1515KV18 200BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 0
32. a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The TAP controller clock can only operate at a freguency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock freguencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001
33. ack PERFORM TAP AC Switching Characteristics Over the Operating Range 5 16 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Parameter Description Min Max Unit trcyc TCK Clock Cycle Time 50 ns trr TCK Clock Freguency 20 MHz tru TCK Clock HIGH 20 ns Fo TCK Clock LOW 20 ns Setup Times tryss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise ns Hold Times trMsH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Output Times ttpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 16 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 1 8V 0 9V TDO OV Zoe L c 20 pF a GND tty tre ca e e Test Clock 7 TCK treyc tysH rm trMss Lal a a Test Mode Select TMS WK YG trpis i TDIH ep m HEK DER TDI Test Data Out TDO 4 JE trpov o trpox Notes 15 tcs and tcp refer to the setup and hold time requirements of latching data from the bou 16 Test conditions are specified using the load in TAP AC Test Conditions ta tr 1 ns Document Number 001 00435 Rev E ndary scan register Page 17 of 31 Feedback PERFORM
34. bed in Identification Register Definitions on page 18 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 18 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 13 of 31 Feedback PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is
35. ch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Commercial CY7C1511KV18 333BZl CYT7C1526KV18 333BZl CY7C1513KV18 333BZl CY7C1515KV18 333BZl 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1511KV18 333BZXI CY7C1526KV18 333BZXI CY7C1513KV18 333BZXI CYT7C1515KV18 333BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 300 CY7C1511KV18 300BZC CY7C1526KV18 300BZC CY7C1513KV18 300BZC CY7C1515KV18 300BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1511KV18 300BZXC CY7C1526KV18 300BZXC CY7C1513KV18 300BZXC CY7C1515KV18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1511KV18 300BZI CY7C1526KV18 300BZI CY7C1513KV18 300BZI CY7C1515KV18 300BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1511KV18 300BZXI CY7C1526KV18 300BZXI CY7C1513KV18 300BZXI CY7C1515KV18 300BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 00435 Rev E Page 27 of 31 Feedback PERFORM Table 2 Ordering Information continued CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Ordering Code CY7C1511KV18 250BZC CY7C1526KV18 250BZC CY7C1513KV18 250BZC C
36. ck to the controller See Application Example on page 10 for further details C Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See Application Example on page 10 for further details K Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Op o when in single clock mode All accesses are initiated on the rising edge of K K Input Clock Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and to drive out data through Or o when in single clock mode Document Number 001 00435 Rev E Page 6 of 31 Feedback CY7C1511KV18 CY7C1526KV18 CYPRESS CY7C1513KV18 CY7C1515KV18 PERFOR M Pin Definitions continued Pin Name VO Pin Description CO Echo Clock CO Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the QDR II In the single clock mode CO is generated with respect to K The timings for the echo clocks are shown in the Switching Characteristics on page 24 ca Echo Clock ca Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data
37. e provided on the ODR II to simplify data capture on high speed systems Two echo clocks are generated by the ODR II CQ is referenced with respect to C and CO is referenced with respect to C These are free running clocks and are synchro nized to the output clock of the QDR II In the single clock mode CQ is generated with respect to K and CQ is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 24 PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the PLL is locked after 20 us of stable clock The PLL can_also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the PLL to lock to the desired frequency The PLL automatically locks 20 us after a stable clock is presented The PLL may be disabled by applying ground to the DOFF pin When the PLL is turned off the device behaves in ODR I mode with one cycle latency and a longer access time Page 9 of 31 Feedback CY7C1511KV18 CY7C1526KV18 CYPRESS CY7C1513KV18 CY7C1515KV18 PERFORM Application Example Figure 1 shows four QDR II used in an application Figure 1 Application Example CQ CQ Q C CH K K WWW DATA IN DATA OUT Address RPS BUS WPS MASTER BWS CPU CLKI
38. ement points Von Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the Device Vppa Power Supply Power Supply Inputs for the Outputs of the Device Document Number 001 00435 Rev E Page 7 of 31 Feedback YPRESS PERFORM Ju WWW Functional Overview The CYT7C1511KV18 CY7C1526KV18 CYTC1513KV18 CY7C1515KV18 are synchronous pipelined Burst SRAMs with a read port and a write port The read port is dedicated to read operations and the write port is dedicated to write operations Data flows into the SRAM through the write port and flows out through the read port These devices multiplex the address inputs to minimize the number of address pins reguired By having separate read and write ports the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of four 8 bit data transfers in the case of CY7C1511KV18 four 9 bit data transfers in the case of CY7C1526KV18 four 18 bit data transfers in the case of CY7C1513KV18 and four 36 bit data transfers in the case of CY7C1515KV18 in two clock cycles This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vss then device behaves in ODR I mode with a read latency of one clock cycle Accesses for both ports are initiated on the positive input clock K
39. ented to Dr47 p is also stored into the write data register provided DU Dr o are both asserted active This process continues for one more cycle until four 18 bit words a total of 72 bits of data are stored in the SRAM The 72 bits of data are then written into the memory array atthe specified location Therefore write accesses to the device cannot be initiated on two consecutive K clock rises The internal logic of the device ignores the second write reguest Write accesses can be initiated on every other rising edge of the positive input clock K Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When deselected the write port ignores all inputs after the pending write operations are completed Byte Write Operations Byte write operations are supported by the CY7C1513KV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature is used to simplify read modify or write operations to a byte write operation
40. f a write sequence only the byte D 47 gj is written into the device De o and Droe remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 4gj is written into the device Du and Da527 remains unaltered H H L H L H During the data portion of a write sequence only the byte Dps 1ap is written into the device Dr47 j and Djg5 27 remains unaltered H H H L L H During the data portion of a write sequence only the byte D 35 27 is written into the device De o remains unaltered H H H L L H During the data portion of a write sequence only the byte Dras277 is written into the device De o remains unaltered LH _ No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 00435 Rev E Page 12 of 31 Feedback YPRESS PERFORM Ju Oud C3 IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature lt is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and
41. he output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit is set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output O bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 14 of 31 Feedback PERFORM TAP Controller State Diagram 11 The state diagram for the TAP controller follows 4 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 TEST LOGIC a RESET d 1 TEST LOGIC 1 SELECT SELECT L gt M IDLE DR SCAN IR SCAN f d d 1 CAPTURE DR CAPTURE IR 0 0 SHIFT DR ad SHIFT IR 0 N y 1 gt EXIT1 DR gt EXIT1 IR d N PAUSE DR PAUSE IR 0 N 0 EXIT2 DR EXIT2 IR y Y UPDATE DR UPDATE IR 1 0 Note N 11 The 0 1 next to each state represents the value at TMS at the rising edge of TC
42. ithout the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 00435 Rev E Revised March 30 2009 Page 31 of 31 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
43. may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram on page 15 TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 18 The output changes on the falling edge of TCK TDO is
44. ritten into the device during this portion of a write operation H LH No data is written into the device during this portion of a write operation Note 10 Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWSg NWS4 BWSpg BWS BWS gt and BWS can be altered on different portions of a write cycle as long as the setup and hold reguirements are achieved Document Number 001 00435 Rev E Page 11 of 31 Feedback Write Cycle Descriptions PERFORM CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 The write cycle description table for CY7C1515KV18 follows 2 101 BWS BWS BWS BWS K K Comments L L L L LH During the data portion of a write sequence all four bytes rs ol are written into the device L L L L L H During the data portion of a write sequence all four bytes Dras o are written into the device L H H H L H During the data portion of a write sequence only the lower byte Djg oj is written into the device Droe o remains unaltered L H H H L H During the data portion of a write sequence only the lower byte Dra op is written into the device Drea remains unaltered H L H H LH During the data portion of a write sequence only the byte Du al is written into the device De o and Di35 1a remains unaltered H L H H L H During the data portion o
45. s initiated on the previous cycle the write port takes priority as read operations cannot be initiated on consecutive cycles If a write was initiated on the previous cycle the read port takes priority as write operations cannot be initiated on consecutive cycles Therefore asserting both port selects active from a deselected state results in alter nating read or write operations being initiated with the first access being a read Depth Expansion The CY7C1513KV18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the positive input clock only K Each port select input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write are completed before the device is deselected Document Number 001 00435 Rev E CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM the allowable range of RQ to guarantee impedance matching with a tolerance of 415 is between 175Q and 3500 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks ar
46. s unaltered CY7C1513KV18 only the lower byte Dr o is written into the device Dj17 9 remains unaltered L H L H During the data portion of a write sequence CY7C1511KV18 only the lower nibble Dr ol is written into the device Dr A remains unaltered CY7C1513KV18 only the lower byte Dr ou is written into the device D 7 o remains unaltered H L L H During the data portion of a write sequence CY7C1511KV18 only the upper nibble Dr CY7C1513KV18 only the upper byte UD H L L H During the data portion of a write sequence CYT7C1511KV18 only the upper nibble Dr CY7C1513KV18 only the upper byte D H H L H No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation is written into the device Dro remains unaltered is written into the device Dr a remains unaltered is written into the device Drag remains unaltered is written into the device Djg o remains unaltered Write Cycle Descriptions The write cycle description table for CY7C1526KV18 follows 101 BWS K K L LH During the data portion of a write sequence the single byte Drg o is written into the device L L H During the data portion of a write sequence the single byte Djg oj is written into the device H LH No data is w
47. t Reg Write Reg Address Register ZN A 20 0 Address Register LN 21 A2010 Control VI Kev 6 X ING ES Kev 6 X ING Kev 6 X ING Kev 6 X ING Write Add Decode Read Add Decode DOFF VREF LO WPS Control Ser 9 BWSr g agi Us o Document Number 001 00435 Rev E Page 2 of 31 Feedback PERFORM CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Logic Block Diagram CY7C1513KV18 18 D 17 0 Address 20 A 19 0 Register ZS K gt DOFF VREF WPS gt Control Logic Write Add Decode Write Write Write Write gt Reg gt Reg gt Reg gt Reg Aeuv 84 X WL Aeuv 84 Wl Aeuv 8b Wl Reu 8b X Wl Read Add Decode gt Read Data Reg A 19 0 Logic Block Diagram CY7C1515KV18 36 D 35 0 Address Register 19 A 18 0 Control Logic Document Number 001 00435 Rev E Write Add Decode Write Write Write Write P Reg gt Reg gt Reg gt Reg Reu 9E X MZLS Reu 9 X YZLS Reu 9 X ATIG Reu 9 X MZLS Read Add Decode gt Read Data Reg A 18 0 tr co a6 gt O a5 0
48. through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that is placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions are used to capture the contents of the input and output ring The Boundary Scan Order on page 19 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information descri
49. tsc tiVKH Control Setup to K Clock Rise 04 04 05 06 07 ns RPS WPS tSCDDR tivKH Double Data Rate Control Setup to 0 3 03 035 04 05 ns Clock K K Rise BWS BWS BWS BWS3 tsp tOVKH Do Setup to Clock K K Rise 0 3 03 035 04 05 ns Hold Times tHA tHAX Address Hold after K Clock Rise 04 104 05 06 07 ns tuc tkHIX Control Hold after K Clock Rise 04 041 05 06 07 ns RPS WPS tucppR tkHIx Double Data Rate Control Hold after 0 3 0 3 035 04 05 ns Clock K K Rise BWSp BWS BWS BWS3 HD tkHDx Djx 0 Hold after Clock K K Rise 0 3 0 3 035 04 05 gt ns Notes 23 When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range 24 This part has a voltage regulator internally tpower is the time that the power must be supplied above Vpp minimum initially before a read or write operation is initiated Document Number 001 00435 Rev E Page 24 of 31 Feedback PERFORM Switching Characteristics continued Over the Operating Range 22 23 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18
50. typo in the footnote 25 D 2606839 VKN PYRS 11 13 08 Changed JTAG ID 31 29 from 001 to 000 Updated power up seguence waveform and its description Changed Ambient Temperature with Power Applied from 10 C to 85 C to 55 C to 125 C in the Maximum Ratings on page 21 Included Thermal Resistance values Changed the package size from 15 x 17 x 1 4 mm to 13 x 15 x 1 4 mm E 2681899 VKN PYRS 04 01 2009 Converted from preliminary to final Added note on top of the Ordering Information table Moved to external web Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2005 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry

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