Cypress Perform CY62136EV30 User's Manual
Contents
1. le ec A B ld E D o E E E F G H A B 4 6004000 4 rol 2 v n E S oa B le 8 E X 3 E ui zj Iu V SEATING PLANE i a 0 26 MAX Jr Document 38 05569 Rev B 1 00 MAX CY62136EV30 MoBL BOTTOM VIEW A1 CORNER 0 05 M T go25MCAB 0 30 0 05 48X 6 5 4 3 2 J x L 2 6o602o0npdo Ja Y 1 9 00000 fs K OOO OoOO lc e 3 OOOlOOO Jo f OOO OOO e d B OOOOOO fF OOO OOO e t 1 l eooloee n A 1 875 0 75 3 75 B m 6000 10 1 4 0 15 4X 51 85150 D Page 10 of 12 Feedback CY62136EV30 YPRESS MoBL9 PERFORM Package Diagrams continued 44 pin TSOP II 51 85087 DIMENSIDN IN MM CINCH MAX MIN 22 gt fn 11 938 470 z g gt 10 262 0 404 EJECTOR PIN TOP VIEW BOTTOM VIEW 10 262 0 404 10058 0 396 BASE PLANE i 0 396 0 210 0 008 ui 0120 0 00475 0 10 004 gt 0 03155 LA A 0 800 JUNI F 0 300 TER 18517 D 0 597 0 00355 SEATING A BEANN 51 85087 A 1194 0 0475 0 0395 0 150 0 0059 0 99 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document may be the trademarks of their respe2. to 198 Champion Court Removed 35ns Speed Bin Removed L version of CY62136EV30 Changed lcc Max value from 2 mA to 2 5 mA and Icc Typ value from 1 5 mA to 2 mA at f 1 MHz Changed Icc Typ value from 12 mA to 15 mA at f fmax Changed Isp and Igpo Typ values from 0 7 pA to 1 uA and Max values from 2 5 uA to 7 pA Changed the AC test load capacitance from 50pF to 30pF on Page 4 Changed Vpg from 1 5V to 1V on Page 4 Changed IccpR from 2 5 uA to 3 uA Added lccpg typical value Changed ton tLzce and tj zwg from 6 ns to 10 ns Changed t zgg from 6 ns to 5 ns Changed t zog from 3 ns to 5 ns Changed tHZOE tuZcE tuzpe and tyzwe from 15 ns to 18 ns Changed tsce taw and taw from 40 ns to 35 ns Changed tpwe from 30 ns to 35 ns Changed tsp from 20 ns to 25 ns Corrected typo in the Truth Table on Page 9 Updated the package diagram 48 pin VFBGA from B to D Updated the ordering Information table and replaced the Package Name column with Package Diagram B 427817 See ECN NXR Minor change Moved datasheet to external web Document 38 05569 Rev B Page 12 of 12 Feedback
3. then data from I O pins l Og through I 07 is written into the location specified on the address pins Ag through A46 If Byte High Enable BHE is LOW then data from I O pins l Og through l O 5 is written into the location specified on the address pins Ag through A46 Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins will appear on l Og to I O7 If Byte High Enable BHE is LOW then data from memory will appear on l Og to 1 045 See the truth table at the back of this data sheet for a complete description of read and write modes Logic Block Diagram DATA IN DRIVERS A10 Ag Ag A Ac As 128K x 16 un pos A gt A3 Ao n A1 gt Ao RAM Array COLUMN DECODER HIE y lt t ROW DECODER SENSE AMPS lt gt Og 1 O D gt gt l Og O45 CER CE j LOE Note 1 For best practice recommendations please refer to the Cypress application note System Design Guidelines on http www cypress com Cypress Semiconductor Corporation Document 38 05569 Rev B 198 Champion Court San Jose CA
4. 16 CE tpp tACE tHZCE OE LN HIGH HIGH IMPEDANCE 77 IMPEDANCE CC cc DATA VALID NNSNNNN lizcE tpu Vec lcc SUPPLY 50 50 CURRENT Isp Notes 14 The device is continuously selected OE CE Vi BHE and or BLE Vi 15 WE is HIGH for read cycle ae es 16 Address valid prior to or coincident with CE and BHE BLE transition LOW Document 38 05569 Rev B Page 6 of 12 Feedback CY62136EV30 MoBL PERFORM Switching Waveforms continued 151 Write Cycle No 1 WE Controlled 17 18 X SSS Veet twc taw tHA tsa iPwE BEEBEE NS tew BULLA oara o ROE LO tHZOE Write Cycle No 2 CE Controlled 17 18 twc Ius YEE E tsa taw tHa i NSSSN BREE NS is ow 10 RET MI Ko tHZOE tpwe Notes 17 Data I O is high impedance if OE Vi 18 If CE goes HIGH simultaneously with WE Vip the output remains in a high impedance state 19 During this period the I Os are in output state and input signals should not be applied Document 38 05569 Rev B Page 7 of 12 Feedback E CY62136EV30 amp Z CYPRESS MoBL PERFORM Switching Waveforms continued 15 Write Cycle No 3 WE Controlled OE LOW 8 twc D OK cr SSS MLL LLL BHE BLE SN a y tsa ipwE WE AX paTauio NOTE f QO nvm KX XX tHZWE zwE Write Cycle No 4 BHE BLE Controlled OE Low 8 twc
5. 95134 1709 e 408 943 2600 Revised January 6 2006 Feedback CY62136EV30 CYPRESS MoBL PERFORM Pin Configuration VFBGA Top View 44 TSOP II Top View BOO Dm S 8 GO i s EIA e QN e ONDEE o9 389 690909 F iege 8909 e 9 8 69096 A Product Portfolio Power Dissipation Speed Operating ICC mA Product Vcc Range V ns f 1MHz f fmax Standby Ispo uA Min Typ Max Typ Max Typ Max Typ Max CY62136EV30LL 2 2 3 0 3 6 45 2 2 5 15 20 1 7 Notes 2 NC pins are not connected on the die 3 Pins D3 H1 G2 and H6 in the BGA package are address expansion pins for 4 Mbit 8 Mbit 16 Mbit and 32 Mbit respectively 4 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vecityp TA 25 C Document 38 05569 Rev B Page 2 of 12 Feedback CY62136EV30 CYPRESS MoBL9 PERFORM Maximum Ratings DC Input Voltagel 8l 0 3V to 3 9V Voc max 0 3V Above which the useful life may be impaired For user guide upal uneni into Outputs LOW 20 mA lines not test
6. CE CE gt Vcc 0 2V 1 7 uA Power down Vin Voc 0 2V or Viy lt 0 2V f 0 Current CMOS Vcc 3 60V Inputs Capacitance for all packages Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 f 2 1 MHz 10 pF Cour Output Capacitance Vcc Vecityp 10 pF Notes 5 Vit min 2 0V for pulse durations less than 20 ns 6 ViH max Vcc 0 75V for pulse durations less than 20ns 7 Full Device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after Voc stabilization 8 Tested initially and after any design or process changes that may affect these parameters Document 38 05569 Rev B Page 3 of 12 Feedback CY62136EV30 CYPRESS MoBL PERFORM Thermal Resistance VFBGA TSOP Il Parameter Description Test Conditions Package Package Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch two layer 75 77 C W Junction to Ambient I printed circuit board Oje Thermal Resistance 10 13 C W Junction to Case 8 AC Test Loads and Waveforms R1 ALL INPUT PULSES Voc Vcc e 90 OUTPUT 10 GND 30 pF R2 Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING JIGAND L Equivalent to THEVENIN a isi SRODE OUTPUT e we Vai Parameters 2 50V 3 0V Unit R1 16667 1103 Q R2 15385 1554 Q RTH 8000 645 Q VIH 1 20 1 75 V Data Retention Characteristics
7. ADDRESS S tsa Document 38 05569 Rev B Page 8 of 12 Feedback CY62136EV30 CYPRESS MoBL PERFORM Truth Table CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X High Z Deselect Power down Standby lag L X X H H High Z Output Disabled Active loc L H L L L Data Out 1 Oo l 045 Read Active loc L H L H L Data Out 1 Oo l 07 Read Active Icc l Og I O45 in High Z L H L L H Data Out l Og l O 5 Read Active lcc l Og 1 O in High Z L H H L L High Z Output Disabled Active lec L H H H L High Z Output Disabled Active lec L H H L H High Z Output Disabled Active Icc L L X L L Data In l Og l Oi5 Write Active lcc L L X H L Data In 1 Oo l 07 Write Active loc l Og l O s in High Z L L X L H j Data In 1 O8 l 0O15 Write Active lcc l Og 1 O in High Z Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62136EV30LL 45BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free Industrial CY62136EV30LL 45ZSXI 51 85087 44 pin Thin Small Outline Package II Pb free Please contact your local Cypress sales representative for availability of other parts Document 38 05569 Rev B Page 9 of 12 CYPRESS PERFORM Package Diagrams TOP VIEW A1 CORNER l T2 2 4 3 48 pin VFBGA 6 x 8 x 1 mm 51 85150
8. CY62136EV30 MoBL9 PERFORM Features Very high speed 45 ns Wide voltage range 2 20V 3 60V Pin compatible with CY62136CV30 Ultra low standby power Typical standby current 14A Maximum standby current 74A Ultra low active power Typical active current 2 mA f 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed power Offered in a Pb free 48 ball VFBGA and 44 pin TSOP II packages 2 Mbit 128K x 16 Static RAM Functional Description The CY62136EV30 is a high performance CMOS static RAM organized as 128K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption by 80 when addresses are not toggling The device can also be put into standby mode reducing power consumption by more than 99 when deselected CE HIGH The input output pins l Og through 1 O45 are placed in a high impedance state when deselected CE HIGH outputs are disabled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or during a write operation CE LOW and WE LOW Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW
9. Over the Operating Range l 9 Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 0 V lccpn Data Retention Current Vcc 1 0V 0 8 3 pA CE gt Voc 0 2V Vin gt Voc 0 2V or VIN lt 0 2V tcp Chip Deselect to Data 0 ns Retention Time tg il Operation Recovery inc ns Time Data Retention Waveform DATA RETENTION MODE Vpn 1 0V Notes 9 Full device operation requires linear Vcc ramp from Vpr to Vcc min 100 us or stable at Vcc min 100 us Document 38 05569 Rev B Page 4 of 12 7 CYPRESS PERFORM Switching Characteristics Over the Operating Range 11 12 13 CY62136EV30 MoBL 45 ns Parameter Description Min Max Unit Read Cycle tnc Read Cycle Time 45 ns tAA Address to Data Valid 45 ns lOHA Data Hold from Address Change 10 ns tace CE LOW to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to LOW Zl 5 ns tuzoE OE HIGH to High Zl 12 18 ns lizcE CE LOW to Low ZI 10 ns tuzcE CE HIGH to High ZI 121 18 ns tpy CE LOW to Power Up 0 ns tpp CE HIGH to Power Down 45 ns tope BLE BHE LOW to Data Valid 22 ns lizBE BLE BHE LOW to Low Z 1 5 ns tuzBE BLE BHE HIGH to HIGH zl 12 18 ns Write Cyclel l twc Write Cycle Time 45 ns tsce CE LOW to Write End 35 ns taw Address Set Up to Write End 35 ns tHa Address Hold from Write En
10. ctive holders Document 38 05569 Rev B Page 11 of 12 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PER FQ RM Document History Page CY62136EV30 MoBL Document Title CY62136EV30 MoBL 2 Mbit 128K x 16 Static RAM Document Number 38 05569 REV ECN NO Issue Date Orig of Change Description of Change A 237432 419988 See ECN See ECN AJU RXU New Data Sheet Converted from Advanced Information to Final Changed the address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street
11. d 0 ns tsa Address Set Up to Write Start 0 ns tpwe WE Pulse Width 35 ns tew BLE BHE LOW to Write End 35 ns tsp Data Set Up to Write End 25 ns tup Data Hold from Write End 0 ns tuzwE WE LOW to High Zl 12 18 ns tLzwe WE HIGH to Low z 10 ns Notes 10 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of Voc ypy 2 input pulse levels of 0 to Vecityp and output loading of the specified lo Ioy as shown in the AC Test Loads and Waveforms section 11 At any given temperature and voltage condition tyzc is less than tj zcg tyzpe is less than tj zgg tyzoe is less than tj zog and tyzwe is less than tj zwg for any given device 12 tuzog tuzce tyzBe and tyzwe transitions are measured when the outputs enter a high impedence state 13 The internal Write time of the memory is defined by the overlap of WE CE Vi BHE and or BLE Vj All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input set up and hold timing should be referenced to the edge of the signal that terminates the write Document 38 05569 Rev B Page 5 of 12 Feedback CY62136EV30 CYPRESS MoBL Switching Waveforms 15 Read Cycle 1 Address Transition Controlled 15 inc ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 5
12. ed Static Discharge Voltage n gt 2001V Storage Temperature 65 C to 150 C pet MIE STD eee Method oda Ambient Temperature with Latch up Current aoe gt 200 mA Power Applied 55Cto 125 Operating Range Supply Voltage to Ground Ambient Potential ssusse 0 3V to 3 9V Vcc max 0 3V Device Range Temperature Vcc DC Voltage Applied to Outputs CY62136EV30LL Industrial 40 C to 85 C 2 2V 3 6V in High Z Statel 9l 0 3V to 3 9V Voc max 0 3V Electrical Characteristics Over the Operating Range gt 7 45 ns Parameter Description Test Conditions Min Typ 4 Max Unit Vou Output HIGH lon 2 70 1 mA Vgc 2 20V 2 0 V Voltage lou 1 0mA Vec 2 70V 24 V VoL Output LOW lg 0 1 mA Vcc 2 20V 0 4 V Voltage loL 21mA Veg 2 70V 0 4 V Vin Input HIGH Voltage Voc 2 2V to 2 7V 1 8 Voc 0 3 V Voec 2 7V to 3 6V 2 2 Vec 0 3 V Vit Input LOW Voltage Vcg 2 2V to 2 7V 0 3 0 6 V Voec 2 7V to 3 6V 0 3 0 8 V lix Input Leakage GND lt VI lt Vcc 1 1 pA Current loz Output Leakage GND lt Vo lt Vcc Output Disabled 1 1 pA Current loc Voc Operating f fMAX l tac Voc Vocmax lout 0 mA 15 20 mA Supply Current f 1MHz CMOS levels 2 25 Isp1 Automatic CE CE gt Vcc 0 2V 1 7 uA Power down Viu Vcc 0 2V Vins0 2V Current CMOS f fmax Address and Data Only Inputs f 2 0 OE and WE Vec 3 60V Ispo Automatic
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