Cypress Perform CY14B102N User's Manual
Contents
1. lt tstore gt lt tstore gt t RECALL l lt Document Number 001 45524 Rev A 24 Read and Write cycles are ignored during STORE RECALL and while VCC is below Page 12 of 20 Feedback _ CYPRESS PERFORM ADVANCE CY14E108L CY14E108N Switching Waveforms continued Figure 10 CE Controlled Software STORE RECALL Cyclel7 A tac gt ADDRESS 1 lac ADDRESS ADDRESS 6 K srone trecau 4 HIGH IMPEDANCE DQ DATA DATA VALID DATA VALID Figure 11 OE Controlled Software STORE RECALL Cyclel 7 lt fac lt tac ADDRESS gt lt ADDRESS 1 X j ADDRESS 6 j M Am tas lt tow OE p tonax lt tstore tnecALL gt DQ DATA DATA VALID DATA VALID HIGH IMPEDANCE I j Document Number 001 45524 Rev A Page 13 of 20 Feedback ADVANCE PERFORM Switching Waveforms continued Figure 12 Hardware STORE 0 amp 3 HIGH IMPEDANCE HSB IN tstore HSB OUT HIGH IMPEDANCE DQ DATA OUT DATA VALID DATA VALID Figure 13 Soft Sequence Processing 19 CYPRESS CY14E108L CY14E108N t gt Soft Sequence Command tss Soft Sequence C2. 45ns access speed for both industrial and Commecial temperature Grade Updated Thermal resistance values for 48 FBGA 44 TSOP 54 TSOP II packages Changed tcw value from 16ns to 15ns Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com 2 05 psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for
3. tuzee gt tuz DQ DATA OUT bc DATA VALID gt lt tpu gt ACTIVE STANDBY Figure 7 SRAM Write Cycle 1 WE Controlled 3 21 22 23 twc ADDRESS SCE CE lt taw gt We iu lt tewe gt lt tew gt BHE BLE lt tsp gt lt tap gt DATA IN DATA VALID lt tuzwe lt HIGH IMPEDANCE DATA OUT PREVIOUS DATA ADVANCE CY14E108L CY14E108N Notes 22 CE or WE must be gt during address transitions 23 BHE and BLE are applicable for x16 configuration only Document Number 001 45524 Rev A Page 11 of 20 Feedback CY14E108L CY14E108N LR ADVANCE PERFORM Switching Waveforms continued Figure 8 SRAM Write Cycle 2 CE Controlled 3 21 22 23 twe gt ADDRESS lt tsa N tsce CE n tia gt lt taw gt WE x N towe 4 lt gt BHE BLE tew tsp gt tup DATA IN DATA VALID DATA OUT HIGH IMPEDANCE Figure 9 AutoStore or Power Up 241 STORE occurs only No STORE occurs without atleast one SRAM write Voc if a SRAM write has happened AutoStore POWER UP RECALL Read amp Write Inhibited Y Y gt
4. AC Switching Characteristics In the following table the AC switching characteristics are listed CY14E108L CY14E108N Parameters 20 ns 25 ns 45 ns Description Unit Pana s Te i SRAM Read Cycle tACE tACS Chip Enable Access Time 20 25 45 ns RU thc Read Cycle Time 20 25 45 ns tL taa Address Access Time 20 25 45 ns tpoE toE Output Enable to Data Valid 10 12 20 ns loHA toH Output Hold After Address Change 3 3 3 ns a tiz Chip Enable to Output Active 3 3 3 ns 4l tuz Chip Disable to Output Inactive 8 10 15 ns 1 21 toiz Output Enable to Output Active 0 0 0 ns 4 Output Disable to Output Inactive 8 10 15 ns tp Chip Enable to Power Active 0 0 0 ns 10170 tps Chip Disable to Power Standby 20 25 45 ns tppE Byte Enable to Data Valid 10 12 20 ns tLzBE E Byte Enable to Output Active 0 0 0 ns tuzpE Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle twc twc Write Cycle Time 20 25 45 ns tpwe twp Write Pulse Width 15 20 30 ns tcw Chip Enable To End of Write 15 20 30 ns tsp tpw Data Setup to End of Write 8 10 15 ns tup Data Hold After of Write 0 0 0 ns taw taw Address Setup to End of Write 15 20 30 ns tsa tas Address Setup to Start of Write 0 0 0 ns tua twn Address Hold After End of Write 0 0 0 ns Es Write Enable to Out
5. PERFORM ADVANCE CY14E108L CY14E108N 8 Mbit 1024K x 8 512K x 16 nvSRAM Features 20 ns 25 ns and 45 ns access times m Internally organized as 1024K x 8 CY14E108L or 512K x 16 CY14E108N m Hands off automatic STORE on power down with only a small capacitor m STORE to QuantumTrap nonvolatile elements initiated by software device pin or AutoStore on power down m RECALL to SRAM initiated by software or power up m Infinite read write and recall cycles m 200 000 STORE cycles to QuantumTrap m 20 year data retention m Single 5V 10 operation m Commercial and industrial temperatures m 48 pin FBGA 44 and 54 pin TSOP II packages m Pb free and RoHS compliance Functional Description The Cypress CY14E108L CY14E108N is a fast static RAM with a nonvolatile element in each memory cell The memory is organized as 1024K words of 8 bits each or 512K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL operations are also available under software co
6. charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswircn the part automatically disconnects the Vcap pin from A STORE operation is initiated with power provided by the Vcap capacitor Figure 3 shows the proper connection of the storage capacitor Vcap for automatic store operation Refer to the section DC Electrical Characteristics on page 7 for the size of Vcap Document Number 001 45524 Rev A ADVANCE CY14E108L CY14E108N To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress Figure 3 AutoStore Mode Vcc M M 0 1uF Vcc 10kOhm CAP Vcap IE s il Hardware STORE Operation The CY14B108L CY14B108N provides the HSB pin to control and acknowledge the STORE operations Use the HSB pin to request a hardware STORE cycle When the HSB pin is driven LOW the CY14B108L CY14B108N conditionally initiates a STORE operation after Ay An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle The HSB pin also acts as an open drain dri
7. 4V This parameter is characterized but not tested Document Number 001 45524 Rev A Page 7 of 20 Feedback EC C ADVANCE CYPRESS CY14E108L CY14E108N adi PERFORM Capacitance In the following table the capacitance parameters are listed 9 Parameter Description Test Conditions Max Unit Input Capacitance Ty 25 C f 1 MHz 14 pF Cour Output Capacitance Voc 0 to 3 0V 14 pF Thermal Resistance In the following table the thermal resistance parameters are listed 9 Parameter Description Test Conditions 48 FBGA 44 TSOP Il 54 TSOP Il Unit Thermal Resistance Test conditions follow standard test methods 28 82 31 11 30 73 C W Junction to Ambient and procedures for measuring thermal Osc Thermal Resistance impedance in accordance with EIA JESD51 7 84 5 56 6 08 C W Junction to Case Figure 4 AC Test Loads 9630 9630 for tri state specs 5 0V 5 0V R1 R1 OUTPUT OUTPUT R2 5120 30 pF T AC Test Conditions Input Pulse Levels a OV to 3V Input Rise and Fall Times 10 90 lt 5 ns Input and Output Timing Reference Levels 1 5V Note 9 These parameters are guaranteed but not tested Document Number 001 45524 Rev A R2 5 pF 5120 Page 8 of 20 Feedback a 9 3 gt 2 CYPRESS PERFORM ADVANCE
8. 51 85160 Se DIMENSION IN MM CINCH 38 MIN MAX ole at 22 313 0878 Gi DETAIL W 22517 0 8865 27 1 mr LLEECECLELELCLELELELELELELELELELELELELELELELE LE LLL ELE EZ 46 IO Ne eux xp x lt iO e gg ipy HHUUBUUHUUUUUUUHUUUUUUUUUUUU 44 28 54 L 095 0374 105 00413 R O12 0 005 MINS OMIN R O12 0 0055 025 0 0105 0 300 0 012 025 0 800 0 4000 0165 7 0318 GAUGE PLANE 120 lt 0 0472MAX3 t qa cH i 1 oe 0045 0358 iode gets 22 313 0 8785 0450 0 00595 22 517 0 8865 SEATING PLANE 0 406 0 0160 0 597 0 08355 DETAIL A 51 85160 Document Number 001 45524 Rev A Page 19 of 20 Feedback ADVANCE ES CYPRESS CY14E108L CY14E108N PERFORM Document History Page Document Title CY14E108L CY14E108N 8 Mbit 1024K x 8 512K x 16 nvSRAM Document Number 001 45524 Submission Orig of a REV ECN NO Date Change Description of Change 2428826 See ECN GVCH New Data Sheet 2520023 06 23 08 GVCH PYRS Updated Icc for tRC 20ns 25ns
9. AutoStore is re enabled by initiating an AutoStore enable sequence A sequence of read operations is performed in a manner similar to the software RECALL initiation To initiate the AutoStore enable sequence the following sequence of CE controlled read operations must be performed Read address 0x4E38 Valid READ Read address 0xB1C7 Valid READ Read address 0x83E0 Valid READ Read address 0x7C1F Valid READ Read address 0x703F Valid READ Read address 0 4 46 AutoStore Enable GQ Document Number 001 45524 Rev A If the AutoStore function is disabled or re enabled a manual STORE operation hardware or software must be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Data Protection The CY14E108L CY14E108N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when Vcc lt Vswircrn If the CY14E108L CY14E108N is in a write mode both CE and WE LOW at power up after a RECALL or STORE the write is inhibited until a negative transition on CE or WE is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations Refer CY Application Note AN1064 Page 6 of 20 Feedback UE ADVANCE art 2 CYP
10. Commercial CY14E108L ZSP25XCT 51 85160 54 pin TSOP II Commercial CY14E108L ZSP25XIT 51 85160 54 pin TSOP II Industrial CY14E108L ZSP25XI 51 85160 54 pin TSOP II CY14E108N BA25XCT 51 85128 48 ball FBGA Commercial CY14E108N BA25XIT 51 85128 48 ball FBGA Industrial CY14E108N BA25XI 51 85128 48 ball FBGA CY14E108N ZSP25XCT 51 85160 54 pin TSOP II Commercial CY14E108N ZSP25XIT 51 85160 54 pin TSOP II Industrial CY14E108N ZSP25XI 51 85160 54 pin TSOP II Document Number 001 45524 Rev A Page 15 of 20 Feedback ADVANCE T CYPRESS CY14E108L CY14E108N PERFORM Ordering Information continued poen Ordering Code Package 45 14 1081 2545 51 85087 44 pin TSOP II Commercial CY14E108L ZS45XIT 51 85087 44 pin TSOP II Industrial CY14E108L ZS45XI 51 85087 44 pin TSOP II CY14E108L BA45XCT 51 85128 48 ball FBGA Commercial CY14E108L BA45XIT 51 85128 48 ball FBGA Industrial CY14E108L BA45XI 51 85128 48 ball FBGA CY14E108L ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14E108L ZSP45XIT 51 85160 54 pin TSOP II Industrial 14 1081 75 45 51 85160 54 TSOP II CY14E108N BA45XCT 51 85128 48 ball FBGA Commercial CY14E108N BA45XIT 51 85128 48 ball FBGA Industrial CY14E108N BA45XI 51 85128 48 ball FBGA CY14E108N ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14E108N ZSP45XIT 51 85160 54 pin TSOP II Industrial
11. use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described h
12. 3 i i __ St 0 120 0 0047 I 004 i T 18517 0729 0 597 0 0235 18313 0 721 0 406 0 0160 PLANE 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 51 85087 A Document Number 001 45524 Rev A Page 17 of 20 Feedback A ADVANCE Cypress CY14E108L CY14E108N PERFORM Package Diagrams continued Figure 15 48 ball FBGA 6 mm x 10 mm x 1 2 mm 51 85128 OP VIEW BOTTOM VIEW CORNER 90 05 MC V g025 MCA CORNER N 00 30 0 05 48 8 6 6 5 4 3 N A B T OOO OOO 3 p 4 18 jp E t F F 2 R G OOOOOO G H t i ooo n A A 1 875 zi B 4 6 00 0 10 0 75 3 75 A B r 6 00 0 10 3 p A 0 15 4 X An lt NZ X XZ Y SEATING PLANE od S s 51 85128 D Document Number 001 45524 Rev A Page 18 of 20 Feedback ADVANCE LPA CYPRESS CY14E108L CY14E108N PERFORM Package Diagrams continued Figure 16 54 Pin TSOP II
13. CY14E108N ZSP45XI 51 85160 54 pin TSOP II All parts are Pb free The above table contains Advance information Please contact your local Cypress sales representative for availability of these parts Part Numbering Nomenclature CY 14 E 1081 25 P20X CT NVSRAM 14 Auto Store Software Store Hardware Store Cypress Document Number 001 45524 Rev A Option T Tape amp Reel Blank Std Temperature C Commercial 0 to 70 C Industrial 40 to 85 C Pb Free Speed 20 20ns 25 25 ns 54 Package 45 45 ns Blank 44 Pin BA 48 FBGA Data Bus ZS TSOP II N x16 Density 108 8 Mb Voltage 5 0V Page 16 of 20 Feedback We ADVANCE F CYPRESS CY14E108L CY14E108N Package Diagrams Figure 14 44 Pin TSOP II 51 85087 DIMENSION IN MM INCH MAX MIN HRRRRRRRRRRHRHHRHRHRRHHRRH 10 262 0 404 10 058 0 396 REN K XA _ HEHHHHEHEHHHHHEHHHHHHH 2 EJECTOR PIN TOP VIEW BOTTOM VIEW 0 400 0 016 10 262 0 404 0 800 BSC 10 058 0 396 0 0315 0 300 0 012 BASE PLANE dum 0 210 0 008
14. HIGH during all six cycles to enable a nonvolatile cycle 4 While there are 20 19 address lines on the CY14B108L CY14B108N only the lower 16 lines are used to control software modes 5 IO state depends on the state of OE BHE and BLE The IO table shown assumes OE BHE and BLE LOW Document Number 001 45524 Rev A Page 5 of 20 CYPRESS PERFORM Table 1 Mode Selection continued ADVANCE CY14E108L CY14E108N CE WE OE A15 A0 Mode 10 Power L H L 0x4E38 Read SRAM Output Data Active as 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Store Output High Z L H L 0x4E38 Read SRAM Output Data Activel 4 5 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High Z Recall Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence A sequence of read operations is performed in a manner similar to the software STORE initiation To initiate the AutoStore disable sequence the following sequence of CE controlled read operations must be performed 1 Read address Ox4E38 Valid READ 2 Read address OxB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address Ox7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8B45 AutoStore Disable The
15. M c Pin Definitions ADVANCE CY14E108L CY14E108N Pin Name IO Type Description Ao Ay 9 Input Address Inputs Used to Select One of the 1 048 576 bytes of the nvSRAM for x8 Configuration Address Inputs Used to Select One of the 524 288 bytes of the nvSRAM for x16 Configuration DQO DQ7 Input Output Bidirectional Data IO Lines for x8 Configuration Used as input or output lines depending on operation DQ0 DQ15 Bidirectional Data IO Lines for x16 Configuration Used as input or output lines depending on operation WE Input Write Enable Input Active LOW When selected LOW data on the IO pins is written to the address location latched by the falling edge of CE CE Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles IO pins are tri stated on deasserting OE high BHE Input Byte High Enable Active LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQO Vss Ground Ground for the Device Must be connected to the ground of the system Vcc Power Supply Power Supply Inputs to the Device HSB Input Output VcAP Power Supply Hardware Store Busy HSB When LOW this output indicates that a hardware store is in progress When pulled LOW external to the chip it initiates a nonvolat
16. RESS CY14E108L CY14E108N To PERFORM Maximum Ratings Package Power Dissipation Capability TA 25 1 0W Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device These user guidelines are not tested Temperature 3 Seconds 260 Storage Temperature 65 C to 150 C Output Short Circuit Current 15 Ambient Temperature with Static Discharge 2001V Power Applied 55 C to 150 C per MIL STD 883 Method 3015 Supply Voltage on Relative to GND 0 5 to 7 0V Latch Up gt 200 mA Voltage Applied to Outputs in High Z State 0 5V to 0 5V Operating Range Input 0 5V to 0 Range Ambient Temperature Vcc Transient Voltage lt 20 ns on Commercial 0 C to 70 C 4 5V to 5 5V Any Pin to Ground Potential 2 0V to Voc 4 2 0V Industrial 40 to 85 C 4 5N to 5 5V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6 Parameter Description Test Conditions Min Max Unit Average Current tac 20 ns Commercial 70 mA tac 25 ns 70 mA tac 45 ns 55 mA Dependent on output loading and cycle rate Values obtained without output loads ISSN 2 D lout 0 m 57 mA loce Average Vcc Curr
17. e width 15 ns Switching Waveforms lt gt ADDRESS Pd lt taa Eton DQ DATA OUT DATA VALID gt 4 Notes Figure 5 SRAM Read Cycle 1 Address Controlled 11 21 14 Starts from the time Vcc rises above 15 If an SRAM Write has not taken place since the last nonvolatile cycle no STORE takes place 16 The software sequence is clocked with CE controlled or OE controlled reads 17 The six consecutive addresses must be read in the order listed in the mode selection table WE must be HIGH during all six consecutive cycles 18 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 19 Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time See the specific command 20 On a hardware STORE initiation SRAM operation continues to be enabled for time tpg Ay to allow read and write cycles to complete 21 HSB must remain HIGH during READ and WRITE cycles Document Number 001 45524 Rev A Page 10 of 20 Feedback I PERFORM Switching Waveforms continued Figure 6 SRAM Read Cycle 2 CE and OE Controlled 21 23 lt tac gt ADDRESS EN tace gt I teo CE t zce gt lt tuzce gt OE lt tuzoe gt lt gt BLE lt luce gt tose K
18. ent All Inputs Don t Care Vcc Max 12 mA During STORE Average current for duration tsToRE local Average Vcc Currentat gt Vcc 0 2 All other I P cycling 38 mA trc 200 ns 5V 25 C Dependent on output loading and cycle rate Values obtained typical without output loads loca Average Vcap Current All Inputs Don t Care Max 12 mA During AutoStore Cycle Average current for duration teronE Isp Vcc Standby Current CE gt Vec 0 2 All others Viy lt 0 2V or gt Voc 0 2V 6 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHz lix Input Leakage Current Vcc Max Vss lt Vin lt Voc 2 2 pA except HSB Input Leakage Current Vcc Max Vss lt Vin lt Voc 200 2 HA For HSB loz Off State Output Vcc Max Vss lt VIN lt Voc CE Or OE gt ViH 2 2 uA Leakage Current Vin Input HIGH Voltage 2 0 Voo 0 5 V ViL Input LOW Voltage Vss 0 5 0 8 V Vou Output HIGH Voltage lour 2 mA 2 4 V VoL Output LOW Voltage loyr 4 mA 0 4 V VcAP Storage Capacitor Between Vcap pin and Vss 5V Rated 122 164 uF Notes 6 Outputs shorted for no more than one second No more than one output shorted at a time 7 Typical conditions for the active current shown on the front page of the data sheet are average values at 25 C room temperature and Vcc 5V Not 100 tested 8 The HSB pin has 100 for of 2
19. er a delay of taa If the read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later The data outputs repeatedly respond to address changes within the taa access time without the need for transitions on any control input pins This remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A WRITE cycle is performed when CE and WE are LOW and HSB is HIGH The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle The data on the common IO pins DQg 15 are written into the memory if the data is valid tsp before the end of a WE controlled WRITE or before the end of a CE controlled WRITE It is recommended that OE be kept HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tuzwE after WE goes LOW AutoStore Operation The CY14B108L CY14B108N stores data to the nvSRAM using one of the following three storage operations Hardware Store activated by HSB Software Store activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108L CY14B108N During a normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored
20. erein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 45524 Rev A Revised June 24 2008 Page 20 of 20 AutoStore and QuantumTrap are registered trademarks of Simtek Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
21. ile STORE operation A weak internal pull up resistor keeps this pin HIGH if not connected connection optional AutoStore Capacitor Supplies power to the nvSRAM during power loss to store data from the SRAM to nonvolatile elements NC No Connect No Connect Do not connect this pin to the die Document Number 001 45524 Rev A Page 3 of 20 Feedback Device Operation The CY14E108L CY14E108N nvSRAM is made up of two functional components paired in the same physical cell They are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell tne STORE operation or from the nonvolatile cell to the SRAM the RECALL operation Using this unique architecture all cells are stored and recalled in parallel During the STORE and RECALL operations SRAM read and write operations are inhibited The CY14E108L CY14E108N supports infinite reads and writes similar to a typical SRAM In addition it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations SRAM Read The CY14E108L CY14E108N performs a READ cycle when CE and OE are LOW and WE and HSB are HIGH The address specified on pins Ag g or Ag4g determines which of the 1 048 576 data bytes or 524 288 words of 16 bits each is accessed When the read is initiated by an address transition the outputs are valid aft
22. ntrol Logic Block Diagram Vec VcAP 1 Address Ag Aig 1 gt 4 007 OE CY14E108L CY14E108N WE BHE 4 HSB BLE Vss Note 1 Address Ag A49 and Data DQO DQ7 for x8 configuration Address Ag and Data DQO DQ15 for x16 configuration Cypress Semiconductor Corporation Document Number 001 45524 Rev A 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised June 24 2008 Feedback E ADVANCE CYPRESS CY14E108L CY14E108N Pinouts Figure 1 Pin Diagram 48 FBGA 48 T poA 48 View View not to scale not to scale 1 2 3 4 5 6 1 2 4 5 6 OOD 99 e G9 3 CS C69 e 9 3 0 5 As FE Cay C 69 Ge Gea eX C99 G9 C DOOS 2009202 H Figure 2 Pin Diagram 44 54 TSOP II 44 HSB 43 NC 54 TSOP II x16 Top View not to scale 44 TSOP II 4 Vss x8 Top View not to scale 30 1 Vcap Note 2 Address expansion for 16 Mbit NC pin not connected to die Document Number 001 45524 Rev A Page 2 of 20 Feedback ILC Ed lt CYPRESS PERFOR
23. ommand SS ADDRESS ADDRESS 1 gt X ADDRESS 6 ADDRESS 1 gt ADDRESS 6 Vec N Document Number 001 45524 Rev A Page 14 of 20 Feedback T SES CYPRESS PERFORM Ordering Information ADVANCE CY14E108L CY14E108N prem Ordering Code Package 20 CY14E108L ZS20XCT 51 85087 44 pin TSOP II Commercial CY14E108L ZS20XIT 51 85087 44 pin TSOP II Industrial CY14E108L ZS20XI 51 85087 44 pin TSOP II CY14E108L BA20XCT 51 85128 48 ball FBGA Commercial CY14E108L BA20XIT 51 85128 48 ball FBGA Industrial CY14E108L BA20XI 51 85128 48 ball FBGA CY14E108L ZSP20XCT 51 85160 54 pin TSOP II Commercial CY14E108L ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14E108L ZSP20XI 51 85160 54 pin TSOP II CY14E108N BA20XCT 51 85128 48 ball FBGA Commercial CY14E108N BA20XIT 51 85128 48 ball FBGA Industrial CY14E108N BA20XI 51 85128 48 ball FBGA CY14E108N ZSP20XCT 51 85160 54 pin TSOP II Commercial CY14E108N ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14E108N ZSP20XI 51 85160 54 pin TSOP II 25 CY14E108L ZS25XCT 51 85087 44 pin TSOP II Commercial CY14E108L ZS25XIT 51 85087 44 pin TSOP II Industrial CY14E108L ZS25XI 51 85087 44 pin TSOP II CY14E108L BA25XIT 51 85128 48 ball FBGA Industrial CY14E108L BA25XI 51 85128 48 ball FBGA CY14E108N BA25XCT 51 85128 48 ball FBGA
24. put Disable 8 10 15 ns lice tow Output Active after End of Write 3 3 3 ns Byte Enable to End of Write 15 20 30 ns Notes _ 10 WE must be HIGH during SRAM read cycles _ 11 Device is continuously selected with CE and OE both LOW 12 Measured 200 mV from steady state output voltage 13 If WE is LOW when CE goes LOW the output goes into high impedance state Document Number 001 45524 Rev A Page 9 of 20 Feedback ADVANCE T CYPRESS CY14E108L CY14E108N PERFORM AutoStore and Power Up RECALL CY14E108L CY14E108N Parameters Description Min Max tuRECALL 18 Power Up RECALL Duration 20 ms tstore I STORE Cycle Duration 15 ms VswITCH Low Voltage Trigger Level 4 4 V VCCRISE VCC Rise Time 150 us Software Controlled STORE and RECALL Cycle In the following table the software controlled STORE RECALL cycle parameters are listed 6 17 Parameters Description 2308 dons Unit Min Max Min Max Min Max tnc STORE RECALL Initiation Cycle Time 20 25 45 ns tas Address Setup Time 0 0 0 ns tew Clock Pulse Width 15 20 30 ns lGHAX Address Hold Time 1 1 1 ns tRECALL RECALL Duration 200 200 200 us tgg 78 19 Soft Sequence Processing Time 70 70 70 us Hardware STORE Cycle e CY14E108L CY14E108N Parameters Description Unit Min Max tpELAY 20 Time allowed to complete SRAM cycle 1 70 us tui ux Hardware STORE puls
25. sequence A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled READ operations must be performed 1 Read Address Ox4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle Internally RECALL is a two step procedure First the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells After the cycle time the SRAM is again ready for READ and WRITE operations The RECALL operation does not alter the data in the nonvolatile elements CE WE OE A15 A0 Mode 10 Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 Read SRAM Output Data Activel 4 5 OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable L H L 0x4E38 Read SRAM Output Data Activel 4 5 OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data Notes 3 The six consecutive address locations must be in the order listed WE must be
26. six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation it is important that no other READ or WRITE accesses intervene in the sequence If there are intervening READ or WRITE accesses the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following READ sequence must be performed 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled READs or OE controlled READs After the sixth address in the sequence is entered the STORE cycle commences and the chip Table 1 Mode Selection ADVANCE CY14E108L CY14E108N is disabled It is important to use READ cycles and not WRITE cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the cycle time is fulfilled the SRAMis activated again for the READ and WRITE operation Software RECALL Transfer the data from the nonvolatile memory to the SRAM with a software address
27. ver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the CY14B108L CY14B108N continues SRAM operations for tpELAY During tpg Ay multiple SRAM READ operations may take place If a WRITE is in progress when HSB is pulled low it is allowed a time Ay to complete However any SRAM WRITE cycles requested after HSB goes LOW is inhibited until HSB returns HIGH During any STORE operation regardless of how it was initiated the CY14B108L CY14B108N continues to drive the HSB pin LOW releasing it only when the STORE is complete Upon completion of the STORE operation the CY14B108L CY14B108N remains disabled until the HSB pin returns HIGH Leave the HSB unconnected if it is not used Hardware RECALL Power Up During power up or after any low power condition Vcc an internal RECALL request is latched When Vcc again exceeds the sense voltage of Vswitcy a RECALL cycle is automatically initiated and takes ttinEcALL to complete Page 4 of 20 Feedback Software STORE Transfer data from the SRAM to the nonvolatile memory with a software address sequence The CY14B108L CY14B108N software STORE cycle is initiated by executing sequential CE controlled READ cycles from
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