Cypress NoBL CY7C1471V25 User's Manual
Contents
1. CY7C1471V25 PERFORM Pin Configurations 100 Pin TQFP Pinout 5 o x Z gt lt lt E 5 EB 9 lt lt lt lt o N e o e N o DQPc 1 80 DAP DQc 2 79 DQc 3 78 Vppo 4 7T Vppa Vss 5 76 Vss BYTE DQc 1 6 75 DQg BED DQc 7 74 DQc 8 73 DQc 9 72 Vss 10 71 Vss Vppa 11 70 Vppa DQc 12 69 DQg DQc L 13 68 CY7C1471V25 DOs NC 14 67 Vss Vpp 15 66 NC NC 16 65 Vpp Vss 17 64 ZZ DQ 18 63 DQ DQp 1 19 62 DQA VDDQ L 20 61 Vppo Vss 21 60 Vss DQp 22 59 DQA BYTED DQp 23 58 DQA DQp 24 57 DQ BYTEA DQp 25 56 DQ Vss 26 55 Vss 27 54 DQp EH 28 53 DQ DQp L 29 52 DQ DQPp 30 51 N eo Q o N e lo N C O A G c0 c02. CY7C1473V25 CYPRESS CY7C1475V25 PERFORM TAP AC Switching Characteristics Over the Operating Rangel 11 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns Clock Frequency 20 MHz Clock HIGH Time 20 ns tr TCK Clock LOW Time 20 ns Output Times trbov TCK Clock LOW to TDO Valid 10 ns Clock LOW to Invalid 0 ns Setup Times ttuss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tes Capture Setup to TCK Rise 5 ns Hold Times trMsH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Notes 10 tcs and refer to the setup and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load TAP AC Test Conditions 1 ns Document 38 05287 Rev 1 Page 16 of 32 Feedback 2 CYPRESS j PERFORM 1 8V TAP AC Test Conditions Input pulse levels 0 2V to Vppo 0 2 Input rise and fall time ins Input timing reference levels 0 9V Output reference 0 9V Test load termination supply voltage 0 9V 1 8V TAP AC Output Load E
3. CY7C1471V25 72 Mbit 2M x 36 4M x 18 1M x 72 CY7C1473V25 i YPRESS CY7C1475V25 Flow Through SRAM with NoBL Architecture Features Functional Description No Bus Latency NoBL architecture eliminates dead The CY7C1471V25 CY7C1473V25 and CY7C1475V25 are cycles between write and read cycles 2 5V 2M x 36 4M x 18 1M x 72 synchronous flow through burst Supports up to 133 MHz bus operations with zero wait states SRAMs designed specifically to support unlimited true back to back read or write operations without the insertion of Data is on every clock wait states The CY7C1471V25 CY7C1473V25 and Pin compatible and functionally equivalent to ZBT devices CY7C1475V25 are equipped with the advanced No Bus Internally self timed output buffer control to eliminate the Latency NoBL logic required to enable consecutive read or need to use OE write operations with data transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Registered inputs for flow through operation Byte Write capability write read transitions 2 5V 1 8V IO supply All synchronous inputs pass through input registers controlled Fast clock to output times by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted ie i te suspends op
4. Vppo Daf DQf H DQc Vss Vss Vss NC Vss Vss Vss DQf Dat J DQc Vppo Vppa NC Voo Vppo DQf K NC NC CLK NC Vss CEN Vss NC NC NC NC L DQh Vppa NC Vppa DQa DQa M DQh DQh Vss Vss Vss NC Vss Vss Vss DQa DQa N DQh DQh Vppa NC Voo Vopa DQa P DQh DQh Vss Vss Vss zZ Vss Vss Vss DQa DQa R DQPd DQPh Vppo Vppa Vpp Vpp Vppo DQPa DQPe T DQd DQd Vss NC NC MODE NC NC Vss DQe DQe U DQd NC 44M A A A NC 288M poe V DQd DQd A A A A1 A A A DQe DQe w DQd DQd TMS TDI A A0 A TDO TCK pQe DQe Document 38 05287 Rev 1 Page 7 of 32 Feedback CY7C1471V25 CY7C1473V25 CY7C1475V25 Name IO Description Ao A4 Input Address Inputs used to select one of the address locations Sampled at the rising edge Synchronous of the CLK Aro are fed to the two bit burst counter BWA BW Input Byte Write Inputs Active LOW Qualified with WE to conduct writes to the SRAM BWc BWp Synchronous Sampled on the rising edge of CLK BWe BWp BWy WE Input Write Enable Input Active LOW Sampled on the rising edge of CLK if CEN is active LOW Synchronous This signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip addres
5. DQ OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 DON T Q UNDEFINED Not 19 For this waveform ZZ is tied LOW 20 When CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH CE is LOW or CE is HIGH 21 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05287 Rev 1 24 of 32 Feedback CY7C1471V25 bs CY7C1473V25 amp CYPRESS _ 7 1475 25 PERFORM Switching Waveforms continued Figure 2 shows NOP STALL and DESELECT Cycles waveform Figure 2 NOP STALL and DESELECT Cycles 19 20 22 w 2 LE S D E m m m ADVID wm BW o DANAC DQ DIAN o WQ 4 gt CONTINUE DESELECT READ DESELECT Q A5 WRITE D A4 READ Q A3 DONT CARE UNDEFINED ERE WRITE D A1 Note 22 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Document 38 05287 Rev 1 Page 25 of 32 Feedback PERFORM Switching Waveforms conti
6. 0 c00 st cst cs S wp S p lt lt lt lt lt a oe a zz gt Z lt lt lt lt lt lt lt lt lt 2 zz Document 38 05287 Rev 1 Page 4 of 32 Feedback CY7C1471V25 gt CY7C1473V25 VEEZCYPRES __ CY7C145V25 Pin Configurations continued 100 Pin TQFP Pinout ADV LD oo m lt 2 lt lt 2 8 lt lt lt lt PTT ty tt HI OANT S 85858 O O 5988 89 G 90333859385 NC 1 80 A NC 2 79 NC NC 3 78 NC 4 77 7 Vss 5 76 Vss NC 6 75 NC NC 7 74 DQP DQg 8 73 DQA 9 72 DQ Vss 10 71 Vss 11 70 DQg 12 69 DQA 13 68 DQ NC 14 67 Vss 15 66 NC BYTEA BYTE B NC L 16 CY7C1473V25 65 Vss 17 64 22 DQg 18 63 DQA DQg 19 62 DQA 20 61 Vppo Vss H 21 60 Vss DQg 22 59 DQ DQg 23 58 DQ 24 57 NC N
7. Note 9 Table lists only a partial listing of the byte write combinations Any combination of BWx is valid Appropriate write is based on which byte write is active Document 38 05287 Rev 1 Page 12 of 32 Feedback IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1471V25 CY7C1473V25 and CY7C1475V25 and incorporate a serial boundary scan test access port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 2 5V or 1 8V IO logic levels The CY7C1471V25 CY7C1473V25 and CY7C1475V25 contain a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO must be left unconnected During power up the device comes up in a reset state which does not interfere wi
8. CY7C1475V25 100BGXI 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free Document 38 05287 Rev 1 Page 27 of 32 Feedback PERFORM Package Diagrams CY7C1471V25 CY7C1473V25 CY7C1475V25 Figure 4 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 100 81 AHARHAARARAHAAAAAARAA 15 za 0 30 0 08 I ES 5 d 3 5 o E CE 1 5 065 Es ES TYP ES c EB 51 Y UUHHHHHEEEUHHHHHHHUU 31 50 R 0 08 MIN f 0 20 MAX 0 MIN STAND OFF 0 05 MIN 0 15 GAUGE PLANE L Y i ES R 0 08 MIN 97 020MAX 0 60 0 15 0 20 MIN 1 00 REF IT DETAIL Document 38 05287 Rev 1 1 40 0 05 DETAIL I SEATING PLANE 1 STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS NOTE 51 85050 Page 28 of 32 Feedback PERFORM Package Diagrams continued TOP VIEW PIN 1 CORNER Figure 5 165 Ball FBGA 15 x 17 x 1 4 mm 51 85165 8 9 10 n 0 25C in E ge a 9 rol a 2
9. Document 38 05287 Rev 1 Page 20 of 32 Feedback ee s j 724 CYPRESS PERFORM Maximum Ratings CY7C1471V25 CY7C1473V25 CY7C1475V25 DC Input Voltage Current into Outputs LOW 20 mA Exceeding maximum ratings may impair the useful life of the UR device These user guidelines are not tested E E T E E ET E gt 2001V Storage Temperature 65 C to 150 C i T Ambient Temperature with atch Up Current oca gt 200 m Power Applied eene 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 3 6V Ambient Range Vpp Vppo Supply Voltage on Vppq Relative to GND 0 5V to Vpp Temperature DC Voltage Applied to Outputs Commercial 0 to 70 C 2 5V 5 5 1 7 to Vpp in Tri Stal iret 0 5V to Vppo 0 5V Industrial 40 to 85 C Electrical Characteristics Over the Operating Range 13 14 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 2 375 2 625 V Vppa IO Supply Voltage For 2 5V IO 2 375 Vpp V For 1 8V IO 1 7 1 9 V Vou Output HIGH Voltage For 2 5V IO lop 1 0 mA 2 0 V For 1 8V IO lop 100 pA 1 6 V VoL Output LOW Voltage For 2 5V IO loj 1 0 mA 0 4 V For 1 8V IO 100 pA 0 2 V
10. 01011 01011 01011 Reserved for internal use Architecture Memory Type 23 18 001001 001001 001001 Defines memory type and architecture Bus Width Density 17 12 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 1 Indicates the presence of an ID register Note 12 All voltages refer to Vss GND Document 38 05287 Rev 1 Page 17 of 32 Feedback 2 CYPRESS j PERFORM Scan Register Sizes CY7C1471V25 CY7C1473V25 CY7C1475V25 Document 38 05287 Rev 1 Register Bit Size x36 Bit Size x18 Bit Size x72 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165FBGA 71 52 Boundary Scan Order 209BGA 110 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is r
11. CE3 CEN ADV LD A A A B A CE2 nc BW WE OE A A NC Vss Vss Vss Vss Vss VDDQ NC DQPA D NC DQs Vppo Vss Vss Vss Vpp Vppa NC DQA E NC DQg Vppa Vpp Vss Vss Vss Vpp NC F NC DQg Vppa Vpp Vss Vss Vss Vpp NC G NC DQg Vppa Vpp Vss Vss Vss Vpp NC DQA H NC NC NC Vpp Vss Vss Vss NC NC 77 NC Vppa Vpp Vss Vss Vss Vpp DQA NC K DQg NC Vppa Vpp Vss Vss Vss Vpp L DQg NC Vpp Vss Vss Vss Vpp DQA NC M NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC N DQPg NC VDDQ Vss NC NC NC Vss VDDQ NC NC P NC 144M A A A TDI A1 TDO A A A NC 288M R MODE A A A TMS AO TCK A A A A Document 38 05287 Rev 1 Page 6 of 32 Feedback CY7C1471V25 CY7C1473V25 CYPRESS CY7C1475V25 Pin Configurations continued 209 Ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1475V25 1M x 72 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A ADVLD DQb DQb B DQg DQg BWS BWS NC WE A BWS BWS DQb DQb C DQg BWS BWS NC 576M CE NC BWS BWS DQb DQb D DQg DQg Vss NC NCHG OE NC NC Vss DQb DQb E DQPg DQPc Vppo Vppo Vpp Vpp Vppo DQPf DQPb F DQc pQc Vss Vss Vss NC Vss Vss Vss DQf DQf G DQc DQc Vppa Vopa NC
12. CEN CLK Deselect Cycle None H X X L L X X X Tri State Deselect Cycle None X X H L L X X X Tri State Deselect Cycle None X L X L L X X X Tri State Continue Deselect Cycle None X X X L H X X X Tri State Read Cycle External L H L L L H X L L gt H Data Out Q Begin Burst Read Cycle Next X X X L H X X L Data Out Q Continue Burst NOP Dummy Read External L H L L L H X H L gt H Tri State Begin Burst Dummy Read Next X X X L H X X H L gt H Tri State Continue Burst Write Cycle External L H L L L L L X gt Data In D Begin Burst Write Cycle Next X X X L H X L X gt Data In D Continue Burst NOP Write Abort None L H L L L L H x L L gt H Tri State Begin Burst Write Abort Next X X X L H X H X Tri State Continue Burst Ignore Clock Edge Stall Current X X X L X X X X H gt Sleep Mode None X X X H X X X X X X Tri State Notes 2 X Don t Care H Logic HIGH L Logic LOW BW L signifies at least one Byte Write Select is active BW Valid signifies that the desired Byte Write Selects are asserted see Truth Table for Read Write on page 12 for details 3 Write is defined by BW and WE See Truth Table for Read Write on page 12 4 When a write cycle is detected all IOs are tri stated even during byte writes 5 The DQs DQPy pins are controlled by the current cycle and the OE signal OE is asynchronous and
13. Power supply inputs to the core of the device VDDQ IO Power Supply Power supply for the IO circuitry Vss Ground Ground for the device TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the Synchronous JTAG feature is not used this pin must be left unconnected This pin is not available on TQFP packages Document 38 05287 Rev 1 Page 8 of 32 Feedback Pin Definitions continued CY7C1471V25 CY7C1473V25 CY7C1475V25 Name IO Description TDI JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous is not used this pin can be left floating or connected to Vpp through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous is not used this pin can be disconnected or connected to Vpp This pin is not available on TQFP packages TCK JTAG Clock Clock input to the JTAG circuitry If the JTAG feature is not used this pin must be connected to Vss This pin is not available on TQFP packages NC No Connects Not internally connected to the die 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Functional Overview The CY7C1471V25 CY7C1473V25 and CY7C1475V25 are synchronous flow through burst SRAMs d
14. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output may undergo a transition The TAP may then try to capture a Page 14 of 32 Feedback signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold time tcs plus tcp The SRAM clock input might not be captured correctly
15. Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Document History Page CY7C1471V25 CY7C1473V25 CY7C1475V25 Document Title CY7C1471V25 CY7C1473V25 CY7C1475V25 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM with NoBL Architecture Document Number 38 05287 REV No BSue e D Description of Change dd 114674 08 06 02 PKS New Data Sheet 121522 01 27 03 Updated features for package offering Updated ordering information Changed Advanced Information to Preliminary B 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified Functional Overview section Added boundary sc
16. Vin Input HIGH Voltagel 3 For 2 5V IO 17 Vpp 0 3V V For 1 8V 1 26 Vpp 0 3 V ViL Input LOW Voltagel For 2 5V IO 0 3 0 7 V For 1 8V IO 0 3 0 36 V Ix Input Leakage Current GND lt Vj lt Vppo 5 5 uA except ZZ and MODE Input Current of MODE Input Vas 30 Input Vpp 5 Input Current of ZZ Input Vas 5 Input Vpp 30 uA loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 uA Ipp Vpp Operating Supply Vpp Max lour 0 mA 6 5 ns cycle 133 MHz 305 mA Current f fmax 1 8 5 ns cycle 100 MHz 275 Isp4 Automatic CE Vpp Max Device Deselected 6 5 cycle 133 MHz 170 mA Power Down Vin gt Vin or Vin E Vi Current TTL Inputs f fmax inputs switching 9 508 6ycle 100 Miz 1 0 Ispo Automatic CE Vpp Max Device Deselected All speeds 120 mA Power Down Vin lt 0 3V or Vin gt Vpp 0 3V Current CMOS Inputs f 0 inputs static Isp3 Automatic CE Vpp Max Device Deselected or 6 5 ns cycle 133 MHz 170 mA Power Down Vin lt 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f fmax inputs switching Bons cycle 100 2 179 Isp4 Automatic CE Vpp Max Device Deselected All Speeds 135 mA Power Down Vin gt 0 3V or Vin lt 0 3V Current TTL Inputs f 0 inputs static Notes 13 Overshoot lt Vpp 1 5V pulse width less than tcyc 2 Undershoot Vj AC gt 2V pulse width less than 2 14 Tpow
17. chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access read or write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when these conditions are satisfied at clock rise CEN is asserted LOW CE4 and CE are ALL asserted active WE is asserted LOW The address presented to the address bus is loaded into the Address Register The write signals are latched into the Control Logic block The data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs DQPy On the next clock rise the data presented to DQs and or a subset for Byte Write operations see Truth Table for Read Write on page 12 for details inputs is latched into the device and the write is complete Additional accesses read write deselect can be initiated on this cycle The data written during the write operation is controlled by BWy signals The CY7C1471V25 CY7C1473V25 and CY7C1475V25 provide Byte Write capability that is described in the Truth Table for Read Write on page 12 The input WE with the selected BW input selectively writes to only the desired bytes Bytes not selected during a Byte Write operation remain unaltered A synchronous self timed write mechanism is provided to simplify the write operations Byte Write capability is included to greatly sim
18. is not sampled with the clock 6 CEN H inserts wait states Device powers up deselected with the lOs in a tri state condition regardless of OE 8 OEis asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPy tri state when OE is inactive or when the device is deselected and DQs and DQPy data when OE is active Document 38 05287 Rev 1 Page 11 of 32 Feedback CY7C1471V25 CY7C1473V25 CYPRESS CY7C1475V25 PERFORM Truth Table for Read Write The read write truth table for CY7C1471V25 follows 3 9 Function WE BW BWg BWc BWp Read H X X X X Write No bytes written L H H H H Write Byte A DQ4 and DQPA L L H H H Write Byte B DQg and L H L H H Write Byte C DQc and DQPc L H H L H Write Byte D DQp and DQPp L H H H L Write All Bytes L L L L L Truth Table for Read Write The read write truth table for CY7C1473V25 follows 3 9 Function WE BW BW Read H X X Write No Bytes Written L H H Write Byte a DQ and L H L Write Byte b DQ and DQP L L H Write Both Bytes L L L Truth Table for Read Write The read write truth table for CY7C1475V25 follows I 3 9 Function WE BW Read H X Write No Bytes Written L H Write Byte X DQ and L L Write All Bytes L All BW L
19. of the Burst Write to write the correct bytes of data A1 A0 A1 AO A1 A1 AO Sleep Mode 00 01 10 11 The ZZ input pin is an asynchronous input Asserting ZZ 01 10 11 00 places the SRAM in a power conservation sleep mode Two 10 11 00 01 clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed 11 00 01 10 Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected before entering the sleep mode CE and CE3 must remain inactive for the duration of tz7pE after the ZZ input returns LOW ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 120 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ lt 0 2V 2tcyc ns 77 ZZ active to sleep current This parameter is sampled 2tcyc ns 277 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05287 Rev 1 Page 10 of 32 Feedback CY7C1471V25 CY7C1473V25 CY7C1475V25 y CYPRESS PERFORM Truth Table The truth table for CY7C1471V25 CY7C1473V25 and CY7C1475V25 follows 2 3 4 5 6 7 8 Operation Address CE CE ZZ ADVILD WE BWy OE
20. used to capture the contents of the IO ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Defini tions on page 17 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in Identification Codes on page 18 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Document 38 05287 Rev 1 CY7C1471V25 CY7C1473V25 CY7C1475V25 The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE
21. 2 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 48 4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Document 38 05287 Rev 1 Page 19 of 32 Feedback CY7C1471V25 x CY7C1473V25 2 CYPRESS CY7C1475V25 l PERFORM Boundary Scan Exit Order 1M x 72 Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 AT 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 4 24 2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 26 P2 54 V11 82 D10 110 A3 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10
22. AM When deasserted HIGH the clock signal is masked Because deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQ IO Bidirectional Data IO Lines As inputs they feed into an on chip data register that is Synchronous triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ DQP are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPx IO Bidirectional Data Parity IO Lines Functionally these signals are identical to DQ During Synchronous write sequences DQP is controlled by BW correspondingly MODE Input Strap Pin Mode Input Selects the burst order of the device When tied to Gnd selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence Vpp Power Supply
23. C 25 56 NC Vss 26 55 J Vss 27 54 I Vppa 28 53 7 NC NC 29 52 NC NC 30 51 NC s 835595959099 S S 93 q 5 e lt lt lt lt G lt lt lt lt lt lt lt lt lt s 9g Document 38 05287 Rev 1 Page 5 of 32 Feedback CY7C1471V25 Z CY7C1473V25 CYPRESS CY7C1475V25 PERFORM Pin Configurations continued 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1471V25 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A 576 A CE BWc BWg ADV LD NC B NC 1G A CE2 BWp BWA CLK WE OE A A NC C DQPc NC Vppo Vss Vss Vss Vss Vss VDDQ NC DQPg D DQc DQc Vppa Vpp Vss Vss Vss Vpp VDDQ DQg DQg E DQc DQc Vppo Vpp Vss Vss Vss Vpp DQg DQg F DQc DQc Vppo Vpp Vss Vss Vss Vpp DQg G DQc DQc Vppo Vpp Vss Vss Vss Vpp Vppo H NC NC NC Von Vss Vss Vss Vpop NC NC ZZ J DQp DQp Vss Vss Vss Vpp DQA K DQp DQp Vppa Vpp Vss Vss Vss Vpp Vppo DQA DQA L DQp DQp Vpp Vss Vss Vss Vpp VDDQ DQA DQA M DQp DQp Vppa Vpp Vss Vss Vss Vpp VDDQ DQPp NC VDDQ Vss NC NC NC Vss VDDQ NC DQPA P NC 144M A A A TDI A1 TDO A A A NC 288M R MODE A A A TMS AO TCK A A A A CY7C1473V25 4M x 18 1 2 3 4 5 6 7 8 9 10 11 NC 576M CE BWg NC
24. Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1471V25 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1473V25 133AXI CY7C1471V25 133BZI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473V25 133BZI CY7C1471V25 133BZXI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V25 133BZXI CY7C1475V25 133BGI 51 85167 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1475V25 133BGXI 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free 100 CY7C1471V25 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1473V25 100AXC CY7C1471V25 100BZC 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473V25 100BZC CY7C1471V25 100BZXC 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V25 100BZXC CY7C1475V25 100BGC 51 85167 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1475V25 100BGXC 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1471V25 100AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1473V25 100AXI CY7C1471V25 100BZI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473V25 100BZI CY7C1471V25 100BZXI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V25 100BZXI CY7C1475V25 100BGI 51 85167 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm
25. LL INPUT PULSES OUTPUT 500 5 R 14KQ 0 9V INCLUDING JIG AND a scope 0 P Document 38 05287 Rev 1 Page 22 of 32 Feedback Switching Characteristics Over the Operating Range Timing reference level is 1 25V when Vppo 2 5V and is 0 9V when Vppq 1 8V Test conditions shown in a of AC Test Loads and Waveforms on page 22 unless otherwise noted CY7C1471V25 CY7C1473V25 CY7C1475V25 133 MHz 100 MHz Parameter Description Unit Min Max Min Max POWER 1 1 ms Clock Clock Cycle Time 7 5 10 ns tcu Clock HIGH 2 5 3 0 ns teL Clock LOW 2 5 3 0 ns Output Times tepv Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 5 2 5 ns bus Clock to Low Z 16 17 18 3 0 3 0 ns tonz Clock to High z 116 17 18 3 8 4 5 ns tory OE LOW to Output Valid 3 0 3 8 ns toELZ OE LOW to Output Low Z 116 17 18 0 0 ns toEuz OE HIGH to Output High Z 116 17 18 3 0 4 0 ns Setup Times tas Address Setup Before CLK Rise 1 5 1 5 ns tats ADV LD Setup Before CLK Rise 1 5 1 5 ns twes WE BW Setup Before CLK Rise 1 5 1 5 ns icENS CEN Setup Before CLK Rise 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 5 1 5 ns tcEs Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 5 0 5 ns tALH ADV LD Hold After CLK Rise 0 5 0 5 ns tWeH WE BW Hold After CLK Rise 0 5 0 5 ns t
26. PRELOAD rather it performs a capture of the IO ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction after it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all Os EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize all 0 instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state
27. U T T ADVILD N A BWA MEMORY B mi WRITE REGISTRY WRITE gt array PN LN gt u i BWB AND DATA COHERENCY DRIVERS P T F DQPA CONTROL LOGIC gt A E F DQPB M E E P R R E S N E r INPUT K REGISTER READ LOGIC 4 1 2 zz SLEEP CONTROL Document 38 05287 Rev 1 Page 2 of 32 Feedback CY7C1471V25 CY7C1473V25 CYPRESS CY7C1475V25 PERFORM Logic Block Diagram CY7C1475V25 1M x 72 AQ ADDRESS m REGISTER 0 MODE c DH CEN q_ WRITE ADDRESS REGISTER 1 o o gt u y S F D P ADV LD e T u BWa 5 jt R k BW WHITE MEMORY PNE 5 ARRAY S WRITE REGISTRY DRIVERS I T E DQ Pa Bwa AND DATA COHERENCY M E E DQ Pb awe CONTROL LOGIC S I R R DQ Pc BWr R N DQ Pd BW 9 G DQ Pe BWh DQ Pf gt DQ Pg DQPh WE fo INPUT INPUT lt REGISTER 1 4 REGISTER 0 4 A e d OE READ LOGIC CE1 CE3 zz Sleep Control Document 38 05287 Rev l Page 3 of 32 Feedback
28. a 5 5 Ba SEATING PLANE 1 1 T 8 E S Document 38 05287 Rev 1 CY7C1471V25 CY7C1473V25 CY7C1475V25 BOTTOM VIEW PIN 1 CORNER amp g005MC Y gos MEAIB 0 45 0 05 165X 10 s E 7 6 S 4 3 2 1 A eoooo ooood y 60000000000 8 2 8 D je 3 O o6 96 0 O OOG O H B 1 E L N R A H 5 00 10 00 B 15 00 0 10 A 0 15 4X 51 85165 A Page 29 of 32 Feedback CY7C1471V25 CY7C1473V25 CY7C1475V25 PERFORM Package Diagrams continued Figure 6 209 Ball FBGA 14 x 22 x 1 76 mm 51 85167 22 A 51 85167 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05287 Rev 1 30 of 32 Cypress Semiconductor Corporation 2002 2007 The information contained herein is subject to change without notice Cypress
29. a is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13 During power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to enable fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be
30. an order for all packages Included thermal numbers and capacitance values for all packages Removed 150MHz speed grade offering Included ISB and IDD values Changed package outline for 165FBGA package and 209 Ball BGA package Removed 119 BGA package offering C 235012 See ECN RYQ Minor Change The data sheets do not match on the spec system and external web D 243572 See ECN NJY Changed ball H2 from Vpp to NC in the 165 Ball FBGA package in page 6 Changed ball R11 in 209 Ball BGA package from DQPa to DQPe in page 7 Modified Capacitance values on page 21 E 299511 See ECN SYT Removed 117 MHz Speed Bin Changed from 16 8 to 24 63 C W and jc from 3 3 to 2 28 C W for 100 TQFP Package on Page 22 Added Pb free information for 100 Pin TQFP 165 FBGA and 209 BGA Packages Added comment of Pb free BG packages availability below the Ordering Information F 323039 See ECN PCI Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified Vo Voy Test Conditions Changed package name from 209 Ball PBGA to 209 Ball FBGA on page 7 Added Industrial temperature range Added Pb free information in the ordering information table Removed comment of Pb free BG packages availability below the Ordering Information Updated Ordering Information Table G 416221 See ECN NXR Converted from Preliminary to Final Changed address of Cypress Semiconductor Corpo
31. cENH CEN Hold After CLK Rise 0 5 0 5 ns Data Input Hold After CLK Rise 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 15 This part has a voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 16 tci z tog z and toguz are specified with AC test conditions shown part b of AC Test Loads and Waveforms on page 22 Transition is measured 200 mV from steady state voltage 17 At any supplied voltage and temperature togpz is less than tog 7 and is less than tc 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z before Low Z under the same system conditions 18 This parameter is sampled and not 100 tested Document 38 05287 Rev 1 23 of 32 Feedback CY7C1471V25 e s CY7C1473V25 SA 6614755 PERFORM Switching Waveforms Figure 1 shows read write timing waveform 19 20 21 Figure 1 Read Write Timing 1 2 tec 3 4 5 6 7 8 9 10 gt tCENSI CENH mL Y NU m O m m A YR MA VA VA m ADDRESS MA 2 NS 6 NT tas tAH DOH tcHz
32. connected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram o gt Bypass Register 200 Instruction Register Selection Circuitry Selection TDI Circuitry TDO I 313029 1 1 121110 Identification Register Boundary Scan Register TAP CONTROLLER TMS Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating During power up the TAP is reset internally to ensure that TDO comes up in a High Z state Page 13 of 32 Feedback TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Dat
33. er up assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp Document 38 05287 Rev 1 Page 21 of 32 CY7C1471V25 es CY7C1473V25 ZCYPRESS CYTCMTSV25 PERFORM Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions ren e cds Unit CADDRESS Address Input Capacitance 25 C f 1 MHz 6 6 6 pF CDATA Data Input Capacitance 5 5 5 pF CcTRL Control Input Capacitance 8 8 8 pF Clock Input Capacitance 6 6 6 pF Cio Input Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters EF e 100 TQFP 165FBGA 209 FBGA Parameter Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow 24 63 16 3 15 2 C W Junction to Ambient standard test methods and procedures for Thermal Resistance measuring thermal 2 28 2 1 1 7 C W Junction to Case impedance according to EIA JESD51 AC Test Loads and Waveforms 2 5V IO Test Load R 16670 OUTPUT 2 5V 7 ALL INPUT PULSES OUTPUT 90 500 5 pF GND V 125V 15380 lt 1ns gt lt 1ns L INCLUDING JIG AND a scope b e 1 8V IO Test Load R 14KQ OUTPUT 1 8V d A
34. eration and extends the previous clock cycle Clock Enable CEN pin to enable clock and suspend Maximum access delay from the clock rise is 6 5 ns 133 MHz operation device Synchronous self timed writes __ Write operations are controlled by two or four Byte Write Select Asynchronous Output Enable OE BWy and a Write Enable WE input All writes are conducted CY7C1471V25 CY7C1473V25 available in with on chip synchronous self timed write circuitry JEDEC standard Pb free 100 pin TQFP Pb free and Three synchronous Chip Enables CE3 and an non Pb free 165 Ball FBGA package CY7C1475V25 asynchronous Output Enable OE provide easy bank available in Pb free and non Pb free 209 Ball FBGA selection and output tri state control To avoid bus contention package EN the output drivers are synchronously tri stated during the data Three Chip Enables CE CE3 for simple depth portion of a write sequence expansion Automatic power down feature available using ZZ mode or CE deselect IEEE 1149 1 JTAG Boundary Scan compatible Burst Capability linear or interleaved burst order Low standby power Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 305 275 mA Maximum CMOS Standby Current 120 120 mA Note 1 For best practice recommendations refer to the Cypress application note AN 1064 SRAM System Guidelines Cypress Semiconductor Cor
35. eserved for future use SAMPLE PRELOAD 100 Captures IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Page 18 of 32 Feedback CY7C1471V25 Z CY7C1473V25 CYPRESS CY7C1475V25 PERFORM Boundary Scan Exit Order 2M x 36 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 e 21 R3 41 11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Boundary Scan Exit Order 4M x 18 Bit 165 BallID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 4
36. esigned specifically to eliminate wait states during write read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN Maximum access delay from the clock rise t py is 6 5 ns 133 MHz device Accesses are initiated by asserting all three Chip Enables CE4 CE3 active at the rising edge of the clock If CEN is active LOW and ADV LD is asserted LOW the address presented to the device is latched The access can either be a read or write operation depending on the status of the Write Enable WE Byte Write Select BW can be used to conduct Byte Write operations Write operations are qualified by the WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 CE3 and an asynchronous Output Enable OE simplify depth expansion All operations reads writes and deselects are pipelined ADV LD must be driven LOW after the device is deselected to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and are ALL asserted active 3 WE is deasserted HIGH a
37. if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls TAP Timing Test Clock TCK CY7C1471V25 CY7C1473V25 CY7C1475V25 Note that since the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect as the Pause DR command BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Mode Select XX XX TMS tTDIS SS Test Data In y V TDI trpov lt lt trpox Test Data Out TDO DON T CARE 2 UNDEFINED Document 38 05287 Rev 1 15 of 32 Feedback CY7C1471V25
38. nd 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers The data is available within 6 5 ns 133 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW to drive out the requested data On the subsequent clock another operation read write deselect can be initiated When the SRAM is deselected at clock rise by one of the chip enable signals the output is tri stated immediately Document 38 05287 Rev 1 Burst Read Accesses The CY7C1471V25 CY7C1473V25 and CY7C1475V25 has an on chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs ADV LD must be driven LOW to load a new address into the SRAM as described in the Single Read Access section The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an inter leaved burst sequence Both burst counters use AO and A1 in the burst sequence and wraps around when incremented sufficiently A HIGH input on ADV LD increments the internal burst counter regardless of the state of
39. nued 23 24 Figure 3 shows ZZ Mode timing waveform Figure 3 ZZ Mode Timing CY7C1471V25 CY7C1473V25 CY7C1475V25 tzzREC AA lt ZZ tzzl except ZZ DON T CARE Notes 24 DGs are in high Z when exiting ZZ sleep mode Document 38 05287 Rev 1 suppLy Y DDzz Lu Rz 23 Device must be deselected when entering ZZ mode See Truth Table on page 11 for all possible signal conditions to deselect the device Page 26 of 32 Feedback CY7C1471V25 ox CY7C1473V25 Z CYPRESS CY7C1475V25 l PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered atte Ordering Code Dorm Part and Package Type ieri 133 CY7C1471V25 133AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 1 4 mm Pb Free Commercial CY7C1473V25 133AXC CY7C1471V25 133BZC 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1473V25 133BZC CY7C1471V25 133BZXC 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V25 133BZXC CY7C1475V25 133BGC 51 85167 209 Ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1475V25 133BGXC 209 Ball
40. plify read modify write sequences which can be reduced to simple byte write operations Page 9 of 32 Feedback Because the CY 7C1471V25 CY7C1473V25 CY7C1475V25 are common IO devices data must not be driven into the device while the outputs are active The OE can CY7C1471V25 CY7C1473V25 CY7C1475V25 Interleaved Burst Address Table MODE Floating or Vpp be deasserted HIGH before presenting data to the DQs and First Second Third Fourth inputs This tri states the output drivers As a safety Address Address Address Address precaution DQs and are automatically tri stated during A1 A0 1 AO A1 A0 A1 A0 the data portion of a write cycle regardless of the state of OE 00 01 10 11 Burst Write Accesses 01 00 11 10 The CY7C1471V25 CY7C1473V25 and CY7C1475V25 10 1 00 01 have an on chip burst counter that enables the user to supply 11 10 01 00 a single address and conduct up to four Write operations without reasserting the address inputs ADV LD must be driven LOW to load the initial address as described in the Single Write Access section When ADV LD is driven HIGH on Linear Burst Address Table the subsequent clock rise the Chip Enables CE4 and MODE GND CE3 and WE inputs are ignored and the burst counter is incre mented The correct BWy inputs must be driven in each cycle A aon mS oo ress ress ress ress
41. poration e 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 38 05287 Rev l Revised July 04 2007 Feedback CY7C1471V25 E CY7C1473V25 CYPRESS CY7C1475V25 Logic Block Diagram CY7C1471V25 2M x 36 A0 Al A v s gt ADDRESS REGISTER MODE H C D ADV LD CEN q He WRITE ADDRESS REGISTER U D p 4 5 U E 7 T ADV LD N A BWa WRITE one E i WRITE REGISTRY L ARRAY ER J pos BWs AND DATA COHERENCY DRIVERS p E ie e I DOP A ws E BWc CONTROL LOGIC i DOP s E R DQPc S S DQP p WE N E INPUT K REGISTER DE READ LOGIC CE A CE3 SLEEP CONTROL Logic Block Diagram CY7C1473V25 4M x 18 A0 A1 A ADDRESS REGISTER MODE BURST C D ADVILD LOGIC CEN 9 Fe WRITE ADDRESS REGISTER 5 U T D P S A
42. quivalent 0 9V 500 TDO Zo 500 20pF CY7C1471V25 CY7C1473V25 CY7C1475V25 2 5V TAP AC Test Conditions Input p lse levels e Vgg to 2 5V Input rise and fall time ins Input timing reference levels 1 25V Output reference levels 1 25V Test load termination supply voltage 1 25V 2 5V TAP AC Output Load Equivalent 1 25V 500 TDO Zo 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt Ty lt 70 C Vpp 2 375 to 2 625 unless otherwise noted 2 Parameter Description Test Conditions Min Max Unit Output HIGH Voltage loH 1 0 mA Vppa 2 5 2 0 V Vou2 Output HIGH Voltage loH 100 VDDQ 2 5V 2 1 V Vppo 1 8V 1 6 V Output LOW Voltage lo 1 0 mA Vppa 2 5 0 4 V Voi2 Output LOW Voltage 100 pA Vppo 2 5V 0 2 V Vppo 1 8V 0 2 V Vin Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V Vppo 1 8V 1 26 Vpp 0 3 V Vi Input LOW Voltage Vppo 2 5V 0 3 0 7 V Vppa 1 8V 0 3 0 36 V Ix Input Load Current GND lt Vin Vppo 5 5 Identification Register Definitions Instruction Field MX36 CY MXT2 5 Description Revision Number 31 29 000 000 000 Describes the version number Device Depth 28 24
43. ration on Page 1 from 3901 North First Street to 198 Champion Court Changed the description of lx from Input Load Current to Input Leakage Current on page 20 Changed the lx current values of MODE on page 20 from 5 uA and 30 pA to 30 pA and 5 pA Changed the ly current values of ZZ on page 20 from 30 uA and 5 pA to 5 and 30 uA Changed lt Vpp to Vi lt Vpp page 20 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information table Document 38 05287 Rev 1 Page 31 of 32 Feedback Document Title CY7C1471V25 CY7C1473V25 CY7C1475V25 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM CY7C1471V25 CY7C1473V25 CY7C1475V25 with NoBL Architecture Document Number 38 05287 REV B5ue Description of Change H 472335 See ECN VKN Corrected the typo in the pin configuration for 209 Ball FBGA pinout Corrected the ball name for H9 to Vas from Vggq Added the Maximum Rating for Supply Voltage on Vppq Relative to GND Changed trr tz from 25 ns to 20 ns and trpoy from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table 1274732 See VKN AESA Corrected typo in the NOP STALL and DESELECT Cycles waveform Document 38 05287 Rev 1 32 of 32 Feedback
44. s counter or load anew address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW new address be loaded into the device for an access After being deselected ADV LD must be driven LOW to load a new address CLK Input Clock Input Captures all synchronous inputs to the device CLK is qualified with CEN Clock CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with and CE to select or deselect the device Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and to select or deselect the device CE3 Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select or deselect the device OE Input Output Enable Asynchronous Input Active LOW Combined with the synchronous logic Asynchronous block inside the device to control the direction of the IO pins When LOW the IO pins are enabled to behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input Active LOW When asserted LOW the clock signal is recognized by Synchronous the SR
45. th the operation of the device TAP Controller State Diagram C lt RUNTE 1 4 TEST LOGIC RESET 0 SELECT 1 IR SCAN SELECT 1 DR SCAN 0 0 Y Y CAPTURE DR CAPTURE IR Le EXITI DR L UPDATE IR 2 UPDATE DR 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Document 38 05287 Rev 1 CY7C1471V25 CY7C1473V25 CY7C1475V25 Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be un
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