Cypress NoBL CY7C1370DV25 User's Manual
Contents
1. Document 38 05558 Rev D a N QU ox gt u uoo a lt lt E E S S LO F CO T OD CO LO sb CO T O CO CO CO cO CO CO DQPb NC 1 80 A DQb NC 2 79 NC DQb NC g 3 78 NC Vppq Voa 4 77 O Vppa Ves 5 5 76 Vss DQb NC d 6 75 NC DQb NC 7 74 DQPe o 73 E 9 72 O Vss Vss 10 71 Vss PDQL 11 70 DQb DQb 12 69 DQa DQb DQb O 13 68 DQa Vss NC 14 67 Vss NC CY7C1372DV25 es P Ne DD 16 65 Vpp zz Vss 17 1M x 18 HZZ DQa DQb 18 63 DQa DQa DQb 19 62 5 DQa 20 61 Vppo Vss Vss L 21 60 E Vss DQb 22 59 Li DQa DQb 23 58 DQa DQa DQPb 24 57 NC DQa NC 25 56 H NC Vss Vss 26 55 Vss VDbatj 27 54 O DQa NC 28 53 NC DQa NC 29 52 NC DQPa NCC 30 51 CO CO CO CO CO CO CO CO sb sb lt SF SF ob lt O P ao A lt lt lt lt o 9 3 lt lt lt lt lt lt lt lt lt 6522559 5 gt gt 222. 1 ooood py fe c E ooooo ocoooo 6 e e DAC i e 1 3 5 e o 8 8 ooooo ocoooo p L Fa ooooogpooooo 8 M N In eooooooooee r 1 00 5 00 10 00 13 00 0 10 B n 13 00 0 10 A 0 15 4 NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 4759 JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE 0 53 0 05 7 0256 mM e 0456 2 2 57 al 51 85180 A 0 36 0 35 0 06 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05558 Rev D Page 26 of 27 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product
3. Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 167 CY7C1370DV25 167AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1372DV25 167AXC CY7C1370DV25 167BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1372DV25 167BGC CY7C1370DV25 167BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1372DV25 167BGXC CY7C1370DV25 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 167BZC CY7C1370DV25 167BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 167BZXC Lead Free CY7C1370DV25 167AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1372DV25 167AXI CY7C1370DV25 167BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 CY7C1372DV25 167BGI CY7C1370DV25 167BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C4372DV25 167BGXI CY7C4370DV25 167BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 167BZI CY7C1370DV25 167BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 167BZXI Lead Free 200 CY7C1370DV25 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1372DV25 200AXC CY7C1370DV25 200BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1372DV25 200BGC CY7C1370DV25 200BGXC
4. On s 2 ZZ77 _ 27 77 noores ZZ s XL aa UMMM AS ZU ADV LD ee m Data DAD 08 DE QA3 In Out DQ l WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D A1 Q A2 Q A3 D A4 5 DESELECT zZ DON T CARE UNDEFINED ZZ Mode Timing 29 tzzaEC tz SUPPLY rz ALL INPUTS 777 2 DESELECT or READ Only except ZZ m DON T CARE Notes 27 The Ignore Clock Edge or Stall cycle Clock 3 illustrated CEN being used to create a pause A write is not performed during this cycle 28 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 29 1 are in High Z when exiting ZZ sleep mode Document 38 05558 Rev D Page 21 of 27 Feedback 2 CYPRESS PERFORM Ordering Information CY7C1370DV25 CY7C1372DV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered
5. we EE 70 gt i 2 LA I A7 ADDRESS X Al Y A3 i et tas tay I ps DH I toEV tcHZ ue lt Data i D A1 D A2 VA A241 Q A3 Q A4 QUA441 5 6 In Out DQ ti OEHZ id EN tOELZ l i i WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A241 Q A4 1 DON T CARE UNDEFINED 24 For this waveform ZZ is tied LOW 25 When CE is LOW CE is LOW CE is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH 26 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Notes Document 38 05558 Rev D Page 20 of 27 CY7C1370DV25 SS c CYPRESS CY7C1372DV25 PERFORM Switching Waveforms continued NOP STALL and DESELECT 2 25 27 7 8 9 10 1 f T I I I I N 3 f 5 Ee NEL E A WLLL Z 22700 SS eee to re
6. Automatic Vpp Device Deselected All speed grades 80 mA Power down Vin gt Vin or Vy lt Vj f 0 Current TTL Inputs Notes 15 Overshoot lt Vpp 1 5 Pulse width less than 2 undershoot Vi gt 2V Pulse width less than 2 16 Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt and lt Vpp 17 Tested initially and after any design or process change that may affect these parameters Document 38 05558 Rev D Page 17 of 27 Feedback CY7C1370DV25 CYPRESS CY7C1372DV25 P ER FOR M Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Cin Input Capacitance 25 C f 1 MHz 5 8 9 pF Clock Input Capacitance VDD 0 5 8 9 Cio Input Output Capacitance 5 8 9 Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow standard 28 66 23 8 20 7 C W Junction to Ambient test methods and procedures for measuring thermal Thermal Resistance 4 08 6 2 4 0 Junction to Case impedance per EIA JESD51 AC Test Loads and Waveforms 2 5V Test Load R 16670 OUTPUT 2 SV y ALL INPUT PULSES OUTPUT RL 500
7. SM e 4 CY7C1370DV25 YPHES5 CY7C1372DV25 Features Functional Description Pin compatible and functionally equivalent to ZBT The CY7C1370DV25 and CY7C1372DV25 are 2 5V 512K x PERFORM 18 Mbit 512K x 36 1M x 18 Pipelined SRAM with NoBL Architecture Supports 250 MHz bus operations with zero wait states 4 They T Available speed grades are 250 200 and 167 MHz designed to support unlimited true back to back Read Write Internally self timed output buffer control to eliminate Operations with no wait states The CY7C1370DV25 and the need to use asynchronous OE CY7C1372DV25 are equipped with the advanced NoBL logic Full d i d f ipelined required to enable consecutive Read Write operations with registere inputs and outputs for pipeline data being transferred on every clock cycle This feature operation dramatically improves the throughput of data in systems that Byte Write capability require frequent Write Read transitions The CY7C1370DV25 Single 2 5V core power supply Vpp and CY7C1372DV25 are pin compatible and functionally 2 5V I O Iv V equivalent to ZBT devices 4 All synchronous inputs pass through input registers controlled Fast clock to output times by the rising edge of the clock All data outputs pass through 2 6 ns for 250 MHz device output registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when dea
8. BWa P DQP WE 5 R DQPa 1 m gt N E gt G 4 INPUT INPUT REGISTER 1 REGISTER 0 CE2 READ LOGIC SLEEP CONTROL Cypress Semiconductor Corporation 198 Champion Court Jose CA 95134 1709 e 408 943 2600 Document 38 05558 Rev D Revised June 29 2006 Feedback Ti CY7C1370DV25 ZCYPRESS CY7CI372DV25 j PERFORM Logic Block Diagram CY7C1372DV25 1 18 A0 A1 A MODE N WRITE ADDRESS REGISTER 1 0 0 b y y 22 S P D P ADV LD i WRITE REGISTRY BW AND DATA COHERENCY MEMORY E ry D ii am p DEEP BWo L i S z DQP S I R R N i INPUT INPUT K REGISIER1 REGISTER O 4 4 i e D gt OE T READ LOGIC 2 22 control Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2 6 3 0 3 4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA Document 38 05558 Rev D Page 2
9. ES 30 Y 31 50 0 20 MAX 1 60 R0 08 MIN 0 20 MAX 0 MIN SEATING PLANE N STAND OFF 0 05 MIN NOTE 0 15 MAX GAUGE PLANE J 1 JEDEC STD REF 5 026 i 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH 0 08 MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 20 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 51 85050 1 00 p DETAIL Document 38 05558 Rev D Page 24 of 27 Feedback 7 CYPRESS CYPRESS CY7C1370DV25 CY7C1372DV25 PERFORM Package Diagrams continued 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 51 85115 Document 38 05558 Rev D Page 25 of 27 Feedback CY7C1370DV25 d gt CYPRESS CY7C1372DV25 PERFORM Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN 1 CORNER 3 TOP VIEW p V go2sMCAB 00 50 85x 0 14 PIN 1 CORNER w gt u E o o E 6 5 4 3
10. 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1372DV25 200BGXC CY7C1370DV25 200BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 200BZC CY7C1370DV25 200BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 200BZXC Lead Free CY7C1370DV25 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1372DV25 200AXI CY7C1370DV25 200BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 CY7C1372DV25 200BGI CY7C1370DV25 200BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C4372DV25 200BGXI CY7C41370DV25 200BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 200BZI CY7C1370DV25 200BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 200BZXI Lead Free Document 38 05558 Rev D Page 22 of 27 Feedback Ordering Information continued 4 CYPRESS PERFORM CY7C1370DV25 CY7C1372DV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered 250 CY7C1372DV25 250AXI CY7C1370DV25 250BGI CY7C1372DV25 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1370DV25 250AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commer
11. 5pF L 15380 1 25V INCLUDING a JIG AND c scope 0 Document 38 05558 Rev D Page 18 of 27 Feedback CY7C1370DV25 7 CYPRESS CY7C1372DV25 PERFORM Switching Characteristics Over the Operating Range 122 23 250 200 167 Parameter Description Min Max Min Max Unit tPower 3 Vcc typical to the first access read or write 1 1 1 ms Clock Clock Cycle Time 4 0 5 6 ns FMAX Maximum Operating Frequency 250 200 167 MHz tcu Clock HIGH 1 7 2 0 2 2 ns teL Clock LOW 1 7 2 0 2 2 ns Output Times tco Data Output Valid After CLK Rise 2 6 3 0 3 4 ns tEov OE LOW to Output Valid 2 6 3 0 3 4 ns Data Output Hold After CLK Rise 1 0 1 3 1 3 ns tcHz Clock to High Z 9 20 21 2 6 3 0 3 4 ns telz Clock to Low Z 9 20 21 1 0 1 3 1 3 ns tEOHZ OE HIGH to Output 2119 20 21 2 6 3 0 3 4 ns tEOLZ OE LOW to Output Low Z 9 20 21 0 0 0 ns Set up Times tas Address Set up Before CLK Rise 1 2 1 4 1 5 ns tps Data Input Set up Before CLK Rise 1 2 1 4 1 5 ns tcENS CEN Set up Before CLK Rise 1 2 1 4 1 5 ns twes WE BW Set up Before CLK Rise 12 1 4 1 5 ns tALS ADV LD Set up Before CLK Rise 1 2 1 4 1 5 ns tcES Chip Select Set up 1 2 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tpH Data Input Hold After C
12. RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations 119 Ball BGA Boundary Scan Order 12 131 Bit Ball ID Bit Ball ID Bit Ball ID Bit Ball ID 1 H4 23 F6 45 G4 67 L1 T4 24 7 46 4 68 2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 50 B3 72 L2 7 R6 29 D6 51 73 2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 1 12 7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 16 7 38 04 60 H2 82 L4 17 N6 39 B4 61 D1 83 4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 12 Balls which are NC No Connect are pre set LOW 13 Bit 85 is pre set HIGH Document 38 05558 Rev D Page 15 of 27 Feedback CY7C1370DV25 CYPRESS CY7C1372DV25 PERFORM 165 Ball FBGA Boundary Scan Order 14 Bit Ball ID Bit Ball ID Bit Ball ID 1 N6 31 010 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10
13. 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 2 16 Kt 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 4 78 1 19 L10 49 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 ps 84 R4 25 11 55 1 85 4 26 11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Note 14 Bit 89 is pre set HIGH Document 38 05558 Rev D Page 16 of 27 Feedback ae CYPRESS PERFORM Maximum Ratings Above which the useful life may be impaired For user guide DC Input Voltage CY7C1370DV25 CY7C1372DV25 Current into Outputs 20 mA lines not tested Static Discharge gt 2001V Storage Temperature 65 to 150 C Ambient Temperature with Latch up Current sse gt 200 Power 55 to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 3 6V Ambient Supply Voltage on Relative to GND 0 5V to Vpp Range Temperature DC t
14. 85 Boundary Scan Order 165 ball fBGA package 89 89 Identification Register Definitions Instruction Field CY7C1372DV25 CY7C1370DV25 Description Revision Number 31 29 000 000 Reserved for version number Cypress Device ID 28 12 01011001000100101 01011001000010101 Reserved for future use Cypress JEDEC ID 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 1 Indicate the presence of an ID register Note 11 All voltages referenced to Vss GND Document 38 05558 Rev D Page 14 of 27 Feedback I EZ CYPRESS PERFORM 4 Identification Codes CY7C1370DV25 CY7C1372DV25 Instruction Code Description EXTEST 000 Captures ring contents Places the boundary scan register between TDI Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures I O ring contents Places the boundary scan register between TDI Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use
15. Description table for details inputs is latched into the device and the write is complete The data written during the write operation is controlled by BW BW p c a for CY7C1370DV25 and BW p for CY7C1372DV25 Page 7 of 27 Feedback ze CYPRESS PERFORM signals The CY7C1370DV25 CY7C1372DV25 provides byte write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW input will selectively write to only the desired bytes Bytes not selected during a byte write operation will remain unaltered A synchronous self timed write mechanism has been provided to simplify the write operations Byte write capability has been included in order to greatly simplify Read Modify Write sequences which can be reduced to simple byte write operations Because the CY7C1370DV25 and CY7C1372DV25 are common I O devices data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQ and DQP for CY7C1370DV25 and DQ yDQP b for CY7C1372DV25 inputs Doing so will three state the output drivers As a safety precaution DQ and DQP DQa p c g DQPa p c g for CY7C1370DV25 and DQ for 3720 25 are automatically three stated durin ing the data portion of a write cycle regardless of the state of OE 4 Burst Write
16. Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C1370DV25 CY7C1372DV25 is CYPRESS F PERFORM Document History Page 4 Document Title CY7C1370DV25 CY7C1372DV25 18 Mbit 512K x 36 1M x 18 Pipelined SRAM with NoBLTM Architecture Document Number 38 05558 Orig of REV No Issue Date Change Description of Change zi 254509 See RKF New data sheet A 288531 See ECN SYT Edited description under IEEE 1149 1 Serial Boundary Scan JTAG for non compliance with 1149 1 Removed 225 Mhz Speed Bin Added lead free information for 100 Pin TQFP 119 BGA and 165 FBGA package Added comment of Lead free BG packages availability below the Ordering Information B 326078 See ECN PCI Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added
17. Page 3 of 27 Feedback CY7C1370DV25 CYPRESS CY7C1372DV25 PERF ORN M Pin Configurations continued 119 Ball BGA Pinout CY7C1370DV25 512K x 36 1 2 3 4 5 6 7 A Vppa A A A A A VDDQ NC 576M A ADV LD A NC C NC 1G A A Vien A A NC D DQ Ves NC Vss DQ DQ DQ Vss CE Vss DQ DQ F DQ Vss OE Vss DQ DQ BW A BW 67 DQ H DQ DQ Vss WE Vss DQ DQ J Vppa Vpp NC Vpp NC Vpp K Vss CLK Vss DQ DQ L BW NC BW DQ DQ M VDDQ Vss CEN Vss DQa VDDQ N DQg Vas A1 Vss DQ DQ P DG Vss Vss NC 144M A MODE Vpp NC A NC 288M T NC NC 72M A A A NC 36M 22 U VDDQ TMS TDI TCK TDO NC VDDQ CY7C1372DV25 1M x 18 1 2 3 4 5 6 7 Vov A A A A Vona NC 576M CE A ADV LD A VDD A A NG D DQ NC Ves NC Vss DOP NC E NC DQ Vss Vss NC DQ F VDDQ NC Vss Vss VDDQ G NC BW A NC NC DQ H DQ NC Vss WE Vss DQ NC J VDDQ VDD NC VDD NC Vpp Vppo K NC DQ Vss CLK Vss NC DQ L DQ NG NC NC BW DQ NC M DQb Vss CEN Vss NC DQ NC Veg A1 Vss DQ NC P NC DAP Vss Vss NC DQ R NCA44MM MODE NC NC 288M T NC 72M A A NC 36M A A 22 0 Vooo TM
18. of 27 Feedback CYPRESS PERFORM 1 100 Pin TQFP Pinout CY7C1370DV25 CY7C1372DV25 Pin Configurations L S S 2 gt lt lt DREE 8232689 lt lt lt lt i So SO OS DQPc 1 80 DQco 2 79 DQcH 3 78 Vppor 4 7 Vss O 5 76 DQc 6 75 DQc 7 74 DQc 8 73 DQc 9 72 Vss 10 71 Vppqr 11 70 DQcH 12 DQc 13 n V i CY7C1370DV25 67 NC d 46 512K x 36 Vss 17 64 DQdq 18 63 DQdq 19 62 20 61 Vss O 21 60 DQdr 22 59 91619 23 58 DQdrj 24 57 DQdH 25 56 Ves 26 55 27 54 DQdr 28 53 DQdH 29 52 DQPdr 30 51 N CO st LO CO OO QUI st LO CO CO CO CO CO CO CO sb sb SE Sb sb Sb Sb lt lt 90588 lt lt lt lt lt lt lt 59 29g 22
19. 0 11 mented The correct BW BW pc q for CY7C1370DV25 and 01 10 1 00 BW b for CY7C1372DV25 inputs must be driven in each cycle of the burst write in order to write the correct bytes of 10 11 00 01 data 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 80 mA 1775 Device operation to ZZ ZZ Vpp 0 2V 2tcyc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ active to sleep current This parameter is sampled 2tcyc ns ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05558 Rev D Page 8 of 27 Feedback i CY7C1370DV25 s CYPRESS CY7C1372DV25 PERFORM Truth Tablel 2 3 4 5 6 7 Address Operation Used ZZ ADV LD WE BW OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri state Continue Deselect Cycle None X L H X X X L L H Tri state Read Cycle Begin Burst External L L L H X L L L H Data Out Q Read Cycle Continue Burst Next X L H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L L H X H L L H Tri state Dummy Read Continue Burst Next X L H X X L L H Tri state Write Cycle Begin Burst External L L L L L X L L H Data In D Write Cycle Continue Burst Next X L H X L X L L H Dat
20. Accesses The CY7C1370DV25 CY7C1372DV25 has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs ADV LD must be driven LOW CY7C1370DV25 CY7C1372DV25 Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 and CE3 must remain inactive for the duration of tzzpec after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND I Fi Thi F h in order to load the initial address as described in the Single HM Write Access section above When ADV LD is driven HIGH on the subsequent clock rise the chip enables CE CE and A1 A0 A1 A0 A1 A0 A1 A0 and WE inputs are ignored and the burst counter is incre 00 01 1
21. LK Rise 0 3 0 4 0 5 ns tcENH CEN Hold After CLK Rise 0 3 0 4 0 5 ns twEH WE BW Hold After CLK Rise 0 3 0 4 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 4 0 5 ns Chip Select Hold After CLK Rise 0 3 0 4 0 5 ns Notes voltage regulator internally tpower is the time power needs to be supplied above Vpp minimum initially before a Read or Write operation can 19 tcuz teorz and are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 20 At any given voltage and temperature is less than tgo 7 and is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 21 This parameter is sampled and not 100 tested 22 Timing reference 1 25V when 2 5V 23 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05558 Rev D Page 19 of 27 Feedback CY7C1370DV25 CYPRESS CY7C1372DV25 Switching Waveforms Read Write Timingl 25 26 i 4 5 6 7 8 9 10 SE a m d d ES A AT cH I tCES lt 4 5 MA A A 7 Ws
22. S TDI TDO NC Venn Document 38 05558 Rev D Page 4 of 27 Feedback E CY7C1370DV25 TZ CYPRESS CY7C1372DV25 PERFORM Pin Configurations continued 165 Ball FBGA Pinout CY7C1370DV25 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A NC 576M CE BW BW CEN ADV D A A NC B NC 1G A CE2 BW CLK WE OE A A NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D DQ DQ VDD Vss Vss Vss VDD VDDQ DQ E DQ Vpp Vss Vss Vss Vpp DQ DQ F DQ Vpp Vss Vss Vss Vpp 20 DQ G DQ DQ VDDQ VDD Vss Vss Vss Vpp Vppo DQ DQ H NC NC NC Vio Vss Vss Vss Vpp NC NC ZZ J DQg Vpp Vss Vss Vss DQ DQ K DQg Vpp Vss Vss Vss Vppo DQ DQ L DQg DQg Vpp Vss Vss Vss Vpp Vppa DQ DQ M DQg Vss Vss Vss Vpp Vppo DQ DQ N NC Ves NC NC NC Vss Vba NC P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS TCK A A A A CY7C1372DV25 1M x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 576M CE BW NC CEN ADV D A A A B NC 1G A CE2 NC BW CLK WE OE A A NC C NC NC Vss Vss Vss Vss Vss VDDQ NC DQPa D NC DQ Vss Vss Vss Vpp VDDQ NC DQ E NC Vpp Vss
23. Vss Vss Vpp Vppo NC DQa F NC Vss Vss Vss Vppo NC DQ G NC DQ Vss Vss Vss Vpp Vppo NC DQa H NC NC NC Vi Vss Vss Vss NC NC 27 J Vss Vss Vss Vppa DQ NC K DQb NC Vss Vss Vss Vpp Vppo DQ NC L Vss Vss Vss Vpp DQ NC M Vss Vss Vss Vppa DQ NC NC Vooo Vss NC NC NO Vas Vong NC NC P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS TCK A A A A Document 38 05558 Rev D Page 5 of 27 Feedback e YPRESS PERFORM Pin Definitions CY7C1370DV25 CY7C1372DV25 Pin Name Type Pin Description Input Address Inputs used to select one of the address locations Sampled at the rising edge of A1 Synchronous the CLK A BW Input Byte Write Select Inputs active LOW Qualified with WE to conduct writes to the SRAM Synchronous Sampled on the rising edge of CLK BW controls DQ and BW controls DQ and BW BW controls DQ BW controls DQq and DQPg Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input used to adva
24. a In D NOP Write Abort Begin Burst None L L L L H X L L H Tri state Write Abort Continue Burst Next X L H X H X L L H Tri state Ignore Clock Edge Stall Current X L X X X X H L H Sleep Mode None X H X X X X X X Tri state Partial Write Cycle Description 2 3 8 Function CY7C1370DV25 WE BW BW BW BW Read H X X X X Write No bytes written L H H H H Write Byte a DQ and DQP L H H H L Write Byte b DQ L H H L H Write Bytes b a L H H L L Write Byte c DQ and L H L H H Write Bytes c a L H L H L Write Bytes c b L H L L H Write Bytes c b a L H L L L Write Byte d and L L H H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Notes 1 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWx L signifies at least one Byte Write Select is active BW Valid signifies that the desired byte write selects are asserted see Write Cycle Description table for details Write is defined by WE and BWy See Write Cycle Description table for details When a write cycle is detected all I Os are tri stated even during byte writes The DQ and pins are controlled by the current cycle and the OE signal CEN H inserts wait states paves Device will po
25. bit will directly control the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Clock TCK Test Mode Select TMS Test Data In TDI Test Data Out TDO DONTCARE UNDEFINED Document 38 05558 Rev D Page 12 of 27 Feedback EU CY7C1370DV25 CYPRESS CY7C1372DV25 PERFORM AC Switching Characteristics Over the Operating Rangel 10 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tn TCK Clock LOW time 20 ns Output Times Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set up to TCK Clock Rise 5 ns trpis TDI Set up to TCK Clock Rise 5 ns Capture Set up to Rise 5 ns Hold Times trMSH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns icu Capture Hold after Clock Rise 5 ns Notes 9 tcs and tcu refer to the set up and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the loa
26. by the Synchronous SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required DQs Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered Synchronous the rising edge of CLK As outputs they deliver the data contained in the memory location specified by A 47 9 during the previous clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ DQg are placed in a three state condition The outputs are automatically three stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE Bidirectional Data Parity I O lines Functionally these signals are identical to DQ During write Synchronous sequences is controlled by BW is controlled by BWp is controlled by BW and DQPj is controlled by BW MODE Input Strap Pin Mode Input Selects the burst order of the device Tied HIGH selects the interleaved burst order Pulled LOW selects the linear burst order MODE should not change states during operation When left floating MODE will default HIGH to an interleaved burst order TDO serial Serial data out to the JTAG circu
27. cial CY7C1372DV25 250AXC CY7C1370DV25 250BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1372DV25 250BGC CY7C1370DV25 250BGXO 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1372DV25 250BGXC CY7C1370DV25 250BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 250BZC CY7C1370DV25 250BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372DV25 250BZXC Lead Free CY7C1370DV25 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1370DV25 250BGXI CY7C1372DV25 250BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1370DV25 250BZI CY7C1372DV25 250BZ7I CY7C1370DV25 250BZXI CY7C1372DV25 250BZXI 51 85180 51 85180 165 ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm 165 ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Lead Free Document 38 05558 Rev D Page 23 of 27 Feedback j j CY7C1370DV25 CYZCIS72DV25 PERFORM Package Diagrams 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 j 1400010 1 40 0 05 100 81 g 1 m E 80 eo E ES ES ES 0 30 0 08 ES ES ES s 3 g d S E T Es I ES E 77 SEE DETAIL A TYP ES ES
28. d in AC test Conditions 1 ns Document 38 05558 Rev D Page 13 of 27 Feedback 2 5V TAP AC Test Conditions CY7C1370DV25 CY7C1372DV25 2 5V TAP AC Output Load Equivalent Input pulse levels Vss to 2 5V 1 25V Input rise and fall 1ns Input timing reference levels 1 25V 500 Output reference levels 1 25V TDO Test load termination supply voltage 1 25V 2 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt TA lt 70 Vpp 2 5V 0 125V unless otherwise noted Parameter Description Test Conditions Min Max Unit Output HIGH Voltage 1 0 2 5 2 0 V Output HIGH Voltage 100 pA Vppo 2 5V 2 1 V Vout Output LOW Voltage 8 0 MA Vppo 2 5V 0 4 V VoL2 Output LOW Voltage loL 100 pA 2 5V 0 2 V Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V ViL Input LOW Voltage Vppo 2 5V 0 3 0 7 V Input Load Current GND lt Vin lt Vppo 5 5 Scan Register Sizes Register Name Bit Size x18 Bit Size x36 Instruction 3 Bypass 1 ID 32 32 Boundary Scan Order 119 ball BGA package 85
29. description on EXTEST Output Bus Tri State Changed description on the Tap Instruction Set Overview and Extest Changed 0 4 and for TQFP Package from 31 and 6 C W to 28 66 and 4 08 C W respectively Changed j4 and jc for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed and jc for FBGA Package from 46 and C W to 20 7 and 4 0 C W respectively Modified VoL Vox test conditions Removed comment of Lead free BG packages availability below the Ordering Information Updated Ordering Information Table C 418125 See ECN NXR Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 8901 North First Street to 198 Champion Court Changed the description of lx from Input Load Current to Input Leakage Current on page 18 Changed the current values of MODE on page 18 from 5 pA and 30 pA to 30 nA and 5 uA Changed the ly current values of ZZ on page 18 from 30 uA and 5 pA to 5 and 30 uA Changed lt Vpp to lt Vppon page 18 Updated Ordering Information Table D 475677 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Changed trr tr from 25 ns to 20 ns and from 5 ns to 10 ns AC Switching Characteristics table Updated the Ordering Information table Document 38 05558 Rev D Page 27 of 27 Feedback
30. ed data can be shifted in Page 11 of 27 Feedback See 022 SS CYPRESS PERFORM BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST Bus Tri State IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 285 for 119 BGA package or bit 89 for 165 fBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the TAP Timing CY7C1370DV25 CY7C1372DV25 current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload register When the EXTEST instruction is entered this
31. gned specifi cally to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 6 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a read or write operation depending on the status of the Write Enable WE BWy can be used to conduct byte write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE and an asynchronous Output Enable OE simplify depth expansion operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisf
32. ied at clock rise 1 CEN is asserted LOW 2 CE4 and are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2 6 ns 250 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in Document 38 05558 Rev D second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output will three state following the next clock rise Burst Read Accesses The CY7C1370DV25 and CY7C1372DV25 have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determi
33. it Delivers data on the negative edge of output Synchronous TDI JTAG serial Serial data In to the JTAG circuit Sampled on the rising edge of TCK input Synchronous TMS Test Mode This pin controls the Test Access Port state machine Sampled on the rising edge of TCK Select Synchronous TCK JTAG Clock input to the JTAG circuitry Document 38 05558 Rev D Page 6 of 27 Feedback CYPRESS PERFORM Pin Definitions continued CY7C1370DV25 CY7C1372DV25 Pin Name Type Pin Description Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Power supply for the I O circuitry Supply Vss Ground Ground for the device Should be connected to ground of the system NC connects This is not connected to the die NC 36M 72M These pins not connected They will be used for expansion to the 36M 72M 144M 288M 144M 288M 576M and 1G densities 576 1G ZZ Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down Introduction order for the device to drive out the requested data During the Functional Overview The CY7C1370DV25 and CY7C1372DV25 synchronous pipelined Burst NoBL SRAMs desi
34. n register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the in struction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is cap tured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while
35. nce the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN Clock CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select deselect the device Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and to select deselect the device OE Input Output Enable active LOW Combined with the synchronous logic block inside the device to Asynchronous control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH pins are three stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the clock signal is recognized
36. ned by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use 0 and A1 in the burst sequence and will wrap around when incremented suffi ciently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and CE are ALL asserted active and 3 the write signal WE is asserted LOW The address presented is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically three stated regardless of the state of the OE input signal This allows the external logic to present the data on DQ and DQP DQ p c DQPa p c q for CY7C1370DV25 DQ yDQPa b for CY7C1372DV25 In addition the address for the subse quent access Read Write Deselect is latched into the Address Register provided the appropriate control signals are asserted On the next clock rise the data presented to DQ and DQP DQa p c g DQPa p c q for CY7C1370DV25 amp DQ DQP A b for CY7C1372DV25 or a subset for byte write operations see Write Cycle
37. o Outputs in Tri State 0 5V to Vppg 0 5V Commercial 0 to 70 2 5V 5 Industrial 40 to 85 C Electrical Characteristics Over the Operating Rangel 161 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 2 375 2 625 V VDDQ Supply Voltage for 2 5V 2 375 Vpp V VoH Output HIGH Voltage for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage for 2 5V I O 1 0 mA 0 4 V Input HIGH Voltage for 2 5V 17 Vpp 0 3V V Input LOW Voltage 7 for 2 5V 0 3 0 7 Ix Input Leakage Current GND lt V lt Vppo 5 5 uA except ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 uA loz Output Leakage Current GND lt V lt Vpp Output Disabled 5 5 155 Vpp Operating Supply Vpp Max lour 0 mA 4 0 ns cycle 250 MHz 350 mA f fmax 1 5 0 ns cycle 200 MHz 300 mA 6 0 ns cycle 167 MHz 275 mA Ispi Automatic CE Vpp Device Deselected 4 0 cycle 250 MHz 160 mA ays a n or Vin lt Vit f 5 0 ns cycle 200 MHz 150 mA 6 0 ns cycle 167 MHz 140 mA Ispo Automatic CE Vpp Device Deselected All speed grades 70 mA Power down Vin lt 0 3V or Vin gt 0 3V Current CMOS Inputs f 0 Vpp Device Deselected 4 0 cycle 250 MHz 135 mA 6 0 ns cycle 167 MHz 125 mA
38. oaded into the TAP instruction register For information on loading the instruction register see TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram gt 0 Bypass Register 2 1 0 Selection Instruction Register Circuitry Selection pisopg 21 0 Circuitry TDI TDO Identification Register T Boundary Scan Register TMS CONTROLLER Performing Reset RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state Page 10 of 27 Feedback ES Cypress CYPRESS PERFORM TAP Registers Registers are connected between the TDI and TDO ball
39. pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RESET 0 Y o RUN TEST 1 SELECT 1 SELECT 1 n DR SCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIFT DR D SHIFT IR D UPDATE DR UPDATE IR a 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 38 05558 Rev D The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is l
40. s and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM ring
41. sserted suspends operation and extends the Clock Enable CEN pin to suspend operation Synchronous self timed writes previous clock cycle Available in JEDEC standard lead free 100 Pin TQFP Write operations are controlled by the Byte Write Selects lead free and non lead free 119 Ball BGA and 165 Ball BW BWg for CY7C1370DV25 and BW BW for FBGA packages CY7C1372DV25 and a Write Enable WE input All writes are IEEE 1149 1 JTAG Compatible Boundary Scan conducted with on chip synchronous self timed write circuitry uL i Three synchronous Chip Enables CE4 CE3 and Burst capability or interleaved sa asynchronous Output Enable OE provide for easy bank ZZ Sleep Mode option and Stop Clock option selection and output three state control In order to avoid bus contention the output drivers are synchronously three stated during the data portion of a write sequence Logic Block Diagram CY7C1370DV25 512K x 36 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 2 WRITE ADDRESS REGISTER 1 o 0 E y D U gt P A T N P ADV LD E T WRITE REGISTRY R BW AND DATA COHERENCY WRITE MEMORY 5 gt DQs BW CONTROL LOGIC DRIVERS DA ABNF DA p n D BW M 5 E F
42. the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possi ble that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the bound ary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preload
43. wer up deselected and the I Os a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQ and DQPy Three state when OE is inactive or when the device is deselected and DQ data when OE is active Document 38 05558 Rev D Table only lists a partial listing of the byte write combinations Any Combination of is valid Appropriate write will be done based on which byte write is active Page 9 of 27 Feedback CY7C1370DV25 CYPRESS CY7C1372DV25 PERFORM Function CY7C1372DV25 WE BW BW Read H x x Write No Bytes Written L H H Write Byte a DQ and L H L Write Byte b and L L H Write Both Bytes L L L IEEE 1149 1 Serial Boundary Scan JTAG Test Mode Select TMS The CY7C1370DV25 CY7C1372DV25 incorporates a serial boundary scan test access port TAP This part is fully compliant with 1149 1 The operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1370DV25 CY7C1372DV25 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS inter nally
44. when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted Document 38 05558 Rev D CY7C1370DV25 CY7C1372DV25 through the instructio
Download Pdf Manuals
Related Search