Cypress NoBL CY7C1355C User's Manual
Contents
1. CY7C1355C 256K x 36 CY7C1357C 512K x 18 Signal Signal Signal Signal Bit ball ID Name Bit ballID Name Bit ball ID Name Bit ball ID Name 1 B6 CLK 37 R4 A B6 CLK 37 R4 A 2 B7 WE 38 P4 A 2 B7 WE 38 P4 A 3 39 R3 A 3 A7 CEN 39 R3 A 4 B8 OE 40 P3 A 4 B8 OE 40 P3 A 5 A8 ADV LD 41 R1 MODE 5 A8 ADV LD 41 R1 MODE 6 A9 A 42 N1 DQPp 6 A9 A 42 Internal Internal 7 B10 A 43 L2 DQp 7 B10 A 43 Internal Internal 8 A10 A 44 K2 DQp 8 A10 A 44 Internal Internal 9 C11 45 DQp 9 11 45 Internal Internal 10 E10 46 2 DQp 10 Internal Internal 46 N1 DQPg 11 F10 DQg 47 M1 DQp 11 Internal Internal 47 M1 DQg 12 G10 DQg 48 L1 DQp 12 Internal Internal 48 L1 DQg 13 D10 DQg 49 K1 DQp 13 C11 DOP 49 K1 DQg 14 011 DQg 50 J1 DQp 14 011 DQ 50 J1 DQg 15 E11 DQg 51 Internal Internal 15 E11 51 Internal Internal 16 F11 DQg 52 G2 DQc 16 F11 52 G2 DQg 17 DQg 53 F2 17 G11 53 F2 18 H11 22 54 2 DQc 18 H11 ZZ 54 E2 19 J10 55 2 DQc 19 J10 55 02 DQg 20 K10 DQA 56 G1 DQc 20 K10 56 Internal Internal 21 L10 57 F1 DQc 21 L10 57 Internal Internal 22 M10 58 DQc 22 M10 58 Internal Internal 23 J11 59 01 DQc 23 Internal Internal 59 Internal Internal 24 K11 60 C1 24 Internal Internal2. BOTTOM VIEW PIN 1 CORNER TOP VIEW amp g005MC V 0025 1 CORNER 00 50 7906 165X 30 14 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 2 1 0000000000 ET D Qooooooocooo D E Oo 000 o e d H d G H E i 2 2 2 n L T 8 M 5 OO0O00 00000 0 M N OO Q N P R Oooo0 9 R A 1 00 1 5 00 10 00 13 002010 B 1300 010 5 0 15 4 NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 4759 JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 0 53 0 05 Z ozsc 2 036 5340 au e esc SEATING PLANE C 51 85180 A 0 35 0 06 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05539 Rev E Page 27 of 28 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change withou
3. H X X w 9 x rrrim Tri State Partial Truth Table for Read Write 3 9 Function CY7C1355C gt o 5 Read Write No bytes written Write Byte A DQ and DQPA Write Byte B DQg and Write Byte C DQc Write Byte D DQp and DQPp Write All Bytes Truth Table for Read Write 39 Function CY7C1357C w z z w 8 Ww Read Write No bytes written Write Byte A DQ and DQPA Write Byte B DQg and DQPp Write All Bytes Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW is valid Appropriate write will be done based on which byte write is active Document 38 05539 Rev E r rir 2 Page 10 of 28 Feedback SES Cypress CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1355C CY7C1357C incorporates a serial boundary scan test access port TAP in the BGA package only The TQFP package does not offer this functionality This part operates in accordance with IEEE Standard 1149 1 1900 but doesn t have the set of functions required for full 1149 1 compliance These functions from the IEEE spec
4. The 0 1 next to each state represents the value of TMS at the rising edge of the TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 38 05539 Rev E CY7C1355C CY7C1357C Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram i Bypass Register
5. Name 1 0 Description TMS JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous 15 not being utilized this be disconnected or connected to Vpp This pin is not available on TQFP packages JTAG Clock input to the JTAG circuitry If the JTAG feature is not being utilized this pin must Clock be connected to Vas This pin is not available on TQFP packages NC No Connects Not internally connected to the die 18 Mbit 36 Mbit 72 Mbit 144 Mbit 288 Mbit 576 Mbit and 1G are address expansion pins and are not internally connected to the die Vgg DNU Ground DNU This pin can be connected to Ground or should be left floating Functional Overview CY7C1355C CY7C1357C is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recog nized all internal states are maintained All synchronous operations are qualified with CEN Maximum access delay from the clock rise is 6 5 ns 133 MHz device Accesses can be initiated by asserting all three Chip Enables CE4 CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is ass
6. pe 0 Selection un Instruction Register TDI gt Circuitry Seledion 313029 2 1 0 gt Circuitry Identification Register Boundary Scan Register I T T T TAP CONTROLLER TDC o 5 gt Performing a TAP Reset A RESET is performed by forcing TMS HIGH VDD for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Page 11 of 28 Feedback CYPRESS CYPRESS PERFORM i Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the
7. mn m SM CY7C1355C SSE ecr CYPRESS 7 1357 PERFOR 9 Mbit 256K x 36 512K x 18 Flow Through SRAM with NoBL Architecture Features Functional Description No Bus Latency NoBL architecture eliminates The CY7C1355C CY7C1357C is a 3 3V 256K x 36 512K x 18 dead cycles between write and read cycles Synchronous Flow through Burst SRAM designed specifically to support unlimited true back to back Read Write operations without the insertion of wait states The Can support up to 133 MHz bus operations with zero walt states CY7C1355C CY7C1357C is equipped with the advanced No Data is transferred on every clock Bus Latency NoBL logic required to enable consecutive Pin compatible and functionally equivalent to ZBT Read Write operations with data being transferred on every devices clock cycle This feature dramatically improves the throughput m f h h the SRAM ially i h i Internally self timed output buffer control to eliminate ee y In Systems that require the need to use OE A All synchronous inputs pass through input registers controlled Registered inputs for flow through operation by the rising edge of the clock The clock input is qualified by Byte Write capability the Clock Enable CEN signal which when deasserted 3V 2 5V V suspends operation and extends the previous clock cycle
8. V O Power Supp Vona Maximum access delay from the clock rise is 6 5 ns 133 2 Fast clock to output times device 6 5 ns for 133 2 device Write operations are controlled by the two or four Byte Write Clock Enable CEN pin to enable clock and suspend Select BWx and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry operation writ Synchronous self timed writes Three synchronous Chip Enables CE4 CE3 and an A h Output Enabl asynchronous Output Enable OE provide for easy bank VEE enable selection and output tri state control In order to avoid bus Available in JEDEC standard and lead free 100 Pin contention the output drivers are synchronously tri stated TQFP lead free and non lead free 119 Ball BGA during the data portion of a write sequence package and 165 Ball FBGA package Three chip enables for simple depth expansion Automatic Power down feature available using ZZ mode or CE deselect 1149 1 JTAG Compatible Boundary Scan Burst Capability linear or interleaved burst order Low standby power Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6 5 7 5 ns Maximum Operating Current 250 180 mA Maximum CMOS Standby Current 40 40 mA Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress S
9. lt lt lt lt 9 3 R 8 Ys 99 22 Document 38 05539 Rev CY7C1355C CY7C1357C DOP DQg DQg Vss DQ DQ DQ DQ DQg DQg Vss NC Vpp ZZ DQ Vss DQA pap BYTE of 28 Feedback 4 CYPRESS PERFORM Pin Configurations continued 100 Pin Pinout S B lt lt Besskees2seebwees lt lt 8 9905 083958 gt 58680258 o NC 1 80 2 79 NCL 3 78 Vppa 4 77 Vss 5 76 NC 6 75 NC 7 74 DQg 8 73 DQg H 9 72 Vss 10 71 H 11 70 DQg 12 69 DQg 13 68 Vss DNU ia CY7C1357C e Vpp 15 66 BYTEB NC 16 65 Vss 17 64 DQg 18 63 DQg 19 62 20 61 Vss 21 60 22 59 23 58 24 57 NC 25 56 Vss 26 55 Vppa 27 54
10. 10 11 00 01 Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation 11 00 01 10 guaranteed device must be deselected prior to entering the sleep mode CE CEs and CE3 must remain inactive for the duration of tzzpgec after the ZZ input returns LOW ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 50 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ lt 0 2V 2tcyc ns ZZ active to sleep current This parameter is sampled 2tcyc ns trzzI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 4 5 6 7 8 Address es J Operation Used ZZ ADV LD BW OE CLK DQ Deselect Cycle None L X X X L H Tri State Deselect Cycle None X X L X X X L H Tri State Deselect Cycle None X L X L L X X X L H Tri State Continue Deselect Cycle None X X X L L gt H Tri State READ Cycle Begin Burst External L H LY L L H X L L 5H Out READ Cycle Continue Burst Next X X L L 5H Out NOP DUMMY READ Begin Burst External L H L L L H X H L H Tri State DUMMY READ Continue Burst Next H X X H L gt H Tri State WRITE Cycle Begin Burst External L H L L L L L X L L gt H Data In D WRITE Cy
11. 3 3V I O Test Load R 3170 UE 3 3V ALL INPUT PULSES OUTPUT 500 5 pF 3510 Vr 1 5V INCLUDING gt JIG AND a a scope 0 R 16670 OUTPUT 500 5 pF R 15380 Vr 1 25V INCLUDING JIGAND L scope 0 c Note 15 Tested initially and after any design or process change that may affect these parameters Document 38 05539 Rev E Page 19 of 28 Feedback CY7C1355C ET CYPRESS CY7C1357C reer Switching Characteristics Over the Operating Range 17 133 100 Parameter Description Min Max Min Max Unit tPOWER Vpp Typical to the First Access 8l 1 1 ms Clock 7 5 10 ns Clock HIGH 3 0 4 0 ns Clock LOW 3 0 4 0 ns Output Times lcpv Data Output Valid after CLK Rise 6 5 7 5 ns Data Output Hold after CLK Rise 2 0 2 0 ns 2 Clock to 219 20 21 0 0 ns 2 Clock to High z 9 20 21 3 5 3 5 ns OE LOW to Output 3 5 3 5 ns toELz OE LOW to Output 219 20 21 0 0 ns 2 OE HIGH to Output 2119 20 21 3 5 3 5 ns Set up Times tas Address Set up before CLK Rise 1 5 1 5 ns tats ADV LD Set up before CLK Rise 1 5 1 5 ns twes WE BW Set up before CLK Rise 1 5 1 5 ns tcENS CEN Set up before CLK Rise 1 5 1 5 ns tps Data Input Set up befor
12. 60 Internal Internal 25 L11 61 2 25 Internal Internal 61 B2 A 26 M11 DQA 62 A2 A 26 Internal Internal 62 A2 A 27 N11 DQPA 63 A3 CE 27 Internal Internal 63 A3 CE 28 R11 A 64 B3 28 R11 A 64 B3 29 10 65 4 BWp 29 R10 A 65 Internal Internal 30 P10 A 66 4 BWc 30 P10 A 66 Internal Internal 31 R9 A 67 A5 31 R9 A 67 4 BWg 32 P9 A 68 B5 32 P9 A 68 B5 BWa 33 R8 A 69 A6 CE 33 R8 A 69 A6 34 8 34 8 35 R6 AO 35 R6 0 36 6 1 36 P6 Al Document 38 05539 Rev E Page 17 of 28 Feedback 7 1355 eed lt CYPRESS CY7C1357C OE Maximum Ratings DC Input Voltage 0 5V to Vpp 0 5V LAbavawhich fie aeui fe maybe dmpsired For aserauides Current into Outputs 20 mA lines not tested Static Discharge Voltage eese gt 2001V Storage Temperature 65 C to 150 C Method OMS Ambient Temperature with Latch up gt 200 mA Power 55 to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range Temperature Vpp Vppa DC Voltage Applied to Outputs Co
13. NC Vii Vss Vss Vss NC NC ZZ J DQp DQp Vppa Vss Vss Vss Vpp Vppa DQa K DQp DQp VDDQ VDD Vss Vss Vss VDD VDDQ DQa L DQp DQp VDDQ VDD Vss Vss Vss VDD VDDQ DQp DQp VDDQ Vpp Vss Vss Vss Vpp VDDQ DQA NC NC NC NC Vss NC P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS A0 CY7C1357C 512K x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 576M CE BW NC ADV LD NC 1G A CE2 NC BW CLK WE OE NC 18M A NC NC Vss Vss Vss Vss Vss NC D NC DQg Vppo Vpp Vss Vss Vss Vpp DQ E NC DQg Vpp Vss Vss Vss Vpp VDDQ NC NC DQg Vpp Vss Vss Vss Vpp VDDQ NC DQg Vppo Vpp Vss Vss Vss Vpp DQ H NC NC NC Von Vss Vss Vss NC NC 77 J DQg NC VDDQ VDD Vss Vss Vss VDD VDDQ K DQg NC VDDQ Vpp Vss Vss Vss Vpp VDDQ L DQg NC VDDQ Vpp Vss Vss Vss Vpp VDDQ DQg NC Vppo Vpp Vss Vss Vss Vpp VDDQ N NC Voa Vss NC NC NC Vss Vowa NG P 144 72 TDI Al TDO A A A NC 288M R NC 36M 5 0 Document 38 05539 Rev E Page 6 of 28 Feedback 7 CYPRESS PERFORM Pin Definitions CY7C1355C CY7C1357C Name
14. select deselect the device OE Input Output Enable asynchronous input active LOW Combined with the synchronous logic Asynchronous block inside the device to control the direction of the I O pins When LOW the I O pins allowed to behave as outputs When deasserted HIGH I O pins tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by Synchronous SRAM When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQ Bidirectional Data I O lines As inputs they feed into an on chip data register that is Synchronous triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ and DQPy are placed in
15. 2 4 mm CY7C1357C 100BGI CY7C41355C 100BGXI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1357C 100BGXI CY7C1355C 100BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1357C 100BZI CY7C1355C 100BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1357C 100BZXI Document 38 05539 Rev E Page 24 of 28 Feedback Package Diagrams CY7C1355C CY7C1357C 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 100 81 80 0 30 0 08 m i i 1 e S om H H e e e N L 0 65 TYP 30 51 31 50 R 0 08 MIN 0 20 MAX 0 MIN STAND OFF 0 05 0 25 f H 0 15 MAX GAUGE PLANE LEA W i e R 0 08 MIN oe 0 20 MAX 0 60 0 15 H 0 20 MIN 1 00 REF DETAIL Document 38 05539 Rev 1 40 0 05 DETAIL 1 0 20 MAX 1 60 SEATING PLANE 1 JEDEC STD REF 5 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS C 0 10 NOTE 51 85050 B Page 25 of 28 Feedback Package Diagrams continue
16. 28 53 29 52 NC 30 51 5 505585855868 252952985 lt lt lt lt 2 gt lt lt lt lt lt lt lt S 99 Document 38 05539 Rev NC 288M NC 144M CY7C1355C CY7C1357C NC NC Vppa Vss NC DAP DQ DQ DQ Vss NC Vpp ZZ DQ Vss 4 28 Feedback Pin Configurations continued 119 Ball BGA Pinout 3 Chip Enables with JTAG CY7C1355C 256K x 36 1 2 3 4 5 6 7 Nowa A A NO 8M A Vana NC 576M NC A Vis NC D Vss NC Vss DOP DQ E DQc DQc Vas CE Vas VDDQ DQc Vss OE Vss BW A BW DQg DO DQ Vs WE J NC NC 54 CLK Vss DQ L DQp DQp BWp NC M DQp Vss CEN Vss DQ DQ Vss 1 Vss DQp DQPp Vss AO Vss DQPA 144 MODE 288 72 NC 36M ZZ U Voa TMS TDO NC CY7C1357C 51
17. 2K x 18 1 2 3 4 5 6 7 Vona A 48 Von B NC 576M A ADV LD A C A A rae D NC Vss Vss DOP NC E NC Vas Vas NC DO F VDDQ NC Vss OE Vss DQa DQg Vss NC DQ NC WE NC J Vpp NC Vpp VDDQ K NC DQg Vss CLK Vss NC L Vss NC BW Vss CEN Vss NC VDDQ N NC Vee 1 Vss DQ NC P NC Vss A0 Ves NC 144 MODE 288 72 NC 36M A A ZZ U Vba TMS TDI TCK TDO NC Document 38 05539 Rev E CY7C1355C CY7C1357C Page 5 of 28 Feedback gpa CY7C1355C CYPRESS CY7C1357C PERFORM Pin Configurations continued 165 Ball FBGA Pinout 3 Chip enable with JTAG CY7C1355C 256K x 36 1 2 3 4 5 6 7 8 9 10 11 NC 576M CE BWc BWg ADV LD B NC 1G A CE2 BWp BW CLK WE OE NC 18M A NC C DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D VDDQ Vpp Vss Vss Vss VDD VDDQ DQg DQg E DQc Vppa Vpp Vss Vss Vss Vpp DQg DQg F DQc Vpp Vss Vss Vss VDD VDDQ VDDQ VDD Vss Vss Vss VDD VDDQ DQg DQg H NC NC
18. 357C PERFORM TAP Timing 1 2 3 4 5 6 Test Clock ind tH 5n truss Test Mode Select AE E TM S tos Test Data In yl V TDI by Test Data Out X TDO DON T CARE UNDEFINED AC Switching Characteristics Over the Operating Rangel 111 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns 20 2 try TCK Clock HIGH Time 20 ns tr TCK Clock LOW Time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set Up to TCK Clock Rise 5 ns TDI Set Up to Clock Rise 5 ns Capture Set Up to Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns Notes 10 tcs and refer to the set up and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load AC Test Conditions 1 ns Document 38 05539 Rev Page 13 of 28 Feedback 3 3V Test Conditions Input pulse Vgg to 3 3V Input rise and fall 41040411 1ns Input timing reference 1 5V Output reference 1 5V Test load termination supply vol
19. 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table Document 38 05539 Rev E Page 28 of 28 Feedback
20. AND DATA COHERENCY DRIVERS P P T D i CONTROL LOGIC E M E E P R R __ 5 5 WE N E _ o 6 We m REGISTER OE READ LOGIC C24 EE CONTROL Document 38 05539 Rev E Page 2 of 28 Feedback 4 CYPRESS PERFORM Pin Configurations 100 Pinout gt lt 4 lt lt 8 96558562 gt 85685868058 096 DQPc 1 80 2 79 3 78 4 77 Vss 5 76 BYTE 6 75 7 74 8 73 DQc 9 72 Vss 10 71 11 70 12 69 13 68 Vss DNU ia CY7C1355C d Vpp 15 66 NC 16 65 Vss 17 64 DQp 18 63 DQp 19 62 k 20 61 Vss 21 60 DQp 22 59 BYTE D DQp 23 58 DQp 24 57 DQp 25 56 Vss 26 55 27 54 DQp 28 53 DQp 29 52 DQPp 30 51 lt lt lt a 2 gt 2 lt lt
21. Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1357C 133BGXC CY7C1355C 133BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1357C 133BZC CY7C1355C 133BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1357C 133BZXC CY7C1355C 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1357C 133AXI CY7C1355C 133BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1357C 133BGI CY7C41355C 133BGXI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1357C 133BGXI CY7C1355C 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1357C 133BZI CY7C18355C 133BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1357C 133BZXI 100 CY7C1355C 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1357C 100AXC CY7C1355C 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1357C 100BGC CY7C1355C 100BGXC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1357C 100BGXC CY7C1355C 100BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1357C 100BZC CY7C1355C 100BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1357C 100BZXC CY7C1355C 100AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1357C 100AXI CY7C1355C 100BGI 51 85115 119 ball Ball Grid Array 14 x 22 x
22. Internal 48 M2 DQg 13 D7 49 L1 DQp 13 D6 DQPA 49 L1 DQg 14 E7 50 K2 DQp 14 E7 50 K2 DQg 15 F6 51 Internal Internal 15 F6 51 Internal Internal 16 G7 52 H1 DQc 16 G7 52 H1 DQg 17 H6 DQg 53 G2 DQc 17 H6 53 G2 DQg 18 T7 22 54 2 DQc 18 T7 22 54 2 19 K7 55 D1 DQc 19 K7 55 D1 DQg 20 L6 56 H2 DQc 20 L6 56 Internal Internal 21 N6 57 G1 DQc 21 N6 57 Internal Internal 22 P7 58 2 DQc 22 P7 DQA 58 Internal Internal 23 N7 59 1 DQc 23 Internal Internal 59 Internal Internal 24 M6 60 D2 DQPc 24 Internal Internal 60 Internal Internal 25 L7 DQA 61 C2 A 25 Internal Internal 61 C2 A 26 K6 62 2 26 Internal Internal 62 A2 A 27 P6 DQPA 63 E4 CE 27 Internal Internal 63 E4 CE 28 4 64 2 28 6 64 B2 29 65 L3 BWp 29 A3 A 65 Internal Internal 30 C5 A 66 G3 30 5 66 BWg 31 B5 A 67 G5 BWB 31 B5 A 67 Internal Internal 32 A5 A 68 L5 32 5 68 L5 BWa 33 C6 A 69 B6 CE 33 C6 A 69 B6 34 34 35 4 0 35 4 AO 36 N4 Al 36 N4 Al Document 38 05539 Rev Page 16 of 28 Feedback f CY7C1355C CYPRESS CY7C1357C 165 ball FBGA Boundary Scan Order
23. OCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Document 38 05539 Rev E Page 22 of 28 Feedback Em CY7C1355C ES CYPRESS CY7C1357C PERFORM Switching Waveforms continued ZZ Mode Timing 271 a a ee a iZZREC gt gt 2 1 tz Y 10072 R ALL INPUTS DESELECT or READ Only except ZZ lg A DON T CARE Notes 26 Device must be deselected when entering ZZ mode See truth table for all possible signal conditions to deselect the device 27 DGs are in high Z when exiting ZZ sleep mode Document 38 05539 Rev E Page 23 of 28 Feedback 7 CYPRESS PERFORM Ordering Information CY7C1355C CY7C1357C Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 133 CY7C1355C 133AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1357C 133AXC CY7C1355C 133BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1357C 133BGC CY7C1355C 133BGXC 51 85115 119 Ball
24. TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be sh
25. a lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs and DQPy On the next clock rise the data presented to DQs and or a subset for byte write operations see Truth Table for details inputs is latched into the device and the write is complete Additional accesses Read Write Deselect can be initiated on this cycle The data written during the Write operation is controlled by BW signals The CY7C1355C CY7C1357C provides byte write capability that is described in the Truth Table Asserting the Write Enable input WE with the selected Byte Write Select input will selectively write to only the desired bytes Bytes not selected during a byte write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Byte Write capability has been included in order to greatly simplify Read Modify Write sequences which can be reduced to simple Byte Write operations Because the CY7C1355C CY7C1357C is a common device data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQs and DQPy inputs Doing so will tri state the output drivers As a safety Page 8 of 28 Feedback a rd CYPRESS PERFORM precaution DQs DQPy are automatically tri stated during the data po
26. a tri state condition The outputs are automatically tri stated during the data portion of a Write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE Bidirectional Data Parity I O Lines Functionally these signals are identical to During Synchronous Write sequences is controlled by BWy correspondingly MODE Input Strap Pin Mode Input Selects the burst order of the device When tied to Gnd selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Power supply for the circuitry Supply Vss Ground Ground for the device TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the JTAG Synchronous feature is not being utilized this pin should be left unconnected This pin is not available on TQFP packages TDI JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of If the JTAG feature Synchronous is not being utilized this pin can be left floating or connected to Vpp through a pull up resistor This pin is not available on TQFP packages Document 38 05539 Rev Page 7 of 28 Feedback ES Cypress CYPRESS PERFORM Pin Definitions continued CY7C1355C CY7C1357C
27. aptured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the bound ary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state Heserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 12 of 28 Feedback a CE CY7C1355C CYPRESS CY7C1
28. bsequent clock another operation Read Write Deselect can be initiated When the SRAM is deselected at clock rise by one of the chip enable signals its output will be tri stated immediately Document 38 05539 Rev E Burst Read Accesses The CY7C1355C CY7C1357C has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented suffi ciently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to the address bus is loaded into the address register The write signals are latched into the Control Logic block The dat
29. cle Continue Burst Next H X L X L gt H Data In D Notes 2 X Don t Care H Logic HIGH L Logic LOW BWXx L signifies at least one Byte Write Select is active BWx Valid signifies that the desired Byte Write Selects are asserted see Truth Table for details Write is defined by BWx and WE See Truth Table for Read Write CEN H inserts wait states When Write cycle is detected all I Os are tri stated even during Byte Writes The DQs and DQPy pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock Device will power up deselected and the l Os in a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle DQs and DQPy Tri state when OE is inactive or when the device is deselected and DQs and DQPy data when OE is active Document 38 05539 Rev E Page 9 of 28 Feedback CYPRESS PERFORM Truth Table 3 4 5 6 7 8 CY7C1355C CY7C1357C Address Operation Used CE ADV LD Oo N CLK DQ NOP WRITE ABORT Begin Burst None L L H Tri State WRITE ABORT Continue Burst Next L H Tri State IGNORE CLOCK EDGE Stall Current L gt H SLEEP MODE None amp l xl gl XOXDXIr
30. d 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 60 05 CY7C1355C CY7C1357C 60 25 B 0 75 0 15 119X 20 32 T 600o00 GE C a 2 2000000 10 16 OO OO OO Lor 6 F ORD gt OO SE gt em 22 00 0 20 A1 CORNER 1 00 3X REF 123456 7 _ B F G H J H 4 8 a M El L M N P R T u Ll 12 00 _ d _ 30 E 2 t x 13 I 1 i C XU UU Et SEATING PLANE d in 0 60 0 10 Document 38 05539 Rev 7 62 4 14 00 0 20 D 0 15 4X 51 85115 2 TA VA gt 127 26 28 Feedback a CY7C1355C d 2 CYPRESS CY7C1357C M PERFORM Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180
31. d 256Kx36 512Kx18 Description Revision Number 31 29 010 010 Describes the version number Device Depth 28 24 01010 01010 Reserved for Internal Use Device Width 23 18 001001 001001 Defines memory type and architecture Cypress Device ID 17 12 100110 010110 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 5 unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Note 12 All voltages referenced to Vss GND Document 38 05539 Rev E Page 14 of 28 gpa CY7C1355C CYPRESS CY7C1357C PERFORM Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 69 69 Boundary Scan Order 165 ball FBGA package 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures ring contents Places the boundary scan register between TDI TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This i
32. e CLK Rise 1 5 1 5 ns Chip Enable Set Up before CLK Rise 1 5 1 5 ns Hold Times Address Hold after CLK Rise 0 5 0 5 ns taLH ADV LD Hold after CLK Rise 0 5 0 5 ns twEH WE BW Hold after CLK Rise 0 5 0 5 ns tcENH CEN Hold after CLK Rise 0 5 0 5 ns toy Data Input Hold after CLK Rise 0 5 0 5 ns Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes 16 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 17 Test conditions shown in a of AC Test Loads unless otherwise noted 18 This part has a voltage regulator internally tpgwer is the time that the power needs to be supplied above Vpp minimum initially before a Read or Write operation can be initiated 19 tci z togrz and are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 20 At any given voltage and temperature is less than tog z and toy is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 21 This parameter is sampled and not 100 tested Document 38 05539 Rev E Page 20 of 28 Feedback CY7C1355C CY7Ci857C PERFORM Switching Wavef
33. emiconductor Corporation 198 Champion Court Jose 95134 1709 e 408 943 2600 Document 38 05539 Rev E Revised September 14 2006 Feedback CY7C1355C 7 CYPRESS CY7C1357C T FOR M Logic Block Diagram CY7C1355C 256K x 36 A1 ADDRESS REGISTER MODE C ADV D CEN a WRITE ADDRESS REGISTER o U D P E ADV LD N A ba WRITE REGISTRY WRITE ae EL s p i DOs BWs AND DATA COHERENCY DRIVERS gt L F B CONTROL LOGIC E DOPs edi R DQPc 5 5 DQPp WE N E F 5 77 gt lt REGISTER t READ LOGIC x CE3 SLEEP 2 CONTROL Logic Block Diagram CY7C1357C 512K x 18 AL A ADDRESS REGISTER MODE CLK C c CEN WRITE ADDRESS REGISTER 5 _ if ADV LD e A BWa WRITE e E eis WRITE REGISTRY ARRAY 5 005 BWe
34. erted LOW the address presented to the device will be latched The access can either be a Read or Write operation depending on the status of the Write Enable WE BWy can be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Enables CE4 CE3 and asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and CE are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the address register and presented to the memory array and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers The data is available within 7 5 ns 133 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data On the su
35. ification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1355C CY7C1357C contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS internally pulled up and may be unconnected They may alter nately be connected to Vpp through a pull up resistor should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TESTLOGIC RESET 0 C RUN TEST 1 SELECT 1 SELECT 1 IDLE i DRSCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 3 T SHIFT DR D SHIFTIR 707 9 1 1 1 1 EXITLDR Le EXITHR 0 0 Y Y PAUSEDR 707 PAUSE IR D 9 1 1 0 0 EXIT2 DR EXIT2IR 1 1 Y i d UPDATEDR UPDATER 0 1 0 Y
36. ifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state Document 38 05539 Rev E CY7C1355C CY7C1357C SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP cont
37. mmercial 0 C to 70 C 3 3 5 10 2 5V 5 in 0 5V to 0 5V Industrial 40 C to 85 to Vpp Electrical Characteristics Over the Operating Rangel 141 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage for 3 3V 3 135 V for25VVO 23 2625 Output HIGH Voltage for 3 3V 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage 3 3V I O loj 8 0 mA 0 4 V for 2 5V I O 1 0 mA 0 4 V Vin Input HIGH for 3 3V 20 Vpp 03V V for2 5VVO 37 Vpp 03V V ViL Input LOW Voltagel 3 3V 0 3 0 8 V for 2 5V I O 0 3 0 7 V Ix Input Leakage Current GND lt lt Vppq 5 5 except ZZ and MODE Input Current of MODE Vss 30 Input Vpp 5 Input Current of ZZ Input Vas 5 Input Vpp 30 loz Output Leakage Current GND x V x Output Disabled 5 5 Ipp Operating Supply Vpp Max lour 0 mA 7 5 ns cycle 133 MHz 250 mA Current f fmax 1 10 ns cycle 100 MHz 180 mA Automatic CE Vpp Max Device Deselected All speeds 110 mA Power down Vin 2 Vin Or Vin Vit Current TTL Inputs f fmax inputs switching Ispo Automatic CE Vpp Max Device Deselected All speeds 40 mA Power down Vin lt 0 3V or gt 0 3V Current CMOS Inputs f 0 inputs static A
38. nsion pins balls in the pinouts for all packages are modified as per JEDEC standard Modified test conditions Corrected lsg4 Test Condition from Vij 2 Vpp 0 3V or lt 0 3V to Vin or Vy lt Vi in the Electrical Characteristic Table on Pg 18 Changed Oj and for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed and for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed and for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Added lead free information for 100 pin TQFP 119 BGA and 165 FBGA Packages Updated Ordering Information Table Changed from Preliminary to Final B 351895 See ECN Changed 5 from 30 to 40 mA Updated Ordering Information Table 377095 Modified test condition note 14 from lt Vpp to lt D 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page 1 from 8901 North First Street to 198 Champion Court Modified Input Load to Input Leakage Current except ZZ and in the Electrical Characteristics Table Changed three state to tri state Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table E 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Changed try trj from 25 ns to 20 ns and from
39. nstruction is reserved for future use SAMPLE PRELOAD 100 Captures ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Document 38 05539 Rev E Page 15 of 28 Feedback 119 ball BGA Boundary Scan Order CY7C1355C CY7C1357C CY7C1355C 256K x 36 CY7C1357C 512K x 18 Signal Signal Signal Signal Bit ball ID Name Bit ball ID Name Bit ball Id Name Bit ball Id Name 1 K4 CLK 37 R6 A 1 K4 CLK 37 R6 A 2 H4 WE 38 T5 A 2 H4 WE 38 T5 A 3 M4 CEN 39 T3 A 3 M4 CEN 39 T3 A 4 F4 OE 40 R2 A 4 F4 OE 40 R2 A 5 B4 ADV LD 41 MODE 5 B4 ADV LD 41 MODE 6 G4 A 42 P2 DQPp 6 G4 A 42 Internal Internal 7 C3 A 43 1 DQp 7 C3 A 43 Internal Internal 8 B3 A 44 L2 DQp 8 B3 A 44 Internal Internal 9 D6 DQPg 45 K1 DQp 9 T2 A 45 Internal Internal 10 H7 DQg 46 N2 DQp 10 Internal Internal 46 P2 11 G6 47 1 DQp 11 Internal Internal 47 N1 12 DQg 48 M2 DQp 12 Internal
40. orms Read Write 22 23 24 1 2 tyc 3 4 5 6 7 8 9 10 tcens CA WN ll A HA MA VA MA M BWx A WA A I M DQ OE COM MAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 Q A4H DONT UNDEFINED 22 For this waveform ZZ is tied LOW u u u u 23 When CE is LOW CE is LOW CE is HIGH and CE is LOW When is HIGH CE is HIGH or is LOW or is HIGH 24 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05539 Rev E Page 21 of 28 Feedback CY7C1355C SSF CYPRESS ORM OO Switching Waveforms continued NOP STALL and DESELECT 22 23 251 1 2 3 4 5 6 7 8 9 10 4 tcens 45 lt gt lt gt lt gt GA 7 A HA V A WA Ih BWx A UA M ADDRESS DQ OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A2 1 Q A4 1 DONT i UNDEFINED Note 25 The IGNORE CL
41. roller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the in struction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is cap tured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possi ble that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcu The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK c
42. rtion of a write cycle regardless of the state of OE Burst Write Accesses CY7C1355C CY7C1357C Interleaved Burst Address Table MODE Floating or VDD First Second Third Fourth Address Address Address Address The CY7C1355C CY7C1357C has an on chip burst counter A1 AO 1 0 1 0 1 that allows the user the ability to supply single address and 00 01 10 11 conduct up to four Write operations without reasserting the address inputs ADV LD must be driven LOW in order to load 01 00 11 10 the initial address as described the Single Write Access 10 11 00 01 section above When ADV LD is driven HIGH on the subse quent clock rise the Chip Enables CE4 and CE3 and 11 10 01 00 WE inputs are ignored and the burst counter is incremented The correct BWy inputs must be driven in each cycle of the Linear Burst Address Table MODE GND burst write in order to write the correct bytes of data First Sacond Third Fourth Address Address Address Address Sleep Mode 1 0 1 0 1 0 1 0 ZZ input is an asynchronous input Asserting ZZ 00 01 10 1 places the SRAM power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep 01 10 11 00 mode While in this mode data integrity is guaranteed
43. t notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C1355C CYPRESS 7 PERFORM 4 Document History Page Document Title CY7C1355C CY7C1357C 9 Mbit 256K x 36 512K x 18 Flow Through SRAM with NoBL Architecture Document Number 38 05539 Orig of REV NO Issue Date Change Description of Change d 242032 See ECN RKF New data sheet A 332059 See ECN PCI Changed Boundary Scan Order to match the B rev of these devices Removed description on Extest Output Bus Tri state Removed 117 MHz Speed Bin Changed from 35 mA to 50 mA on Pg 9 Changed and from 40 mA to 110 and 100 mA respectively Address expa
44. tage 1 5V 3 3V TAP AC Output Load Equivalent 1 5V 50Q TDO 20 500 20pF CY7C1355C CY7C1357C 2 5V TAP AC Test Conditions Input pulse levels sse Vss to 2 5V Input rise and fall time 1ns Input timing reference 1 25V Output reference levels 1 25V Test load termination supply voltage 1 25V 2 5V TAP AC Output Load Equivalent 1 25V 500 TDO 20 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt T4 lt 70 C Vpp 3 3V 0 165V unless otherwise 12 Parameter Description Conditions Min Max Unit Vout Output HIGH Voltage 4 0 mA 3 3V 2 4 1 0 mA Vppo 2 5V 20 V Output HIGH Voltage 100 pA Vppo 3 3 2 9 V Vppq 2 5V 2 1 V Vout Output LOW Voltage 8 0 mA Vppo 3 3V 0 4 V loL 8 0 mA Vppo 2 5V 0 4 V Voi2 Output LOW Voltage 10 100 pA Vppo 3 3V 0 2 V Vppo 2 5V 0 2 V Input HIGH Voltage Vppq 3 3V 2 0 Vpp 0 3 V Vppo 2 5V 1 7 Vpp 0 3 V Input LOW Voltage Vppo 3 3V 0 5 0 7 V 2 5V 0 3 0 7 V Ix Input Load Current GND lt lt Vppa 5 5 Identification Register Definitions CY7C1355C CY7C1357C Instruction Fiel
45. utomatic Vpp Max Device Deselected speeds 100 mA Power down Vin lt 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f fmax inputs switching 4 Automatic CE Vpp Max Device Deselected All Speeds 40 mA Power down Vin 2 Vin or Vin lt Vic f 0 inputs Current TTL Inputs static Notes 13 Overshoot lt 1 5V Pulse width less than 2 undershoot AC gt 2 Pulse width less than 2 14 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt and Vppo lt Document 38 05539 Rev E Page 18 of 28 Feedback 7 1355 CYPRESS 7 5 Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit Cin Input Capacitance TA 25 f 1 MHz 5 5 5 pF Clock Input Capacitance M DD AT 5 5 5 pF Input Output Capacitance 5 7 7 pF Thermal Resistance 100 TQFP 119BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Thermal Resistance Test conditions follow standard 29 41 34 1 16 8 C W Junction to Ambient test methods and procedures for measuring thermal o Thermal Resistance 6 31 14 0 3 0 C W Junction to Case impedance per EIA JESD51 AC Test Loads and Waveforms
46. yo Description Ag A4 Input Address Inputs used to select one of the address locations Sampled at the rising edge Synchronous of the CLK are fed to the two bit burst counter BWA BWg Input Byte Write Inputs active LOW Qualified with WE to conduct Writes to the SRAM Sampled BWc BWp Synchronous the rising edge of CLK WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW Synchronous This signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW anew address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with Clock CEN CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with and CEs to select deselect the device Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE3 to select deselect the device Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with and to
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