Cypress MoBL CY62157EV30 User's Manual
Contents
1. 65 to 150 C Method atte Ambient Temperature with Latch up Current reru ets gt 200 mA Power Applied 55 C to 125 C Operating Range Supply Voltage to Ground Ambient Potential ess 0 3V to 3 9V Vecmax 03 DC Voltage Applied to Outputs High Z State 16 7 0 3V to 3 9V 0 3V CY62157EV30LLInd Auto A 3 60V Electrical Characteristics Over the Operating Range 45 ns Ind l Auto A Parameter Description Test Conditions Unit Min Typ 2 Max VoH Output HIGH Voltage 0 1 mA 2 0 V lop 1 0 mA Vcc gt 2 70V 24 V VoL Output LOW Voltage loy 0 1 mA 0 4 V lo 2 1mA Vcc gt 2 70V 0 4 V Input HIGH Voltage Vec 22V to 2 7V 1 8 0 3 V Vec 2 7V to 3 6V 2 2 0 3 V Vit Input LOW Voltage Vec 2 2V to 2 7V 0 3 0 6 V Vec 2 7V to 3 6V 0 3 0 8 V lix Input Leakage Current GND lt Vj lt Vee 1 1 loz Output Leakage Current GND lt Vo lt Output Disabled 1 1 lec Vcc Operating Supply Current f fmax 1 tgc Vec Vecmax 18 25 f 1 MHz lout 0 mA 1 8 3 mA CMOS levels leg Automatic CE Power Down gt Vcc 0 2V CE lt 0 2V 2 8 uA Current CMOS Inputs Vin gt Vec 0 2V Vin lt 0 2V f fmax A2. _ gt Se HERRERA SSE ecr T _ CY62157EV30 MoBL YPRESS PERFOR Features TSOP I package configurable as 512K x 16 or as 1M x 8 SRAM High speed 45 ns Wide voltage range 2 20V 3 60V Pin compatible with CY62157DV30 Ultra low standby power Typical Standby current 2 Maximum Standby current 8 uA Industrial Ultra low active power Typical active current 1 8 mA f 1 MHz Easy memory expansion with CE4 OE features Automatic power down when deselected CMOS for optimum speed and power Available in both Pb free and non Pb free 48 ball VFBGA Pb free 44 TSOP II and 48 pin TSOP packages Functional Description The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly Logic Block Diagram 8 Mbit 512K x 16 Static RAM reduces power consumption when addresses are not toggling Place the device into standby mode when deselected CE HIGH or CE2 LOW or both and BLE are HIGH The input or output pins lOg through 1045 are placed a high impedance state when D
3. 120 25 0121 24 22 23 A43 1 2 3 4 5 6 7 8 9 48 Pin TSOP I 512K x 16 1M x 8 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Vcc Vcc yp Ta 25 NC pins are not connected on the die 3 4 The 44 TSOP package has only one chip enable CE pin 5 The BYTE pin in the 48 TSOP package has to be tied HIGH to use the device as a 512K x 16 SRAM The 48 TSOP package can also be used as a 1M x 8 SRAM by tying the BYTE signal LOW In the 1M x 8 configuration Pin 45 is A19 while BHE Document 38 05445 Rev E LE and 108 to 1014 pins are not used DNU Page 2 of 14 Feedback PERFORM Pin Configuration continued The following picture shows the 48 ball VFBGA pinout 4 5 Document 38 05445 Rev 48 VFBGA 1 2 3 4 5 6 OBO CO DD OOO QOS DOG ao OOo gt CY62157EV30 MoBL Page 3 of 14 Feedback us 2 CYPRESS CY62157EV30 MoBL 1 PERFORM Maximum Ratings DC Input Voltage 71 0 3V to 3 9V Voc max 0 3V Exceeding maximum ratings may shorten the battery life of the Output Current into Outputs LOW 20 mA device User guidelines are not tested Static Discharge Voltage gt 2001 Storage Temperature
4. COLUMN DECODER 4 4 p s ONO eee 26 lt lt lt lt lt lt lt lt CE p CE a b ae 1 For best practice recommendations please refer to the Cypress application note AN1064 SRAM System Guidelines Cypress Semiconductor Corporation Document 38 05445 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised 07 2007 Product Portfolio CY62157EV30 MoBL Power Dissipation Speed 2 Vcc Range V Operating Icc mA Product Range id ns xd Standby 15 2 f 1MHz f fmax 21 Max 21 21 Max 21 Max CY62157EV30LL 1 2 2V 3 0 3 6 45 1 8 3 18 25 2 8 Pin Configuration The following pictures show the 44 pin TSOP and 48 pin TSOP pinouts 5 Notes 44 Pin TSOP Il Top View pa 44 D As 2 43 O L3 42 7 4 41 OE 5 40 6 39 O BLE 07 O 1045 8 37 0 1044 9 36 O 1043 110 35 1042 11 34 O Vss 12 1 Vec 13 32 O IO 14 31 1049 15 30 O lOg 16 29 17 28 O Ag 18 27 O Ag 19 26 O
5. Document 38 05445 Rev E Page 7 of 14 Feedback 2 CYG2I57EV30 MoBL PERFORM Switching Waveforms continued Write Cycle No 1 WE Controlled 8 22 23 Figure 5 Write Cycle No 1 aes taw tHa tsa tpwe RASS FEE SX 2 DATAIO NOTE 24 IX VALID DATA s tuzoE Write Cycle No 2 CE or Controlled 22 23 Figure 6 Write Cycle No 1 x yZ tsa t AW j omo tuzoE O Not 22 Data IO is s high impedance if OE 23 If CE goe s HIGH a nd CE aneous ly with WE the output remains in a high impedance state 24 Duri ring this period the 10 output state Do not apply input 5 signe als Document 38 05445 Rev E Page 8 of 14 Feedback y 6 CYPRESS CY62157EV30 MoBL PERFORM Switching Waveforms continued Write Cycle No 3 WE Controlled OE LOW Figure 7 Write Cycle No 3 E 2222 RII m tsa ENS A tuzwe awe Write Cycle No 4 BHE BLE Controlled LOW P l Figure 8 Write Cycle No 4 twe mores OK tsce taw tran BERE is tsa lt tpwE gt tsp
6. Pitch Ball Grid Array Pb free Automotive A CY62157EV30LL 45ZSXA 51 85087 44 pin Thin Small Outline Package Type II Pb free Contact your local Cypress sales representative for availability of these parts Document 38 05445 Rev E Page 10 of 14 Feedback PERFORM Package Diagrams TOP VIEW 1 CORNER 1234 5 CY62157EV30 MoBL Figure 9 48 VFBGA 6 x 8 x 1 51 85150 rm 0 10 A B 2 D e 8 G H B 6 005010 19 2 8 S e X 3 1 i C CZ CZ T SEATING PLANE lt 3 5 8 Document 38 05445 Rev E BOTTOM VIEW 1 CORNER p 0 05 ME 20 25 MEAB 0 30 0 05 48 6543 2 Fi X i L soeobodo B 4 OO DIO O5 a 18 D 8 5 OOO OOO e 8 G 0oo0ooo H A 1 875 0 75 3 75 B m 6004040 A 0 15 4 51 85150 D Page 11 of 14 Feedback 2 CYPRESS PERFORM 1 Package Diagrams continued TOP VIEW 400 lt 0 2 030000185 18 517 _ 0 729 gt 18313 0 7213 1194 0 047 Document 38 05445 Rev CY62157EV30 MoBL F
7. uL E 2 79 49 QOO Document 38 05445 Rev E Page 9 of 14 Feedback l 7 254 us CYPRESS PERFORM Truth Table CY62157EV30 MoBL CE CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X X MHigh Z Deselect Power Down Standby lag X L X X X X MHigh Z Deselect Power Down Standby lag X X X X H H High Z Deselect Power Down Standby lag L H H L L L Data Out lOg IO45 Read Active Icc L H H L H Out 105 105 Read Active lec High Z IOg 1O45 L H H L L High Z 00 07 Read Active lec Data Out lOg 1O45 L H H H L H High Z Output Disabled Active lec L H H H H L High Z Output Disabled Active L H H H L L High Z Output Disabled Active L H L X L L Data In 105 105 Write Active loc L H L X H L In 105 107 Write Active lec High Z IOg 1O45 L H L X L H High Z IOg 1O Write Active lec Data In lOg 1O45 Ordering Information ees Ordering Code Dam Package Type Rages 45 CY62157EV30LL 45BVI 51 85150 48 ball Very Fine Pitch Ball Grid Array Industrial CY62157EV30LL 45BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free CY62157EV30LL 45ZSXI 51 85087 44 pin Thin Small Outline Package Type II Pb free CY62157EV30LL 45ZXI 51 85183 48 pin Thin Small Outline Package Type Pb free 45 CY62157EV30LL 45BVXA 51 85150 48 ball Very Fine
8. AC Test Loads and Waveforms R1 ALL INPUT PULSES Vec Voc 9096 OUTPUT 1096 GND 30 pF R2 Rise Time 1 V ns Fall Time 7 1 V ns INCLUDING JIGAND 7 Equivalent to EQUIVALENT SCOPE R TH OUTPUT o w VH Parameters 2 5V 3 0V Unit R1 16667 1103 Q R2 15385 1554 Q RTH 8000 645 Q VTH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 21 Unit VDR Vcc for Data Retention 1 5 V 21 Data Retention Current 1 5V gt Vee 0 2 Ind l Auto A 2 5 pA CE lt 0 2V Vin Vcc 0 2V or Vin lt 0 2V 0 Chip Deselect to Data 0 ns Retention Time tg M Operation Recovery Time ns Data Retention Waveform Figure 2 Data Retention Waveform DATA RETENTION MODE Vpr gt 1 5V u gt tR CE or BHE BLE or CE Notes 11 Full device operation requires linear Vcc ramp from Vpg to gt 100 or stable at Vec min gt 100 us 12 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE Document 38 05445 Rev E Page 5 of 14 Feedback CY62157EV30 MoBL Switching Characteristics Over the Operating Rangel 141 45 ns Ind l Auto A Parameter Description Unit Min Max Read C
9. arification 15 At any temperature and voltage condition gt is less than tj tyzpe is less than tj is less than tj zog and tyzwe_ is less than tj zwe for any device 16 tuzog and tyzwe transitions are measured when the outputs enter a high impedance state 17 If both byte enables are toggled together this value is 10 ns EPIS 2585 18 The internal write time of the memory is defined by the overlap of WE CE BLE or both Vj and All signals must be active to initiate write and any of mese signals can terminate a write by going inactive The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 38 05445 Rev E Page 6 of 14 Feedback ______ CY62457EV30 Switching Waveforms Read Cycle No 1 Address Transition Controlled Figure 3 Read Cycle No 1 y e 20 ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE 20 211 Figure 4 Read Cycle No 2 ADDRESS CE BHE BLE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT Voc SUPPLY CURRENT Notes 19 The device is continuously selected OE CE BLE or both Vi 20 WE is HIGH for read cycle __ 21 Address valid before or similar to CE4 BLE transition LOW and CE transition HIGH
10. ce Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Document History Page CY62157EV30 MoBL Document Title CY62157EV30 MoBL 8 Mbit 512K x 16 Static RAM Document Number 38 05445 REV ECN NO Issue Date Orig of Change Description of Change kk 202940 See ECN AJU New Data Sheet A 291272 See ECN SYT Converted from Advance Information to Preliminary Removed 48 TSOP Package and the associated footnote _ Added footnote stating 44 TSOP Package has only one CE on Page 2 Changed Vcc stabilization time in footnote 7 from 100 us to 200 us Changed lccpg from 4 to 4 5 uA Changed topa from 6 to 10 ns for both 35 and 45 ns Speed Bi
11. ddress and Data Only f 0 OE BLE and WE Vcc 3 60V Isp2 9 Automatic CE Power Down CE gt Vec 0 2V or lt 0 2V 2 8 Current CMOS Inputs gt 0 2V or Viy lt 0 2V f 0 3 60V Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance 25 C f 1 MHz 10 pF Cour Output Capacitance Voc 10 Notes 6 Vi min 2 0V for pulse durations less than 20 ns 7 Vin max 0 75V for pulse durations less than 20 ns 8 Full device AC operation assumes a 100 us ramp time from 0 to 200 us wait time after stabilization 9 Only chip enables CE and CE3 byte enables and BLE and BYTE 48 TSOP only need to be tied to CMOS levels to meet the 5 2 1 spec Other inputs can be left floating 10 Tested initially and after any design or process changes that may affect these parameters Document 38 05445 Rev E Page 4 of 14 Feedback CY62157EV30 MoBL Thermal Resistance 10 Parameter Description Test Conditions BGA TSOP TSOP Il Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 72 74 88 76 88 C W Junction to Ambient two layer printed circuit board Thermal Resistance 8 86 8 6 13 52 C W Junction to Case AC Test Loads and Waveforms Figure 1
12. eselected CE4HIGH or CE LOW Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH Write operation is active CE LOW CE HIGH and WE LOW To write to the device take Chip Enable CE4 LOW and CE HIGH and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from IO pins IOg through 107 is written into the location specified on the address pins through A4g If Byte High Enable BHE is LOW then data from pins lOg through 1045 is written into the location specified on the address pins Ag through A48 To read from the device take Chip Enable CE LOW and CE3 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on to 107 If Byte High Enable is LOW then data from memory appears on to 1045 See the Truth Table on page 10 for a complete description of read and write modes peres CE Gum BHE BLE Power Down Circuit Notes DATA IN DRIVERS lt 9 Z e 7 O gt 6 9 512K x 16 1Mx8 lt 5 RAM Array l a L lt gt Og 107 4 gt 2 oH lt gt 031045 X E
13. from 6 to 5 Changed tpwe_ from 30 to 35 Changed tgp from 22 to 25 Changed t from 6 to 10 Added footnote 15 Updated the ordering Information and replaced the Package Name column with Package Diagram D 467052 925501 See ECN See ECN NXR VKN Modified Data sheet to include x8 configurability Updated the Ordering Information table Removed Automotive E information Added Preliminary Automotive A information Added footnote 10 related to lag and Iccpr Added footnote 15 related AC timing parameters E 1045801 See ECN VKN Converted Automotive A specs from preliminary to final Updated footnote 9 Document 38 05445 Rev E Page 14 of 14 Feedback
14. igure 10 44 Pin TSOP Il 51 85087 DIMENSION IN MM INCH MAX MIN 10 262 0 404 EJECTDR PIN BOTTOM VIEW 10 262 0 4045 10 058 0 3965 BASE PLANE 0 5 0 210 00083 0120 0 0047 30 10 lt 0042 0 597 0 0235 0 406 0 01605 SEATING BEANE 51 85087 A 0 150 0 0059 gt Page 12 of 14 Feedback M CES CiPRESS CYGZIS7EV30 MOBL PERFORM Package Diagrams continued Figure 11 48 Pin TSOP I 12 mm x 18 4 mm x 1 0 mm 51 85183 DIMENSIONS IN INCHES MM MIN MAX JEDEC MO 142 0 037 0 95 0 041 1 05 i 071 4 0 020 0 50 ES JEL Y LS r3 0 472 12 00 0 007 0 17 oo 0 011 0 27 Ira mo H lt B 0 002 0 05 0 724 18 40 0 006 0 15 0 047 1 20 0 787 20 00 SEATING PLANE le 0004010 0 004 0 10 001010225 010081021 S GAUGE PLANE 2 0 020 0 50 51 85183 0 5 0 028 0 70 is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05445 Rev E Page 13 of 14 Cypress Semiconductor Corporation 2004 2007 The information contained herein is subject to change without noti
15. ns Changed tpog from 15 to 18 ns for 35 ns Speed Bin Changed and tyzwe from 12 and 15 ns to 15 and 18 ns for 35 and 45 ns Speed Bins respectively Changed from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Changed taw and tgw from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed Bins respectively Changed tap from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively Added Lead Free Package Information 444306 See ECN NXR Converted from Preliminary to Final Changed ball E3 from DNU to NC Removed redundant footnote on DNU Removed 35 ns speed bin Removed L bin Added 48 pin TSOP package Added Automotive product information Changed the Icc Typ value from 16 mA to 18 mA and Max value from 28 mA to 25 mA for test condition f fax 1 tgc Changed the Max value from 2 3 mA to 3 mA for test condition 1MHz Changed the 5 and 5 Max value from 4 5 uA to 8 pA and Typ value from 0 9 uA to 2 uA respectively LL Modified ISB test condition to include BHE BLE Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF Added Typ value for lccpg Changed the Max value from 4 5 pA to 5 pA Corrected in Data Retention Characteristics from 100 us to tre ns Changed t zog from to 5 Changed t gt from 6 to 10 Changed from 22 to 18 Changed t
16. ycle tre Read Cycle Time 45 ns taa Address to Data Valid 45 ns toHa Data Hold from Address Change 10 ns CE LOW and HIGH to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to LOW Z l 5 ns fusci OE HIGH to 2115 16 18 ns lizcE CE LOW and HIGH to 1 21151 10 ns 2 CE HIGH and CE LOW to 2115 161 18 ns tpu LOW and HIGH to Power Up 0 ns tpp CE HIGH and CE LOW to Power Down 45 ns BLE BHE LOW to Data Valid 45 ns tizpE BLE BHE LOW to 2115 17 5 ns tuzBE BLE BHE HIGH to HIGH ZI15 16 18 ns Write Cyclel8 twc Write Cycle Time 45 ns tecE CE LOW and HIGH to Write End 35 ns taw Address Setup to Write End 35 ns tua Address Hold from Write End ns tsa Address Setup to Write Start ns tpwe WE Pulse Width 35 ns tew BLE BHE LOW to Write End 35 ns tsp Data Setup to Write End 25 ns tup Data Hold from Write End 0 ns tuzwe WE LOW to 2115 16 18 ns lizwe WE HIGH to Low Z 5l 10 ns Notes 13 Test conditions for all parameters other than tri state parameters assume signal transition time of ns or less timing reference levels of 2 input pulse levels of 0 to and output loading of the specified as shown in the AC Test Loads and Waveforms on page 5 14 AC timing parameters are subject to byte enable signals or BLE not switching when chip is disabled See application note AN 138402 for further cl
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