Cypress MoBL CY62138F User's Manual
Contents
1. tpog Kc NENNEN NND HIGH IMPEDANCE tLZ0E HIGH IMPEDANCE DATA OUT Vcc SUPPLY CURRENT Isp Write Cycle No 1 WE controlled 1 14 18 19 twc lt tscE i E IOs A taw tha gt tsa tpwe E R RANNU E LLK lup DATA IO lt NorE20 X KX DATA VALID tuzoE Notes _ 15 The device is continuously selected OE CE Vu CE Vj 16 WE is HIGH for read cycle 17 Address valid before or similar to CE transition LOW and CE transition HIGH 18 Data IO is high impedance if OE Vj 19 If CE goes HIGH or CE goes LOW simultaneously with WE HIGH the output remains in high impedance state 20 During this period the IOs are in output state Do not apply input signals Document 001 13194 Rev A Page 6 of 10 Feedback CYPRESS PERFORM Switching Waveforms continued Write Cycle No 2 CE1 or CE2 controlled 110 14 18 19 CY62138F MoBL Write Cycle No 3 WE controlled OE LOW 10 19 twc ADDRESS N NN Z FE INI LLL taw tHa tsa tpwe WE N NN SS HD 7 a i OED OK ie 90 tHZWE tLZwe Truth Table CE WE OE Inputs Outputs Mode Power H X X High Z Deselect Power Down Standby lag L H L Data Out Read Active lcc L L X Data In Write Active loc L H H High Z Selected Outputs Disabled Active lcc Ordering Information Speed Package Operating ns Ordering Code2. s CYPRESS CY62138F MoBL PERFORM Z 1 LC W 2 Mbit 256K x 8 Static RAM Features Functional Description l High speed 45 ns The CY62138F is a high performance CMOS static RAM Wide voltage range 4 5 V 5 5 V organized as 256K words by 8 bits This device features f i advanced circuit design to provide ultra low active current Pin compatible with CY62138V This is ideal for providing More Battery Life MoBL in Ultra low standby power portable applications such as cellular telephones The device Typical standby current 1 pA also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Maximum standby current 5 pA Placing the device into standby mode reduces power Ultra low active power consumption by more than 99 when deselected CE HIGH Typical active current 1 6 mA f 1 MHz or CE2 LOW Easy memory expansion with CE4 CE and OE features To write to the device take Chip Enable CE LOW and CE i HIGH and Write Enable WE inputs LOW Data on the eight Automatic power down when deselected IO pins IOo through 107 is then written into the location CMOS for optimum speed and power specified on the address pins Ag through A47 Available in Pb free 32 pin SOIC and 32 pin TSOP II To read from the device take Chip Enable CE LOW and CE packages HIGH and output enable OE LOW while forcing Write Enable WE
3. taw Address Setup to Write End 35 ns tha Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 35 ns tsp Data Setup to Write end 25 ns tup Data Hold from Write End 0 ns tuzwe WE LOW to High Z 12 131 18 ns tizwE WE HIGH to Low Z 12 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of Vcc typy2 input pulse levels of 0 to Vecityp and output loading of the specified lo Ioy as shown in the AC Test Loads and Waveforms on page 4 12 At any given temperature and voltage condition tuzcg is less than tj zcg tuzoe is less than tj zog and tyzwe is less than tj zwe for any given device 13 tuzog tyzce and tyzwe transitions are measured when the outputs enter a high impedance state 14 The internal write time of the memory is defined by the overlap of WE CE Vj and CE Vj All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 001 13194 Rev A Page 5 of 10 Feedback A PERFORM iil Was C Switching Waveforms Read Cycle 1 Address transition controlled 15 16 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE controlled 110 16 17 ADDRESS CE
4. Vec 0 2V or Vin lt 0 2V f 0 Vec Vec max Capacitance For all packages 8 Parameter Description Test Conditions Max Unit CiN Input capacitance Ta 25 C f 1 MHz 10 pF Cout Output capacitance Vcc Vecityp 10 pF Thermal Resistance E Parameter Description Test Conditions SOIC TSOP Il Unit OJA Thermal Resistance Still air soldered on a 3 x 4 5 inch 44 53 44 16 C W Junction to Ambient two layer printed circuit board Ojc Thermal Resistance 24 05 11 97 C W Junction to Case Notes Vit min 2 0V for pulse durations less than 20 ns ViH max Vec 0 75V for pulse durations less than 20ns Only chip enables CE and CE must be at CMOS level to meet the Isgo Iccpr spec Other inputs can be left floating 4 5 6 Full device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after Vcc stabilization T 8 Tested initially and after any design or process changes that may affect these parameters Document 001 13194 Rev A Page 3 of 10 CY62138F MoBL PERFORM AC Test Loads and Waveforms R1 Vcc ALL INPUT PULSES OUTPUT 3 0V 90 10 30 pF R2 GND 2 T Rise Time 1 V ns Fall Time 1 V ns INCLUDING 7 JIG AND SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o w o V Parameters 5 0V Unit R1 1800 Q R2 990 Q RTH 639 Q VTH 1 77 V Data Retention Characteristics Over the Operating Range
5. Diagram Package Type Range 45 CY62138FLL 45SXI 51 85081 32 pin Small Outline Integrated Circuit Pb free Industrial CY62138FLL 45ZSXI 51 85095 32 pin Thin Small Outline Package II Pb free Contact your local Cypress sales representative for availability of these parts Page 7 of 10 Document 001 13194 Rev A Feedback CY62138F MoBL cypress Package Diagrams Figure 1 32 pin 450 Mil Molded SOIC 51 85081 O 0 546 13 868 0 566 14 376 0 440 11 176 0 450 11 430 Y CHER HEHEHE aed 7 32 0 793 20 142 0 817 20 751 0 006 0 152 0 012 0 304 l N 0 101 2 565 0 118 2 997 0 111 2 819 MAX ror hi p BA LF HL HH HHH JH JH HH HH et Jj IU 4 4 V A 0 004 0 1021 ml E f eS 0 047 1 193 0 004 0 102 f 0 063 1 600 ars 2 MIN 0 023 0 584 i 0 014 0 355 0 039 0 990 00200508 71 MT SEATING PLANE J 51 85081 B Document 001 13194 Rev A Page 8 of 10 Feedback CY62138F MoBL Package Diagrams continued Figure 2 32 Pin TSOP Il 51 85095 EE ILILILILILILILILII SEE DETAIL A DIMENSIONS IN MILLIMETERS MIN MAX 15 5 TOP VIEW 07 MIN R 0 12 MIN R 0 12 0 25 1 27 BSC Q 5 0 40 0 60 DETAIL A 51 85095 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semicondu
6. FORM e Maximum Ratings Exceeding maximum ratings may impair the useful life of the CY62138F MoBL device These user guidelines are not tested m ao Mn aie rU gt 2001V Storage Temperature muc ne ceee ceace 65 C to 150 C 3 A pe deut Ambient Temperature with atch up Current mc eee nana nana gt 200 m Power Applied ccenn 55 C to 125 C i dM Operating Range Supply Voltage to Ground Potential eee 0 5V to 6 0V VcCmax 0 5V Device Range Ter Vec 6 DC Voltage Applied to Outputs in High Z state 4 5 0 5V to 6 0V Vccmax 0 5V CY62138FLL Industrial 40 C to 85 C 4 5V to 5 5V Electrical Characteristics Over the Operating Range 45 ns Parameter Description Test Conditions Unit Min Typ 3 Max VoH Output HIGH Voltage lop 1 0 mA 2 4 V VoL Output LOW Voltage lo 2 1 mA 0 4 V Vin Input HIGH Voltage Vec 4 5V to 5 5V 2 2 Vcc 0 5 V Vi Input LOW Voltage Voc 4 5V to 5 5V 0 5 0 8 V lix Input Leakage Current GND lt V x Voc 1 1 uA loz Output Leakage Current GND lt Vo x Vcc Output Disabled 1 1 LA loc Vee Operating Supply f fmax 1 tRe Vec Vcc max 13 18 mA Current 7 lout Om f 1 MHz CMOS levels 1 6 2 5 Isa I Automatic CE Power Down CE gt Vec 0 2V or CE lt 0 2V 1 5 pA Current CMOS inputs Vin gt
7. HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins The eight input and output pins IOg through 107 are placed in a high impedance state when the device is deselected CE HIGH or CE LOW the outputs are disabled OE HIGH or during a write operation CE LOW and CE HIGH and WE LOW Logic Block Diagram o Ao 0 Ay o A2 1 A3 m O5 oO z E O3 ul 2 IO Z 4 a O5 Og CE CE2 07 So 5 ss Note 1 For best practice recommendations refer to the Cypress application note System Design Guidelines at http www cypress com Cypress Semiconductor Corporation e 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 001 13194 Rev A Revised March 26 2007 Feedback 2 CYPRESS PERFORM Pin Configuration P 32 Pin SOIC TSOP II Pinout Top View CY62138F MoBL Product Portfolio Power Dissipation Vcc Range V Operating Icc mA Product Speed Standby lsgz uA f 1MHz f fmax Min Typ 3 Max Typ 3 Max Typ 3 Max Typ 3 Max CY62138FLL 4 5V 5 0V 5 5V 45 1 6 2 5 13 18 1 5 typy TA 25 C Page 2 of 10 Notes 2 NC pins are not connected on the die 3 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vcc Document 001 13194 Rev A Feedback CYPRESS PER
8. Parameter Description Conditions Min Typ I3 Max Unit VDR Vcc for Data Retention 2 0 V lcg t Data Retention Current Vec Von CE4 gt Voc 0 2V or CE lt 0 2V 1 5 uA ViN gt Vec 0 2V or ViN lt 0 2V tcpr 8 Chip Deselect to Data 0 ns Retention Time tr DI Operation Recovery Time tre ns Data Retention Waveform 10 DATA RETENTION MODE VDR 2 0V tR Notes 9 Full device AC operation requires linear Vcc ramp from Vpr to Vcc min 2 100 us or stable at Vcc min 2 100 us 10 CE is the logical combination of CE and CE When CE is LOW and CE is HIGH CE is LOW when CE is HIGH or CE3 is LOW CE is HIGH Document 001 13194 Rev A Page 4 of 10 Feedback CYPRESS PERFORM Switching Characteristics Over the Operating Range 11 CY62138F MoBL 45 ns Parameter Description Unit Min Max Read Cycle tre Read Cycle Time 45 ns taa Address to Data Valid 45 ns TOHA Data Hold from Address Change 10 ns tACE CE4 LOW and CE HIGH to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to Low Z 12 5 ns tuzoE OE HIGH to High Z 12 13 18 ns tice CE LOW and CE HIGH to Low Z 12 10 ns tuzcE CE HIGH or CE LOW to High z 2 131 18 ns tpu CE4 LOW and CE HIGH to power up 0 ns tpp CE HIGH or CE LOW to power down 45 ns Write Cycle 14 twc Write Cycle Time 45 ns tsce CE LOW and CE HIGH to Write End 35 ns
9. ctor All product and company names mentioned in this document may be the trademarks of their respective holders Document 001 13194 Rev A Page 9 of 10 Cypress Semiconductor Corporation 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS N lt e a MEAM 94 I Q w gt gt SS a PERFORM Document History Page CY62138F MoBL Document Title CY62138F MoBL 2 Mbit 256K x 8 Static RAM Document Number 001 13194 Orig of Description of Change REV ECN NO Issue Date See ECN Change VKN New Data Shee
10. t 797956 VKN Added footnote 7 related to Isg and Iccpr A 940341 See ECN Document 001 13194 Rev A Page 10 of 10 Feedback
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